target/linux/mediatek/patches/0023-thermal-Add-Mediatek-thermal-controller-support.patch

   1 From 014330a304100782a26bc7df02778c8c386b2857 Mon Sep 17 00:00:00 2001
   2 From: Sascha Hauer <s.hauer@pengutronix.de>
   3 Date: Wed, 13 May 2015 10:52:42 +0200
   4 Subject: [PATCH 23/76] thermal: Add Mediatek thermal controller support
   5
   6 This adds support for the Mediatek thermal controller found on MT8173
   7 and likely other SoCs.
   8 The controller is a bit special. It does not have its own ADC, instead
   9 it controls the on-SoC AUXADC via AHB bus accesses. For this reason
  10 we need the physical address of the AUXADC. Also it controls a mux
  11 using AHB bus accesses, so we need the APMIXEDSYS physical address aswell.
  12
  13 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
  14 ---
  15  drivers/thermal/Kconfig       |    8 +
  16  drivers/thermal/Makefile      |    1 +
  17  drivers/thermal/mtk_thermal.c |  728 +++++++++++++++++++++++++++++++++++++++++
  18  3 files changed, 737 insertions(+)
  19  create mode 100644 drivers/thermal/mtk_thermal.c
  20
  21 --- a/drivers/thermal/Kconfig
  22 +++ b/drivers/thermal/Kconfig
  23 @@ -285,6 +285,14 @@ config ACPI_THERMAL_REL
  24         tristate
  25         depends on ACPI
  26
  27 +config MTK_THERMAL
  28 +       tristate "Temperature sensor driver for mediatek SoCs"
  29 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  30 +       default y
  31 +       help
  32 +         Enable this option if you want to have support for thermal management
  33 +         controller present in Mediatek SoCs
  34 +
  35  menu "Texas Instruments thermal drivers"
  36  source "drivers/thermal/ti-soc-thermal/Kconfig"
  37  endmenu
  38 --- a/drivers/thermal/Makefile
  39 +++ b/drivers/thermal/Makefile
  40 @@ -39,3 +39,4 @@ obj-$(CONFIG_TI_SOC_THERMAL)  += ti-soc-t
  41  obj-$(CONFIG_INT340X_THERMAL)  += int340x_thermal/
  42  obj-$(CONFIG_ST_THERMAL)       += st/
  43  obj-$(CONFIG_TEGRA_SOCTHERM)   += tegra_soctherm.o
  44 +obj-$(CONFIG_MTK_THERMAL)      += mtk_thermal.o
  45 --- /dev/null
  46 +++ b/drivers/thermal/mtk_thermal.c
  47 @@ -0,0 +1,728 @@
  48 +/*
  49 + * Copyright (c) 2014 MediaTek Inc.
  50 + * Author: Hanyi.Wu <hanyi.wu@mediatek.com>
  51 + *
  52 + * This program is free software; you can redistribute it and/or modify
  53 + * it under the terms of the GNU General Public License version 2 as
  54 + * published by the Free Software Foundation.
  55 + *
  56 + * This program is distributed in the hope that it will be useful,
  57 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  58 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  59 + * GNU General Public License for more details.
  60 + */
  61 +
  62 +#include <linux/kernel.h>
  63 +#include <linux/module.h>
  64 +#include <linux/dmi.h>
  65 +#include <linux/thermal.h>
  66 +#include <linux/platform_device.h>
  67 +#include <linux/types.h>
  68 +#include <linux/delay.h>
  69 +#include <linux/slab.h>
  70 +#include <linux/clk.h>
  71 +#include <linux/time.h>
  72 +#include <linux/of.h>
  73 +#include <linux/of_irq.h>
  74 +#include <linux/of_address.h>
  75 +#include <linux/interrupt.h>
  76 +#include <linux/reset.h>
  77 +
  78 +/* AUXADC Registers */
  79 +#define AUXADC_CON0_V          0x000
  80 +#define AUXADC_CON1_V          0x004
  81 +#define AUXADC_CON1_SET_V      0x008
  82 +#define AUXADC_CON1_CLR_V      0x00c
  83 +#define AUXADC_CON2_V          0x010
  84 +#define AUXADC_DATA(channel)   (0x14 + (channel) * 4)
  85 +#define AUXADC_MISC_V          0x094
  86 +
  87 +#define AUXADC_CON1_CHANNEL(x) (1 << (x))
  88 +
  89 +/* Thermal Controller Registers */
  90 +#define TEMPMONCTL0            0x000
  91 +#define TEMPMONCTL1            0x004
  92 +#define TEMPMONCTL2            0x008
  93 +#define TEMPMONINT             0x00c
  94 +#define TEMPMONINTSTS          0x010
  95 +#define TEMPMONIDET0           0x014
  96 +#define TEMPMONIDET1           0x018
  97 +#define TEMPMONIDET2           0x01c
  98 +#define TEMPH2NTHRE            0x024
  99 +#define TEMPHTHRE              0x028
 100 +#define TEMPCTHRE              0x02c
 101 +#define TEMPOFFSETH            0x030
 102 +#define TEMPOFFSETL            0x034
 103 +#define TEMPMSRCTL0            0x038
 104 +#define TEMPMSRCTL1            0x03c
 105 +#define TEMPAHBPOLL            0x040
 106 +#define TEMPAHBTO              0x044
 107 +#define TEMPADCPNP0            0x048
 108 +#define TEMPADCPNP1            0x04c
 109 +#define TEMPADCPNP2            0x050
 110 +#define TEMPADCPNP3            0x0b4
 111 +
 112 +#define TEMPADCMUX             0x054
 113 +#define TEMPADCEXT             0x058
 114 +#define TEMPADCEXT1            0x05c
 115 +#define TEMPADCEN              0x060
 116 +#define TEMPPNPMUXADDR         0x064
 117 +#define TEMPADCMUXADDR         0x068
 118 +#define TEMPADCEXTADDR         0x06c
 119 +#define TEMPADCEXT1ADDR                0x070
 120 +#define TEMPADCENADDR          0x074
 121 +#define TEMPADCVALIDADDR       0x078
 122 +#define TEMPADCVOLTADDR                0x07c
 123 +#define TEMPRDCTRL             0x080
 124 +#define TEMPADCVALIDMASK       0x084
 125 +#define TEMPADCVOLTAGESHIFT    0x088
 126 +#define TEMPADCWRITECTRL       0x08c
 127 +#define TEMPMSR0               0x090
 128 +#define TEMPMSR1               0x094
 129 +#define TEMPMSR2               0x098
 130 +#define TEMPMSR3               0x0B8
 131 +
 132 +#define TEMPIMMD0              0x0a0
 133 +#define TEMPIMMD1              0x0a4
 134 +#define TEMPIMMD2              0x0a8
 135 +
 136 +#define TEMPPROTCTL            0x0c0
 137 +#define TEMPPROTTA             0x0c4
 138 +#define TEMPPROTTB             0x0c8
 139 +#define TEMPPROTTC             0x0cc
 140 +
 141 +#define TEMPSPARE0             0x0f0
 142 +#define TEMPSPARE1             0x0f4
 143 +#define TEMPSPARE2             0x0f8
 144 +#define TEMPSPARE3             0x0fc
 145 +
 146 +#define PTPCORESEL             0x400
 147 +#define THERMINTST             0x404
 148 +#define PTPODINTST             0x408
 149 +#define THSTAGE0ST             0x40c
 150 +#define THSTAGE1ST             0x410
 151 +#define THSTAGE2ST             0x414
 152 +#define THAHBST0               0x418
 153 +#define THAHBST1               0x41c   /* Only for DE debug */
 154 +#define PTPSPARE0              0x420
 155 +#define PTPSPARE1              0x424
 156 +#define PTPSPARE2              0x428
 157 +#define PTPSPARE3              0x42c
 158 +#define THSLPEVEB              0x430
 159 +
 160 +#define TEMPMONINT_COLD(sp)                    ((1 << 0) << ((sp) * 5))
 161 +#define TEMPMONINT_HOT(sp)                     ((1 << 1) << ((sp) * 5))
 162 +#define TEMPMONINT_LOW_OFS(sp)                 ((1 << 2) << ((sp) * 5))
 163 +#define TEMPMONINT_HIGH_OFS(sp)                        ((1 << 3) << ((sp) * 5))
 164 +#define TEMPMONINT_HOT_TO_NORM(sp)             ((1 << 4) << ((sp) * 5))
 165 +#define TEMPMONINT_TIMEOUT                     (1 << 15)
 166 +#define TEMPMONINT_IMMEDIATE_SENSE(sp)         (1 << (16 + (sp)))
 167 +#define TEMPMONINT_FILTER_SENSE(sp)            (1 << (19 + (sp)))
 168 +
 169 +#define TEMPADCWRITECTRL_ADC_PNP_WRITE         (1 << 0)
 170 +#define TEMPADCWRITECTRL_ADC_MUX_WRITE         (1 << 1)
 171 +#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE       (1 << 2)
 172 +#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE      (1 << 3)
 173 +
 174 +#define TEMPADCVALIDMASK_VALID_HIGH            (1 << 5)
 175 +#define TEMPADCVALIDMASK_VALID_POS(bit)                (bit)
 176 +
 177 +#define TEMPPROTCTL_AVERAGE                    (0 << 16)
 178 +#define TEMPPROTCTL_MAXIMUM                    (1 << 16)
 179 +#define TEMPPROTCTL_SELECTED                   (2 << 16)
 180 +
 181 +#define MT8173_THERMAL_ZONE_CA57               0
 182 +#define MT8173_THERMAL_ZONE_CA53               1
 183 +#define MT8173_THERMAL_ZONE_GPU                        2
 184 +#define MT8173_THERMAL_ZONE_CORE               3
 185 +
 186 +#define MT8173_TS1     0
 187 +#define MT8173_TS2     1
 188 +#define MT8173_TS3     2
 189 +#define MT8173_TS4     3
 190 +#define MT8173_TSABB   4
 191 +
 192 +/* AUXADC channel 11 is used for the temperature sensors */
 193 +#define MT8173_TEMP_AUXADC_CHANNEL     11
 194 +
 195 +/* The total number of temperature sensors in the MT8173 */
 196 +#define MT8173_NUM_SENSORS             5
 197 +
 198 +/* The number of banks in the MT8173 */
 199 +#define MT8173_NUM_BANKS               4
 200 +
 201 +/* The number of sensing points per bank */
 202 +#define MT8173_NUM_SENSING_POINTS      4
 203 +
 204 +#define THERMAL_NAME    "mtk-thermal"
 205 +
 206 +struct mtk_thermal;
 207 +
 208 +struct mtk_thermal_bank {
 209 +       struct mtk_thermal *mt;
 210 +       struct thermal_zone_device *tz;
 211 +       int id;
 212 +};
 213 +
 214 +struct mtk_thermal {
 215 +       struct device *dev;
 216 +       void __iomem *thermal_base;
 217 +       void __iomem *auxadc_base;
 218 +
 219 +       u64 auxadc_phys_base;
 220 +       u64 apmixed_phys_base;
 221 +       struct reset_control *reset;
 222 +       struct clk *clk_peri_therm;
 223 +       struct clk *clk_auxadc;
 224 +
 225 +       struct mtk_thermal_bank banks[MT8173_NUM_BANKS];
 226 +
 227 +       struct mutex lock;
 228 +
 229 +       /* Calibration values */
 230 +       s32 adc_ge;
 231 +       s32 adc_oe;
 232 +       s32 degc_cali;
 233 +       s32 o_slope;
 234 +       s32 vts;
 235 +};
 236 +
 237 +struct mtk_thermal_bank_cfg {
 238 +       unsigned int enable_mask;
 239 +       unsigned int sensors[4];
 240 +};
 241 +
 242 +static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
 243 +
 244 +/*
 245 + * The MT8173 thermal controller has four banks. Each bank can read up to
 246 + * four temperature sensors simultaneously. The MT8173 has a total of 5
 247 + * temperature sensors. We use each bank to measure a certain area of the
 248 + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
 249 + * areas, hence is used in different banks.
 250 + */
 251 +static struct mtk_thermal_bank_cfg bank_data[] = {
 252 +       {
 253 +               .enable_mask = 3,
 254 +               .sensors = { MT8173_TS2, MT8173_TS3 },
 255 +       }, {
 256 +               .enable_mask = 3,
 257 +               .sensors = { MT8173_TS2, MT8173_TS4 },
 258 +       }, {
 259 +               .enable_mask = 7,
 260 +               .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
 261 +       }, {
 262 +               .enable_mask = 1,
 263 +               .sensors = { MT8173_TS2 },
 264 +       },
 265 +};
 266 +
 267 +static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = {
 268 +       TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3
 269 +};
 270 +
 271 +static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = {
 272 +       TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3
 273 +};
 274 +
 275 +/**
 276 + * raw_to_mcelsius - convert a raw ADC value to mcelsius
 277 + * @mt:                The thermal controller
 278 + * @raw:       raw ADC value
 279 + *
 280 + * This converts the raw ADC value to mcelsius using the SoC specific
 281 + * calibration constants
 282 + */
 283 +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw)
 284 +{
 285 +       s32 format_1, format_2, format_3, format_4;
 286 +       s32 xtoomt;
 287 +       s32 gain;
 288 +
 289 +       raw &= 0xfff;
 290 +
 291 +       gain = (10000 + mt->adc_ge);
 292 +
 293 +       xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) /
 294 +               gain;
 295 +
 296 +       format_1 = ((mt->degc_cali * 10) >> 1);
 297 +       format_2 = (raw - mt->adc_oe);
 298 +       format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt;
 299 +       format_3 = format_3 * 15 / 18;
 300 +       format_4 = ((format_3 * 100) / (165 + mt->o_slope));
 301 +       format_4 = format_4 - (format_4 << 1);
 302 +
 303 +       return (format_1 + format_4) * 100;
 304 +}
 305 +
 306 +/**
 307 + * mcelsius_to_raw - convert mcelsius to raw ADC value
 308 + * @mt:                The thermal controller
 309 + * @temp:      The temperature in mcelsius
 310 + *
 311 + * This converts a temperature in mcelsius to a raw ADC value, needed to
 312 + * calculate the trigger values for interrupt generation.
 313 + */
 314 +static u32 mcelsius_to_raw(struct mtk_thermal *mt, int temp)
 315 +{
 316 +       s32 format_1, format_2, format_3, format_4;
 317 +       s32 xtoomt;
 318 +       s32 gain;
 319 +
 320 +       gain = (10000 + mt->adc_ge);
 321 +
 322 +       xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) /
 323 +               gain;
 324 +
 325 +       format_1 = temp - (mt->degc_cali * 1000 / 2);
 326 +       format_2 = format_1 * (165 + mt->o_slope) * 18 / 15;
 327 +       format_2 = format_2 - 2 * format_2;
 328 +       format_3 = format_2 / 1000 + xtoomt * 10;
 329 +       format_4 = (format_3 * 4096 / 10000 * gain) / 100000 + mt->adc_oe;
 330 +
 331 +       return format_4;
 332 +}
 333 +
 334 +/**
 335 + * mtk_thermal_get_bank - get bank
 336 + * @bank:      The bank
 337 + *
 338 + * The bank registers are banked, we have to select a bank in the
 339 + * PTPCORESEL register to access it.
 340 + */
 341 +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
 342 +{
 343 +       struct mtk_thermal *mt = bank->mt;
 344 +       u32 val;
 345 +
 346 +       mutex_lock(&mt->lock);
 347 +
 348 +       val = readl(mt->thermal_base + PTPCORESEL);
 349 +       val &= ~0xf;
 350 +       val |= bank->id;
 351 +       writel(val, mt->thermal_base + PTPCORESEL);
 352 +}
 353 +
 354 +/**
 355 + * mtk_thermal_put_bank - release bank
 356 + * @bank:      The bank
 357 + *
 358 + * release a bank previously taken with mtk_thermal_get_bank,
 359 + */
 360 +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
 361 +{
 362 +       struct mtk_thermal *mt = bank->mt;
 363 +
 364 +       mutex_unlock(&mt->lock);
 365 +}
 366 +
 367 +/**
 368 + * mtk_thermal_bank_temperature - get the temperature of a bank
 369 + * @bank:      The bank
 370 + *
 371 + * The temperature of a bank is considered the maximum temperature of
 372 + * the sensors associated to the bank.
 373 + */
 374 +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
 375 +{
 376 +       struct mtk_thermal *mt = bank->mt;
 377 +       int temp, i, max;
 378 +       u32 raw;
 379 +
 380 +       temp = max = -INT_MAX;
 381 +
 382 +       for (i = 0; i < 4; i++) {
 383 +               int sensno;
 384 +
 385 +               if (!(bank_data[bank->id].enable_mask & (1 << i)))
 386 +                       continue;
 387 +
 388 +               raw = readl(mt->thermal_base + tempmsr_ofs[i]);
 389 +
 390 +               sensno = bank_data[bank->id].sensors[i];
 391 +               temp = raw_to_mcelsius(mt, raw);
 392 +
 393 +               if (temp > max)
 394 +                       max = temp;
 395 +       }
 396 +
 397 +       return max;
 398 +}
 399 +
 400 +static void mtk_thermal_irq_bank(struct mtk_thermal_bank *bank)
 401 +{
 402 +       struct mtk_thermal *mt = bank->mt;
 403 +       int sp;
 404 +       u32 irqstat;
 405 +       bool update = false;
 406 +
 407 +       mtk_thermal_get_bank(bank);
 408 +
 409 +       irqstat = readl(mt->thermal_base + TEMPMONINTSTS);
 410 +
 411 +       mtk_thermal_put_bank(bank);
 412 +
 413 +       for (sp = 0; sp < 3; sp++) {
 414 +               if (irqstat & TEMPMONINT_LOW_OFS(sp)) {
 415 +                       update = true;
 416 +                       dev_vdbg(mt->dev, "bank %d sensor %d low offset interrupt\n",
 417 +                                       bank->id, sp);
 418 +               }
 419 +
 420 +               if (irqstat & TEMPMONINT_HIGH_OFS(sp)) {
 421 +                       update = true;
 422 +                       dev_vdbg(mt->dev, "bank %d sensor %d high offset interrupt\n",
 423 +                                       bank->id, sp);
 424 +               }
 425 +       }
 426 +
 427 +       if (update)
 428 +               thermal_zone_device_update(bank->tz);
 429 +}
 430 +
 431 +static irqreturn_t mtk_thermal_irq(int irq, void *dev_id)
 432 +{
 433 +       struct mtk_thermal *mt = dev_id;
 434 +       u32 irqstat = 0;
 435 +       int i;
 436 +
 437 +       irqstat = readl(mt->thermal_base + THERMINTST);
 438 +
 439 +       dev_vdbg(mt->dev, "thermal_interrupt_handler : THERMINTST = 0x%x\n",
 440 +                       irqstat);
 441 +
 442 +       for (i = 0; i < MT8173_NUM_BANKS; i++) {
 443 +               if (!(irqstat & (1 << i)))
 444 +                       mtk_thermal_irq_bank(&mt->banks[i]);
 445 +       }
 446 +
 447 +       return IRQ_HANDLED;
 448 +}
 449 +
 450 +static int mtk_read_temp(void *data, int *temp)
 451 +{
 452 +       struct mtk_thermal_bank *bank = data;
 453 +
 454 +       mtk_thermal_get_bank(bank);
 455 +
 456 +       *temp = mtk_thermal_bank_temperature(bank);
 457 +
 458 +       mtk_thermal_put_bank(bank);
 459 +
 460 +       return 0;
 461 +}
 462 +
 463 +static int mtk_set_trips(void *data, int low, int high)
 464 +{
 465 +       struct mtk_thermal_bank *bank = data;
 466 +       struct mtk_thermal *mt = bank->mt;
 467 +       int i;
 468 +       u32 val, enable_mask;
 469 +       u32 raw_low, raw_high;
 470 +
 471 +       raw_low = mcelsius_to_raw(mt, low);
 472 +       raw_high = mcelsius_to_raw(mt, high);
 473 +
 474 +       mtk_thermal_get_bank(bank);
 475 +
 476 +       writel(0x0, mt->thermal_base + TEMPMONINT);
 477 +
 478 +       writel(TEMPPROTCTL_SELECTED, mt->thermal_base + TEMPPROTCTL);
 479 +
 480 +       writel(raw_low, mt->thermal_base + TEMPOFFSETL);
 481 +       writel(raw_high, mt->thermal_base + TEMPOFFSETH);
 482 +
 483 +       enable_mask = readl(mt->thermal_base + TEMPMONCTL0);
 484 +
 485 +       val = 0;
 486 +       for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++)
 487 +               if (enable_mask & (1 << i))
 488 +                       val |=  TEMPMONINT_LOW_OFS(i) | TEMPMONINT_HIGH_OFS(i);
 489 +
 490 +       writel(val, mt->thermal_base + TEMPMONINT);
 491 +
 492 +       mtk_thermal_put_bank(bank);
 493 +
 494 +       dev_dbg(mt->dev, "new boundaries: %d (0x%04x) < x < %d (0x%04x)\n",
 495 +                       low, mcelsius_to_raw(mt, low),
 496 +                       high, mcelsius_to_raw(mt, high));
 497 +
 498 +       return 0;
 499 +}
 500 +
 501 +static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
 502 +       .get_temp = mtk_read_temp,
 503 +       .set_trips = mtk_set_trips,
 504 +};
 505 +
 506 +static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank)
 507 +{
 508 +       struct mtk_thermal *mt = bank->mt;
 509 +       struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id];
 510 +       int i;
 511 +
 512 +       mtk_thermal_get_bank(bank);
 513 +
 514 +       /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
 515 +       writel(0x0000000c, mt->thermal_base + TEMPMONCTL1);
 516 +
 517 +       /*
 518 +        * filt interval is 1 * 46.540us = 46.54us,
 519 +        * sen interval is 429 * 46.540us = 19.96ms
 520 +        */
 521 +       writel(0x000101ad, mt->thermal_base + TEMPMONCTL2);
 522 +
 523 +       /* poll is set to 10u */
 524 +       writel(0x00000300, mt->thermal_base + TEMPAHBPOLL);
 525 +
 526 +       /* temperature sampling control, 1 sample */
 527 +       writel(0x00000000, mt->thermal_base + TEMPMSRCTL0);
 528 +
 529 +       /* exceed this polling time, IRQ would be inserted */
 530 +       writel(0xffffffff, mt->thermal_base + TEMPAHBTO);
 531 +
 532 +       /* number of interrupts per event, 1 is enough */
 533 +       writel(0x0, mt->thermal_base + TEMPMONIDET0);
 534 +       writel(0x0, mt->thermal_base + TEMPMONIDET1);
 535 +
 536 +       /*
 537 +        * The MT8173 thermal controller does not have its own ADC. Instead it
 538 +        * uses AHB bus accesses to control the AUXADC. To do this the thermal
 539 +        * controller has to be programmed with the physical addresses of the
 540 +        * AUXADC registers and with the various bit positions in the AUXADC.
 541 +        * Also the thermal controller controls a mux in the APMIXEDSYS register
 542 +        * space.
 543 +        */
 544 +
 545 +       /*
 546 +        * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0)
 547 +        * automatically by hw
 548 +        */
 549 +       writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX);
 550 +
 551 +       /* AHB address for auxadc mux selection */
 552 +       writel(mt->auxadc_phys_base + 0x00c,
 553 +                       mt->thermal_base + TEMPADCMUXADDR);
 554 +
 555 +       /* AHB address for pnp sensor mux selection */
 556 +       writel(mt->apmixed_phys_base + 0x0604,
 557 +                       mt->thermal_base + TEMPPNPMUXADDR);
 558 +
 559 +       /* AHB value for auxadc enable */
 560 +       writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN);
 561 +
 562 +       /* AHB address for auxadc enable (channel 0 immediate mode selected) */
 563 +       writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V,
 564 +                       mt->thermal_base + TEMPADCENADDR);
 565 +
 566 +       /* AHB address for auxadc valid bit */
 567 +       writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
 568 +                       mt->thermal_base + TEMPADCVALIDADDR);
 569 +
 570 +       /* AHB address for auxadc voltage output */
 571 +       writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
 572 +                       mt->thermal_base + TEMPADCVOLTADDR);
 573 +
 574 +       /* read valid & voltage are at the same register */
 575 +       writel(0x0, mt->thermal_base + TEMPRDCTRL);
 576 +
 577 +       /* indicate where the valid bit is */
 578 +       writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12),
 579 +                       mt->thermal_base + TEMPADCVALIDMASK);
 580 +
 581 +       /* no shift */
 582 +       writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT);
 583 +
 584 +       /* enable auxadc mux write transaction */
 585 +       writel(TEMPADCWRITECTRL_ADC_MUX_WRITE,
 586 +                       mt->thermal_base + TEMPADCWRITECTRL);
 587 +
 588 +       for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++)
 589 +               writel(sensor_mux_values[cfg->sensors[i]],
 590 +                               mt->thermal_base + tempadcpnp_ofs[i]);
 591 +
 592 +       writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0);
 593 +
 594 +       writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE,
 595 +                       mt->thermal_base + TEMPADCWRITECTRL);
 596 +
 597 +       mtk_thermal_put_bank(bank);
 598 +}
 599 +
 600 +static u64 of_get_phys_base(struct device_node *np)
 601 +{
 602 +       u64 size64;
 603 +       const __be32 *regaddr_p;
 604 +
 605 +       regaddr_p = of_get_address(np, 0, &size64, NULL);
 606 +       if (!regaddr_p)
 607 +               return OF_BAD_ADDR;
 608 +
 609 +       return of_translate_address(np, regaddr_p);
 610 +}
 611 +
 612 +static int mtk_thermal_probe(struct platform_device *pdev)
 613 +{
 614 +       int ret, i;
 615 +       struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
 616 +       int irq;
 617 +       struct mtk_thermal *mt;
 618 +       struct resource *res;
 619 +
 620 +       mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
 621 +       if (!mt)
 622 +               return -ENOMEM;
 623 +
 624 +       mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
 625 +       if (IS_ERR(mt->clk_peri_therm))
 626 +               return PTR_ERR(mt->clk_peri_therm);
 627 +
 628 +       mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
 629 +       if (IS_ERR(mt->clk_auxadc))
 630 +               return PTR_ERR(mt->clk_auxadc);
 631 +
 632 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 633 +       mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
 634 +       if (IS_ERR(mt->thermal_base))
 635 +               return PTR_ERR(mt->thermal_base);
 636 +
 637 +       mt->reset = devm_reset_control_get(&pdev->dev, "therm");
 638 +       if (IS_ERR(mt->reset)) {
 639 +               ret = PTR_ERR(mt->reset);
 640 +               dev_err(&pdev->dev, "cannot get reset: %d\n", ret);
 641 +               return ret;
 642 +       }
 643 +
 644 +       mutex_init(&mt->lock);
 645 +
 646 +       mt->dev = &pdev->dev;
 647 +
 648 +       auxadc = of_parse_phandle(np, "auxadc", 0);
 649 +       if (!auxadc) {
 650 +               dev_err(&pdev->dev, "missing auxadc node\n");
 651 +               return -ENODEV;
 652 +       }
 653 +
 654 +       mt->auxadc_phys_base = of_get_phys_base(auxadc);
 655 +       if (mt->auxadc_phys_base == OF_BAD_ADDR) {
 656 +               dev_err(&pdev->dev, "Can't get auxadc phys address\n");
 657 +               return -EINVAL;
 658 +       }
 659 +
 660 +       apmixedsys = of_parse_phandle(np, "apmixedsys", 0);
 661 +       if (!apmixedsys) {
 662 +               dev_err(&pdev->dev, "missing apmixedsys node\n");
 663 +               return -ENODEV;
 664 +       }
 665 +
 666 +       mt->apmixed_phys_base = of_get_phys_base(apmixedsys);
 667 +       if (mt->apmixed_phys_base == OF_BAD_ADDR) {
 668 +               dev_err(&pdev->dev, "Can't get auxadc phys address\n");
 669 +               return -EINVAL;
 670 +       }
 671 +
 672 +       irq = platform_get_irq(pdev, 0);
 673 +       if (!irq) {
 674 +               dev_err(&pdev->dev, "Can't find irq\n");
 675 +               return -EINVAL;
 676 +       }
 677 +
 678 +       ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, mtk_thermal_irq,
 679 +                       IRQF_ONESHOT, THERMAL_NAME, mt);
 680 +       if (ret) {
 681 +               dev_err(&pdev->dev, "Can't request irq %d: %d\n", irq, ret);
 682 +               return ret;
 683 +       }
 684 +
 685 +       ret = clk_prepare_enable(mt->clk_auxadc);
 686 +       if (ret) {
 687 +               dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
 688 +               return ret;
 689 +       }
 690 +
 691 +       reset_control_reset(mt->reset);
 692 +
 693 +       ret = clk_prepare_enable(mt->clk_peri_therm);
 694 +       if (ret) {
 695 +               dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
 696 +               goto err_enable_clk;
 697 +       }
 698 +
 699 +       /*
 700 +        * These calibration values should finally be provided by the
 701 +        * firmware or fuses. For now use default values.
 702 +        */
 703 +       mt->adc_ge = ((512 - 512) * 10000) / 4096;
 704 +       mt->adc_oe = 512 - 512;
 705 +       mt->degc_cali = 40;
 706 +       mt->o_slope = 0;
 707 +       mt->vts = 260;
 708 +
 709 +       for (i = 0; i < MT8173_NUM_BANKS; i++) {
 710 +               struct mtk_thermal_bank *bank = &mt->banks[i];
 711 +
 712 +               bank->id = i;
 713 +               bank->mt = mt;
 714 +               mtk_thermal_init_bank(&mt->banks[i]);
 715 +       }
 716 +
 717 +       platform_set_drvdata(pdev, mt);
 718 +
 719 +       /*
 720 +        * This is needed after initialising the banks because otherwise
 721 +        * the first temperature read contains bogus high temperatures which
 722 +        * immediately cause a system shutdown.
 723 +        */
 724 +       msleep(100);
 725 +
 726 +       for (i = 0; i < MT8173_NUM_BANKS; i++) {
 727 +               struct mtk_thermal_bank *bank = &mt->banks[i];
 728 +
 729 +               bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank,
 730 +                               &mtk_thermal_ops);
 731 +       }
 732 +
 733 +       return 0;
 734 +
 735 +err_enable_clk:
 736 +       clk_disable_unprepare(mt->clk_peri_therm);
 737 +
 738 +       return ret;
 739 +}
 740 +
 741 +static int mtk_thermal_remove(struct platform_device *pdev)
 742 +{
 743 +       struct mtk_thermal *mt = platform_get_drvdata(pdev);
 744 +       int i;
 745 +
 746 +       for (i = 0; i < MT8173_NUM_BANKS; i++) {
 747 +               struct mtk_thermal_bank *bank = &mt->banks[i];
 748 +
 749 +               if (!IS_ERR(bank))
 750 +                       thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz);
 751 +       }
 752 +
 753 +       clk_disable_unprepare(mt->clk_peri_therm);
 754 +       clk_disable_unprepare(mt->clk_auxadc);
 755 +
 756 +       return 0;
 757 +}
 758 +
 759 +static const struct of_device_id mtk_thermal_of_match[] = {
 760 +       {
 761 +               .compatible = "mediatek,mt8173-thermal",
 762 +       }, {
 763 +       },
 764 +};
 765 +
 766 +static struct platform_driver mtk_thermal_driver = {
 767 +       .probe = mtk_thermal_probe,
 768 +       .remove = mtk_thermal_remove,
 769 +       .driver = {
 770 +               .name = THERMAL_NAME,
 771 +               .of_match_table = mtk_thermal_of_match,
 772 +       },
 773 +};
 774 +
 775 +module_platform_driver(mtk_thermal_driver);