target/linux/mvebu/patches-3.10/0008-clk-mvebu-add-more-PCIe-clocks-for-Armada-XP.patch

   1 From 5006da299ae65cadf92932f2f7b062b5a8c65798 Mon Sep 17 00:00:00 2001
   2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   3 Date: Fri, 18 Jan 2013 16:42:01 +0100
   4 Subject: [PATCH 008/203] clk: mvebu: add more PCIe clocks for Armada XP
   5
   6 The current revision of the datasheet only mentions the gatable clocks
   7 for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention
   8 the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0
   9 interfaces. After confirmation with Marvell engineers, this patch adds
  10 the missing gatable clocks for those PCIe interfaces.
  11
  12 It also changes the name of the previously existing PCIe gatable
  13 clocks, in order to match the naming using the datasheets.
  14
  15 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  16 Cc: Mike Turquette <mturquette@linaro.org>
  17 ---
  18  drivers/clk/mvebu/clk-gating-ctrl.c | 14 ++++++++++----
  19  1 file changed, 10 insertions(+), 4 deletions(-)
  20
  21 --- a/drivers/clk/mvebu/clk-gating-ctrl.c
  22 +++ b/drivers/clk/mvebu/clk-gating-ctrl.c
  23 @@ -137,10 +137,14 @@ static const struct mvebu_soc_descr __in
  24         { "ge2", NULL,  2 },
  25         { "ge1", NULL, 3 },
  26         { "ge0", NULL, 4 },
  27 -       { "pex0", NULL, 5 },
  28 -       { "pex1", NULL, 6 },
  29 -       { "pex2", NULL, 7 },
  30 -       { "pex3", NULL, 8 },
  31 +       { "pex00", NULL, 5 },
  32 +       { "pex01", NULL, 6 },
  33 +       { "pex02", NULL, 7 },
  34 +       { "pex03", NULL, 8 },
  35 +       { "pex10", NULL, 9 },
  36 +       { "pex11", NULL, 10 },
  37 +       { "pex12", NULL, 11 },
  38 +       { "pex13", NULL, 12 },
  39         { "bp", NULL, 13 },
  40         { "sata0lnk", NULL, 14 },
  41         { "sata0", "sata0lnk", 15 },
  42 @@ -152,6 +156,8 @@ static const struct mvebu_soc_descr __in
  43         { "xor0", NULL, 22 },
  44         { "crypto", NULL, 23 },
  45         { "tdm", NULL, 25 },
  46 +       { "pex20", NULL, 26 },
  47 +       { "pex30", NULL, 27 },
  48         { "xor1", NULL, 28 },
  49         { "sata1lnk", NULL, 29 },
  50         { "sata1", "sata1lnk", 30 },