target/linux/octeon/patches-3.10/0011-MIPS-Octeon-Add-twsi-interrupt-initialization-for-OC.patch

   1 From a53825ef4e9b2f42a21ad2b903f4d0ce691a5d63 Mon Sep 17 00:00:00 2001
   2 From: Eunbong Song <eunb.song@samsung.com>
   3 Date: Tue, 22 Apr 2014 06:16:15 +0000
   4 Subject: [PATCH] MIPS: Octeon: Add twsi interrupt initialization for OCTEON
   5  3XXX, 5XXX, 63XX
   6
   7 In octeon_3xxx.dts file, there is a definiton for twsi/twsi2 interrupts.
   8 But there is no code for initialization of this interrupts. This patch adds
   9 code for initialization of twsi interrupts.
  10
  11 Signed-off-by: Eunbong Song <eunb.song@samsung.com>
  12 Cc: linux-kernel@vger.kernel.org
  13 Cc: linux-mips@linux-mips.org
  14 Patchwork: https://patchwork.linux-mips.org/patch/6816/
  15 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  16 ---
  17  arch/mips/cavium-octeon/octeon-irq.c           | 2 ++
  18  arch/mips/include/asm/mach-cavium-octeon/irq.h | 2 ++
  19  2 files changed, 4 insertions(+)
  20
  21 --- a/arch/mips/cavium-octeon/octeon-irq.c
  22 +++ b/arch/mips/cavium-octeon/octeon-irq.c
  23 @@ -1260,11 +1260,13 @@ static void __init octeon_irq_init_ciu(v
  24         for (i = 0; i < 4; i++)
  25                 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40);
  26
  27 +       octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI, 0, 45);
  28         octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46);
  29         for (i = 0; i < 4; i++)
  30                 octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
  31
  32         octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
  33 +       octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_TWSI2, 0, 59);
  34
  35         /* CIU_1 */
  36         for (i = 0; i < 16; i++)
  37 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
  38 +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
  39 @@ -35,6 +35,8 @@ enum octeon_irq {
  40         OCTEON_IRQ_PCI_MSI2,
  41         OCTEON_IRQ_PCI_MSI3,
  42
  43 +       OCTEON_IRQ_TWSI,
  44 +       OCTEON_IRQ_TWSI2,
  45         OCTEON_IRQ_RML,
  46         OCTEON_IRQ_TIMER0,
  47         OCTEON_IRQ_TIMER1,