target/linux/ramips/files-3.7/drivers/usb/dwc_otg/dwc_otg_regs.h

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
   3  * $Revision: 1.2 $
   4  * $Date: 2008-11-21 05:39:15 $
   5  * $Change: 1099526 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 #ifndef __DWC_OTG_REGS_H__
  35 #define __DWC_OTG_REGS_H__
  36
  37 /**
  38  * @file
  39  *
  40  * This file contains the data structures for accessing the DWC_otg core registers.
  41  *
  42  * The application interfaces with the HS OTG core by reading from and
  43  * writing to the Control and Status Register (CSR) space through the
  44  * AHB Slave interface. These registers are 32 bits wide, and the
  45  * addresses are 32-bit-block aligned.
  46  * CSRs are classified as follows:
  47  * - Core Global Registers
  48  * - Device Mode Registers
  49  * - Device Global Registers
  50  * - Device Endpoint Specific Registers
  51  * - Host Mode Registers
  52  * - Host Global Registers
  53  * - Host Port CSRs
  54  * - Host Channel Specific Registers
  55  *
  56  * Only the Core Global registers can be accessed in both Device and
  57  * Host modes. When the HS OTG core is operating in one mode, either
  58  * Device or Host, the application must not access registers from the
  59  * other mode. When the core switches from one mode to another, the
  60  * registers in the new mode of operation must be reprogrammed as they
  61  * would be after a power-on reset.
  62  */
  63
  64 /** Maximum number of Periodic FIFOs */
  65 #define MAX_PERIO_FIFOS 15
  66 /** Maximum number of Transmit FIFOs */
  67 #define MAX_TX_FIFOS 15
  68
  69 /** Maximum number of Endpoints/HostChannels */
  70 #define MAX_EPS_CHANNELS 16
  71
  72 /****************************************************************************/
  73 /** DWC_otg Core registers .
  74  * The dwc_otg_core_global_regs structure defines the size
  75  * and relative field offsets for the Core Global registers.
  76  */
  77 typedef struct dwc_otg_core_global_regs
  78 {
  79         /** OTG Control and Status Register.  <i>Offset: 000h</i> */
  80         volatile uint32_t gotgctl;
  81         /** OTG Interrupt Register.      <i>Offset: 004h</i> */
  82         volatile uint32_t gotgint;
  83         /**Core AHB Configuration Register.      <i>Offset: 008h</i> */
  84         volatile uint32_t gahbcfg;
  85
  86 #define DWC_GLBINTRMASK         0x0001
  87 #define DWC_DMAENABLE           0x0020
  88 #define DWC_NPTXEMPTYLVL_EMPTY  0x0080
  89 #define DWC_NPTXEMPTYLVL_HALFEMPTY      0x0000
  90 #define DWC_PTXEMPTYLVL_EMPTY   0x0100
  91 #define DWC_PTXEMPTYLVL_HALFEMPTY       0x0000
  92
  93         /**Core USB Configuration Register.      <i>Offset: 00Ch</i> */
  94         volatile uint32_t gusbcfg;
  95         /**Core Reset Register.  <i>Offset: 010h</i> */
  96         volatile uint32_t grstctl;
  97         /**Core Interrupt Register.      <i>Offset: 014h</i> */
  98         volatile uint32_t gintsts;
  99         /**Core Interrupt Mask Register.  <i>Offset: 018h</i> */
 100         volatile uint32_t gintmsk;
 101         /**Receive Status Queue Read Register (Read Only).      <i>Offset: 01Ch</i> */
 102         volatile uint32_t grxstsr;
 103         /**Receive Status Queue Read & POP Register (Read Only).  <i>Offset: 020h</i>*/
 104         volatile uint32_t grxstsp;
 105         /**Receive FIFO Size Register.  <i>Offset: 024h</i> */
 106         volatile uint32_t grxfsiz;
 107         /**Non Periodic Transmit FIFO Size Register.  <i>Offset: 028h</i> */
 108         volatile uint32_t gnptxfsiz;
 109         /**Non Periodic Transmit FIFO/Queue Status Register (Read
 110          * Only). <i>Offset: 02Ch</i> */
 111         volatile uint32_t gnptxsts;
 112         /**I2C Access Register.  <i>Offset: 030h</i> */
 113         volatile uint32_t gi2cctl;
 114         /**PHY Vendor Control Register.  <i>Offset: 034h</i> */
 115         volatile uint32_t gpvndctl;
 116         /**General Purpose Input/Output Register.  <i>Offset: 038h</i> */
 117         volatile uint32_t ggpio;
 118         /**User ID Register.  <i>Offset: 03Ch</i> */
 119         volatile uint32_t guid;
 120         /**Synopsys ID Register (Read Only).  <i>Offset: 040h</i> */
 121         volatile uint32_t gsnpsid;
 122         /**User HW Config1 Register (Read Only).  <i>Offset: 044h</i> */
 123         volatile uint32_t ghwcfg1;
 124         /**User HW Config2 Register (Read Only).  <i>Offset: 048h</i> */
 125         volatile uint32_t ghwcfg2;
 126 #define DWC_SLAVE_ONLY_ARCH 0
 127 #define DWC_EXT_DMA_ARCH 1
 128 #define DWC_INT_DMA_ARCH 2
 129
 130 #define DWC_MODE_HNP_SRP_CAPABLE        0
 131 #define DWC_MODE_SRP_ONLY_CAPABLE       1
 132 #define DWC_MODE_NO_HNP_SRP_CAPABLE             2
 133 #define DWC_MODE_SRP_CAPABLE_DEVICE             3
 134 #define DWC_MODE_NO_SRP_CAPABLE_DEVICE  4
 135 #define DWC_MODE_SRP_CAPABLE_HOST       5
 136 #define DWC_MODE_NO_SRP_CAPABLE_HOST    6
 137
 138         /**User HW Config3 Register (Read Only).  <i>Offset: 04Ch</i> */
 139         volatile uint32_t ghwcfg3;
 140         /**User HW Config4 Register (Read Only).  <i>Offset: 050h</i>*/
 141         volatile uint32_t ghwcfg4;
 142         /** Reserved  <i>Offset: 054h-0FFh</i> */
 143         volatile uint32_t reserved[43];
 144         /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
 145         volatile uint32_t hptxfsiz;
 146         /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
 147                 otherwise Device Transmit FIFO#n Register.
 148          * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
 149         volatile uint32_t dptxfsiz_dieptxf[15];
 150 } dwc_otg_core_global_regs_t;
 151
 152 /**
 153  * This union represents the bit fields of the Core OTG Control
 154  * and Status Register (GOTGCTL).  Set the bits using the bit
 155  * fields then write the <i>d32</i> value to the register.
 156  */
 157 typedef union gotgctl_data
 158 {
 159         /** raw register data */
 160         uint32_t d32;
 161         /** register bits */
 162         struct
 163         {
 164                 unsigned sesreqscs : 1;
 165                 unsigned sesreq : 1;
 166                 unsigned reserved2_7 : 6;
 167                 unsigned hstnegscs : 1;
 168                 unsigned hnpreq : 1;
 169                 unsigned hstsethnpen : 1;
 170                 unsigned devhnpen : 1;
 171                 unsigned reserved12_15 : 4;
 172                 unsigned conidsts : 1;
 173                 unsigned reserved17 : 1;
 174                 unsigned asesvld : 1;
 175                 unsigned bsesvld : 1;
 176                 unsigned currmod : 1;
 177                 unsigned reserved21_31 : 11;
 178         } b;
 179 } gotgctl_data_t;
 180
 181 /**
 182  * This union represents the bit fields of the Core OTG Interrupt Register
 183  * (GOTGINT).  Set/clear the bits using the bit fields then write the <i>d32</i>
 184  * value to the register.
 185  */
 186 typedef union gotgint_data
 187 {
 188         /** raw register data */
 189         uint32_t d32;
 190         /** register bits */
 191         struct
 192         {
 193                 /** Current Mode */
 194                 unsigned reserved0_1 : 2;
 195
 196                 /** Session End Detected */
 197                 unsigned sesenddet : 1;
 198
 199                 unsigned reserved3_7 : 5;
 200
 201                 /** Session Request Success Status Change */
 202                 unsigned sesreqsucstschng : 1;
 203                 /** Host Negotiation Success Status Change */
 204                 unsigned hstnegsucstschng : 1;
 205
 206                 unsigned reserver10_16 : 7;
 207
 208                 /** Host Negotiation Detected */
 209                 unsigned hstnegdet : 1;
 210                 /** A-Device Timeout Change */
 211                 unsigned adevtoutchng : 1;
 212                 /** Debounce Done */
 213                 unsigned debdone : 1;
 214
 215                 unsigned reserved31_20 : 12;
 216
 217         } b;
 218 } gotgint_data_t;
 219
 220
 221 /**
 222  * This union represents the bit fields of the Core AHB Configuration
 223  * Register (GAHBCFG).  Set/clear the bits using the bit fields then
 224  * write the <i>d32</i> value to the register.
 225  */
 226 typedef union gahbcfg_data
 227 {
 228         /** raw register data */
 229         uint32_t d32;
 230         /** register bits */
 231         struct
 232         {
 233                 unsigned glblintrmsk : 1;
 234 #define DWC_GAHBCFG_GLBINT_ENABLE               1
 235
 236                 unsigned hburstlen : 4;
 237 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE        0
 238 #define DWC_GAHBCFG_INT_DMA_BURST_INCR          1
 239 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4         3
 240 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8         5
 241 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16        7
 242
 243                 unsigned dmaenable : 1;
 244 #define DWC_GAHBCFG_DMAENABLE                   1
 245                 unsigned reserved : 1;
 246                 unsigned nptxfemplvl_txfemplvl : 1;
 247                 unsigned ptxfemplvl : 1;
 248 #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY           1
 249 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY       0
 250                 unsigned reserved9_31 : 23;
 251         } b;
 252 } gahbcfg_data_t;
 253
 254 /**
 255  * This union represents the bit fields of the Core USB Configuration
 256  * Register (GUSBCFG).  Set the bits using the bit fields then write
 257  * the <i>d32</i> value to the register.
 258  */
 259 typedef union gusbcfg_data
 260 {
 261         /** raw register data */
 262         uint32_t d32;
 263         /** register bits */
 264         struct
 265         {
 266                 unsigned toutcal : 3;
 267                 unsigned phyif : 1;
 268                 unsigned ulpi_utmi_sel : 1;
 269                 unsigned fsintf : 1;
 270                 unsigned physel : 1;
 271                 unsigned ddrsel : 1;
 272                 unsigned srpcap : 1;
 273                 unsigned hnpcap : 1;
 274                 unsigned usbtrdtim : 4;
 275                 unsigned nptxfrwnden : 1;
 276                 unsigned phylpwrclksel : 1;
 277                 unsigned otgutmifssel : 1;
 278                 unsigned ulpi_fsls : 1;
 279                 unsigned ulpi_auto_res : 1;
 280                 unsigned ulpi_clk_sus_m : 1;
 281                 unsigned ulpi_ext_vbus_drv : 1;
 282                 unsigned ulpi_int_vbus_indicator : 1;
 283                 unsigned term_sel_dl_pulse : 1;
 284                 unsigned reserved23_27 : 5;
 285                 unsigned tx_end_delay : 1;
 286                 unsigned reserved29_31 : 3;
 287         } b;
 288 } gusbcfg_data_t;
 289
 290 /**
 291  * This union represents the bit fields of the Core Reset Register
 292  * (GRSTCTL).  Set/clear the bits using the bit fields then write the
 293  * <i>d32</i> value to the register.
 294  */
 295 typedef union grstctl_data
 296 {
 297         /** raw register data */
 298         uint32_t d32;
 299         /** register bits */
 300         struct
 301         {
 302                 /** Core Soft Reset (CSftRst) (Device and Host)
 303                  *
 304                  * The application can flush the control logic in the
 305                  * entire core using this bit. This bit resets the
 306                  * pipelines in the AHB Clock domain as well as the
 307                  * PHY Clock domain.
 308                  *
 309                  * The state machines are reset to an IDLE state, the
 310                  * control bits in the CSRs are cleared, all the
 311                  * transmit FIFOs and the receive FIFO are flushed.
 312                  *
 313                  * The status mask bits that control the generation of
 314                  * the interrupt, are cleared, to clear the
 315                  * interrupt. The interrupt status bits are not
 316                  * cleared, so the application can get the status of
 317                  * any events that occurred in the core after it has
 318                  * set this bit.
 319                  *
 320                  * Any transactions on the AHB are terminated as soon
 321                  * as possible following the protocol. Any
 322                  * transactions on the USB are terminated immediately.
 323                  *
 324                  * The configuration settings in the CSRs are
 325                  * unchanged, so the software doesn't have to
 326                  * reprogram these registers (Device
 327                  * Configuration/Host Configuration/Core System
 328                  * Configuration/Core PHY Configuration).
 329                  *
 330                  * The application can write to this bit, any time it
 331                  * wants to reset the core. This is a self clearing
 332                  * bit and the core clears this bit after all the
 333                  * necessary logic is reset in the core, which may
 334                  * take several clocks, depending on the current state
 335                  * of the core.
 336                  */
 337                 unsigned csftrst : 1;
 338                 /** Hclk Soft Reset
 339                  *
 340                  * The application uses this bit to reset the control logic in
 341                  * the AHB clock domain. Only AHB clock domain pipelines are
 342                  * reset.
 343                  */
 344                 unsigned hsftrst : 1;
 345                 /** Host Frame Counter Reset (Host Only)<br>
 346                  *
 347                  * The application can reset the (micro)frame number
 348                  * counter inside the core, using this bit. When the
 349                  * (micro)frame counter is reset, the subsequent SOF
 350                  * sent out by the core, will have a (micro)frame
 351                  * number of 0.
 352                  */
 353                 unsigned hstfrm : 1;
 354                 /** In Token Sequence Learning Queue Flush
 355                  * (INTknQFlsh) (Device Only)
 356                  */
 357                 unsigned intknqflsh : 1;
 358                 /** RxFIFO Flush (RxFFlsh) (Device and Host)
 359                  *
 360                  * The application can flush the entire Receive FIFO
 361                  * using this bit.      <p>The application must first
 362                  * ensure that the core is not in the middle of a
 363                  * transaction.  <p>The application should write into
 364                  * this bit, only after making sure that neither the
 365                  * DMA engine is reading from the RxFIFO nor the MAC
 366                  * is writing the data in to the FIFO.  <p>The
 367                  * application should wait until the bit is cleared
 368                  * before performing any other operations. This bit
 369                  * will takes 8 clocks (slowest of PHY or AHB clock)
 370                  * to clear.
 371                  */
 372                 unsigned rxfflsh : 1;
 373                 /** TxFIFO Flush (TxFFlsh) (Device and Host).
 374                  *
 375                  * This bit is used to selectively flush a single or
 376                  * all transmit FIFOs.  The application must first
 377                  * ensure that the core is not in the middle of a
 378                  * transaction.  <p>The application should write into
 379                  * this bit, only after making sure that neither the
 380                  * DMA engine is writing into the TxFIFO nor the MAC
 381                  * is reading the data out of the FIFO.  <p>The
 382                  * application should wait until the core clears this
 383                  * bit, before performing any operations. This bit
 384                  * will takes 8 clocks (slowest of PHY or AHB clock)
 385                  * to clear.
 386                  */
 387                 unsigned txfflsh : 1;
 388
 389                 /** TxFIFO Number (TxFNum) (Device and Host).
 390                  *
 391                  * This is the FIFO number which needs to be flushed,
 392                  * using the TxFIFO Flush bit. This field should not
 393                  * be changed until the TxFIFO Flush bit is cleared by
 394                  * the core.
 395                  *       - 0x0 : Non Periodic TxFIFO Flush
 396                  *       - 0x1 : Periodic TxFIFO #1 Flush in device mode
 397                  *         or Periodic TxFIFO in host mode
 398                  *       - 0x2 : Periodic TxFIFO #2 Flush in device mode.
 399                  *       - ...
 400                  *       - 0xF : Periodic TxFIFO #15 Flush in device mode
 401                  *       - 0x10: Flush all the Transmit NonPeriodic and
 402                  *         Transmit Periodic FIFOs in the core
 403                  */
 404                 unsigned txfnum : 5;
 405                 /** Reserved */
 406                 unsigned reserved11_29 : 19;
 407                 /** DMA Request Signal.  Indicated DMA request is in
 408                  * probress.  Used for debug purpose. */
 409                 unsigned dmareq : 1;
 410                 /** AHB Master Idle.  Indicates the AHB Master State
 411                  * Machine is in IDLE condition. */
 412                 unsigned ahbidle : 1;
 413         } b;
 414 } grstctl_t;
 415
 416
 417 /**
 418  * This union represents the bit fields of the Core Interrupt Mask
 419  * Register (GINTMSK).  Set/clear the bits using the bit fields then
 420  * write the <i>d32</i> value to the register.
 421  */
 422 typedef union gintmsk_data
 423 {
 424         /** raw register data */
 425         uint32_t d32;
 426         /** register bits */
 427         struct
 428         {
 429                 unsigned reserved0 : 1;
 430                 unsigned modemismatch : 1;
 431                 unsigned otgintr : 1;
 432                 unsigned sofintr : 1;
 433                 unsigned rxstsqlvl : 1;
 434                 unsigned nptxfempty : 1;
 435                 unsigned ginnakeff : 1;
 436                 unsigned goutnakeff : 1;
 437                 unsigned reserved8 : 1;
 438                 unsigned i2cintr : 1;
 439                 unsigned erlysuspend : 1;
 440                 unsigned usbsuspend : 1;
 441                 unsigned usbreset : 1;
 442                 unsigned enumdone : 1;
 443                 unsigned isooutdrop : 1;
 444                 unsigned eopframe : 1;
 445                 unsigned reserved16 : 1;
 446                 unsigned epmismatch : 1;
 447                 unsigned inepintr : 1;
 448                 unsigned outepintr : 1;
 449                 unsigned incomplisoin : 1;
 450                 unsigned incomplisoout : 1;
 451                 unsigned reserved22_23 : 2;
 452                 unsigned portintr : 1;
 453                 unsigned hcintr : 1;
 454                 unsigned ptxfempty : 1;
 455                 unsigned reserved27 : 1;
 456                 unsigned conidstschng : 1;
 457                 unsigned disconnect : 1;
 458                 unsigned sessreqintr : 1;
 459                 unsigned wkupintr : 1;
 460         } b;
 461 } gintmsk_data_t;
 462 /**
 463  * This union represents the bit fields of the Core Interrupt Register
 464  * (GINTSTS).  Set/clear the bits using the bit fields then write the
 465  * <i>d32</i> value to the register.
 466  */
 467 typedef union gintsts_data
 468 {
 469         /** raw register data */
 470         uint32_t d32;
 471 #define DWC_SOF_INTR_MASK 0x0008
 472         /** register bits */
 473         struct
 474         {
 475 #define DWC_HOST_MODE 1
 476                 unsigned curmode : 1;
 477                 unsigned modemismatch : 1;
 478                 unsigned otgintr : 1;
 479                 unsigned sofintr : 1;
 480                 unsigned rxstsqlvl : 1;
 481                 unsigned nptxfempty : 1;
 482                 unsigned ginnakeff : 1;
 483                 unsigned goutnakeff : 1;
 484                 unsigned reserved8 : 1;
 485                 unsigned i2cintr : 1;
 486                 unsigned erlysuspend : 1;
 487                 unsigned usbsuspend : 1;
 488                 unsigned usbreset : 1;
 489                 unsigned enumdone : 1;
 490                 unsigned isooutdrop : 1;
 491                 unsigned eopframe : 1;
 492                 unsigned intokenrx : 1;
 493                 unsigned epmismatch : 1;
 494                 unsigned inepint: 1;
 495                 unsigned outepintr : 1;
 496                 unsigned incomplisoin : 1;
 497                 unsigned incomplisoout : 1;
 498                 unsigned reserved22_23 : 2;
 499                 unsigned portintr : 1;
 500                 unsigned hcintr : 1;
 501                 unsigned ptxfempty : 1;
 502                 unsigned reserved27 : 1;
 503                 unsigned conidstschng : 1;
 504                 unsigned disconnect : 1;
 505                 unsigned sessreqintr : 1;
 506                 unsigned wkupintr : 1;
 507         } b;
 508 } gintsts_data_t;
 509
 510
 511 /**
 512  * This union represents the bit fields in the Device Receive Status Read and
 513  * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
 514  * element then read out the bits using the <i>b</i>it elements.
 515  */
 516 typedef union device_grxsts_data
 517 {
 518         /** raw register data */
 519         uint32_t d32;
 520         /** register bits */
 521         struct
 522         {
 523                 unsigned epnum : 4;
 524                 unsigned bcnt : 11;
 525                 unsigned dpid : 2;
 526
 527 #define DWC_STS_DATA_UPDT               0x2                               // OUT Data Packet
 528 #define DWC_STS_XFER_COMP               0x3                               // OUT Data Transfer Complete
 529
 530 #define DWC_DSTS_GOUT_NAK               0x1                               // Global OUT NAK
 531 #define DWC_DSTS_SETUP_COMP             0x4                               // Setup Phase Complete
 532 #define DWC_DSTS_SETUP_UPDT 0x6                           // SETUP Packet
 533                 unsigned pktsts : 4;
 534                 unsigned fn : 4;
 535                 unsigned reserved : 7;
 536         } b;
 537 } device_grxsts_data_t;
 538
 539 /**
 540  * This union represents the bit fields in the Host Receive Status Read and
 541  * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
 542  * element then read out the bits using the <i>b</i>it elements.
 543  */
 544 typedef union host_grxsts_data
 545 {
 546         /** raw register data */
 547         uint32_t d32;
 548         /** register bits */
 549         struct
 550         {
 551                 unsigned chnum : 4;
 552                 unsigned bcnt : 11;
 553                 unsigned dpid : 2;
 554
 555                 unsigned pktsts : 4;
 556 #define DWC_GRXSTS_PKTSTS_IN                      0x2
 557 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP    0x3
 558 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
 559 #define DWC_GRXSTS_PKTSTS_CH_HALTED               0x7
 560
 561                 unsigned reserved : 11;
 562         } b;
 563 } host_grxsts_data_t;
 564
 565 /**
 566  * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
 567  * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element then
 568  * read out the bits using the <i>b</i>it elements.
 569  */
 570 typedef union fifosize_data
 571 {
 572         /** raw register data */
 573         uint32_t d32;
 574         /** register bits */
 575         struct
 576         {
 577                 unsigned startaddr : 16;
 578                 unsigned depth : 16;
 579         } b;
 580 } fifosize_data_t;
 581
 582 /**
 583  * This union represents the bit fields in the Non-Periodic Transmit
 584  * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
 585  * <i>d32</i> element then read out the bits using the <i>b</i>it
 586  * elements.
 587  */
 588 typedef union gnptxsts_data
 589 {
 590         /** raw register data */
 591         uint32_t d32;
 592         /** register bits */
 593         struct
 594         {
 595                 unsigned nptxfspcavail : 16;
 596                 unsigned nptxqspcavail : 8;
 597                 /** Top of the Non-Periodic Transmit Request Queue
 598                  *      - bit 24 - Terminate (Last entry for the selected
 599                  *        channel/EP)
 600                  *      - bits 26:25 - Token Type
 601                  *        - 2'b00 - IN/OUT
 602                  *        - 2'b01 - Zero Length OUT
 603                  *        - 2'b10 - PING/Complete Split
 604                  *        - 2'b11 - Channel Halt
 605                  *      - bits 30:27 - Channel/EP Number
 606                  */
 607                 unsigned nptxqtop_terminate : 1;
 608                 unsigned nptxqtop_token : 2;
 609                 unsigned nptxqtop_chnep : 4;
 610                 unsigned reserved : 1;
 611         } b;
 612 } gnptxsts_data_t;
 613
 614 /**
 615  * This union represents the bit fields in the Transmit
 616  * FIFO Status Register (DTXFSTS). Read the register into the
 617  * <i>d32</i> element then read out the bits using the <i>b</i>it
 618  * elements.
 619  */
 620 typedef union dtxfsts_data
 621 {
 622         /** raw register data */
 623         uint32_t d32;
 624         /** register bits */
 625         struct
 626         {
 627                 unsigned txfspcavail : 16;
 628                 unsigned reserved : 16;
 629         } b;
 630 } dtxfsts_data_t;
 631
 632 /**
 633  * This union represents the bit fields in the I2C Control Register
 634  * (I2CCTL). Read the register into the <i>d32</i> element then read out the
 635  * bits using the <i>b</i>it elements.
 636  */
 637 typedef union gi2cctl_data
 638 {
 639         /** raw register data */
 640         uint32_t d32;
 641         /** register bits */
 642         struct
 643         {
 644                 unsigned rwdata : 8;
 645                 unsigned regaddr : 8;
 646                 unsigned addr : 7;
 647                 unsigned i2cen : 1;
 648                 unsigned ack : 1;
 649                 unsigned i2csuspctl : 1;
 650                 unsigned i2cdevaddr : 2;
 651                 unsigned reserved : 2;
 652                 unsigned rw : 1;
 653                 unsigned bsydne : 1;
 654         } b;
 655 } gi2cctl_data_t;
 656
 657 /**
 658  * This union represents the bit fields in the User HW Config1
 659  * Register.  Read the register into the <i>d32</i> element then read
 660  * out the bits using the <i>b</i>it elements.
 661  */
 662 typedef union hwcfg1_data
 663 {
 664         /** raw register data */
 665         uint32_t d32;
 666         /** register bits */
 667         struct
 668         {
 669                 unsigned ep_dir0 : 2;
 670                 unsigned ep_dir1 : 2;
 671                 unsigned ep_dir2 : 2;
 672                 unsigned ep_dir3 : 2;
 673                 unsigned ep_dir4 : 2;
 674                 unsigned ep_dir5 : 2;
 675                 unsigned ep_dir6 : 2;
 676                 unsigned ep_dir7 : 2;
 677                 unsigned ep_dir8 : 2;
 678                 unsigned ep_dir9 : 2;
 679                 unsigned ep_dir10 : 2;
 680                 unsigned ep_dir11 : 2;
 681                 unsigned ep_dir12 : 2;
 682                 unsigned ep_dir13 : 2;
 683                 unsigned ep_dir14 : 2;
 684                 unsigned ep_dir15 : 2;
 685         } b;
 686 } hwcfg1_data_t;
 687
 688 /**
 689  * This union represents the bit fields in the User HW Config2
 690  * Register.  Read the register into the <i>d32</i> element then read
 691  * out the bits using the <i>b</i>it elements.
 692  */
 693 typedef union hwcfg2_data
 694 {
 695         /** raw register data */
 696         uint32_t d32;
 697         /** register bits */
 698         struct
 699         {
 700                 /* GHWCFG2 */
 701                 unsigned op_mode : 3;
 702 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
 703 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
 704 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
 705 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
 706 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
 707 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
 708 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
 709
 710                 unsigned architecture : 2;
 711                 unsigned point2point : 1;
 712                 unsigned hs_phy_type : 2;
 713 #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
 714 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
 715 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
 716 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
 717
 718                 unsigned fs_phy_type : 2;
 719                 unsigned num_dev_ep : 4;
 720                 unsigned num_host_chan : 4;
 721                 unsigned perio_ep_supported : 1;
 722                 unsigned dynamic_fifo : 1;
 723                 unsigned multi_proc_int : 1;
 724                 unsigned reserved21 : 1;
 725                 unsigned nonperio_tx_q_depth : 2;
 726                 unsigned host_perio_tx_q_depth : 2;
 727                 unsigned dev_token_q_depth : 5;
 728                 unsigned reserved31 : 1;
 729         } b;
 730 } hwcfg2_data_t;
 731
 732 /**
 733  * This union represents the bit fields in the User HW Config3
 734  * Register.  Read the register into the <i>d32</i> element then read
 735  * out the bits using the <i>b</i>it elements.
 736  */
 737 typedef union hwcfg3_data
 738 {
 739         /** raw register data */
 740         uint32_t d32;
 741         /** register bits */
 742         struct
 743         {
 744                 /* GHWCFG3 */
 745                 unsigned xfer_size_cntr_width : 4;
 746                 unsigned packet_size_cntr_width : 3;
 747                 unsigned otg_func : 1;
 748                 unsigned i2c : 1;
 749                 unsigned vendor_ctrl_if : 1;
 750                 unsigned optional_features : 1;
 751                 unsigned synch_reset_type : 1;
 752                 unsigned ahb_phy_clock_synch : 1;
 753                 unsigned reserved15_13 : 3;
 754                 unsigned dfifo_depth : 16;
 755         } b;
 756 } hwcfg3_data_t;
 757
 758 /**
 759  * This union represents the bit fields in the User HW Config4
 760  * Register.  Read the register into the <i>d32</i> element then read
 761  * out the bits using the <i>b</i>it elements.
 762  */
 763 typedef union hwcfg4_data
 764 {
 765         /** raw register data */
 766         uint32_t d32;
 767         /** register bits */
 768         struct
 769         {
 770                 unsigned num_dev_perio_in_ep : 4;
 771                 unsigned power_optimiz : 1;
 772                 unsigned min_ahb_freq : 9;
 773                 unsigned utmi_phy_data_width : 2;
 774                 unsigned num_dev_mode_ctrl_ep : 4;
 775                 unsigned iddig_filt_en : 1;
 776                 unsigned vbus_valid_filt_en : 1;
 777                 unsigned a_valid_filt_en : 1;
 778                 unsigned b_valid_filt_en : 1;
 779                 unsigned session_end_filt_en : 1;
 780                 unsigned ded_fifo_en : 1;
 781                 unsigned num_in_eps : 4;
 782                 unsigned desc_dma : 1;
 783                 unsigned desc_dma_dyn : 1;
 784         } b;
 785 } hwcfg4_data_t;
 786
 787 ////////////////////////////////////////////
 788 // Device Registers
 789 /**
 790  * Device Global Registers. <i>Offsets 800h-BFFh</i>
 791  *
 792  * The following structures define the size and relative field offsets
 793  * for the Device Mode Registers.
 794  *
 795  * <i>These registers are visible only in Device mode and must not be
 796  * accessed in Host mode, as the results are unknown.</i>
 797  */
 798 typedef struct dwc_otg_dev_global_regs
 799 {
 800         /** Device Configuration Register. <i>Offset 800h</i> */
 801         volatile uint32_t dcfg;
 802         /** Device Control Register. <i>Offset: 804h</i> */
 803         volatile uint32_t dctl;
 804         /** Device Status Register (Read Only). <i>Offset: 808h</i> */
 805         volatile uint32_t dsts;
 806         /** Reserved. <i>Offset: 80Ch</i> */
 807         uint32_t unused;
 808         /** Device IN Endpoint Common Interrupt Mask
 809          * Register. <i>Offset: 810h</i> */
 810         volatile uint32_t diepmsk;
 811         /** Device OUT Endpoint Common Interrupt Mask
 812          * Register. <i>Offset: 814h</i> */
 813         volatile uint32_t doepmsk;
 814         /** Device All Endpoints Interrupt Register.  <i>Offset: 818h</i> */
 815         volatile uint32_t daint;
 816         /** Device All Endpoints Interrupt Mask Register.  <i>Offset:
 817          * 81Ch</i> */
 818         volatile uint32_t daintmsk;
 819         /** Device IN Token Queue Read Register-1 (Read Only).
 820          * <i>Offset: 820h</i> */
 821         volatile uint32_t dtknqr1;
 822         /** Device IN Token Queue Read Register-2 (Read Only).
 823          * <i>Offset: 824h</i> */
 824         volatile uint32_t dtknqr2;
 825         /** Device VBUS  discharge Register.  <i>Offset: 828h</i> */
 826         volatile uint32_t dvbusdis;
 827         /** Device VBUS Pulse Register.  <i>Offset: 82Ch</i> */
 828         volatile uint32_t dvbuspulse;
 829         /** Device IN Token Queue Read Register-3 (Read Only). /
 830          *      Device Thresholding control register (Read/Write)
 831          * <i>Offset: 830h</i> */
 832         volatile uint32_t dtknqr3_dthrctl;
 833         /** Device IN Token Queue Read Register-4 (Read Only). /
 834          *      Device IN EPs empty Inr. Mask Register (Read/Write)
 835          * <i>Offset: 834h</i> */
 836         volatile uint32_t dtknqr4_fifoemptymsk;
 837         /** Device Each Endpoint Interrupt Register (Read Only). /
 838          * <i>Offset: 838h</i> */
 839         volatile uint32_t deachint;
 840         /** Device Each Endpoint Interrupt mask Register (Read/Write). /
 841          * <i>Offset: 83Ch</i> */
 842         volatile uint32_t deachintmsk;
 843         /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
 844          * <i>Offset: 840h</i> */
 845         volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
 846         /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
 847          * <i>Offset: 880h</i> */
 848         volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
 849 } dwc_otg_device_global_regs_t;
 850
 851 /**
 852  * This union represents the bit fields in the Device Configuration
 853  * Register.  Read the register into the <i>d32</i> member then
 854  * set/clear the bits using the <i>b</i>it elements.  Write the
 855  * <i>d32</i> member to the dcfg register.
 856  */
 857 typedef union dcfg_data
 858 {
 859         /** raw register data */
 860         uint32_t d32;
 861         /** register bits */
 862         struct
 863         {
 864                 /** Device Speed */
 865                 unsigned devspd : 2;
 866                 /** Non Zero Length Status OUT Handshake */
 867                 unsigned nzstsouthshk : 1;
 868 #define DWC_DCFG_SEND_STALL 1
 869
 870                 unsigned reserved3 : 1;
 871                 /** Device Addresses */
 872                 unsigned devaddr : 7;
 873                 /** Periodic Frame Interval */
 874                 unsigned perfrint : 2;
 875 #define DWC_DCFG_FRAME_INTERVAL_80 0
 876 #define DWC_DCFG_FRAME_INTERVAL_85 1
 877 #define DWC_DCFG_FRAME_INTERVAL_90 2
 878 #define DWC_DCFG_FRAME_INTERVAL_95 3
 879
 880                 unsigned reserved13_17 : 5;
 881                 /** In Endpoint Mis-match count */
 882                 unsigned epmscnt : 5;
 883                 /** Enable Descriptor DMA in Device mode */
 884                 unsigned descdma : 1;
 885         } b;
 886 } dcfg_data_t;
 887
 888 /**
 889  * This union represents the bit fields in the Device Control
 890  * Register.  Read the register into the <i>d32</i> member then
 891  * set/clear the bits using the <i>b</i>it elements.
 892  */
 893 typedef union dctl_data
 894 {
 895         /** raw register data */
 896         uint32_t d32;
 897         /** register bits */
 898         struct
 899         {
 900                 /** Remote Wakeup */
 901                 unsigned rmtwkupsig : 1;
 902                 /** Soft Disconnect */
 903                 unsigned sftdiscon : 1;
 904                 /** Global Non-Periodic IN NAK Status */
 905                 unsigned gnpinnaksts : 1;
 906                 /** Global OUT NAK Status */
 907                 unsigned goutnaksts : 1;
 908                 /** Test Control */
 909                 unsigned tstctl : 3;
 910                 /** Set Global Non-Periodic IN NAK */
 911                 unsigned sgnpinnak : 1;
 912                 /** Clear Global Non-Periodic IN NAK */
 913                 unsigned cgnpinnak : 1;
 914                 /** Set Global OUT NAK */
 915                 unsigned sgoutnak : 1;
 916                 /** Clear Global OUT NAK */
 917                 unsigned cgoutnak : 1;
 918
 919                 /** Power-On Programming Done */
 920                 unsigned pwronprgdone : 1;
 921                 /** Global Continue on BNA */
 922                 unsigned gcontbna : 1;
 923                 /** Global Multi Count */
 924                 unsigned gmc : 2;
 925                 /** Ignore Frame Number for ISOC EPs */
 926                 unsigned ifrmnum : 1;
 927                 /** NAK on Babble */
 928                 unsigned nakonbble : 1;
 929
 930                 unsigned reserved16_31 : 16;
 931         } b;
 932 } dctl_data_t;
 933
 934 /**
 935  * This union represents the bit fields in the Device Status
 936  * Register.  Read the register into the <i>d32</i> member then
 937  * set/clear the bits using the <i>b</i>it elements.
 938  */
 939 typedef union dsts_data
 940 {
 941         /** raw register data */
 942         uint32_t d32;
 943         /** register bits */
 944         struct
 945         {
 946                 /** Suspend Status */
 947                 unsigned suspsts : 1;
 948                 /** Enumerated Speed */
 949                 unsigned enumspd : 2;
 950 #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
 951 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
 952 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ               2
 953 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ              3
 954                 /** Erratic Error */
 955                 unsigned errticerr : 1;
 956                 unsigned reserved4_7: 4;
 957                 /** Frame or Microframe Number of the received SOF */
 958                 unsigned soffn : 14;
 959                 unsigned reserved22_31 : 10;
 960         } b;
 961 } dsts_data_t;
 962
 963
 964 /**
 965  * This union represents the bit fields in the Device IN EP Interrupt
 966  * Register and the Device IN EP Common Mask Register.
 967  *
 968  * - Read the register into the <i>d32</i> member then set/clear the
 969  *       bits using the <i>b</i>it elements.
 970  */
 971 typedef union diepint_data
 972 {
 973         /** raw register data */
 974         uint32_t d32;
 975         /** register bits */
 976         struct
 977         {
 978                 /** Transfer complete mask */
 979                 unsigned xfercompl : 1;
 980                 /** Endpoint disable mask */
 981                 unsigned epdisabled : 1;
 982                 /** AHB Error mask */
 983                 unsigned ahberr : 1;
 984                 /** TimeOUT Handshake mask (non-ISOC EPs) */
 985                 unsigned timeout : 1;
 986                 /** IN Token received with TxF Empty mask */
 987                 unsigned intktxfemp : 1;
 988                 /** IN Token Received with EP mismatch mask */
 989                 unsigned intknepmis : 1;
 990                 /** IN Endpoint HAK Effective mask */
 991                 unsigned inepnakeff : 1;
 992                 /** IN Endpoint HAK Effective mask */
 993                 unsigned emptyintr : 1;
 994
 995                 unsigned txfifoundrn : 1;
 996
 997                 /** BNA Interrupt mask */
 998                 unsigned bna : 1;
 999
1000                 unsigned reserved10_12 : 3;
1001                 /** BNA Interrupt mask */
1002                 unsigned nak : 1;
1003
1004                 unsigned reserved14_31 : 18;
1005                 } b;
1006 } diepint_data_t;
1007
1008 /**
1009  * This union represents the bit fields in the Device IN EP
1010  * Common/Dedicated Interrupt Mask Register.
1011  */
1012 typedef union diepint_data diepmsk_data_t;
1013
1014 /**
1015  * This union represents the bit fields in the Device OUT EP Interrupt
1016  * Registerand Device OUT EP Common Interrupt Mask Register.
1017  *
1018  * - Read the register into the <i>d32</i> member then set/clear the
1019  *       bits using the <i>b</i>it elements.
1020  */
1021 typedef union doepint_data
1022 {
1023         /** raw register data */
1024         uint32_t d32;
1025         /** register bits */
1026         struct
1027         {
1028                 /** Transfer complete */
1029                 unsigned xfercompl : 1;
1030                 /** Endpoint disable  */
1031                 unsigned epdisabled : 1;
1032                 /** AHB Error */
1033                 unsigned ahberr : 1;
1034                 /** Setup Phase Done (contorl EPs) */
1035                 unsigned setup : 1;
1036                 /** OUT Token Received when Endpoint Disabled */
1037                 unsigned outtknepdis : 1;
1038
1039                 unsigned stsphsercvd : 1;
1040                 /** Back-to-Back SETUP Packets Received */
1041                 unsigned back2backsetup : 1;
1042
1043                 unsigned reserved7 : 1;
1044                 /** OUT packet Error */
1045                 unsigned outpkterr : 1;
1046                 /** BNA Interrupt */
1047                 unsigned bna : 1;
1048
1049                 unsigned reserved10 : 1;
1050                 /** Packet Drop Status */
1051                 unsigned pktdrpsts : 1;
1052                 /** Babble Interrupt */
1053                 unsigned babble : 1;
1054                 /** NAK Interrupt */
1055                 unsigned nak : 1;
1056                 /** NYET Interrupt */
1057                 unsigned nyet : 1;
1058
1059                 unsigned reserved15_31 : 17;
1060         } b;
1061 } doepint_data_t;
1062
1063 /**
1064  * This union represents the bit fields in the Device OUT EP
1065  * Common/Dedicated Interrupt Mask Register.
1066  */
1067 typedef union doepint_data doepmsk_data_t;
1068
1069 /**
1070  * This union represents the bit fields in the Device All EP Interrupt
1071  * and Mask Registers.
1072  * - Read the register into the <i>d32</i> member then set/clear the
1073  *       bits using the <i>b</i>it elements.
1074  */
1075 typedef union daint_data
1076 {
1077         /** raw register data */
1078         uint32_t d32;
1079         /** register bits */
1080         struct
1081         {
1082                 /** IN Endpoint bits */
1083                 unsigned in : 16;
1084                 /** OUT Endpoint bits */
1085                 unsigned out : 16;
1086         } ep;
1087         struct
1088         {
1089                 /** IN Endpoint bits */
1090                 unsigned inep0  : 1;
1091                 unsigned inep1  : 1;
1092                 unsigned inep2  : 1;
1093                 unsigned inep3  : 1;
1094                 unsigned inep4  : 1;
1095                 unsigned inep5  : 1;
1096                 unsigned inep6  : 1;
1097                 unsigned inep7  : 1;
1098                 unsigned inep8  : 1;
1099                 unsigned inep9  : 1;
1100                 unsigned inep10 : 1;
1101                 unsigned inep11 : 1;
1102                 unsigned inep12 : 1;
1103                 unsigned inep13 : 1;
1104                 unsigned inep14 : 1;
1105                 unsigned inep15 : 1;
1106                 /** OUT Endpoint bits */
1107                 unsigned outep0  : 1;
1108                 unsigned outep1  : 1;
1109                 unsigned outep2  : 1;
1110                 unsigned outep3  : 1;
1111                 unsigned outep4  : 1;
1112                 unsigned outep5  : 1;
1113                 unsigned outep6  : 1;
1114                 unsigned outep7  : 1;
1115                 unsigned outep8  : 1;
1116                 unsigned outep9  : 1;
1117                 unsigned outep10 : 1;
1118                 unsigned outep11 : 1;
1119                 unsigned outep12 : 1;
1120                 unsigned outep13 : 1;
1121                 unsigned outep14 : 1;
1122                 unsigned outep15 : 1;
1123         } b;
1124 } daint_data_t;
1125
1126 /**
1127  * This union represents the bit fields in the Device IN Token Queue
1128  * Read Registers.
1129  * - Read the register into the <i>d32</i> member.
1130  * - READ-ONLY Register
1131  */
1132 typedef union dtknq1_data
1133 {
1134         /** raw register data */
1135         uint32_t d32;
1136         /** register bits */
1137         struct
1138         {
1139                 /** In Token Queue Write Pointer */
1140                 unsigned intknwptr : 5;
1141                 /** Reserved */
1142                 unsigned reserved05_06 : 2;
1143                 /** write pointer has wrapped. */
1144                 unsigned wrap_bit : 1;
1145                 /** EP Numbers of IN Tokens 0 ... 4 */
1146                 unsigned epnums0_5 : 24;
1147         }b;
1148 } dtknq1_data_t;
1149
1150 /**
1151  * This union represents Threshold control Register
1152  * - Read and write the register into the <i>d32</i> member.
1153  * - READ-WRITABLE Register
1154  */
1155 typedef union dthrctl_data
1156 {
1157         /** raw register data */
1158         uint32_t d32;
1159         /** register bits */
1160         struct
1161         {
1162                 /** non ISO Tx Thr. Enable */
1163                 unsigned non_iso_thr_en : 1;
1164                 /** ISO Tx Thr. Enable */
1165                 unsigned iso_thr_en : 1;
1166                 /** Tx Thr. Length */
1167                 unsigned tx_thr_len : 9;
1168                 /** Reserved */
1169                 unsigned reserved11_15 : 5;
1170                 /** Rx Thr. Enable */
1171                 unsigned rx_thr_en : 1;
1172                 /** Rx Thr. Length */
1173                 unsigned rx_thr_len : 9;
1174                 /** Reserved */
1175                 unsigned reserved26_31 : 6;
1176         }b;
1177 } dthrctl_data_t;
1178
1179
1180 /**
1181  * Device Logical IN Endpoint-Specific Registers. <i>Offsets
1182  * 900h-AFCh</i>
1183  *
1184  * There will be one set of endpoint registers per logical endpoint
1185  * implemented.
1186  *
1187  * <i>These registers are visible only in Device mode and must not be
1188  * accessed in Host mode, as the results are unknown.</i>
1189  */
1190 typedef struct dwc_otg_dev_in_ep_regs
1191 {
1192         /** Device IN Endpoint Control Register. <i>Offset:900h +
1193          * (ep_num * 20h) + 00h</i> */
1194         volatile uint32_t diepctl;
1195         /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
1196         uint32_t reserved04;
1197         /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
1198          * (ep_num * 20h) + 08h</i> */
1199         volatile uint32_t diepint;
1200         /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
1201         uint32_t reserved0C;
1202         /** Device IN Endpoint Transfer Size
1203          * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
1204         volatile uint32_t dieptsiz;
1205         /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
1206          * (ep_num * 20h) + 14h</i> */
1207         volatile uint32_t diepdma;
1208         /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
1209          * (ep_num * 20h) + 18h</i> */
1210         volatile uint32_t dtxfsts;
1211         /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
1212          * (ep_num * 20h) + 1Ch</i> */
1213         volatile uint32_t diepdmab;
1214 } dwc_otg_dev_in_ep_regs_t;
1215
1216 /**
1217  * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
1218  * B00h-CFCh</i>
1219  *
1220  * There will be one set of endpoint registers per logical endpoint
1221  * implemented.
1222  *
1223  * <i>These registers are visible only in Device mode and must not be
1224  * accessed in Host mode, as the results are unknown.</i>
1225  */
1226 typedef struct dwc_otg_dev_out_ep_regs
1227 {
1228         /** Device OUT Endpoint Control Register. <i>Offset:B00h +
1229          * (ep_num * 20h) + 00h</i> */
1230         volatile uint32_t doepctl;
1231         /** Device OUT Endpoint Frame number Register.  <i>Offset:
1232          * B00h + (ep_num * 20h) + 04h</i> */
1233         volatile uint32_t doepfn;
1234         /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
1235          * (ep_num * 20h) + 08h</i> */
1236         volatile uint32_t doepint;
1237         /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
1238         uint32_t reserved0C;
1239         /** Device OUT Endpoint Transfer Size Register. <i>Offset:
1240          * B00h + (ep_num * 20h) + 10h</i> */
1241         volatile uint32_t doeptsiz;
1242         /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
1243          * + (ep_num * 20h) + 14h</i> */
1244         volatile uint32_t doepdma;
1245         /** Reserved. <i>Offset:B00h +   * (ep_num * 20h) + 1Ch</i> */
1246         uint32_t unused;
1247         /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
1248          * + (ep_num * 20h) + 1Ch</i> */
1249         uint32_t doepdmab;
1250 } dwc_otg_dev_out_ep_regs_t;
1251
1252 /**
1253  * This union represents the bit fields in the Device EP Control
1254  * Register.  Read the register into the <i>d32</i> member then
1255  * set/clear the bits using the <i>b</i>it elements.
1256  */
1257 typedef union depctl_data
1258 {
1259         /** raw register data */
1260         uint32_t d32;
1261         /** register bits */
1262         struct
1263         {
1264                 /** Maximum Packet Size
1265                  * IN/OUT EPn
1266                  * IN/OUT EP0 - 2 bits
1267                  *       2'b00: 64 Bytes
1268                  *       2'b01: 32
1269                  *       2'b10: 16
1270                  *       2'b11: 8 */
1271                 unsigned mps : 11;
1272 #define DWC_DEP0CTL_MPS_64       0
1273 #define DWC_DEP0CTL_MPS_32       1
1274 #define DWC_DEP0CTL_MPS_16       2
1275 #define DWC_DEP0CTL_MPS_8        3
1276
1277                 /** Next Endpoint
1278                  * IN EPn/IN EP0
1279                  * OUT EPn/OUT EP0 - reserved */
1280                 unsigned nextep : 4;
1281
1282                 /** USB Active Endpoint */
1283                 unsigned usbactep : 1;
1284
1285                 /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
1286                  * This field contains the PID of the packet going to
1287                  * be received or transmitted on this endpoint. The
1288                  * application should program the PID of the first
1289                  * packet going to be received or transmitted on this
1290                  * endpoint , after the endpoint is
1291                  * activated. Application use the SetD1PID and
1292                  * SetD0PID fields of this register to program either
1293                  * D0 or D1 PID.
1294                  *
1295                  * The encoding for this field is
1296                  *       - 0: D0
1297                  *       - 1: D1
1298                  */
1299                 unsigned dpid : 1;
1300
1301                 /** NAK Status */
1302                 unsigned naksts : 1;
1303
1304                 /** Endpoint Type
1305                  *      2'b00: Control
1306                  *      2'b01: Isochronous
1307                  *      2'b10: Bulk
1308                  *      2'b11: Interrupt */
1309                 unsigned eptype : 2;
1310
1311                 /** Snoop Mode
1312                  * OUT EPn/OUT EP0
1313                  * IN EPn/IN EP0 - reserved */
1314                 unsigned snp : 1;
1315
1316                 /** Stall Handshake */
1317                 unsigned stall : 1;
1318
1319                 /** Tx Fifo Number
1320                  * IN EPn/IN EP0
1321                  * OUT EPn/OUT EP0 - reserved */
1322                 unsigned txfnum : 4;
1323
1324                 /** Clear NAK */
1325                 unsigned cnak : 1;
1326                 /** Set NAK */
1327                 unsigned snak : 1;
1328                 /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
1329                  * Writing to this field sets the Endpoint DPID (DPID)
1330                  * field in this register to DATA0. Set Even
1331                  * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
1332                  * Writing to this field sets the Even/Odd
1333                  * (micro)frame (EO_FrNum) field to even (micro)
1334                  * frame.
1335                  */
1336                 unsigned setd0pid : 1;
1337                 /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
1338                  * Writing to this field sets the Endpoint DPID (DPID)
1339                  * field in this register to DATA1 Set Odd
1340                  * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
1341                  * Writing to this field sets the Even/Odd
1342                  * (micro)frame (EO_FrNum) field to odd (micro) frame.
1343                  */
1344                 unsigned setd1pid : 1;
1345
1346                 /** Endpoint Disable */
1347                 unsigned epdis : 1;
1348                 /** Endpoint Enable */
1349                 unsigned epena : 1;
1350                 } b;
1351 } depctl_data_t;
1352
1353 /**
1354  * This union represents the bit fields in the Device EP Transfer
1355  * Size Register.  Read the register into the <i>d32</i> member then
1356  * set/clear the bits using the <i>b</i>it elements.
1357  */
1358 typedef union deptsiz_data
1359 {
1360                 /** raw register data */
1361                 uint32_t d32;
1362                 /** register bits */
1363                 struct {
1364                 /** Transfer size */
1365                 unsigned xfersize : 19;
1366                 /** Packet Count */
1367                 unsigned pktcnt : 10;
1368                 /** Multi Count - Periodic IN endpoints */
1369                 unsigned mc : 2;
1370                 unsigned reserved : 1;
1371                 } b;
1372 } deptsiz_data_t;
1373
1374 /**
1375  * This union represents the bit fields in the Device EP 0 Transfer
1376  * Size Register.  Read the register into the <i>d32</i> member then
1377  * set/clear the bits using the <i>b</i>it elements.
1378  */
1379 typedef union deptsiz0_data
1380 {
1381                 /** raw register data */
1382                 uint32_t d32;
1383                 /** register bits */
1384                 struct {
1385                 /** Transfer size */
1386                 unsigned xfersize : 7;
1387                                 /** Reserved */
1388                                 unsigned reserved7_18 : 12;
1389                 /** Packet Count */
1390                 unsigned pktcnt : 1;
1391                                 /** Reserved */
1392                 unsigned reserved20_28 : 9;
1393                                 /**Setup Packet Count (DOEPTSIZ0 Only) */
1394                                 unsigned supcnt : 2;
1395                                 unsigned reserved31;
1396                 } b;
1397 } deptsiz0_data_t;
1398
1399
1400 /////////////////////////////////////////////////
1401 // DMA Descriptor Specific Structures
1402 //
1403
1404 /** Buffer status definitions */
1405
1406 #define BS_HOST_READY   0x0
1407 #define BS_DMA_BUSY             0x1
1408 #define BS_DMA_DONE             0x2
1409 #define BS_HOST_BUSY    0x3
1410
1411 /** Receive/Transmit status definitions */
1412
1413 #define RTS_SUCCESS             0x0
1414 #define RTS_BUFFLUSH    0x1
1415 #define RTS_RESERVED    0x2
1416 #define RTS_BUFERR              0x3
1417
1418
1419 /**
1420  * This union represents the bit fields in the DMA Descriptor
1421  * status quadlet. Read the quadlet into the <i>d32</i> member then
1422  * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
1423  * <i>b_iso_in</i> elements.
1424  */
1425 typedef union desc_sts_data
1426 {
1427                 /** raw register data */
1428                 uint32_t d32;
1429                 /** quadlet bits */
1430                 struct {
1431                 /** Received number of bytes */
1432                 unsigned bytes : 16;
1433
1434                 unsigned reserved16_22 : 7;
1435                 /** Multiple Transfer - only for OUT EPs */
1436                 unsigned mtrf : 1;
1437                 /** Setup Packet received - only for OUT EPs */
1438                 unsigned sr : 1;
1439                 /** Interrupt On Complete */
1440                 unsigned ioc : 1;
1441                 /** Short Packet */
1442                 unsigned sp : 1;
1443                 /** Last */
1444                 unsigned l : 1;
1445                 /** Receive Status */
1446                 unsigned sts : 2;
1447                 /** Buffer Status */
1448                 unsigned bs : 2;
1449                 } b;
1450
1451 #ifdef DWC_EN_ISOC
1452                 /** iso out quadlet bits */
1453                 struct {
1454                 /** Received number of bytes */
1455                 unsigned rxbytes : 11;
1456
1457                 unsigned reserved11 : 1;
1458                 /** Frame Number */
1459                 unsigned framenum : 11;
1460                 /** Received ISO Data PID */
1461                 unsigned pid : 2;
1462                 /** Interrupt On Complete */
1463                 unsigned ioc : 1;
1464                 /** Short Packet */
1465                 unsigned sp : 1;
1466                 /** Last */
1467                 unsigned l : 1;
1468                 /** Receive Status */
1469                 unsigned rxsts : 2;
1470                 /** Buffer Status */
1471                 unsigned bs : 2;
1472                 } b_iso_out;
1473
1474                 /** iso in quadlet bits */
1475                 struct {
1476                 /** Transmited number of bytes */
1477                 unsigned txbytes : 12;
1478                 /** Frame Number */
1479                 unsigned framenum : 11;
1480                 /** Transmited ISO Data PID */
1481                 unsigned pid : 2;
1482                 /** Interrupt On Complete */
1483                 unsigned ioc : 1;
1484                 /** Short Packet */
1485                 unsigned sp : 1;
1486                 /** Last */
1487                 unsigned l : 1;
1488                 /** Transmit Status */
1489                 unsigned txsts : 2;
1490                 /** Buffer Status */
1491                 unsigned bs : 2;
1492                 } b_iso_in;
1493 #endif //DWC_EN_ISOC
1494 } desc_sts_data_t;
1495
1496 /**
1497  * DMA Descriptor structure
1498  *
1499  * DMA Descriptor structure contains two quadlets:
1500  * Status quadlet and Data buffer pointer.
1501  */
1502 typedef struct dwc_otg_dma_desc
1503 {
1504         /** DMA Descriptor status quadlet */
1505         desc_sts_data_t status;
1506         /** DMA Descriptor data buffer pointer */
1507         dma_addr_t      buf;
1508 } dwc_otg_dma_desc_t;
1509
1510 /**
1511  * The dwc_otg_dev_if structure contains information needed to manage
1512  * the DWC_otg controller acting in device mode. It represents the
1513  * programming view of the device-specific aspects of the controller.
1514  */
1515 typedef struct dwc_otg_dev_if
1516 {
1517         /** Pointer to device Global registers.
1518          * Device Global Registers starting at offset 800h
1519          */
1520         dwc_otg_device_global_regs_t *dev_global_regs;
1521 #define DWC_DEV_GLOBAL_REG_OFFSET 0x800
1522
1523         /**
1524          * Device Logical IN Endpoint-Specific Registers 900h-AFCh
1525          */
1526         dwc_otg_dev_in_ep_regs_t         *in_ep_regs[MAX_EPS_CHANNELS];
1527 #define DWC_DEV_IN_EP_REG_OFFSET 0x900
1528 #define DWC_EP_REG_OFFSET 0x20
1529
1530         /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
1531         dwc_otg_dev_out_ep_regs_t        *out_ep_regs[MAX_EPS_CHANNELS];
1532 #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
1533
1534         /* Device configuration information*/
1535         uint8_t  speed;                          /**< Device Speed      0: Unknown, 1: LS, 2:FS, 3: HS */
1536         uint8_t  num_in_eps;             /**< Number # of Tx EP range: 0-15 exept ep0 */
1537         uint8_t  num_out_eps;            /**< Number # of Rx EP range: 0-15 exept ep 0*/
1538
1539         /** Size of periodic FIFOs (Bytes) */
1540         uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
1541
1542         /** Size of Tx FIFOs (Bytes) */
1543         uint16_t tx_fifo_size[MAX_TX_FIFOS];
1544
1545         /** Thresholding enable flags and length varaiables **/
1546         uint16_t rx_thr_en;
1547         uint16_t iso_tx_thr_en;
1548         uint16_t non_iso_tx_thr_en;
1549
1550         uint16_t rx_thr_length;
1551         uint16_t tx_thr_length;
1552
1553         /**
1554          * Pointers to the DMA Descriptors for EP0 Control
1555          * transfers (virtual and physical)
1556          */
1557
1558         /** 2 descriptors for SETUP packets */
1559         uint32_t dma_setup_desc_addr[2];
1560         dwc_otg_dma_desc_t* setup_desc_addr[2];
1561
1562         /** Pointer to Descriptor with latest SETUP packet */
1563         dwc_otg_dma_desc_t* psetup;
1564
1565         /** Index of current SETUP handler descriptor */
1566         uint32_t setup_desc_index;
1567
1568         /** Descriptor for Data In or Status In phases */
1569         uint32_t dma_in_desc_addr;
1570         dwc_otg_dma_desc_t* in_desc_addr;;
1571
1572         /** Descriptor for Data Out or Status Out phases */
1573         uint32_t dma_out_desc_addr;
1574         dwc_otg_dma_desc_t* out_desc_addr;
1575
1576 } dwc_otg_dev_if_t;
1577
1578
1579
1580
1581 /////////////////////////////////////////////////
1582 // Host Mode Register Structures
1583 //
1584 /**
1585  * The Host Global Registers structure defines the size and relative
1586  * field offsets for the Host Mode Global Registers.  Host Global
1587  * Registers offsets 400h-7FFh.
1588 */
1589 typedef struct dwc_otg_host_global_regs
1590 {
1591         /** Host Configuration Register.   <i>Offset: 400h</i> */
1592         volatile uint32_t hcfg;
1593         /** Host Frame Interval Register.       <i>Offset: 404h</i> */
1594         volatile uint32_t hfir;
1595         /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
1596         volatile uint32_t hfnum;
1597         /** Reserved.   <i>Offset: 40Ch</i> */
1598         uint32_t reserved40C;
1599         /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
1600         volatile uint32_t hptxsts;
1601         /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
1602         volatile uint32_t haint;
1603         /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
1604         volatile uint32_t haintmsk;
1605 } dwc_otg_host_global_regs_t;
1606
1607 /**
1608  * This union represents the bit fields in the Host Configuration Register.
1609  * Read the register into the <i>d32</i> member then set/clear the bits using
1610  * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
1611  */
1612 typedef union hcfg_data
1613 {
1614         /** raw register data */
1615         uint32_t d32;
1616
1617         /** register bits */
1618         struct
1619         {
1620                 /** FS/LS Phy Clock Select */
1621                 unsigned fslspclksel : 2;
1622 #define DWC_HCFG_30_60_MHZ 0
1623 #define DWC_HCFG_48_MHZ    1
1624 #define DWC_HCFG_6_MHZ     2
1625
1626                 /** FS/LS Only Support */
1627                 unsigned fslssupp : 1;
1628                 } b;
1629 } hcfg_data_t;
1630
1631 /**
1632  * This union represents the bit fields in the Host Frame Remaing/Number
1633  * Register.
1634  */
1635 typedef union hfir_data
1636 {
1637         /** raw register data */
1638         uint32_t d32;
1639
1640         /** register bits */
1641         struct
1642         {
1643                 unsigned frint : 16;
1644                 unsigned reserved : 16;
1645         } b;
1646 } hfir_data_t;
1647
1648 /**
1649  * This union represents the bit fields in the Host Frame Remaing/Number
1650  * Register.
1651  */
1652 typedef union hfnum_data
1653 {
1654         /** raw register data */
1655         uint32_t d32;
1656
1657         /** register bits */
1658         struct
1659         {
1660                 unsigned frnum : 16;
1661 #define DWC_HFNUM_MAX_FRNUM 0x3FFF
1662                 unsigned frrem : 16;
1663         } b;
1664 } hfnum_data_t;
1665
1666 typedef union hptxsts_data
1667 {
1668         /** raw register data */
1669         uint32_t d32;
1670
1671         /** register bits */
1672         struct
1673         {
1674                 unsigned ptxfspcavail : 16;
1675                 unsigned ptxqspcavail : 8;
1676                 /** Top of the Periodic Transmit Request Queue
1677                  *      - bit 24 - Terminate (last entry for the selected channel)
1678                  *      - bits 26:25 - Token Type
1679                  *        - 2'b00 - Zero length
1680                  *        - 2'b01 - Ping
1681                  *        - 2'b10 - Disable
1682                  *      - bits 30:27 - Channel Number
1683                  *      - bit 31 - Odd/even microframe
1684                  */
1685                 unsigned ptxqtop_terminate : 1;
1686                 unsigned ptxqtop_token : 2;
1687                 unsigned ptxqtop_chnum : 4;
1688                 unsigned ptxqtop_odd : 1;
1689         } b;
1690 } hptxsts_data_t;
1691
1692 /**
1693  * This union represents the bit fields in the Host Port Control and Status
1694  * Register. Read the register into the <i>d32</i> member then set/clear the
1695  * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1696  * hprt0 register.
1697  */
1698 typedef union hprt0_data
1699 {
1700         /** raw register data */
1701         uint32_t d32;
1702         /** register bits */
1703         struct
1704         {
1705                 unsigned prtconnsts : 1;
1706                 unsigned prtconndet : 1;
1707                 unsigned prtena : 1;
1708                 unsigned prtenchng : 1;
1709                 unsigned prtovrcurract : 1;
1710                 unsigned prtovrcurrchng : 1;
1711                 unsigned prtres : 1;
1712                 unsigned prtsusp : 1;
1713                 unsigned prtrst : 1;
1714                 unsigned reserved9 : 1;
1715                 unsigned prtlnsts : 2;
1716                 unsigned prtpwr : 1;
1717                 unsigned prttstctl : 4;
1718                 unsigned prtspd : 2;
1719 #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
1720 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1
1721 #define DWC_HPRT0_PRTSPD_LOW_SPEED      2
1722                 unsigned reserved19_31 : 13;
1723         } b;
1724 } hprt0_data_t;
1725
1726 /**
1727  * This union represents the bit fields in the Host All Interrupt
1728  * Register.
1729  */
1730 typedef union haint_data
1731 {
1732         /** raw register data */
1733         uint32_t d32;
1734         /** register bits */
1735         struct
1736         {
1737                 unsigned ch0 : 1;
1738                 unsigned ch1 : 1;
1739                 unsigned ch2 : 1;
1740                 unsigned ch3 : 1;
1741                 unsigned ch4 : 1;
1742                 unsigned ch5 : 1;
1743                 unsigned ch6 : 1;
1744                 unsigned ch7 : 1;
1745                 unsigned ch8 : 1;
1746                 unsigned ch9 : 1;
1747                 unsigned ch10 : 1;
1748                 unsigned ch11 : 1;
1749                 unsigned ch12 : 1;
1750                 unsigned ch13 : 1;
1751                 unsigned ch14 : 1;
1752                 unsigned ch15 : 1;
1753                 unsigned reserved : 16;
1754         } b;
1755
1756         struct
1757         {
1758                 unsigned chint : 16;
1759                 unsigned reserved : 16;
1760         } b2;
1761 } haint_data_t;
1762
1763 /**
1764  * This union represents the bit fields in the Host All Interrupt
1765  * Register.
1766  */
1767 typedef union haintmsk_data
1768 {
1769         /** raw register data */
1770         uint32_t d32;
1771         /** register bits */
1772         struct
1773         {
1774                 unsigned ch0 : 1;
1775                 unsigned ch1 : 1;
1776                 unsigned ch2 : 1;
1777                 unsigned ch3 : 1;
1778                 unsigned ch4 : 1;
1779                 unsigned ch5 : 1;
1780                 unsigned ch6 : 1;
1781                 unsigned ch7 : 1;
1782                 unsigned ch8 : 1;
1783                 unsigned ch9 : 1;
1784                 unsigned ch10 : 1;
1785                 unsigned ch11 : 1;
1786                 unsigned ch12 : 1;
1787                 unsigned ch13 : 1;
1788                 unsigned ch14 : 1;
1789                 unsigned ch15 : 1;
1790                 unsigned reserved : 16;
1791         } b;
1792
1793         struct
1794         {
1795                 unsigned chint : 16;
1796                 unsigned reserved : 16;
1797         } b2;
1798 } haintmsk_data_t;
1799
1800 /**
1801  * Host Channel Specific Registers. <i>500h-5FCh</i>
1802  */
1803 typedef struct dwc_otg_hc_regs
1804 {
1805         /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
1806         volatile uint32_t hcchar;
1807         /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
1808         volatile uint32_t hcsplt;
1809         /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
1810         volatile uint32_t hcint;
1811         /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
1812         volatile uint32_t hcintmsk;
1813         /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
1814         volatile uint32_t hctsiz;
1815         /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
1816         volatile uint32_t hcdma;
1817         /** Reserved.  <i>Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch</i> */
1818         uint32_t reserved[2];
1819 } dwc_otg_hc_regs_t;
1820
1821 /**
1822  * This union represents the bit fields in the Host Channel Characteristics
1823  * Register. Read the register into the <i>d32</i> member then set/clear the
1824  * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1825  * hcchar register.
1826  */
1827 typedef union hcchar_data
1828 {
1829         /** raw register data */
1830         uint32_t d32;
1831
1832         /** register bits */
1833         struct
1834         {
1835                 /** Maximum packet size in bytes */
1836                 unsigned mps : 11;
1837
1838                 /** Endpoint number */
1839                 unsigned epnum : 4;
1840
1841                 /** 0: OUT, 1: IN */
1842                 unsigned epdir : 1;
1843
1844                 unsigned reserved : 1;
1845
1846                 /** 0: Full/high speed device, 1: Low speed device */
1847                 unsigned lspddev : 1;
1848
1849                 /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
1850                 unsigned eptype : 2;
1851
1852                 /** Packets per frame for periodic transfers. 0 is reserved. */
1853                 unsigned multicnt : 2;
1854
1855                 /** Device address */
1856                 unsigned devaddr : 7;
1857
1858                 /**
1859                  * Frame to transmit periodic transaction.
1860                  * 0: even, 1: odd
1861                  */
1862                 unsigned oddfrm : 1;
1863
1864                 /** Channel disable */
1865                 unsigned chdis : 1;
1866
1867                 /** Channel enable */
1868                 unsigned chen : 1;
1869         } b;
1870 } hcchar_data_t;
1871
1872 typedef union hcsplt_data
1873 {
1874         /** raw register data */
1875         uint32_t d32;
1876
1877         /** register bits */
1878         struct
1879         {
1880                 /** Port Address */
1881                 unsigned prtaddr : 7;
1882
1883                 /** Hub Address */
1884                 unsigned hubaddr : 7;
1885
1886                 /** Transaction Position */
1887                 unsigned xactpos : 2;
1888 #define DWC_HCSPLIT_XACTPOS_MID 0
1889 #define DWC_HCSPLIT_XACTPOS_END 1
1890 #define DWC_HCSPLIT_XACTPOS_BEGIN 2
1891 #define DWC_HCSPLIT_XACTPOS_ALL 3
1892
1893                 /** Do Complete Split */
1894                 unsigned compsplt : 1;
1895
1896                 /** Reserved */
1897                 unsigned reserved : 14;
1898
1899                 /** Split Enble */
1900                 unsigned spltena : 1;
1901         } b;
1902 } hcsplt_data_t;
1903
1904
1905 /**
1906  * This union represents the bit fields in the Host All Interrupt
1907  * Register.
1908  */
1909 typedef union hcint_data
1910 {
1911         /** raw register data */
1912         uint32_t d32;
1913         /** register bits */
1914         struct
1915         {
1916                 /** Transfer Complete */
1917                 unsigned xfercomp : 1;
1918                 /** Channel Halted */
1919                 unsigned chhltd : 1;
1920                 /** AHB Error */
1921                 unsigned ahberr : 1;
1922                 /** STALL Response Received */
1923                 unsigned stall : 1;
1924                 /** NAK Response Received */
1925                 unsigned nak : 1;
1926                 /** ACK Response Received */
1927                 unsigned ack : 1;
1928                 /** NYET Response Received */
1929                 unsigned nyet : 1;
1930                 /** Transaction Err */
1931                 unsigned xacterr : 1;
1932                 /** Babble Error */
1933                 unsigned bblerr : 1;
1934                 /** Frame Overrun */
1935                 unsigned frmovrun : 1;
1936                 /** Data Toggle Error */
1937                 unsigned datatglerr : 1;
1938                 /** Reserved */
1939                 unsigned reserved : 21;
1940         } b;
1941 } hcint_data_t;
1942
1943 /**
1944  * This union represents the bit fields in the Host Channel Transfer Size
1945  * Register. Read the register into the <i>d32</i> member then set/clear the
1946  * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1947  * hcchar register.
1948  */
1949 typedef union hctsiz_data
1950 {
1951         /** raw register data */
1952         uint32_t d32;
1953
1954         /** register bits */
1955         struct
1956         {
1957                 /** Total transfer size in bytes */
1958                 unsigned xfersize : 19;
1959
1960                 /** Data packets to transfer */
1961                 unsigned pktcnt : 10;
1962
1963                 /**
1964                  * Packet ID for next data packet
1965                  * 0: DATA0
1966                  * 1: DATA2
1967                  * 2: DATA1
1968                  * 3: MDATA (non-Control), SETUP (Control)
1969                  */
1970                 unsigned pid : 2;
1971 #define DWC_HCTSIZ_DATA0 0
1972 #define DWC_HCTSIZ_DATA1 2
1973 #define DWC_HCTSIZ_DATA2 1
1974 #define DWC_HCTSIZ_MDATA 3
1975 #define DWC_HCTSIZ_SETUP 3
1976
1977                 /** Do PING protocol when 1 */
1978                 unsigned dopng : 1;
1979         } b;
1980 } hctsiz_data_t;
1981
1982 /**
1983  * This union represents the bit fields in the Host Channel Interrupt Mask
1984  * Register. Read the register into the <i>d32</i> member then set/clear the
1985  * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
1986  * hcintmsk register.
1987  */
1988 typedef union hcintmsk_data
1989 {
1990         /** raw register data */
1991         uint32_t d32;
1992
1993         /** register bits */
1994         struct
1995         {
1996                 unsigned xfercompl : 1;
1997                 unsigned chhltd : 1;
1998                 unsigned ahberr : 1;
1999                 unsigned stall : 1;
2000                 unsigned nak : 1;
2001                 unsigned ack : 1;
2002                 unsigned nyet : 1;
2003                 unsigned xacterr : 1;
2004                 unsigned bblerr : 1;
2005                 unsigned frmovrun : 1;
2006                 unsigned datatglerr : 1;
2007                 unsigned reserved : 21;
2008         } b;
2009 } hcintmsk_data_t;
2010
2011 /** OTG Host Interface Structure.
2012  *
2013  * The OTG Host Interface Structure structure contains information
2014  * needed to manage the DWC_otg controller acting in host mode. It
2015  * represents the programming view of the host-specific aspects of the
2016  * controller.
2017  */
2018 typedef struct dwc_otg_host_if
2019 {
2020         /** Host Global Registers starting at offset 400h.*/
2021         dwc_otg_host_global_regs_t *host_global_regs;
2022 #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
2023
2024         /** Host Port 0 Control and Status Register */
2025         volatile uint32_t *hprt0;
2026 #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
2027
2028
2029         /** Host Channel Specific Registers at offsets 500h-5FCh. */
2030         dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
2031 #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
2032 #define DWC_OTG_CHAN_REGS_OFFSET 0x20
2033
2034
2035         /* Host configuration information */
2036         /** Number of Host Channels (range: 1-16) */
2037         uint8_t  num_host_channels;
2038         /** Periodic EPs supported (0: no, 1: yes) */
2039         uint8_t  perio_eps_supported;
2040         /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
2041         uint16_t perio_tx_fifo_size;
2042
2043 } dwc_otg_host_if_t;
2044
2045
2046 /**
2047  * This union represents the bit fields in the Power and Clock Gating Control
2048  * Register. Read the register into the <i>d32</i> member then set/clear the
2049  * bits using the <i>b</i>it elements.
2050  */
2051 typedef union pcgcctl_data
2052 {
2053         /** raw register data */
2054         uint32_t d32;
2055
2056         /** register bits */
2057         struct
2058         {
2059                 /** Stop Pclk */
2060                 unsigned stoppclk : 1;
2061                 /** Gate Hclk */
2062                 unsigned gatehclk : 1;
2063                 /** Power Clamp */
2064                 unsigned pwrclmp : 1;
2065                 /** Reset Power Down Modules */
2066                 unsigned rstpdwnmodule : 1;
2067                 /** PHY Suspended */
2068                 unsigned physuspended : 1;
2069
2070                 unsigned reserved : 27;
2071         } b;
2072 } pcgcctl_data_t;
2073
2074
2075 #endif