target/linux/ramips/files/arch/mips/pci/pci-rt288x.c

   1 #include <linux/types.h>
   2 #include <linux/pci.h>
   3 #include <linux/io.h>
   4 #include <linux/init.h>
   5
   6 #include <asm/mach-ralink/rt288x.h>
   7
   8 #define RT2880_PCI_SLOT1_BASE           0x20000000
   9 #define RALINK_PCI_BASE                 0xA0440000
  10 #define RT2880_PCI_PCICFG_ADDR          ((unsigned long*)(RALINK_PCI_BASE + 0x0000))
  11 #define RT2880_PCI_ARBCTL               ((unsigned long*)(RALINK_PCI_BASE + 0x0080))
  12 #define RT2880_PCI_BAR0SETUP_ADDR       ((unsigned long*)(RALINK_PCI_BASE + 0x0010))
  13 #define RT2880_PCI_CONFIG_ADDR          ((unsigned long*)(RALINK_PCI_BASE + 0x0020))
  14 #define RT2880_PCI_CONFIG_DATA          ((unsigned long*)(RALINK_PCI_BASE + 0x0024))
  15 #define RT2880_PCI_MEMBASE              ((unsigned long*)(RALINK_PCI_BASE + 0x0028))
  16 #define RT2880_PCI_IOBASE               ((unsigned long*)(RALINK_PCI_BASE + 0x002C))
  17 #define RT2880_PCI_IMBASEBAR0_ADDR      ((unsigned long*)(RALINK_PCI_BASE + 0x0018))
  18 #define RT2880_PCI_ID                   ((unsigned long*)(RALINK_PCI_BASE + 0x0030))
  19 #define RT2880_PCI_CLASS                ((unsigned long*)(RALINK_PCI_BASE + 0x0034))
  20 #define RT2880_PCI_SUBID                ((unsigned long*)(RALINK_PCI_BASE + 0x0038))
  21 #define RT2880_PCI_PCIMSK_ADDR          ((unsigned long*)(RALINK_PCI_BASE + 0x000C))
  22
  23 #define PCI_ACCESS_READ  0
  24 #define PCI_ACCESS_WRITE 1
  25
  26 static int config_access(unsigned char access_type, struct pci_bus *bus,
  27                          unsigned int devfn, unsigned char where, u32 *data)
  28 {
  29         unsigned int slot = PCI_SLOT(devfn);
  30         unsigned int address;
  31         u8 func = PCI_FUNC(devfn);
  32
  33         address = (bus->number << 16) | (slot << 11) | (func << 8) |
  34                   (where & 0xfc) | 0x80000000;
  35
  36         writel(address, RT2880_PCI_CONFIG_ADDR);
  37         if (access_type == PCI_ACCESS_WRITE)
  38                 writel(*data, RT2880_PCI_CONFIG_DATA);
  39         else
  40                 *data = readl(RT2880_PCI_CONFIG_DATA);
  41
  42         return 0;
  43 }
  44
  45 int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
  46                     int size, u32 *val)
  47 {
  48         u32 data = 0;
  49
  50         if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
  51                 return PCIBIOS_DEVICE_NOT_FOUND;
  52
  53         if (size == 1)
  54                 *val = (data >> ((where & 3) << 3)) & 0xff;
  55         else if (size == 2)
  56                 *val = (data >> ((where & 3) << 3)) & 0xffff;
  57         else
  58                 *val = data;
  59
  60         return PCIBIOS_SUCCESSFUL;
  61 }
  62
  63 int pci_config_write(struct pci_bus *bus, unsigned int devfn,
  64                      int where, int size, u32 val)
  65 {
  66         u32 data = 0;
  67
  68         if (size == 4) {
  69                 data = val;
  70         } else {
  71                 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
  72                         return PCIBIOS_DEVICE_NOT_FOUND;
  73                 if (size == 1)
  74                         data = (data & ~(0xff << ((where & 3) << 3))) |
  75                                (val << ((where & 3) << 3));
  76                 else if (size == 2)
  77                         data = (data & ~(0xffff << ((where & 3) << 3))) |
  78                                (val << ((where & 3) << 3));
  79         }
  80
  81         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
  82                 return PCIBIOS_DEVICE_NOT_FOUND;
  83
  84         return PCIBIOS_SUCCESSFUL;
  85 }
  86
  87 struct pci_ops rt2880_pci_ops = {
  88         .read   = pci_config_read,
  89         .write  = pci_config_write,
  90 };
  91
  92 static struct resource pci_io_resource = {
  93         .name   = "pci MEM space",
  94         .start  = 0x20000000,
  95         .end    = 0x2FFFFFFF,
  96         .flags  = IORESOURCE_MEM,
  97 };
  98
  99 static struct resource pci_mem_resource = {
 100         .name   = "pci IO space",
 101         .start  = 0x00460000,
 102         .end    = 0x0046FFFF,
 103         .flags  = IORESOURCE_IO,
 104 };
 105
 106 struct pci_controller rt2880_controller = {
 107         .pci_ops        = &rt2880_pci_ops,
 108         .mem_resource   = &pci_io_resource,
 109         .io_resource    = &pci_mem_resource,
 110         .mem_offset     = 0x00000000UL,
 111         .io_offset      = 0x00000000UL,
 112 };
 113
 114 void inline read_config(unsigned long bus, unsigned long dev,
 115                         unsigned long func, unsigned long reg,
 116                         unsigned long *val)
 117 {
 118         unsigned long address;
 119
 120         address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
 121                   0x80000000;
 122         writel(address, RT2880_PCI_CONFIG_ADDR);
 123         *val = readl(RT2880_PCI_CONFIG_DATA);
 124 }
 125
 126 void inline write_config(unsigned long bus, unsigned long dev,
 127                          unsigned long func, unsigned long reg,
 128                          unsigned long val)
 129 {
 130         unsigned long address;
 131
 132         address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
 133                   0x80000000;
 134         writel(address, RT2880_PCI_CONFIG_ADDR);
 135         writel(val, RT2880_PCI_CONFIG_DATA);
 136 }
 137
 138 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 139 {
 140         u16 cmd;
 141         unsigned long val;
 142         int irq = -1;
 143
 144         if (dev->bus->number != 0)
 145                 return 0;
 146
 147         switch (PCI_SLOT(dev->devfn)) {
 148         case 0x00:
 149                 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 150                 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 151                 break;
 152         case 0x11:
 153                 irq = RT288X_CPU_IRQ_PCI;
 154                 break;
 155         default:
 156                 printk("%s:%s[%d] trying to alloc unknown pci irq\n",
 157                        __FILE__, __func__, __LINE__);
 158                 BUG();
 159                 break;
 160         }
 161
 162         pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
 163         pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
 164         pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
 165         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 166                PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
 167                PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
 168         pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
 169         pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
 170                               dev->irq);
 171         return irq;
 172 }
 173
 174 int init_rt2880pci(void)
 175 {
 176         unsigned long val = 0;
 177         int i;
 178
 179         writel(0, RT2880_PCI_PCICFG_ADDR);
 180         for(i = 0; i < 0xfffff; i++) {}
 181
 182         writel(0x79, RT2880_PCI_ARBCTL);
 183         writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR);
 184         writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE);
 185         writel(0x00460000, RT2880_PCI_IOBASE);
 186         writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR);
 187         writel(0x08021814, RT2880_PCI_ID);
 188         writel(0x00800001, RT2880_PCI_CLASS);
 189         writel(0x28801814, RT2880_PCI_SUBID);
 190         writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR);
 191         write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 192         read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 193
 194         register_pci_controller(&rt2880_controller);
 195         return 0;
 196 }
 197
 198 int pcibios_plat_dev_init(struct pci_dev *dev)
 199 {
 200         return 0;
 201 }
 202
 203 struct pci_fixup pcibios_fixups[] = {
 204         {0}
 205 };
 206
 207 arch_initcall(init_rt2880pci);