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ralink: update ethernet driver to use new ralink_soc variable
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / esw_rt3052.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31
32 #include <asm/mach-ralink/ralink_regs.h>
33
34 #include "ralink_soc_eth.h"
35
36 #include <linux/ioport.h>
37 #include <linux/switch.h>
38 #include <linux/mii.h>
39
40 #include <ralink_regs.h>
41
42 #include <asm/mach-ralink/rt305x_esw_platform.h>
43
44 /*
45 * HW limitations for this switch:
46 * - No large frame support (PKT_MAX_LEN at most 1536)
47 * - Can't have untagged vlan and tagged vlan on one port at the same time,
48 * though this might be possible using the undocumented PPE.
49 */
50
51 #define RT305X_ESW_REG_ISR 0x00
52 #define RT305X_ESW_REG_IMR 0x04
53 #define RT305X_ESW_REG_FCT0 0x08
54 #define RT305X_ESW_REG_PFC1 0x14
55 #define RT305X_ESW_REG_ATS 0x24
56 #define RT305X_ESW_REG_ATS0 0x28
57 #define RT305X_ESW_REG_ATS1 0x2c
58 #define RT305X_ESW_REG_ATS2 0x30
59 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
60 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
61 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
62 #define RT305X_ESW_REG_POA 0x80
63 #define RT305X_ESW_REG_FPA 0x84
64 #define RT305X_ESW_REG_SOCPC 0x8c
65 #define RT305X_ESW_REG_POC0 0x90
66 #define RT305X_ESW_REG_POC1 0x94
67 #define RT305X_ESW_REG_POC2 0x98
68 #define RT305X_ESW_REG_SGC 0x9c
69 #define RT305X_ESW_REG_STRT 0xa0
70 #define RT305X_ESW_REG_PCR0 0xc0
71 #define RT305X_ESW_REG_PCR1 0xc4
72 #define RT305X_ESW_REG_FPA2 0xc8
73 #define RT305X_ESW_REG_FCT2 0xcc
74 #define RT305X_ESW_REG_SGC2 0xe4
75 #define RT305X_ESW_REG_P0LED 0xa4
76 #define RT305X_ESW_REG_P1LED 0xa8
77 #define RT305X_ESW_REG_P2LED 0xac
78 #define RT305X_ESW_REG_P3LED 0xb0
79 #define RT305X_ESW_REG_P4LED 0xb4
80 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
81 #define RT305X_ESW_REG_P1PC 0xec
82 #define RT305X_ESW_REG_P2PC 0xf0
83 #define RT305X_ESW_REG_P3PC 0xf4
84 #define RT305X_ESW_REG_P4PC 0xf8
85 #define RT305X_ESW_REG_P5PC 0xfc
86
87 #define RT305X_ESW_LED_LINK 0
88 #define RT305X_ESW_LED_100M 1
89 #define RT305X_ESW_LED_DUPLEX 2
90 #define RT305X_ESW_LED_ACTIVITY 3
91 #define RT305X_ESW_LED_COLLISION 4
92 #define RT305X_ESW_LED_LINKACT 5
93 #define RT305X_ESW_LED_DUPLCOLL 6
94 #define RT305X_ESW_LED_10MACT 7
95 #define RT305X_ESW_LED_100MACT 8
96 /* Additional led states not in datasheet: */
97 #define RT305X_ESW_LED_BLINK 10
98 #define RT305X_ESW_LED_ON 12
99
100 #define RT305X_ESW_LINK_S 25
101 #define RT305X_ESW_DUPLEX_S 9
102 #define RT305X_ESW_SPD_S 0
103
104 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
105 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
106 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
107
108 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
109
110 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
111 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
112
113 #define RT305X_ESW_PVIDC_PVID_M 0xfff
114 #define RT305X_ESW_PVIDC_PVID_S 12
115
116 #define RT305X_ESW_VLANI_VID_M 0xfff
117 #define RT305X_ESW_VLANI_VID_S 12
118
119 #define RT305X_ESW_VMSC_MSC_M 0xff
120 #define RT305X_ESW_VMSC_MSC_S 8
121
122 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
123 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
124 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
125 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
126
127 #define RT305X_ESW_POC0_EN_BP_S 0
128 #define RT305X_ESW_POC0_EN_FC_S 8
129 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
130 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
131 #define RT305X_ESW_POC0_DIS_PORT_S 23
132
133 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
134 #define RT305X_ESW_POC2_UNTAG_EN_S 0
135 #define RT305X_ESW_POC2_ENAGING_S 8
136 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
137
138 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
139 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
140 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
141 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
142
143 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
144 #define RT305X_ESW_PFC1_EN_VLAN_S 16
145 #define RT305X_ESW_PFC1_EN_TOS_S 24
146
147 #define RT305X_ESW_VLAN_NONE 0xfff
148
149 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
150 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
151
152 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
153 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
154
155 #define RT305X_ESW_POA_LINK_MASK 0x1f
156 #define RT305X_ESW_POA_LINK_SHIFT 25
157
158 #define RT305X_ESW_PORT_ST_CHG BIT(26)
159 #define RT305X_ESW_PORT0 0
160 #define RT305X_ESW_PORT1 1
161 #define RT305X_ESW_PORT2 2
162 #define RT305X_ESW_PORT3 3
163 #define RT305X_ESW_PORT4 4
164 #define RT305X_ESW_PORT5 5
165 #define RT305X_ESW_PORT6 6
166
167 #define RT305X_ESW_PORTS_NONE 0
168
169 #define RT305X_ESW_PMAP_LLLLLL 0x3f
170 #define RT305X_ESW_PMAP_LLLLWL 0x2f
171 #define RT305X_ESW_PMAP_WLLLLL 0x3e
172
173 #define RT305X_ESW_PORTS_INTERNAL \
174 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
175 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
176 BIT(RT305X_ESW_PORT4))
177
178 #define RT305X_ESW_PORTS_NOCPU \
179 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
180
181 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
182
183 #define RT305X_ESW_PORTS_ALL \
184 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
185
186 #define RT305X_ESW_NUM_VLANS 16
187 #define RT305X_ESW_NUM_VIDS 4096
188 #define RT305X_ESW_NUM_PORTS 7
189 #define RT305X_ESW_NUM_LANWAN 6
190 #define RT305X_ESW_NUM_LEDS 5
191
192 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
193 #define RT5350_EWS_REG_LED_POLARITY 0x168
194 #define RT5350_RESET_EPHY BIT(24)
195 #define SYSC_REG_RESET_CTRL 0x34
196
197 enum {
198 /* Global attributes. */
199 RT305X_ESW_ATTR_ENABLE_VLAN,
200 RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
201 RT305X_ESW_ATTR_BC_STATUS,
202 RT305X_ESW_ATTR_LED_FREQ,
203 /* Port attributes. */
204 RT305X_ESW_ATTR_PORT_DISABLE,
205 RT305X_ESW_ATTR_PORT_DOUBLETAG,
206 RT305X_ESW_ATTR_PORT_UNTAG,
207 RT305X_ESW_ATTR_PORT_LED,
208 RT305X_ESW_ATTR_PORT_LAN,
209 RT305X_ESW_ATTR_PORT_RECV_BAD,
210 RT305X_ESW_ATTR_PORT_RECV_GOOD,
211 RT5350_ESW_ATTR_PORT_TR_BAD,
212 RT5350_ESW_ATTR_PORT_TR_GOOD,
213 };
214
215 struct esw_port {
216 bool disable;
217 bool doubletag;
218 bool untag;
219 u8 led;
220 u16 pvid;
221 };
222
223 struct esw_vlan {
224 u8 ports;
225 u16 vid;
226 };
227
228 struct rt305x_esw {
229 struct device *dev;
230 void __iomem *base;
231 int irq;
232 const struct rt305x_esw_platform_data *pdata;
233 /* Protects against concurrent register rmw operations. */
234 spinlock_t reg_rw_lock;
235
236 unsigned char port_map;
237 unsigned int reg_initval_fct2;
238 unsigned int reg_initval_fpa2;
239 unsigned int reg_led_polarity;
240
241
242 struct switch_dev swdev;
243 bool global_vlan_enable;
244 bool alt_vlan_disable;
245 int bc_storm_protect;
246 int led_frequency;
247 struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
248 struct esw_port ports[RT305X_ESW_NUM_PORTS];
249
250 };
251
252 static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
253 {
254 __raw_writel(val, esw->base + reg);
255 }
256
257 static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
258 {
259 return __raw_readl(esw->base + reg);
260 }
261
262 static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
263 unsigned long val)
264 {
265 unsigned long t;
266
267 t = __raw_readl(esw->base + reg) & ~mask;
268 __raw_writel(t | val, esw->base + reg);
269 }
270
271 static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
272 unsigned long val)
273 {
274 unsigned long flags;
275
276 spin_lock_irqsave(&esw->reg_rw_lock, flags);
277 esw_rmw_raw(esw, reg, mask, val);
278 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
279 }
280
281 static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
282 u32 write_data)
283 {
284 unsigned long t_start = jiffies;
285 int ret = 0;
286
287 while (1) {
288 if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
289 RT305X_ESW_PCR1_WT_DONE))
290 break;
291 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
292 ret = 1;
293 goto out;
294 }
295 }
296
297 write_data &= 0xffff;
298 esw_w32(esw,
299 (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
300 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
301 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
302 RT305X_ESW_REG_PCR0);
303
304 t_start = jiffies;
305 while (1) {
306 if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
307 RT305X_ESW_PCR1_WT_DONE)
308 break;
309
310 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
311 ret = 1;
312 break;
313 }
314 }
315 out:
316 if (ret)
317 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
318 return ret;
319 }
320
321 static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
322 {
323 unsigned s;
324 unsigned val;
325
326 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
327 val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
328 val = (val >> s) & RT305X_ESW_VLANI_VID_M;
329
330 return val;
331 }
332
333 static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
334 {
335 unsigned s;
336
337 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
338 esw_rmw(esw,
339 RT305X_ESW_REG_VLANI(vlan / 2),
340 RT305X_ESW_VLANI_VID_M << s,
341 (vid & RT305X_ESW_VLANI_VID_M) << s);
342 }
343
344 static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
345 {
346 unsigned s, val;
347
348 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
349 val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
350 return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
351 }
352
353 static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
354 {
355 unsigned s;
356
357 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
358 esw_rmw(esw,
359 RT305X_ESW_REG_PVIDC(port / 2),
360 RT305X_ESW_PVIDC_PVID_M << s,
361 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
362 }
363
364 static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
365 {
366 unsigned s, val;
367
368 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
369 val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
370 val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
371
372 return val;
373 }
374
375 static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
376 {
377 unsigned s;
378
379 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
380 esw_rmw(esw,
381 RT305X_ESW_REG_VMSC(vlan / 4),
382 RT305X_ESW_VMSC_MSC_M << s,
383 (msc & RT305X_ESW_VMSC_MSC_M) << s);
384 }
385
386 static unsigned esw_get_port_disable(struct rt305x_esw *esw)
387 {
388 unsigned reg;
389 reg = esw_r32(esw, RT305X_ESW_REG_POC0);
390 return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
391 RT305X_ESW_POC0_DIS_PORT_M;
392 }
393
394 static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
395 {
396 unsigned old_mask;
397 unsigned enable_mask;
398 unsigned changed;
399 int i;
400
401 old_mask = esw_get_port_disable(esw);
402 changed = old_mask ^ disable_mask;
403 enable_mask = old_mask & disable_mask;
404
405 /* enable before writing to MII */
406 esw_rmw(esw, RT305X_ESW_REG_POC0,
407 (RT305X_ESW_POC0_DIS_PORT_M <<
408 RT305X_ESW_POC0_DIS_PORT_S),
409 enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
410
411 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
412 if (!(changed & (1 << i)))
413 continue;
414 if (disable_mask & (1 << i)) {
415 /* disable */
416 rt305x_mii_write(esw, i, MII_BMCR,
417 BMCR_PDOWN);
418 } else {
419 /* enable */
420 rt305x_mii_write(esw, i, MII_BMCR,
421 BMCR_FULLDPLX |
422 BMCR_ANENABLE |
423 BMCR_ANRESTART |
424 BMCR_SPEED100);
425 }
426 }
427
428 /* disable after writing to MII */
429 esw_rmw(esw, RT305X_ESW_REG_POC0,
430 (RT305X_ESW_POC0_DIS_PORT_M <<
431 RT305X_ESW_POC0_DIS_PORT_S),
432 disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
433 }
434
435 static void esw_set_gsc(struct rt305x_esw *esw)
436 {
437 esw_rmw(esw, RT305X_ESW_REG_SGC,
438 RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
439 esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
440 esw_rmw(esw, RT305X_ESW_REG_SGC,
441 RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
442 esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
443 }
444
445 static int esw_apply_config(struct switch_dev *dev);
446
447 static void esw_hw_init(struct rt305x_esw *esw)
448 {
449 int i;
450 u8 port_disable = 0;
451 u8 port_map = RT305X_ESW_PMAP_LLLLLL;
452
453 /* vodoo from original driver */
454 esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
455 esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
456 /* Port priority 1 for all ports, vlan enabled. */
457 esw_w32(esw, 0x00005555 |
458 (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
459 RT305X_ESW_REG_PFC1);
460
461 /* Enable Back Pressure, and Flow Control */
462 esw_w32(esw,
463 ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
464 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
465 RT305X_ESW_REG_POC0);
466
467 /* Enable Aging, and VLAN TAG removal */
468 esw_w32(esw,
469 ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
470 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
471 RT305X_ESW_REG_POC2);
472
473 if (esw->reg_initval_fct2)
474 esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
475 else
476 esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
477
478 /*
479 * 300s aging timer, max packet len 1536, broadcast storm prevention
480 * disabled, disable collision abort, mac xor48 hash, 10 packet back
481 * pressure jam, GMII disable was_transmit, back pressure disabled,
482 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
483 * ports.
484 */
485 esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
486
487 /* Setup SoC Port control register */
488 esw_w32(esw,
489 (RT305X_ESW_SOCPC_CRC_PADDING |
490 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
491 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
492 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
493 RT305X_ESW_REG_SOCPC);
494
495 if (esw->reg_initval_fpa2)
496 esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
497 else
498 esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
499 esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
500
501 /* Force Link/Activity on ports */
502 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
503 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
504 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
505 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
506 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
507
508 /* Copy disabled port configuration from bootloader setup */
509 port_disable = esw_get_port_disable(esw);
510 for (i = 0; i < 6; i++)
511 esw->ports[i].disable = (port_disable & (1 << i)) != 0;
512
513 if (ralink_soc == RT305X_SOC_RT3352) {
514 /* reset EPHY */
515 u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
516 rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
517 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
518
519 rt305x_mii_write(esw, 0, 31, 0x8000);
520 for (i = 0; i < 5; i++) {
521 if (esw->ports[i].disable) {
522 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
523 } else {
524 rt305x_mii_write(esw, i, MII_BMCR,
525 BMCR_FULLDPLX |
526 BMCR_ANENABLE |
527 BMCR_SPEED100);
528 }
529 /* TX10 waveform coefficient LSB=0 disable PHY */
530 rt305x_mii_write(esw, i, 26, 0x1601);
531 /* TX100/TX10 AD/DA current bias */
532 rt305x_mii_write(esw, i, 29, 0x7016);
533 /* TX100 slew rate control */
534 rt305x_mii_write(esw, i, 30, 0x0038);
535 }
536
537 /* select global register */
538 rt305x_mii_write(esw, 0, 31, 0x0);
539 /* enlarge agcsel threshold 3 and threshold 2 */
540 rt305x_mii_write(esw, 0, 1, 0x4a40);
541 /* enlarge agcsel threshold 5 and threshold 4 */
542 rt305x_mii_write(esw, 0, 2, 0x6254);
543 /* enlarge agcsel threshold */
544 rt305x_mii_write(esw, 0, 3, 0xa17f);
545 rt305x_mii_write(esw, 0,12, 0x7eaa);
546 /* longer TP_IDL tail length */
547 rt305x_mii_write(esw, 0, 14, 0x65);
548 /* increased squelch pulse count threshold. */
549 rt305x_mii_write(esw, 0, 16, 0x0684);
550 /* set TX10 signal amplitude threshold to minimum */
551 rt305x_mii_write(esw, 0, 17, 0x0fe0);
552 /* set squelch amplitude to higher threshold */
553 rt305x_mii_write(esw, 0, 18, 0x40ba);
554 /* tune TP_IDL tail and head waveform, enable power down slew rate control */
555 rt305x_mii_write(esw, 0, 22, 0x253f);
556 /* set PLL/Receive bias current are calibrated */
557 rt305x_mii_write(esw, 0, 27, 0x2fda);
558 /* change PLL/Receive bias current to internal(RT3350) */
559 rt305x_mii_write(esw, 0, 28, 0xc410);
560 /* change PLL bias current to internal(RT3052_MP3) */
561 rt305x_mii_write(esw, 0, 29, 0x598b);
562 /* select local register */
563 rt305x_mii_write(esw, 0, 31, 0x8000);
564 } else if (ralink_soc == RT305X_SOC_RT5350) {
565 /* reset EPHY */
566 u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
567 rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
568 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
569
570 /* set the led polarity */
571 esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
572
573 /* local registers */
574 rt305x_mii_write(esw, 0, 31, 0x8000);
575 for (i = 0; i < 5; i++) {
576 if (esw->ports[i].disable) {
577 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
578 } else {
579 rt305x_mii_write(esw, i, MII_BMCR,
580 BMCR_FULLDPLX |
581 BMCR_ANENABLE |
582 BMCR_SPEED100);
583 }
584 /* TX10 waveform coefficient LSB=0 disable PHY */
585 rt305x_mii_write(esw, i, 26, 0x1601);
586 /* TX100/TX10 AD/DA current bias */
587 rt305x_mii_write(esw, i, 29, 0x7015);
588 /* TX100 slew rate control */
589 rt305x_mii_write(esw, i, 30, 0x0038);
590 }
591
592 /* global registers */
593 rt305x_mii_write(esw, 0, 31, 0x0);
594 /* enlarge agcsel threshold 3 and threshold 2 */
595 rt305x_mii_write(esw, 0, 1, 0x4a40);
596 /* enlarge agcsel threshold 5 and threshold 4 */
597 rt305x_mii_write(esw, 0, 2, 0x6254);
598 /* enlarge agcsel threshold 6 */
599 rt305x_mii_write(esw, 0, 3, 0xa17f);
600 rt305x_mii_write(esw, 0, 12, 0x7eaa);
601 /* longer TP_IDL tail length */
602 rt305x_mii_write(esw, 0, 14, 0x65);
603 /* increased squelch pulse count threshold. */
604 rt305x_mii_write(esw, 0, 16, 0x0684);
605 /* set TX10 signal amplitude threshold to minimum */
606 rt305x_mii_write(esw, 0, 17, 0x0fe0);
607 /* set squelch amplitude to higher threshold */
608 rt305x_mii_write(esw, 0, 18, 0x40ba);
609 /* tune TP_IDL tail and head waveform, enable power down slew rate control */
610 rt305x_mii_write(esw, 0, 22, 0x253f);
611 /* set PLL/Receive bias current are calibrated */
612 rt305x_mii_write(esw, 0, 27, 0x2fda);
613 /* change PLL/Receive bias current to internal(RT3350) */
614 rt305x_mii_write(esw, 0, 28, 0xc410);
615 /* change PLL bias current to internal(RT3052_MP3) */
616 rt305x_mii_write(esw, 0, 29, 0x598b);
617 /* select local register */
618 rt305x_mii_write(esw, 0, 31, 0x8000);
619 } else if (ralink_soc == MT762X_SOC_MT7628AN) {
620 int i;
621 // u32 phy_val;
622 u32 val;
623
624 /* reset EPHY */
625 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
626 rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
627 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
628
629 rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
630 rt305x_mii_write(esw, 0, 26, 0x0020);
631
632 for (i = 0; i < 5; i++) {
633 rt305x_mii_write(esw, i, 31, 0x8000); //change L0 page
634 rt305x_mii_write(esw, i, 0, 0x3100);
635 // mii_mgr_read(i, 26, &phy_val);// EEE setting
636 // phy_val |= (1 << 5);
637 // rt305x_mii_write(esw, i, 26, phy_val);
638 rt305x_mii_write(esw, i, 30, 0xa000);
639 rt305x_mii_write(esw, i, 31, 0xa000); // change L2 page
640 rt305x_mii_write(esw, i, 16, 0x0606);
641 rt305x_mii_write(esw, i, 23, 0x0f0e);
642 rt305x_mii_write(esw, i, 24, 0x1610);
643 rt305x_mii_write(esw, i, 30, 0x1f15);
644 rt305x_mii_write(esw, i, 28, 0x6111);
645 // mii_mgr_read(i, 4, &phy_val);
646 // phy_val |= (1 << 10);
647 // rt305x_mii_write(esw, i, 4, phy_val);
648 rt305x_mii_write(esw, i, 31, 0x2000); // change G2 page
649 rt305x_mii_write(esw, i, 26, 0x0000);
650 }
651
652 //100Base AOI setting
653 rt305x_mii_write(esw, 0, 31, 0x5000); //change G5 page
654 rt305x_mii_write(esw, 0, 19, 0x004a);
655 rt305x_mii_write(esw, 0, 20, 0x015a);
656 rt305x_mii_write(esw, 0, 21, 0x00ee);
657 rt305x_mii_write(esw, 0, 22, 0x0033);
658 rt305x_mii_write(esw, 0, 23, 0x020a);
659 rt305x_mii_write(esw, 0, 24, 0x0000);
660 rt305x_mii_write(esw, 0, 25, 0x024a);
661 rt305x_mii_write(esw, 0, 26, 0x035a);
662 rt305x_mii_write(esw, 0, 27, 0x02ee);
663 rt305x_mii_write(esw, 0, 28, 0x0233);
664 rt305x_mii_write(esw, 0, 29, 0x000a);
665 rt305x_mii_write(esw, 0, 30, 0x0000);
666 } else {
667 rt305x_mii_write(esw, 0, 31, 0x8000);
668 for (i = 0; i < 5; i++) {
669 if (esw->ports[i].disable) {
670 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
671 } else {
672 rt305x_mii_write(esw, i, MII_BMCR,
673 BMCR_FULLDPLX |
674 BMCR_ANENABLE |
675 BMCR_SPEED100);
676 }
677 /* TX10 waveform coefficient */
678 rt305x_mii_write(esw, i, 26, 0x1601);
679 /* TX100/TX10 AD/DA current bias */
680 rt305x_mii_write(esw, i, 29, 0x7058);
681 /* TX100 slew rate control */
682 rt305x_mii_write(esw, i, 30, 0x0018);
683 }
684
685 /* PHY IOT */
686 /* select global register */
687 rt305x_mii_write(esw, 0, 31, 0x0);
688 /* tune TP_IDL tail and head waveform */
689 rt305x_mii_write(esw, 0, 22, 0x052f);
690 /* set TX10 signal amplitude threshold to minimum */
691 rt305x_mii_write(esw, 0, 17, 0x0fe0);
692 /* set squelch amplitude to higher threshold */
693 rt305x_mii_write(esw, 0, 18, 0x40ba);
694 /* longer TP_IDL tail length */
695 rt305x_mii_write(esw, 0, 14, 0x65);
696 /* select local register */
697 rt305x_mii_write(esw, 0, 31, 0x8000);
698 }
699
700 if (esw->port_map)
701 port_map = esw->port_map;
702 else
703 port_map = RT305X_ESW_PMAP_LLLLLL;
704
705 /*
706 * Unused HW feature, but still nice to be consistent here...
707 * This is also exported to userspace ('lan' attribute) so it's
708 * conveniently usable to decide which ports go into the wan vlan by
709 * default.
710 */
711 esw_rmw(esw, RT305X_ESW_REG_SGC2,
712 RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
713 port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
714
715 /* make the switch leds blink */
716 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
717 esw->ports[i].led = 0x05;
718
719 /* Apply the empty config. */
720 esw_apply_config(&esw->swdev);
721
722 /* Only unmask the port change interrupt */
723 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
724 }
725
726 static irqreturn_t esw_interrupt(int irq, void *_esw)
727 {
728 struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
729 u32 status;
730
731 status = esw_r32(esw, RT305X_ESW_REG_ISR);
732 if (status & RT305X_ESW_PORT_ST_CHG) {
733 u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
734 link >>= RT305X_ESW_POA_LINK_SHIFT;
735 link &= RT305X_ESW_POA_LINK_MASK;
736 dev_info(esw->dev, "link changed 0x%02X\n", link);
737 }
738 esw_w32(esw, status, RT305X_ESW_REG_ISR);
739
740 return IRQ_HANDLED;
741 }
742
743 static int esw_apply_config(struct switch_dev *dev)
744 {
745 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
746 int i;
747 u8 disable = 0;
748 u8 doubletag = 0;
749 u8 en_vlan = 0;
750 u8 untag = 0;
751
752 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
753 u32 vid, vmsc;
754 if (esw->global_vlan_enable) {
755 vid = esw->vlans[i].vid;
756 vmsc = esw->vlans[i].ports;
757 } else {
758 vid = RT305X_ESW_VLAN_NONE;
759 vmsc = RT305X_ESW_PORTS_NONE;
760 }
761 esw_set_vlan_id(esw, i, vid);
762 esw_set_vmsc(esw, i, vmsc);
763 }
764
765 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
766 u32 pvid;
767 disable |= esw->ports[i].disable << i;
768 if (esw->global_vlan_enable) {
769 doubletag |= esw->ports[i].doubletag << i;
770 en_vlan |= 1 << i;
771 untag |= esw->ports[i].untag << i;
772 pvid = esw->ports[i].pvid;
773 } else {
774 int x = esw->alt_vlan_disable ? 0 : 1;
775 doubletag |= x << i;
776 en_vlan |= x << i;
777 untag |= x << i;
778 pvid = 0;
779 }
780 esw_set_pvid(esw, i, pvid);
781 if (i < RT305X_ESW_NUM_LEDS)
782 esw_w32(esw, esw->ports[i].led,
783 RT305X_ESW_REG_P0LED + 4*i);
784 }
785
786 esw_set_gsc(esw);
787 esw_set_port_disable(esw, disable);
788 esw_rmw(esw, RT305X_ESW_REG_SGC2,
789 (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
790 RT305X_ESW_SGC2_DOUBLE_TAG_S),
791 doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
792 esw_rmw(esw, RT305X_ESW_REG_PFC1,
793 RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
794 en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
795 esw_rmw(esw, RT305X_ESW_REG_POC2,
796 RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
797 untag << RT305X_ESW_POC2_UNTAG_EN_S);
798
799 if (!esw->global_vlan_enable) {
800 /*
801 * Still need to put all ports into vlan 0 or they'll be
802 * isolated.
803 * NOTE: vlan 0 is special, no vlan tag is prepended
804 */
805 esw_set_vlan_id(esw, 0, 0);
806 esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
807 }
808
809 return 0;
810 }
811
812 static int esw_reset_switch(struct switch_dev *dev)
813 {
814 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
815
816 esw->global_vlan_enable = 0;
817 memset(esw->ports, 0, sizeof(esw->ports));
818 memset(esw->vlans, 0, sizeof(esw->vlans));
819 esw_hw_init(esw);
820
821 return 0;
822 }
823
824 static int esw_get_vlan_enable(struct switch_dev *dev,
825 const struct switch_attr *attr,
826 struct switch_val *val)
827 {
828 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
829
830 val->value.i = esw->global_vlan_enable;
831
832 return 0;
833 }
834
835 static int esw_set_vlan_enable(struct switch_dev *dev,
836 const struct switch_attr *attr,
837 struct switch_val *val)
838 {
839 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
840
841 esw->global_vlan_enable = val->value.i != 0;
842
843 return 0;
844 }
845
846 static int esw_get_alt_vlan_disable(struct switch_dev *dev,
847 const struct switch_attr *attr,
848 struct switch_val *val)
849 {
850 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
851
852 val->value.i = esw->alt_vlan_disable;
853
854 return 0;
855 }
856
857 static int esw_set_alt_vlan_disable(struct switch_dev *dev,
858 const struct switch_attr *attr,
859 struct switch_val *val)
860 {
861 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
862
863 esw->alt_vlan_disable = val->value.i != 0;
864
865 return 0;
866 }
867
868 static int
869 rt305x_esw_set_bc_status(struct switch_dev *dev,
870 const struct switch_attr *attr,
871 struct switch_val *val)
872 {
873 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
874
875 esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
876
877 return 0;
878 }
879
880 static int
881 rt305x_esw_get_bc_status(struct switch_dev *dev,
882 const struct switch_attr *attr,
883 struct switch_val *val)
884 {
885 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
886
887 val->value.i = esw->bc_storm_protect;
888
889 return 0;
890 }
891
892 static int
893 rt305x_esw_set_led_freq(struct switch_dev *dev,
894 const struct switch_attr *attr,
895 struct switch_val *val)
896 {
897 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
898
899 esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
900
901 return 0;
902 }
903
904 static int
905 rt305x_esw_get_led_freq(struct switch_dev *dev,
906 const struct switch_attr *attr,
907 struct switch_val *val)
908 {
909 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
910
911 val->value.i = esw->led_frequency;
912
913 return 0;
914 }
915
916 static int esw_get_port_link(struct switch_dev *dev,
917 int port,
918 struct switch_port_link *link)
919 {
920 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
921 u32 speed, poa;
922
923 if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
924 return -EINVAL;
925
926 poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
927
928 link->link = (poa >> RT305X_ESW_LINK_S) & 1;
929 link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
930 if (port < RT305X_ESW_NUM_LEDS) {
931 speed = (poa >> RT305X_ESW_SPD_S) & 1;
932 } else {
933 if (port == RT305X_ESW_NUM_PORTS - 1)
934 poa >>= 1;
935 speed = (poa >> RT305X_ESW_SPD_S) & 3;
936 }
937 switch (speed) {
938 case 0:
939 link->speed = SWITCH_PORT_SPEED_10;
940 break;
941 case 1:
942 link->speed = SWITCH_PORT_SPEED_100;
943 break;
944 case 2:
945 case 3: /* forced gige speed can be 2 or 3 */
946 link->speed = SWITCH_PORT_SPEED_1000;
947 break;
948 default:
949 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
950 break;
951 }
952
953 return 0;
954 }
955
956 static int esw_get_port_bool(struct switch_dev *dev,
957 const struct switch_attr *attr,
958 struct switch_val *val)
959 {
960 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
961 int idx = val->port_vlan;
962 u32 x, reg, shift;
963
964 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
965 return -EINVAL;
966
967 switch (attr->id) {
968 case RT305X_ESW_ATTR_PORT_DISABLE:
969 reg = RT305X_ESW_REG_POC0;
970 shift = RT305X_ESW_POC0_DIS_PORT_S;
971 break;
972 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
973 reg = RT305X_ESW_REG_SGC2;
974 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
975 break;
976 case RT305X_ESW_ATTR_PORT_UNTAG:
977 reg = RT305X_ESW_REG_POC2;
978 shift = RT305X_ESW_POC2_UNTAG_EN_S;
979 break;
980 case RT305X_ESW_ATTR_PORT_LAN:
981 reg = RT305X_ESW_REG_SGC2;
982 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
983 if (idx >= RT305X_ESW_NUM_LANWAN)
984 return -EINVAL;
985 break;
986 default:
987 return -EINVAL;
988 }
989
990 x = esw_r32(esw, reg);
991 val->value.i = (x >> (idx + shift)) & 1;
992
993 return 0;
994 }
995
996 static int esw_set_port_bool(struct switch_dev *dev,
997 const struct switch_attr *attr,
998 struct switch_val *val)
999 {
1000 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1001 int idx = val->port_vlan;
1002
1003 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1004 val->value.i < 0 || val->value.i > 1)
1005 return -EINVAL;
1006
1007 switch (attr->id) {
1008 case RT305X_ESW_ATTR_PORT_DISABLE:
1009 esw->ports[idx].disable = val->value.i;
1010 break;
1011 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1012 esw->ports[idx].doubletag = val->value.i;
1013 break;
1014 case RT305X_ESW_ATTR_PORT_UNTAG:
1015 esw->ports[idx].untag = val->value.i;
1016 break;
1017 default:
1018 return -EINVAL;
1019 }
1020
1021 return 0;
1022 }
1023
1024 static int esw_get_port_recv_badgood(struct switch_dev *dev,
1025 const struct switch_attr *attr,
1026 struct switch_val *val)
1027 {
1028 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1029 int idx = val->port_vlan;
1030 int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1031 u32 reg;
1032
1033 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1034 return -EINVAL;
1035 reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1036 val->value.i = (reg >> shift) & 0xffff;
1037
1038 return 0;
1039 }
1040
1041 static int
1042 esw_get_port_tr_badgood(struct switch_dev *dev,
1043 const struct switch_attr *attr,
1044 struct switch_val *val)
1045 {
1046 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1047
1048 int idx = val->port_vlan;
1049 int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1050 u32 reg;
1051
1052 if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN))
1053 return -EINVAL;
1054
1055 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1056 return -EINVAL;
1057
1058 reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1059 val->value.i = (reg >> shift) & 0xffff;
1060
1061 return 0;
1062 }
1063
1064 static int esw_get_port_led(struct switch_dev *dev,
1065 const struct switch_attr *attr,
1066 struct switch_val *val)
1067 {
1068 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1069 int idx = val->port_vlan;
1070
1071 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1072 idx >= RT305X_ESW_NUM_LEDS)
1073 return -EINVAL;
1074
1075 val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1076
1077 return 0;
1078 }
1079
1080 static int esw_set_port_led(struct switch_dev *dev,
1081 const struct switch_attr *attr,
1082 struct switch_val *val)
1083 {
1084 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1085 int idx = val->port_vlan;
1086
1087 if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1088 return -EINVAL;
1089
1090 esw->ports[idx].led = val->value.i;
1091
1092 return 0;
1093 }
1094
1095 static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1096 {
1097 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1098
1099 if (port >= RT305X_ESW_NUM_PORTS)
1100 return -EINVAL;
1101
1102 *val = esw_get_pvid(esw, port);
1103
1104 return 0;
1105 }
1106
1107 static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1108 {
1109 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1110
1111 if (port >= RT305X_ESW_NUM_PORTS)
1112 return -EINVAL;
1113
1114 esw->ports[port].pvid = val;
1115
1116 return 0;
1117 }
1118
1119 static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1120 {
1121 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1122 u32 vmsc, poc2;
1123 int vlan_idx = -1;
1124 int i;
1125
1126 val->len = 0;
1127
1128 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1129 return -EINVAL;
1130
1131 /* valid vlan? */
1132 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1133 if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1134 esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1135 vlan_idx = i;
1136 break;
1137 }
1138 }
1139
1140 if (vlan_idx == -1)
1141 return -EINVAL;
1142
1143 vmsc = esw_get_vmsc(esw, vlan_idx);
1144 poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1145
1146 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1147 struct switch_port *p;
1148 int port_mask = 1 << i;
1149
1150 if (!(vmsc & port_mask))
1151 continue;
1152
1153 p = &val->value.ports[val->len++];
1154 p->id = i;
1155 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1156 p->flags = 0;
1157 else
1158 p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1159 }
1160
1161 return 0;
1162 }
1163
1164 static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1165 {
1166 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1167 int ports;
1168 int vlan_idx = -1;
1169 int i;
1170
1171 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1172 val->len > RT305X_ESW_NUM_PORTS)
1173 return -EINVAL;
1174
1175 /* one of the already defined vlans? */
1176 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1177 if (esw->vlans[i].vid == val->port_vlan &&
1178 esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1179 vlan_idx = i;
1180 break;
1181 }
1182 }
1183
1184 /* select a free slot */
1185 for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1186 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1187 vlan_idx = i;
1188 }
1189
1190 /* bail if all slots are in use */
1191 if (vlan_idx == -1)
1192 return -EINVAL;
1193
1194 ports = RT305X_ESW_PORTS_NONE;
1195 for (i = 0; i < val->len; i++) {
1196 struct switch_port *p = &val->value.ports[i];
1197 int port_mask = 1 << p->id;
1198 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1199
1200 if (p->id >= RT305X_ESW_NUM_PORTS)
1201 return -EINVAL;
1202
1203 ports |= port_mask;
1204 esw->ports[p->id].untag = untagged;
1205 }
1206 esw->vlans[vlan_idx].ports = ports;
1207 if (ports == RT305X_ESW_PORTS_NONE)
1208 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1209 else
1210 esw->vlans[vlan_idx].vid = val->port_vlan;
1211
1212 return 0;
1213 }
1214
1215 static const struct switch_attr esw_global[] = {
1216 {
1217 .type = SWITCH_TYPE_INT,
1218 .name = "enable_vlan",
1219 .description = "VLAN mode (1:enabled)",
1220 .max = 1,
1221 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1222 .get = esw_get_vlan_enable,
1223 .set = esw_set_vlan_enable,
1224 },
1225 {
1226 .type = SWITCH_TYPE_INT,
1227 .name = "alternate_vlan_disable",
1228 .description = "Use en_vlan instead of doubletag to disable"
1229 " VLAN mode",
1230 .max = 1,
1231 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1232 .get = esw_get_alt_vlan_disable,
1233 .set = esw_set_alt_vlan_disable,
1234 },
1235 {
1236 .type = SWITCH_TYPE_INT,
1237 .name = "bc_storm_protect",
1238 .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1239 .max = 3,
1240 .id = RT305X_ESW_ATTR_BC_STATUS,
1241 .get = rt305x_esw_get_bc_status,
1242 .set = rt305x_esw_set_bc_status,
1243 },
1244 {
1245 .type = SWITCH_TYPE_INT,
1246 .name = "led_frequency",
1247 .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1248 .max = 3,
1249 .id = RT305X_ESW_ATTR_LED_FREQ,
1250 .get = rt305x_esw_get_led_freq,
1251 .set = rt305x_esw_set_led_freq,
1252 }
1253 };
1254
1255 static const struct switch_attr esw_port[] = {
1256 {
1257 .type = SWITCH_TYPE_INT,
1258 .name = "disable",
1259 .description = "Port state (1:disabled)",
1260 .max = 1,
1261 .id = RT305X_ESW_ATTR_PORT_DISABLE,
1262 .get = esw_get_port_bool,
1263 .set = esw_set_port_bool,
1264 },
1265 {
1266 .type = SWITCH_TYPE_INT,
1267 .name = "doubletag",
1268 .description = "Double tagging for incoming vlan packets "
1269 "(1:enabled)",
1270 .max = 1,
1271 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1272 .get = esw_get_port_bool,
1273 .set = esw_set_port_bool,
1274 },
1275 {
1276 .type = SWITCH_TYPE_INT,
1277 .name = "untag",
1278 .description = "Untag (1:strip outgoing vlan tag)",
1279 .max = 1,
1280 .id = RT305X_ESW_ATTR_PORT_UNTAG,
1281 .get = esw_get_port_bool,
1282 .set = esw_set_port_bool,
1283 },
1284 {
1285 .type = SWITCH_TYPE_INT,
1286 .name = "led",
1287 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1288 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1289 " 8:100mact, 10:blink, 11:off, 12:on)",
1290 .max = 15,
1291 .id = RT305X_ESW_ATTR_PORT_LED,
1292 .get = esw_get_port_led,
1293 .set = esw_set_port_led,
1294 },
1295 {
1296 .type = SWITCH_TYPE_INT,
1297 .name = "lan",
1298 .description = "HW port group (0:wan, 1:lan)",
1299 .max = 1,
1300 .id = RT305X_ESW_ATTR_PORT_LAN,
1301 .get = esw_get_port_bool,
1302 },
1303 {
1304 .type = SWITCH_TYPE_INT,
1305 .name = "recv_bad",
1306 .description = "Receive bad packet counter",
1307 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1308 .get = esw_get_port_recv_badgood,
1309 },
1310 {
1311 .type = SWITCH_TYPE_INT,
1312 .name = "recv_good",
1313 .description = "Receive good packet counter",
1314 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1315 .get = esw_get_port_recv_badgood,
1316 },
1317 {
1318 .type = SWITCH_TYPE_INT,
1319 .name = "tr_bad",
1320
1321 .description = "Transmit bad packet counter. rt5350 only",
1322 .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1323 .get = esw_get_port_tr_badgood,
1324 },
1325 {
1326 .type = SWITCH_TYPE_INT,
1327 .name = "tr_good",
1328
1329 .description = "Transmit good packet counter. rt5350 only",
1330 .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1331 .get = esw_get_port_tr_badgood,
1332 },
1333 };
1334
1335 static const struct switch_attr esw_vlan[] = {
1336 };
1337
1338 static const struct switch_dev_ops esw_ops = {
1339 .attr_global = {
1340 .attr = esw_global,
1341 .n_attr = ARRAY_SIZE(esw_global),
1342 },
1343 .attr_port = {
1344 .attr = esw_port,
1345 .n_attr = ARRAY_SIZE(esw_port),
1346 },
1347 .attr_vlan = {
1348 .attr = esw_vlan,
1349 .n_attr = ARRAY_SIZE(esw_vlan),
1350 },
1351 .get_vlan_ports = esw_get_vlan_ports,
1352 .set_vlan_ports = esw_set_vlan_ports,
1353 .get_port_pvid = esw_get_port_pvid,
1354 .set_port_pvid = esw_set_port_pvid,
1355 .get_port_link = esw_get_port_link,
1356 .apply_config = esw_apply_config,
1357 .reset_switch = esw_reset_switch,
1358 };
1359
1360 static struct rt305x_esw_platform_data rt3050_esw_data = {
1361 /* All ports are LAN ports. */
1362 .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1363 .reg_initval_fct2 = 0x00d6500c,
1364 /*
1365 * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1366 * turbo mii off, rgmi 3.3v off
1367 * port5: disabled
1368 * port6: enabled, gige, full-duplex, rx/tx-flow-control
1369 */
1370 .reg_initval_fpa2 = 0x3f502b28,
1371 };
1372
1373 static const struct of_device_id ralink_esw_match[] = {
1374 { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1375 {},
1376 };
1377 MODULE_DEVICE_TABLE(of, ralink_esw_match);
1378
1379 static int esw_probe(struct platform_device *pdev)
1380 {
1381 struct device_node *np = pdev->dev.of_node;
1382 const struct rt305x_esw_platform_data *pdata;
1383 const __be32 *port_map, *reg_init;
1384 struct rt305x_esw *esw;
1385 struct switch_dev *swdev;
1386 struct resource *res, *irq;
1387 int err;
1388
1389 pdata = pdev->dev.platform_data;
1390 if (!pdata) {
1391 const struct of_device_id *match;
1392 match = of_match_device(ralink_esw_match, &pdev->dev);
1393 if (match)
1394 pdata = (struct rt305x_esw_platform_data *) match->data;
1395 }
1396 if (!pdata)
1397 return -EINVAL;
1398
1399 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1400 if (!res) {
1401 dev_err(&pdev->dev, "no memory resource found\n");
1402 return -ENOMEM;
1403 }
1404
1405 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1406 if (!irq) {
1407 dev_err(&pdev->dev, "no irq resource found\n");
1408 return -ENOMEM;
1409 }
1410
1411 esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1412 if (!esw) {
1413 dev_err(&pdev->dev, "no memory for private data\n");
1414 return -ENOMEM;
1415 }
1416
1417 esw->dev = &pdev->dev;
1418 esw->irq = irq->start;
1419 esw->base = ioremap(res->start, resource_size(res));
1420 if (!esw->base) {
1421 dev_err(&pdev->dev, "ioremap failed\n");
1422 err = -ENOMEM;
1423 goto free_esw;
1424 }
1425
1426 port_map = of_get_property(np, "ralink,portmap", NULL);
1427 if (port_map)
1428 esw->port_map = be32_to_cpu(*port_map);
1429
1430 reg_init = of_get_property(np, "ralink,fct2", NULL);
1431 if (reg_init)
1432 esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1433
1434 reg_init = of_get_property(np, "ralink,fpa2", NULL);
1435 if (reg_init)
1436 esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1437
1438 reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1439 if (reg_init)
1440 esw->reg_led_polarity = be32_to_cpu(*reg_init);
1441
1442 swdev = &esw->swdev;
1443 swdev->of_node = pdev->dev.of_node;
1444 swdev->name = "rt305x-esw";
1445 swdev->alias = "rt305x";
1446 swdev->cpu_port = RT305X_ESW_PORT6;
1447 swdev->ports = RT305X_ESW_NUM_PORTS;
1448 swdev->vlans = RT305X_ESW_NUM_VIDS;
1449 swdev->ops = &esw_ops;
1450
1451 err = register_switch(swdev, NULL);
1452 if (err < 0) {
1453 dev_err(&pdev->dev, "register_switch failed\n");
1454 goto unmap_base;
1455 }
1456
1457 platform_set_drvdata(pdev, esw);
1458
1459 esw->pdata = pdata;
1460 spin_lock_init(&esw->reg_rw_lock);
1461
1462 esw_hw_init(esw);
1463
1464 esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1465 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1466 request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1467
1468 return 0;
1469
1470 unmap_base:
1471 iounmap(esw->base);
1472 free_esw:
1473 kfree(esw);
1474 return err;
1475 }
1476
1477 static int esw_remove(struct platform_device *pdev)
1478 {
1479 struct rt305x_esw *esw;
1480
1481 esw = platform_get_drvdata(pdev);
1482 if (esw) {
1483 unregister_switch(&esw->swdev);
1484 platform_set_drvdata(pdev, NULL);
1485 iounmap(esw->base);
1486 kfree(esw);
1487 }
1488
1489 return 0;
1490 }
1491
1492 static struct platform_driver esw_driver = {
1493 .probe = esw_probe,
1494 .remove = esw_remove,
1495 .driver = {
1496 .name = "rt305x-esw",
1497 .owner = THIS_MODULE,
1498 .of_match_table = ralink_esw_match,
1499 },
1500 };
1501
1502 int __init rtesw_init(void)
1503 {
1504 return platform_driver_register(&esw_driver);
1505 }
1506
1507 void rtesw_exit(void)
1508 {
1509 platform_driver_unregister(&esw_driver);
1510 }
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