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[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / esw_rt3052.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31
32 #include <asm/mach-ralink/ralink_regs.h>
33
34 #include "ralink_soc_eth.h"
35
36 #include <linux/ioport.h>
37 #include <linux/switch.h>
38 #include <linux/mii.h>
39
40 #include <ralink_regs.h>
41 #ifdef CONFIG_SOC_MT7620
42 static inline int soc_is_rt3352(void)
43 {
44 return 0;
45 }
46
47 static inline int soc_is_mt7628(void)
48 {
49 return 1;
50 }
51
52 static inline int soc_is_rt5350(void)
53 {
54 return 0;
55 }
56 #else
57 #include <asm/mach-ralink/rt305x.h>
58 static inline int soc_is_mt7628(void)
59 {
60 return 0;
61 }
62 #endif
63
64 #include <asm/mach-ralink/rt305x_esw_platform.h>
65
66 /*
67 * HW limitations for this switch:
68 * - No large frame support (PKT_MAX_LEN at most 1536)
69 * - Can't have untagged vlan and tagged vlan on one port at the same time,
70 * though this might be possible using the undocumented PPE.
71 */
72
73 #define RT305X_ESW_REG_ISR 0x00
74 #define RT305X_ESW_REG_IMR 0x04
75 #define RT305X_ESW_REG_FCT0 0x08
76 #define RT305X_ESW_REG_PFC1 0x14
77 #define RT305X_ESW_REG_ATS 0x24
78 #define RT305X_ESW_REG_ATS0 0x28
79 #define RT305X_ESW_REG_ATS1 0x2c
80 #define RT305X_ESW_REG_ATS2 0x30
81 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
82 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
83 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
84 #define RT305X_ESW_REG_POA 0x80
85 #define RT305X_ESW_REG_FPA 0x84
86 #define RT305X_ESW_REG_SOCPC 0x8c
87 #define RT305X_ESW_REG_POC0 0x90
88 #define RT305X_ESW_REG_POC1 0x94
89 #define RT305X_ESW_REG_POC2 0x98
90 #define RT305X_ESW_REG_SGC 0x9c
91 #define RT305X_ESW_REG_STRT 0xa0
92 #define RT305X_ESW_REG_PCR0 0xc0
93 #define RT305X_ESW_REG_PCR1 0xc4
94 #define RT305X_ESW_REG_FPA2 0xc8
95 #define RT305X_ESW_REG_FCT2 0xcc
96 #define RT305X_ESW_REG_SGC2 0xe4
97 #define RT305X_ESW_REG_P0LED 0xa4
98 #define RT305X_ESW_REG_P1LED 0xa8
99 #define RT305X_ESW_REG_P2LED 0xac
100 #define RT305X_ESW_REG_P3LED 0xb0
101 #define RT305X_ESW_REG_P4LED 0xb4
102 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
103 #define RT305X_ESW_REG_P1PC 0xec
104 #define RT305X_ESW_REG_P2PC 0xf0
105 #define RT305X_ESW_REG_P3PC 0xf4
106 #define RT305X_ESW_REG_P4PC 0xf8
107 #define RT305X_ESW_REG_P5PC 0xfc
108
109 #define RT305X_ESW_LED_LINK 0
110 #define RT305X_ESW_LED_100M 1
111 #define RT305X_ESW_LED_DUPLEX 2
112 #define RT305X_ESW_LED_ACTIVITY 3
113 #define RT305X_ESW_LED_COLLISION 4
114 #define RT305X_ESW_LED_LINKACT 5
115 #define RT305X_ESW_LED_DUPLCOLL 6
116 #define RT305X_ESW_LED_10MACT 7
117 #define RT305X_ESW_LED_100MACT 8
118 /* Additional led states not in datasheet: */
119 #define RT305X_ESW_LED_BLINK 10
120 #define RT305X_ESW_LED_ON 12
121
122 #define RT305X_ESW_LINK_S 25
123 #define RT305X_ESW_DUPLEX_S 9
124 #define RT305X_ESW_SPD_S 0
125
126 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
127 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
128 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
129
130 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
131
132 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
133 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
134
135 #define RT305X_ESW_PVIDC_PVID_M 0xfff
136 #define RT305X_ESW_PVIDC_PVID_S 12
137
138 #define RT305X_ESW_VLANI_VID_M 0xfff
139 #define RT305X_ESW_VLANI_VID_S 12
140
141 #define RT305X_ESW_VMSC_MSC_M 0xff
142 #define RT305X_ESW_VMSC_MSC_S 8
143
144 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
145 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
146 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
147 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
148
149 #define RT305X_ESW_POC0_EN_BP_S 0
150 #define RT305X_ESW_POC0_EN_FC_S 8
151 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
152 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
153 #define RT305X_ESW_POC0_DIS_PORT_S 23
154
155 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
156 #define RT305X_ESW_POC2_UNTAG_EN_S 0
157 #define RT305X_ESW_POC2_ENAGING_S 8
158 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
159
160 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
161 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
162 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
163 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
164
165 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
166 #define RT305X_ESW_PFC1_EN_VLAN_S 16
167 #define RT305X_ESW_PFC1_EN_TOS_S 24
168
169 #define RT305X_ESW_VLAN_NONE 0xfff
170
171 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
172 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
173
174 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
175 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
176
177 #define RT305X_ESW_POA_LINK_MASK 0x1f
178 #define RT305X_ESW_POA_LINK_SHIFT 25
179
180 #define RT305X_ESW_PORT_ST_CHG BIT(26)
181 #define RT305X_ESW_PORT0 0
182 #define RT305X_ESW_PORT1 1
183 #define RT305X_ESW_PORT2 2
184 #define RT305X_ESW_PORT3 3
185 #define RT305X_ESW_PORT4 4
186 #define RT305X_ESW_PORT5 5
187 #define RT305X_ESW_PORT6 6
188
189 #define RT305X_ESW_PORTS_NONE 0
190
191 #define RT305X_ESW_PMAP_LLLLLL 0x3f
192 #define RT305X_ESW_PMAP_LLLLWL 0x2f
193 #define RT305X_ESW_PMAP_WLLLLL 0x3e
194
195 #define RT305X_ESW_PORTS_INTERNAL \
196 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
197 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
198 BIT(RT305X_ESW_PORT4))
199
200 #define RT305X_ESW_PORTS_NOCPU \
201 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
202
203 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
204
205 #define RT305X_ESW_PORTS_ALL \
206 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
207
208 #define RT305X_ESW_NUM_VLANS 16
209 #define RT305X_ESW_NUM_VIDS 4096
210 #define RT305X_ESW_NUM_PORTS 7
211 #define RT305X_ESW_NUM_LANWAN 6
212 #define RT305X_ESW_NUM_LEDS 5
213
214 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
215 #define RT5350_EWS_REG_LED_POLARITY 0x168
216 #define RT5350_RESET_EPHY BIT(24)
217 #define SYSC_REG_RESET_CTRL 0x34
218
219 enum {
220 /* Global attributes. */
221 RT305X_ESW_ATTR_ENABLE_VLAN,
222 RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
223 RT305X_ESW_ATTR_BC_STATUS,
224 RT305X_ESW_ATTR_LED_FREQ,
225 /* Port attributes. */
226 RT305X_ESW_ATTR_PORT_DISABLE,
227 RT305X_ESW_ATTR_PORT_DOUBLETAG,
228 RT305X_ESW_ATTR_PORT_UNTAG,
229 RT305X_ESW_ATTR_PORT_LED,
230 RT305X_ESW_ATTR_PORT_LAN,
231 RT305X_ESW_ATTR_PORT_RECV_BAD,
232 RT305X_ESW_ATTR_PORT_RECV_GOOD,
233 RT5350_ESW_ATTR_PORT_TR_BAD,
234 RT5350_ESW_ATTR_PORT_TR_GOOD,
235 };
236
237 struct esw_port {
238 bool disable;
239 bool doubletag;
240 bool untag;
241 u8 led;
242 u16 pvid;
243 };
244
245 struct esw_vlan {
246 u8 ports;
247 u16 vid;
248 };
249
250 struct rt305x_esw {
251 struct device *dev;
252 void __iomem *base;
253 int irq;
254 const struct rt305x_esw_platform_data *pdata;
255 /* Protects against concurrent register rmw operations. */
256 spinlock_t reg_rw_lock;
257
258 unsigned char port_map;
259 unsigned int reg_initval_fct2;
260 unsigned int reg_initval_fpa2;
261 unsigned int reg_led_polarity;
262
263
264 struct switch_dev swdev;
265 bool global_vlan_enable;
266 bool alt_vlan_disable;
267 int bc_storm_protect;
268 int led_frequency;
269 struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
270 struct esw_port ports[RT305X_ESW_NUM_PORTS];
271
272 };
273
274 static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
275 {
276 __raw_writel(val, esw->base + reg);
277 }
278
279 static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
280 {
281 return __raw_readl(esw->base + reg);
282 }
283
284 static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
285 unsigned long val)
286 {
287 unsigned long t;
288
289 t = __raw_readl(esw->base + reg) & ~mask;
290 __raw_writel(t | val, esw->base + reg);
291 }
292
293 static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
294 unsigned long val)
295 {
296 unsigned long flags;
297
298 spin_lock_irqsave(&esw->reg_rw_lock, flags);
299 esw_rmw_raw(esw, reg, mask, val);
300 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
301 }
302
303 static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
304 u32 write_data)
305 {
306 unsigned long t_start = jiffies;
307 int ret = 0;
308
309 while (1) {
310 if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
311 RT305X_ESW_PCR1_WT_DONE))
312 break;
313 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
314 ret = 1;
315 goto out;
316 }
317 }
318
319 write_data &= 0xffff;
320 esw_w32(esw,
321 (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
322 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
323 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
324 RT305X_ESW_REG_PCR0);
325
326 t_start = jiffies;
327 while (1) {
328 if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
329 RT305X_ESW_PCR1_WT_DONE)
330 break;
331
332 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
333 ret = 1;
334 break;
335 }
336 }
337 out:
338 if (ret)
339 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
340 return ret;
341 }
342
343 static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
344 {
345 unsigned s;
346 unsigned val;
347
348 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
349 val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
350 val = (val >> s) & RT305X_ESW_VLANI_VID_M;
351
352 return val;
353 }
354
355 static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
356 {
357 unsigned s;
358
359 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
360 esw_rmw(esw,
361 RT305X_ESW_REG_VLANI(vlan / 2),
362 RT305X_ESW_VLANI_VID_M << s,
363 (vid & RT305X_ESW_VLANI_VID_M) << s);
364 }
365
366 static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
367 {
368 unsigned s, val;
369
370 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
371 val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
372 return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
373 }
374
375 static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
376 {
377 unsigned s;
378
379 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
380 esw_rmw(esw,
381 RT305X_ESW_REG_PVIDC(port / 2),
382 RT305X_ESW_PVIDC_PVID_M << s,
383 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
384 }
385
386 static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
387 {
388 unsigned s, val;
389
390 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
391 val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
392 val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
393
394 return val;
395 }
396
397 static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
398 {
399 unsigned s;
400
401 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
402 esw_rmw(esw,
403 RT305X_ESW_REG_VMSC(vlan / 4),
404 RT305X_ESW_VMSC_MSC_M << s,
405 (msc & RT305X_ESW_VMSC_MSC_M) << s);
406 }
407
408 static unsigned esw_get_port_disable(struct rt305x_esw *esw)
409 {
410 unsigned reg;
411 reg = esw_r32(esw, RT305X_ESW_REG_POC0);
412 return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
413 RT305X_ESW_POC0_DIS_PORT_M;
414 }
415
416 static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
417 {
418 unsigned old_mask;
419 unsigned enable_mask;
420 unsigned changed;
421 int i;
422
423 old_mask = esw_get_port_disable(esw);
424 changed = old_mask ^ disable_mask;
425 enable_mask = old_mask & disable_mask;
426
427 /* enable before writing to MII */
428 esw_rmw(esw, RT305X_ESW_REG_POC0,
429 (RT305X_ESW_POC0_DIS_PORT_M <<
430 RT305X_ESW_POC0_DIS_PORT_S),
431 enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
432
433 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
434 if (!(changed & (1 << i)))
435 continue;
436 if (disable_mask & (1 << i)) {
437 /* disable */
438 rt305x_mii_write(esw, i, MII_BMCR,
439 BMCR_PDOWN);
440 } else {
441 /* enable */
442 rt305x_mii_write(esw, i, MII_BMCR,
443 BMCR_FULLDPLX |
444 BMCR_ANENABLE |
445 BMCR_ANRESTART |
446 BMCR_SPEED100);
447 }
448 }
449
450 /* disable after writing to MII */
451 esw_rmw(esw, RT305X_ESW_REG_POC0,
452 (RT305X_ESW_POC0_DIS_PORT_M <<
453 RT305X_ESW_POC0_DIS_PORT_S),
454 disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
455 }
456
457 static void esw_set_gsc(struct rt305x_esw *esw)
458 {
459 esw_rmw(esw, RT305X_ESW_REG_SGC,
460 RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
461 esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
462 esw_rmw(esw, RT305X_ESW_REG_SGC,
463 RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
464 esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
465 }
466
467 static int esw_apply_config(struct switch_dev *dev);
468
469 static void esw_hw_init(struct rt305x_esw *esw)
470 {
471 int i;
472 u8 port_disable = 0;
473 u8 port_map = RT305X_ESW_PMAP_LLLLLL;
474
475 /* vodoo from original driver */
476 esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
477 esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
478 /* Port priority 1 for all ports, vlan enabled. */
479 esw_w32(esw, 0x00005555 |
480 (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
481 RT305X_ESW_REG_PFC1);
482
483 /* Enable Back Pressure, and Flow Control */
484 esw_w32(esw,
485 ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
486 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
487 RT305X_ESW_REG_POC0);
488
489 /* Enable Aging, and VLAN TAG removal */
490 esw_w32(esw,
491 ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
492 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
493 RT305X_ESW_REG_POC2);
494
495 if (esw->reg_initval_fct2)
496 esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
497 else
498 esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
499
500 /*
501 * 300s aging timer, max packet len 1536, broadcast storm prevention
502 * disabled, disable collision abort, mac xor48 hash, 10 packet back
503 * pressure jam, GMII disable was_transmit, back pressure disabled,
504 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
505 * ports.
506 */
507 esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
508
509 /* Setup SoC Port control register */
510 esw_w32(esw,
511 (RT305X_ESW_SOCPC_CRC_PADDING |
512 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
513 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
514 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
515 RT305X_ESW_REG_SOCPC);
516
517 if (esw->reg_initval_fpa2)
518 esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
519 else
520 esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
521 esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
522
523 /* Force Link/Activity on ports */
524 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
525 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
526 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
527 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
528 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
529
530 /* Copy disabled port configuration from bootloader setup */
531 port_disable = esw_get_port_disable(esw);
532 for (i = 0; i < 6; i++)
533 esw->ports[i].disable = (port_disable & (1 << i)) != 0;
534
535 if (soc_is_rt3352()) {
536 /* reset EPHY */
537 u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
538 rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
539 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
540
541 rt305x_mii_write(esw, 0, 31, 0x8000);
542 for (i = 0; i < 5; i++) {
543 if (esw->ports[i].disable) {
544 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
545 } else {
546 rt305x_mii_write(esw, i, MII_BMCR,
547 BMCR_FULLDPLX |
548 BMCR_ANENABLE |
549 BMCR_SPEED100);
550 }
551 /* TX10 waveform coefficient LSB=0 disable PHY */
552 rt305x_mii_write(esw, i, 26, 0x1601);
553 /* TX100/TX10 AD/DA current bias */
554 rt305x_mii_write(esw, i, 29, 0x7016);
555 /* TX100 slew rate control */
556 rt305x_mii_write(esw, i, 30, 0x0038);
557 }
558
559 /* select global register */
560 rt305x_mii_write(esw, 0, 31, 0x0);
561 /* enlarge agcsel threshold 3 and threshold 2 */
562 rt305x_mii_write(esw, 0, 1, 0x4a40);
563 /* enlarge agcsel threshold 5 and threshold 4 */
564 rt305x_mii_write(esw, 0, 2, 0x6254);
565 /* enlarge agcsel threshold */
566 rt305x_mii_write(esw, 0, 3, 0xa17f);
567 rt305x_mii_write(esw, 0,12, 0x7eaa);
568 /* longer TP_IDL tail length */
569 rt305x_mii_write(esw, 0, 14, 0x65);
570 /* increased squelch pulse count threshold. */
571 rt305x_mii_write(esw, 0, 16, 0x0684);
572 /* set TX10 signal amplitude threshold to minimum */
573 rt305x_mii_write(esw, 0, 17, 0x0fe0);
574 /* set squelch amplitude to higher threshold */
575 rt305x_mii_write(esw, 0, 18, 0x40ba);
576 /* tune TP_IDL tail and head waveform, enable power down slew rate control */
577 rt305x_mii_write(esw, 0, 22, 0x253f);
578 /* set PLL/Receive bias current are calibrated */
579 rt305x_mii_write(esw, 0, 27, 0x2fda);
580 /* change PLL/Receive bias current to internal(RT3350) */
581 rt305x_mii_write(esw, 0, 28, 0xc410);
582 /* change PLL bias current to internal(RT3052_MP3) */
583 rt305x_mii_write(esw, 0, 29, 0x598b);
584 /* select local register */
585 rt305x_mii_write(esw, 0, 31, 0x8000);
586 } else if (soc_is_rt5350()) {
587 /* reset EPHY */
588 u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
589 rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
590 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
591
592 /* set the led polarity */
593 esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
594
595 /* local registers */
596 rt305x_mii_write(esw, 0, 31, 0x8000);
597 for (i = 0; i < 5; i++) {
598 if (esw->ports[i].disable) {
599 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
600 } else {
601 rt305x_mii_write(esw, i, MII_BMCR,
602 BMCR_FULLDPLX |
603 BMCR_ANENABLE |
604 BMCR_SPEED100);
605 }
606 /* TX10 waveform coefficient LSB=0 disable PHY */
607 rt305x_mii_write(esw, i, 26, 0x1601);
608 /* TX100/TX10 AD/DA current bias */
609 rt305x_mii_write(esw, i, 29, 0x7015);
610 /* TX100 slew rate control */
611 rt305x_mii_write(esw, i, 30, 0x0038);
612 }
613
614 /* global registers */
615 rt305x_mii_write(esw, 0, 31, 0x0);
616 /* enlarge agcsel threshold 3 and threshold 2 */
617 rt305x_mii_write(esw, 0, 1, 0x4a40);
618 /* enlarge agcsel threshold 5 and threshold 4 */
619 rt305x_mii_write(esw, 0, 2, 0x6254);
620 /* enlarge agcsel threshold 6 */
621 rt305x_mii_write(esw, 0, 3, 0xa17f);
622 rt305x_mii_write(esw, 0, 12, 0x7eaa);
623 /* longer TP_IDL tail length */
624 rt305x_mii_write(esw, 0, 14, 0x65);
625 /* increased squelch pulse count threshold. */
626 rt305x_mii_write(esw, 0, 16, 0x0684);
627 /* set TX10 signal amplitude threshold to minimum */
628 rt305x_mii_write(esw, 0, 17, 0x0fe0);
629 /* set squelch amplitude to higher threshold */
630 rt305x_mii_write(esw, 0, 18, 0x40ba);
631 /* tune TP_IDL tail and head waveform, enable power down slew rate control */
632 rt305x_mii_write(esw, 0, 22, 0x253f);
633 /* set PLL/Receive bias current are calibrated */
634 rt305x_mii_write(esw, 0, 27, 0x2fda);
635 /* change PLL/Receive bias current to internal(RT3350) */
636 rt305x_mii_write(esw, 0, 28, 0xc410);
637 /* change PLL bias current to internal(RT3052_MP3) */
638 rt305x_mii_write(esw, 0, 29, 0x598b);
639 /* select local register */
640 rt305x_mii_write(esw, 0, 31, 0x8000);
641 } else if (soc_is_mt7628()) {
642 int i;
643 u32 phy_val;
644 u32 val;
645
646 /* reset EPHY */
647 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
648 rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
649 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
650
651 rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
652 rt305x_mii_write(esw, 0, 26, 0x0020);
653
654 for (i = 0; i < 5; i++) {
655 rt305x_mii_write(esw, i, 31, 0x8000); //change L0 page
656 rt305x_mii_write(esw, i, 0, 0x3100);
657 // mii_mgr_read(i, 26, &phy_val);// EEE setting
658 // phy_val |= (1 << 5);
659 // rt305x_mii_write(esw, i, 26, phy_val);
660 rt305x_mii_write(esw, i, 30, 0xa000);
661 rt305x_mii_write(esw, i, 31, 0xa000); // change L2 page
662 rt305x_mii_write(esw, i, 16, 0x0606);
663 rt305x_mii_write(esw, i, 23, 0x0f0e);
664 rt305x_mii_write(esw, i, 24, 0x1610);
665 rt305x_mii_write(esw, i, 30, 0x1f15);
666 rt305x_mii_write(esw, i, 28, 0x6111);
667 // mii_mgr_read(i, 4, &phy_val);
668 // phy_val |= (1 << 10);
669 // rt305x_mii_write(esw, i, 4, phy_val);
670 rt305x_mii_write(esw, i, 31, 0x2000); // change G2 page
671 rt305x_mii_write(esw, i, 26, 0x0000);
672 }
673
674 //100Base AOI setting
675 rt305x_mii_write(esw, 0, 31, 0x5000); //change G5 page
676 rt305x_mii_write(esw, 0, 19, 0x004a);
677 rt305x_mii_write(esw, 0, 20, 0x015a);
678 rt305x_mii_write(esw, 0, 21, 0x00ee);
679 rt305x_mii_write(esw, 0, 22, 0x0033);
680 rt305x_mii_write(esw, 0, 23, 0x020a);
681 rt305x_mii_write(esw, 0, 24, 0x0000);
682 rt305x_mii_write(esw, 0, 25, 0x024a);
683 rt305x_mii_write(esw, 0, 26, 0x035a);
684 rt305x_mii_write(esw, 0, 27, 0x02ee);
685 rt305x_mii_write(esw, 0, 28, 0x0233);
686 rt305x_mii_write(esw, 0, 29, 0x000a);
687 rt305x_mii_write(esw, 0, 30, 0x0000);
688 } else {
689 rt305x_mii_write(esw, 0, 31, 0x8000);
690 for (i = 0; i < 5; i++) {
691 if (esw->ports[i].disable) {
692 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
693 } else {
694 rt305x_mii_write(esw, i, MII_BMCR,
695 BMCR_FULLDPLX |
696 BMCR_ANENABLE |
697 BMCR_SPEED100);
698 }
699 /* TX10 waveform coefficient */
700 rt305x_mii_write(esw, i, 26, 0x1601);
701 /* TX100/TX10 AD/DA current bias */
702 rt305x_mii_write(esw, i, 29, 0x7058);
703 /* TX100 slew rate control */
704 rt305x_mii_write(esw, i, 30, 0x0018);
705 }
706
707 /* PHY IOT */
708 /* select global register */
709 rt305x_mii_write(esw, 0, 31, 0x0);
710 /* tune TP_IDL tail and head waveform */
711 rt305x_mii_write(esw, 0, 22, 0x052f);
712 /* set TX10 signal amplitude threshold to minimum */
713 rt305x_mii_write(esw, 0, 17, 0x0fe0);
714 /* set squelch amplitude to higher threshold */
715 rt305x_mii_write(esw, 0, 18, 0x40ba);
716 /* longer TP_IDL tail length */
717 rt305x_mii_write(esw, 0, 14, 0x65);
718 /* select local register */
719 rt305x_mii_write(esw, 0, 31, 0x8000);
720 }
721
722 if (esw->port_map)
723 port_map = esw->port_map;
724 else
725 port_map = RT305X_ESW_PMAP_LLLLLL;
726
727 /*
728 * Unused HW feature, but still nice to be consistent here...
729 * This is also exported to userspace ('lan' attribute) so it's
730 * conveniently usable to decide which ports go into the wan vlan by
731 * default.
732 */
733 esw_rmw(esw, RT305X_ESW_REG_SGC2,
734 RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
735 port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
736
737 /* make the switch leds blink */
738 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
739 esw->ports[i].led = 0x05;
740
741 /* Apply the empty config. */
742 esw_apply_config(&esw->swdev);
743
744 /* Only unmask the port change interrupt */
745 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
746 }
747
748 static irqreturn_t esw_interrupt(int irq, void *_esw)
749 {
750 struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
751 u32 status;
752
753 status = esw_r32(esw, RT305X_ESW_REG_ISR);
754 if (status & RT305X_ESW_PORT_ST_CHG) {
755 u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
756 link >>= RT305X_ESW_POA_LINK_SHIFT;
757 link &= RT305X_ESW_POA_LINK_MASK;
758 dev_info(esw->dev, "link changed 0x%02X\n", link);
759 }
760 esw_w32(esw, status, RT305X_ESW_REG_ISR);
761
762 return IRQ_HANDLED;
763 }
764
765 static int esw_apply_config(struct switch_dev *dev)
766 {
767 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
768 int i;
769 u8 disable = 0;
770 u8 doubletag = 0;
771 u8 en_vlan = 0;
772 u8 untag = 0;
773
774 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
775 u32 vid, vmsc;
776 if (esw->global_vlan_enable) {
777 vid = esw->vlans[i].vid;
778 vmsc = esw->vlans[i].ports;
779 } else {
780 vid = RT305X_ESW_VLAN_NONE;
781 vmsc = RT305X_ESW_PORTS_NONE;
782 }
783 esw_set_vlan_id(esw, i, vid);
784 esw_set_vmsc(esw, i, vmsc);
785 }
786
787 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
788 u32 pvid;
789 disable |= esw->ports[i].disable << i;
790 if (esw->global_vlan_enable) {
791 doubletag |= esw->ports[i].doubletag << i;
792 en_vlan |= 1 << i;
793 untag |= esw->ports[i].untag << i;
794 pvid = esw->ports[i].pvid;
795 } else {
796 int x = esw->alt_vlan_disable ? 0 : 1;
797 doubletag |= x << i;
798 en_vlan |= x << i;
799 untag |= x << i;
800 pvid = 0;
801 }
802 esw_set_pvid(esw, i, pvid);
803 if (i < RT305X_ESW_NUM_LEDS)
804 esw_w32(esw, esw->ports[i].led,
805 RT305X_ESW_REG_P0LED + 4*i);
806 }
807
808 esw_set_gsc(esw);
809 esw_set_port_disable(esw, disable);
810 esw_rmw(esw, RT305X_ESW_REG_SGC2,
811 (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
812 RT305X_ESW_SGC2_DOUBLE_TAG_S),
813 doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
814 esw_rmw(esw, RT305X_ESW_REG_PFC1,
815 RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
816 en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
817 esw_rmw(esw, RT305X_ESW_REG_POC2,
818 RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
819 untag << RT305X_ESW_POC2_UNTAG_EN_S);
820
821 if (!esw->global_vlan_enable) {
822 /*
823 * Still need to put all ports into vlan 0 or they'll be
824 * isolated.
825 * NOTE: vlan 0 is special, no vlan tag is prepended
826 */
827 esw_set_vlan_id(esw, 0, 0);
828 esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
829 }
830
831 return 0;
832 }
833
834 static int esw_reset_switch(struct switch_dev *dev)
835 {
836 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
837
838 esw->global_vlan_enable = 0;
839 memset(esw->ports, 0, sizeof(esw->ports));
840 memset(esw->vlans, 0, sizeof(esw->vlans));
841 esw_hw_init(esw);
842
843 return 0;
844 }
845
846 static int esw_get_vlan_enable(struct switch_dev *dev,
847 const struct switch_attr *attr,
848 struct switch_val *val)
849 {
850 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
851
852 val->value.i = esw->global_vlan_enable;
853
854 return 0;
855 }
856
857 static int esw_set_vlan_enable(struct switch_dev *dev,
858 const struct switch_attr *attr,
859 struct switch_val *val)
860 {
861 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
862
863 esw->global_vlan_enable = val->value.i != 0;
864
865 return 0;
866 }
867
868 static int esw_get_alt_vlan_disable(struct switch_dev *dev,
869 const struct switch_attr *attr,
870 struct switch_val *val)
871 {
872 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
873
874 val->value.i = esw->alt_vlan_disable;
875
876 return 0;
877 }
878
879 static int esw_set_alt_vlan_disable(struct switch_dev *dev,
880 const struct switch_attr *attr,
881 struct switch_val *val)
882 {
883 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
884
885 esw->alt_vlan_disable = val->value.i != 0;
886
887 return 0;
888 }
889
890 static int
891 rt305x_esw_set_bc_status(struct switch_dev *dev,
892 const struct switch_attr *attr,
893 struct switch_val *val)
894 {
895 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
896
897 esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
898
899 return 0;
900 }
901
902 static int
903 rt305x_esw_get_bc_status(struct switch_dev *dev,
904 const struct switch_attr *attr,
905 struct switch_val *val)
906 {
907 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
908
909 val->value.i = esw->bc_storm_protect;
910
911 return 0;
912 }
913
914 static int
915 rt305x_esw_set_led_freq(struct switch_dev *dev,
916 const struct switch_attr *attr,
917 struct switch_val *val)
918 {
919 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
920
921 esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
922
923 return 0;
924 }
925
926 static int
927 rt305x_esw_get_led_freq(struct switch_dev *dev,
928 const struct switch_attr *attr,
929 struct switch_val *val)
930 {
931 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
932
933 val->value.i = esw->led_frequency;
934
935 return 0;
936 }
937
938 static int esw_get_port_link(struct switch_dev *dev,
939 int port,
940 struct switch_port_link *link)
941 {
942 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
943 u32 speed, poa;
944
945 if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
946 return -EINVAL;
947
948 poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
949
950 link->link = (poa >> RT305X_ESW_LINK_S) & 1;
951 link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
952 if (port < RT305X_ESW_NUM_LEDS) {
953 speed = (poa >> RT305X_ESW_SPD_S) & 1;
954 } else {
955 if (port == RT305X_ESW_NUM_PORTS - 1)
956 poa >>= 1;
957 speed = (poa >> RT305X_ESW_SPD_S) & 3;
958 }
959 switch (speed) {
960 case 0:
961 link->speed = SWITCH_PORT_SPEED_10;
962 break;
963 case 1:
964 link->speed = SWITCH_PORT_SPEED_100;
965 break;
966 case 2:
967 case 3: /* forced gige speed can be 2 or 3 */
968 link->speed = SWITCH_PORT_SPEED_1000;
969 break;
970 default:
971 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
972 break;
973 }
974
975 return 0;
976 }
977
978 static int esw_get_port_bool(struct switch_dev *dev,
979 const struct switch_attr *attr,
980 struct switch_val *val)
981 {
982 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
983 int idx = val->port_vlan;
984 u32 x, reg, shift;
985
986 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
987 return -EINVAL;
988
989 switch (attr->id) {
990 case RT305X_ESW_ATTR_PORT_DISABLE:
991 reg = RT305X_ESW_REG_POC0;
992 shift = RT305X_ESW_POC0_DIS_PORT_S;
993 break;
994 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
995 reg = RT305X_ESW_REG_SGC2;
996 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
997 break;
998 case RT305X_ESW_ATTR_PORT_UNTAG:
999 reg = RT305X_ESW_REG_POC2;
1000 shift = RT305X_ESW_POC2_UNTAG_EN_S;
1001 break;
1002 case RT305X_ESW_ATTR_PORT_LAN:
1003 reg = RT305X_ESW_REG_SGC2;
1004 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1005 if (idx >= RT305X_ESW_NUM_LANWAN)
1006 return -EINVAL;
1007 break;
1008 default:
1009 return -EINVAL;
1010 }
1011
1012 x = esw_r32(esw, reg);
1013 val->value.i = (x >> (idx + shift)) & 1;
1014
1015 return 0;
1016 }
1017
1018 static int esw_set_port_bool(struct switch_dev *dev,
1019 const struct switch_attr *attr,
1020 struct switch_val *val)
1021 {
1022 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1023 int idx = val->port_vlan;
1024
1025 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1026 val->value.i < 0 || val->value.i > 1)
1027 return -EINVAL;
1028
1029 switch (attr->id) {
1030 case RT305X_ESW_ATTR_PORT_DISABLE:
1031 esw->ports[idx].disable = val->value.i;
1032 break;
1033 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1034 esw->ports[idx].doubletag = val->value.i;
1035 break;
1036 case RT305X_ESW_ATTR_PORT_UNTAG:
1037 esw->ports[idx].untag = val->value.i;
1038 break;
1039 default:
1040 return -EINVAL;
1041 }
1042
1043 return 0;
1044 }
1045
1046 static int esw_get_port_recv_badgood(struct switch_dev *dev,
1047 const struct switch_attr *attr,
1048 struct switch_val *val)
1049 {
1050 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1051 int idx = val->port_vlan;
1052 int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1053 u32 reg;
1054
1055 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1056 return -EINVAL;
1057 reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1058 val->value.i = (reg >> shift) & 0xffff;
1059
1060 return 0;
1061 }
1062
1063 static int
1064 esw_get_port_tr_badgood(struct switch_dev *dev,
1065 const struct switch_attr *attr,
1066 struct switch_val *val)
1067 {
1068 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1069
1070 int idx = val->port_vlan;
1071 int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1072 u32 reg;
1073
1074 if (!soc_is_rt5350() && !soc_is_mt7628())
1075 return -EINVAL;
1076
1077 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1078 return -EINVAL;
1079
1080 reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1081 val->value.i = (reg >> shift) & 0xffff;
1082
1083 return 0;
1084 }
1085
1086 static int esw_get_port_led(struct switch_dev *dev,
1087 const struct switch_attr *attr,
1088 struct switch_val *val)
1089 {
1090 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1091 int idx = val->port_vlan;
1092
1093 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1094 idx >= RT305X_ESW_NUM_LEDS)
1095 return -EINVAL;
1096
1097 val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1098
1099 return 0;
1100 }
1101
1102 static int esw_set_port_led(struct switch_dev *dev,
1103 const struct switch_attr *attr,
1104 struct switch_val *val)
1105 {
1106 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1107 int idx = val->port_vlan;
1108
1109 if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1110 return -EINVAL;
1111
1112 esw->ports[idx].led = val->value.i;
1113
1114 return 0;
1115 }
1116
1117 static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1118 {
1119 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1120
1121 if (port >= RT305X_ESW_NUM_PORTS)
1122 return -EINVAL;
1123
1124 *val = esw_get_pvid(esw, port);
1125
1126 return 0;
1127 }
1128
1129 static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1130 {
1131 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1132
1133 if (port >= RT305X_ESW_NUM_PORTS)
1134 return -EINVAL;
1135
1136 esw->ports[port].pvid = val;
1137
1138 return 0;
1139 }
1140
1141 static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1142 {
1143 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1144 u32 vmsc, poc2;
1145 int vlan_idx = -1;
1146 int i;
1147
1148 val->len = 0;
1149
1150 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1151 return -EINVAL;
1152
1153 /* valid vlan? */
1154 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1155 if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1156 esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1157 vlan_idx = i;
1158 break;
1159 }
1160 }
1161
1162 if (vlan_idx == -1)
1163 return -EINVAL;
1164
1165 vmsc = esw_get_vmsc(esw, vlan_idx);
1166 poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1167
1168 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1169 struct switch_port *p;
1170 int port_mask = 1 << i;
1171
1172 if (!(vmsc & port_mask))
1173 continue;
1174
1175 p = &val->value.ports[val->len++];
1176 p->id = i;
1177 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1178 p->flags = 0;
1179 else
1180 p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1181 }
1182
1183 return 0;
1184 }
1185
1186 static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1187 {
1188 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1189 int ports;
1190 int vlan_idx = -1;
1191 int i;
1192
1193 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1194 val->len > RT305X_ESW_NUM_PORTS)
1195 return -EINVAL;
1196
1197 /* one of the already defined vlans? */
1198 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1199 if (esw->vlans[i].vid == val->port_vlan &&
1200 esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1201 vlan_idx = i;
1202 break;
1203 }
1204 }
1205
1206 /* select a free slot */
1207 for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1208 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1209 vlan_idx = i;
1210 }
1211
1212 /* bail if all slots are in use */
1213 if (vlan_idx == -1)
1214 return -EINVAL;
1215
1216 ports = RT305X_ESW_PORTS_NONE;
1217 for (i = 0; i < val->len; i++) {
1218 struct switch_port *p = &val->value.ports[i];
1219 int port_mask = 1 << p->id;
1220 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1221
1222 if (p->id >= RT305X_ESW_NUM_PORTS)
1223 return -EINVAL;
1224
1225 ports |= port_mask;
1226 esw->ports[p->id].untag = untagged;
1227 }
1228 esw->vlans[vlan_idx].ports = ports;
1229 if (ports == RT305X_ESW_PORTS_NONE)
1230 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1231 else
1232 esw->vlans[vlan_idx].vid = val->port_vlan;
1233
1234 return 0;
1235 }
1236
1237 static const struct switch_attr esw_global[] = {
1238 {
1239 .type = SWITCH_TYPE_INT,
1240 .name = "enable_vlan",
1241 .description = "VLAN mode (1:enabled)",
1242 .max = 1,
1243 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1244 .get = esw_get_vlan_enable,
1245 .set = esw_set_vlan_enable,
1246 },
1247 {
1248 .type = SWITCH_TYPE_INT,
1249 .name = "alternate_vlan_disable",
1250 .description = "Use en_vlan instead of doubletag to disable"
1251 " VLAN mode",
1252 .max = 1,
1253 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1254 .get = esw_get_alt_vlan_disable,
1255 .set = esw_set_alt_vlan_disable,
1256 },
1257 {
1258 .type = SWITCH_TYPE_INT,
1259 .name = "bc_storm_protect",
1260 .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1261 .max = 3,
1262 .id = RT305X_ESW_ATTR_BC_STATUS,
1263 .get = rt305x_esw_get_bc_status,
1264 .set = rt305x_esw_set_bc_status,
1265 },
1266 {
1267 .type = SWITCH_TYPE_INT,
1268 .name = "led_frequency",
1269 .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1270 .max = 3,
1271 .id = RT305X_ESW_ATTR_LED_FREQ,
1272 .get = rt305x_esw_get_led_freq,
1273 .set = rt305x_esw_set_led_freq,
1274 }
1275 };
1276
1277 static const struct switch_attr esw_port[] = {
1278 {
1279 .type = SWITCH_TYPE_INT,
1280 .name = "disable",
1281 .description = "Port state (1:disabled)",
1282 .max = 1,
1283 .id = RT305X_ESW_ATTR_PORT_DISABLE,
1284 .get = esw_get_port_bool,
1285 .set = esw_set_port_bool,
1286 },
1287 {
1288 .type = SWITCH_TYPE_INT,
1289 .name = "doubletag",
1290 .description = "Double tagging for incoming vlan packets "
1291 "(1:enabled)",
1292 .max = 1,
1293 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1294 .get = esw_get_port_bool,
1295 .set = esw_set_port_bool,
1296 },
1297 {
1298 .type = SWITCH_TYPE_INT,
1299 .name = "untag",
1300 .description = "Untag (1:strip outgoing vlan tag)",
1301 .max = 1,
1302 .id = RT305X_ESW_ATTR_PORT_UNTAG,
1303 .get = esw_get_port_bool,
1304 .set = esw_set_port_bool,
1305 },
1306 {
1307 .type = SWITCH_TYPE_INT,
1308 .name = "led",
1309 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1310 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1311 " 8:100mact, 10:blink, 11:off, 12:on)",
1312 .max = 15,
1313 .id = RT305X_ESW_ATTR_PORT_LED,
1314 .get = esw_get_port_led,
1315 .set = esw_set_port_led,
1316 },
1317 {
1318 .type = SWITCH_TYPE_INT,
1319 .name = "lan",
1320 .description = "HW port group (0:wan, 1:lan)",
1321 .max = 1,
1322 .id = RT305X_ESW_ATTR_PORT_LAN,
1323 .get = esw_get_port_bool,
1324 },
1325 {
1326 .type = SWITCH_TYPE_INT,
1327 .name = "recv_bad",
1328 .description = "Receive bad packet counter",
1329 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1330 .get = esw_get_port_recv_badgood,
1331 },
1332 {
1333 .type = SWITCH_TYPE_INT,
1334 .name = "recv_good",
1335 .description = "Receive good packet counter",
1336 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1337 .get = esw_get_port_recv_badgood,
1338 },
1339 {
1340 .type = SWITCH_TYPE_INT,
1341 .name = "tr_bad",
1342
1343 .description = "Transmit bad packet counter. rt5350 only",
1344 .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1345 .get = esw_get_port_tr_badgood,
1346 },
1347 {
1348 .type = SWITCH_TYPE_INT,
1349 .name = "tr_good",
1350
1351 .description = "Transmit good packet counter. rt5350 only",
1352 .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1353 .get = esw_get_port_tr_badgood,
1354 },
1355 };
1356
1357 static const struct switch_attr esw_vlan[] = {
1358 };
1359
1360 static const struct switch_dev_ops esw_ops = {
1361 .attr_global = {
1362 .attr = esw_global,
1363 .n_attr = ARRAY_SIZE(esw_global),
1364 },
1365 .attr_port = {
1366 .attr = esw_port,
1367 .n_attr = ARRAY_SIZE(esw_port),
1368 },
1369 .attr_vlan = {
1370 .attr = esw_vlan,
1371 .n_attr = ARRAY_SIZE(esw_vlan),
1372 },
1373 .get_vlan_ports = esw_get_vlan_ports,
1374 .set_vlan_ports = esw_set_vlan_ports,
1375 .get_port_pvid = esw_get_port_pvid,
1376 .set_port_pvid = esw_set_port_pvid,
1377 .get_port_link = esw_get_port_link,
1378 .apply_config = esw_apply_config,
1379 .reset_switch = esw_reset_switch,
1380 };
1381
1382 static struct rt305x_esw_platform_data rt3050_esw_data = {
1383 /* All ports are LAN ports. */
1384 .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1385 .reg_initval_fct2 = 0x00d6500c,
1386 /*
1387 * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1388 * turbo mii off, rgmi 3.3v off
1389 * port5: disabled
1390 * port6: enabled, gige, full-duplex, rx/tx-flow-control
1391 */
1392 .reg_initval_fpa2 = 0x3f502b28,
1393 };
1394
1395 static const struct of_device_id ralink_esw_match[] = {
1396 { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1397 {},
1398 };
1399 MODULE_DEVICE_TABLE(of, ralink_esw_match);
1400
1401 static int esw_probe(struct platform_device *pdev)
1402 {
1403 struct device_node *np = pdev->dev.of_node;
1404 const struct rt305x_esw_platform_data *pdata;
1405 const __be32 *port_map, *reg_init;
1406 struct rt305x_esw *esw;
1407 struct switch_dev *swdev;
1408 struct resource *res, *irq;
1409 int err;
1410
1411 pdata = pdev->dev.platform_data;
1412 if (!pdata) {
1413 const struct of_device_id *match;
1414 match = of_match_device(ralink_esw_match, &pdev->dev);
1415 if (match)
1416 pdata = (struct rt305x_esw_platform_data *) match->data;
1417 }
1418 if (!pdata)
1419 return -EINVAL;
1420
1421 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1422 if (!res) {
1423 dev_err(&pdev->dev, "no memory resource found\n");
1424 return -ENOMEM;
1425 }
1426
1427 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1428 if (!irq) {
1429 dev_err(&pdev->dev, "no irq resource found\n");
1430 return -ENOMEM;
1431 }
1432
1433 esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1434 if (!esw) {
1435 dev_err(&pdev->dev, "no memory for private data\n");
1436 return -ENOMEM;
1437 }
1438
1439 esw->dev = &pdev->dev;
1440 esw->irq = irq->start;
1441 esw->base = ioremap(res->start, resource_size(res));
1442 if (!esw->base) {
1443 dev_err(&pdev->dev, "ioremap failed\n");
1444 err = -ENOMEM;
1445 goto free_esw;
1446 }
1447
1448 port_map = of_get_property(np, "ralink,portmap", NULL);
1449 if (port_map)
1450 esw->port_map = be32_to_cpu(*port_map);
1451
1452 reg_init = of_get_property(np, "ralink,fct2", NULL);
1453 if (reg_init)
1454 esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1455
1456 reg_init = of_get_property(np, "ralink,fpa2", NULL);
1457 if (reg_init)
1458 esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1459
1460 reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1461 if (reg_init)
1462 esw->reg_led_polarity = be32_to_cpu(*reg_init);
1463
1464 swdev = &esw->swdev;
1465 swdev->of_node = pdev->dev.of_node;
1466 swdev->name = "rt305x-esw";
1467 swdev->alias = "rt305x";
1468 swdev->cpu_port = RT305X_ESW_PORT6;
1469 swdev->ports = RT305X_ESW_NUM_PORTS;
1470 swdev->vlans = RT305X_ESW_NUM_VIDS;
1471 swdev->ops = &esw_ops;
1472
1473 err = register_switch(swdev, NULL);
1474 if (err < 0) {
1475 dev_err(&pdev->dev, "register_switch failed\n");
1476 goto unmap_base;
1477 }
1478
1479 platform_set_drvdata(pdev, esw);
1480
1481 esw->pdata = pdata;
1482 spin_lock_init(&esw->reg_rw_lock);
1483
1484 esw_hw_init(esw);
1485
1486 esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1487 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1488 request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1489
1490 return 0;
1491
1492 unmap_base:
1493 iounmap(esw->base);
1494 free_esw:
1495 kfree(esw);
1496 return err;
1497 }
1498
1499 static int esw_remove(struct platform_device *pdev)
1500 {
1501 struct rt305x_esw *esw;
1502
1503 esw = platform_get_drvdata(pdev);
1504 if (esw) {
1505 unregister_switch(&esw->swdev);
1506 platform_set_drvdata(pdev, NULL);
1507 iounmap(esw->base);
1508 kfree(esw);
1509 }
1510
1511 return 0;
1512 }
1513
1514 static struct platform_driver esw_driver = {
1515 .probe = esw_probe,
1516 .remove = esw_remove,
1517 .driver = {
1518 .name = "rt305x-esw",
1519 .owner = THIS_MODULE,
1520 .of_match_table = ralink_esw_match,
1521 },
1522 };
1523
1524 int __init rtesw_init(void)
1525 {
1526 return platform_driver_register(&esw_driver);
1527 }
1528
1529 void rtesw_exit(void)
1530 {
1531 platform_driver_unregister(&esw_driver);
1532 }
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