projects / openwrt / svn-archive / archive.git / blob
? search:


5bc9b58336962a14b820c9f25e32e9ea1dd0fd76
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35 #include <linux/bug.h>
36
37 #include <asm/mach-ralink/ralink_regs.h>
38
39 #include "ralink_soc_eth.h"
40 #include "esw_rt3052.h"
41 #include "mdio.h"
42 #include "ralink_ethtool.h"
43
44 #define MAX_RX_LENGTH 1536
45 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
46 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
47 #define DMA_DUMMY_DESC 0xffffffff
48 #define FE_DEFAULT_MSG_ENABLE \
49 (NETIF_MSG_DRV | \
50 NETIF_MSG_PROBE | \
51 NETIF_MSG_LINK | \
52 NETIF_MSG_TIMER | \
53 NETIF_MSG_IFDOWN | \
54 NETIF_MSG_IFUP | \
55 NETIF_MSG_RX_ERR | \
56 NETIF_MSG_TX_ERR)
57
58 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
59 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
60 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
61 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
62
63 #define SYSC_REG_RSTCTRL 0x34
64
65 static int fe_msg_level = -1;
66 module_param_named(msg_level, fe_msg_level, int, 0);
67 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
68
69 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
70 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
71 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
72 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
73 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
74 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
75 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
76 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
77 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
78 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
79 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
80 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
81 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
82 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
83 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
84 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
85 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
86 };
87
88 static const u16 *fe_reg_table = fe_reg_table_default;
89
90 struct fe_work_t {
91 int bitnr;
92 void (*action)(struct fe_priv *);
93 };
94
95 static void __iomem *fe_base = 0;
96
97 void fe_w32(u32 val, unsigned reg)
98 {
99 __raw_writel(val, fe_base + reg);
100 }
101
102 u32 fe_r32(unsigned reg)
103 {
104 return __raw_readl(fe_base + reg);
105 }
106
107 void fe_reg_w32(u32 val, enum fe_reg reg)
108 {
109 fe_w32(val, fe_reg_table[reg]);
110 }
111
112 u32 fe_reg_r32(enum fe_reg reg)
113 {
114 return fe_r32(fe_reg_table[reg]);
115 }
116
117 void fe_reset(u32 reset_bits)
118 {
119 u32 t;
120
121 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
122 t |= reset_bits;
123 rt_sysc_w32(t , SYSC_REG_RSTCTRL);
124 udelay(10);
125
126 t &= ~reset_bits;
127 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
128 udelay(10);
129 }
130
131 static inline void fe_int_disable(u32 mask)
132 {
133 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
134 FE_REG_FE_INT_ENABLE);
135 /* flush write */
136 fe_reg_r32(FE_REG_FE_INT_ENABLE);
137 }
138
139 static inline void fe_int_enable(u32 mask)
140 {
141 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
142 FE_REG_FE_INT_ENABLE);
143 /* flush write */
144 fe_reg_r32(FE_REG_FE_INT_ENABLE);
145 }
146
147 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
148 {
149 unsigned long flags;
150
151 spin_lock_irqsave(&priv->page_lock, flags);
152 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
153 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
154 FE_GDMA1_MAC_ADRL);
155 spin_unlock_irqrestore(&priv->page_lock, flags);
156 }
157
158 static int fe_set_mac_address(struct net_device *dev, void *p)
159 {
160 int ret = eth_mac_addr(dev, p);
161
162 if (!ret) {
163 struct fe_priv *priv = netdev_priv(dev);
164
165 if (priv->soc->set_mac)
166 priv->soc->set_mac(priv, dev->dev_addr);
167 else
168 fe_hw_set_macaddr(priv, p);
169 }
170
171 return ret;
172 }
173
174 static inline int fe_max_frag_size(int mtu)
175 {
176 /* make sure buf_size will be at least MAX_RX_LENGTH */
177 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
178 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
179
180 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
181 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
182 }
183
184 static inline int fe_max_buf_size(int frag_size)
185 {
186 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
187 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
188
189 BUG_ON(buf_size < MAX_RX_LENGTH);
190 return buf_size;
191 }
192
193 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
194 {
195 rxd->rxd1 = dma_rxd->rxd1;
196 rxd->rxd2 = dma_rxd->rxd2;
197 rxd->rxd3 = dma_rxd->rxd3;
198 rxd->rxd4 = dma_rxd->rxd4;
199 }
200
201 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
202 {
203 dma_txd->txd1 = txd->txd1;
204 dma_txd->txd3 = txd->txd3;
205 dma_txd->txd4 = txd->txd4;
206 /* clean dma done flag last */
207 dma_txd->txd2 = txd->txd2;
208 }
209
210 static void fe_clean_rx(struct fe_priv *priv)
211 {
212 int i;
213 struct fe_rx_ring *ring = &priv->rx_ring;
214
215 if (ring->rx_data) {
216 for (i = 0; i < ring->rx_ring_size; i++)
217 if (ring->rx_data[i]) {
218 if (ring->rx_dma && ring->rx_dma[i].rxd1)
219 dma_unmap_single(&priv->netdev->dev,
220 ring->rx_dma[i].rxd1,
221 ring->rx_buf_size,
222 DMA_FROM_DEVICE);
223 put_page(virt_to_head_page(ring->rx_data[i]));
224 }
225
226 kfree(ring->rx_data);
227 ring->rx_data = NULL;
228 }
229
230 if (ring->rx_dma) {
231 dma_free_coherent(&priv->netdev->dev,
232 ring->rx_ring_size * sizeof(*ring->rx_dma),
233 ring->rx_dma,
234 ring->rx_phys);
235 ring->rx_dma = NULL;
236 }
237 }
238
239 static int fe_alloc_rx(struct fe_priv *priv)
240 {
241 struct net_device *netdev = priv->netdev;
242 struct fe_rx_ring *ring = &priv->rx_ring;
243 int i, pad;
244
245 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
246 GFP_KERNEL);
247 if (!ring->rx_data)
248 goto no_rx_mem;
249
250 for (i = 0; i < ring->rx_ring_size; i++) {
251 ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
252 if (!ring->rx_data[i])
253 goto no_rx_mem;
254 }
255
256 ring->rx_dma = dma_alloc_coherent(&netdev->dev,
257 ring->rx_ring_size * sizeof(*ring->rx_dma),
258 &ring->rx_phys,
259 GFP_ATOMIC | __GFP_ZERO);
260 if (!ring->rx_dma)
261 goto no_rx_mem;
262
263 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
264 pad = 0;
265 else
266 pad = NET_IP_ALIGN;
267 for (i = 0; i < ring->rx_ring_size; i++) {
268 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
269 ring->rx_data[i] + NET_SKB_PAD + pad,
270 ring->rx_buf_size,
271 DMA_FROM_DEVICE);
272 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
273 goto no_rx_mem;
274 ring->rx_dma[i].rxd1 = (unsigned int) dma_addr;
275
276 if (priv->flags & FE_FLAG_RX_SG_DMA)
277 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
278 else
279 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
280 }
281 ring->rx_calc_idx = ring->rx_ring_size - 1;
282 wmb();
283
284 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
285 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
286 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
287 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
288
289 return 0;
290
291 no_rx_mem:
292 return -ENOMEM;
293 }
294
295 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
296 {
297 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
298 dma_unmap_single(dev,
299 dma_unmap_addr(tx_buf, dma_addr0),
300 dma_unmap_len(tx_buf, dma_len0),
301 DMA_TO_DEVICE);
302 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
303 dma_unmap_page(dev,
304 dma_unmap_addr(tx_buf, dma_addr0),
305 dma_unmap_len(tx_buf, dma_len0),
306 DMA_TO_DEVICE);
307 }
308 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
309 dma_unmap_page(dev,
310 dma_unmap_addr(tx_buf, dma_addr1),
311 dma_unmap_len(tx_buf, dma_len1),
312 DMA_TO_DEVICE);
313
314 tx_buf->flags = 0;
315 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *) DMA_DUMMY_DESC)) {
316 dev_kfree_skb_any(tx_buf->skb);
317 }
318 tx_buf->skb = NULL;
319 }
320
321 static void fe_clean_tx(struct fe_priv *priv)
322 {
323 int i;
324 struct device *dev = &priv->netdev->dev;
325 struct fe_tx_ring *ring = &priv->tx_ring;
326
327 if (ring->tx_buf) {
328 for (i = 0; i < ring->tx_ring_size; i++)
329 fe_txd_unmap(dev, &ring->tx_buf[i]);
330 kfree(ring->tx_buf);
331 ring->tx_buf = NULL;
332 }
333
334 if (ring->tx_dma) {
335 dma_free_coherent(dev,
336 ring->tx_ring_size * sizeof(*ring->tx_dma),
337 ring->tx_dma,
338 ring->tx_phys);
339 ring->tx_dma = NULL;
340 }
341
342 netdev_reset_queue(priv->netdev);
343 }
344
345 static int fe_alloc_tx(struct fe_priv *priv)
346 {
347 int i;
348 struct fe_tx_ring *ring = &priv->tx_ring;
349
350 ring->tx_free_idx = 0;
351 ring->tx_next_idx = 0;
352 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2, MAX_SKB_FRAGS);
353
354 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
355 GFP_KERNEL);
356 if (!ring->tx_buf)
357 goto no_tx_mem;
358
359 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
360 ring->tx_ring_size * sizeof(*ring->tx_dma),
361 &ring->tx_phys,
362 GFP_ATOMIC | __GFP_ZERO);
363 if (!ring->tx_dma)
364 goto no_tx_mem;
365
366 for (i = 0; i < ring->tx_ring_size; i++) {
367 if (priv->soc->tx_dma) {
368 priv->soc->tx_dma(&ring->tx_dma[i]);
369 }
370 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
371 }
372 wmb();
373
374 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
375 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
376 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
377 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
378
379 return 0;
380
381 no_tx_mem:
382 return -ENOMEM;
383 }
384
385 static int fe_init_dma(struct fe_priv *priv)
386 {
387 int err;
388
389 err = fe_alloc_tx(priv);
390 if (err)
391 return err;
392
393 err = fe_alloc_rx(priv);
394 if (err)
395 return err;
396
397 return 0;
398 }
399
400 static void fe_free_dma(struct fe_priv *priv)
401 {
402 fe_clean_tx(priv);
403 fe_clean_rx(priv);
404 }
405
406 void fe_stats_update(struct fe_priv *priv)
407 {
408 struct fe_hw_stats *hwstats = priv->hw_stats;
409 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
410 u64 stats;
411
412 u64_stats_update_begin(&hwstats->syncp);
413
414 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
415 hwstats->rx_bytes += fe_r32(base);
416 stats = fe_r32(base + 0x04);
417 if (stats)
418 hwstats->rx_bytes += (stats << 32);
419 hwstats->rx_packets += fe_r32(base + 0x08);
420 hwstats->rx_overflow += fe_r32(base + 0x10);
421 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
422 hwstats->rx_short_errors += fe_r32(base + 0x18);
423 hwstats->rx_long_errors += fe_r32(base + 0x1c);
424 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
425 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
426 hwstats->tx_skip += fe_r32(base + 0x28);
427 hwstats->tx_collisions += fe_r32(base + 0x2c);
428 hwstats->tx_bytes += fe_r32(base + 0x30);
429 stats = fe_r32(base + 0x34);
430 if (stats)
431 hwstats->tx_bytes += (stats << 32);
432 hwstats->tx_packets += fe_r32(base + 0x38);
433 } else {
434 hwstats->tx_bytes += fe_r32(base);
435 hwstats->tx_packets += fe_r32(base + 0x04);
436 hwstats->tx_skip += fe_r32(base + 0x08);
437 hwstats->tx_collisions += fe_r32(base + 0x0c);
438 hwstats->rx_bytes += fe_r32(base + 0x20);
439 hwstats->rx_packets += fe_r32(base + 0x24);
440 hwstats->rx_overflow += fe_r32(base + 0x28);
441 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
442 hwstats->rx_short_errors += fe_r32(base + 0x30);
443 hwstats->rx_long_errors += fe_r32(base + 0x34);
444 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
445 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
446 }
447
448 u64_stats_update_end(&hwstats->syncp);
449 }
450
451 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
452 struct rtnl_link_stats64 *storage)
453 {
454 struct fe_priv *priv = netdev_priv(dev);
455 struct fe_hw_stats *hwstats = priv->hw_stats;
456 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
457 unsigned int start;
458
459 if (!base) {
460 netdev_stats_to_stats64(storage, &dev->stats);
461 return storage;
462 }
463
464 if (netif_running(dev) && netif_device_present(dev)) {
465 if (spin_trylock(&hwstats->stats_lock)) {
466 fe_stats_update(priv);
467 spin_unlock(&hwstats->stats_lock);
468 }
469 }
470
471 do {
472 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
473 storage->rx_packets = hwstats->rx_packets;
474 storage->tx_packets = hwstats->tx_packets;
475 storage->rx_bytes = hwstats->rx_bytes;
476 storage->tx_bytes = hwstats->tx_bytes;
477 storage->collisions = hwstats->tx_collisions;
478 storage->rx_length_errors = hwstats->rx_short_errors +
479 hwstats->rx_long_errors;
480 storage->rx_over_errors = hwstats->rx_overflow;
481 storage->rx_crc_errors = hwstats->rx_fcs_errors;
482 storage->rx_errors = hwstats->rx_checksum_errors;
483 storage->tx_aborted_errors = hwstats->tx_skip;
484 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
485
486 storage->tx_errors = priv->netdev->stats.tx_errors;
487 storage->rx_dropped = priv->netdev->stats.rx_dropped;
488 storage->tx_dropped = priv->netdev->stats.tx_dropped;
489
490 return storage;
491 }
492
493 static int fe_vlan_rx_add_vid(struct net_device *dev,
494 __be16 proto, u16 vid)
495 {
496 struct fe_priv *priv = netdev_priv(dev);
497 u32 idx = (vid & 0xf);
498 u32 vlan_cfg;
499
500 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
501 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
502 return 0;
503
504 if (test_bit(idx, &priv->vlan_map)) {
505 netdev_warn(dev, "disable tx vlan offload\n");
506 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
507 netdev_update_features(dev);
508 } else {
509 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
510 ((idx >> 1) << 2));
511 if (idx & 0x1) {
512 vlan_cfg &= 0xffff;
513 vlan_cfg |= (vid << 16);
514 } else {
515 vlan_cfg &= 0xffff0000;
516 vlan_cfg |= vid;
517 }
518 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
519 ((idx >> 1) << 2));
520 set_bit(idx, &priv->vlan_map);
521 }
522
523 return 0;
524 }
525
526 static int fe_vlan_rx_kill_vid(struct net_device *dev,
527 __be16 proto, u16 vid)
528 {
529 struct fe_priv *priv = netdev_priv(dev);
530 u32 idx = (vid & 0xf);
531
532 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
533 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
534 return 0;
535
536 clear_bit(idx, &priv->vlan_map);
537
538 return 0;
539 }
540
541 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
542 {
543 barrier();
544 return (u32)(ring->tx_ring_size -
545 ((ring->tx_next_idx - ring->tx_free_idx) &
546 (ring->tx_ring_size - 1)));
547 }
548
549 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
550 int tx_num, struct fe_tx_ring *ring)
551 {
552 struct fe_priv *priv = netdev_priv(dev);
553 struct skb_frag_struct *frag;
554 struct fe_tx_dma txd, *ptxd;
555 struct fe_tx_buf *tx_buf;
556 dma_addr_t mapped_addr;
557 unsigned int nr_frags;
558 u32 def_txd4;
559 int i, j, k, frag_size, frag_map_size, offset;
560
561 tx_buf = &ring->tx_buf[ring->tx_next_idx];
562 memset(tx_buf, 0, sizeof(*tx_buf));
563 memset(&txd, 0, sizeof(txd));
564 nr_frags = skb_shinfo(skb)->nr_frags;
565
566 /* init tx descriptor */
567 if (priv->soc->tx_dma)
568 priv->soc->tx_dma(&txd);
569 else
570 txd.txd4 = TX_DMA_DESP4_DEF;
571 def_txd4 = txd.txd4;
572
573 /* TX Checksum offload */
574 if (skb->ip_summed == CHECKSUM_PARTIAL)
575 txd.txd4 |= TX_DMA_CHKSUM;
576
577 /* VLAN header offload */
578 if (skb_vlan_tag_present(skb)) {
579 u16 tag = skb_vlan_tag_get(skb);
580
581 if (IS_ENABLED(CONFIG_SOC_MT7621))
582 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
583 else
584 txd.txd4 |= TX_DMA_INS_VLAN |
585 ((tag >> VLAN_PRIO_SHIFT) << 4) |
586 (tag & 0xF);
587 }
588
589 /* TSO: fill MSS info in tcp checksum field */
590 if (skb_is_gso(skb)) {
591 if (skb_cow_head(skb, 0)) {
592 netif_warn(priv, tx_err, dev,
593 "GSO expand head fail.\n");
594 goto err_out;
595 }
596 if (skb_shinfo(skb)->gso_type &
597 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
598 txd.txd4 |= TX_DMA_TSO;
599 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
600 }
601 }
602
603 mapped_addr = dma_map_single(&dev->dev, skb->data,
604 skb_headlen(skb), DMA_TO_DEVICE);
605 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
606 goto err_out;
607 txd.txd1 = mapped_addr;
608 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
609
610 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
611 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
612 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
613
614 /* TX SG offload */
615 j = ring->tx_next_idx;
616 k = 0;
617 for (i = 0; i < nr_frags; i++) {
618 offset = 0;
619 frag = &skb_shinfo(skb)->frags[i];
620 frag_size = skb_frag_size(frag);
621
622 while (frag_size > 0) {
623 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
624 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
625 frag_map_size, DMA_TO_DEVICE);
626 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
627 goto err_dma;
628
629 if (k & 0x1) {
630 j = NEXT_TX_DESP_IDX(j);
631 txd.txd1 = mapped_addr;
632 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
633 txd.txd4 = def_txd4;
634
635 tx_buf = &ring->tx_buf[j];
636 memset(tx_buf, 0, sizeof(*tx_buf));
637
638 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
639 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
640 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
641 } else {
642 txd.txd3 = mapped_addr;
643 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
644
645 tx_buf->skb = (struct sk_buff *) DMA_DUMMY_DESC;
646 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
647 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
648 dma_unmap_len_set(tx_buf, dma_len1, frag_map_size);
649
650 if (!((i == (nr_frags -1)) &&
651 (frag_map_size == frag_size))) {
652 fe_set_txd(&txd, &ring->tx_dma[j]);
653 memset(&txd, 0, sizeof(txd));
654 }
655 }
656 frag_size -= frag_map_size;
657 offset += frag_map_size;
658 k++;
659 }
660 }
661
662 /* set last segment */
663 if (k & 0x1)
664 txd.txd2 |= TX_DMA_LS1;
665 else
666 txd.txd2 |= TX_DMA_LS0;
667 fe_set_txd(&txd, &ring->tx_dma[j]);
668
669 /* store skb to cleanup */
670 tx_buf->skb = skb;
671
672 netdev_sent_queue(dev, skb->len);
673 skb_tx_timestamp(skb);
674
675 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
676 wmb();
677 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
678 netif_stop_queue(dev);
679 smp_mb();
680 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
681 netif_wake_queue(dev);
682 }
683
684 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
685 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
686
687 return 0;
688
689 err_dma:
690 j = ring->tx_next_idx;
691 for (i = 0; i < tx_num; i++) {
692 ptxd = &ring->tx_dma[j];
693 tx_buf = &ring->tx_buf[j];
694
695 /* unmap dma */
696 fe_txd_unmap(&dev->dev, tx_buf);
697
698 ptxd->txd2 = TX_DMA_DESP2_DEF;
699 j = NEXT_TX_DESP_IDX(j);
700 }
701 wmb();
702
703 err_out:
704 return -1;
705 }
706
707 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
708 unsigned int len;
709 int ret;
710
711 ret = 0;
712 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
713 if ((priv->flags & FE_FLAG_PADDING_64B) &&
714 !(priv->flags & FE_FLAG_PADDING_BUG))
715 return ret;
716 if (skb_vlan_tag_present(skb))
717 len = ETH_ZLEN;
718 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
719 len = VLAN_ETH_ZLEN;
720 else if(!(priv->flags & FE_FLAG_PADDING_64B))
721 len = ETH_ZLEN;
722 else
723 return ret;
724
725 if (skb->len < len) {
726 if ((ret = skb_pad(skb, len - skb->len)) < 0)
727 return ret;
728 skb->len = len;
729 skb_set_tail_pointer(skb, len);
730 }
731 }
732
733 return ret;
734 }
735
736 static inline int fe_cal_txd_req(struct sk_buff *skb)
737 {
738 int i, nfrags;
739 struct skb_frag_struct *frag;
740
741 nfrags = 1;
742 if (skb_is_gso(skb)) {
743 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
744 frag = &skb_shinfo(skb)->frags[i];
745 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
746 }
747 } else {
748 nfrags += skb_shinfo(skb)->nr_frags;
749 }
750
751 return DIV_ROUND_UP(nfrags, 2);
752 }
753
754 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
755 {
756 struct fe_priv *priv = netdev_priv(dev);
757 struct fe_tx_ring *ring = &priv->tx_ring;
758 struct net_device_stats *stats = &dev->stats;
759 int tx_num;
760 int len = skb->len;
761
762 if (fe_skb_padto(skb, priv)) {
763 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
764 return NETDEV_TX_OK;
765 }
766
767 tx_num = fe_cal_txd_req(skb);
768 if (unlikely(fe_empty_txd(ring) <= tx_num))
769 {
770 netif_stop_queue(dev);
771 netif_err(priv, tx_queued,dev,
772 "Tx Ring full when queue awake!\n");
773 return NETDEV_TX_BUSY;
774 }
775
776 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
777 stats->tx_dropped++;
778 } else {
779 stats->tx_packets++;
780 stats->tx_bytes += len;
781 }
782
783 return NETDEV_TX_OK;
784 }
785
786 static inline void fe_rx_vlan(struct sk_buff *skb)
787 {
788 struct ethhdr *ehdr;
789 u16 vlanid;
790
791 if (!__vlan_get_tag(skb, &vlanid)) {
792 /* pop the vlan tag */
793 ehdr = (struct ethhdr *)skb->data;
794 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
795 skb_pull(skb, VLAN_HLEN);
796 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
797 }
798 }
799
800 static int fe_poll_rx(struct napi_struct *napi, int budget,
801 struct fe_priv *priv, u32 rx_intr)
802 {
803 struct net_device *netdev = priv->netdev;
804 struct net_device_stats *stats = &netdev->stats;
805 struct fe_soc_data *soc = priv->soc;
806 struct fe_rx_ring *ring = &priv->rx_ring;
807 int idx = ring->rx_calc_idx;
808 u32 checksum_bit;
809 struct sk_buff *skb;
810 u8 *data, *new_data;
811 struct fe_rx_dma *rxd, trxd;
812 int done = 0, pad;
813 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
814
815 if (netdev->features & NETIF_F_RXCSUM)
816 checksum_bit = soc->checksum_bit;
817 else
818 checksum_bit = 0;
819
820 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
821 pad = 0;
822 else
823 pad = NET_IP_ALIGN;
824
825 while (done < budget) {
826 unsigned int pktlen;
827 dma_addr_t dma_addr;
828 idx = NEXT_RX_DESP_IDX(idx);
829 rxd = &ring->rx_dma[idx];
830 data = ring->rx_data[idx];
831
832 fe_get_rxd(&trxd, rxd);
833 if (!(trxd.rxd2 & RX_DMA_DONE))
834 break;
835
836 /* alloc new buffer */
837 new_data = netdev_alloc_frag(ring->frag_size);
838 if (unlikely(!new_data)) {
839 stats->rx_dropped++;
840 goto release_desc;
841 }
842 dma_addr = dma_map_single(&netdev->dev,
843 new_data + NET_SKB_PAD + pad,
844 ring->rx_buf_size,
845 DMA_FROM_DEVICE);
846 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
847 put_page(virt_to_head_page(new_data));
848 goto release_desc;
849 }
850
851 /* receive data */
852 skb = build_skb(data, ring->frag_size);
853 if (unlikely(!skb)) {
854 put_page(virt_to_head_page(new_data));
855 goto release_desc;
856 }
857 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
858
859 dma_unmap_single(&netdev->dev, trxd.rxd1,
860 ring->rx_buf_size, DMA_FROM_DEVICE);
861 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
862 skb->dev = netdev;
863 skb_put(skb, pktlen);
864 if (trxd.rxd4 & checksum_bit) {
865 skb->ip_summed = CHECKSUM_UNNECESSARY;
866 } else {
867 skb_checksum_none_assert(skb);
868 }
869 if (rx_vlan)
870 fe_rx_vlan(skb);
871 skb->protocol = eth_type_trans(skb, netdev);
872
873 stats->rx_packets++;
874 stats->rx_bytes += pktlen;
875
876 napi_gro_receive(napi, skb);
877
878 ring->rx_data[idx] = new_data;
879 rxd->rxd1 = (unsigned int) dma_addr;
880
881 release_desc:
882 if (priv->flags & FE_FLAG_RX_SG_DMA)
883 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
884 else
885 rxd->rxd2 = RX_DMA_LSO;
886
887 ring->rx_calc_idx = idx;
888 wmb();
889 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
890 done++;
891 }
892
893 if (done < budget)
894 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
895
896 return done;
897 }
898
899 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
900 int *tx_again)
901 {
902 struct net_device *netdev = priv->netdev;
903 struct device *dev = &netdev->dev;
904 unsigned int bytes_compl = 0;
905 struct sk_buff *skb;
906 struct fe_tx_buf *tx_buf;
907 int done = 0;
908 u32 idx, hwidx;
909 struct fe_tx_ring *ring = &priv->tx_ring;
910
911 idx = ring->tx_free_idx;
912 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
913
914 while ((idx != hwidx) && budget) {
915 tx_buf = &ring->tx_buf[idx];
916 skb = tx_buf->skb;
917
918 if (!skb)
919 break;
920
921 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
922 bytes_compl += skb->len;
923 done++;
924 budget--;
925 }
926 fe_txd_unmap(dev, tx_buf);
927 idx = NEXT_TX_DESP_IDX(idx);
928 }
929 ring->tx_free_idx = idx;
930
931 if (idx == hwidx) {
932 /* read hw index again make sure no new tx packet */
933 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
934 if (idx == hwidx)
935 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
936 else
937 *tx_again = 1;
938 } else
939 *tx_again = 1;
940
941 if (done) {
942 netdev_completed_queue(netdev, done, bytes_compl);
943 smp_mb();
944 if (unlikely(netif_queue_stopped(netdev) &&
945 (fe_empty_txd(ring) > ring->tx_thresh)))
946 netif_wake_queue(netdev);
947 }
948
949 return done;
950 }
951
952 static int fe_poll(struct napi_struct *napi, int budget)
953 {
954 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
955 struct fe_hw_stats *hwstat = priv->hw_stats;
956 int tx_done, rx_done, tx_again;
957 u32 status, fe_status, status_reg, mask;
958 u32 tx_intr, rx_intr, status_intr;
959
960 fe_status = status = fe_reg_r32(FE_REG_FE_INT_STATUS);
961 tx_intr = priv->soc->tx_int;
962 rx_intr = priv->soc->rx_int;
963 status_intr = priv->soc->status_int;
964 tx_done = rx_done = tx_again = 0;
965
966 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
967 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
968 status_reg = FE_REG_FE_INT_STATUS2;
969 } else
970 status_reg = FE_REG_FE_INT_STATUS;
971
972 if (status & tx_intr)
973 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
974
975 if (status & rx_intr)
976 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
977
978 if (unlikely(fe_status & status_intr)) {
979 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
980 fe_stats_update(priv);
981 spin_unlock(&hwstat->stats_lock);
982 }
983 fe_reg_w32(status_intr, status_reg);
984 }
985
986 if (unlikely(netif_msg_intr(priv))) {
987 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
988 netdev_info(priv->netdev,
989 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
990 tx_done, rx_done, status, mask);
991 }
992
993 if (!tx_again && (rx_done < budget)) {
994 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
995 if (status & (tx_intr | rx_intr)) {
996 /* let napi poll again */
997 rx_done = budget;
998 goto poll_again;
999 }
1000
1001 napi_complete(napi);
1002 fe_int_enable(tx_intr | rx_intr);
1003 } else {
1004 rx_done = budget;
1005 }
1006
1007 poll_again:
1008 return rx_done;
1009 }
1010
1011 static void fe_tx_timeout(struct net_device *dev)
1012 {
1013 struct fe_priv *priv = netdev_priv(dev);
1014 struct fe_tx_ring *ring = &priv->tx_ring;
1015
1016 priv->netdev->stats.tx_errors++;
1017 netif_err(priv, tx_err, dev,
1018 "transmit timed out\n");
1019 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1020 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1021 netif_info(priv, drv, dev, "tx_ring=%d, " \
1022 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n", 0,
1023 fe_reg_r32(FE_REG_TX_BASE_PTR0),
1024 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1025 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1026 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1027 ring->tx_free_idx,
1028 ring->tx_next_idx
1029 );
1030 netif_info(priv, drv, dev, "rx_ring=%d, " \
1031 "base=%08x, max=%u, calc=%u, drx=%u\n", 0,
1032 fe_reg_r32(FE_REG_RX_BASE_PTR0),
1033 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1034 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1035 fe_reg_r32(FE_REG_RX_DRX_IDX0)
1036 );
1037
1038 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1039 schedule_work(&priv->pending_work);
1040 }
1041
1042 static irqreturn_t fe_handle_irq(int irq, void *dev)
1043 {
1044 struct fe_priv *priv = netdev_priv(dev);
1045 u32 status, int_mask;
1046
1047 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1048
1049 if (unlikely(!status))
1050 return IRQ_NONE;
1051
1052 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1053 if (likely(status & int_mask)) {
1054 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1055 fe_int_disable(int_mask);
1056 __napi_schedule(&priv->rx_napi);
1057 }
1058 } else {
1059 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1060 }
1061
1062 return IRQ_HANDLED;
1063 }
1064
1065 #ifdef CONFIG_NET_POLL_CONTROLLER
1066 static void fe_poll_controller(struct net_device *dev)
1067 {
1068 struct fe_priv *priv = netdev_priv(dev);
1069 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1070
1071 fe_int_disable(int_mask);
1072 fe_handle_irq(dev->irq, dev);
1073 fe_int_enable(int_mask);
1074 }
1075 #endif
1076
1077 int fe_set_clock_cycle(struct fe_priv *priv)
1078 {
1079 unsigned long sysclk = priv->sysclk;
1080
1081 if (!sysclk) {
1082 return -EINVAL;
1083 }
1084
1085 sysclk /= FE_US_CYC_CNT_DIVISOR;
1086 sysclk <<= FE_US_CYC_CNT_SHIFT;
1087
1088 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1089 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1090 sysclk,
1091 FE_FE_GLO_CFG);
1092 return 0;
1093 }
1094
1095 void fe_fwd_config(struct fe_priv *priv)
1096 {
1097 u32 fwd_cfg;
1098
1099 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1100
1101 /* disable jumbo frame */
1102 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1103 fwd_cfg &= ~FE_GDM1_JMB_EN;
1104
1105 /* set unicast/multicast/broadcast frame to cpu */
1106 fwd_cfg &= ~0xffff;
1107
1108 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1109 }
1110
1111 static void fe_rxcsum_config(bool enable)
1112 {
1113 if (enable)
1114 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1115 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1116 FE_GDMA1_FWD_CFG);
1117 else
1118 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1119 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1120 FE_GDMA1_FWD_CFG);
1121 }
1122
1123 static void fe_txcsum_config(bool enable)
1124 {
1125 if (enable)
1126 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1127 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1128 FE_CDMA_CSG_CFG);
1129 else
1130 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1131 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1132 FE_CDMA_CSG_CFG);
1133 }
1134
1135 void fe_csum_config(struct fe_priv *priv)
1136 {
1137 struct net_device *dev = priv_netdev(priv);
1138
1139 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1140 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1141 }
1142
1143 static int fe_hw_init(struct net_device *dev)
1144 {
1145 struct fe_priv *priv = netdev_priv(dev);
1146 int i, err;
1147
1148 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1149 dev_name(priv->device), dev);
1150 if (err)
1151 return err;
1152
1153 if (priv->soc->set_mac)
1154 priv->soc->set_mac(priv, dev->dev_addr);
1155 else
1156 fe_hw_set_macaddr(priv, dev->dev_addr);
1157
1158 /* disable delay interrupt */
1159 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1160
1161 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1162
1163 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1164 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1165 for (i = 0; i < 16; i += 2)
1166 fe_w32(((i + 1) << 16) + i,
1167 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1168 (i * 2));
1169
1170 BUG_ON(!priv->soc->fwd_config);
1171 if (priv->soc->fwd_config(priv))
1172 netdev_err(dev, "unable to get clock\n");
1173
1174 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1175 fe_reg_w32(1, FE_REG_FE_RST_GL);
1176 fe_reg_w32(0, FE_REG_FE_RST_GL);
1177 }
1178
1179 return 0;
1180 }
1181
1182 static int fe_open(struct net_device *dev)
1183 {
1184 struct fe_priv *priv = netdev_priv(dev);
1185 unsigned long flags;
1186 u32 val;
1187 int err;
1188
1189 err = fe_init_dma(priv);
1190 if (err)
1191 goto err_out;
1192
1193 spin_lock_irqsave(&priv->page_lock, flags);
1194
1195 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1196 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1197 val |= FE_RX_2B_OFFSET;
1198 val |= priv->soc->pdma_glo_cfg;
1199 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1200
1201 spin_unlock_irqrestore(&priv->page_lock, flags);
1202
1203 if (priv->phy)
1204 priv->phy->start(priv);
1205
1206 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1207 netif_carrier_on(dev);
1208
1209 napi_enable(&priv->rx_napi);
1210 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1211 netif_start_queue(dev);
1212
1213 return 0;
1214
1215 err_out:
1216 fe_free_dma(priv);
1217 return err;
1218 }
1219
1220 static int fe_stop(struct net_device *dev)
1221 {
1222 struct fe_priv *priv = netdev_priv(dev);
1223 unsigned long flags;
1224 int i;
1225
1226 netif_tx_disable(dev);
1227 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1228 napi_disable(&priv->rx_napi);
1229
1230 if (priv->phy)
1231 priv->phy->stop(priv);
1232
1233 spin_lock_irqsave(&priv->page_lock, flags);
1234
1235 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1236 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1237 FE_REG_PDMA_GLO_CFG);
1238 spin_unlock_irqrestore(&priv->page_lock, flags);
1239
1240 /* wait dma stop */
1241 for (i = 0; i < 10; i++) {
1242 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1243 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1244 msleep(10);
1245 continue;
1246 }
1247 break;
1248 }
1249
1250 fe_free_dma(priv);
1251
1252 return 0;
1253 }
1254
1255 static int __init fe_init(struct net_device *dev)
1256 {
1257 struct fe_priv *priv = netdev_priv(dev);
1258 struct device_node *port;
1259 int err;
1260
1261 BUG_ON(!priv->soc->reset_fe);
1262 priv->soc->reset_fe();
1263
1264 if (priv->soc->switch_init)
1265 priv->soc->switch_init(priv);
1266
1267 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1268 /*If the mac address is invalid, use random mac address */
1269 if (!is_valid_ether_addr(dev->dev_addr)) {
1270 random_ether_addr(dev->dev_addr);
1271 dev_err(priv->device, "generated random MAC address %pM\n",
1272 dev->dev_addr);
1273 }
1274
1275 err = fe_mdio_init(priv);
1276 if (err)
1277 return err;
1278
1279 if (priv->soc->port_init)
1280 for_each_child_of_node(priv->device->of_node, port)
1281 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1282 priv->soc->port_init(priv, port);
1283
1284 if (priv->phy) {
1285 err = priv->phy->connect(priv);
1286 if (err)
1287 goto err_phy_disconnect;
1288 }
1289
1290 err = fe_hw_init(dev);
1291 if (err)
1292 goto err_phy_disconnect;
1293
1294 if (priv->soc->switch_config)
1295 priv->soc->switch_config(priv);
1296
1297 return 0;
1298
1299 err_phy_disconnect:
1300 if (priv->phy)
1301 priv->phy->disconnect(priv);
1302 fe_mdio_cleanup(priv);
1303
1304 return err;
1305 }
1306
1307 static void fe_uninit(struct net_device *dev)
1308 {
1309 struct fe_priv *priv = netdev_priv(dev);
1310
1311 if (priv->phy)
1312 priv->phy->disconnect(priv);
1313 fe_mdio_cleanup(priv);
1314
1315 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1316 free_irq(dev->irq, dev);
1317 }
1318
1319 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1320 {
1321 struct fe_priv *priv = netdev_priv(dev);
1322
1323 if (!priv->phy_dev)
1324 return -ENODEV;
1325
1326 switch (cmd) {
1327 case SIOCETHTOOL:
1328 return phy_ethtool_ioctl(priv->phy_dev,
1329 (void *) ifr->ifr_data);
1330 case SIOCGMIIPHY:
1331 case SIOCGMIIREG:
1332 case SIOCSMIIREG:
1333 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1334 default:
1335 break;
1336 }
1337
1338 return -EOPNOTSUPP;
1339 }
1340
1341 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1342 {
1343 struct fe_priv *priv = netdev_priv(dev);
1344 int frag_size, old_mtu;
1345 u32 fwd_cfg;
1346
1347 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1348 return eth_change_mtu(dev, new_mtu);
1349
1350 frag_size = fe_max_frag_size(new_mtu);
1351 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1352 return -EINVAL;
1353
1354 old_mtu = dev->mtu;
1355 dev->mtu = new_mtu;
1356
1357 /* return early if the buffer sizes will not change */
1358 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1359 return 0;
1360 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1361 return 0;
1362
1363 if (new_mtu <= ETH_DATA_LEN)
1364 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1365 else
1366 priv->rx_ring.frag_size = PAGE_SIZE;
1367 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1368
1369 if (!netif_running(dev))
1370 return 0;
1371
1372 fe_stop(dev);
1373 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1374 if (new_mtu <= ETH_DATA_LEN)
1375 fwd_cfg &= ~FE_GDM1_JMB_EN;
1376 else {
1377 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1378 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1379 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1380 }
1381 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1382
1383 return fe_open(dev);
1384 }
1385
1386 static const struct net_device_ops fe_netdev_ops = {
1387 .ndo_init = fe_init,
1388 .ndo_uninit = fe_uninit,
1389 .ndo_open = fe_open,
1390 .ndo_stop = fe_stop,
1391 .ndo_start_xmit = fe_start_xmit,
1392 .ndo_set_mac_address = fe_set_mac_address,
1393 .ndo_validate_addr = eth_validate_addr,
1394 .ndo_do_ioctl = fe_do_ioctl,
1395 .ndo_change_mtu = fe_change_mtu,
1396 .ndo_tx_timeout = fe_tx_timeout,
1397 .ndo_get_stats64 = fe_get_stats64,
1398 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1399 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1400 #ifdef CONFIG_NET_POLL_CONTROLLER
1401 .ndo_poll_controller = fe_poll_controller,
1402 #endif
1403 };
1404
1405 static void fe_reset_pending(struct fe_priv *priv)
1406 {
1407 struct net_device *dev = priv->netdev;
1408 int err;
1409
1410 rtnl_lock();
1411 fe_stop(dev);
1412
1413 err = fe_open(dev);
1414 if (err)
1415 goto error;
1416 rtnl_unlock();
1417
1418 return;
1419 error:
1420 netif_alert(priv, ifup, dev,
1421 "Driver up/down cycle failed, closing device.\n");
1422 dev_close(dev);
1423 rtnl_unlock();
1424 }
1425
1426 static const struct fe_work_t fe_work[] = {
1427 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1428 };
1429
1430 static void fe_pending_work(struct work_struct *work)
1431 {
1432 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1433 int i;
1434 bool pending;
1435
1436 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1437 pending = test_and_clear_bit(fe_work[i].bitnr,
1438 priv->pending_flags);
1439 if (pending)
1440 fe_work[i].action(priv);
1441 }
1442 }
1443
1444 static int fe_probe(struct platform_device *pdev)
1445 {
1446 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1447 const struct of_device_id *match;
1448 struct fe_soc_data *soc;
1449 struct net_device *netdev;
1450 struct fe_priv *priv;
1451 struct clk *sysclk;
1452 int err, napi_weight;
1453
1454 device_reset(&pdev->dev);
1455
1456 match = of_match_device(of_fe_match, &pdev->dev);
1457 soc = (struct fe_soc_data *) match->data;
1458
1459 if (soc->reg_table)
1460 fe_reg_table = soc->reg_table;
1461 else
1462 soc->reg_table = fe_reg_table;
1463
1464 fe_base = devm_ioremap_resource(&pdev->dev, res);
1465 if (!fe_base) {
1466 err = -EADDRNOTAVAIL;
1467 goto err_out;
1468 }
1469
1470 netdev = alloc_etherdev(sizeof(*priv));
1471 if (!netdev) {
1472 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1473 err = -ENOMEM;
1474 goto err_iounmap;
1475 }
1476
1477 SET_NETDEV_DEV(netdev, &pdev->dev);
1478 netdev->netdev_ops = &fe_netdev_ops;
1479 netdev->base_addr = (unsigned long) fe_base;
1480
1481 netdev->irq = platform_get_irq(pdev, 0);
1482 if (netdev->irq < 0) {
1483 dev_err(&pdev->dev, "no IRQ resource found\n");
1484 err = -ENXIO;
1485 goto err_free_dev;
1486 }
1487
1488 if (soc->init_data)
1489 soc->init_data(soc, netdev);
1490 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1491 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1492 netdev->vlan_features = netdev->hw_features &
1493 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1494 netdev->features |= netdev->hw_features;
1495
1496 /* fake rx vlan filter func. to support tx vlan offload func */
1497 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1498 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1499
1500 priv = netdev_priv(netdev);
1501 spin_lock_init(&priv->page_lock);
1502 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1503 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1504 if (!priv->hw_stats) {
1505 err = -ENOMEM;
1506 goto err_free_dev;
1507 }
1508 spin_lock_init(&priv->hw_stats->stats_lock);
1509 }
1510
1511 sysclk = devm_clk_get(&pdev->dev, NULL);
1512 if (!IS_ERR(sysclk))
1513 priv->sysclk = clk_get_rate(sysclk);
1514
1515 priv->netdev = netdev;
1516 priv->device = &pdev->dev;
1517 priv->soc = soc;
1518 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1519 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1520 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1521 priv->tx_ring.tx_ring_size = priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1522 INIT_WORK(&priv->pending_work, fe_pending_work);
1523
1524 napi_weight = 32;
1525 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1526 napi_weight *= 4;
1527 priv->tx_ring.tx_ring_size *= 4;
1528 priv->rx_ring.rx_ring_size *= 4;
1529 }
1530 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1531 fe_set_ethtool_ops(netdev);
1532
1533 err = register_netdev(netdev);
1534 if (err) {
1535 dev_err(&pdev->dev, "error bringing up device\n");
1536 goto err_free_dev;
1537 }
1538
1539 platform_set_drvdata(pdev, netdev);
1540
1541 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1542 netdev->base_addr, netdev->irq);
1543
1544 return 0;
1545
1546 err_free_dev:
1547 free_netdev(netdev);
1548 err_iounmap:
1549 devm_iounmap(&pdev->dev, fe_base);
1550 err_out:
1551 return err;
1552 }
1553
1554 static int fe_remove(struct platform_device *pdev)
1555 {
1556 struct net_device *dev = platform_get_drvdata(pdev);
1557 struct fe_priv *priv = netdev_priv(dev);
1558
1559 netif_napi_del(&priv->rx_napi);
1560 if (priv->hw_stats)
1561 kfree(priv->hw_stats);
1562
1563 cancel_work_sync(&priv->pending_work);
1564
1565 unregister_netdev(dev);
1566 free_netdev(dev);
1567 platform_set_drvdata(pdev, NULL);
1568
1569 return 0;
1570 }
1571
1572 static struct platform_driver fe_driver = {
1573 .probe = fe_probe,
1574 .remove = fe_remove,
1575 .driver = {
1576 .name = "ralink_soc_eth",
1577 .owner = THIS_MODULE,
1578 .of_match_table = of_fe_match,
1579 },
1580 };
1581
1582 static int __init init_rtfe(void)
1583 {
1584 int ret;
1585
1586 ret = rtesw_init();
1587 if (ret)
1588 return ret;
1589
1590 ret = platform_driver_register(&fe_driver);
1591 if (ret)
1592 rtesw_exit();
1593
1594 return ret;
1595 }
1596
1597 static void __exit exit_rtfe(void)
1598 {
1599 platform_driver_unregister(&fe_driver);
1600 rtesw_exit();
1601 }
1602
1603 module_init(init_rtfe);
1604 module_exit(exit_rtfe);
1605
1606 MODULE_LICENSE("GPL");
1607 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1608 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1609 MODULE_VERSION(FE_DRV_VERSION);
OpenWrt SVN history