projects / openwrt / svn-archive / archive.git / blob
? search:


925cc4cc6b6aae65b9696408b1939ceb791a99d2
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define TX_TIMEOUT (2 * HZ)
44 #define MAX_RX_LENGTH 1536
45 #define FE_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
46 #define FE_RX_HLEN (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
47 ETH_FCS_LEN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
50 (NETIF_MSG_DRV | \
51 NETIF_MSG_PROBE | \
52 NETIF_MSG_LINK | \
53 NETIF_MSG_TIMER | \
54 NETIF_MSG_IFDOWN | \
55 NETIF_MSG_IFUP | \
56 NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR)
58
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u32 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
78 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
79 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
80 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
81 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
82 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
83 };
84
85 static const u32 *fe_reg_table = fe_reg_table_default;
86
87 static void __iomem *fe_base = 0;
88
89 void fe_w32(u32 val, unsigned reg)
90 {
91 __raw_writel(val, fe_base + reg);
92 }
93
94 u32 fe_r32(unsigned reg)
95 {
96 return __raw_readl(fe_base + reg);
97 }
98
99 void fe_reg_w32(u32 val, enum fe_reg reg)
100 {
101 fe_w32(val, fe_reg_table[reg]);
102 }
103
104 u32 fe_reg_r32(enum fe_reg reg)
105 {
106 return fe_r32(fe_reg_table[reg]);
107 }
108
109 static inline void fe_int_disable(u32 mask)
110 {
111 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
112 FE_REG_FE_INT_ENABLE);
113 /* flush write */
114 fe_reg_r32(FE_REG_FE_INT_ENABLE);
115 }
116
117 static inline void fe_int_enable(u32 mask)
118 {
119 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
120 FE_REG_FE_INT_ENABLE);
121 /* flush write */
122 fe_reg_r32(FE_REG_FE_INT_ENABLE);
123 }
124
125 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
126 {
127 unsigned long flags;
128
129 spin_lock_irqsave(&priv->page_lock, flags);
130 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
131 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
132 FE_GDMA1_MAC_ADRL);
133 spin_unlock_irqrestore(&priv->page_lock, flags);
134 }
135
136 static int fe_set_mac_address(struct net_device *dev, void *p)
137 {
138 int ret = eth_mac_addr(dev, p);
139
140 if (!ret) {
141 struct fe_priv *priv = netdev_priv(dev);
142
143 if (priv->soc->set_mac)
144 priv->soc->set_mac(priv, dev->dev_addr);
145 else
146 fe_hw_set_macaddr(priv, p);
147 }
148
149 return ret;
150 }
151
152 static inline int fe_max_frag_size(int mtu)
153 {
154 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
155 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
156 }
157
158 static inline int fe_max_buf_size(int frag_size)
159 {
160 return frag_size - FE_RX_HLEN -
161 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
162 }
163
164 static void fe_clean_rx(struct fe_priv *priv)
165 {
166 int i;
167
168 if (priv->rx_data) {
169 for (i = 0; i < NUM_DMA_DESC; i++)
170 if (priv->rx_data[i]) {
171 if (priv->rx_dma && priv->rx_dma[i].rxd1)
172 dma_unmap_single(&priv->netdev->dev,
173 priv->rx_dma[i].rxd1,
174 priv->rx_buf_size,
175 DMA_FROM_DEVICE);
176 put_page(virt_to_head_page(priv->rx_data[i]));
177 }
178
179 kfree(priv->rx_data);
180 priv->rx_data = NULL;
181 }
182
183 if (priv->rx_dma) {
184 dma_free_coherent(&priv->netdev->dev,
185 NUM_DMA_DESC * sizeof(*priv->rx_dma),
186 priv->rx_dma,
187 priv->rx_phys);
188 priv->rx_dma = NULL;
189 }
190 }
191
192 static int fe_alloc_rx(struct fe_priv *priv)
193 {
194 struct net_device *netdev = priv->netdev;
195 int i;
196
197 priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
198 GFP_KERNEL);
199 if (!priv->rx_data)
200 goto no_rx_mem;
201
202 for (i = 0; i < NUM_DMA_DESC; i++) {
203 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
204 if (!priv->rx_data[i])
205 goto no_rx_mem;
206 }
207
208 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
209 NUM_DMA_DESC * sizeof(*priv->rx_dma),
210 &priv->rx_phys,
211 GFP_ATOMIC | __GFP_ZERO);
212 if (!priv->rx_dma)
213 goto no_rx_mem;
214
215 for (i = 0; i < NUM_DMA_DESC; i++) {
216 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
217 priv->rx_data[i] + FE_RX_OFFSET,
218 priv->rx_buf_size,
219 DMA_FROM_DEVICE);
220 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
221 goto no_rx_mem;
222 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
223
224 if (priv->soc->rx_dma)
225 priv->soc->rx_dma(priv, i, priv->rx_buf_size);
226 else
227 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
228 }
229 wmb();
230
231 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
232 fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
233 fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
234 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
235
236 return 0;
237
238 no_rx_mem:
239 return -ENOMEM;
240 }
241
242 static void fe_clean_tx(struct fe_priv *priv)
243 {
244 int i;
245
246 if (priv->tx_skb) {
247 for (i = 0; i < NUM_DMA_DESC; i++) {
248 if (priv->tx_skb[i])
249 dev_kfree_skb_any(priv->tx_skb[i]);
250 }
251 kfree(priv->tx_skb);
252 priv->tx_skb = NULL;
253 }
254
255 if (priv->tx_dma) {
256 dma_free_coherent(&priv->netdev->dev,
257 NUM_DMA_DESC * sizeof(*priv->tx_dma),
258 priv->tx_dma,
259 priv->tx_phys);
260 priv->tx_dma = NULL;
261 }
262 }
263
264 static int fe_alloc_tx(struct fe_priv *priv)
265 {
266 int i;
267
268 priv->tx_free_idx = 0;
269
270 priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
271 GFP_KERNEL);
272 if (!priv->tx_skb)
273 goto no_tx_mem;
274
275 priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
276 NUM_DMA_DESC * sizeof(*priv->tx_dma),
277 &priv->tx_phys,
278 GFP_ATOMIC | __GFP_ZERO);
279 if (!priv->tx_dma)
280 goto no_tx_mem;
281
282 for (i = 0; i < NUM_DMA_DESC; i++) {
283 if (priv->soc->tx_dma) {
284 priv->soc->tx_dma(priv, i, NULL);
285 continue;
286 }
287 priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
288 }
289 wmb();
290
291 fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
292 fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
293 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
294 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
295
296 return 0;
297
298 no_tx_mem:
299 return -ENOMEM;
300 }
301
302 static int fe_init_dma(struct fe_priv *priv)
303 {
304 int err;
305
306 err = fe_alloc_tx(priv);
307 if (err)
308 return err;
309
310 err = fe_alloc_rx(priv);
311 if (err)
312 return err;
313
314 return 0;
315 }
316
317 static void fe_free_dma(struct fe_priv *priv)
318 {
319 fe_clean_tx(priv);
320 fe_clean_rx(priv);
321
322 netdev_reset_queue(priv->netdev);
323 }
324
325 static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
326 {
327 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
328 dma_unmap_single(dev, txd->txd1,
329 TX_DMA_GET_PLEN0(txd->txd2),
330 DMA_TO_DEVICE);
331 }
332
333 static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
334 {
335 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
336 dma_unmap_page(dev, txd->txd1,
337 TX_DMA_GET_PLEN0(txd->txd2),
338 DMA_TO_DEVICE);
339 }
340
341 static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
342 {
343 if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
344 dma_unmap_page(dev, txd->txd3,
345 TX_DMA_GET_PLEN1(txd->txd2),
346 DMA_TO_DEVICE);
347 }
348
349 void fe_stats_update(struct fe_priv *priv)
350 {
351 struct fe_hw_stats *hwstats = priv->hw_stats;
352 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
353
354 u64_stats_update_begin(&hwstats->syncp);
355
356 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
357 hwstats->rx_bytes += fe_r32(base);
358 hwstats->rx_packets += fe_r32(base + 0x08);
359 hwstats->rx_overflow += fe_r32(base + 0x10);
360 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
361 hwstats->rx_short_errors += fe_r32(base + 0x18);
362 hwstats->rx_long_errors += fe_r32(base + 0x1c);
363 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
364 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
365 hwstats->tx_skip += fe_r32(base + 0x28);
366 hwstats->tx_collisions += fe_r32(base + 0x2c);
367 hwstats->tx_bytes += fe_r32(base + 0x30);
368 hwstats->tx_packets += fe_r32(base + 0x38);
369 } else {
370 hwstats->tx_bytes += fe_r32(base);
371 hwstats->tx_packets += fe_r32(base + 0x04);
372 hwstats->tx_skip += fe_r32(base + 0x08);
373 hwstats->tx_collisions += fe_r32(base + 0x0c);
374 hwstats->rx_bytes += fe_r32(base + 0x20);
375 hwstats->rx_packets += fe_r32(base + 0x24);
376 hwstats->rx_overflow += fe_r32(base + 0x28);
377 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
378 hwstats->rx_short_errors += fe_r32(base + 0x30);
379 hwstats->rx_long_errors += fe_r32(base + 0x34);
380 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
381 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
382 }
383
384 u64_stats_update_end(&hwstats->syncp);
385 }
386
387 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
388 struct rtnl_link_stats64 *storage)
389 {
390 struct fe_priv *priv = netdev_priv(dev);
391 struct fe_hw_stats *hwstats = priv->hw_stats;
392 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
393 unsigned int start;
394
395 if (!base) {
396 netdev_stats_to_stats64(storage, &dev->stats);
397 return storage;
398 }
399
400 if (netif_running(dev) && netif_device_present(dev)) {
401 if (spin_trylock(&hwstats->stats_lock)) {
402 fe_stats_update(priv);
403 spin_unlock(&hwstats->stats_lock);
404 }
405 }
406
407 do {
408 start = u64_stats_fetch_begin_bh(&hwstats->syncp);
409 storage->rx_packets = hwstats->rx_packets;
410 storage->tx_packets = hwstats->tx_packets;
411 storage->rx_bytes = hwstats->rx_bytes;
412 storage->tx_bytes = hwstats->tx_bytes;
413 storage->collisions = hwstats->tx_collisions;
414 storage->rx_length_errors = hwstats->rx_short_errors +
415 hwstats->rx_long_errors;
416 storage->rx_over_errors = hwstats->rx_overflow;
417 storage->rx_crc_errors = hwstats->rx_fcs_errors;
418 storage->rx_errors = hwstats->rx_checksum_errors;
419 storage->tx_aborted_errors = hwstats->tx_skip;
420 } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
421
422 storage->tx_errors = priv->netdev->stats.tx_errors;
423 storage->rx_dropped = priv->netdev->stats.rx_dropped;
424 storage->tx_dropped = priv->netdev->stats.tx_dropped;
425
426 return storage;
427 }
428
429 static int fe_vlan_rx_add_vid(struct net_device *dev,
430 __be16 proto, u16 vid)
431 {
432 struct fe_priv *priv = netdev_priv(dev);
433 u32 idx = (vid & 0xf);
434 u32 vlan_cfg;
435
436 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
437 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
438 return 0;
439
440 if (test_bit(idx, &priv->vlan_map)) {
441 netdev_warn(dev, "disable tx vlan offload\n");
442 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
443 netdev_update_features(dev);
444 } else {
445 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
446 ((idx >> 1) << 2));
447 if (idx & 0x1) {
448 vlan_cfg &= 0xffff;
449 vlan_cfg |= (vid << 16);
450 } else {
451 vlan_cfg &= 0xffff0000;
452 vlan_cfg |= vid;
453 }
454 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
455 ((idx >> 1) << 2));
456 set_bit(idx, &priv->vlan_map);
457 }
458
459 return 0;
460 }
461
462 static int fe_vlan_rx_kill_vid(struct net_device *dev,
463 __be16 proto, u16 vid)
464 {
465 struct fe_priv *priv = netdev_priv(dev);
466 u32 idx = (vid & 0xf);
467
468 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
469 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
470 return 0;
471
472 clear_bit(idx, &priv->vlan_map);
473
474 return 0;
475 }
476
477 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
478 int idx)
479 {
480 struct fe_priv *priv = netdev_priv(dev);
481 struct skb_frag_struct *frag;
482 struct fe_tx_dma *txd;
483 dma_addr_t mapped_addr;
484 unsigned int nr_frags;
485 u32 def_txd4, txd2;
486 int i, j, unmap_idx, tx_num;
487
488 txd = &priv->tx_dma[idx];
489 nr_frags = skb_shinfo(skb)->nr_frags;
490 tx_num = 1 + (nr_frags >> 1);
491
492 /* init tx descriptor */
493 if (priv->soc->tx_dma)
494 priv->soc->tx_dma(priv, idx, skb);
495 else
496 txd->txd4 = TX_DMA_DESP4_DEF;
497 def_txd4 = txd->txd4;
498
499 /* use dma_unmap_single to free it */
500 txd->txd4 |= priv->soc->tx_udf_bit;
501
502 /* TX Checksum offload */
503 if (skb->ip_summed == CHECKSUM_PARTIAL)
504 txd->txd4 |= TX_DMA_CHKSUM;
505
506 /* VLAN header offload */
507 if (vlan_tx_tag_present(skb)) {
508 if (IS_ENABLED(CONFIG_SOC_MT7621))
509 txd->txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
510 else
511 txd->txd4 |= TX_DMA_INS_VLAN |
512 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
513 (vlan_tx_tag_get(skb) & 0xF);
514 }
515
516 /* TSO: fill MSS info in tcp checksum field */
517 if (skb_is_gso(skb)) {
518 if (skb_cow_head(skb, 0)) {
519 netif_warn(priv, tx_err, dev,
520 "GSO expand head fail.\n");
521 goto err_out;
522 }
523 if (skb_shinfo(skb)->gso_type &
524 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
525 txd->txd4 |= TX_DMA_TSO;
526 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
527 }
528 }
529
530 mapped_addr = dma_map_single(&dev->dev, skb->data,
531 skb_headlen(skb), DMA_TO_DEVICE);
532 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
533 goto err_out;
534 txd->txd1 = mapped_addr;
535 txd2 = TX_DMA_PLEN0(skb_headlen(skb));
536
537 /* TX SG offload */
538 j = idx;
539 for (i = 0; i < nr_frags; i++) {
540
541 frag = &skb_shinfo(skb)->frags[i];
542 mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
543 skb_frag_size(frag), DMA_TO_DEVICE);
544 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
545 goto err_dma;
546
547 if (i & 0x1) {
548 j = NEXT_TX_DESP_IDX(j);
549 txd = &priv->tx_dma[j];
550 txd->txd1 = mapped_addr;
551 txd2 = TX_DMA_PLEN0(frag->size);
552 txd->txd4 = def_txd4;
553 } else {
554 txd->txd3 = mapped_addr;
555 txd2 |= TX_DMA_PLEN1(frag->size);
556 if (i != (nr_frags -1))
557 txd->txd2 = txd2;
558 priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
559 }
560 }
561
562 /* set last segment */
563 if (nr_frags & 0x1)
564 txd->txd2 = (txd2 | TX_DMA_LS1);
565 else
566 txd->txd2 = (txd2 | TX_DMA_LS0);
567
568 /* store skb to cleanup */
569 priv->tx_skb[j] = skb;
570
571 netdev_sent_queue(dev, skb->len);
572 skb_tx_timestamp(skb);
573
574 wmb();
575 j = NEXT_TX_DESP_IDX(j);
576 fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
577
578 return 0;
579
580 err_dma:
581 /* unmap dma */
582 txd = &priv->tx_dma[idx];
583 txd_unmap_single(&dev->dev, txd);
584
585 j = idx;
586 unmap_idx = i;
587 for (i = 0; i < unmap_idx; i++) {
588 if (i & 0x1) {
589 j = NEXT_TX_DESP_IDX(j);
590 txd = &priv->tx_dma[j];
591 txd_unmap_page0(&dev->dev, txd);
592 } else {
593 txd_unmap_page1(&dev->dev, txd);
594 }
595 }
596
597 err_out:
598 /* reinit descriptors and skb */
599 j = idx;
600 for (i = 0; i < tx_num; i++) {
601 priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
602 priv->tx_skb[j] = NULL;
603 j = NEXT_TX_DESP_IDX(j);
604 }
605 wmb();
606
607 return -1;
608 }
609
610 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
611 unsigned int len;
612 int ret;
613
614 ret = 0;
615 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
616 if ((priv->flags & FE_FLAG_PADDING_64B) &&
617 !(priv->flags & FE_FLAG_PADDING_BUG))
618 return ret;
619
620 if (vlan_tx_tag_present(skb))
621 len = ETH_ZLEN;
622 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
623 len = VLAN_ETH_ZLEN;
624 else if(!(priv->flags & FE_FLAG_PADDING_64B))
625 len = ETH_ZLEN;
626 else
627 return ret;
628
629 if (skb->len < len) {
630 if ((ret = skb_pad(skb, len - skb->len)) < 0)
631 return ret;
632 skb->len = len;
633 skb_set_tail_pointer(skb, len);
634 }
635 }
636
637 return ret;
638 }
639
640 static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
641 {
642 return (u32)(NUM_DMA_DESC - ((tx_fill_idx - priv->tx_free_idx) &
643 (NUM_DMA_DESC - 1)));
644 }
645
646 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
647 {
648 struct fe_priv *priv = netdev_priv(dev);
649 struct net_device_stats *stats = &dev->stats;
650 u32 tx;
651 int tx_num;
652 int len = skb->len;
653
654 if (fe_skb_padto(skb, priv)) {
655 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
656 return NETDEV_TX_OK;
657 }
658
659 spin_lock(&priv->page_lock);
660 tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
661 tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
662 if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
663 {
664 netif_stop_queue(dev);
665 spin_unlock(&priv->page_lock);
666 netif_err(priv, tx_queued,dev,
667 "Tx Ring full when queue awake!\n");
668 return NETDEV_TX_BUSY;
669 }
670
671 if (fe_tx_map_dma(skb, dev, tx) < 0) {
672 kfree_skb(skb);
673
674 stats->tx_dropped++;
675 } else {
676 stats->tx_packets++;
677 stats->tx_bytes += len;
678 }
679
680 spin_unlock(&priv->page_lock);
681
682 return NETDEV_TX_OK;
683 }
684
685 static inline void fe_rx_vlan(struct sk_buff *skb)
686 {
687 struct ethhdr *ehdr;
688 u16 vlanid;
689
690 if (!__vlan_get_tag(skb, &vlanid)) {
691 /* pop the vlan tag */
692 ehdr = (struct ethhdr *)skb->data;
693 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
694 skb_pull(skb, VLAN_HLEN);
695 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
696 }
697 }
698
699 static int fe_poll_rx(struct napi_struct *napi, int budget,
700 struct fe_priv *priv)
701 {
702 struct net_device *netdev = priv->netdev;
703 struct net_device_stats *stats = &netdev->stats;
704 struct fe_soc_data *soc = priv->soc;
705 u32 checksum_bit;
706 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
707 struct sk_buff *skb;
708 u8 *data, *new_data;
709 struct fe_rx_dma *rxd;
710 int done = 0;
711 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
712
713 if (netdev->features & NETIF_F_RXCSUM)
714 checksum_bit = soc->checksum_bit;
715 else
716 checksum_bit = 0;
717
718 while (done < budget) {
719 unsigned int pktlen;
720 dma_addr_t dma_addr;
721 idx = NEXT_RX_DESP_IDX(idx);
722 rxd = &priv->rx_dma[idx];
723 data = priv->rx_data[idx];
724
725 if (!(rxd->rxd2 & RX_DMA_DONE))
726 break;
727
728 /* alloc new buffer */
729 new_data = netdev_alloc_frag(priv->frag_size);
730 if (unlikely(!new_data)) {
731 stats->rx_dropped++;
732 goto release_desc;
733 }
734 dma_addr = dma_map_single(&netdev->dev,
735 new_data + FE_RX_OFFSET,
736 priv->rx_buf_size,
737 DMA_FROM_DEVICE);
738 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
739 put_page(virt_to_head_page(new_data));
740 goto release_desc;
741 }
742
743 /* receive data */
744 skb = build_skb(data, priv->frag_size);
745 if (unlikely(!skb)) {
746 put_page(virt_to_head_page(new_data));
747 goto release_desc;
748 }
749 skb_reserve(skb, FE_RX_OFFSET);
750
751 dma_unmap_single(&netdev->dev, rxd->rxd1,
752 priv->rx_buf_size, DMA_FROM_DEVICE);
753 pktlen = RX_DMA_PLEN0(rxd->rxd2);
754 skb_put(skb, pktlen);
755 skb->dev = netdev;
756 if (rxd->rxd4 & checksum_bit) {
757 skb->ip_summed = CHECKSUM_UNNECESSARY;
758 } else {
759 skb_checksum_none_assert(skb);
760 }
761 if (rx_vlan)
762 fe_rx_vlan(skb);
763 skb->protocol = eth_type_trans(skb, netdev);
764
765 stats->rx_packets++;
766 stats->rx_bytes += pktlen;
767
768 if (skb->ip_summed == CHECKSUM_NONE)
769 netif_receive_skb(skb);
770 else
771 napi_gro_receive(napi, skb);
772
773 priv->rx_data[idx] = new_data;
774 rxd->rxd1 = (unsigned int) dma_addr;
775
776 release_desc:
777 if (soc->rx_dma)
778 soc->rx_dma(priv, idx, priv->rx_buf_size);
779 else
780 rxd->rxd2 = RX_DMA_LSO;
781
782 wmb();
783 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
784 done++;
785 }
786
787 return done;
788 }
789
790 static int fe_poll_tx(struct fe_priv *priv, int budget)
791 {
792 struct net_device *netdev = priv->netdev;
793 struct device *dev = &netdev->dev;
794 unsigned int bytes_compl = 0;
795 struct sk_buff *skb;
796 struct fe_tx_dma *txd;
797 int done = 0, idx;
798 u32 udf_bit = priv->soc->tx_udf_bit;
799
800 idx = priv->tx_free_idx;
801 while (done < budget) {
802 txd = &priv->tx_dma[idx];
803 skb = priv->tx_skb[idx];
804
805 if (!(txd->txd2 & TX_DMA_DONE) || !skb)
806 break;
807
808 txd_unmap_page1(dev, txd);
809
810 if (txd->txd4 & udf_bit)
811 txd_unmap_single(dev, txd);
812 else
813 txd_unmap_page0(dev, txd);
814
815 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
816 bytes_compl += skb->len;
817 dev_kfree_skb_any(skb);
818 done++;
819 }
820 priv->tx_skb[idx] = NULL;
821 idx = NEXT_TX_DESP_IDX(idx);
822 }
823 priv->tx_free_idx = idx;
824
825 if (!done)
826 return 0;
827
828 netdev_completed_queue(netdev, done, bytes_compl);
829 if (unlikely(netif_queue_stopped(netdev) &&
830 netif_carrier_ok(netdev))) {
831 netif_wake_queue(netdev);
832 }
833
834 return done;
835 }
836
837 static int fe_poll(struct napi_struct *napi, int budget)
838 {
839 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
840 struct fe_hw_stats *hwstat = priv->hw_stats;
841 int tx_done, rx_done;
842 u32 status, mask;
843 u32 tx_intr, rx_intr;
844
845 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
846 tx_intr = priv->soc->tx_int;
847 rx_intr = priv->soc->rx_int;
848 tx_done = rx_done = 0;
849
850 poll_again:
851 if (status & tx_intr) {
852 tx_done += fe_poll_tx(priv, budget - tx_done);
853 if (tx_done < budget) {
854 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
855 }
856 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
857 }
858
859 if (status & rx_intr) {
860 rx_done += fe_poll_rx(napi, budget - rx_done, priv);
861 if (rx_done < budget) {
862 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
863 }
864 }
865
866 if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
867 if (spin_trylock(&hwstat->stats_lock)) {
868 fe_stats_update(priv);
869 spin_unlock(&hwstat->stats_lock);
870 }
871 fe_reg_w32(FE_CNT_GDM_AF, FE_REG_FE_INT_STATUS);
872 }
873
874 if (unlikely(netif_msg_intr(priv))) {
875 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
876 netdev_info(priv->netdev,
877 "done tx %d, rx %d, intr 0x%x/0x%x\n",
878 tx_done, rx_done, status, mask);
879 }
880
881 if ((tx_done < budget) && (rx_done < budget)) {
882 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
883 if (status & (tx_intr | rx_intr )) {
884 goto poll_again;
885 }
886 napi_complete(napi);
887 fe_int_enable(tx_intr | rx_intr);
888 }
889
890 return rx_done;
891 }
892
893 static void fe_tx_timeout(struct net_device *dev)
894 {
895 struct fe_priv *priv = netdev_priv(dev);
896
897 priv->netdev->stats.tx_errors++;
898 netif_err(priv, tx_err, dev,
899 "transmit timed out, waking up the queue\n");
900 netif_info(priv, drv, dev, ": dma_cfg:%08x, free_idx:%d, " \
901 "dma_ctx_idx=%u, dma_crx_idx=%u\n",
902 fe_reg_r32(FE_REG_PDMA_GLO_CFG), priv->tx_free_idx,
903 fe_reg_r32(FE_REG_TX_CTX_IDX0),
904 fe_reg_r32(FE_REG_RX_CALC_IDX0));
905 netif_wake_queue(dev);
906 }
907
908 static irqreturn_t fe_handle_irq(int irq, void *dev)
909 {
910 struct fe_priv *priv = netdev_priv(dev);
911 u32 status, int_mask;
912
913 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
914
915 if (unlikely(!status))
916 return IRQ_NONE;
917
918 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
919 if (likely(status & int_mask)) {
920 fe_int_disable(int_mask);
921 napi_schedule(&priv->rx_napi);
922 } else {
923 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
924 }
925
926 return IRQ_HANDLED;
927 }
928
929 #ifdef CONFIG_NET_POLL_CONTROLLER
930 static void fe_poll_controller(struct net_device *dev)
931 {
932 struct fe_priv *priv = netdev_priv(dev);
933 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
934
935 fe_int_disable(int_mask);
936 fe_handle_irq(dev->irq, dev);
937 fe_int_enable(int_mask);
938 }
939 #endif
940
941 int fe_set_clock_cycle(struct fe_priv *priv)
942 {
943 unsigned long sysclk = priv->sysclk;
944
945 if (!sysclk) {
946 return -EINVAL;
947 }
948
949 sysclk /= FE_US_CYC_CNT_DIVISOR;
950 sysclk <<= FE_US_CYC_CNT_SHIFT;
951
952 fe_w32((fe_r32(FE_FE_GLO_CFG) &
953 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
954 sysclk,
955 FE_FE_GLO_CFG);
956 return 0;
957 }
958
959 void fe_fwd_config(struct fe_priv *priv)
960 {
961 u32 fwd_cfg;
962
963 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
964
965 /* disable jumbo frame */
966 if (priv->flags & FE_FLAG_JUMBO_FRAME)
967 fwd_cfg &= ~FE_GDM1_JMB_EN;
968
969 /* set unicast/multicast/broadcast frame to cpu */
970 fwd_cfg &= ~0xffff;
971
972 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
973 }
974
975 static void fe_rxcsum_config(bool enable)
976 {
977 if (enable)
978 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
979 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
980 FE_GDMA1_FWD_CFG);
981 else
982 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
983 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
984 FE_GDMA1_FWD_CFG);
985 }
986
987 static void fe_txcsum_config(bool enable)
988 {
989 if (enable)
990 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
991 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
992 FE_CDMA_CSG_CFG);
993 else
994 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
995 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
996 FE_CDMA_CSG_CFG);
997 }
998
999 void fe_csum_config(struct fe_priv *priv)
1000 {
1001 struct net_device *dev = priv_netdev(priv);
1002
1003 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1004 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1005 }
1006
1007 static int fe_hw_init(struct net_device *dev)
1008 {
1009 struct fe_priv *priv = netdev_priv(dev);
1010 int i, err;
1011
1012 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1013 dev_name(priv->device), dev);
1014 if (err)
1015 return err;
1016
1017 if (priv->soc->set_mac)
1018 priv->soc->set_mac(priv, dev->dev_addr);
1019 else
1020 fe_hw_set_macaddr(priv, dev->dev_addr);
1021
1022 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1023
1024 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1025 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1026 for (i = 0; i < 16; i += 2)
1027 fe_w32(((i + 1) << 16) + i,
1028 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1029 (i * 2));
1030
1031 BUG_ON(!priv->soc->fwd_config);
1032 if (priv->soc->fwd_config(priv))
1033 netdev_err(dev, "unable to get clock\n");
1034
1035 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1036 fe_reg_w32(1, FE_REG_FE_RST_GL);
1037 fe_reg_w32(0, FE_REG_FE_RST_GL);
1038 }
1039
1040 return 0;
1041 }
1042
1043 static int fe_open(struct net_device *dev)
1044 {
1045 struct fe_priv *priv = netdev_priv(dev);
1046 unsigned long flags;
1047 u32 val;
1048 int err;
1049
1050 err = fe_init_dma(priv);
1051 if (err)
1052 goto err_out;
1053
1054 spin_lock_irqsave(&priv->page_lock, flags);
1055 napi_enable(&priv->rx_napi);
1056
1057 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1058 val |= priv->soc->pdma_glo_cfg;
1059 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1060
1061 spin_unlock_irqrestore(&priv->page_lock, flags);
1062
1063 if (priv->phy)
1064 priv->phy->start(priv);
1065
1066 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1067 netif_carrier_on(dev);
1068
1069 netif_start_queue(dev);
1070 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1071
1072 return 0;
1073
1074 err_out:
1075 fe_free_dma(priv);
1076 return err;
1077 }
1078
1079 static int fe_stop(struct net_device *dev)
1080 {
1081 struct fe_priv *priv = netdev_priv(dev);
1082 unsigned long flags;
1083 int i;
1084
1085 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1086
1087 netif_tx_disable(dev);
1088
1089 if (priv->phy)
1090 priv->phy->stop(priv);
1091
1092 spin_lock_irqsave(&priv->page_lock, flags);
1093 napi_disable(&priv->rx_napi);
1094
1095 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1096 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1097 FE_REG_PDMA_GLO_CFG);
1098 spin_unlock_irqrestore(&priv->page_lock, flags);
1099
1100 /* wait dma stop */
1101 for (i = 0; i < 10; i++) {
1102 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1103 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1104 msleep(10);
1105 continue;
1106 }
1107 break;
1108 }
1109
1110 fe_free_dma(priv);
1111
1112 return 0;
1113 }
1114
1115 static int __init fe_init(struct net_device *dev)
1116 {
1117 struct fe_priv *priv = netdev_priv(dev);
1118 struct device_node *port;
1119 int err;
1120
1121 BUG_ON(!priv->soc->reset_fe);
1122 priv->soc->reset_fe();
1123
1124 if (priv->soc->switch_init)
1125 priv->soc->switch_init(priv);
1126
1127 memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
1128 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1129
1130 err = fe_mdio_init(priv);
1131 if (err)
1132 return err;
1133
1134 if (priv->soc->port_init)
1135 for_each_child_of_node(priv->device->of_node, port)
1136 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1137 priv->soc->port_init(priv, port);
1138
1139 if (priv->phy) {
1140 err = priv->phy->connect(priv);
1141 if (err)
1142 goto err_phy_disconnect;
1143 }
1144
1145 err = fe_hw_init(dev);
1146 if (err)
1147 goto err_phy_disconnect;
1148
1149 if (priv->soc->switch_config)
1150 priv->soc->switch_config(priv);
1151
1152 return 0;
1153
1154 err_phy_disconnect:
1155 if (priv->phy)
1156 priv->phy->disconnect(priv);
1157 fe_mdio_cleanup(priv);
1158
1159 return err;
1160 }
1161
1162 static void fe_uninit(struct net_device *dev)
1163 {
1164 struct fe_priv *priv = netdev_priv(dev);
1165
1166 if (priv->phy)
1167 priv->phy->disconnect(priv);
1168 fe_mdio_cleanup(priv);
1169
1170 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1171 free_irq(dev->irq, dev);
1172 }
1173
1174 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1175 {
1176 struct fe_priv *priv = netdev_priv(dev);
1177
1178 if (!priv->phy_dev)
1179 return -ENODEV;
1180
1181 switch (cmd) {
1182 case SIOCETHTOOL:
1183 return phy_ethtool_ioctl(priv->phy_dev,
1184 (void *) ifr->ifr_data);
1185 case SIOCGMIIPHY:
1186 case SIOCGMIIREG:
1187 case SIOCSMIIREG:
1188 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1189 default:
1190 break;
1191 }
1192
1193 return -EOPNOTSUPP;
1194 }
1195
1196 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1197 {
1198 struct fe_priv *priv = netdev_priv(dev);
1199 int frag_size, old_mtu;
1200 u32 fwd_cfg;
1201
1202 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1203 return eth_change_mtu(dev, new_mtu);
1204
1205 frag_size = fe_max_frag_size(new_mtu);
1206 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1207 return -EINVAL;
1208
1209 old_mtu = dev->mtu;
1210 dev->mtu = new_mtu;
1211
1212 /* return early if the buffer sizes will not change */
1213 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1214 return 0;
1215 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1216 return 0;
1217
1218 if (new_mtu <= ETH_DATA_LEN) {
1219 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1220 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1221 } else {
1222 priv->frag_size = PAGE_SIZE;
1223 priv->rx_buf_size = fe_max_buf_size(PAGE_SIZE);
1224 }
1225
1226 if (!netif_running(dev))
1227 return 0;
1228
1229 fe_stop(dev);
1230 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1231 if (new_mtu <= ETH_DATA_LEN)
1232 fwd_cfg &= ~FE_GDM1_JMB_EN;
1233 else {
1234 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1235 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1236 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1237 }
1238 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1239
1240 return fe_open(dev);
1241 }
1242
1243 static const struct net_device_ops fe_netdev_ops = {
1244 .ndo_init = fe_init,
1245 .ndo_uninit = fe_uninit,
1246 .ndo_open = fe_open,
1247 .ndo_stop = fe_stop,
1248 .ndo_start_xmit = fe_start_xmit,
1249 .ndo_set_mac_address = fe_set_mac_address,
1250 .ndo_validate_addr = eth_validate_addr,
1251 .ndo_do_ioctl = fe_do_ioctl,
1252 .ndo_change_mtu = fe_change_mtu,
1253 .ndo_tx_timeout = fe_tx_timeout,
1254 .ndo_get_stats64 = fe_get_stats64,
1255 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1256 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1257 #ifdef CONFIG_NET_POLL_CONTROLLER
1258 .ndo_poll_controller = fe_poll_controller,
1259 #endif
1260 };
1261
1262 static int fe_probe(struct platform_device *pdev)
1263 {
1264 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1265 const struct of_device_id *match;
1266 struct fe_soc_data *soc;
1267 struct net_device *netdev;
1268 struct fe_priv *priv;
1269 struct clk *sysclk;
1270 int err;
1271
1272 device_reset(&pdev->dev);
1273
1274 match = of_match_device(of_fe_match, &pdev->dev);
1275 soc = (struct fe_soc_data *) match->data;
1276
1277 if (soc->reg_table)
1278 fe_reg_table = soc->reg_table;
1279 else
1280 soc->reg_table = fe_reg_table;
1281
1282 fe_base = devm_request_and_ioremap(&pdev->dev, res);
1283 if (!fe_base) {
1284 err = -EADDRNOTAVAIL;
1285 goto err_out;
1286 }
1287
1288 netdev = alloc_etherdev(sizeof(*priv));
1289 if (!netdev) {
1290 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1291 err = -ENOMEM;
1292 goto err_iounmap;
1293 }
1294
1295 SET_NETDEV_DEV(netdev, &pdev->dev);
1296 netdev->netdev_ops = &fe_netdev_ops;
1297 netdev->base_addr = (unsigned long) fe_base;
1298 netdev->watchdog_timeo = TX_TIMEOUT;
1299
1300 netdev->irq = platform_get_irq(pdev, 0);
1301 if (netdev->irq < 0) {
1302 dev_err(&pdev->dev, "no IRQ resource found\n");
1303 err = -ENXIO;
1304 goto err_free_dev;
1305 }
1306
1307 if (soc->init_data)
1308 soc->init_data(soc, netdev);
1309 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1310 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1311 netdev->vlan_features = netdev->hw_features &
1312 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1313 netdev->features |= netdev->hw_features;
1314
1315 /* fake rx vlan filter func. to support tx vlan offload func */
1316 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1317 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1318
1319 priv = netdev_priv(netdev);
1320 spin_lock_init(&priv->page_lock);
1321 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1322 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1323 if (!priv->hw_stats) {
1324 err = -ENOMEM;
1325 goto err_free_dev;
1326 }
1327 spin_lock_init(&priv->hw_stats->stats_lock);
1328 }
1329
1330 sysclk = devm_clk_get(&pdev->dev, NULL);
1331 if (!IS_ERR(sysclk))
1332 priv->sysclk = clk_get_rate(sysclk);
1333
1334 priv->netdev = netdev;
1335 priv->device = &pdev->dev;
1336 priv->soc = soc;
1337 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1338 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1339 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1340 if (priv->frag_size > PAGE_SIZE) {
1341 dev_err(&pdev->dev, "error frag size.\n");
1342 err = -EINVAL;
1343 goto err_free_dev;
1344 }
1345
1346 netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
1347 fe_set_ethtool_ops(netdev);
1348
1349 err = register_netdev(netdev);
1350 if (err) {
1351 dev_err(&pdev->dev, "error bringing up device\n");
1352 goto err_free_dev;
1353 }
1354
1355 platform_set_drvdata(pdev, netdev);
1356
1357 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1358 netdev->base_addr, netdev->irq);
1359
1360 return 0;
1361
1362 err_free_dev:
1363 free_netdev(netdev);
1364 err_iounmap:
1365 devm_iounmap(&pdev->dev, fe_base);
1366 err_out:
1367 return err;
1368 }
1369
1370 static int fe_remove(struct platform_device *pdev)
1371 {
1372 struct net_device *dev = platform_get_drvdata(pdev);
1373 struct fe_priv *priv = netdev_priv(dev);
1374
1375 netif_napi_del(&priv->rx_napi);
1376 if (priv->hw_stats)
1377 kfree(priv->hw_stats);
1378
1379 unregister_netdev(dev);
1380 free_netdev(dev);
1381 platform_set_drvdata(pdev, NULL);
1382
1383 return 0;
1384 }
1385
1386 static struct platform_driver fe_driver = {
1387 .probe = fe_probe,
1388 .remove = fe_remove,
1389 .driver = {
1390 .name = "ralink_soc_eth",
1391 .owner = THIS_MODULE,
1392 .of_match_table = of_fe_match,
1393 },
1394 };
1395
1396 static int __init init_rtfe(void)
1397 {
1398 int ret;
1399
1400 ret = rtesw_init();
1401 if (ret)
1402 return ret;
1403
1404 ret = platform_driver_register(&fe_driver);
1405 if (ret)
1406 rtesw_exit();
1407
1408 return ret;
1409 }
1410
1411 static void __exit exit_rtfe(void)
1412 {
1413 platform_driver_unregister(&fe_driver);
1414 rtesw_exit();
1415 }
1416
1417 module_init(init_rtfe);
1418 module_exit(exit_rtfe);
1419
1420 MODULE_LICENSE("GPL");
1421 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1422 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1423 MODULE_VERSION(FE_DRV_VERSION);
OpenWrt SVN history