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ralink: improve check rx sg function. use check frags instead of function call
[openwrt/svn-archive/archive.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define MAX_RX_LENGTH 1536
44 #define FE_RX_HLEN (NET_SKB_PAD + VLAN_ETH_HLEN + VLAN_HLEN + \
45 + NET_IP_ALIGN + ETH_FCS_LEN)
46 #define DMA_DUMMY_DESC 0xffffffff
47 #define FE_DEFAULT_MSG_ENABLE \
48 (NETIF_MSG_DRV | \
49 NETIF_MSG_PROBE | \
50 NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_IFDOWN | \
53 NETIF_MSG_IFUP | \
54 NETIF_MSG_RX_ERR | \
55 NETIF_MSG_TX_ERR)
56
57 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
58 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
59 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
60 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
61
62 #define SYSC_REG_RSTCTRL 0x34
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u32 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
76 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
77 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
78 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
79 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
80 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
81 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
82 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
83 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
84 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
85 };
86
87 static const u32 *fe_reg_table = fe_reg_table_default;
88
89 struct fe_work_t {
90 int bitnr;
91 void (*action)(struct fe_priv *);
92 };
93
94 static void __iomem *fe_base = 0;
95
96 void fe_w32(u32 val, unsigned reg)
97 {
98 __raw_writel(val, fe_base + reg);
99 }
100
101 u32 fe_r32(unsigned reg)
102 {
103 return __raw_readl(fe_base + reg);
104 }
105
106 void fe_reg_w32(u32 val, enum fe_reg reg)
107 {
108 fe_w32(val, fe_reg_table[reg]);
109 }
110
111 u32 fe_reg_r32(enum fe_reg reg)
112 {
113 return fe_r32(fe_reg_table[reg]);
114 }
115
116 void fe_reset(u32 reset_bits)
117 {
118 u32 t;
119
120 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
121 t |= reset_bits;
122 rt_sysc_w32(t , SYSC_REG_RSTCTRL);
123 udelay(10);
124
125 t &= ~reset_bits;
126 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
127 udelay(10);
128 }
129
130 static inline void fe_int_disable(u32 mask)
131 {
132 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
133 FE_REG_FE_INT_ENABLE);
134 /* flush write */
135 fe_reg_r32(FE_REG_FE_INT_ENABLE);
136 }
137
138 static inline void fe_int_enable(u32 mask)
139 {
140 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
141 FE_REG_FE_INT_ENABLE);
142 /* flush write */
143 fe_reg_r32(FE_REG_FE_INT_ENABLE);
144 }
145
146 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
147 {
148 unsigned long flags;
149
150 spin_lock_irqsave(&priv->page_lock, flags);
151 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
152 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
153 FE_GDMA1_MAC_ADRL);
154 spin_unlock_irqrestore(&priv->page_lock, flags);
155 }
156
157 static int fe_set_mac_address(struct net_device *dev, void *p)
158 {
159 int ret = eth_mac_addr(dev, p);
160
161 if (!ret) {
162 struct fe_priv *priv = netdev_priv(dev);
163
164 if (priv->soc->set_mac)
165 priv->soc->set_mac(priv, dev->dev_addr);
166 else
167 fe_hw_set_macaddr(priv, p);
168 }
169
170 return ret;
171 }
172
173 static inline int fe_max_frag_size(int mtu)
174 {
175 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
176 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
177 }
178
179 static inline int fe_max_buf_size(int frag_size)
180 {
181 return frag_size - FE_RX_HLEN -
182 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
183 }
184
185 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
186 {
187 rxd->rxd1 = dma_rxd->rxd1;
188 rxd->rxd2 = dma_rxd->rxd2;
189 rxd->rxd3 = dma_rxd->rxd3;
190 rxd->rxd4 = dma_rxd->rxd4;
191 }
192
193 static inline void fe_get_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
194 {
195 txd->txd1 = dma_txd->txd1;
196 txd->txd2 = dma_txd->txd2;
197 txd->txd3 = dma_txd->txd3;
198 txd->txd4 = dma_txd->txd4;
199 }
200
201 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
202 {
203 dma_txd->txd1 = txd->txd1;
204 dma_txd->txd3 = txd->txd3;
205 dma_txd->txd4 = txd->txd4;
206 /* clean dma done flag last */
207 dma_txd->txd2 = txd->txd2;
208 }
209
210 static void fe_clean_rx(struct fe_priv *priv)
211 {
212 int i;
213
214 if (priv->rx_data) {
215 for (i = 0; i < NUM_DMA_DESC; i++)
216 if (priv->rx_data[i]) {
217 if (priv->rx_dma && priv->rx_dma[i].rxd1)
218 dma_unmap_single(&priv->netdev->dev,
219 priv->rx_dma[i].rxd1,
220 priv->rx_buf_size,
221 DMA_FROM_DEVICE);
222 put_page(virt_to_head_page(priv->rx_data[i]));
223 }
224
225 kfree(priv->rx_data);
226 priv->rx_data = NULL;
227 }
228
229 if (priv->rx_dma) {
230 dma_free_coherent(&priv->netdev->dev,
231 NUM_DMA_DESC * sizeof(*priv->rx_dma),
232 priv->rx_dma,
233 priv->rx_phys);
234 priv->rx_dma = NULL;
235 }
236 }
237
238 static int fe_alloc_rx(struct fe_priv *priv)
239 {
240 struct net_device *netdev = priv->netdev;
241 int i, pad;
242
243 priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
244 GFP_KERNEL);
245 if (!priv->rx_data)
246 goto no_rx_mem;
247
248 for (i = 0; i < NUM_DMA_DESC; i++) {
249 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
250 if (!priv->rx_data[i])
251 goto no_rx_mem;
252 }
253
254 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
255 NUM_DMA_DESC * sizeof(*priv->rx_dma),
256 &priv->rx_phys,
257 GFP_ATOMIC | __GFP_ZERO);
258 if (!priv->rx_dma)
259 goto no_rx_mem;
260
261 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
262 pad = 0;
263 else
264 pad = NET_IP_ALIGN;
265 for (i = 0; i < NUM_DMA_DESC; i++) {
266 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
267 priv->rx_data[i] + NET_SKB_PAD + pad,
268 priv->rx_buf_size,
269 DMA_FROM_DEVICE);
270 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
271 goto no_rx_mem;
272 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
273
274 if (priv->flags & FE_FLAG_RX_SG_DMA)
275 priv->rx_dma[i].rxd2 = RX_DMA_PLEN0(priv->rx_buf_size);
276 else
277 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
278 }
279 wmb();
280
281 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
282 fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
283 fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
284 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
285
286 return 0;
287
288 no_rx_mem:
289 return -ENOMEM;
290 }
291
292 static void fe_clean_tx(struct fe_priv *priv)
293 {
294 int i;
295
296 if (priv->tx_skb) {
297 for (i = 0; i < NUM_DMA_DESC; i++) {
298 if (priv->tx_skb[i])
299 dev_kfree_skb_any(priv->tx_skb[i]);
300 }
301 kfree(priv->tx_skb);
302 priv->tx_skb = NULL;
303 }
304
305 if (priv->tx_dma) {
306 dma_free_coherent(&priv->netdev->dev,
307 NUM_DMA_DESC * sizeof(*priv->tx_dma),
308 priv->tx_dma,
309 priv->tx_phys);
310 priv->tx_dma = NULL;
311 }
312 }
313
314 static int fe_alloc_tx(struct fe_priv *priv)
315 {
316 int i;
317
318 priv->tx_free_idx = 0;
319
320 priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
321 GFP_KERNEL);
322 if (!priv->tx_skb)
323 goto no_tx_mem;
324
325 priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
326 NUM_DMA_DESC * sizeof(*priv->tx_dma),
327 &priv->tx_phys,
328 GFP_ATOMIC | __GFP_ZERO);
329 if (!priv->tx_dma)
330 goto no_tx_mem;
331
332 for (i = 0; i < NUM_DMA_DESC; i++) {
333 if (priv->soc->tx_dma) {
334 priv->soc->tx_dma(&priv->tx_dma[i]);
335 continue;
336 }
337 priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
338 }
339 wmb();
340
341 fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
342 fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
343 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
344 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
345
346 return 0;
347
348 no_tx_mem:
349 return -ENOMEM;
350 }
351
352 static int fe_init_dma(struct fe_priv *priv)
353 {
354 int err;
355
356 err = fe_alloc_tx(priv);
357 if (err)
358 return err;
359
360 err = fe_alloc_rx(priv);
361 if (err)
362 return err;
363
364 return 0;
365 }
366
367 static void fe_free_dma(struct fe_priv *priv)
368 {
369 fe_clean_tx(priv);
370 fe_clean_rx(priv);
371
372 netdev_reset_queue(priv->netdev);
373 }
374
375 static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
376 {
377 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
378 dma_unmap_single(dev, txd->txd1,
379 TX_DMA_GET_PLEN0(txd->txd2),
380 DMA_TO_DEVICE);
381 }
382
383 static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
384 {
385 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
386 dma_unmap_page(dev, txd->txd1,
387 TX_DMA_GET_PLEN0(txd->txd2),
388 DMA_TO_DEVICE);
389 }
390
391 static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
392 {
393 if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
394 dma_unmap_page(dev, txd->txd3,
395 TX_DMA_GET_PLEN1(txd->txd2),
396 DMA_TO_DEVICE);
397 }
398
399 void fe_stats_update(struct fe_priv *priv)
400 {
401 struct fe_hw_stats *hwstats = priv->hw_stats;
402 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
403
404 u64_stats_update_begin(&hwstats->syncp);
405
406 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
407 hwstats->rx_bytes += fe_r32(base);
408 hwstats->rx_packets += fe_r32(base + 0x08);
409 hwstats->rx_overflow += fe_r32(base + 0x10);
410 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
411 hwstats->rx_short_errors += fe_r32(base + 0x18);
412 hwstats->rx_long_errors += fe_r32(base + 0x1c);
413 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
414 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
415 hwstats->tx_skip += fe_r32(base + 0x28);
416 hwstats->tx_collisions += fe_r32(base + 0x2c);
417 hwstats->tx_bytes += fe_r32(base + 0x30);
418 hwstats->tx_packets += fe_r32(base + 0x38);
419 } else {
420 hwstats->tx_bytes += fe_r32(base);
421 hwstats->tx_packets += fe_r32(base + 0x04);
422 hwstats->tx_skip += fe_r32(base + 0x08);
423 hwstats->tx_collisions += fe_r32(base + 0x0c);
424 hwstats->rx_bytes += fe_r32(base + 0x20);
425 hwstats->rx_packets += fe_r32(base + 0x24);
426 hwstats->rx_overflow += fe_r32(base + 0x28);
427 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
428 hwstats->rx_short_errors += fe_r32(base + 0x30);
429 hwstats->rx_long_errors += fe_r32(base + 0x34);
430 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
431 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
432 }
433
434 u64_stats_update_end(&hwstats->syncp);
435 }
436
437 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
438 struct rtnl_link_stats64 *storage)
439 {
440 struct fe_priv *priv = netdev_priv(dev);
441 struct fe_hw_stats *hwstats = priv->hw_stats;
442 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
443 unsigned int start;
444
445 if (!base) {
446 netdev_stats_to_stats64(storage, &dev->stats);
447 return storage;
448 }
449
450 if (netif_running(dev) && netif_device_present(dev)) {
451 if (spin_trylock(&hwstats->stats_lock)) {
452 fe_stats_update(priv);
453 spin_unlock(&hwstats->stats_lock);
454 }
455 }
456
457 do {
458 start = u64_stats_fetch_begin_bh(&hwstats->syncp);
459 storage->rx_packets = hwstats->rx_packets;
460 storage->tx_packets = hwstats->tx_packets;
461 storage->rx_bytes = hwstats->rx_bytes;
462 storage->tx_bytes = hwstats->tx_bytes;
463 storage->collisions = hwstats->tx_collisions;
464 storage->rx_length_errors = hwstats->rx_short_errors +
465 hwstats->rx_long_errors;
466 storage->rx_over_errors = hwstats->rx_overflow;
467 storage->rx_crc_errors = hwstats->rx_fcs_errors;
468 storage->rx_errors = hwstats->rx_checksum_errors;
469 storage->tx_aborted_errors = hwstats->tx_skip;
470 } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
471
472 storage->tx_errors = priv->netdev->stats.tx_errors;
473 storage->rx_dropped = priv->netdev->stats.rx_dropped;
474 storage->tx_dropped = priv->netdev->stats.tx_dropped;
475
476 return storage;
477 }
478
479 static int fe_vlan_rx_add_vid(struct net_device *dev,
480 __be16 proto, u16 vid)
481 {
482 struct fe_priv *priv = netdev_priv(dev);
483 u32 idx = (vid & 0xf);
484 u32 vlan_cfg;
485
486 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
487 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
488 return 0;
489
490 if (test_bit(idx, &priv->vlan_map)) {
491 netdev_warn(dev, "disable tx vlan offload\n");
492 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
493 netdev_update_features(dev);
494 } else {
495 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
496 ((idx >> 1) << 2));
497 if (idx & 0x1) {
498 vlan_cfg &= 0xffff;
499 vlan_cfg |= (vid << 16);
500 } else {
501 vlan_cfg &= 0xffff0000;
502 vlan_cfg |= vid;
503 }
504 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
505 ((idx >> 1) << 2));
506 set_bit(idx, &priv->vlan_map);
507 }
508
509 return 0;
510 }
511
512 static int fe_vlan_rx_kill_vid(struct net_device *dev,
513 __be16 proto, u16 vid)
514 {
515 struct fe_priv *priv = netdev_priv(dev);
516 u32 idx = (vid & 0xf);
517
518 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
519 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
520 return 0;
521
522 clear_bit(idx, &priv->vlan_map);
523
524 return 0;
525 }
526
527 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
528 int idx)
529 {
530 struct fe_priv *priv = netdev_priv(dev);
531 struct skb_frag_struct *frag;
532 struct fe_tx_dma txd, *ptxd;
533 dma_addr_t mapped_addr;
534 unsigned int nr_frags;
535 u32 def_txd4;
536 int i, j, unmap_idx, tx_num;
537
538 memset(&txd, 0, sizeof(txd));
539 nr_frags = skb_shinfo(skb)->nr_frags;
540 tx_num = 1 + (nr_frags >> 1);
541
542 /* init tx descriptor */
543 if (priv->soc->tx_dma)
544 priv->soc->tx_dma(&txd);
545 else
546 txd.txd4 = TX_DMA_DESP4_DEF;
547 def_txd4 = txd.txd4;
548
549 /* use dma_unmap_single to free it */
550 txd.txd4 |= priv->soc->tx_udf_bit;
551
552 /* TX Checksum offload */
553 if (skb->ip_summed == CHECKSUM_PARTIAL)
554 txd.txd4 |= TX_DMA_CHKSUM;
555
556 /* VLAN header offload */
557 if (vlan_tx_tag_present(skb)) {
558 if (IS_ENABLED(CONFIG_SOC_MT7621))
559 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
560 else
561 txd.txd4 |= TX_DMA_INS_VLAN |
562 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
563 (vlan_tx_tag_get(skb) & 0xF);
564 }
565
566 /* TSO: fill MSS info in tcp checksum field */
567 if (skb_is_gso(skb)) {
568 if (skb_cow_head(skb, 0)) {
569 netif_warn(priv, tx_err, dev,
570 "GSO expand head fail.\n");
571 goto err_out;
572 }
573 if (skb_shinfo(skb)->gso_type &
574 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
575 txd.txd4 |= TX_DMA_TSO;
576 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
577 }
578 }
579
580 mapped_addr = dma_map_single(&dev->dev, skb->data,
581 skb_headlen(skb), DMA_TO_DEVICE);
582 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
583 goto err_out;
584 txd.txd1 = mapped_addr;
585 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
586
587 /* TX SG offload */
588 j = idx;
589 for (i = 0; i < nr_frags; i++) {
590
591 frag = &skb_shinfo(skb)->frags[i];
592 mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
593 skb_frag_size(frag), DMA_TO_DEVICE);
594 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
595 goto err_dma;
596
597 if (i & 0x1) {
598 j = NEXT_TX_DESP_IDX(j);
599 txd.txd1 = mapped_addr;
600 txd.txd2 = TX_DMA_PLEN0(frag->size);
601 txd.txd4 = def_txd4;
602 } else {
603 txd.txd3 = mapped_addr;
604 txd.txd2 |= TX_DMA_PLEN1(frag->size);
605 if (i != (nr_frags -1)) {
606 fe_set_txd(&txd, &priv->tx_dma[j]);
607 memset(&txd, 0, sizeof(txd));
608 }
609 priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
610 }
611 }
612
613 /* set last segment */
614 if (nr_frags & 0x1)
615 txd.txd2 |= TX_DMA_LS1;
616 else
617 txd.txd2 |= TX_DMA_LS0;
618 fe_set_txd(&txd, &priv->tx_dma[j]);
619
620 /* store skb to cleanup */
621 priv->tx_skb[j] = skb;
622
623 netdev_sent_queue(dev, skb->len);
624 skb_tx_timestamp(skb);
625
626 wmb();
627 j = NEXT_TX_DESP_IDX(j);
628 fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
629
630 return 0;
631
632 err_dma:
633 /* unmap dma */
634 ptxd = &priv->tx_dma[idx];
635 txd_unmap_single(&dev->dev, ptxd);
636
637 j = idx;
638 unmap_idx = i;
639 for (i = 0; i < unmap_idx; i++) {
640 if (i & 0x1) {
641 j = NEXT_TX_DESP_IDX(j);
642 ptxd = &priv->tx_dma[j];
643 txd_unmap_page0(&dev->dev, ptxd);
644 } else {
645 txd_unmap_page1(&dev->dev, ptxd);
646 }
647 }
648
649 err_out:
650 /* reinit descriptors and skb */
651 j = idx;
652 for (i = 0; i < tx_num; i++) {
653 priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
654 priv->tx_skb[j] = NULL;
655 j = NEXT_TX_DESP_IDX(j);
656 }
657 wmb();
658
659 return -1;
660 }
661
662 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
663 unsigned int len;
664 int ret;
665
666 ret = 0;
667 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
668 if ((priv->flags & FE_FLAG_PADDING_64B) &&
669 !(priv->flags & FE_FLAG_PADDING_BUG))
670 return ret;
671
672 if (vlan_tx_tag_present(skb))
673 len = ETH_ZLEN;
674 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
675 len = VLAN_ETH_ZLEN;
676 else if(!(priv->flags & FE_FLAG_PADDING_64B))
677 len = ETH_ZLEN;
678 else
679 return ret;
680
681 if (skb->len < len) {
682 if ((ret = skb_pad(skb, len - skb->len)) < 0)
683 return ret;
684 skb->len = len;
685 skb_set_tail_pointer(skb, len);
686 }
687 }
688
689 return ret;
690 }
691
692 static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
693 {
694 return (u32)(NUM_DMA_DESC - ((tx_fill_idx - priv->tx_free_idx) &
695 (NUM_DMA_DESC - 1)));
696 }
697
698 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
699 {
700 struct fe_priv *priv = netdev_priv(dev);
701 struct net_device_stats *stats = &dev->stats;
702 u32 tx;
703 int tx_num;
704 int len = skb->len;
705
706 if (fe_skb_padto(skb, priv)) {
707 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
708 return NETDEV_TX_OK;
709 }
710
711 tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
712 tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
713 if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
714 {
715 netif_stop_queue(dev);
716 netif_err(priv, tx_queued,dev,
717 "Tx Ring full when queue awake!\n");
718 return NETDEV_TX_BUSY;
719 }
720
721 if (fe_tx_map_dma(skb, dev, tx) < 0) {
722 kfree_skb(skb);
723
724 stats->tx_dropped++;
725 } else {
726 stats->tx_packets++;
727 stats->tx_bytes += len;
728 }
729
730 return NETDEV_TX_OK;
731 }
732
733 static inline void fe_rx_vlan(struct sk_buff *skb)
734 {
735 struct ethhdr *ehdr;
736 u16 vlanid;
737
738 if (!__vlan_get_tag(skb, &vlanid)) {
739 /* pop the vlan tag */
740 ehdr = (struct ethhdr *)skb->data;
741 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
742 skb_pull(skb, VLAN_HLEN);
743 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
744 }
745 }
746
747 static int fe_poll_rx(struct napi_struct *napi, int budget,
748 struct fe_priv *priv)
749 {
750 struct net_device *netdev = priv->netdev;
751 struct net_device_stats *stats = &netdev->stats;
752 struct fe_soc_data *soc = priv->soc;
753 u32 checksum_bit;
754 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
755 struct sk_buff *skb;
756 u8 *data, *new_data;
757 struct fe_rx_dma *rxd, trxd;
758 int done = 0, pad;
759 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
760
761 if (netdev->features & NETIF_F_RXCSUM)
762 checksum_bit = soc->checksum_bit;
763 else
764 checksum_bit = 0;
765
766 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
767 pad = 0;
768 else
769 pad = NET_IP_ALIGN;
770 while (done < budget) {
771 unsigned int pktlen;
772 dma_addr_t dma_addr;
773 idx = NEXT_RX_DESP_IDX(idx);
774 rxd = &priv->rx_dma[idx];
775 data = priv->rx_data[idx];
776
777 fe_get_rxd(&trxd, rxd);
778 if (!(trxd.rxd2 & RX_DMA_DONE))
779 break;
780
781 /* alloc new buffer */
782 new_data = netdev_alloc_frag(priv->frag_size);
783 if (unlikely(!new_data)) {
784 stats->rx_dropped++;
785 goto release_desc;
786 }
787 dma_addr = dma_map_single(&netdev->dev,
788 new_data + NET_SKB_PAD + pad,
789 priv->rx_buf_size,
790 DMA_FROM_DEVICE);
791 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
792 put_page(virt_to_head_page(new_data));
793 goto release_desc;
794 }
795
796 /* receive data */
797 skb = build_skb(data, priv->frag_size);
798 if (unlikely(!skb)) {
799 put_page(virt_to_head_page(new_data));
800 goto release_desc;
801 }
802 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
803
804 dma_unmap_single(&netdev->dev, trxd.rxd1,
805 priv->rx_buf_size, DMA_FROM_DEVICE);
806 pktlen = RX_DMA_PLEN0(trxd.rxd2);
807 skb->dev = netdev;
808 skb_put(skb, pktlen);
809 if (trxd.rxd4 & checksum_bit) {
810 skb->ip_summed = CHECKSUM_UNNECESSARY;
811 } else {
812 skb_checksum_none_assert(skb);
813 }
814 if (rx_vlan)
815 fe_rx_vlan(skb);
816 skb->protocol = eth_type_trans(skb, netdev);
817
818 stats->rx_packets++;
819 stats->rx_bytes += pktlen;
820
821 if (skb->ip_summed == CHECKSUM_NONE)
822 netif_receive_skb(skb);
823 else
824 napi_gro_receive(napi, skb);
825
826 priv->rx_data[idx] = new_data;
827 rxd->rxd1 = (unsigned int) dma_addr;
828
829 release_desc:
830 if (priv->flags & FE_FLAG_RX_SG_DMA)
831 rxd->rxd2 = RX_DMA_PLEN0(priv->rx_buf_size);
832 else
833 rxd->rxd2 = RX_DMA_LSO;
834
835 wmb();
836 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
837 done++;
838 }
839
840 return done;
841 }
842
843 static int fe_poll_tx(struct fe_priv *priv, int budget)
844 {
845 struct net_device *netdev = priv->netdev;
846 struct device *dev = &netdev->dev;
847 unsigned int bytes_compl = 0;
848 struct sk_buff *skb;
849 struct fe_tx_dma txd;
850 int done = 0, idx;
851 u32 udf_bit = priv->soc->tx_udf_bit;
852
853 idx = priv->tx_free_idx;
854 while (done < budget) {
855 fe_get_txd(&txd, &priv->tx_dma[idx]);
856 skb = priv->tx_skb[idx];
857
858 if (!(txd.txd2 & TX_DMA_DONE) || !skb)
859 break;
860
861 txd_unmap_page1(dev, &txd);
862
863 if (txd.txd4 & udf_bit)
864 txd_unmap_single(dev, &txd);
865 else
866 txd_unmap_page0(dev, &txd);
867
868 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
869 bytes_compl += skb->len;
870 dev_kfree_skb_any(skb);
871 done++;
872 }
873 priv->tx_skb[idx] = NULL;
874 idx = NEXT_TX_DESP_IDX(idx);
875 }
876 priv->tx_free_idx = idx;
877
878 if (!done)
879 return 0;
880
881 netdev_completed_queue(netdev, done, bytes_compl);
882 if (unlikely(netif_queue_stopped(netdev) &&
883 netif_carrier_ok(netdev))) {
884 netif_wake_queue(netdev);
885 }
886
887 return done;
888 }
889
890 static int fe_poll(struct napi_struct *napi, int budget)
891 {
892 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
893 struct fe_hw_stats *hwstat = priv->hw_stats;
894 int tx_done, rx_done;
895 u32 status, mask;
896 u32 tx_intr, rx_intr;
897
898 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
899 tx_intr = priv->soc->tx_int;
900 rx_intr = priv->soc->rx_int;
901 tx_done = rx_done = 0;
902
903 poll_again:
904 if (status & tx_intr) {
905 tx_done += fe_poll_tx(priv, budget - tx_done);
906 if (tx_done < budget) {
907 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
908 }
909 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
910 }
911
912 if (status & rx_intr) {
913 rx_done += fe_poll_rx(napi, budget - rx_done, priv);
914 if (rx_done < budget) {
915 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
916 }
917 }
918
919 if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
920 if (spin_trylock(&hwstat->stats_lock)) {
921 fe_stats_update(priv);
922 spin_unlock(&hwstat->stats_lock);
923 }
924 fe_reg_w32(FE_CNT_GDM_AF, FE_REG_FE_INT_STATUS);
925 }
926
927 if (unlikely(netif_msg_intr(priv))) {
928 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
929 netdev_info(priv->netdev,
930 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
931 tx_done, rx_done, status, mask);
932 }
933
934 if ((tx_done < budget) && (rx_done < budget)) {
935 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
936 if (status & (tx_intr | rx_intr )) {
937 goto poll_again;
938 }
939 napi_complete(napi);
940 fe_int_enable(tx_intr | rx_intr);
941 }
942
943 return rx_done;
944 }
945
946 static void fe_tx_timeout(struct net_device *dev)
947 {
948 struct fe_priv *priv = netdev_priv(dev);
949
950 priv->netdev->stats.tx_errors++;
951 netif_err(priv, tx_err, dev,
952 "transmit timed out\n");
953 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
954 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
955 netif_info(priv, drv, dev, "tx_ring=%d, " \
956 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%d\n", 0,
957 fe_reg_r32(FE_REG_TX_BASE_PTR0),
958 fe_reg_r32(FE_REG_TX_MAX_CNT0),
959 fe_reg_r32(FE_REG_TX_CTX_IDX0),
960 fe_reg_r32(FE_REG_TX_DTX_IDX0),
961 priv->tx_free_idx
962 );
963 netif_info(priv, drv, dev, "rx_ring=%d, " \
964 "base=%08x, max=%u, calc=%u, drx=%u\n", 0,
965 fe_reg_r32(FE_REG_RX_BASE_PTR0),
966 fe_reg_r32(FE_REG_RX_MAX_CNT0),
967 fe_reg_r32(FE_REG_RX_CALC_IDX0),
968 fe_reg_r32(FE_REG_RX_DRX_IDX0)
969 );
970
971 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
972 schedule_work(&priv->pending_work);
973 }
974
975 static irqreturn_t fe_handle_irq(int irq, void *dev)
976 {
977 struct fe_priv *priv = netdev_priv(dev);
978 u32 status, int_mask;
979
980 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
981
982 if (unlikely(!status))
983 return IRQ_NONE;
984
985 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
986 if (likely(status & int_mask)) {
987 fe_int_disable(int_mask);
988 napi_schedule(&priv->rx_napi);
989 } else {
990 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
991 }
992
993 return IRQ_HANDLED;
994 }
995
996 #ifdef CONFIG_NET_POLL_CONTROLLER
997 static void fe_poll_controller(struct net_device *dev)
998 {
999 struct fe_priv *priv = netdev_priv(dev);
1000 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1001
1002 fe_int_disable(int_mask);
1003 fe_handle_irq(dev->irq, dev);
1004 fe_int_enable(int_mask);
1005 }
1006 #endif
1007
1008 int fe_set_clock_cycle(struct fe_priv *priv)
1009 {
1010 unsigned long sysclk = priv->sysclk;
1011
1012 if (!sysclk) {
1013 return -EINVAL;
1014 }
1015
1016 sysclk /= FE_US_CYC_CNT_DIVISOR;
1017 sysclk <<= FE_US_CYC_CNT_SHIFT;
1018
1019 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1020 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1021 sysclk,
1022 FE_FE_GLO_CFG);
1023 return 0;
1024 }
1025
1026 void fe_fwd_config(struct fe_priv *priv)
1027 {
1028 u32 fwd_cfg;
1029
1030 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1031
1032 /* disable jumbo frame */
1033 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1034 fwd_cfg &= ~FE_GDM1_JMB_EN;
1035
1036 /* set unicast/multicast/broadcast frame to cpu */
1037 fwd_cfg &= ~0xffff;
1038
1039 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1040 }
1041
1042 static void fe_rxcsum_config(bool enable)
1043 {
1044 if (enable)
1045 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1046 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1047 FE_GDMA1_FWD_CFG);
1048 else
1049 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1050 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1051 FE_GDMA1_FWD_CFG);
1052 }
1053
1054 static void fe_txcsum_config(bool enable)
1055 {
1056 if (enable)
1057 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1058 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1059 FE_CDMA_CSG_CFG);
1060 else
1061 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1062 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1063 FE_CDMA_CSG_CFG);
1064 }
1065
1066 void fe_csum_config(struct fe_priv *priv)
1067 {
1068 struct net_device *dev = priv_netdev(priv);
1069
1070 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1071 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1072 }
1073
1074 static int fe_hw_init(struct net_device *dev)
1075 {
1076 struct fe_priv *priv = netdev_priv(dev);
1077 int i, err;
1078
1079 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1080 dev_name(priv->device), dev);
1081 if (err)
1082 return err;
1083
1084 if (priv->soc->set_mac)
1085 priv->soc->set_mac(priv, dev->dev_addr);
1086 else
1087 fe_hw_set_macaddr(priv, dev->dev_addr);
1088
1089 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1090
1091 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1092 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1093 for (i = 0; i < 16; i += 2)
1094 fe_w32(((i + 1) << 16) + i,
1095 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1096 (i * 2));
1097
1098 BUG_ON(!priv->soc->fwd_config);
1099 if (priv->soc->fwd_config(priv))
1100 netdev_err(dev, "unable to get clock\n");
1101
1102 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1103 fe_reg_w32(1, FE_REG_FE_RST_GL);
1104 fe_reg_w32(0, FE_REG_FE_RST_GL);
1105 }
1106
1107 return 0;
1108 }
1109
1110 static int fe_open(struct net_device *dev)
1111 {
1112 struct fe_priv *priv = netdev_priv(dev);
1113 unsigned long flags;
1114 u32 val;
1115 int err;
1116
1117 err = fe_init_dma(priv);
1118 if (err)
1119 goto err_out;
1120
1121 spin_lock_irqsave(&priv->page_lock, flags);
1122 napi_enable(&priv->rx_napi);
1123
1124 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1125 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1126 val |= FE_RX_2B_OFFSET;
1127 val |= priv->soc->pdma_glo_cfg;
1128 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1129
1130 spin_unlock_irqrestore(&priv->page_lock, flags);
1131
1132 if (priv->phy)
1133 priv->phy->start(priv);
1134
1135 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1136 netif_carrier_on(dev);
1137
1138 netif_start_queue(dev);
1139 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1140
1141 return 0;
1142
1143 err_out:
1144 fe_free_dma(priv);
1145 return err;
1146 }
1147
1148 static int fe_stop(struct net_device *dev)
1149 {
1150 struct fe_priv *priv = netdev_priv(dev);
1151 unsigned long flags;
1152 int i;
1153
1154 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1155
1156 netif_tx_disable(dev);
1157
1158 if (priv->phy)
1159 priv->phy->stop(priv);
1160
1161 spin_lock_irqsave(&priv->page_lock, flags);
1162 napi_disable(&priv->rx_napi);
1163
1164 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1165 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1166 FE_REG_PDMA_GLO_CFG);
1167 spin_unlock_irqrestore(&priv->page_lock, flags);
1168
1169 /* wait dma stop */
1170 for (i = 0; i < 10; i++) {
1171 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1172 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1173 msleep(10);
1174 continue;
1175 }
1176 break;
1177 }
1178
1179 fe_free_dma(priv);
1180
1181 return 0;
1182 }
1183
1184 static int __init fe_init(struct net_device *dev)
1185 {
1186 struct fe_priv *priv = netdev_priv(dev);
1187 struct device_node *port;
1188 int err;
1189
1190 BUG_ON(!priv->soc->reset_fe);
1191 priv->soc->reset_fe();
1192
1193 if (priv->soc->switch_init)
1194 priv->soc->switch_init(priv);
1195
1196 memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
1197 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1198
1199 err = fe_mdio_init(priv);
1200 if (err)
1201 return err;
1202
1203 if (priv->soc->port_init)
1204 for_each_child_of_node(priv->device->of_node, port)
1205 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1206 priv->soc->port_init(priv, port);
1207
1208 if (priv->phy) {
1209 err = priv->phy->connect(priv);
1210 if (err)
1211 goto err_phy_disconnect;
1212 }
1213
1214 err = fe_hw_init(dev);
1215 if (err)
1216 goto err_phy_disconnect;
1217
1218 if (priv->soc->switch_config)
1219 priv->soc->switch_config(priv);
1220
1221 return 0;
1222
1223 err_phy_disconnect:
1224 if (priv->phy)
1225 priv->phy->disconnect(priv);
1226 fe_mdio_cleanup(priv);
1227
1228 return err;
1229 }
1230
1231 static void fe_uninit(struct net_device *dev)
1232 {
1233 struct fe_priv *priv = netdev_priv(dev);
1234
1235 if (priv->phy)
1236 priv->phy->disconnect(priv);
1237 fe_mdio_cleanup(priv);
1238
1239 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1240 free_irq(dev->irq, dev);
1241 }
1242
1243 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1244 {
1245 struct fe_priv *priv = netdev_priv(dev);
1246
1247 if (!priv->phy_dev)
1248 return -ENODEV;
1249
1250 switch (cmd) {
1251 case SIOCETHTOOL:
1252 return phy_ethtool_ioctl(priv->phy_dev,
1253 (void *) ifr->ifr_data);
1254 case SIOCGMIIPHY:
1255 case SIOCGMIIREG:
1256 case SIOCSMIIREG:
1257 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1258 default:
1259 break;
1260 }
1261
1262 return -EOPNOTSUPP;
1263 }
1264
1265 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1266 {
1267 struct fe_priv *priv = netdev_priv(dev);
1268 int frag_size, old_mtu;
1269 u32 fwd_cfg;
1270
1271 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1272 return eth_change_mtu(dev, new_mtu);
1273
1274 frag_size = fe_max_frag_size(new_mtu);
1275 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1276 return -EINVAL;
1277
1278 old_mtu = dev->mtu;
1279 dev->mtu = new_mtu;
1280
1281 /* return early if the buffer sizes will not change */
1282 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1283 return 0;
1284 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1285 return 0;
1286
1287 if (new_mtu <= ETH_DATA_LEN) {
1288 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1289 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1290 } else {
1291 priv->frag_size = PAGE_SIZE;
1292 priv->rx_buf_size = fe_max_buf_size(PAGE_SIZE);
1293 }
1294
1295 if (!netif_running(dev))
1296 return 0;
1297
1298 fe_stop(dev);
1299 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1300 if (new_mtu <= ETH_DATA_LEN)
1301 fwd_cfg &= ~FE_GDM1_JMB_EN;
1302 else {
1303 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1304 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1305 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1306 }
1307 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1308
1309 return fe_open(dev);
1310 }
1311
1312 static const struct net_device_ops fe_netdev_ops = {
1313 .ndo_init = fe_init,
1314 .ndo_uninit = fe_uninit,
1315 .ndo_open = fe_open,
1316 .ndo_stop = fe_stop,
1317 .ndo_start_xmit = fe_start_xmit,
1318 .ndo_set_mac_address = fe_set_mac_address,
1319 .ndo_validate_addr = eth_validate_addr,
1320 .ndo_do_ioctl = fe_do_ioctl,
1321 .ndo_change_mtu = fe_change_mtu,
1322 .ndo_tx_timeout = fe_tx_timeout,
1323 .ndo_get_stats64 = fe_get_stats64,
1324 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1325 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1326 #ifdef CONFIG_NET_POLL_CONTROLLER
1327 .ndo_poll_controller = fe_poll_controller,
1328 #endif
1329 };
1330
1331 static void fe_reset_pending(struct fe_priv *priv)
1332 {
1333 struct net_device *dev = priv->netdev;
1334 int err;
1335
1336 rtnl_lock();
1337 fe_stop(dev);
1338
1339 err = fe_open(dev);
1340 if (err)
1341 goto error;
1342 rtnl_unlock();
1343
1344 return;
1345 error:
1346 netif_alert(priv, ifup, dev,
1347 "Driver up/down cycle failed, closing device.\n");
1348 dev_close(dev);
1349 rtnl_unlock();
1350 }
1351
1352 static const struct fe_work_t fe_work[] = {
1353 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1354 };
1355
1356 static void fe_pending_work(struct work_struct *work)
1357 {
1358 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1359 int i;
1360 bool pending;
1361
1362 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1363 pending = test_and_clear_bit(fe_work[i].bitnr,
1364 priv->pending_flags);
1365 if (pending)
1366 fe_work[i].action(priv);
1367 }
1368 }
1369
1370 static int fe_probe(struct platform_device *pdev)
1371 {
1372 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1373 const struct of_device_id *match;
1374 struct fe_soc_data *soc;
1375 struct net_device *netdev;
1376 struct fe_priv *priv;
1377 struct clk *sysclk;
1378 int err;
1379
1380 device_reset(&pdev->dev);
1381
1382 match = of_match_device(of_fe_match, &pdev->dev);
1383 soc = (struct fe_soc_data *) match->data;
1384
1385 if (soc->reg_table)
1386 fe_reg_table = soc->reg_table;
1387 else
1388 soc->reg_table = fe_reg_table;
1389
1390 fe_base = devm_request_and_ioremap(&pdev->dev, res);
1391 if (!fe_base) {
1392 err = -EADDRNOTAVAIL;
1393 goto err_out;
1394 }
1395
1396 netdev = alloc_etherdev(sizeof(*priv));
1397 if (!netdev) {
1398 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1399 err = -ENOMEM;
1400 goto err_iounmap;
1401 }
1402
1403 SET_NETDEV_DEV(netdev, &pdev->dev);
1404 netdev->netdev_ops = &fe_netdev_ops;
1405 netdev->base_addr = (unsigned long) fe_base;
1406
1407 netdev->irq = platform_get_irq(pdev, 0);
1408 if (netdev->irq < 0) {
1409 dev_err(&pdev->dev, "no IRQ resource found\n");
1410 err = -ENXIO;
1411 goto err_free_dev;
1412 }
1413
1414 if (soc->init_data)
1415 soc->init_data(soc, netdev);
1416 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1417 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1418 netdev->vlan_features = netdev->hw_features &
1419 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1420 netdev->features |= netdev->hw_features;
1421
1422 /* fake rx vlan filter func. to support tx vlan offload func */
1423 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1424 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1425
1426 priv = netdev_priv(netdev);
1427 spin_lock_init(&priv->page_lock);
1428 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1429 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1430 if (!priv->hw_stats) {
1431 err = -ENOMEM;
1432 goto err_free_dev;
1433 }
1434 spin_lock_init(&priv->hw_stats->stats_lock);
1435 }
1436
1437 sysclk = devm_clk_get(&pdev->dev, NULL);
1438 if (!IS_ERR(sysclk))
1439 priv->sysclk = clk_get_rate(sysclk);
1440
1441 priv->netdev = netdev;
1442 priv->device = &pdev->dev;
1443 priv->soc = soc;
1444 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1445 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1446 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1447 if (priv->frag_size > PAGE_SIZE) {
1448 dev_err(&pdev->dev, "error frag size.\n");
1449 err = -EINVAL;
1450 goto err_free_dev;
1451 }
1452 INIT_WORK(&priv->pending_work, fe_pending_work);
1453
1454 netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
1455 fe_set_ethtool_ops(netdev);
1456
1457 err = register_netdev(netdev);
1458 if (err) {
1459 dev_err(&pdev->dev, "error bringing up device\n");
1460 goto err_free_dev;
1461 }
1462
1463 platform_set_drvdata(pdev, netdev);
1464
1465 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1466 netdev->base_addr, netdev->irq);
1467
1468 return 0;
1469
1470 err_free_dev:
1471 free_netdev(netdev);
1472 err_iounmap:
1473 devm_iounmap(&pdev->dev, fe_base);
1474 err_out:
1475 return err;
1476 }
1477
1478 static int fe_remove(struct platform_device *pdev)
1479 {
1480 struct net_device *dev = platform_get_drvdata(pdev);
1481 struct fe_priv *priv = netdev_priv(dev);
1482
1483 netif_napi_del(&priv->rx_napi);
1484 if (priv->hw_stats)
1485 kfree(priv->hw_stats);
1486
1487 cancel_work_sync(&priv->pending_work);
1488
1489 unregister_netdev(dev);
1490 free_netdev(dev);
1491 platform_set_drvdata(pdev, NULL);
1492
1493 return 0;
1494 }
1495
1496 static struct platform_driver fe_driver = {
1497 .probe = fe_probe,
1498 .remove = fe_remove,
1499 .driver = {
1500 .name = "ralink_soc_eth",
1501 .owner = THIS_MODULE,
1502 .of_match_table = of_fe_match,
1503 },
1504 };
1505
1506 static int __init init_rtfe(void)
1507 {
1508 int ret;
1509
1510 ret = rtesw_init();
1511 if (ret)
1512 return ret;
1513
1514 ret = platform_driver_register(&fe_driver);
1515 if (ret)
1516 rtesw_exit();
1517
1518 return ret;
1519 }
1520
1521 static void __exit exit_rtfe(void)
1522 {
1523 platform_driver_unregister(&fe_driver);
1524 rtesw_exit();
1525 }
1526
1527 module_init(init_rtfe);
1528 module_exit(exit_rtfe);
1529
1530 MODULE_LICENSE("GPL");
1531 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1532 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1533 MODULE_VERSION(FE_DRV_VERSION);
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