target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/if_vlan.h>
  21
  22 #include <asm/mach-ralink/ralink_regs.h>
  23
  24 #include <mt7620.h>
  25 #include "ralink_soc_eth.h"
  26 #include "gsw_mt7620a.h"
  27
  28 #define MT7620A_CDMA_CSG_CFG    0x400
  29 #define MT7620_DMA_VID          (MT7620A_CDMA_CSG_CFG | 0x30)
  30 #define MT7620A_DMA_2B_OFFSET   BIT(31)
  31 #define MT7620A_RESET_FE        BIT(21)
  32 #define MT7621_RESET_FE         BIT(6)
  33 #define MT7620A_RESET_ESW       BIT(23)
  34 #define MT7620_L4_VALID         BIT(23)
  35 #define MT7621_L4_VALID         BIT(24)
  36
  37 #define MT7620_TX_DMA_UDF       BIT(15)
  38 #define MT7621_TX_DMA_UDF       BIT(19)
  39 #define TX_DMA_FP_BMAP          ((0xff) << 19)
  40
  41 #define SYSC_REG_RESET_CTRL     0x34
  42
  43 #define CDMA_ICS_EN             BIT(2)
  44 #define CDMA_UCS_EN             BIT(1)
  45 #define CDMA_TCS_EN             BIT(0)
  46
  47 #define GDMA_ICS_EN             BIT(22)
  48 #define GDMA_TCS_EN             BIT(21)
  49 #define GDMA_UCS_EN             BIT(20)
  50
  51 /* frame engine counters */
  52 #define MT7620_REG_MIB_OFFSET   0x1000
  53 #define MT7620_PPE_AC_BCNT0     (MT7620_REG_MIB_OFFSET + 0x00)
  54 #define MT7620_GDM1_TX_GBCNT    (MT7620_REG_MIB_OFFSET + 0x300)
  55 #define MT7620_GDM2_TX_GBCNT    (MT7620_GDM1_TX_GBCNT + 0x40)
  56
  57 #define GSW_REG_GDMA1_MAC_ADRL  0x508
  58 #define GSW_REG_GDMA1_MAC_ADRH  0x50C
  59
  60 #define MT7621_FE_RST_GL        (FE_FE_OFFSET + 0x04)
  61
  62 static const u32 mt7620_reg_table[FE_REG_COUNT] = {
  63         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  64         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  65         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  66         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  67         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  68         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  69         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  70         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  71         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  72         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  73         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  74         [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
  75         [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
  76         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
  77 };
  78
  79 static void mt7620_fe_reset(void)
  80 {
  81         u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
  82
  83         rt_sysc_w32(val | MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
  84         rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
  85 }
  86
  87 static void mt7621_fe_reset(void)
  88 {
  89         u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
  90
  91         rt_sysc_w32(val | MT7621_RESET_FE, SYSC_REG_RESET_CTRL);
  92         rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
  93 }
  94
  95 static void mt7620_rxcsum_config(bool enable)
  96 {
  97         if (enable)
  98                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
  99                                         GDMA_TCS_EN | GDMA_UCS_EN),
 100                                 MT7620A_GDMA1_FWD_CFG);
 101         else
 102                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
 103                                         GDMA_TCS_EN | GDMA_UCS_EN),
 104                                 MT7620A_GDMA1_FWD_CFG);
 105 }
 106
 107 static void mt7620_txcsum_config(bool enable)
 108 {
 109         if (enable)
 110                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
 111                                         CDMA_UCS_EN | CDMA_TCS_EN),
 112                                 MT7620A_CDMA_CSG_CFG);
 113         else
 114                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
 115                                         CDMA_UCS_EN | CDMA_TCS_EN),
 116                                 MT7620A_CDMA_CSG_CFG);
 117 }
 118
 119 static int mt7620_fwd_config(struct fe_priv *priv)
 120 {
 121         struct net_device *dev = priv_netdev(priv);
 122
 123         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
 124
 125         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 126         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 127
 128         return 0;
 129 }
 130
 131 static int mt7621_fwd_config(struct fe_priv *priv)
 132 {
 133         struct net_device *dev = priv_netdev(priv);
 134
 135         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
 136
 137         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 138         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 139
 140         return 0;
 141 }
 142
 143 static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
 144 {
 145         priv->tx_dma[idx].txd4 = 0;
 146 }
 147
 148 static void mt7621_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
 149 {
 150         priv->tx_dma[idx].txd4 = BIT(25);
 151 }
 152
 153 static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
 154 {
 155         priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
 156 }
 157
 158 static void mt7620_init_data(struct fe_soc_data *data,
 159                 struct net_device *netdev)
 160 {
 161         struct fe_priv *priv = netdev_priv(netdev);
 162
 163         priv->flags = FE_FLAG_PADDING_64B;
 164         netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 165                 NETIF_F_HW_VLAN_CTAG_TX;
 166
 167         if (mt7620_get_eco() >= 5 || IS_ENABLED(CONFIG_SOC_MT7621))
 168                 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 169                         NETIF_F_IPV6_CSUM;
 170 }
 171
 172 static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
 173 {
 174         unsigned long flags;
 175
 176         spin_lock_irqsave(&priv->page_lock, flags);
 177         fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
 178         fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 179                 GSW_REG_GDMA1_MAC_ADRL);
 180         spin_unlock_irqrestore(&priv->page_lock, flags);
 181 }
 182
 183 static struct fe_soc_data mt7620_data = {
 184         .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
 185         .init_data = mt7620_init_data,
 186         .reset_fe = mt7620_fe_reset,
 187         .set_mac = mt7620_set_mac,
 188         .fwd_config = mt7620_fwd_config,
 189         .tx_dma = mt7620_tx_dma,
 190         .rx_dma = mt7620_rx_dma,
 191         .switch_init = mt7620_gsw_probe,
 192         .switch_config = mt7620_gsw_config,
 193         .port_init = mt7620_port_init,
 194         .reg_table = mt7620_reg_table,
 195         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
 196         .rx_dly_int = RT5350_RX_DLY_INT,
 197         .tx_dly_int = RT5350_TX_DLY_INT,
 198         .checksum_bit = MT7620_L4_VALID,
 199         .tx_udf_bit = MT7620_TX_DMA_UDF,
 200         .has_carrier = mt7620a_has_carrier,
 201         .mdio_read = mt7620_mdio_read,
 202         .mdio_write = mt7620_mdio_write,
 203         .mdio_adjust_link = mt7620_mdio_link_adjust,
 204 };
 205
 206 static struct fe_soc_data mt7621_data = {
 207         .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
 208         .init_data = mt7620_init_data,
 209         .reset_fe = mt7621_fe_reset,
 210         .set_mac = mt7621_set_mac,
 211         .fwd_config = mt7621_fwd_config,
 212         .tx_dma = mt7621_tx_dma,
 213         .rx_dma = mt7620_rx_dma,
 214         .switch_init = mt7620_gsw_probe,
 215         .switch_config = mt7621_gsw_config,
 216         .reg_table = mt7620_reg_table,
 217         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
 218         .rx_dly_int = RT5350_RX_DLY_INT,
 219         .tx_dly_int = RT5350_TX_DLY_INT,
 220         .checksum_bit = MT7621_L4_VALID,
 221         .tx_udf_bit = MT7621_TX_DMA_UDF,
 222         .has_carrier = mt7620a_has_carrier,
 223         .mdio_read = mt7620_mdio_read,
 224         .mdio_write = mt7620_mdio_write,
 225         .mdio_adjust_link = mt7620_mdio_link_adjust,
 226 };
 227
 228 const struct of_device_id of_fe_match[] = {
 229         { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
 230         { .compatible = "ralink,mt7621-eth", .data = &mt7621_data },
 231         {},
 232 };
 233
 234 MODULE_DEVICE_TABLE(of, of_fe_match);