target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/if_vlan.h>
  21
  22 #include <asm/mach-ralink/ralink_regs.h>
  23
  24 #include <mt7620.h>
  25 #include "ralink_soc_eth.h"
  26 #include "gsw_mt7620a.h"
  27
  28 #define MT7620A_CDMA_CSG_CFG    0x400
  29 #define MT7620_DMA_VID          (MT7620A_CDMA_CSG_CFG | 0x30)
  30 #define MT7621_CDMP_IG_CTRL     (MT7620A_CDMA_CSG_CFG + 0x00)
  31 #define MT7621_CDMP_EG_CTRL     (MT7620A_CDMA_CSG_CFG + 0x04)
  32 #define MT7620A_RESET_FE        BIT(21)
  33 #define MT7621_RESET_FE         BIT(6)
  34 #define MT7620A_RESET_ESW       BIT(23)
  35 #define MT7620_L4_VALID         BIT(23)
  36 #define MT7621_L4_VALID         BIT(24)
  37
  38 #define MT7620_TX_DMA_UDF       BIT(15)
  39 #define MT7621_TX_DMA_UDF       BIT(19)
  40 #define TX_DMA_FP_BMAP          ((0xff) << 19)
  41
  42 #define CDMA_ICS_EN             BIT(2)
  43 #define CDMA_UCS_EN             BIT(1)
  44 #define CDMA_TCS_EN             BIT(0)
  45
  46 #define GDMA_ICS_EN             BIT(22)
  47 #define GDMA_TCS_EN             BIT(21)
  48 #define GDMA_UCS_EN             BIT(20)
  49
  50 /* frame engine counters */
  51 #define MT7620_REG_MIB_OFFSET   0x1000
  52 #define MT7620_PPE_AC_BCNT0     (MT7620_REG_MIB_OFFSET + 0x00)
  53 #define MT7620_GDM1_TX_GBCNT    (MT7620_REG_MIB_OFFSET + 0x300)
  54 #define MT7620_GDM2_TX_GBCNT    (MT7620_GDM1_TX_GBCNT + 0x40)
  55
  56 #define MT7621_REG_MIB_OFFSET   0x2000
  57 #define MT7621_PPE_AC_BCNT0     (MT7621_REG_MIB_OFFSET + 0x00)
  58 #define MT7621_GDM1_TX_GBCNT    (MT7621_REG_MIB_OFFSET + 0x400)
  59 #define MT7621_GDM2_TX_GBCNT    (MT7621_GDM1_TX_GBCNT + 0x40)
  60
  61 #define GSW_REG_GDMA1_MAC_ADRL  0x508
  62 #define GSW_REG_GDMA1_MAC_ADRH  0x50C
  63
  64 #define MT7621_FE_RST_GL        (FE_FE_OFFSET + 0x04)
  65 #define MT7620_FE_INT_STATUS2   (FE_FE_OFFSET + 0x08)
  66
  67 /*
  68  * FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
  69  * but after test it should be BIT(13).
  70  */
  71 #define MT7620_FE_GDM1_AF       BIT(13)
  72 #define MT7621_FE_GDM1_AF       BIT(28)
  73 #define MT7621_FE_GDM2_AF       BIT(29)
  74
  75 static const u32 mt7620_reg_table[FE_REG_COUNT] = {
  76         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  77         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  78         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  79         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  80         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  81         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  82         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  83         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  84         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  85         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  86         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  87         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  88         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  89         [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
  90         [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
  91         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
  92         [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
  93 };
  94
  95 static const u32 mt7621_reg_table[FE_REG_COUNT] = {
  96         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  97         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  98         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  99         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
 100         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
 101         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
 102         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
 103         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
 104         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
 105         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
 106         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
 107         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
 108         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
 109         [FE_REG_FE_DMA_VID_BASE] = 0,
 110         [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
 111         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
 112         [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
 113 };
 114
 115 static void mt7620_fe_reset(void)
 116 {
 117         fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
 118 }
 119
 120 static void mt7621_fe_reset(void)
 121 {
 122         fe_reset(MT7621_RESET_FE);
 123 }
 124
 125 static void mt7620_rxcsum_config(bool enable)
 126 {
 127         if (enable)
 128                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
 129                                         GDMA_TCS_EN | GDMA_UCS_EN),
 130                                 MT7620A_GDMA1_FWD_CFG);
 131         else
 132                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
 133                                         GDMA_TCS_EN | GDMA_UCS_EN),
 134                                 MT7620A_GDMA1_FWD_CFG);
 135 }
 136
 137 static void mt7620_txcsum_config(bool enable)
 138 {
 139         if (enable)
 140                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
 141                                         CDMA_UCS_EN | CDMA_TCS_EN),
 142                                 MT7620A_CDMA_CSG_CFG);
 143         else
 144                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
 145                                         CDMA_UCS_EN | CDMA_TCS_EN),
 146                                 MT7620A_CDMA_CSG_CFG);
 147 }
 148
 149 static void mt7621_rxvlan_config(bool enable)
 150 {
 151         if (enable)
 152                 fe_w32(1, MT7621_CDMP_EG_CTRL);
 153         else
 154                 fe_w32(0, MT7621_CDMP_EG_CTRL);
 155 }
 156
 157 static int mt7620_fwd_config(struct fe_priv *priv)
 158 {
 159         struct net_device *dev = priv_netdev(priv);
 160
 161         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
 162
 163         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 164         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 165
 166         return 0;
 167 }
 168
 169 static int mt7621_fwd_config(struct fe_priv *priv)
 170 {
 171         struct net_device *dev = priv_netdev(priv);
 172
 173         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
 174
 175         /* mt7621 don't have txcsum config */
 176         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 177         mt7621_rxvlan_config((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
 178                         (priv->flags & FE_FLAG_RX_VLAN_CTAG));
 179
 180         return 0;
 181 }
 182
 183 static void mt7620_tx_dma(struct fe_tx_dma *txd)
 184 {
 185 }
 186
 187 static void mt7621_tx_dma(struct fe_tx_dma *txd)
 188 {
 189         txd->txd4 = BIT(25);
 190 }
 191
 192 static void mt7620_init_data(struct fe_soc_data *data,
 193                 struct net_device *netdev)
 194 {
 195         struct fe_priv *priv = netdev_priv(netdev);
 196
 197         priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
 198                 FE_FLAG_RX_SG_DMA;
 199
 200         netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 201                 NETIF_F_HW_VLAN_CTAG_TX;
 202         if (mt7620_get_eco() >= 5)
 203                 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 204                         NETIF_F_IPV6_CSUM;
 205 }
 206
 207 static void mt7621_init_data(struct fe_soc_data *data,
 208                 struct net_device *netdev)
 209 {
 210         struct fe_priv *priv = netdev_priv(netdev);
 211
 212         priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
 213                 FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT;
 214
 215         netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 216                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
 217                 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
 218 }
 219
 220 static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
 221 {
 222         unsigned long flags;
 223
 224         spin_lock_irqsave(&priv->page_lock, flags);
 225         fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
 226         fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 227                 GSW_REG_GDMA1_MAC_ADRL);
 228         spin_unlock_irqrestore(&priv->page_lock, flags);
 229 }
 230
 231 static struct fe_soc_data mt7620_data = {
 232         .init_data = mt7620_init_data,
 233         .reset_fe = mt7620_fe_reset,
 234         .set_mac = mt7620_set_mac,
 235         .fwd_config = mt7620_fwd_config,
 236         .tx_dma = mt7620_tx_dma,
 237         .switch_init = mt7620_gsw_probe,
 238         .switch_config = mt7620_gsw_config,
 239         .port_init = mt7620_port_init,
 240         .reg_table = mt7620_reg_table,
 241         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
 242         .rx_int = RT5350_RX_DONE_INT,
 243         .tx_int = RT5350_TX_DONE_INT,
 244         .status_int = MT7620_FE_GDM1_AF,
 245         .checksum_bit = MT7620_L4_VALID,
 246         .has_carrier = mt7620a_has_carrier,
 247         .mdio_read = mt7620_mdio_read,
 248         .mdio_write = mt7620_mdio_write,
 249         .mdio_adjust_link = mt7620_mdio_link_adjust,
 250 };
 251
 252 static struct fe_soc_data mt7621_data = {
 253         .init_data = mt7621_init_data,
 254         .reset_fe = mt7621_fe_reset,
 255         .set_mac = mt7621_set_mac,
 256         .fwd_config = mt7621_fwd_config,
 257         .tx_dma = mt7621_tx_dma,
 258         .switch_init = mt7620_gsw_probe,
 259         .switch_config = mt7621_gsw_config,
 260         .reg_table = mt7621_reg_table,
 261         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
 262         .rx_int = RT5350_RX_DONE_INT,
 263         .tx_int = RT5350_TX_DONE_INT,
 264         .status_int = (MT7621_FE_GDM1_AF | MT7621_FE_GDM2_AF),
 265         .checksum_bit = MT7621_L4_VALID,
 266         .has_carrier = mt7620a_has_carrier,
 267         .mdio_read = mt7620_mdio_read,
 268         .mdio_write = mt7620_mdio_write,
 269         .mdio_adjust_link = mt7620_mdio_link_adjust,
 270 };
 271
 272 const struct of_device_id of_fe_match[] = {
 273         { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
 274         { .compatible = "ralink,mt7621-eth", .data = &mt7621_data },
 275         {},
 276 };
 277
 278 MODULE_DEVICE_TABLE(of, of_fe_match);