c406013228cdb254e296f9a9b5116465c1c66879
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
18 #include <linux/module.h>
20 #include <asm/mach-ralink/ralink_regs.h>
21 #ifdef CONFIG_SOC_MT7620
22 static inline int soc_is_rt3352(void)
27 static inline int soc_is_rt3052(void)
32 #include <asm/mach-ralink/rt305x.h>
35 #include "ralink_soc_eth.h"
36 #include "mdio_rt2880.h"
38 #define RT305X_RESET_FE BIT(21)
39 #define RT305X_RESET_ESW BIT(23)
40 #define SYSC_REG_RESET_CTRL 0x034
42 static const u32 rt5350_reg_table
[FE_REG_COUNT
] = {
43 [FE_REG_PDMA_GLO_CFG
] = RT5350_PDMA_GLO_CFG
,
44 [FE_REG_PDMA_RST_CFG
] = RT5350_PDMA_RST_CFG
,
45 [FE_REG_DLY_INT_CFG
] = RT5350_DLY_INT_CFG
,
46 [FE_REG_TX_BASE_PTR0
] = RT5350_TX_BASE_PTR0
,
47 [FE_REG_TX_MAX_CNT0
] = RT5350_TX_MAX_CNT0
,
48 [FE_REG_TX_CTX_IDX0
] = RT5350_TX_CTX_IDX0
,
49 [FE_REG_RX_BASE_PTR0
] = RT5350_RX_BASE_PTR0
,
50 [FE_REG_RX_MAX_CNT0
] = RT5350_RX_MAX_CNT0
,
51 [FE_REG_RX_CALC_IDX0
] = RT5350_RX_CALC_IDX0
,
52 [FE_REG_FE_INT_ENABLE
] = RT5350_FE_INT_ENABLE
,
53 [FE_REG_FE_INT_STATUS
] = RT5350_FE_INT_STATUS
,
54 [FE_REG_FE_RST_GL
] = 0,
55 [FE_REG_FE_DMA_VID_BASE
] = 0,
58 static void rt305x_init_data(struct fe_soc_data
*data
,
59 struct net_device
*netdev
)
61 struct fe_priv
*priv
= netdev_priv(netdev
);
63 priv
->flags
= FE_FLAG_PADDING_64B
| FE_FLAG_PADDING_BUG
;
64 netdev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
|
65 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
;
68 static int rt3050_fwd_config(struct fe_priv
*priv
)
72 if (soc_is_rt3052()) {
73 ret
= fe_set_clock_cycle(priv
);
80 fe_w32(FE_PSE_FQFC_CFG_INIT
, FE_PSE_FQ_CFG
);
86 static void rt305x_fe_reset(void)
88 rt_sysc_w32(RT305X_RESET_FE
, SYSC_REG_RESET_CTRL
);
89 rt_sysc_w32(0, SYSC_REG_RESET_CTRL
);
92 static void rt5350_init_data(struct fe_soc_data
*data
,
93 struct net_device
*netdev
)
95 netdev
->hw_features
= NETIF_F_SG
| NETIF_F_RXCSUM
;
98 static void rt5350_set_mac(struct fe_priv
*priv
, unsigned char *mac
)
102 spin_lock_irqsave(&priv
->page_lock
, flags
);
103 fe_w32((mac
[0] << 8) | mac
[1], RT5350_SDM_MAC_ADRH
);
104 fe_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
105 RT5350_SDM_MAC_ADRL
);
106 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
109 static void rt5350_rxcsum_config(bool enable
)
112 fe_w32(fe_r32(RT5350_SDM_CFG
) | (RT5350_SDM_ICS_EN
|
113 RT5350_SDM_TCS_EN
| RT5350_SDM_UCS_EN
),
116 fe_w32(fe_r32(RT5350_SDM_CFG
) & ~(RT5350_SDM_ICS_EN
|
117 RT5350_SDM_TCS_EN
| RT5350_SDM_UCS_EN
),
121 static int rt5350_fwd_config(struct fe_priv
*priv
)
123 struct net_device
*dev
= priv_netdev(priv
);
125 rt5350_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
130 static void rt5350_tx_dma(struct fe_priv
*priv
, int idx
, struct sk_buff
*skb
)
132 priv
->tx_dma
[idx
].txd4
= 0;
135 static void rt5350_fe_reset(void)
137 rt_sysc_w32(RT305X_RESET_FE
| RT305X_RESET_ESW
, SYSC_REG_RESET_CTRL
);
138 rt_sysc_w32(0, SYSC_REG_RESET_CTRL
);
141 static struct fe_soc_data rt3050_data
= {
142 .mac
= { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
143 .init_data
= rt305x_init_data
,
144 .reset_fe
= rt305x_fe_reset
,
145 .fwd_config
= rt3050_fwd_config
,
146 .pdma_glo_cfg
= FE_PDMA_SIZE_8DWORDS
,
147 .checksum_bit
= RX_DMA_L4VALID
,
148 .tx_udf_bit
= TX_DMA_UDF
,
149 .rx_dly_int
= FE_RX_DLY_INT
,
150 .tx_dly_int
= FE_TX_DLY_INT
,
153 static struct fe_soc_data rt5350_data
= {
154 .mac
= { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
155 .init_data
= rt5350_init_data
,
156 .reg_table
= rt5350_reg_table
,
157 .reset_fe
= rt5350_fe_reset
,
158 .set_mac
= rt5350_set_mac
,
159 .fwd_config
= rt5350_fwd_config
,
160 .tx_dma
= rt5350_tx_dma
,
161 .pdma_glo_cfg
= FE_PDMA_SIZE_8DWORDS
,
162 .checksum_bit
= RX_DMA_L4VALID
,
163 .tx_udf_bit
= TX_DMA_UDF
,
164 .rx_dly_int
= RT5350_RX_DLY_INT
,
165 .tx_dly_int
= RT5350_TX_DLY_INT
,
168 const struct of_device_id of_fe_match
[] = {
169 { .compatible
= "ralink,rt3050-eth", .data
= &rt3050_data
},
170 { .compatible
= "ralink,rt5350-eth", .data
= &rt5350_data
},
174 MODULE_DEVICE_TABLE(of
, of_fe_match
);