target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_eth.h

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   based on Ralink SDK3.3
  16  *   Copyright (C) 2009 John Crispin <blogic@openwrt.org>
  17  */
  18
  19 #ifndef RAMIPS_ETH_H
  20 #define RAMIPS_ETH_H
  21
  22 #include <linux/mii.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #define NUM_RX_DESC     256
  28 #define NUM_TX_DESC     256
  29
  30 #define RAMIPS_DELAY_EN_INT             0x80
  31 #define RAMIPS_DELAY_MAX_INT            0x04
  32 #define RAMIPS_DELAY_MAX_TOUT           0x04
  33 #define RAMIPS_DELAY_CHAN               (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT)
  34 #define RAMIPS_DELAY_INIT               ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN)
  35 #define RAMIPS_PSE_FQFC_CFG_INIT        0x80504000
  36
  37 /* interrupt bits */
  38 #define RAMIPS_CNT_PPE_AF               BIT(31)
  39 #define RAMIPS_CNT_GDM_AF               BIT(29)
  40 #define RAMIPS_PSE_P2_FC                BIT(26)
  41 #define RAMIPS_PSE_BUF_DROP             BIT(24)
  42 #define RAMIPS_GDM_OTHER_DROP           BIT(23)
  43 #define RAMIPS_PSE_P1_FC                BIT(22)
  44 #define RAMIPS_PSE_P0_FC                BIT(21)
  45 #define RAMIPS_PSE_FQ_EMPTY             BIT(20)
  46 #define RAMIPS_GE1_STA_CHG              BIT(18)
  47 #define RAMIPS_TX_COHERENT              BIT(17)
  48 #define RAMIPS_RX_COHERENT              BIT(16)
  49 #define RAMIPS_TX_DONE_INT3             BIT(11)
  50 #define RAMIPS_TX_DONE_INT2             BIT(10)
  51 #define RAMIPS_TX_DONE_INT1             BIT(9)
  52 #define RAMIPS_TX_DONE_INT0             BIT(8)
  53 #define RAMIPS_RX_DONE_INT0             BIT(2)
  54 #define RAMIPS_TX_DLY_INT               BIT(1)
  55 #define RAMIPS_RX_DLY_INT               BIT(0)
  56
  57 /* registers */
  58 #define RAMIPS_FE_OFFSET                0x0000
  59 #define RAMIPS_GDMA_OFFSET              0x0020
  60 #define RAMIPS_PSE_OFFSET               0x0040
  61 #define RAMIPS_GDMA2_OFFSET             0x0060
  62 #define RAMIPS_CDMA_OFFSET              0x0080
  63 #define RAMIPS_PDMA_OFFSET              0x0100
  64 #define RAMIPS_PPE_OFFSET               0x0200
  65 #define RAMIPS_CMTABLE_OFFSET           0x0400
  66 #define RAMIPS_POLICYTABLE_OFFSET       0x1000
  67
  68 #define RAMIPS_MDIO_ACCESS              (RAMIPS_FE_OFFSET + 0x00)
  69 #define RAMIPS_MDIO_CFG                 (RAMIPS_FE_OFFSET + 0x04)
  70 #define RAMIPS_FE_GLO_CFG               (RAMIPS_FE_OFFSET + 0x08)
  71 #define RAMIPS_FE_RST_GL                (RAMIPS_FE_OFFSET + 0x0C)
  72 #define RAMIPS_FE_INT_STATUS            (RAMIPS_FE_OFFSET + 0x10)
  73 #define RAMIPS_FE_INT_ENABLE            (RAMIPS_FE_OFFSET + 0x14)
  74 #define RAMIPS_MDIO_CFG2                (RAMIPS_FE_OFFSET + 0x18)
  75 #define RAMIPS_FOC_TS_T                 (RAMIPS_FE_OFFSET + 0x1C)
  76
  77 #define RAMIPS_GDMA1_FWD_CFG            (RAMIPS_GDMA_OFFSET + 0x00)
  78 #define RAMIPS_GDMA1_SCH_CFG            (RAMIPS_GDMA_OFFSET + 0x04)
  79 #define RAMIPS_GDMA1_SHPR_CFG           (RAMIPS_GDMA_OFFSET + 0x08)
  80 #define RAMIPS_GDMA1_MAC_ADRL           (RAMIPS_GDMA_OFFSET + 0x0C)
  81 #define RAMIPS_GDMA1_MAC_ADRH           (RAMIPS_GDMA_OFFSET + 0x10)
  82
  83 #define RAMIPS_GDMA2_FWD_CFG            (RAMIPS_GDMA2_OFFSET + 0x00)
  84 #define RAMIPS_GDMA2_SCH_CFG            (RAMIPS_GDMA2_OFFSET + 0x04)
  85 #define RAMIPS_GDMA2_SHPR_CFG           (RAMIPS_GDMA2_OFFSET + 0x08)
  86 #define RAMIPS_GDMA2_MAC_ADRL           (RAMIPS_GDMA2_OFFSET + 0x0C)
  87 #define RAMIPS_GDMA2_MAC_ADRH           (RAMIPS_GDMA2_OFFSET + 0x10)
  88
  89 #define RAMIPS_PSE_FQ_CFG               (RAMIPS_PSE_OFFSET + 0x00)
  90 #define RAMIPS_CDMA_FC_CFG              (RAMIPS_PSE_OFFSET + 0x04)
  91 #define RAMIPS_GDMA1_FC_CFG             (RAMIPS_PSE_OFFSET + 0x08)
  92 #define RAMIPS_GDMA2_FC_CFG             (RAMIPS_PSE_OFFSET + 0x0C)
  93
  94 #define RAMIPS_CDMA_CSG_CFG             (RAMIPS_CDMA_OFFSET + 0x00)
  95 #define RAMIPS_CDMA_SCH_CFG             (RAMIPS_CDMA_OFFSET + 0x04)
  96
  97 #define RAMIPS_PDMA_GLO_CFG             (RAMIPS_PDMA_OFFSET + 0x00)
  98 #define RAMIPS_PDMA_RST_CFG             (RAMIPS_PDMA_OFFSET + 0x04)
  99 #define RAMIPS_PDMA_SCH_CFG             (RAMIPS_PDMA_OFFSET + 0x08)
 100 #define RAMIPS_DLY_INT_CFG              (RAMIPS_PDMA_OFFSET + 0x0C)
 101 #define RAMIPS_TX_BASE_PTR0             (RAMIPS_PDMA_OFFSET + 0x10)
 102 #define RAMIPS_TX_MAX_CNT0              (RAMIPS_PDMA_OFFSET + 0x14)
 103 #define RAMIPS_TX_CTX_IDX0              (RAMIPS_PDMA_OFFSET + 0x18)
 104 #define RAMIPS_TX_DTX_IDX0              (RAMIPS_PDMA_OFFSET + 0x1C)
 105 #define RAMIPS_TX_BASE_PTR1             (RAMIPS_PDMA_OFFSET + 0x20)
 106 #define RAMIPS_TX_MAX_CNT1              (RAMIPS_PDMA_OFFSET + 0x24)
 107 #define RAMIPS_TX_CTX_IDX1              (RAMIPS_PDMA_OFFSET + 0x28)
 108 #define RAMIPS_TX_DTX_IDX1              (RAMIPS_PDMA_OFFSET + 0x2C)
 109 #define RAMIPS_RX_BASE_PTR0             (RAMIPS_PDMA_OFFSET + 0x30)
 110 #define RAMIPS_RX_MAX_CNT0              (RAMIPS_PDMA_OFFSET + 0x34)
 111 #define RAMIPS_RX_CALC_IDX0             (RAMIPS_PDMA_OFFSET + 0x38)
 112 #define RAMIPS_RX_DRX_IDX0              (RAMIPS_PDMA_OFFSET + 0x3C)
 113 #define RAMIPS_TX_BASE_PTR2             (RAMIPS_PDMA_OFFSET + 0x40)
 114 #define RAMIPS_TX_MAX_CNT2              (RAMIPS_PDMA_OFFSET + 0x44)
 115 #define RAMIPS_TX_CTX_IDX2              (RAMIPS_PDMA_OFFSET + 0x48)
 116 #define RAMIPS_TX_DTX_IDX2              (RAMIPS_PDMA_OFFSET + 0x4C)
 117 #define RAMIPS_TX_BASE_PTR3             (RAMIPS_PDMA_OFFSET + 0x50)
 118 #define RAMIPS_TX_MAX_CNT3              (RAMIPS_PDMA_OFFSET + 0x54)
 119 #define RAMIPS_TX_CTX_IDX3              (RAMIPS_PDMA_OFFSET + 0x58)
 120 #define RAMIPS_TX_DTX_IDX3              (RAMIPS_PDMA_OFFSET + 0x5C)
 121 #define RAMIPS_RX_BASE_PTR1             (RAMIPS_PDMA_OFFSET + 0x60)
 122 #define RAMIPS_RX_MAX_CNT1              (RAMIPS_PDMA_OFFSET + 0x64)
 123 #define RAMIPS_RX_CALC_IDX1             (RAMIPS_PDMA_OFFSET + 0x68)
 124 #define RAMIPS_RX_DRX_IDX1              (RAMIPS_PDMA_OFFSET + 0x6C)
 125
 126 /* MDIO_CFG register bits */
 127 #define RAMIPS_MDIO_CFG_AUTO_POLL_EN    BIT(29)
 128 #define RAMIPS_MDIO_CFG_GP1_BP_EN       BIT(16)
 129 #define RAMIPS_MDIO_CFG_GP1_FRC_EN      BIT(15)
 130 #define RAMIPS_MDIO_CFG_GP1_SPEED_10    (0 << 13)
 131 #define RAMIPS_MDIO_CFG_GP1_SPEED_100   (1 << 13)
 132 #define RAMIPS_MDIO_CFG_GP1_SPEED_1000  (2 << 13)
 133 #define RAMIPS_MDIO_CFG_GP1_DUPLEX      BIT(12)
 134 #define RAMIPS_MDIO_CFG_GP1_FC_TX       BIT(11)
 135 #define RAMIPS_MDIO_CFG_GP1_FC_RX       BIT(10)
 136 #define RAMIPS_MDIO_CFG_GP1_LNK_DWN     BIT(9)
 137 #define RAMIPS_MDIO_CFG_GP1_AN_FAIL     BIT(8)
 138 #define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1   (0 << 6)
 139 #define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2   (1 << 6)
 140 #define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4   (2 << 6)
 141 #define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8   (3 << 6)
 142 #define RAMIPS_MDIO_CFG_TURBO_MII_FREQ  BIT(5)
 143 #define RAMIPS_MDIO_CFG_TURBO_MII_MODE  BIT(4)
 144 #define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0   (0 << 2)
 145 #define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
 146 #define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
 147 #define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
 148 #define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0   0
 149 #define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1
 150 #define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2
 151 #define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3
 152
 153 /* uni-cast port */
 154 #define RAMIPS_GDM1_ICS_EN              BIT(22)
 155 #define RAMIPS_GDM1_TCS_EN              BIT(21)
 156 #define RAMIPS_GDM1_UCS_EN              BIT(20)
 157 #define RAMIPS_GDM1_JMB_EN              BIT(19)
 158 #define RAMIPS_GDM1_STRPCRC             BIT(16)
 159 #define RAMIPS_GDM1_UFRC_P_CPU          (0 << 12)
 160 #define RAMIPS_GDM1_UFRC_P_GDMA1        (1 << 12)
 161 #define RAMIPS_GDM1_UFRC_P_PPE          (6 << 12)
 162
 163 /* checksums */
 164 #define RAMIPS_ICS_GEN_EN               BIT(2)
 165 #define RAMIPS_UCS_GEN_EN               BIT(1)
 166 #define RAMIPS_TCS_GEN_EN               BIT(0)
 167
 168 /* dma ring */
 169 #define RAMIPS_PST_DRX_IDX0             BIT(16)
 170 #define RAMIPS_PST_DTX_IDX3             BIT(3)
 171 #define RAMIPS_PST_DTX_IDX2             BIT(2)
 172 #define RAMIPS_PST_DTX_IDX1             BIT(1)
 173 #define RAMIPS_PST_DTX_IDX0             BIT(0)
 174
 175 #define RAMIPS_TX_WB_DDONE              BIT(6)
 176 #define RAMIPS_RX_DMA_BUSY              BIT(3)
 177 #define RAMIPS_TX_DMA_BUSY              BIT(1)
 178 #define RAMIPS_RX_DMA_EN                BIT(2)
 179 #define RAMIPS_TX_DMA_EN                BIT(0)
 180
 181 #define RAMIPS_PDMA_SIZE_4DWORDS        (0 << 4)
 182 #define RAMIPS_PDMA_SIZE_8DWORDS        (1 << 4)
 183 #define RAMIPS_PDMA_SIZE_16DWORDS       (2 << 4)
 184
 185 #define RAMIPS_US_CYC_CNT_MASK          0xff
 186 #define RAMIPS_US_CYC_CNT_SHIFT         0x8
 187 #define RAMIPS_US_CYC_CNT_DIVISOR       1000000
 188
 189 #define RX_DMA_PLEN0(_x)                (((_x) >> 16) & 0x3fff)
 190 #define RX_DMA_LSO                      BIT(30)
 191 #define RX_DMA_DONE                     BIT(31)
 192
 193 struct ramips_rx_dma {
 194         unsigned int rxd1;
 195         unsigned int rxd2;
 196         unsigned int rxd3;
 197         unsigned int rxd4;
 198 } __packed __aligned(4);
 199
 200 #define TX_DMA_PLEN0_MASK               ((0x3fff) << 16)
 201 #define TX_DMA_PLEN0(_x)                (((_x) & 0x3fff) << 16)
 202 #define TX_DMA_LSO                      BIT(30)
 203 #define TX_DMA_DONE                     BIT(31)
 204 #define TX_DMA_QN(_x)                   ((_x) << 16)
 205 #define TX_DMA_PN(_x)                   ((_x) << 24)
 206 #define TX_DMA_QN_MASK                  TX_DMA_QN(0x7)
 207 #define TX_DMA_PN_MASK                  TX_DMA_PN(0x7)
 208
 209 struct ramips_tx_dma {
 210         unsigned int txd1;
 211         unsigned int txd2;
 212         unsigned int txd3;
 213         unsigned int txd4;
 214 } __packed __aligned(4);
 215
 216 struct raeth_priv
 217 {
 218         dma_addr_t              rx_desc_dma;
 219         struct tasklet_struct   rx_tasklet;
 220         struct ramips_rx_dma    *rx;
 221         struct sk_buff          *rx_skb[NUM_RX_DESC];
 222         dma_addr_t              rx_dma[NUM_RX_DESC];
 223
 224         dma_addr_t              tx_desc_dma;
 225         struct tasklet_struct   tx_housekeeping_tasklet;
 226         struct ramips_tx_dma    *tx;
 227         struct sk_buff          *tx_skb[NUM_TX_DESC];
 228
 229         unsigned int            skb_free_idx;
 230
 231         spinlock_t              page_lock;
 232         struct net_device       *netdev;
 233         struct device           *parent;
 234         struct ramips_eth_platform_data *plat;
 235
 236         int                     link;
 237         int                     speed;
 238         int                     duplex;
 239         int                     tx_fc;
 240         int                     rx_fc;
 241
 242         struct mii_bus          *mii_bus;
 243         int                     mii_irq[PHY_MAX_ADDR];
 244         struct phy_device       *phy_dev;
 245         spinlock_t              phy_lock;
 246 };
 247
 248 #endif /* RAMIPS_ETH_H */