target/linux/ramips/patches-3.10/0023-GPIO-MIPS-ralink-adds-ralink-gpio-support.patch

   1 From 3af8b2904d2d4758f88bc96c7c9ecff4a708347f Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 14 Jul 2013 23:17:27 +0200
   4 Subject: [PATCH 23/33] GPIO: MIPS: ralink: adds ralink gpio support
   5
   6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
   7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  arch/mips/Kconfig                        |    1 +
  12  arch/mips/include/asm/mach-ralink/gpio.h |   24 +++
  13  drivers/gpio/Kconfig                     |    6 +
  14  drivers/gpio/Makefile                    |    1 +
  15  drivers/gpio/gpio-ralink.c               |  326 ++++++++++++++++++++++++++++++
  16  5 files changed, 358 insertions(+)
  17  create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
  18  create mode 100644 drivers/gpio/gpio-ralink.c
  19
  20 --- a/arch/mips/Kconfig
  21 +++ b/arch/mips/Kconfig
  22 @@ -443,6 +443,7 @@ config RALINK
  23         select SYS_HAS_EARLY_PRINTK
  24         select HAVE_MACH_CLKDEV
  25         select CLKDEV_LOOKUP
  26 +       select ARCH_REQUIRE_GPIOLIB
  27
  28  config SGI_IP22
  29         bool "SGI IP22 (Indy/Indigo2)"
  30 --- /dev/null
  31 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
  32 @@ -0,0 +1,24 @@
  33 +/*
  34 + *  Ralink SoC GPIO API support
  35 + *
  36 + *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  37 + *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  38 + *
  39 + *  This program is free software; you can redistribute it and/or modify it
  40 + *  under the terms of the GNU General Public License version 2 as published
  41 + *  by the Free Software Foundation.
  42 + *
  43 + */
  44 +
  45 +#ifndef __ASM_MACH_RALINK_GPIO_H
  46 +#define __ASM_MACH_RALINK_GPIO_H
  47 +
  48 +#define ARCH_NR_GPIOS  128
  49 +#include <asm-generic/gpio.h>
  50 +
  51 +#define gpio_get_value __gpio_get_value
  52 +#define gpio_set_value __gpio_set_value
  53 +#define gpio_cansleep  __gpio_cansleep
  54 +#define gpio_to_irq    __gpio_to_irq
  55 +
  56 +#endif /* __ASM_MACH_RALINK_GPIO_H */
  57 --- a/drivers/gpio/Kconfig
  58 +++ b/drivers/gpio/Kconfig
  59 @@ -209,6 +209,12 @@ config GPIO_RCAR
  60         help
  61           Say yes here to support GPIO on Renesas R-Car SoCs.
  62
  63 +config GPIO_RALINK
  64 +       bool "Ralink GPIO Support"
  65 +       depends on RALINK
  66 +       help
  67 +         Say yes here to support the Ralink SoC GPIO device
  68 +
  69  config GPIO_SPEAR_SPICS
  70         bool "ST SPEAr13xx SPI Chip Select as GPIO support"
  71         depends on PLAT_SPEAR
  72 --- a/drivers/gpio/Makefile
  73 +++ b/drivers/gpio/Makefile
  74 @@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_PCF857X)    += gpio-pcf85
  75  obj-$(CONFIG_GPIO_PCH)         += gpio-pch.o
  76  obj-$(CONFIG_GPIO_PL061)       += gpio-pl061.o
  77  obj-$(CONFIG_GPIO_PXA)         += gpio-pxa.o
  78 +obj-$(CONFIG_GPIO_RALINK)      += gpio-ralink.o
  79  obj-$(CONFIG_GPIO_RC5T583)     += gpio-rc5t583.o
  80  obj-$(CONFIG_GPIO_RDC321X)     += gpio-rdc321x.o
  81  obj-$(CONFIG_GPIO_RCAR)                += gpio-rcar.o
  82 --- /dev/null
  83 +++ b/drivers/gpio/gpio-ralink.c
  84 @@ -0,0 +1,326 @@
  85 +/*
  86 + * This program is free software; you can redistribute it and/or modify it
  87 + * under the terms of the GNU General Public License version 2 as published
  88 + * by the Free Software Foundation.
  89 + *
  90 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  91 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  92 + */
  93 +
  94 +#include <linux/module.h>
  95 +#include <linux/io.h>
  96 +#include <linux/gpio.h>
  97 +#include <linux/spinlock.h>
  98 +#include <linux/platform_device.h>
  99 +#include <linux/of_irq.h>
 100 +#include <linux/irqdomain.h>
 101 +#include <linux/interrupt.h>
 102 +
 103 +enum ralink_gpio_reg {
 104 +       GPIO_REG_INT = 0,
 105 +       GPIO_REG_EDGE,
 106 +       GPIO_REG_RENA,
 107 +       GPIO_REG_FENA,
 108 +       GPIO_REG_DATA,
 109 +       GPIO_REG_DIR,
 110 +       GPIO_REG_POL,
 111 +       GPIO_REG_SET,
 112 +       GPIO_REG_RESET,
 113 +       GPIO_REG_TOGGLE,
 114 +       GPIO_REG_MAX
 115 +};
 116 +
 117 +struct ralink_gpio_chip {
 118 +       struct gpio_chip chip;
 119 +       u8 regs[GPIO_REG_MAX];
 120 +
 121 +       spinlock_t lock;
 122 +       void __iomem *membase;
 123 +       struct irq_domain *domain;
 124 +       int irq;
 125 +
 126 +       u32 rising;
 127 +       u32 falling;
 128 +};
 129 +
 130 +#define MAP_MAX        4
 131 +static struct irq_domain *irq_map[MAP_MAX];
 132 +static int irq_map_count;
 133 +static atomic_t irq_refcount = ATOMIC_INIT(0);
 134 +
 135 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
 136 +{
 137 +       struct ralink_gpio_chip *rg;
 138 +
 139 +       rg = container_of(chip, struct ralink_gpio_chip, chip);
 140 +
 141 +       return rg;
 142 +}
 143 +
 144 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
 145 +{
 146 +       iowrite32(val, rg->membase + rg->regs[reg]);
 147 +}
 148 +
 149 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
 150 +{
 151 +       return ioread32(rg->membase + rg->regs[reg]);
 152 +}
 153 +
 154 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 155 +{
 156 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 157 +
 158 +       rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
 159 +}
 160 +
 161 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
 162 +{
 163 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 164 +
 165 +       return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 166 +}
 167 +
 168 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 169 +{
 170 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 171 +       unsigned long flags;
 172 +       u32 t;
 173 +
 174 +       spin_lock_irqsave(&rg->lock, flags);
 175 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 176 +       t &= ~BIT(offset);
 177 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 178 +       spin_unlock_irqrestore(&rg->lock, flags);
 179 +
 180 +       return 0;
 181 +}
 182 +
 183 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
 184 +                                       unsigned offset, int value)
 185 +{
 186 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 187 +       unsigned long flags;
 188 +       u32 t;
 189 +
 190 +       spin_lock_irqsave(&rg->lock, flags);
 191 +       ralink_gpio_set(chip, offset, value);
 192 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 193 +       t |= BIT(offset);
 194 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 195 +       spin_unlock_irqrestore(&rg->lock, flags);
 196 +
 197 +       return 0;
 198 +}
 199 +
 200 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 201 +{
 202 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 203 +
 204 +       if (rg->irq < 1)
 205 +               return -1;
 206 +
 207 +       ralink_gpio_direction_input(chip, pin);
 208 +
 209 +       return irq_create_mapping(rg->domain, pin);
 210 +}
 211 +
 212 +static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 213 +{
 214 +       int i;
 215 +
 216 +       for (i = 0; i < irq_map_count; i++) {
 217 +               struct irq_domain *domain = irq_map[i];
 218 +               struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) domain->host_data;
 219 +               unsigned long pending = rt_gpio_r32(rg, GPIO_REG_INT);
 220 +               int bit;
 221 +
 222 +               for_each_set_bit(bit, &pending, rg->chip.ngpio) {
 223 +                       u32 map = irq_find_mapping(domain, bit);
 224 +                       generic_handle_irq(map);
 225 +                       rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
 226 +               }
 227 +       }
 228 +}
 229 +
 230 +static void ralink_gpio_irq_unmask(struct irq_data *d)
 231 +{
 232 +       struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
 233 +       u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
 234 +       unsigned long flags;
 235 +
 236 +       spin_lock_irqsave(&rg->lock, flags);
 237 +       rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
 238 +       rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
 239 +       spin_unlock_irqrestore(&rg->lock, flags);
 240 +}
 241 +
 242 +static void ralink_gpio_irq_mask(struct irq_data *d)
 243 +{
 244 +       struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
 245 +       u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
 246 +       unsigned long flags;
 247 +
 248 +       spin_lock_irqsave(&rg->lock, flags);
 249 +       rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
 250 +       rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
 251 +       spin_unlock_irqrestore(&rg->lock, flags);
 252 +}
 253 +
 254 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
 255 +{
 256 +       struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
 257 +       u32 mask = BIT(d->hwirq);
 258 +
 259 +       if (type == IRQ_TYPE_PROBE) {
 260 +               if ((rg->rising | rg->falling) & mask)
 261 +                       return 0;
 262 +
 263 +               type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_RISING;
 264 +       }
 265 +
 266 +       if (type & IRQ_TYPE_EDGE_RISING)
 267 +               rg->rising |= mask;
 268 +       else
 269 +               rg->rising &= mask;
 270 +
 271 +       if (type & IRQ_TYPE_EDGE_RISING)
 272 +               rg->falling |= mask;
 273 +       else
 274 +               rg->falling &= mask;
 275 +
 276 +       return 0;
 277 +}
 278 +
 279 +static struct irq_chip ralink_gpio_irq_chip = {
 280 +       .name           = "GPIO",
 281 +       .irq_unmask     = ralink_gpio_irq_unmask,
 282 +       .irq_mask       = ralink_gpio_irq_mask,
 283 +       .irq_mask_ack   = ralink_gpio_irq_mask,
 284 +       .irq_set_type   = ralink_gpio_irq_type,
 285 +};
 286 +
 287 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 288 +{
 289 +       irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
 290 +       irq_set_handler_data(irq, d);
 291 +
 292 +       return 0;
 293 +}
 294 +
 295 +static const struct irq_domain_ops irq_domain_ops = {
 296 +       .xlate = irq_domain_xlate_onecell,
 297 +       .map = gpio_map,
 298 +};
 299 +
 300 +static void ralink_gpio_irq_init(struct device_node *np, struct ralink_gpio_chip *rg)
 301 +{
 302 +       if (irq_map_count >= MAP_MAX)
 303 +               return;
 304 +
 305 +       rg->irq = irq_of_parse_and_map(np, 0);
 306 +       if (!rg->irq)
 307 +               return;
 308 +
 309 +       rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, &irq_domain_ops, rg);
 310 +       if (!rg->domain) {
 311 +               dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
 312 +               return;
 313 +       }
 314 +
 315 +       irq_map[irq_map_count++] = rg->domain;
 316 +
 317 +       rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
 318 +       rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
 319 +
 320 +       if (!atomic_read(&irq_refcount))
 321 +               irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
 322 +       atomic_inc(&irq_refcount);
 323 +
 324 +       dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
 325 +}
 326 +
 327 +static int ralink_gpio_probe(struct platform_device *pdev)
 328 +{
 329 +       struct device_node *np = pdev->dev.of_node;
 330 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 331 +       struct ralink_gpio_chip *rg;
 332 +       const __be32 *ngpio, *gpiobase;
 333 +
 334 +       if (!res) {
 335 +               dev_err(&pdev->dev, "failed to find resource\n");
 336 +               return -ENOMEM;
 337 +       }
 338 +
 339 +       rg = devm_kzalloc(&pdev->dev,
 340 +                       sizeof(struct ralink_gpio_chip), GFP_KERNEL);
 341 +       if (!rg)
 342 +               return -ENOMEM;
 343 +
 344 +       rg->membase = devm_request_and_ioremap(&pdev->dev, res);
 345 +       if (!rg->membase) {
 346 +               dev_err(&pdev->dev, "cannot remap I/O memory region\n");
 347 +               return -ENOMEM;
 348 +       }
 349 +
 350 +       if (of_property_read_u8_array(np, "ralink,register-map",
 351 +                       rg->regs, GPIO_REG_MAX)) {
 352 +               dev_err(&pdev->dev, "failed to read register definition\n");
 353 +               return -EINVAL;
 354 +       }
 355 +
 356 +       ngpio = of_get_property(np, "ralink,num-gpios", NULL);
 357 +       if (!ngpio) {
 358 +               dev_err(&pdev->dev, "failed to read number of pins\n");
 359 +               return -EINVAL;
 360 +       }
 361 +
 362 +       gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
 363 +       if (gpiobase)
 364 +               rg->chip.base = be32_to_cpu(*gpiobase);
 365 +       else
 366 +               rg->chip.base = -1;
 367 +
 368 +       spin_lock_init(&rg->lock);
 369 +
 370 +       rg->chip.dev = &pdev->dev;
 371 +       rg->chip.label = dev_name(&pdev->dev);
 372 +       rg->chip.of_node = np;
 373 +       rg->chip.ngpio = be32_to_cpu(*ngpio);
 374 +       rg->chip.direction_input = ralink_gpio_direction_input;
 375 +       rg->chip.direction_output = ralink_gpio_direction_output;
 376 +       rg->chip.get = ralink_gpio_get;
 377 +       rg->chip.set = ralink_gpio_set;
 378 +       rg->chip.to_irq = ralink_gpio_to_irq;
 379 +
 380 +       /* set polarity to low for all lines */
 381 +       rt_gpio_w32(rg, GPIO_REG_POL, 0);
 382 +
 383 +       dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
 384 +
 385 +       ralink_gpio_irq_init(np, rg);
 386 +
 387 +       return gpiochip_add(&rg->chip);
 388 +}
 389 +
 390 +static const struct of_device_id ralink_gpio_match[] = {
 391 +       { .compatible = "ralink,rt2880-gpio" },
 392 +       {},
 393 +};
 394 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
 395 +
 396 +static struct platform_driver ralink_gpio_driver = {
 397 +       .probe = ralink_gpio_probe,
 398 +       .driver = {
 399 +               .name = "rt2880_gpio",
 400 +               .owner = THIS_MODULE,
 401 +               .of_match_table = ralink_gpio_match,
 402 +       },
 403 +};
 404 +
 405 +static int __init ralink_gpio_init(void)
 406 +{
 407 +       return platform_driver_register(&ralink_gpio_driver);
 408 +}
 409 +
 410 +subsys_initcall(ralink_gpio_init);