projects / openwrt / svn-archive / archive.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: update 3.10 to 3.10.2
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.10 / 0027-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
1 From de1defdad7554d6ba885a6d3dc55105e01e9a07e Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 2 May 2013 14:59:01 +0200
4 Subject: [PATCH 27/33] mmc: MIPS: ralink: add sdhci for mt7620a SoC
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mmc/host/Kconfig | 11 +
9 drivers/mmc/host/Makefile | 1 +
10 drivers/mmc/host/mt6575_sd.h | 1068 ++++++++++++++++++
11 drivers/mmc/host/sdhci-mt7620.c | 2314 +++++++++++++++++++++++++++++++++++++++
12 4 files changed, 3394 insertions(+)
13 create mode 100644 drivers/mmc/host/mt6575_sd.h
14 create mode 100644 drivers/mmc/host/sdhci-mt7620.c
15
16 --- a/drivers/mmc/host/Kconfig
17 +++ b/drivers/mmc/host/Kconfig
18 @@ -260,6 +260,17 @@ config MMC_SDHCI_BCM2835
19
20 If unsure, say N.
21
22 +config MMC_SDHCI_MT7620
23 + tristate "SDHCI platform support for the MT7620 SD/MMC Controller"
24 + depends on SOC_MT7620
25 + depends on MMC_SDHCI_PLTFM
26 + select MMC_SDHCI_IO_ACCESSORS
27 + help
28 + This selects the BCM2835 SD/MMC controller. If you have a BCM2835
29 + platform with SD or MMC devices, say Y or M here.
30 +
31 + If unsure, say N.
32 +
33 config MMC_OMAP
34 tristate "TI OMAP Multimedia Card Interface support"
35 depends on ARCH_OMAP
36 --- a/drivers/mmc/host/Makefile
37 +++ b/drivers/mmc/host/Makefile
38 @@ -62,6 +62,7 @@ obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-
39 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
40 obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
41 obj-$(CONFIG_MMC_SDHCI_BCM2835) += sdhci-bcm2835.o
42 +obj-$(CONFIG_MMC_SDHCI_MT7620) += sdhci-mt7620.o
43
44 ifeq ($(CONFIG_CB710_DEBUG),y)
45 CFLAGS-cb710-mmc += -DDEBUG
46 --- /dev/null
47 +++ b/drivers/mmc/host/mt6575_sd.h
48 @@ -0,0 +1,1068 @@
49 +/* Copyright Statement:
50 + *
51 + * This software/firmware and related documentation ("MediaTek Software") are
52 + * protected under relevant copyright laws. The information contained herein
53 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
54 + * Without the prior written permission of MediaTek inc. and/or its licensors,
55 + * any reproduction, modification, use or disclosure of MediaTek Software,
56 + * and information contained herein, in whole or in part, shall be strictly prohibited.
57 + */
58 +/* MediaTek Inc. (C) 2010. All rights reserved.
59 + *
60 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
61 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
62 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
63 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
64 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
65 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
66 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
67 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
68 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
69 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
70 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
71 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
72 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
73 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
74 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
75 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
76 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
77 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
78 + *
79 + * The following software/firmware and/or related documentation ("MediaTek Software")
80 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
81 + * applicable license agreements with MediaTek Inc.
82 + */
83 +
84 +#ifndef MT6575_SD_H
85 +#define MT6575_SD_H
86 +
87 +#include <linux/bitops.h>
88 +#include <linux/mmc/host.h>
89 +
90 +// #include <mach/mt6575_reg_base.h> /* --- by chhung */
91 +
92 +typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
93 +typedef void (*pm_callback_t)(pm_message_t state, void *data);
94 +
95 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
96 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
97 +#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
98 +#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
99 +#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
100 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
101 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
102 +#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
103 +#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
104 +#define MSDC_DDR (1 << 9) /* ddr mode support */
105 +#define MSDC_SPE (1 << 10) /* special support */
106 +#define MSDC_INTERNAL_CLK (1 << 11) /* Force Internal clock */
107 +#define MSDC_TABDRV (1 << 12) /* TABLET */
108 +
109 +
110 +#define MSDC_SMPL_RISING (0)
111 +#define MSDC_SMPL_FALLING (1)
112 +
113 +#define MSDC_CMD_PIN (0)
114 +#define MSDC_DAT_PIN (1)
115 +#define MSDC_CD_PIN (2)
116 +#define MSDC_WP_PIN (3)
117 +#define MSDC_RST_PIN (4)
118 +
119 +enum {
120 + MSDC_CLKSRC_26MHZ = 0,
121 + MSDC_CLKSRC_197MHZ = 1,
122 + MSDC_CLKSRC_208MHZ = 2
123 +};
124 +
125 +struct msdc_hw {
126 + unsigned char clk_src; /* host clock source */
127 + unsigned char cmd_edge; /* command latch edge */
128 + unsigned char data_edge; /* data latch edge */
129 + unsigned char clk_drv; /* clock pad driving */
130 + unsigned char cmd_drv; /* command pad driving */
131 + unsigned char dat_drv; /* data pad driving */
132 + unsigned long flags; /* hardware capability flags */
133 + unsigned long data_pins; /* data pins */
134 + unsigned long data_offset; /* data address offset */
135 +
136 + /* config gpio pull mode */
137 + void (*config_gpio_pin)(int type, int pull);
138 +
139 + /* external power control for card */
140 + void (*ext_power_on)(void);
141 + void (*ext_power_off)(void);
142 +
143 + /* external sdio irq operations */
144 + void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
145 + void (*enable_sdio_eirq)(void);
146 + void (*disable_sdio_eirq)(void);
147 +
148 + /* external cd irq operations */
149 + void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
150 + void (*enable_cd_eirq)(void);
151 + void (*disable_cd_eirq)(void);
152 + int (*get_cd_status)(void);
153 +
154 + /* power management callback for external module */
155 + void (*register_pm)(pm_callback_t pm_cb, void *data);
156 +};
157 +
158 +extern struct msdc_hw msdc0_hw;
159 +extern struct msdc_hw msdc1_hw;
160 +extern struct msdc_hw msdc2_hw;
161 +extern struct msdc_hw msdc3_hw;
162 +
163 +
164 +/*--------------------------------------------------------------------------*/
165 +/* Common Macro */
166 +/*--------------------------------------------------------------------------*/
167 +#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
168 +
169 +/*--------------------------------------------------------------------------*/
170 +/* Common Definition */
171 +/*--------------------------------------------------------------------------*/
172 +#define MSDC_FIFO_SZ (128)
173 +#define MSDC_FIFO_THD (64) // (128)
174 +#define MSDC_NUM (4)
175 +
176 +#define MSDC_MS (0)
177 +#define MSDC_SDMMC (1)
178 +
179 +#define MSDC_MODE_UNKNOWN (0)
180 +#define MSDC_MODE_PIO (1)
181 +#define MSDC_MODE_DMA_BASIC (2)
182 +#define MSDC_MODE_DMA_DESC (3)
183 +#define MSDC_MODE_DMA_ENHANCED (4)
184 +#define MSDC_MODE_MMC_STREAM (5)
185 +
186 +#define MSDC_BUS_1BITS (0)
187 +#define MSDC_BUS_4BITS (1)
188 +#define MSDC_BUS_8BITS (2)
189 +
190 +#define MSDC_BRUST_8B (3)
191 +#define MSDC_BRUST_16B (4)
192 +#define MSDC_BRUST_32B (5)
193 +#define MSDC_BRUST_64B (6)
194 +
195 +#define MSDC_PIN_PULL_NONE (0)
196 +#define MSDC_PIN_PULL_DOWN (1)
197 +#define MSDC_PIN_PULL_UP (2)
198 +#define MSDC_PIN_KEEP (3)
199 +
200 +#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
201 +#define MSDC_MIN_SCLK (260000)
202 +
203 +#define MSDC_AUTOCMD12 (0x0001)
204 +#define MSDC_AUTOCMD23 (0x0002)
205 +#define MSDC_AUTOCMD19 (0x0003)
206 +
207 +#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
208 +#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
209 +
210 +enum {
211 + RESP_NONE = 0,
212 + RESP_R1,
213 + RESP_R2,
214 + RESP_R3,
215 + RESP_R4,
216 + RESP_R5,
217 + RESP_R6,
218 + RESP_R7,
219 + RESP_R1B
220 +};
221 +
222 +/*--------------------------------------------------------------------------*/
223 +/* Register Offset */
224 +/*--------------------------------------------------------------------------*/
225 +#define OFFSET_MSDC_CFG (0x0)
226 +#define OFFSET_MSDC_IOCON (0x04)
227 +#define OFFSET_MSDC_PS (0x08)
228 +#define OFFSET_MSDC_INT (0x0c)
229 +#define OFFSET_MSDC_INTEN (0x10)
230 +#define OFFSET_MSDC_FIFOCS (0x14)
231 +#define OFFSET_MSDC_TXDATA (0x18)
232 +#define OFFSET_MSDC_RXDATA (0x1c)
233 +#define OFFSET_SDC_CFG (0x30)
234 +#define OFFSET_SDC_CMD (0x34)
235 +#define OFFSET_SDC_ARG (0x38)
236 +#define OFFSET_SDC_STS (0x3c)
237 +#define OFFSET_SDC_RESP0 (0x40)
238 +#define OFFSET_SDC_RESP1 (0x44)
239 +#define OFFSET_SDC_RESP2 (0x48)
240 +#define OFFSET_SDC_RESP3 (0x4c)
241 +#define OFFSET_SDC_BLK_NUM (0x50)
242 +#define OFFSET_SDC_CSTS (0x58)
243 +#define OFFSET_SDC_CSTS_EN (0x5c)
244 +#define OFFSET_SDC_DCRC_STS (0x60)
245 +#define OFFSET_EMMC_CFG0 (0x70)
246 +#define OFFSET_EMMC_CFG1 (0x74)
247 +#define OFFSET_EMMC_STS (0x78)
248 +#define OFFSET_EMMC_IOCON (0x7c)
249 +#define OFFSET_SDC_ACMD_RESP (0x80)
250 +#define OFFSET_SDC_ACMD19_TRG (0x84)
251 +#define OFFSET_SDC_ACMD19_STS (0x88)
252 +#define OFFSET_MSDC_DMA_SA (0x90)
253 +#define OFFSET_MSDC_DMA_CA (0x94)
254 +#define OFFSET_MSDC_DMA_CTRL (0x98)
255 +#define OFFSET_MSDC_DMA_CFG (0x9c)
256 +#define OFFSET_MSDC_DBG_SEL (0xa0)
257 +#define OFFSET_MSDC_DBG_OUT (0xa4)
258 +#define OFFSET_MSDC_PATCH_BIT (0xb0)
259 +#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
260 +#define OFFSET_MSDC_PAD_CTL0 (0xe0)
261 +#define OFFSET_MSDC_PAD_CTL1 (0xe4)
262 +#define OFFSET_MSDC_PAD_CTL2 (0xe8)
263 +#define OFFSET_MSDC_PAD_TUNE (0xec)
264 +#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
265 +#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
266 +#define OFFSET_MSDC_HW_DBG (0xf8)
267 +#define OFFSET_MSDC_VERSION (0x100)
268 +#define OFFSET_MSDC_ECO_VER (0x104)
269 +
270 +/*--------------------------------------------------------------------------*/
271 +/* Register Address */
272 +/*--------------------------------------------------------------------------*/
273 +
274 +/* common register */
275 +#define MSDC_CFG REG_ADDR(MSDC_CFG)
276 +#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
277 +#define MSDC_PS REG_ADDR(MSDC_PS)
278 +#define MSDC_INT REG_ADDR(MSDC_INT)
279 +#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
280 +#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
281 +#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
282 +#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
283 +#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
284 +
285 +/* sdmmc register */
286 +#define SDC_CFG REG_ADDR(SDC_CFG)
287 +#define SDC_CMD REG_ADDR(SDC_CMD)
288 +#define SDC_ARG REG_ADDR(SDC_ARG)
289 +#define SDC_STS REG_ADDR(SDC_STS)
290 +#define SDC_RESP0 REG_ADDR(SDC_RESP0)
291 +#define SDC_RESP1 REG_ADDR(SDC_RESP1)
292 +#define SDC_RESP2 REG_ADDR(SDC_RESP2)
293 +#define SDC_RESP3 REG_ADDR(SDC_RESP3)
294 +#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
295 +#define SDC_CSTS REG_ADDR(SDC_CSTS)
296 +#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
297 +#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
298 +
299 +/* emmc register*/
300 +#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
301 +#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
302 +#define EMMC_STS REG_ADDR(EMMC_STS)
303 +#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
304 +
305 +/* auto command register */
306 +#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
307 +#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
308 +#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
309 +
310 +/* dma register */
311 +#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
312 +#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
313 +#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
314 +#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
315 +
316 +/* pad ctrl register */
317 +#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
318 +#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
319 +#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
320 +
321 +/* data read delay */
322 +#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
323 +#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
324 +
325 +/* debug register */
326 +#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
327 +#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
328 +
329 +/* misc register */
330 +#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
331 +#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
332 +#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
333 +#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
334 +#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
335 +#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
336 +
337 +/*--------------------------------------------------------------------------*/
338 +/* Register Mask */
339 +/*--------------------------------------------------------------------------*/
340 +
341 +/* MSDC_CFG mask */
342 +#define MSDC_CFG_MODE (0x1 << 0) /* RW */
343 +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
344 +#define MSDC_CFG_RST (0x1 << 2) /* RW */
345 +#define MSDC_CFG_PIO (0x1 << 3) /* RW */
346 +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
347 +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
348 +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
349 +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
350 +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
351 +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
352 +
353 +/* MSDC_IOCON mask */
354 +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
355 +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
356 +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
357 +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
358 +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
359 +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
360 +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
361 +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
362 +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
363 +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
364 +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
365 +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
366 +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
367 +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
368 +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
369 +
370 +/* MSDC_PS mask */
371 +#define MSDC_PS_CDEN (0x1 << 0) /* RW */
372 +#define MSDC_PS_CDSTS (0x1 << 1) /* R */
373 +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
374 +#define MSDC_PS_DAT (0xff << 16) /* R */
375 +#define MSDC_PS_CMD (0x1 << 24) /* R */
376 +#define MSDC_PS_WP (0x1UL<< 31) /* R */
377 +
378 +/* MSDC_INT mask */
379 +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
380 +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
381 +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
382 +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
383 +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
384 +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
385 +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
386 +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
387 +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
388 +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
389 +#define MSDC_INT_CSTA (0x1 << 11) /* R */
390 +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
391 +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
392 +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
393 +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
394 +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
395 +
396 +/* MSDC_INTEN mask */
397 +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
398 +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
399 +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
400 +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
401 +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
402 +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
403 +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
404 +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
405 +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
406 +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
407 +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
408 +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
409 +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
410 +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
411 +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
412 +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
413 +
414 +/* MSDC_FIFOCS mask */
415 +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
416 +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
417 +#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
418 +
419 +/* SDC_CFG mask */
420 +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
421 +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
422 +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
423 +#define SDC_CFG_SDIO (0x1 << 19) /* RW */
424 +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
425 +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
426 +#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
427 +
428 +/* SDC_CMD mask */
429 +#define SDC_CMD_OPC (0x3f << 0) /* RW */
430 +#define SDC_CMD_BRK (0x1 << 6) /* RW */
431 +#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
432 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
433 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
434 +#define SDC_CMD_RW (0x1 << 13) /* RW */
435 +#define SDC_CMD_STOP (0x1 << 14) /* RW */
436 +#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
437 +#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
438 +#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
439 +#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
440 +
441 +/* SDC_STS mask */
442 +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
443 +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
444 +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
445 +
446 +/* SDC_DCRC_STS mask */
447 +#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
448 +#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
449 +
450 +/* EMMC_CFG0 mask */
451 +#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
452 +#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
453 +#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
454 +#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
455 +#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
456 +#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
457 +
458 +/* EMMC_CFG1 mask */
459 +#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
460 +#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
461 +
462 +/* EMMC_STS mask */
463 +#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
464 +#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
465 +#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
466 +#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
467 +#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
468 +#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
469 +#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
470 +
471 +/* EMMC_IOCON mask */
472 +#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
473 +
474 +/* SDC_ACMD19_TRG mask */
475 +#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
476 +
477 +/* MSDC_DMA_CTRL mask */
478 +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
479 +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
480 +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
481 +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
482 +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
483 +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
484 +#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
485 +
486 +/* MSDC_DMA_CFG mask */
487 +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
488 +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
489 +#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
490 +#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
491 +
492 +/* MSDC_PATCH_BIT mask */
493 +#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
494 +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
495 +#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
496 +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
497 +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
498 +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
499 +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
500 +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
501 +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
502 +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
503 +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
504 +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
505 +
506 +/* MSDC_PATCH_BIT1 mask */
507 +#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
508 +#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
509 +
510 +/* MSDC_PAD_CTL0 mask */
511 +#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
512 +#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
513 +#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
514 +#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
515 +#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
516 +#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
517 +#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
518 +#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
519 +#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
520 +
521 +/* MSDC_PAD_CTL1 mask */
522 +#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
523 +#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
524 +#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
525 +#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
526 +#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
527 +#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
528 +#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
529 +#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
530 +#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
531 +
532 +/* MSDC_PAD_CTL2 mask */
533 +#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
534 +#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
535 +#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
536 +#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
537 +#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
538 +#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
539 +#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
540 +#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
541 +#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
542 +
543 +/* MSDC_PAD_TUNE mask */
544 +#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
545 +#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
546 +#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
547 +#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
548 +#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
549 +
550 +/* MSDC_DAT_RDDLY0/1 mask */
551 +#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
552 +#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
553 +#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
554 +#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
555 +
556 +#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
557 +#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
558 +#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
559 +#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
560 +
561 +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
562 +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
563 +#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
564 +#define CARD_READY_FOR_DATA (1<<8)
565 +#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
566 +
567 +/*--------------------------------------------------------------------------*/
568 +/* Descriptor Structure */
569 +/*--------------------------------------------------------------------------*/
570 +typedef struct {
571 + u32 hwo:1; /* could be changed by hw */
572 + u32 bdp:1;
573 + u32 rsv0:6;
574 + u32 chksum:8;
575 + u32 intr:1;
576 + u32 rsv1:15;
577 + void *next;
578 + void *ptr;
579 + u32 buflen:16;
580 + u32 extlen:8;
581 + u32 rsv2:8;
582 + u32 arg;
583 + u32 blknum;
584 + u32 cmd;
585 +} gpd_t;
586 +
587 +typedef struct {
588 + u32 eol:1;
589 + u32 rsv0:7;
590 + u32 chksum:8;
591 + u32 rsv1:1;
592 + u32 blkpad:1;
593 + u32 dwpad:1;
594 + u32 rsv2:13;
595 + void *next;
596 + void *ptr;
597 + u32 buflen:16;
598 + u32 rsv3:16;
599 +} bd_t;
600 +
601 +/*--------------------------------------------------------------------------*/
602 +/* Register Debugging Structure */
603 +/*--------------------------------------------------------------------------*/
604 +
605 +typedef struct {
606 + u32 msdc:1;
607 + u32 ckpwn:1;
608 + u32 rst:1;
609 + u32 pio:1;
610 + u32 ckdrven:1;
611 + u32 start18v:1;
612 + u32 pass18v:1;
613 + u32 ckstb:1;
614 + u32 ckdiv:8;
615 + u32 ckmod:2;
616 + u32 pad:14;
617 +} msdc_cfg_reg;
618 +typedef struct {
619 + u32 sdr104cksel:1;
620 + u32 rsmpl:1;
621 + u32 dsmpl:1;
622 + u32 ddlysel:1;
623 + u32 ddr50ckd:1;
624 + u32 dsplsel:1;
625 + u32 pad1:10;
626 + u32 d0spl:1;
627 + u32 d1spl:1;
628 + u32 d2spl:1;
629 + u32 d3spl:1;
630 + u32 d4spl:1;
631 + u32 d5spl:1;
632 + u32 d6spl:1;
633 + u32 d7spl:1;
634 + u32 riscsz:1;
635 + u32 pad2:7;
636 +} msdc_iocon_reg;
637 +typedef struct {
638 + u32 cden:1;
639 + u32 cdsts:1;
640 + u32 pad1:10;
641 + u32 cddebounce:4;
642 + u32 dat:8;
643 + u32 cmd:1;
644 + u32 pad2:6;
645 + u32 wp:1;
646 +} msdc_ps_reg;
647 +typedef struct {
648 + u32 mmcirq:1;
649 + u32 cdsc:1;
650 + u32 pad1:1;
651 + u32 atocmdrdy:1;
652 + u32 atocmdtmo:1;
653 + u32 atocmdcrc:1;
654 + u32 dmaqempty:1;
655 + u32 sdioirq:1;
656 + u32 cmdrdy:1;
657 + u32 cmdtmo:1;
658 + u32 rspcrc:1;
659 + u32 csta:1;
660 + u32 xfercomp:1;
661 + u32 dxferdone:1;
662 + u32 dattmo:1;
663 + u32 datcrc:1;
664 + u32 atocmd19done:1;
665 + u32 pad2:15;
666 +} msdc_int_reg;
667 +typedef struct {
668 + u32 mmcirq:1;
669 + u32 cdsc:1;
670 + u32 pad1:1;
671 + u32 atocmdrdy:1;
672 + u32 atocmdtmo:1;
673 + u32 atocmdcrc:1;
674 + u32 dmaqempty:1;
675 + u32 sdioirq:1;
676 + u32 cmdrdy:1;
677 + u32 cmdtmo:1;
678 + u32 rspcrc:1;
679 + u32 csta:1;
680 + u32 xfercomp:1;
681 + u32 dxferdone:1;
682 + u32 dattmo:1;
683 + u32 datcrc:1;
684 + u32 atocmd19done:1;
685 + u32 pad2:15;
686 +} msdc_inten_reg;
687 +typedef struct {
688 + u32 rxcnt:8;
689 + u32 pad1:8;
690 + u32 txcnt:8;
691 + u32 pad2:7;
692 + u32 clr:1;
693 +} msdc_fifocs_reg;
694 +typedef struct {
695 + u32 val;
696 +} msdc_txdat_reg;
697 +typedef struct {
698 + u32 val;
699 +} msdc_rxdat_reg;
700 +typedef struct {
701 + u32 sdiowkup:1;
702 + u32 inswkup:1;
703 + u32 pad1:14;
704 + u32 buswidth:2;
705 + u32 pad2:1;
706 + u32 sdio:1;
707 + u32 sdioide:1;
708 + u32 intblkgap:1;
709 + u32 pad4:2;
710 + u32 dtoc:8;
711 +} sdc_cfg_reg;
712 +typedef struct {
713 + u32 cmd:6;
714 + u32 brk:1;
715 + u32 rsptyp:3;
716 + u32 pad1:1;
717 + u32 dtype:2;
718 + u32 rw:1;
719 + u32 stop:1;
720 + u32 goirq:1;
721 + u32 blklen:12;
722 + u32 atocmd:2;
723 + u32 volswth:1;
724 + u32 pad2:1;
725 +} sdc_cmd_reg;
726 +typedef struct {
727 + u32 arg;
728 +} sdc_arg_reg;
729 +typedef struct {
730 + u32 sdcbusy:1;
731 + u32 cmdbusy:1;
732 + u32 pad:29;
733 + u32 swrcmpl:1;
734 +} sdc_sts_reg;
735 +typedef struct {
736 + u32 val;
737 +} sdc_resp0_reg;
738 +typedef struct {
739 + u32 val;
740 +} sdc_resp1_reg;
741 +typedef struct {
742 + u32 val;
743 +} sdc_resp2_reg;
744 +typedef struct {
745 + u32 val;
746 +} sdc_resp3_reg;
747 +typedef struct {
748 + u32 num;
749 +} sdc_blknum_reg;
750 +typedef struct {
751 + u32 sts;
752 +} sdc_csts_reg;
753 +typedef struct {
754 + u32 sts;
755 +} sdc_cstsen_reg;
756 +typedef struct {
757 + u32 datcrcsts:8;
758 + u32 ddrcrcsts:4;
759 + u32 pad:20;
760 +} sdc_datcrcsts_reg;
761 +typedef struct {
762 + u32 bootstart:1;
763 + u32 bootstop:1;
764 + u32 bootmode:1;
765 + u32 pad1:9;
766 + u32 bootwaidly:3;
767 + u32 bootsupp:1;
768 + u32 pad2:16;
769 +} emmc_cfg0_reg;
770 +typedef struct {
771 + u32 bootcrctmc:16;
772 + u32 pad:4;
773 + u32 bootacktmc:12;
774 +} emmc_cfg1_reg;
775 +typedef struct {
776 + u32 bootcrcerr:1;
777 + u32 bootackerr:1;
778 + u32 bootdattmo:1;
779 + u32 bootacktmo:1;
780 + u32 bootupstate:1;
781 + u32 bootackrcv:1;
782 + u32 bootdatrcv:1;
783 + u32 pad:25;
784 +} emmc_sts_reg;
785 +typedef struct {
786 + u32 bootrst:1;
787 + u32 pad:31;
788 +} emmc_iocon_reg;
789 +typedef struct {
790 + u32 val;
791 +} msdc_acmd_resp_reg;
792 +typedef struct {
793 + u32 tunesel:4;
794 + u32 pad:28;
795 +} msdc_acmd19_trg_reg;
796 +typedef struct {
797 + u32 val;
798 +} msdc_acmd19_sts_reg;
799 +typedef struct {
800 + u32 addr;
801 +} msdc_dma_sa_reg;
802 +typedef struct {
803 + u32 addr;
804 +} msdc_dma_ca_reg;
805 +typedef struct {
806 + u32 start:1;
807 + u32 stop:1;
808 + u32 resume:1;
809 + u32 pad1:5;
810 + u32 mode:1;
811 + u32 pad2:1;
812 + u32 lastbuf:1;
813 + u32 pad3:1;
814 + u32 brustsz:3;
815 + u32 pad4:1;
816 + u32 xfersz:16;
817 +} msdc_dma_ctrl_reg;
818 +typedef struct {
819 + u32 status:1;
820 + u32 decsen:1;
821 + u32 pad1:2;
822 + u32 bdcsen:1;
823 + u32 gpdcsen:1;
824 + u32 pad2:26;
825 +} msdc_dma_cfg_reg;
826 +typedef struct {
827 + u32 sel:16;
828 + u32 pad2:16;
829 +} msdc_dbg_sel_reg;
830 +typedef struct {
831 + u32 val;
832 +} msdc_dbg_out_reg;
833 +typedef struct {
834 + u32 clkdrvn:3;
835 + u32 rsv0:1;
836 + u32 clkdrvp:3;
837 + u32 rsv1:1;
838 + u32 clksr:1;
839 + u32 rsv2:7;
840 + u32 clkpd:1;
841 + u32 clkpu:1;
842 + u32 clksmt:1;
843 + u32 clkies:1;
844 + u32 clktdsel:4;
845 + u32 clkrdsel:8;
846 +} msdc_pad_ctl0_reg;
847 +typedef struct {
848 + u32 cmddrvn:3;
849 + u32 rsv0:1;
850 + u32 cmddrvp:3;
851 + u32 rsv1:1;
852 + u32 cmdsr:1;
853 + u32 rsv2:7;
854 + u32 cmdpd:1;
855 + u32 cmdpu:1;
856 + u32 cmdsmt:1;
857 + u32 cmdies:1;
858 + u32 cmdtdsel:4;
859 + u32 cmdrdsel:8;
860 +} msdc_pad_ctl1_reg;
861 +typedef struct {
862 + u32 datdrvn:3;
863 + u32 rsv0:1;
864 + u32 datdrvp:3;
865 + u32 rsv1:1;
866 + u32 datsr:1;
867 + u32 rsv2:7;
868 + u32 datpd:1;
869 + u32 datpu:1;
870 + u32 datsmt:1;
871 + u32 daties:1;
872 + u32 dattdsel:4;
873 + u32 datrdsel:8;
874 +} msdc_pad_ctl2_reg;
875 +typedef struct {
876 + u32 wrrxdly:3;
877 + u32 pad1:5;
878 + u32 rdrxdly:8;
879 + u32 pad2:16;
880 +} msdc_pad_tune_reg;
881 +typedef struct {
882 + u32 dat0:5;
883 + u32 rsv0:3;
884 + u32 dat1:5;
885 + u32 rsv1:3;
886 + u32 dat2:5;
887 + u32 rsv2:3;
888 + u32 dat3:5;
889 + u32 rsv3:3;
890 +} msdc_dat_rddly0;
891 +typedef struct {
892 + u32 dat4:5;
893 + u32 rsv4:3;
894 + u32 dat5:5;
895 + u32 rsv5:3;
896 + u32 dat6:5;
897 + u32 rsv6:3;
898 + u32 dat7:5;
899 + u32 rsv7:3;
900 +} msdc_dat_rddly1;
901 +typedef struct {
902 + u32 dbg0sel:8;
903 + u32 dbg1sel:6;
904 + u32 pad1:2;
905 + u32 dbg2sel:6;
906 + u32 pad2:2;
907 + u32 dbg3sel:6;
908 + u32 pad3:2;
909 +} msdc_hw_dbg_reg;
910 +typedef struct {
911 + u32 val;
912 +} msdc_version_reg;
913 +typedef struct {
914 + u32 val;
915 +} msdc_eco_ver_reg;
916 +
917 +struct msdc_regs {
918 + msdc_cfg_reg msdc_cfg; /* base+0x00h */
919 + msdc_iocon_reg msdc_iocon; /* base+0x04h */
920 + msdc_ps_reg msdc_ps; /* base+0x08h */
921 + msdc_int_reg msdc_int; /* base+0x0ch */
922 + msdc_inten_reg msdc_inten; /* base+0x10h */
923 + msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
924 + msdc_txdat_reg msdc_txdat; /* base+0x18h */
925 + msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
926 + u32 rsv1[4];
927 + sdc_cfg_reg sdc_cfg; /* base+0x30h */
928 + sdc_cmd_reg sdc_cmd; /* base+0x34h */
929 + sdc_arg_reg sdc_arg; /* base+0x38h */
930 + sdc_sts_reg sdc_sts; /* base+0x3ch */
931 + sdc_resp0_reg sdc_resp0; /* base+0x40h */
932 + sdc_resp1_reg sdc_resp1; /* base+0x44h */
933 + sdc_resp2_reg sdc_resp2; /* base+0x48h */
934 + sdc_resp3_reg sdc_resp3; /* base+0x4ch */
935 + sdc_blknum_reg sdc_blknum; /* base+0x50h */
936 + u32 rsv2[1];
937 + sdc_csts_reg sdc_csts; /* base+0x58h */
938 + sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
939 + sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
940 + u32 rsv3[3];
941 + emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
942 + emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
943 + emmc_sts_reg emmc_sts; /* base+0x78h */
944 + emmc_iocon_reg emmc_iocon; /* base+0x7ch */
945 + msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
946 + msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
947 + msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
948 + u32 rsv4[1];
949 + msdc_dma_sa_reg dma_sa; /* base+0x90h */
950 + msdc_dma_ca_reg dma_ca; /* base+0x94h */
951 + msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
952 + msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
953 + msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
954 + msdc_dbg_out_reg dbg_out; /* base+0xa4h */
955 + u32 rsv5[2];
956 + u32 patch0; /* base+0xb0h */
957 + u32 patch1; /* base+0xb4h */
958 + u32 rsv6[10];
959 + msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
960 + msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
961 + msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
962 + msdc_pad_tune_reg pad_tune; /* base+0xech */
963 + msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
964 + msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
965 + msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
966 + u32 rsv7[1];
967 + msdc_version_reg version; /* base+0x100h */
968 + msdc_eco_ver_reg eco_ver; /* base+0x104h */
969 +};
970 +
971 +struct scatterlist_ex {
972 + u32 cmd;
973 + u32 arg;
974 + u32 sglen;
975 + struct scatterlist *sg;
976 +};
977 +
978 +#define DMA_FLAG_NONE (0x00000000)
979 +#define DMA_FLAG_EN_CHKSUM (0x00000001)
980 +#define DMA_FLAG_PAD_BLOCK (0x00000002)
981 +#define DMA_FLAG_PAD_DWORD (0x00000004)
982 +
983 +struct msdc_dma {
984 + u32 flags; /* flags */
985 + u32 xfersz; /* xfer size in bytes */
986 + u32 sglen; /* size of scatter list */
987 + u32 blklen; /* block size */
988 + struct scatterlist *sg; /* I/O scatter list */
989 + struct scatterlist_ex *esg; /* extended I/O scatter list */
990 + u8 mode; /* dma mode */
991 + u8 burstsz; /* burst size */
992 + u8 intr; /* dma done interrupt */
993 + u8 padding; /* padding */
994 + u32 cmd; /* enhanced mode command */
995 + u32 arg; /* enhanced mode arg */
996 + u32 rsp; /* enhanced mode command response */
997 + u32 autorsp; /* auto command response */
998 +
999 + gpd_t *gpd; /* pointer to gpd array */
1000 + bd_t *bd; /* pointer to bd array */
1001 + dma_addr_t gpd_addr; /* the physical address of gpd array */
1002 + dma_addr_t bd_addr; /* the physical address of bd array */
1003 + u32 used_gpd; /* the number of used gpd elements */
1004 + u32 used_bd; /* the number of used bd elements */
1005 +};
1006 +
1007 +struct msdc_host
1008 +{
1009 + struct msdc_hw *hw;
1010 +
1011 + struct mmc_host *mmc; /* mmc structure */
1012 + struct mmc_command *cmd;
1013 + struct mmc_data *data;
1014 + struct mmc_request *mrq;
1015 + int cmd_rsp;
1016 + int cmd_rsp_done;
1017 + int cmd_r1b_done;
1018 +
1019 + int error;
1020 + spinlock_t lock; /* mutex */
1021 + struct semaphore sem;
1022 +
1023 + u32 blksz; /* host block size */
1024 + u32 base; /* host base address */
1025 + int id; /* host id */
1026 + int pwr_ref; /* core power reference count */
1027 +
1028 + u32 xfer_size; /* total transferred size */
1029 +
1030 + struct msdc_dma dma; /* dma channel */
1031 + u32 dma_addr; /* dma transfer address */
1032 + u32 dma_left_size; /* dma transfer left size */
1033 + u32 dma_xfer_size; /* dma transfer size in bytes */
1034 + int dma_xfer; /* dma transfer mode */
1035 +
1036 + u32 timeout_ns; /* data timeout ns */
1037 + u32 timeout_clks; /* data timeout clks */
1038 +
1039 + atomic_t abort; /* abort transfer */
1040 +
1041 + int irq; /* host interrupt */
1042 +
1043 + struct tasklet_struct card_tasklet;
1044 +
1045 + struct completion cmd_done;
1046 + struct completion xfer_done;
1047 + struct pm_message pm_state;
1048 +
1049 + u32 mclk; /* mmc subsystem clock */
1050 + u32 hclk; /* host clock speed */
1051 + u32 sclk; /* SD/MS clock speed */
1052 + u8 core_clkon; /* Host core clock on ? */
1053 + u8 card_clkon; /* Card clock on ? */
1054 + u8 core_power; /* core power */
1055 + u8 power_mode; /* host power mode */
1056 + u8 card_inserted; /* card inserted ? */
1057 + u8 suspend; /* host suspended ? */
1058 + u8 reserved;
1059 + u8 app_cmd; /* for app command */
1060 + u32 app_cmd_arg;
1061 + u64 starttime;
1062 +};
1063 +
1064 +static inline unsigned int uffs(unsigned int x)
1065 +{
1066 + unsigned int r = 1;
1067 +
1068 + if (!x)
1069 + return 0;
1070 + if (!(x & 0xffff)) {
1071 + x >>= 16;
1072 + r += 16;
1073 + }
1074 + if (!(x & 0xff)) {
1075 + x >>= 8;
1076 + r += 8;
1077 + }
1078 + if (!(x & 0xf)) {
1079 + x >>= 4;
1080 + r += 4;
1081 + }
1082 + if (!(x & 3)) {
1083 + x >>= 2;
1084 + r += 2;
1085 + }
1086 + if (!(x & 1)) {
1087 + x >>= 1;
1088 + r += 1;
1089 + }
1090 + return r;
1091 +}
1092 +#define sdr_read8(reg) __raw_readb(reg)
1093 +#define sdr_read16(reg) __raw_readw(reg)
1094 +#define sdr_read32(reg) __raw_readl(reg)
1095 +#define sdr_write8(reg,val) __raw_writeb(val,reg)
1096 +#define sdr_write16(reg,val) __raw_writew(val,reg)
1097 +#define sdr_write32(reg,val) __raw_writel(val,reg)
1098 +
1099 +#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
1100 +#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
1101 +
1102 +#define sdr_set_field(reg,field,val) \
1103 + do { \
1104 + volatile unsigned int tv = sdr_read32(reg); \
1105 + tv &= ~(field); \
1106 + tv |= ((val) << (uffs((unsigned int)field) - 1)); \
1107 + sdr_write32(reg,tv); \
1108 + } while(0)
1109 +#define sdr_get_field(reg,field,val) \
1110 + do { \
1111 + volatile unsigned int tv = sdr_read32(reg); \
1112 + val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
1113 + } while(0)
1114 +
1115 +#endif
1116 +
1117 --- /dev/null
1118 +++ b/drivers/mmc/host/sdhci-mt7620.c
1119 @@ -0,0 +1,2314 @@
1120 +/* Copyright Statement:
1121 + *
1122 + * This software/firmware and related documentation ("MediaTek Software") are
1123 + * protected under relevant copyright laws. The information contained herein
1124 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
1125 + * Without the prior written permission of MediaTek inc. and/or its licensors,
1126 + * any reproduction, modification, use or disclosure of MediaTek Software,
1127 + * and information contained herein, in whole or in part, shall be strictly prohibited.
1128 + *
1129 + * MediaTek Inc. (C) 2010. All rights reserved.
1130 + *
1131 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1132 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1133 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
1134 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1135 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1136 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1137 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1138 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1139 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
1140 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
1141 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
1142 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
1143 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
1144 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
1145 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1146 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1147 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
1148 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1149 + *
1150 + * The following software/firmware and/or related documentation ("MediaTek Software")
1151 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
1152 + * applicable license agreements with MediaTek Inc.
1153 + */
1154 +
1155 +#include <linux/module.h>
1156 +#include <linux/moduleparam.h>
1157 +#include <linux/init.h>
1158 +#include <linux/spinlock.h>
1159 +#include <linux/timer.h>
1160 +#include <linux/ioport.h>
1161 +#include <linux/device.h>
1162 +#include <linux/platform_device.h>
1163 +#include <linux/of_platform.h>
1164 +#include <linux/interrupt.h>
1165 +#include <linux/delay.h>
1166 +#include <linux/blkdev.h>
1167 +#include <linux/slab.h>
1168 +#include <linux/mmc/host.h>
1169 +#include <linux/mmc/card.h>
1170 +#include <linux/mmc/core.h>
1171 +#include <linux/mmc/mmc.h>
1172 +#include <linux/mmc/sd.h>
1173 +#include <linux/mmc/sdio.h>
1174 +#include <linux/dma-mapping.h>
1175 +
1176 +#include <linux/types.h>
1177 +#include <linux/kernel.h>
1178 +#include <linux/version.h>
1179 +#include <linux/pm.h>
1180 +
1181 +#define MSDC_SMPL_FALLING (1)
1182 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
1183 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
1184 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
1185 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
1186 +#define MSDC_HIGHSPEED (1 << 7)
1187 +
1188 +#define IRQ_SDC 22
1189 +
1190 +#include <asm/dma.h>
1191 +
1192 +#include "mt6575_sd.h"
1193 +
1194 +#define DRV_NAME "mtk-sd"
1195 +
1196 +#define HOST_MAX_NUM (1) /* +/- by chhung */
1197 +
1198 +#define HOST_MAX_MCLK (48000000) /* +/- by chhung */
1199 +#define HOST_MIN_MCLK (260000)
1200 +
1201 +#define HOST_MAX_BLKSZ (2048)
1202 +
1203 +#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
1204 +
1205 +#define GPIO_PULL_DOWN (0)
1206 +#define GPIO_PULL_UP (1)
1207 +
1208 +#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
1209 +#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
1210 +
1211 +#define CMD_TIMEOUT (HZ/10) /* 100ms */
1212 +#define DAT_TIMEOUT (HZ/2 * 5) /* 500ms x5 */
1213 +
1214 +#define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
1215 +
1216 +#define MAX_GPD_NUM (1 + 1) /* one null gpd */
1217 +#define MAX_BD_NUM (1024)
1218 +#define MAX_BD_PER_GPD (MAX_BD_NUM)
1219 +
1220 +#define MAX_HW_SGMTS (MAX_BD_NUM)
1221 +#define MAX_PHY_SGMTS (MAX_BD_NUM)
1222 +#define MAX_SGMT_SZ (MAX_DMA_CNT)
1223 +#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
1224 +
1225 +#ifdef MT6575_SD_DEBUG
1226 +static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
1227 +#endif
1228 +
1229 +//=================================
1230 +#define PERI_MSDC0_PDN (15)
1231 +//#define PERI_MSDC1_PDN (16)
1232 +//#define PERI_MSDC2_PDN (17)
1233 +//#define PERI_MSDC3_PDN (18)
1234 +
1235 +struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
1236 +
1237 +struct msdc_hw msdc0_hw = {
1238 + .clk_src = 0,
1239 + .cmd_edge = MSDC_SMPL_FALLING,
1240 + .data_edge = MSDC_SMPL_FALLING,
1241 + .clk_drv = 4,
1242 + .cmd_drv = 4,
1243 + .dat_drv = 4,
1244 + .data_pins = 4,
1245 + .data_offset = 0,
1246 + .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
1247 +};
1248 +
1249 +static struct resource mtk_sd_resources[] = {
1250 + [0] = {
1251 + .start = 0xb0130000,
1252 + .end = 0xb0133fff,
1253 + .flags = IORESOURCE_MEM,
1254 + },
1255 + [1] = {
1256 + .start = IRQ_SDC, /*FIXME*/
1257 + .end = IRQ_SDC, /*FIXME*/
1258 + .flags = IORESOURCE_IRQ,
1259 + },
1260 +};
1261 +
1262 +static struct platform_device mtk_sd_device = {
1263 + .name = "mtk-sd",
1264 + .id = 0,
1265 + .num_resources = ARRAY_SIZE(mtk_sd_resources),
1266 + .resource = mtk_sd_resources,
1267 +};
1268 +/* end of +++ */
1269 +
1270 +static int msdc_rsp[] = {
1271 + 0, /* RESP_NONE */
1272 + 1, /* RESP_R1 */
1273 + 2, /* RESP_R2 */
1274 + 3, /* RESP_R3 */
1275 + 4, /* RESP_R4 */
1276 + 1, /* RESP_R5 */
1277 + 1, /* RESP_R6 */
1278 + 1, /* RESP_R7 */
1279 + 7, /* RESP_R1b */
1280 +};
1281 +
1282 +/* For Inhanced DMA */
1283 +#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
1284 + do { \
1285 + ((gpd_t*)gpd)->extlen = extlen; \
1286 + ((gpd_t*)gpd)->cmd = cmd; \
1287 + ((gpd_t*)gpd)->arg = arg; \
1288 + ((gpd_t*)gpd)->blknum = blknum; \
1289 + }while(0)
1290 +
1291 +#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
1292 + do { \
1293 + BUG_ON(dlen > 0xFFFFUL); \
1294 + ((bd_t*)bd)->blkpad = blkpad; \
1295 + ((bd_t*)bd)->dwpad = dwpad; \
1296 + ((bd_t*)bd)->ptr = (void*)dptr; \
1297 + ((bd_t*)bd)->buflen = dlen; \
1298 + }while(0)
1299 +
1300 +#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
1301 +#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
1302 +#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
1303 +#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
1304 +#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
1305 +#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
1306 +
1307 +
1308 +#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
1309 +#define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
1310 +
1311 +#define msdc_retry(expr,retry,cnt) \
1312 + do { \
1313 + int backup = cnt; \
1314 + while (retry) { \
1315 + if (!(expr)) break; \
1316 + if (cnt-- == 0) { \
1317 + retry--; mdelay(1); cnt = backup; \
1318 + } \
1319 + } \
1320 + WARN_ON(retry == 0); \
1321 + } while(0)
1322 +
1323 +#if 0 /* +/- chhung */
1324 +#define msdc_reset() \
1325 + do { \
1326 + int retry = 3, cnt = 1000; \
1327 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
1328 + dsb(); \
1329 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
1330 + } while(0)
1331 +#else
1332 +#define msdc_reset() \
1333 + do { \
1334 + int retry = 3, cnt = 1000; \
1335 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
1336 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
1337 + } while(0)
1338 +#endif /* end of +/- */
1339 +
1340 +#define msdc_clr_int() \
1341 + do { \
1342 + volatile u32 val = sdr_read32(MSDC_INT); \
1343 + sdr_write32(MSDC_INT, val); \
1344 + } while(0)
1345 +
1346 +#define msdc_clr_fifo() \
1347 + do { \
1348 + int retry = 3, cnt = 1000; \
1349 + sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
1350 + msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
1351 + } while(0)
1352 +
1353 +#define msdc_irq_save(val) \
1354 + do { \
1355 + val = sdr_read32(MSDC_INTEN); \
1356 + sdr_clr_bits(MSDC_INTEN, val); \
1357 + } while(0)
1358 +
1359 +#define msdc_irq_restore(val) \
1360 + do { \
1361 + sdr_set_bits(MSDC_INTEN, val); \
1362 + } while(0)
1363 +
1364 +/* clock source for host: global */
1365 +static u32 hclks[] = {48000000}; /* +/- by chhung */
1366 +
1367 +//============================================
1368 +// the power for msdc host controller: global
1369 +// always keep the VMC on.
1370 +//============================================
1371 +#define msdc_vcore_on(host) \
1372 + do { \
1373 + printk("[+]VMC ref. count<%d>\n", ++host->pwr_ref); \
1374 + (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
1375 + } while (0)
1376 +#define msdc_vcore_off(host) \
1377 + do { \
1378 + printk("[-]VMC ref. count<%d>\n", --host->pwr_ref); \
1379 + (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
1380 + } while (0)
1381 +
1382 +//====================================
1383 +// the vdd output for card: global
1384 +// always keep the VMCH on.
1385 +//====================================
1386 +#define msdc_vdd_on(host) \
1387 + do { \
1388 + (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
1389 + } while (0)
1390 +#define msdc_vdd_off(host) \
1391 + do { \
1392 + (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
1393 + } while (0)
1394 +
1395 +#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
1396 +#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
1397 +
1398 +#define sdc_send_cmd(cmd,arg) \
1399 + do { \
1400 + sdr_write32(SDC_ARG, (arg)); \
1401 + sdr_write32(SDC_CMD, (cmd)); \
1402 + } while(0)
1403 +
1404 +// can modify to read h/w register.
1405 +//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
1406 +#define is_card_present(h) (((struct msdc_host*)(h))->card_inserted)
1407 +
1408 +/* +++ chhung */
1409 +#ifndef __ASSEMBLY__
1410 +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
1411 +#else
1412 +#define PHYSADDR(a) ((a) & 0x1fffffff)
1413 +#endif
1414 +/* end of +++ */
1415 +static unsigned int msdc_do_command(struct msdc_host *host,
1416 + struct mmc_command *cmd,
1417 + int tune,
1418 + unsigned long timeout);
1419 +
1420 +static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
1421 +
1422 +#ifdef MT6575_SD_DEBUG
1423 +static void msdc_dump_card_status(struct msdc_host *host, u32 status)
1424 +{
1425 + static char *state[] = {
1426 + "Idle", /* 0 */
1427 + "Ready", /* 1 */
1428 + "Ident", /* 2 */
1429 + "Stby", /* 3 */
1430 + "Tran", /* 4 */
1431 + "Data", /* 5 */
1432 + "Rcv", /* 6 */
1433 + "Prg", /* 7 */
1434 + "Dis", /* 8 */
1435 + "Reserved", /* 9 */
1436 + "Reserved", /* 10 */
1437 + "Reserved", /* 11 */
1438 + "Reserved", /* 12 */
1439 + "Reserved", /* 13 */
1440 + "Reserved", /* 14 */
1441 + "I/O mode", /* 15 */
1442 + };
1443 + if (status & R1_OUT_OF_RANGE)
1444 + printk("[CARD_STATUS] Out of Range\n");
1445 + if (status & R1_ADDRESS_ERROR)
1446 + printk("[CARD_STATUS] Address Error\n");
1447 + if (status & R1_BLOCK_LEN_ERROR)
1448 + printk("[CARD_STATUS] Block Len Error\n");
1449 + if (status & R1_ERASE_SEQ_ERROR)
1450 + printk("[CARD_STATUS] Erase Seq Error\n");
1451 + if (status & R1_ERASE_PARAM)
1452 + printk("[CARD_STATUS] Erase Param\n");
1453 + if (status & R1_WP_VIOLATION)
1454 + printk("[CARD_STATUS] WP Violation\n");
1455 + if (status & R1_CARD_IS_LOCKED)
1456 + printk("[CARD_STATUS] Card is Locked\n");
1457 + if (status & R1_LOCK_UNLOCK_FAILED)
1458 + printk("[CARD_STATUS] Lock/Unlock Failed\n");
1459 + if (status & R1_COM_CRC_ERROR)
1460 + printk("[CARD_STATUS] Command CRC Error\n");
1461 + if (status & R1_ILLEGAL_COMMAND)
1462 + printk("[CARD_STATUS] Illegal Command\n");
1463 + if (status & R1_CARD_ECC_FAILED)
1464 + printk("[CARD_STATUS] Card ECC Failed\n");
1465 + if (status & R1_CC_ERROR)
1466 + printk("[CARD_STATUS] CC Error\n");
1467 + if (status & R1_ERROR)
1468 + printk("[CARD_STATUS] Error\n");
1469 + if (status & R1_UNDERRUN)
1470 + printk("[CARD_STATUS] Underrun\n");
1471 + if (status & R1_OVERRUN)
1472 + printk("[CARD_STATUS] Overrun\n");
1473 + if (status & R1_CID_CSD_OVERWRITE)
1474 + printk("[CARD_STATUS] CID/CSD Overwrite\n");
1475 + if (status & R1_WP_ERASE_SKIP)
1476 + printk("[CARD_STATUS] WP Eraser Skip\n");
1477 + if (status & R1_CARD_ECC_DISABLED)
1478 + printk("[CARD_STATUS] Card ECC Disabled\n");
1479 + if (status & R1_ERASE_RESET)
1480 + printk("[CARD_STATUS] Erase Reset\n");
1481 + if (status & R1_READY_FOR_DATA)
1482 + printk("[CARD_STATUS] Ready for Data\n");
1483 + if (status & R1_SWITCH_ERROR)
1484 + printk("[CARD_STATUS] Switch error\n");
1485 + if (status & R1_APP_CMD)
1486 + printk("[CARD_STATUS] App Command\n");
1487 +
1488 + printk("[CARD_STATUS] '%s' State\n", state[R1_CURRENT_STATE(status)]);
1489 +}
1490 +
1491 +static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
1492 +{
1493 + if (resp & (1 << 7))
1494 + printk("[OCR] Low Voltage Range\n");
1495 + if (resp & (1 << 15))
1496 + printk("[OCR] 2.7-2.8 volt\n");
1497 + if (resp & (1 << 16))
1498 + printk("[OCR] 2.8-2.9 volt\n");
1499 + if (resp & (1 << 17))
1500 + printk("[OCR] 2.9-3.0 volt\n");
1501 + if (resp & (1 << 18))
1502 + printk("[OCR] 3.0-3.1 volt\n");
1503 + if (resp & (1 << 19))
1504 + printk("[OCR] 3.1-3.2 volt\n");
1505 + if (resp & (1 << 20))
1506 + printk("[OCR] 3.2-3.3 volt\n");
1507 + if (resp & (1 << 21))
1508 + printk("[OCR] 3.3-3.4 volt\n");
1509 + if (resp & (1 << 22))
1510 + printk("[OCR] 3.4-3.5 volt\n");
1511 + if (resp & (1 << 23))
1512 + printk("[OCR] 3.5-3.6 volt\n");
1513 + if (resp & (1 << 24))
1514 + printk("[OCR] Switching to 1.8V Accepted (S18A)\n");
1515 + if (resp & (1 << 30))
1516 + printk("[OCR] Card Capacity Status (CCS)\n");
1517 + if (resp & (1 << 31))
1518 + printk("[OCR] Card Power Up Status (Idle)\n");
1519 + else
1520 + printk("[OCR] Card Power Up Status (Busy)\n");
1521 +}
1522 +
1523 +static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
1524 +{
1525 + u32 status = (((resp >> 15) & 0x1) << 23) |
1526 + (((resp >> 14) & 0x1) << 22) |
1527 + (((resp >> 13) & 0x1) << 19) |
1528 + (resp & 0x1fff);
1529 +
1530 + printk("[RCA] 0x%.4x\n", resp >> 16);
1531 +
1532 + msdc_dump_card_status(host, status);
1533 +}
1534 +
1535 +static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
1536 +{
1537 + u32 flags = (resp >> 8) & 0xFF;
1538 + char *state[] = {"DIS", "CMD", "TRN", "RFU"};
1539 +
1540 + if (flags & (1 << 7))
1541 + printk("[IO] COM_CRC_ERR\n");
1542 + if (flags & (1 << 6))
1543 + printk("[IO] Illgal command\n");
1544 + if (flags & (1 << 3))
1545 + printk("[IO] Error\n");
1546 + if (flags & (1 << 2))
1547 + printk("[IO] RFU\n");
1548 + if (flags & (1 << 1))
1549 + printk("[IO] Function number error\n");
1550 + if (flags & (1 << 0))
1551 + printk("[IO] Out of range\n");
1552 +
1553 + printk("[IO] State: %s, Data:0x%x\n", state[(resp >> 12) & 0x3], resp & 0xFF);
1554 +}
1555 +#endif
1556 +
1557 +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
1558 +{
1559 + u32 base = host->base;
1560 + u32 timeout, clk_ns;
1561 +
1562 + host->timeout_ns = ns;
1563 + host->timeout_clks = clks;
1564 +
1565 + clk_ns = 1000000000UL / host->sclk;
1566 + timeout = ns / clk_ns + clks;
1567 + timeout = timeout >> 16; /* in 65536 sclk cycle unit */
1568 + timeout = timeout > 1 ? timeout - 1 : 0;
1569 + timeout = timeout > 255 ? 255 : timeout;
1570 +
1571 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
1572 +
1573 +/* printk("Set read data timeout: %dns %dclks -> %d x 65536 cycles\n",
1574 + ns, clks, timeout + 1);*/
1575 +}
1576 +
1577 +static void msdc_eirq_sdio(void *data)
1578 +{
1579 + struct msdc_host *host = (struct msdc_host *)data;
1580 +
1581 +// printk("SDIO EINT\n");
1582 +
1583 + mmc_signal_sdio_irq(host->mmc);
1584 +}
1585 +
1586 +static void msdc_eirq_cd(void *data)
1587 +{
1588 + struct msdc_host *host = (struct msdc_host *)data;
1589 +
1590 +// printk("CD EINT\n");
1591 +
1592 + tasklet_hi_schedule(&host->card_tasklet);
1593 +}
1594 +
1595 +static void msdc_tasklet_card(unsigned long arg)
1596 +{
1597 + struct msdc_host *host = (struct msdc_host *)arg;
1598 + struct msdc_hw *hw = host->hw;
1599 + u32 base = host->base;
1600 + u32 inserted;
1601 + u32 status = 0;
1602 +
1603 + spin_lock(&host->lock);
1604 +
1605 + if (hw->get_cd_status) {
1606 + inserted = hw->get_cd_status();
1607 + } else {
1608 + status = sdr_read32(MSDC_PS);
1609 + inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
1610 + }
1611 +
1612 + host->card_inserted = inserted;
1613 +
1614 + if (!host->suspend) {
1615 + host->mmc->f_max = HOST_MAX_MCLK;
1616 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
1617 + }
1618 +
1619 +// printk("card found<%s>\n", inserted ? "inserted" : "removed");
1620 +
1621 + spin_unlock(&host->lock);
1622 +}
1623 +
1624 +static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
1625 +{
1626 + u32 base = host->base;
1627 + u32 hclk = host->hclk;
1628 + u32 mode, flags, div, sclk;
1629 +
1630 + if (!hz) {
1631 +// printk("set mclk to 0!!!\n");
1632 + msdc_reset();
1633 + return;
1634 + }
1635 +
1636 + msdc_irq_save(flags);
1637 +
1638 + if (ddr) {
1639 + mode = 0x2;
1640 + if (hz >= (hclk >> 2)) {
1641 + div = 1;
1642 + sclk = hclk >> 2;
1643 + } else {
1644 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
1645 + sclk = (hclk >> 2) / div;
1646 + }
1647 + } else if (hz >= hclk) {
1648 + mode = 0x1;
1649 + div = 0;
1650 + sclk = hclk;
1651 + } else {
1652 + mode = 0x0;
1653 + if (hz >= (hclk >> 1)) {
1654 + div = 0;
1655 + sclk = hclk >> 1;
1656 + } else {
1657 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
1658 + sclk = (hclk >> 2) / div;
1659 + }
1660 + }
1661 +
1662 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
1663 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
1664 +
1665 + while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
1666 +
1667 + host->sclk = sclk;
1668 + host->mclk = hz;
1669 + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
1670 +
1671 +/* printk("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>\n",
1672 + hz / 1000, hclk / 1000, sclk / 1000);
1673 +*/
1674 + msdc_irq_restore(flags);
1675 +}
1676 +
1677 +static void msdc_abort_data(struct msdc_host *host)
1678 +{
1679 + u32 base = host->base;
1680 + struct mmc_command *stop = host->mrq->stop;
1681 +
1682 +// printk("Need to Abort. dma<%d>\n", host->dma_xfer);
1683 +
1684 + msdc_reset();
1685 + msdc_clr_fifo();
1686 + msdc_clr_int();
1687 +
1688 + if (stop) {
1689 +// printk("stop when abort CMD<%d>\n", stop->opcode);
1690 + msdc_do_command(host, stop, 0, CMD_TIMEOUT);
1691 + }
1692 +}
1693 +
1694 +static unsigned int msdc_command_start(struct msdc_host *host,
1695 + struct mmc_command *cmd, int tune, unsigned long timeout)
1696 +{
1697 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
1698 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
1699 + MSDC_INT_ACMD19_DONE;
1700 + u32 base = host->base;
1701 + u32 opcode = cmd->opcode;
1702 + u32 rawcmd;
1703 + u32 resp;
1704 + unsigned long tmo;
1705 +
1706 + if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
1707 + resp = RESP_R3;
1708 + else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
1709 + resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
1710 + else if (opcode == MMC_FAST_IO)
1711 + resp = RESP_R4;
1712 + else if (opcode == MMC_GO_IRQ_STATE)
1713 + resp = RESP_R5;
1714 + else if (opcode == MMC_SELECT_CARD)
1715 + resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
1716 + else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
1717 + resp = RESP_R1;
1718 + else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
1719 + resp = RESP_R1;
1720 + else {
1721 + switch (mmc_resp_type(cmd)) {
1722 + case MMC_RSP_R1:
1723 + resp = RESP_R1;
1724 + break;
1725 + case MMC_RSP_R1B:
1726 + resp = RESP_R1B;
1727 + break;
1728 + case MMC_RSP_R2:
1729 + resp = RESP_R2;
1730 + break;
1731 + case MMC_RSP_R3:
1732 + resp = RESP_R3;
1733 + break;
1734 + case MMC_RSP_NONE:
1735 + default:
1736 + resp = RESP_NONE;
1737 + break;
1738 + }
1739 + }
1740 +
1741 + cmd->error = 0;
1742 + rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
1743 +
1744 + if (opcode == MMC_READ_MULTIPLE_BLOCK) {
1745 + rawcmd |= (2 << 11);
1746 + } else if (opcode == MMC_READ_SINGLE_BLOCK) {
1747 + rawcmd |= (1 << 11);
1748 + } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
1749 + rawcmd |= ((2 << 11) | (1 << 13));
1750 + } else if (opcode == MMC_WRITE_BLOCK) {
1751 + rawcmd |= ((1 << 11) | (1 << 13));
1752 + } else if (opcode == SD_IO_RW_EXTENDED) {
1753 + if (cmd->data->flags & MMC_DATA_WRITE)
1754 + rawcmd |= (1 << 13);
1755 + if (cmd->data->blocks > 1)
1756 + rawcmd |= (2 << 11);
1757 + else
1758 + rawcmd |= (1 << 11);
1759 + } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
1760 + rawcmd |= (1 << 14);
1761 + } else if ((opcode == SD_APP_SEND_SCR) ||
1762 + (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
1763 + (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
1764 + (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
1765 + (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
1766 + rawcmd |= (1 << 11);
1767 + } else if (opcode == MMC_STOP_TRANSMISSION) {
1768 + rawcmd |= (1 << 14);
1769 + rawcmd &= ~(0x0FFF << 16);
1770 + }
1771 +
1772 +// printk("CMD<%d><0x%.8x> Arg<0x%.8x>\n", opcode , rawcmd, cmd->arg);
1773 +
1774 + tmo = jiffies + timeout;
1775 +
1776 + if (opcode == MMC_SEND_STATUS) {
1777 + for (;;) {
1778 + if (!sdc_is_cmd_busy())
1779 + break;
1780 +
1781 + if (time_after(jiffies, tmo)) {
1782 + //printk("XXX cmd_busy timeout: before CMD<%d>\n", opcode);
1783 + cmd->error = (unsigned int)-ETIMEDOUT;
1784 + msdc_reset();
1785 + goto end;
1786 + }
1787 + }
1788 + } else {
1789 + for (;;) {
1790 + if (!sdc_is_busy())
1791 + break;
1792 + if (time_after(jiffies, tmo)) {
1793 + //printk("XXX sdc_busy timeout: before CMD<%d>\n", opcode);
1794 + cmd->error = (unsigned int)-ETIMEDOUT;
1795 + msdc_reset();
1796 + goto end;
1797 + }
1798 + }
1799 + }
1800 +
1801 + //BUG_ON(in_interrupt());
1802 + host->cmd = cmd;
1803 + host->cmd_rsp = resp;
1804 + init_completion(&host->cmd_done);
1805 + sdr_set_bits(MSDC_INTEN, wints);
1806 + sdc_send_cmd(rawcmd, cmd->arg);
1807 +
1808 +end:
1809 + return cmd->error;
1810 +}
1811 +
1812 +static unsigned int msdc_command_resp(struct msdc_host *host, struct mmc_command *cmd,
1813 + int tune, unsigned long timeout)
1814 +{
1815 + u32 base = host->base;
1816 + //u32 opcode = cmd->opcode;
1817 + u32 resp;
1818 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
1819 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
1820 + MSDC_INT_ACMD19_DONE;
1821 +
1822 + resp = host->cmd_rsp;
1823 +
1824 + BUG_ON(in_interrupt());
1825 + spin_unlock(&host->lock);
1826 + if (!wait_for_completion_timeout(&host->cmd_done, 10*timeout)) {
1827 + //printk("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>\n", opcode, cmd->arg);
1828 + cmd->error = (unsigned int)-ETIMEDOUT;
1829 + msdc_reset();
1830 + }
1831 + spin_lock(&host->lock);
1832 +
1833 + sdr_clr_bits(MSDC_INTEN, wints);
1834 + host->cmd = NULL;
1835 +
1836 + if (!tune)
1837 + return cmd->error;
1838 +
1839 + /* memory card CRC */
1840 + if (host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
1841 + if (sdr_read32(SDC_CMD) & 0x1800) {
1842 + msdc_abort_data(host);
1843 + } else {
1844 + msdc_reset();
1845 + msdc_clr_fifo();
1846 + msdc_clr_int();
1847 + }
1848 + cmd->error = msdc_tune_cmdrsp(host,cmd);
1849 + }
1850 +
1851 + return cmd->error;
1852 +}
1853 +
1854 +static unsigned int msdc_do_command(struct msdc_host *host, struct mmc_command *cmd,
1855 + int tune, unsigned long timeout)
1856 +{
1857 + if (!msdc_command_start(host, cmd, tune, timeout))
1858 + msdc_command_resp(host, cmd, tune, timeout);
1859 +
1860 + //printk(" return<%d> resp<0x%.8x>\n", cmd->error, cmd->resp[0]);
1861 + return cmd->error;
1862 +}
1863 +
1864 +static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
1865 +{
1866 + u32 base = host->base;
1867 + int ret = 0;
1868 +
1869 + if (atomic_read(&host->abort))
1870 + ret = 1;
1871 +
1872 + if (time_after(jiffies, tmo)) {
1873 + data->error = (unsigned int)-ETIMEDOUT;
1874 + //printk("XXX PIO Data Timeout: CMD<%d>\n", host->mrq->cmd->opcode);
1875 + ret = 1;
1876 + }
1877 +
1878 + if (ret) {
1879 + msdc_reset();
1880 + msdc_clr_fifo();
1881 + msdc_clr_int();
1882 + //printk("msdc pio find abort\n");
1883 + }
1884 +
1885 + return ret;
1886 +}
1887 +
1888 +static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
1889 +{
1890 + struct scatterlist *sg = data->sg;
1891 + u32 base = host->base;
1892 + u32 num = data->sg_len;
1893 + u32 *ptr;
1894 + u8 *u8ptr;
1895 + u32 left;
1896 + u32 count, size = 0;
1897 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1898 + unsigned long tmo = jiffies + DAT_TIMEOUT;
1899 +
1900 + sdr_set_bits(MSDC_INTEN, wints);
1901 + while (num) {
1902 + left = sg_dma_len(sg);
1903 + ptr = sg_virt(sg);
1904 + while (left) {
1905 + if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
1906 + count = MSDC_FIFO_THD >> 2;
1907 + do {
1908 + *ptr++ = msdc_fifo_read32();
1909 + } while (--count);
1910 + left -= MSDC_FIFO_THD;
1911 + } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
1912 + while (left > 3) {
1913 + *ptr++ = msdc_fifo_read32();
1914 + left -= 4;
1915 + }
1916 +
1917 + u8ptr = (u8 *)ptr;
1918 + while(left) {
1919 + * u8ptr++ = msdc_fifo_read8();
1920 + left--;
1921 + }
1922 + }
1923 +
1924 + if (msdc_pio_abort(host, data, tmo))
1925 + goto end;
1926 + }
1927 + size += sg_dma_len(sg);
1928 + sg = sg_next(sg); num--;
1929 + }
1930 +end:
1931 + data->bytes_xfered += size;
1932 + //printk(" PIO Read<%d>bytes\n", size);
1933 +
1934 + sdr_clr_bits(MSDC_INTEN, wints);
1935 + if(data->error)
1936 + printk("read pio data->error<%d> left<%d> size<%d>\n", data->error, left, size);
1937 +
1938 + return data->error;
1939 +}
1940 +
1941 +static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
1942 +{
1943 + u32 base = host->base;
1944 + struct scatterlist *sg = data->sg;
1945 + u32 num = data->sg_len;
1946 + u32 *ptr;
1947 + u8 *u8ptr;
1948 + u32 left;
1949 + u32 count, size = 0;
1950 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1951 + unsigned long tmo = jiffies + DAT_TIMEOUT;
1952 +
1953 + sdr_set_bits(MSDC_INTEN, wints);
1954 + while (num) {
1955 + left = sg_dma_len(sg);
1956 + ptr = sg_virt(sg);
1957 +
1958 + while (left) {
1959 + if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
1960 + count = MSDC_FIFO_SZ >> 2;
1961 + do {
1962 + msdc_fifo_write32(*ptr); ptr++;
1963 + } while (--count);
1964 + left -= MSDC_FIFO_SZ;
1965 + } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
1966 + while (left > 3) {
1967 + msdc_fifo_write32(*ptr); ptr++;
1968 + left -= 4;
1969 + }
1970 +
1971 + u8ptr = (u8*)ptr;
1972 + while( left) {
1973 + msdc_fifo_write8(*u8ptr);
1974 + u8ptr++;
1975 + left--;
1976 + }
1977 + }
1978 +
1979 + if (msdc_pio_abort(host, data, tmo))
1980 + goto end;
1981 + }
1982 + size += sg_dma_len(sg);
1983 + sg = sg_next(sg); num--;
1984 + }
1985 +end:
1986 + data->bytes_xfered += size;
1987 + //printk(" PIO Write<%d>bytes\n", size);
1988 + if(data->error)
1989 + printk("write pio data->error<%d>\n", data->error);
1990 +
1991 + sdr_clr_bits(MSDC_INTEN, wints);
1992 +
1993 + return data->error;
1994 +}
1995 +
1996 +static void msdc_dma_start(struct msdc_host *host)
1997 +{
1998 + u32 base = host->base;
1999 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
2000 +
2001 + sdr_set_bits(MSDC_INTEN, wints);
2002 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
2003 +
2004 + //printk("DMA start\n");
2005 +}
2006 +
2007 +static void msdc_dma_stop(struct msdc_host *host)
2008 +{
2009 + u32 base = host->base;
2010 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
2011 +
2012 + //printk("DMA status: 0x%.8x\n",sdr_read32(MSDC_DMA_CFG));
2013 +
2014 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
2015 + while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
2016 + sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
2017 +
2018 + //printk("DMA stop\n");
2019 +}
2020 +
2021 +static u8 msdc_dma_calcs(u8 *buf, u32 len)
2022 +{
2023 + u32 i, sum = 0;
2024 +
2025 + for (i = 0; i < len; i++)
2026 + sum += buf[i];
2027 +
2028 + return 0xFF - (u8)sum;
2029 +}
2030 +
2031 +static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
2032 +{
2033 + u32 base = host->base;
2034 + u32 sglen = dma->sglen;
2035 + u32 j, num, bdlen;
2036 + u8 blkpad, dwpad, chksum;
2037 + struct scatterlist *sg = dma->sg;
2038 + gpd_t *gpd;
2039 + bd_t *bd;
2040 +
2041 + switch (dma->mode) {
2042 + case MSDC_MODE_DMA_BASIC:
2043 + BUG_ON(dma->xfersz > 65535);
2044 + BUG_ON(dma->sglen != 1);
2045 + sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
2046 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
2047 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
2048 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
2049 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
2050 + break;
2051 +
2052 + case MSDC_MODE_DMA_DESC:
2053 + blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
2054 + dwpad = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
2055 + chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
2056 +
2057 + num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
2058 + BUG_ON(num !=1 );
2059 +
2060 + gpd = dma->gpd;
2061 + bd = dma->bd;
2062 + bdlen = sglen;
2063 +
2064 + gpd->hwo = 1; /* hw will clear it */
2065 + gpd->bdp = 1;
2066 + gpd->chksum = 0; /* need to clear first. */
2067 + gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
2068 +
2069 + for (j = 0; j < bdlen; j++) {
2070 + msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
2071 + if( j == bdlen - 1)
2072 + bd[j].eol = 1;
2073 + else
2074 + bd[j].eol = 0;
2075 + bd[j].chksum = 0; /* checksume need to clear first */
2076 + bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
2077 + sg++;
2078 + }
2079 +
2080 + dma->used_gpd += 2;
2081 + dma->used_bd += bdlen;
2082 +
2083 + sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
2084 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
2085 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
2086 + sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
2087 + break;
2088 + }
2089 +
2090 +// printk("DMA_CTRL = 0x%x\n", sdr_read32(MSDC_DMA_CTRL));
2091 +// printk("DMA_CFG = 0x%x\n", sdr_read32(MSDC_DMA_CFG));
2092 +// printk("DMA_SA = 0x%x\n", sdr_read32(MSDC_DMA_SA));
2093 +
2094 + return 0;
2095 +}
2096 +
2097 +static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
2098 + struct scatterlist *sg, unsigned int sglen)
2099 +{
2100 + BUG_ON(sglen > MAX_BD_NUM);
2101 +
2102 + dma->sg = sg;
2103 + dma->flags = DMA_FLAG_EN_CHKSUM;
2104 + dma->sglen = sglen;
2105 + dma->xfersz = host->xfer_size;
2106 + dma->burstsz = MSDC_BRUST_64B;
2107 +
2108 + if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
2109 + dma->mode = MSDC_MODE_DMA_BASIC;
2110 + else
2111 + dma->mode = MSDC_MODE_DMA_DESC;
2112 +
2113 +// printk("DMA mode<%d> sglen<%d> xfersz<%d>\n", dma->mode, dma->sglen, dma->xfersz);
2114 +
2115 + msdc_dma_config(host, dma);
2116 +}
2117 +
2118 +static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
2119 +{
2120 + u32 base = host->base;
2121 +
2122 + sdr_write32(SDC_BLK_NUM, blknum);
2123 +}
2124 +
2125 +static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
2126 +{
2127 + struct msdc_host *host = mmc_priv(mmc);
2128 + struct mmc_command *cmd;
2129 + struct mmc_data *data;
2130 + u32 base = host->base;
2131 + unsigned int left=0;
2132 + int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
2133 +
2134 +#define SND_DAT 0
2135 +#define SND_CMD 1
2136 +
2137 + BUG_ON(mmc == NULL);
2138 + BUG_ON(mrq == NULL);
2139 +
2140 + host->error = 0;
2141 + atomic_set(&host->abort, 0);
2142 +
2143 + cmd = mrq->cmd;
2144 + data = mrq->cmd->data;
2145 +
2146 + if (!data) {
2147 + send_type = SND_CMD;
2148 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
2149 + goto done;
2150 + } else {
2151 + BUG_ON(data->blksz > HOST_MAX_BLKSZ);
2152 + send_type=SND_DAT;
2153 +
2154 + data->error = 0;
2155 + read = data->flags & MMC_DATA_READ ? 1 : 0;
2156 + host->data = data;
2157 + host->xfer_size = data->blocks * data->blksz;
2158 + host->blksz = data->blksz;
2159 +
2160 + host->dma_xfer = dma = ((host->xfer_size >= 512) ? 1 : 0);
2161 +
2162 + if (read)
2163 + if ((host->timeout_ns != data->timeout_ns) ||
2164 + (host->timeout_clks != data->timeout_clks))
2165 + msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
2166 +
2167 + msdc_set_blknum(host, data->blocks);
2168 +
2169 + if (dma) {
2170 + msdc_dma_on();
2171 + init_completion(&host->xfer_done);
2172 +
2173 + if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
2174 + goto done;
2175 +
2176 + dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2177 + dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
2178 + msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
2179 +
2180 + if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
2181 + goto done;
2182 +
2183 + msdc_dma_start(host);
2184 +
2185 + spin_unlock(&host->lock);
2186 + if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) {
2187 + /*printk("XXX CMD<%d> wait xfer_done<%d> timeout!!\n", cmd->opcode, data->blocks * data->blksz);
2188 + printk(" DMA_SA = 0x%x\n", sdr_read32(MSDC_DMA_SA));
2189 + printk(" DMA_CA = 0x%x\n", sdr_read32(MSDC_DMA_CA));
2190 + printk(" DMA_CTRL = 0x%x\n", sdr_read32(MSDC_DMA_CTRL));
2191 + printk(" DMA_CFG = 0x%x\n", sdr_read32(MSDC_DMA_CFG));*/
2192 + data->error = (unsigned int)-ETIMEDOUT;
2193 +
2194 + msdc_reset();
2195 + msdc_clr_fifo();
2196 + msdc_clr_int();
2197 + }
2198 + spin_lock(&host->lock);
2199 + msdc_dma_stop(host);
2200 + } else {
2201 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
2202 + goto done;
2203 +
2204 + if (read) {
2205 + if (msdc_pio_read(host, data))
2206 + goto done;
2207 + } else {
2208 + if (msdc_pio_write(host, data))
2209 + goto done;
2210 + }
2211 +
2212 + if (!read) {
2213 + while (1) {
2214 + left = msdc_txfifocnt();
2215 + if (left == 0) {
2216 + break;
2217 + }
2218 + if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
2219 + break;
2220 + /* Fix me: what about if data error, when stop ? how to? */
2221 + }
2222 + }
2223 + } else {
2224 + /* Fix me: read case: need to check CRC error */
2225 + }
2226 +
2227 + /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
2228 + For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
2229 + */
2230 +
2231 + /* try not to wait xfer_comp interrupt.
2232 + the next command will check SDC_BUSY.
2233 + SDC_BUSY means xfer_comp assert
2234 + */
2235 +
2236 + } // PIO mode
2237 +
2238 + /* Last: stop transfer */
2239 + if (data->stop){
2240 + if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
2241 + goto done;
2242 + }
2243 + }
2244 + }
2245 +
2246 +done:
2247 + if (data != NULL) {
2248 + host->data = NULL;
2249 + host->dma_xfer = 0;
2250 + if (dma != 0) {
2251 + msdc_dma_off();
2252 + host->dma.used_bd = 0;
2253 + host->dma.used_gpd = 0;
2254 + dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
2255 + }
2256 + host->blksz = 0;
2257 +
2258 + // printk("CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio\n"),
2259 + // (read ? "read ":"write") ,data->blksz, data->blocks, data->error);
2260 + }
2261 +
2262 + if (mrq->cmd->error) host->error = 0x001;
2263 + if (mrq->data && mrq->data->error) host->error |= 0x010;
2264 + if (mrq->stop && mrq->stop->error) host->error |= 0x100;
2265 +
2266 + //if (host->error) printk("host->error<%d>\n", host->error);
2267 +
2268 + return host->error;
2269 +}
2270 +
2271 +static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
2272 +{
2273 + struct mmc_command cmd;
2274 + struct mmc_request mrq;
2275 + u32 err;
2276 +
2277 + memset(&cmd, 0, sizeof(struct mmc_command));
2278 + cmd.opcode = MMC_APP_CMD;
2279 +#if 0 /* bug: we meet mmc->card is null when ACMD6 */
2280 + cmd.arg = mmc->card->rca << 16;
2281 +#else
2282 + cmd.arg = host->app_cmd_arg;
2283 +#endif
2284 + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
2285 +
2286 + memset(&mrq, 0, sizeof(struct mmc_request));
2287 + mrq.cmd = &cmd; cmd.mrq = &mrq;
2288 + cmd.data = NULL;
2289 +
2290 + err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
2291 + return err;
2292 +}
2293 +
2294 +static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
2295 +{
2296 + int result = -1;
2297 + u32 base = host->base;
2298 + u32 rsmpl, cur_rsmpl, orig_rsmpl;
2299 + u32 rrdly, cur_rrdly = 0, orig_rrdly;
2300 + u32 skip = 1;
2301 +
2302 + /* ==== don't support 3.0 now ====
2303 + 1: R_SMPL[1]
2304 + 2: PAD_CMD_RESP_RXDLY[26:22]
2305 + ==========================*/
2306 +
2307 + // save the previous tune result
2308 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
2309 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
2310 +
2311 + rrdly = 0;
2312 + do {
2313 + for (rsmpl = 0; rsmpl < 2; rsmpl++) {
2314 + /* Lv1: R_SMPL[1] */
2315 + cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
2316 + if (skip == 1) {
2317 + skip = 0;
2318 + continue;
2319 + }
2320 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
2321 +
2322 + if (host->app_cmd) {
2323 + result = msdc_app_cmd(host->mmc, host);
2324 + if (result) {
2325 + //printk("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>\n",
2326 + // host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
2327 + continue;
2328 + }
2329 + }
2330 + result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
2331 + //printk("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>\n", cmd->opcode,
2332 +// (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
2333 +
2334 + if (result == 0) {
2335 + return 0;
2336 + }
2337 + if (result != (unsigned int)(-EIO)) {
2338 + // printk("TUNE_CMD<%d> Error<%d> not -EIO\n", cmd->opcode, result);
2339 + return result;
2340 + }
2341 +
2342 + /* should be EIO */
2343 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
2344 + msdc_abort_data(host);
2345 + }
2346 + }
2347 +
2348 + /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
2349 + cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
2350 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
2351 + }while (++rrdly < 32);
2352 +
2353 + return result;
2354 +}
2355 +
2356 +/* Support SD2.0 Only */
2357 +static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
2358 +{
2359 + struct msdc_host *host = mmc_priv(mmc);
2360 + u32 base = host->base;
2361 + u32 ddr=0;
2362 + u32 dcrc = 0;
2363 + u32 rxdly, cur_rxdly0, cur_rxdly1;
2364 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
2365 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
2366 + u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
2367 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
2368 + u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
2369 + int result = -1;
2370 + u32 skip = 1;
2371 +
2372 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
2373 +
2374 + /* Tune Method 2. */
2375 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
2376 +
2377 + rxdly = 0;
2378 + do {
2379 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
2380 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
2381 + if (skip == 1) {
2382 + skip = 0;
2383 + continue;
2384 + }
2385 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
2386 +
2387 + if (host->app_cmd) {
2388 + result = msdc_app_cmd(host->mmc, host);
2389 + if (result) {
2390 + //printk("TUNE_BREAD app_cmd<%d> failed\n", host->mrq->cmd->opcode);
2391 + continue;
2392 + }
2393 + }
2394 + result = msdc_do_request(mmc,mrq);
2395 +
2396 + sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
2397 + if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
2398 + //printk("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>\n",
2399 + // (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
2400 + // sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
2401 +
2402 + /* Fix me: result is 0, but dcrc is still exist */
2403 + if (result == 0 && dcrc == 0) {
2404 + goto done;
2405 + } else {
2406 + /* there is a case: command timeout, and data phase not processed */
2407 + if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
2408 + //printk("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\n",
2409 + // result, mrq->cmd->error, mrq->data->error);
2410 + goto done;
2411 + }
2412 + }
2413 + }
2414 +
2415 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
2416 + cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
2417 +
2418 + /* E1 ECO. YD: Reverse */
2419 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2420 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
2421 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
2422 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
2423 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
2424 + orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
2425 + orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
2426 + orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
2427 + orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
2428 + } else {
2429 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
2430 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
2431 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
2432 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
2433 + orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
2434 + orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
2435 + orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
2436 + orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
2437 + }
2438 +
2439 + if (ddr) {
2440 + cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
2441 + cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
2442 + cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
2443 + cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
2444 + } else {
2445 + cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
2446 + cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
2447 + cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
2448 + cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
2449 + }
2450 + cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
2451 + cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
2452 + cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
2453 + cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
2454 +
2455 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
2456 + cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
2457 +
2458 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
2459 + sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
2460 +
2461 + } while (++rxdly < 32);
2462 +
2463 +done:
2464 + return result;
2465 +}
2466 +
2467 +static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
2468 +{
2469 + struct msdc_host *host = mmc_priv(mmc);
2470 + u32 base = host->base;
2471 +
2472 + u32 wrrdly, cur_wrrdly = 0, orig_wrrdly;
2473 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
2474 + u32 rxdly, cur_rxdly0;
2475 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
2476 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
2477 + int result = -1;
2478 + u32 skip = 1;
2479 +
2480 + // MSDC_IOCON_DDR50CKD need to check. [Fix me]
2481 +
2482 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
2483 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl );
2484 +
2485 + /* Tune Method 2. just DAT0 */
2486 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
2487 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
2488 +
2489 + /* E1 ECO. YD: Reverse */
2490 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2491 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
2492 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
2493 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
2494 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
2495 + } else {
2496 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
2497 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
2498 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
2499 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
2500 + }
2501 +
2502 + rxdly = 0;
2503 + do {
2504 + wrrdly = 0;
2505 + do {
2506 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
2507 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
2508 + if (skip == 1) {
2509 + skip = 0;
2510 + continue;
2511 + }
2512 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
2513 +
2514 + if (host->app_cmd) {
2515 + result = msdc_app_cmd(host->mmc, host);
2516 + if (result) {
2517 + //printk("TUNE_BWRITE app_cmd<%d> failed\n", host->mrq->cmd->opcode);
2518 + continue;
2519 + }
2520 + }
2521 + result = msdc_do_request(mmc,mrq);
2522 +
2523 + //printk("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>\n",
2524 + // result == 0 ? "PASS" : "FAIL",
2525 + // cur_dsmpl, cur_wrrdly, cur_rxdly0);
2526 +
2527 + if (result == 0) {
2528 + goto done;
2529 + }
2530 + else {
2531 + /* there is a case: command timeout, and data phase not processed */
2532 + if (mrq->data->error != (unsigned int)(-EIO)) {
2533 + //printk("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\n",
2534 + // && result, mrq->cmd->error, mrq->data->error);
2535 + goto done;
2536 + }
2537 + }
2538 + }
2539 + cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
2540 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
2541 + } while (++wrrdly < 32);
2542 +
2543 + cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
2544 + cur_dat1 = orig_dat1;
2545 + cur_dat2 = orig_dat2;
2546 + cur_dat3 = orig_dat3;
2547 +
2548 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
2549 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
2550 + } while (++rxdly < 32);
2551 +
2552 +done:
2553 + return result;
2554 +}
2555 +
2556 +static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
2557 +{
2558 + struct mmc_command cmd;
2559 + struct mmc_request mrq;
2560 + u32 err;
2561 +
2562 + memset(&cmd, 0, sizeof(struct mmc_command));
2563 + cmd.opcode = MMC_SEND_STATUS;
2564 + if (mmc->card) {
2565 + cmd.arg = mmc->card->rca << 16;
2566 + } else {
2567 + //printk("cmd13 mmc card is null\n");
2568 + cmd.arg = host->app_cmd_arg;
2569 + }
2570 + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
2571 +
2572 + memset(&mrq, 0, sizeof(struct mmc_request));
2573 + mrq.cmd = &cmd; cmd.mrq = &mrq;
2574 + cmd.data = NULL;
2575 +
2576 + err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
2577 +
2578 + if (status)
2579 + *status = cmd.resp[0];
2580 +
2581 + return err;
2582 +}
2583 +
2584 +static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
2585 +{
2586 + u32 err = 0;
2587 + u32 status = 0;
2588 +
2589 + do {
2590 + err = msdc_get_card_status(mmc, host, &status);
2591 + if (err)
2592 + return err;
2593 + /* need cmd12? */
2594 + //printk("cmd<13> resp<0x%x>\n", status);
2595 + } while (R1_CURRENT_STATE(status) == 7);
2596 +
2597 + return err;
2598 +}
2599 +
2600 +static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
2601 +{
2602 + struct msdc_host *host = mmc_priv(mmc);
2603 + struct mmc_command *cmd;
2604 + struct mmc_data *data;
2605 + int ret=0, read;
2606 +
2607 + cmd = mrq->cmd;
2608 + data = mrq->cmd->data;
2609 +
2610 + read = data->flags & MMC_DATA_READ ? 1 : 0;
2611 +
2612 + if (read) {
2613 + if (data->error == (unsigned int)(-EIO))
2614 + ret = msdc_tune_bread(mmc,mrq);
2615 + } else {
2616 + ret = msdc_check_busy(mmc, host);
2617 + if (ret){
2618 + //printk("XXX cmd13 wait program done failed\n");
2619 + return ret;
2620 + }
2621 + /* CRC and TO */
2622 + /* Fix me: don't care card status? */
2623 + ret = msdc_tune_bwrite(mmc,mrq);
2624 + }
2625 +
2626 + return ret;
2627 +}
2628 +
2629 +static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
2630 +{
2631 + struct msdc_host *host = mmc_priv(mmc);
2632 +
2633 + if (host->mrq) {
2634 + //printk("XXX host->mrq<0x%.8x>\n", (int)host->mrq);
2635 + BUG();
2636 + }
2637 + if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
2638 + //printk("cmd<%d> card<%d> power<%d>\n", mrq->cmd->opcode, is_card_present(host), host->power_mode);
2639 + mrq->cmd->error = (unsigned int)-ENOMEDIUM;
2640 + mrq->done(mrq);
2641 + return;
2642 + }
2643 + spin_lock(&host->lock);
2644 +
2645 + host->mrq = mrq;
2646 +
2647 + if (msdc_do_request(mmc,mrq))
2648 + if(host->hw->flags & MSDC_REMOVABLE && mrq->data && mrq->data->error)
2649 + msdc_tune_request(mmc,mrq);
2650 +
2651 + if (mrq->cmd->opcode == MMC_APP_CMD) {
2652 + host->app_cmd = 1;
2653 + host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
2654 + } else {
2655 + host->app_cmd = 0;
2656 + }
2657 +
2658 + host->mrq = NULL;
2659 +
2660 + spin_unlock(&host->lock);
2661 +
2662 + mmc_request_done(mmc, mrq);
2663 +}
2664 +
2665 +/* called by ops.set_ios */
2666 +static void msdc_set_buswidth(struct msdc_host *host, u32 width)
2667 +{
2668 + u32 base = host->base;
2669 + u32 val = sdr_read32(SDC_CFG);
2670 +
2671 + val &= ~SDC_CFG_BUSWIDTH;
2672 +
2673 + switch (width) {
2674 + default:
2675 + case MMC_BUS_WIDTH_1:
2676 + width = 1;
2677 + val |= (MSDC_BUS_1BITS << 16);
2678 + break;
2679 + case MMC_BUS_WIDTH_4:
2680 + val |= (MSDC_BUS_4BITS << 16);
2681 + break;
2682 + case MMC_BUS_WIDTH_8:
2683 + val |= (MSDC_BUS_8BITS << 16);
2684 + break;
2685 + }
2686 +
2687 + sdr_write32(SDC_CFG, val);
2688 +
2689 + //printk("Bus Width = %d\n", width);
2690 +}
2691 +
2692 +/* ops.set_ios */
2693 +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2694 +{
2695 + struct msdc_host *host = mmc_priv(mmc);
2696 + struct msdc_hw *hw=host->hw;
2697 + u32 base = host->base;
2698 + u32 ddr = 0;
2699 +
2700 +#ifdef MT6575_SD_DEBUG
2701 + static char *vdd[] = {
2702 + "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
2703 + "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
2704 + "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
2705 + "3.40v", "3.50v", "3.60v"
2706 + };
2707 + static char *power_mode[] = {
2708 + "OFF", "UP", "ON"
2709 + };
2710 + static char *bus_mode[] = {
2711 + "UNKNOWN", "OPENDRAIN", "PUSHPULL"
2712 + };
2713 + static char *timing[] = {
2714 + "LEGACY", "MMC_HS", "SD_HS"
2715 + };
2716 +
2717 + /*printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)\n",
2718 + ios->clock / 1000, bus_mode[ios->bus_mode],
2719 + (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
2720 + power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);*/
2721 +#endif
2722 +
2723 + msdc_set_buswidth(host, ios->bus_width);
2724 +
2725 + /* Power control ??? */
2726 + switch (ios->power_mode) {
2727 + case MMC_POWER_OFF:
2728 + case MMC_POWER_UP:
2729 + // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
2730 + break;
2731 + case MMC_POWER_ON:
2732 + host->power_mode = MMC_POWER_ON;
2733 + break;
2734 + default:
2735 + break;
2736 + }
2737 +
2738 + /* Clock control */
2739 + if (host->mclk != ios->clock) {
2740 + if(ios->clock > 25000000) {
2741 + //printk("SD data latch edge<%d>\n", hw->data_edge);
2742 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
2743 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
2744 + } else {
2745 + sdr_write32(MSDC_IOCON, 0x00000000);
2746 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
2747 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
2748 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
2749 + }
2750 + msdc_set_mclk(host, ddr, ios->clock);
2751 + }
2752 +}
2753 +
2754 +/* ops.get_ro */
2755 +static int msdc_ops_get_ro(struct mmc_host *mmc)
2756 +{
2757 + struct msdc_host *host = mmc_priv(mmc);
2758 + u32 base = host->base;
2759 + unsigned long flags;
2760 + int ro = 0;
2761 +
2762 + if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
2763 + spin_lock_irqsave(&host->lock, flags);
2764 + ro = (sdr_read32(MSDC_PS) >> 31);
2765 + spin_unlock_irqrestore(&host->lock, flags);
2766 + }
2767 + return ro;
2768 +}
2769 +
2770 +/* ops.get_cd */
2771 +static int msdc_ops_get_cd(struct mmc_host *mmc)
2772 +{
2773 + struct msdc_host *host = mmc_priv(mmc);
2774 + u32 base = host->base;
2775 + unsigned long flags;
2776 + int present = 1;
2777 +
2778 + /* for sdio, MSDC_REMOVABLE not set, always return 1 */
2779 + if (!(host->hw->flags & MSDC_REMOVABLE)) {
2780 + /* For sdio, read H/W always get<1>, but may timeout some times */
2781 +#if 1
2782 + host->card_inserted = 1;
2783 + return 1;
2784 +#else
2785 + host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
2786 + printk("sdio ops_get_cd<%d>\n", host->card_inserted);
2787 + return host->card_inserted;
2788 +#endif
2789 + }
2790 +
2791 + /* MSDC_CD_PIN_EN set for card */
2792 + if (host->hw->flags & MSDC_CD_PIN_EN) {
2793 + spin_lock_irqsave(&host->lock, flags);
2794 +#if 0
2795 + present = host->card_inserted; /* why not read from H/W: Fix me*/
2796 +#else
2797 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
2798 + host->card_inserted = present;
2799 +#endif
2800 + spin_unlock_irqrestore(&host->lock, flags);
2801 + } else {
2802 + present = 0; /* TODO? Check DAT3 pins for card detection */
2803 + }
2804 +
2805 + //printk("ops_get_cd return<%d>\n", present);
2806 + return present;
2807 +}
2808 +
2809 +/* ops.enable_sdio_irq */
2810 +static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
2811 +{
2812 + struct msdc_host *host = mmc_priv(mmc);
2813 + struct msdc_hw *hw = host->hw;
2814 + u32 base = host->base;
2815 + u32 tmp;
2816 +
2817 + if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
2818 + if (enable) {
2819 + hw->enable_sdio_eirq(); /* combo_sdio_enable_eirq */
2820 + } else {
2821 + hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
2822 + }
2823 + } else {
2824 + //printk("XXX \n"); /* so never enter here */
2825 + tmp = sdr_read32(SDC_CFG);
2826 + /* FIXME. Need to interrupt gap detection */
2827 + if (enable) {
2828 + tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
2829 + } else {
2830 + tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
2831 + }
2832 + sdr_write32(SDC_CFG, tmp);
2833 + }
2834 +}
2835 +
2836 +static struct mmc_host_ops mt_msdc_ops = {
2837 + .request = msdc_ops_request,
2838 + .set_ios = msdc_ops_set_ios,
2839 + .get_ro = msdc_ops_get_ro,
2840 + .get_cd = msdc_ops_get_cd,
2841 + .enable_sdio_irq = msdc_ops_enable_sdio_irq,
2842 +};
2843 +
2844 +/*--------------------------------------------------------------------------*/
2845 +/* interrupt handler */
2846 +/*--------------------------------------------------------------------------*/
2847 +static irqreturn_t msdc_irq(int irq, void *dev_id)
2848 +{
2849 + struct msdc_host *host = (struct msdc_host *)dev_id;
2850 + struct mmc_data *data = host->data;
2851 + struct mmc_command *cmd = host->cmd;
2852 + u32 base = host->base;
2853 +
2854 + u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
2855 + MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
2856 + MSDC_INT_ACMD19_DONE;
2857 + u32 datsts = MSDC_INT_DATCRCERR |MSDC_INT_DATTMO;
2858 +
2859 + u32 intsts = sdr_read32(MSDC_INT);
2860 + u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
2861 +
2862 + sdr_write32(MSDC_INT, intsts); /* clear interrupts */
2863 + /* MSG will cause fatal error */
2864 +
2865 + /* card change interrupt */
2866 + if (intsts & MSDC_INT_CDSC){
2867 + //printk("MSDC_INT_CDSC irq<0x%.8x>\n", intsts);
2868 + tasklet_hi_schedule(&host->card_tasklet);
2869 + /* tuning when plug card ? */
2870 + }
2871 +
2872 + /* sdio interrupt */
2873 + if (intsts & MSDC_INT_SDIOIRQ){
2874 + //printk("XXX MSDC_INT_SDIOIRQ\n"); /* seems not sdio irq */
2875 + //mmc_signal_sdio_irq(host->mmc);
2876 + }
2877 +
2878 + /* transfer complete interrupt */
2879 + if (data != NULL) {
2880 + if (inten & MSDC_INT_XFER_COMPL) {
2881 + data->bytes_xfered = host->dma.xfersz;
2882 + complete(&host->xfer_done);
2883 + }
2884 +
2885 + if (intsts & datsts) {
2886 + /* do basic reset, or stop command will sdc_busy */
2887 + msdc_reset();
2888 + msdc_clr_fifo();
2889 + msdc_clr_int();
2890 + atomic_set(&host->abort, 1); /* For PIO mode exit */
2891 +
2892 + if (intsts & MSDC_INT_DATTMO){
2893 + //printk("XXX CMD<%d> MSDC_INT_DATTMO\n", host->mrq->cmd->opcode);
2894 + data->error = (unsigned int)-ETIMEDOUT;
2895 + }
2896 + else if (intsts & MSDC_INT_DATCRCERR){
2897 + //printk("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>\n", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
2898 + data->error = (unsigned int)-EIO;
2899 + }
2900 +
2901 + //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
2902 + if (host->dma_xfer) {
2903 + complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
2904 + } /* PIO mode can't do complete, because not init */
2905 + }
2906 + }
2907 +
2908 + /* command interrupts */
2909 + if ((cmd != NULL) && (intsts & cmdsts)) {
2910 + if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
2911 + (intsts & MSDC_INT_ACMD19_DONE)) {
2912 + u32 *rsp = &cmd->resp[0];
2913 +
2914 + switch (host->cmd_rsp) {
2915 + case RESP_NONE:
2916 + break;
2917 + case RESP_R2:
2918 + *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
2919 + *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
2920 + break;
2921 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
2922 + if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
2923 + *rsp = sdr_read32(SDC_ACMD_RESP);
2924 + } else {
2925 + *rsp = sdr_read32(SDC_RESP0);
2926 + }
2927 + break;
2928 + }
2929 + } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
2930 + if(intsts & MSDC_INT_ACMDCRCERR){
2931 + //printk("XXX CMD<%d> MSDC_INT_ACMDCRCERR\n",cmd->opcode);
2932 + }
2933 + else {
2934 + //printk("XXX CMD<%d> MSDC_INT_RSPCRCERR\n",cmd->opcode);
2935 + }
2936 + cmd->error = (unsigned int)-EIO;
2937 + } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
2938 + if(intsts & MSDC_INT_ACMDTMO){
2939 + //printk("XXX CMD<%d> MSDC_INT_ACMDTMO\n",cmd->opcode);
2940 + }
2941 + else {
2942 + //printk("XXX CMD<%d> MSDC_INT_CMDTMO\n",cmd->opcode);
2943 + }
2944 + cmd->error = (unsigned int)-ETIMEDOUT;
2945 + msdc_reset();
2946 + msdc_clr_fifo();
2947 + msdc_clr_int();
2948 + }
2949 + complete(&host->cmd_done);
2950 + }
2951 +
2952 + /* mmc irq interrupts */
2953 + if (intsts & MSDC_INT_MMCIRQ) {
2954 + //printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
2955 + }
2956 +
2957 +#ifdef MT6575_SD_DEBUG
2958 + {
2959 + msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
2960 + /*printk("IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)\n",
2961 + intsts,
2962 + int_reg->mmcirq,
2963 + int_reg->cdsc,
2964 + int_reg->atocmdrdy,
2965 + int_reg->atocmdtmo,
2966 + int_reg->atocmdcrc,
2967 + int_reg->atocmd19done);
2968 + printk("IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)\n",
2969 + intsts,
2970 + int_reg->sdioirq,
2971 + int_reg->cmdrdy,
2972 + int_reg->cmdtmo,
2973 + int_reg->rspcrc,
2974 + int_reg->csta);
2975 + printk("IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)\n",
2976 + intsts,
2977 + int_reg->xfercomp,
2978 + int_reg->dxferdone,
2979 + int_reg->dattmo,
2980 + int_reg->datcrc,
2981 + int_reg->dmaqempty);*/
2982 +
2983 + }
2984 +#endif
2985 +
2986 + return IRQ_HANDLED;
2987 +}
2988 +
2989 +/*--------------------------------------------------------------------------*/
2990 +/* platform_driver members */
2991 +/*--------------------------------------------------------------------------*/
2992 +/* called by msdc_drv_probe/remove */
2993 +static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
2994 +{
2995 + struct msdc_hw *hw = host->hw;
2996 + u32 base = host->base;
2997 +
2998 + /* for sdio, not set */
2999 + if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
3000 + /* Pull down card detection pin since it is not avaiable */
3001 + /*
3002 + if (hw->config_gpio_pin)
3003 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
3004 + */
3005 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
3006 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
3007 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
3008 + return;
3009 + }
3010 +
3011 + //printk("CD IRQ Eanable(%d)\n", enable);
3012 +
3013 + if (enable) {
3014 + if (hw->enable_cd_eirq) { /* not set, never enter */
3015 + hw->enable_cd_eirq();
3016 + } else {
3017 + /* card detection circuit relies on the core power so that the core power
3018 + * shouldn't be turned off. Here adds a reference count to keep
3019 + * the core power alive.
3020 + */
3021 + //msdc_vcore_on(host); //did in msdc_init_hw()
3022 +
3023 + if (hw->config_gpio_pin) /* NULL */
3024 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
3025 +
3026 + sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
3027 + sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
3028 + sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
3029 + sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
3030 + }
3031 + } else {
3032 + if (hw->disable_cd_eirq) {
3033 + hw->disable_cd_eirq();
3034 + } else {
3035 + if (hw->config_gpio_pin) /* NULL */
3036 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
3037 +
3038 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
3039 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
3040 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
3041 +
3042 + /* Here decreases a reference count to core power since card
3043 + * detection circuit is shutdown.
3044 + */
3045 + //msdc_vcore_off(host);
3046 + }
3047 + }
3048 +}
3049 +
3050 +/* called by msdc_drv_probe */
3051 +static void msdc_init_hw(struct msdc_host *host)
3052 +{
3053 + u32 base = host->base;
3054 + struct msdc_hw *hw = host->hw;
3055 +
3056 +#ifdef MT6575_SD_DEBUG
3057 + msdc_reg[host->id] = (struct msdc_regs *)host->base;
3058 +#endif
3059 +
3060 + /* Power on */
3061 +#if 0 /* --- chhung */
3062 + msdc_vcore_on(host);
3063 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
3064 + msdc_select_clksrc(host, hw->clk_src);
3065 + enable_clock(PERI_MSDC0_PDN + host->id, "SD");
3066 + msdc_vdd_on(host);
3067 +#endif /* end of --- */
3068 + /* Configure to MMC/SD mode */
3069 + sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
3070 +
3071 + /* Reset */
3072 + msdc_reset();
3073 + msdc_clr_fifo();
3074 +
3075 + /* Disable card detection */
3076 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
3077 +
3078 + /* Disable and clear all interrupts */
3079 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
3080 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
3081 +
3082 +#if 1
3083 + /* reset tuning parameter */
3084 + sdr_write32(MSDC_PAD_CTL0, 0x00090000);
3085 + sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
3086 + sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
3087 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
3088 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
3089 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
3090 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
3091 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
3092 + sdr_write32(MSDC_IOCON, 0x00000000);
3093 +#if 0 // use MT7620 default value: 0x403c004f
3094 + sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
3095 +#endif
3096 +
3097 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3098 + if (host->id == 1) {
3099 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
3100 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
3101 +
3102 + /* internal clock: latch read data */
3103 + sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
3104 + }
3105 + }
3106 +#endif
3107 +
3108 + /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
3109 + pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
3110 + set when kernel driver wants to use SDIO bus interrupt */
3111 + /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
3112 + sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
3113 +
3114 + /* disable detect SDIO device interupt function */
3115 + sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
3116 +
3117 + /* eneable SMT for glitch filter */
3118 + sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
3119 + sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
3120 + sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
3121 +
3122 +#if 1
3123 + /* set clk, cmd, dat pad driving */
3124 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
3125 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
3126 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
3127 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
3128 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
3129 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
3130 +#else
3131 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
3132 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
3133 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
3134 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
3135 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
3136 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
3137 +#endif
3138 +
3139 + /* set sampling edge */
3140 +
3141 + /* write crc timeout detection */
3142 + sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
3143 +
3144 + /* Configure to default data timeout */
3145 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
3146 +
3147 + msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
3148 +
3149 + //printk("init hardware done!\n");
3150 +}
3151 +
3152 +/* called by msdc_drv_remove */
3153 +static void msdc_deinit_hw(struct msdc_host *host)
3154 +{
3155 + u32 base = host->base;
3156 +
3157 + /* Disable and clear all interrupts */
3158 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
3159 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
3160 +
3161 + /* Disable card detection */
3162 + msdc_enable_cd_irq(host, 0);
3163 + // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
3164 +}
3165 +
3166 +/* init gpd and bd list in msdc_drv_probe */
3167 +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
3168 +{
3169 + gpd_t *gpd = dma->gpd;
3170 + bd_t *bd = dma->bd;
3171 + bd_t *ptr, *prev;
3172 +
3173 + /* we just support one gpd */
3174 + int bdlen = MAX_BD_PER_GPD;
3175 +
3176 + /* init the 2 gpd */
3177 + memset(gpd, 0, sizeof(gpd_t) * 2);
3178 + //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */
3179 + //gpd->next = (dma->gpd_addr + 1); /* bug */
3180 + gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));
3181 +
3182 + //gpd->intr = 0;
3183 + gpd->bdp = 1; /* hwo, cs, bd pointer */
3184 + //gpd->ptr = (void*)virt_to_phys(bd);
3185 + gpd->ptr = (void *)dma->bd_addr; /* physical address */
3186 +
3187 + memset(bd, 0, sizeof(bd_t) * bdlen);
3188 + ptr = bd + bdlen - 1;
3189 + //ptr->eol = 1; /* 0 or 1 [Fix me]*/
3190 + //ptr->next = 0;
3191 +
3192 + while (ptr != bd) {
3193 + prev = ptr - 1;
3194 + prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
3195 + ptr = prev;
3196 + }
3197 +}
3198 +
3199 +static int msdc_drv_probe(struct platform_device *pdev)
3200 +{
3201 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3202 + __iomem void *base;
3203 + struct mmc_host *mmc;
3204 + struct resource *mem;
3205 + struct msdc_host *host;
3206 + struct msdc_hw *hw;
3207 + int ret, irq;
3208 + pdev->dev.platform_data = &msdc0_hw;
3209 +
3210 + /* Allocate MMC host for this device */
3211 + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
3212 + if (!mmc) return -ENOMEM;
3213 +
3214 + hw = (struct msdc_hw*)pdev->dev.platform_data;
3215 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3216 + irq = platform_get_irq(pdev, 0);
3217 +
3218 + //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
3219 +
3220 + base = devm_request_and_ioremap(&pdev->dev, res);
3221 + if (IS_ERR(base))
3222 + return PTR_ERR(base);
3223 +
3224 +/* mem = request_mem_region(mem->start - 0xa0000000, (mem->end - mem->start + 1) - 0xa0000000, dev_name(&pdev->dev));
3225 + if (mem == NULL) {
3226 + mmc_free_host(mmc);
3227 + return -EBUSY;
3228 + }
3229 +*/
3230 + /* Set host parameters to mmc */
3231 + mmc->ops = &mt_msdc_ops;
3232 + mmc->f_min = HOST_MIN_MCLK;
3233 + mmc->f_max = HOST_MAX_MCLK;
3234 + mmc->ocr_avail = MSDC_OCR_AVAIL;
3235 +
3236 + /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
3237 + For sdio : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
3238 + if (hw->flags & MSDC_HIGHSPEED) {
3239 + mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
3240 + }
3241 + if (hw->data_pins == 4) { /* current data_pins are all 4*/
3242 + mmc->caps |= MMC_CAP_4_BIT_DATA;
3243 + } else if (hw->data_pins == 8) {
3244 + mmc->caps |= MMC_CAP_8_BIT_DATA;
3245 + }
3246 + if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
3247 + mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
3248 +
3249 + /* MMC core transfer sizes tunable parameters */
3250 + // mmc->max_hw_segs = MAX_HW_SGMTS;
3251 +// mmc->max_phys_segs = MAX_PHY_SGMTS;
3252 + mmc->max_seg_size = MAX_SGMT_SZ;
3253 + mmc->max_blk_size = HOST_MAX_BLKSZ;
3254 + mmc->max_req_size = MAX_REQ_SZ;
3255 + mmc->max_blk_count = mmc->max_req_size;
3256 +
3257 + host = mmc_priv(mmc);
3258 + host->hw = hw;
3259 + host->mmc = mmc;
3260 + host->id = pdev->id;
3261 + host->error = 0;
3262 + host->irq = irq;
3263 + host->base = (unsigned long) base;
3264 + host->mclk = 0; /* mclk: the request clock of mmc sub-system */
3265 + host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
3266 + host->sclk = 0; /* sclk: the really clock after divition */
3267 + host->pm_state = PMSG_RESUME;
3268 + host->suspend = 0;
3269 + host->core_clkon = 0;
3270 + host->card_clkon = 0;
3271 + host->core_power = 0;
3272 + host->power_mode = MMC_POWER_OFF;
3273 +// host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
3274 + host->timeout_ns = 0;
3275 + host->timeout_clks = DEFAULT_DTOC * 65536;
3276 +
3277 + host->mrq = NULL;
3278 + //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
3279 +
3280 + host->dma.used_gpd = 0;
3281 + host->dma.used_bd = 0;
3282 +
3283 + /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
3284 + host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL);
3285 + host->dma.bd = dma_alloc_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), &host->dma.bd_addr, GFP_KERNEL);
3286 + BUG_ON((!host->dma.gpd) || (!host->dma.bd));
3287 + msdc_init_gpd_bd(host, &host->dma);
3288 + /*for emmc*/
3289 + msdc_6575_host[pdev->id] = host;
3290 +
3291 + tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
3292 + spin_lock_init(&host->lock);
3293 + msdc_init_hw(host);
3294 +
3295 + ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
3296 + if (ret) goto release;
3297 + // mt65xx_irq_unmask(irq); /* --- by chhung */
3298 +
3299 + if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
3300 + if (hw->request_cd_eirq) { /* not set for MT6575 */
3301 + hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
3302 + }
3303 + }
3304 +
3305 + if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
3306 + hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
3307 +
3308 + if (hw->register_pm) {/* yes for sdio */
3309 + if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
3310 + //printk("MSDC_SYS_SUSPEND and register_pm both set\n");
3311 + }
3312 + //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
3313 + }
3314 +
3315 + platform_set_drvdata(pdev, mmc);
3316 +
3317 + ret = mmc_add_host(mmc);
3318 + if (ret) goto free_irq;
3319 +
3320 + /* Config card detection pin and enable interrupts */
3321 + if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
3322 + msdc_enable_cd_irq(host, 1);
3323 + } else {
3324 + msdc_enable_cd_irq(host, 0);
3325 + }
3326 +
3327 + return 0;
3328 +
3329 +free_irq:
3330 + free_irq(irq, host);
3331 +release:
3332 + platform_set_drvdata(pdev, NULL);
3333 + msdc_deinit_hw(host);
3334 +
3335 + tasklet_kill(&host->card_tasklet);
3336 +
3337 +/* if (mem)
3338 + release_mem_region(mem->start, mem->end - mem->start + 1);
3339 +*/
3340 + mmc_free_host(mmc);
3341 +
3342 + return ret;
3343 +}
3344 +
3345 +/* 4 device share one driver, using "drvdata" to show difference */
3346 +static int msdc_drv_remove(struct platform_device *pdev)
3347 +{
3348 + struct mmc_host *mmc;
3349 + struct msdc_host *host;
3350 + struct resource *mem;
3351 +
3352 +
3353 + mmc = platform_get_drvdata(pdev);
3354 + BUG_ON(!mmc);
3355 +
3356 + host = mmc_priv(mmc);
3357 + BUG_ON(!host);
3358 +
3359 + //printk("removed !!!\n");
3360 +
3361 + platform_set_drvdata(pdev, NULL);
3362 + mmc_remove_host(host->mmc);
3363 + msdc_deinit_hw(host);
3364 +
3365 + tasklet_kill(&host->card_tasklet);
3366 + free_irq(host->irq, host);
3367 +
3368 + dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
3369 + dma_free_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), host->dma.bd, host->dma.bd_addr);
3370 +
3371 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3372 +
3373 + if (mem)
3374 + release_mem_region(mem->start, mem->end - mem->start + 1);
3375 +
3376 + mmc_free_host(host->mmc);
3377 +
3378 + return 0;
3379 +}
3380 +
3381 +static const struct of_device_id mt7620a_sdhci_match[] = {
3382 + { .compatible = "ralink,mt7620a-sdhci" },
3383 + {},
3384 +};
3385 +MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
3386 +
3387 +/* Fix me: Power Flow */
3388 +static struct platform_driver mt_msdc_driver = {
3389 + .probe = msdc_drv_probe,
3390 + .remove = msdc_drv_remove,
3391 + .driver = {
3392 + .name = DRV_NAME,
3393 + .owner = THIS_MODULE,
3394 + .of_match_table = mt7620a_sdhci_match,
3395 +
3396 + },
3397 +};
3398 +
3399 +static int __init mt_msdc_init(void)
3400 +{
3401 + int ret;
3402 +/* +++ chhung */
3403 + unsigned int reg;
3404 +
3405 + mtk_sd_device.dev.platform_data = &msdc0_hw;
3406 + printk("MTK MSDC device init.\n");
3407 + reg = sdr_read32((__iomem void *) 0xb0000060) & ~(0x3<<18);
3408 + reg |= 0x1 << 18;
3409 + sdr_write32((__iomem void *) 0xb0000060, reg);
3410 +/* end of +++ */
3411 + ret = platform_driver_register(&mt_msdc_driver);
3412 + if (ret) {
3413 + printk(KERN_ERR DRV_NAME ": Can't register driver");
3414 + return ret;
3415 + }
3416 + printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
3417 +
3418 + //msdc_debug_proc_init();
3419 + return 0;
3420 +}
3421 +
3422 +static void __exit mt_msdc_exit(void)
3423 +{
3424 + platform_driver_unregister(&mt_msdc_driver);
3425 +}
3426 +
3427 +module_init(mt_msdc_init);
3428 +module_exit(mt_msdc_exit);
3429 +MODULE_LICENSE("GPL");
3430 +MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
3431 +MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
3432 +
3433 +EXPORT_SYMBOL(msdc_6575_host);
OpenWrt SVN history