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ramips: add ralink v3.10 support
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.10 / 0027-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
1 From de1defdad7554d6ba885a6d3dc55105e01e9a07e Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 2 May 2013 14:59:01 +0200
4 Subject: [PATCH 27/33] mmc: MIPS: ralink: add sdhci for mt7620a SoC
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mmc/host/Kconfig | 11 +
9 drivers/mmc/host/Makefile | 1 +
10 drivers/mmc/host/mt6575_sd.h | 1068 ++++++++++++++++++
11 drivers/mmc/host/sdhci-mt7620.c | 2314 +++++++++++++++++++++++++++++++++++++++
12 4 files changed, 3394 insertions(+)
13 create mode 100644 drivers/mmc/host/mt6575_sd.h
14 create mode 100644 drivers/mmc/host/sdhci-mt7620.c
15
16 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
17 index 9ab8f8d..ef6bf59 100644
18 --- a/drivers/mmc/host/Kconfig
19 +++ b/drivers/mmc/host/Kconfig
20 @@ -260,6 +260,17 @@ config MMC_SDHCI_BCM2835
21
22 If unsure, say N.
23
24 +config MMC_SDHCI_MT7620
25 + tristate "SDHCI platform support for the MT7620 SD/MMC Controller"
26 + depends on SOC_MT7620
27 + depends on MMC_SDHCI_PLTFM
28 + select MMC_SDHCI_IO_ACCESSORS
29 + help
30 + This selects the BCM2835 SD/MMC controller. If you have a BCM2835
31 + platform with SD or MMC devices, say Y or M here.
32 +
33 + If unsure, say N.
34 +
35 config MMC_OMAP
36 tristate "TI OMAP Multimedia Card Interface support"
37 depends on ARCH_OMAP
38 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
39 index cd32280..c800bed 100644
40 --- a/drivers/mmc/host/Makefile
41 +++ b/drivers/mmc/host/Makefile
42 @@ -61,6 +61,7 @@ obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o
43 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
44 obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
45 obj-$(CONFIG_MMC_SDHCI_BCM2835) += sdhci-bcm2835.o
46 +obj-$(CONFIG_MMC_SDHCI_MT7620) += sdhci-mt7620.o
47
48 ifeq ($(CONFIG_CB710_DEBUG),y)
49 CFLAGS-cb710-mmc += -DDEBUG
50 diff --git a/drivers/mmc/host/mt6575_sd.h b/drivers/mmc/host/mt6575_sd.h
51 new file mode 100644
52 index 0000000..406382c
53 --- /dev/null
54 +++ b/drivers/mmc/host/mt6575_sd.h
55 @@ -0,0 +1,1068 @@
56 +/* Copyright Statement:
57 + *
58 + * This software/firmware and related documentation ("MediaTek Software") are
59 + * protected under relevant copyright laws. The information contained herein
60 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
61 + * Without the prior written permission of MediaTek inc. and/or its licensors,
62 + * any reproduction, modification, use or disclosure of MediaTek Software,
63 + * and information contained herein, in whole or in part, shall be strictly prohibited.
64 + */
65 +/* MediaTek Inc. (C) 2010. All rights reserved.
66 + *
67 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
68 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
69 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
70 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
71 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
72 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
73 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
74 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
75 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
76 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
77 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
78 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
79 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
80 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
81 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
82 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
83 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
84 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
85 + *
86 + * The following software/firmware and/or related documentation ("MediaTek Software")
87 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
88 + * applicable license agreements with MediaTek Inc.
89 + */
90 +
91 +#ifndef MT6575_SD_H
92 +#define MT6575_SD_H
93 +
94 +#include <linux/bitops.h>
95 +#include <linux/mmc/host.h>
96 +
97 +// #include <mach/mt6575_reg_base.h> /* --- by chhung */
98 +
99 +typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
100 +typedef void (*pm_callback_t)(pm_message_t state, void *data);
101 +
102 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
103 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
104 +#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
105 +#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
106 +#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
107 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
108 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
109 +#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
110 +#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
111 +#define MSDC_DDR (1 << 9) /* ddr mode support */
112 +#define MSDC_SPE (1 << 10) /* special support */
113 +#define MSDC_INTERNAL_CLK (1 << 11) /* Force Internal clock */
114 +#define MSDC_TABDRV (1 << 12) /* TABLET */
115 +
116 +
117 +#define MSDC_SMPL_RISING (0)
118 +#define MSDC_SMPL_FALLING (1)
119 +
120 +#define MSDC_CMD_PIN (0)
121 +#define MSDC_DAT_PIN (1)
122 +#define MSDC_CD_PIN (2)
123 +#define MSDC_WP_PIN (3)
124 +#define MSDC_RST_PIN (4)
125 +
126 +enum {
127 + MSDC_CLKSRC_26MHZ = 0,
128 + MSDC_CLKSRC_197MHZ = 1,
129 + MSDC_CLKSRC_208MHZ = 2
130 +};
131 +
132 +struct msdc_hw {
133 + unsigned char clk_src; /* host clock source */
134 + unsigned char cmd_edge; /* command latch edge */
135 + unsigned char data_edge; /* data latch edge */
136 + unsigned char clk_drv; /* clock pad driving */
137 + unsigned char cmd_drv; /* command pad driving */
138 + unsigned char dat_drv; /* data pad driving */
139 + unsigned long flags; /* hardware capability flags */
140 + unsigned long data_pins; /* data pins */
141 + unsigned long data_offset; /* data address offset */
142 +
143 + /* config gpio pull mode */
144 + void (*config_gpio_pin)(int type, int pull);
145 +
146 + /* external power control for card */
147 + void (*ext_power_on)(void);
148 + void (*ext_power_off)(void);
149 +
150 + /* external sdio irq operations */
151 + void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
152 + void (*enable_sdio_eirq)(void);
153 + void (*disable_sdio_eirq)(void);
154 +
155 + /* external cd irq operations */
156 + void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
157 + void (*enable_cd_eirq)(void);
158 + void (*disable_cd_eirq)(void);
159 + int (*get_cd_status)(void);
160 +
161 + /* power management callback for external module */
162 + void (*register_pm)(pm_callback_t pm_cb, void *data);
163 +};
164 +
165 +extern struct msdc_hw msdc0_hw;
166 +extern struct msdc_hw msdc1_hw;
167 +extern struct msdc_hw msdc2_hw;
168 +extern struct msdc_hw msdc3_hw;
169 +
170 +
171 +/*--------------------------------------------------------------------------*/
172 +/* Common Macro */
173 +/*--------------------------------------------------------------------------*/
174 +#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
175 +
176 +/*--------------------------------------------------------------------------*/
177 +/* Common Definition */
178 +/*--------------------------------------------------------------------------*/
179 +#define MSDC_FIFO_SZ (128)
180 +#define MSDC_FIFO_THD (64) // (128)
181 +#define MSDC_NUM (4)
182 +
183 +#define MSDC_MS (0)
184 +#define MSDC_SDMMC (1)
185 +
186 +#define MSDC_MODE_UNKNOWN (0)
187 +#define MSDC_MODE_PIO (1)
188 +#define MSDC_MODE_DMA_BASIC (2)
189 +#define MSDC_MODE_DMA_DESC (3)
190 +#define MSDC_MODE_DMA_ENHANCED (4)
191 +#define MSDC_MODE_MMC_STREAM (5)
192 +
193 +#define MSDC_BUS_1BITS (0)
194 +#define MSDC_BUS_4BITS (1)
195 +#define MSDC_BUS_8BITS (2)
196 +
197 +#define MSDC_BRUST_8B (3)
198 +#define MSDC_BRUST_16B (4)
199 +#define MSDC_BRUST_32B (5)
200 +#define MSDC_BRUST_64B (6)
201 +
202 +#define MSDC_PIN_PULL_NONE (0)
203 +#define MSDC_PIN_PULL_DOWN (1)
204 +#define MSDC_PIN_PULL_UP (2)
205 +#define MSDC_PIN_KEEP (3)
206 +
207 +#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
208 +#define MSDC_MIN_SCLK (260000)
209 +
210 +#define MSDC_AUTOCMD12 (0x0001)
211 +#define MSDC_AUTOCMD23 (0x0002)
212 +#define MSDC_AUTOCMD19 (0x0003)
213 +
214 +#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
215 +#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
216 +
217 +enum {
218 + RESP_NONE = 0,
219 + RESP_R1,
220 + RESP_R2,
221 + RESP_R3,
222 + RESP_R4,
223 + RESP_R5,
224 + RESP_R6,
225 + RESP_R7,
226 + RESP_R1B
227 +};
228 +
229 +/*--------------------------------------------------------------------------*/
230 +/* Register Offset */
231 +/*--------------------------------------------------------------------------*/
232 +#define OFFSET_MSDC_CFG (0x0)
233 +#define OFFSET_MSDC_IOCON (0x04)
234 +#define OFFSET_MSDC_PS (0x08)
235 +#define OFFSET_MSDC_INT (0x0c)
236 +#define OFFSET_MSDC_INTEN (0x10)
237 +#define OFFSET_MSDC_FIFOCS (0x14)
238 +#define OFFSET_MSDC_TXDATA (0x18)
239 +#define OFFSET_MSDC_RXDATA (0x1c)
240 +#define OFFSET_SDC_CFG (0x30)
241 +#define OFFSET_SDC_CMD (0x34)
242 +#define OFFSET_SDC_ARG (0x38)
243 +#define OFFSET_SDC_STS (0x3c)
244 +#define OFFSET_SDC_RESP0 (0x40)
245 +#define OFFSET_SDC_RESP1 (0x44)
246 +#define OFFSET_SDC_RESP2 (0x48)
247 +#define OFFSET_SDC_RESP3 (0x4c)
248 +#define OFFSET_SDC_BLK_NUM (0x50)
249 +#define OFFSET_SDC_CSTS (0x58)
250 +#define OFFSET_SDC_CSTS_EN (0x5c)
251 +#define OFFSET_SDC_DCRC_STS (0x60)
252 +#define OFFSET_EMMC_CFG0 (0x70)
253 +#define OFFSET_EMMC_CFG1 (0x74)
254 +#define OFFSET_EMMC_STS (0x78)
255 +#define OFFSET_EMMC_IOCON (0x7c)
256 +#define OFFSET_SDC_ACMD_RESP (0x80)
257 +#define OFFSET_SDC_ACMD19_TRG (0x84)
258 +#define OFFSET_SDC_ACMD19_STS (0x88)
259 +#define OFFSET_MSDC_DMA_SA (0x90)
260 +#define OFFSET_MSDC_DMA_CA (0x94)
261 +#define OFFSET_MSDC_DMA_CTRL (0x98)
262 +#define OFFSET_MSDC_DMA_CFG (0x9c)
263 +#define OFFSET_MSDC_DBG_SEL (0xa0)
264 +#define OFFSET_MSDC_DBG_OUT (0xa4)
265 +#define OFFSET_MSDC_PATCH_BIT (0xb0)
266 +#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
267 +#define OFFSET_MSDC_PAD_CTL0 (0xe0)
268 +#define OFFSET_MSDC_PAD_CTL1 (0xe4)
269 +#define OFFSET_MSDC_PAD_CTL2 (0xe8)
270 +#define OFFSET_MSDC_PAD_TUNE (0xec)
271 +#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
272 +#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
273 +#define OFFSET_MSDC_HW_DBG (0xf8)
274 +#define OFFSET_MSDC_VERSION (0x100)
275 +#define OFFSET_MSDC_ECO_VER (0x104)
276 +
277 +/*--------------------------------------------------------------------------*/
278 +/* Register Address */
279 +/*--------------------------------------------------------------------------*/
280 +
281 +/* common register */
282 +#define MSDC_CFG REG_ADDR(MSDC_CFG)
283 +#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
284 +#define MSDC_PS REG_ADDR(MSDC_PS)
285 +#define MSDC_INT REG_ADDR(MSDC_INT)
286 +#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
287 +#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
288 +#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
289 +#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
290 +#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
291 +
292 +/* sdmmc register */
293 +#define SDC_CFG REG_ADDR(SDC_CFG)
294 +#define SDC_CMD REG_ADDR(SDC_CMD)
295 +#define SDC_ARG REG_ADDR(SDC_ARG)
296 +#define SDC_STS REG_ADDR(SDC_STS)
297 +#define SDC_RESP0 REG_ADDR(SDC_RESP0)
298 +#define SDC_RESP1 REG_ADDR(SDC_RESP1)
299 +#define SDC_RESP2 REG_ADDR(SDC_RESP2)
300 +#define SDC_RESP3 REG_ADDR(SDC_RESP3)
301 +#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
302 +#define SDC_CSTS REG_ADDR(SDC_CSTS)
303 +#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
304 +#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
305 +
306 +/* emmc register*/
307 +#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
308 +#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
309 +#define EMMC_STS REG_ADDR(EMMC_STS)
310 +#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
311 +
312 +/* auto command register */
313 +#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
314 +#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
315 +#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
316 +
317 +/* dma register */
318 +#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
319 +#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
320 +#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
321 +#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
322 +
323 +/* pad ctrl register */
324 +#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
325 +#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
326 +#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
327 +
328 +/* data read delay */
329 +#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
330 +#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
331 +
332 +/* debug register */
333 +#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
334 +#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
335 +
336 +/* misc register */
337 +#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
338 +#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
339 +#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
340 +#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
341 +#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
342 +#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
343 +
344 +/*--------------------------------------------------------------------------*/
345 +/* Register Mask */
346 +/*--------------------------------------------------------------------------*/
347 +
348 +/* MSDC_CFG mask */
349 +#define MSDC_CFG_MODE (0x1 << 0) /* RW */
350 +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
351 +#define MSDC_CFG_RST (0x1 << 2) /* RW */
352 +#define MSDC_CFG_PIO (0x1 << 3) /* RW */
353 +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
354 +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
355 +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
356 +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
357 +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
358 +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
359 +
360 +/* MSDC_IOCON mask */
361 +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
362 +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
363 +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
364 +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
365 +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
366 +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
367 +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
368 +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
369 +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
370 +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
371 +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
372 +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
373 +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
374 +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
375 +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
376 +
377 +/* MSDC_PS mask */
378 +#define MSDC_PS_CDEN (0x1 << 0) /* RW */
379 +#define MSDC_PS_CDSTS (0x1 << 1) /* R */
380 +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
381 +#define MSDC_PS_DAT (0xff << 16) /* R */
382 +#define MSDC_PS_CMD (0x1 << 24) /* R */
383 +#define MSDC_PS_WP (0x1UL<< 31) /* R */
384 +
385 +/* MSDC_INT mask */
386 +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
387 +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
388 +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
389 +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
390 +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
391 +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
392 +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
393 +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
394 +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
395 +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
396 +#define MSDC_INT_CSTA (0x1 << 11) /* R */
397 +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
398 +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
399 +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
400 +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
401 +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
402 +
403 +/* MSDC_INTEN mask */
404 +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
405 +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
406 +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
407 +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
408 +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
409 +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
410 +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
411 +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
412 +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
413 +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
414 +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
415 +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
416 +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
417 +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
418 +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
419 +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
420 +
421 +/* MSDC_FIFOCS mask */
422 +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
423 +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
424 +#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
425 +
426 +/* SDC_CFG mask */
427 +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
428 +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
429 +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
430 +#define SDC_CFG_SDIO (0x1 << 19) /* RW */
431 +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
432 +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
433 +#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
434 +
435 +/* SDC_CMD mask */
436 +#define SDC_CMD_OPC (0x3f << 0) /* RW */
437 +#define SDC_CMD_BRK (0x1 << 6) /* RW */
438 +#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
439 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
440 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
441 +#define SDC_CMD_RW (0x1 << 13) /* RW */
442 +#define SDC_CMD_STOP (0x1 << 14) /* RW */
443 +#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
444 +#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
445 +#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
446 +#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
447 +
448 +/* SDC_STS mask */
449 +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
450 +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
451 +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
452 +
453 +/* SDC_DCRC_STS mask */
454 +#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
455 +#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
456 +
457 +/* EMMC_CFG0 mask */
458 +#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
459 +#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
460 +#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
461 +#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
462 +#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
463 +#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
464 +
465 +/* EMMC_CFG1 mask */
466 +#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
467 +#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
468 +
469 +/* EMMC_STS mask */
470 +#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
471 +#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
472 +#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
473 +#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
474 +#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
475 +#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
476 +#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
477 +
478 +/* EMMC_IOCON mask */
479 +#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
480 +
481 +/* SDC_ACMD19_TRG mask */
482 +#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
483 +
484 +/* MSDC_DMA_CTRL mask */
485 +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
486 +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
487 +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
488 +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
489 +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
490 +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
491 +#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
492 +
493 +/* MSDC_DMA_CFG mask */
494 +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
495 +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
496 +#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
497 +#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
498 +
499 +/* MSDC_PATCH_BIT mask */
500 +#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
501 +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
502 +#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
503 +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
504 +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
505 +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
506 +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
507 +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
508 +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
509 +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
510 +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
511 +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
512 +
513 +/* MSDC_PATCH_BIT1 mask */
514 +#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
515 +#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
516 +
517 +/* MSDC_PAD_CTL0 mask */
518 +#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
519 +#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
520 +#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
521 +#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
522 +#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
523 +#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
524 +#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
525 +#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
526 +#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
527 +
528 +/* MSDC_PAD_CTL1 mask */
529 +#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
530 +#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
531 +#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
532 +#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
533 +#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
534 +#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
535 +#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
536 +#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
537 +#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
538 +
539 +/* MSDC_PAD_CTL2 mask */
540 +#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
541 +#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
542 +#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
543 +#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
544 +#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
545 +#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
546 +#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
547 +#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
548 +#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
549 +
550 +/* MSDC_PAD_TUNE mask */
551 +#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
552 +#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
553 +#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
554 +#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
555 +#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
556 +
557 +/* MSDC_DAT_RDDLY0/1 mask */
558 +#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
559 +#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
560 +#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
561 +#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
562 +
563 +#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
564 +#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
565 +#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
566 +#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
567 +
568 +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
569 +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
570 +#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
571 +#define CARD_READY_FOR_DATA (1<<8)
572 +#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
573 +
574 +/*--------------------------------------------------------------------------*/
575 +/* Descriptor Structure */
576 +/*--------------------------------------------------------------------------*/
577 +typedef struct {
578 + u32 hwo:1; /* could be changed by hw */
579 + u32 bdp:1;
580 + u32 rsv0:6;
581 + u32 chksum:8;
582 + u32 intr:1;
583 + u32 rsv1:15;
584 + void *next;
585 + void *ptr;
586 + u32 buflen:16;
587 + u32 extlen:8;
588 + u32 rsv2:8;
589 + u32 arg;
590 + u32 blknum;
591 + u32 cmd;
592 +} gpd_t;
593 +
594 +typedef struct {
595 + u32 eol:1;
596 + u32 rsv0:7;
597 + u32 chksum:8;
598 + u32 rsv1:1;
599 + u32 blkpad:1;
600 + u32 dwpad:1;
601 + u32 rsv2:13;
602 + void *next;
603 + void *ptr;
604 + u32 buflen:16;
605 + u32 rsv3:16;
606 +} bd_t;
607 +
608 +/*--------------------------------------------------------------------------*/
609 +/* Register Debugging Structure */
610 +/*--------------------------------------------------------------------------*/
611 +
612 +typedef struct {
613 + u32 msdc:1;
614 + u32 ckpwn:1;
615 + u32 rst:1;
616 + u32 pio:1;
617 + u32 ckdrven:1;
618 + u32 start18v:1;
619 + u32 pass18v:1;
620 + u32 ckstb:1;
621 + u32 ckdiv:8;
622 + u32 ckmod:2;
623 + u32 pad:14;
624 +} msdc_cfg_reg;
625 +typedef struct {
626 + u32 sdr104cksel:1;
627 + u32 rsmpl:1;
628 + u32 dsmpl:1;
629 + u32 ddlysel:1;
630 + u32 ddr50ckd:1;
631 + u32 dsplsel:1;
632 + u32 pad1:10;
633 + u32 d0spl:1;
634 + u32 d1spl:1;
635 + u32 d2spl:1;
636 + u32 d3spl:1;
637 + u32 d4spl:1;
638 + u32 d5spl:1;
639 + u32 d6spl:1;
640 + u32 d7spl:1;
641 + u32 riscsz:1;
642 + u32 pad2:7;
643 +} msdc_iocon_reg;
644 +typedef struct {
645 + u32 cden:1;
646 + u32 cdsts:1;
647 + u32 pad1:10;
648 + u32 cddebounce:4;
649 + u32 dat:8;
650 + u32 cmd:1;
651 + u32 pad2:6;
652 + u32 wp:1;
653 +} msdc_ps_reg;
654 +typedef struct {
655 + u32 mmcirq:1;
656 + u32 cdsc:1;
657 + u32 pad1:1;
658 + u32 atocmdrdy:1;
659 + u32 atocmdtmo:1;
660 + u32 atocmdcrc:1;
661 + u32 dmaqempty:1;
662 + u32 sdioirq:1;
663 + u32 cmdrdy:1;
664 + u32 cmdtmo:1;
665 + u32 rspcrc:1;
666 + u32 csta:1;
667 + u32 xfercomp:1;
668 + u32 dxferdone:1;
669 + u32 dattmo:1;
670 + u32 datcrc:1;
671 + u32 atocmd19done:1;
672 + u32 pad2:15;
673 +} msdc_int_reg;
674 +typedef struct {
675 + u32 mmcirq:1;
676 + u32 cdsc:1;
677 + u32 pad1:1;
678 + u32 atocmdrdy:1;
679 + u32 atocmdtmo:1;
680 + u32 atocmdcrc:1;
681 + u32 dmaqempty:1;
682 + u32 sdioirq:1;
683 + u32 cmdrdy:1;
684 + u32 cmdtmo:1;
685 + u32 rspcrc:1;
686 + u32 csta:1;
687 + u32 xfercomp:1;
688 + u32 dxferdone:1;
689 + u32 dattmo:1;
690 + u32 datcrc:1;
691 + u32 atocmd19done:1;
692 + u32 pad2:15;
693 +} msdc_inten_reg;
694 +typedef struct {
695 + u32 rxcnt:8;
696 + u32 pad1:8;
697 + u32 txcnt:8;
698 + u32 pad2:7;
699 + u32 clr:1;
700 +} msdc_fifocs_reg;
701 +typedef struct {
702 + u32 val;
703 +} msdc_txdat_reg;
704 +typedef struct {
705 + u32 val;
706 +} msdc_rxdat_reg;
707 +typedef struct {
708 + u32 sdiowkup:1;
709 + u32 inswkup:1;
710 + u32 pad1:14;
711 + u32 buswidth:2;
712 + u32 pad2:1;
713 + u32 sdio:1;
714 + u32 sdioide:1;
715 + u32 intblkgap:1;
716 + u32 pad4:2;
717 + u32 dtoc:8;
718 +} sdc_cfg_reg;
719 +typedef struct {
720 + u32 cmd:6;
721 + u32 brk:1;
722 + u32 rsptyp:3;
723 + u32 pad1:1;
724 + u32 dtype:2;
725 + u32 rw:1;
726 + u32 stop:1;
727 + u32 goirq:1;
728 + u32 blklen:12;
729 + u32 atocmd:2;
730 + u32 volswth:1;
731 + u32 pad2:1;
732 +} sdc_cmd_reg;
733 +typedef struct {
734 + u32 arg;
735 +} sdc_arg_reg;
736 +typedef struct {
737 + u32 sdcbusy:1;
738 + u32 cmdbusy:1;
739 + u32 pad:29;
740 + u32 swrcmpl:1;
741 +} sdc_sts_reg;
742 +typedef struct {
743 + u32 val;
744 +} sdc_resp0_reg;
745 +typedef struct {
746 + u32 val;
747 +} sdc_resp1_reg;
748 +typedef struct {
749 + u32 val;
750 +} sdc_resp2_reg;
751 +typedef struct {
752 + u32 val;
753 +} sdc_resp3_reg;
754 +typedef struct {
755 + u32 num;
756 +} sdc_blknum_reg;
757 +typedef struct {
758 + u32 sts;
759 +} sdc_csts_reg;
760 +typedef struct {
761 + u32 sts;
762 +} sdc_cstsen_reg;
763 +typedef struct {
764 + u32 datcrcsts:8;
765 + u32 ddrcrcsts:4;
766 + u32 pad:20;
767 +} sdc_datcrcsts_reg;
768 +typedef struct {
769 + u32 bootstart:1;
770 + u32 bootstop:1;
771 + u32 bootmode:1;
772 + u32 pad1:9;
773 + u32 bootwaidly:3;
774 + u32 bootsupp:1;
775 + u32 pad2:16;
776 +} emmc_cfg0_reg;
777 +typedef struct {
778 + u32 bootcrctmc:16;
779 + u32 pad:4;
780 + u32 bootacktmc:12;
781 +} emmc_cfg1_reg;
782 +typedef struct {
783 + u32 bootcrcerr:1;
784 + u32 bootackerr:1;
785 + u32 bootdattmo:1;
786 + u32 bootacktmo:1;
787 + u32 bootupstate:1;
788 + u32 bootackrcv:1;
789 + u32 bootdatrcv:1;
790 + u32 pad:25;
791 +} emmc_sts_reg;
792 +typedef struct {
793 + u32 bootrst:1;
794 + u32 pad:31;
795 +} emmc_iocon_reg;
796 +typedef struct {
797 + u32 val;
798 +} msdc_acmd_resp_reg;
799 +typedef struct {
800 + u32 tunesel:4;
801 + u32 pad:28;
802 +} msdc_acmd19_trg_reg;
803 +typedef struct {
804 + u32 val;
805 +} msdc_acmd19_sts_reg;
806 +typedef struct {
807 + u32 addr;
808 +} msdc_dma_sa_reg;
809 +typedef struct {
810 + u32 addr;
811 +} msdc_dma_ca_reg;
812 +typedef struct {
813 + u32 start:1;
814 + u32 stop:1;
815 + u32 resume:1;
816 + u32 pad1:5;
817 + u32 mode:1;
818 + u32 pad2:1;
819 + u32 lastbuf:1;
820 + u32 pad3:1;
821 + u32 brustsz:3;
822 + u32 pad4:1;
823 + u32 xfersz:16;
824 +} msdc_dma_ctrl_reg;
825 +typedef struct {
826 + u32 status:1;
827 + u32 decsen:1;
828 + u32 pad1:2;
829 + u32 bdcsen:1;
830 + u32 gpdcsen:1;
831 + u32 pad2:26;
832 +} msdc_dma_cfg_reg;
833 +typedef struct {
834 + u32 sel:16;
835 + u32 pad2:16;
836 +} msdc_dbg_sel_reg;
837 +typedef struct {
838 + u32 val;
839 +} msdc_dbg_out_reg;
840 +typedef struct {
841 + u32 clkdrvn:3;
842 + u32 rsv0:1;
843 + u32 clkdrvp:3;
844 + u32 rsv1:1;
845 + u32 clksr:1;
846 + u32 rsv2:7;
847 + u32 clkpd:1;
848 + u32 clkpu:1;
849 + u32 clksmt:1;
850 + u32 clkies:1;
851 + u32 clktdsel:4;
852 + u32 clkrdsel:8;
853 +} msdc_pad_ctl0_reg;
854 +typedef struct {
855 + u32 cmddrvn:3;
856 + u32 rsv0:1;
857 + u32 cmddrvp:3;
858 + u32 rsv1:1;
859 + u32 cmdsr:1;
860 + u32 rsv2:7;
861 + u32 cmdpd:1;
862 + u32 cmdpu:1;
863 + u32 cmdsmt:1;
864 + u32 cmdies:1;
865 + u32 cmdtdsel:4;
866 + u32 cmdrdsel:8;
867 +} msdc_pad_ctl1_reg;
868 +typedef struct {
869 + u32 datdrvn:3;
870 + u32 rsv0:1;
871 + u32 datdrvp:3;
872 + u32 rsv1:1;
873 + u32 datsr:1;
874 + u32 rsv2:7;
875 + u32 datpd:1;
876 + u32 datpu:1;
877 + u32 datsmt:1;
878 + u32 daties:1;
879 + u32 dattdsel:4;
880 + u32 datrdsel:8;
881 +} msdc_pad_ctl2_reg;
882 +typedef struct {
883 + u32 wrrxdly:3;
884 + u32 pad1:5;
885 + u32 rdrxdly:8;
886 + u32 pad2:16;
887 +} msdc_pad_tune_reg;
888 +typedef struct {
889 + u32 dat0:5;
890 + u32 rsv0:3;
891 + u32 dat1:5;
892 + u32 rsv1:3;
893 + u32 dat2:5;
894 + u32 rsv2:3;
895 + u32 dat3:5;
896 + u32 rsv3:3;
897 +} msdc_dat_rddly0;
898 +typedef struct {
899 + u32 dat4:5;
900 + u32 rsv4:3;
901 + u32 dat5:5;
902 + u32 rsv5:3;
903 + u32 dat6:5;
904 + u32 rsv6:3;
905 + u32 dat7:5;
906 + u32 rsv7:3;
907 +} msdc_dat_rddly1;
908 +typedef struct {
909 + u32 dbg0sel:8;
910 + u32 dbg1sel:6;
911 + u32 pad1:2;
912 + u32 dbg2sel:6;
913 + u32 pad2:2;
914 + u32 dbg3sel:6;
915 + u32 pad3:2;
916 +} msdc_hw_dbg_reg;
917 +typedef struct {
918 + u32 val;
919 +} msdc_version_reg;
920 +typedef struct {
921 + u32 val;
922 +} msdc_eco_ver_reg;
923 +
924 +struct msdc_regs {
925 + msdc_cfg_reg msdc_cfg; /* base+0x00h */
926 + msdc_iocon_reg msdc_iocon; /* base+0x04h */
927 + msdc_ps_reg msdc_ps; /* base+0x08h */
928 + msdc_int_reg msdc_int; /* base+0x0ch */
929 + msdc_inten_reg msdc_inten; /* base+0x10h */
930 + msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
931 + msdc_txdat_reg msdc_txdat; /* base+0x18h */
932 + msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
933 + u32 rsv1[4];
934 + sdc_cfg_reg sdc_cfg; /* base+0x30h */
935 + sdc_cmd_reg sdc_cmd; /* base+0x34h */
936 + sdc_arg_reg sdc_arg; /* base+0x38h */
937 + sdc_sts_reg sdc_sts; /* base+0x3ch */
938 + sdc_resp0_reg sdc_resp0; /* base+0x40h */
939 + sdc_resp1_reg sdc_resp1; /* base+0x44h */
940 + sdc_resp2_reg sdc_resp2; /* base+0x48h */
941 + sdc_resp3_reg sdc_resp3; /* base+0x4ch */
942 + sdc_blknum_reg sdc_blknum; /* base+0x50h */
943 + u32 rsv2[1];
944 + sdc_csts_reg sdc_csts; /* base+0x58h */
945 + sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
946 + sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
947 + u32 rsv3[3];
948 + emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
949 + emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
950 + emmc_sts_reg emmc_sts; /* base+0x78h */
951 + emmc_iocon_reg emmc_iocon; /* base+0x7ch */
952 + msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
953 + msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
954 + msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
955 + u32 rsv4[1];
956 + msdc_dma_sa_reg dma_sa; /* base+0x90h */
957 + msdc_dma_ca_reg dma_ca; /* base+0x94h */
958 + msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
959 + msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
960 + msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
961 + msdc_dbg_out_reg dbg_out; /* base+0xa4h */
962 + u32 rsv5[2];
963 + u32 patch0; /* base+0xb0h */
964 + u32 patch1; /* base+0xb4h */
965 + u32 rsv6[10];
966 + msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
967 + msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
968 + msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
969 + msdc_pad_tune_reg pad_tune; /* base+0xech */
970 + msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
971 + msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
972 + msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
973 + u32 rsv7[1];
974 + msdc_version_reg version; /* base+0x100h */
975 + msdc_eco_ver_reg eco_ver; /* base+0x104h */
976 +};
977 +
978 +struct scatterlist_ex {
979 + u32 cmd;
980 + u32 arg;
981 + u32 sglen;
982 + struct scatterlist *sg;
983 +};
984 +
985 +#define DMA_FLAG_NONE (0x00000000)
986 +#define DMA_FLAG_EN_CHKSUM (0x00000001)
987 +#define DMA_FLAG_PAD_BLOCK (0x00000002)
988 +#define DMA_FLAG_PAD_DWORD (0x00000004)
989 +
990 +struct msdc_dma {
991 + u32 flags; /* flags */
992 + u32 xfersz; /* xfer size in bytes */
993 + u32 sglen; /* size of scatter list */
994 + u32 blklen; /* block size */
995 + struct scatterlist *sg; /* I/O scatter list */
996 + struct scatterlist_ex *esg; /* extended I/O scatter list */
997 + u8 mode; /* dma mode */
998 + u8 burstsz; /* burst size */
999 + u8 intr; /* dma done interrupt */
1000 + u8 padding; /* padding */
1001 + u32 cmd; /* enhanced mode command */
1002 + u32 arg; /* enhanced mode arg */
1003 + u32 rsp; /* enhanced mode command response */
1004 + u32 autorsp; /* auto command response */
1005 +
1006 + gpd_t *gpd; /* pointer to gpd array */
1007 + bd_t *bd; /* pointer to bd array */
1008 + dma_addr_t gpd_addr; /* the physical address of gpd array */
1009 + dma_addr_t bd_addr; /* the physical address of bd array */
1010 + u32 used_gpd; /* the number of used gpd elements */
1011 + u32 used_bd; /* the number of used bd elements */
1012 +};
1013 +
1014 +struct msdc_host
1015 +{
1016 + struct msdc_hw *hw;
1017 +
1018 + struct mmc_host *mmc; /* mmc structure */
1019 + struct mmc_command *cmd;
1020 + struct mmc_data *data;
1021 + struct mmc_request *mrq;
1022 + int cmd_rsp;
1023 + int cmd_rsp_done;
1024 + int cmd_r1b_done;
1025 +
1026 + int error;
1027 + spinlock_t lock; /* mutex */
1028 + struct semaphore sem;
1029 +
1030 + u32 blksz; /* host block size */
1031 + u32 base; /* host base address */
1032 + int id; /* host id */
1033 + int pwr_ref; /* core power reference count */
1034 +
1035 + u32 xfer_size; /* total transferred size */
1036 +
1037 + struct msdc_dma dma; /* dma channel */
1038 + u32 dma_addr; /* dma transfer address */
1039 + u32 dma_left_size; /* dma transfer left size */
1040 + u32 dma_xfer_size; /* dma transfer size in bytes */
1041 + int dma_xfer; /* dma transfer mode */
1042 +
1043 + u32 timeout_ns; /* data timeout ns */
1044 + u32 timeout_clks; /* data timeout clks */
1045 +
1046 + atomic_t abort; /* abort transfer */
1047 +
1048 + int irq; /* host interrupt */
1049 +
1050 + struct tasklet_struct card_tasklet;
1051 +
1052 + struct completion cmd_done;
1053 + struct completion xfer_done;
1054 + struct pm_message pm_state;
1055 +
1056 + u32 mclk; /* mmc subsystem clock */
1057 + u32 hclk; /* host clock speed */
1058 + u32 sclk; /* SD/MS clock speed */
1059 + u8 core_clkon; /* Host core clock on ? */
1060 + u8 card_clkon; /* Card clock on ? */
1061 + u8 core_power; /* core power */
1062 + u8 power_mode; /* host power mode */
1063 + u8 card_inserted; /* card inserted ? */
1064 + u8 suspend; /* host suspended ? */
1065 + u8 reserved;
1066 + u8 app_cmd; /* for app command */
1067 + u32 app_cmd_arg;
1068 + u64 starttime;
1069 +};
1070 +
1071 +static inline unsigned int uffs(unsigned int x)
1072 +{
1073 + unsigned int r = 1;
1074 +
1075 + if (!x)
1076 + return 0;
1077 + if (!(x & 0xffff)) {
1078 + x >>= 16;
1079 + r += 16;
1080 + }
1081 + if (!(x & 0xff)) {
1082 + x >>= 8;
1083 + r += 8;
1084 + }
1085 + if (!(x & 0xf)) {
1086 + x >>= 4;
1087 + r += 4;
1088 + }
1089 + if (!(x & 3)) {
1090 + x >>= 2;
1091 + r += 2;
1092 + }
1093 + if (!(x & 1)) {
1094 + x >>= 1;
1095 + r += 1;
1096 + }
1097 + return r;
1098 +}
1099 +#define sdr_read8(reg) __raw_readb(reg)
1100 +#define sdr_read16(reg) __raw_readw(reg)
1101 +#define sdr_read32(reg) __raw_readl(reg)
1102 +#define sdr_write8(reg,val) __raw_writeb(val,reg)
1103 +#define sdr_write16(reg,val) __raw_writew(val,reg)
1104 +#define sdr_write32(reg,val) __raw_writel(val,reg)
1105 +
1106 +#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
1107 +#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
1108 +
1109 +#define sdr_set_field(reg,field,val) \
1110 + do { \
1111 + volatile unsigned int tv = sdr_read32(reg); \
1112 + tv &= ~(field); \
1113 + tv |= ((val) << (uffs((unsigned int)field) - 1)); \
1114 + sdr_write32(reg,tv); \
1115 + } while(0)
1116 +#define sdr_get_field(reg,field,val) \
1117 + do { \
1118 + volatile unsigned int tv = sdr_read32(reg); \
1119 + val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
1120 + } while(0)
1121 +
1122 +#endif
1123 +
1124 diff --git a/drivers/mmc/host/sdhci-mt7620.c b/drivers/mmc/host/sdhci-mt7620.c
1125 new file mode 100644
1126 index 0000000..a3cb5e4
1127 --- /dev/null
1128 +++ b/drivers/mmc/host/sdhci-mt7620.c
1129 @@ -0,0 +1,2314 @@
1130 +/* Copyright Statement:
1131 + *
1132 + * This software/firmware and related documentation ("MediaTek Software") are
1133 + * protected under relevant copyright laws. The information contained herein
1134 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
1135 + * Without the prior written permission of MediaTek inc. and/or its licensors,
1136 + * any reproduction, modification, use or disclosure of MediaTek Software,
1137 + * and information contained herein, in whole or in part, shall be strictly prohibited.
1138 + *
1139 + * MediaTek Inc. (C) 2010. All rights reserved.
1140 + *
1141 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1142 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1143 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
1144 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1145 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1146 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1147 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1148 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1149 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
1150 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
1151 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
1152 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
1153 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
1154 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
1155 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1156 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1157 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
1158 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1159 + *
1160 + * The following software/firmware and/or related documentation ("MediaTek Software")
1161 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
1162 + * applicable license agreements with MediaTek Inc.
1163 + */
1164 +
1165 +#include <linux/module.h>
1166 +#include <linux/moduleparam.h>
1167 +#include <linux/init.h>
1168 +#include <linux/spinlock.h>
1169 +#include <linux/timer.h>
1170 +#include <linux/ioport.h>
1171 +#include <linux/device.h>
1172 +#include <linux/platform_device.h>
1173 +#include <linux/of_platform.h>
1174 +#include <linux/interrupt.h>
1175 +#include <linux/delay.h>
1176 +#include <linux/blkdev.h>
1177 +#include <linux/slab.h>
1178 +#include <linux/mmc/host.h>
1179 +#include <linux/mmc/card.h>
1180 +#include <linux/mmc/core.h>
1181 +#include <linux/mmc/mmc.h>
1182 +#include <linux/mmc/sd.h>
1183 +#include <linux/mmc/sdio.h>
1184 +#include <linux/dma-mapping.h>
1185 +
1186 +#include <linux/types.h>
1187 +#include <linux/kernel.h>
1188 +#include <linux/version.h>
1189 +#include <linux/pm.h>
1190 +
1191 +#define MSDC_SMPL_FALLING (1)
1192 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
1193 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
1194 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
1195 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
1196 +#define MSDC_HIGHSPEED (1 << 7)
1197 +
1198 +#define IRQ_SDC 22
1199 +
1200 +#include <asm/dma.h>
1201 +
1202 +#include "mt6575_sd.h"
1203 +
1204 +#define DRV_NAME "mtk-sd"
1205 +
1206 +#define HOST_MAX_NUM (1) /* +/- by chhung */
1207 +
1208 +#define HOST_MAX_MCLK (48000000) /* +/- by chhung */
1209 +#define HOST_MIN_MCLK (260000)
1210 +
1211 +#define HOST_MAX_BLKSZ (2048)
1212 +
1213 +#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
1214 +
1215 +#define GPIO_PULL_DOWN (0)
1216 +#define GPIO_PULL_UP (1)
1217 +
1218 +#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
1219 +#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
1220 +
1221 +#define CMD_TIMEOUT (HZ/10) /* 100ms */
1222 +#define DAT_TIMEOUT (HZ/2 * 5) /* 500ms x5 */
1223 +
1224 +#define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
1225 +
1226 +#define MAX_GPD_NUM (1 + 1) /* one null gpd */
1227 +#define MAX_BD_NUM (1024)
1228 +#define MAX_BD_PER_GPD (MAX_BD_NUM)
1229 +
1230 +#define MAX_HW_SGMTS (MAX_BD_NUM)
1231 +#define MAX_PHY_SGMTS (MAX_BD_NUM)
1232 +#define MAX_SGMT_SZ (MAX_DMA_CNT)
1233 +#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
1234 +
1235 +#ifdef MT6575_SD_DEBUG
1236 +static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
1237 +#endif
1238 +
1239 +//=================================
1240 +#define PERI_MSDC0_PDN (15)
1241 +//#define PERI_MSDC1_PDN (16)
1242 +//#define PERI_MSDC2_PDN (17)
1243 +//#define PERI_MSDC3_PDN (18)
1244 +
1245 +struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
1246 +
1247 +struct msdc_hw msdc0_hw = {
1248 + .clk_src = 0,
1249 + .cmd_edge = MSDC_SMPL_FALLING,
1250 + .data_edge = MSDC_SMPL_FALLING,
1251 + .clk_drv = 4,
1252 + .cmd_drv = 4,
1253 + .dat_drv = 4,
1254 + .data_pins = 4,
1255 + .data_offset = 0,
1256 + .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
1257 +};
1258 +
1259 +static struct resource mtk_sd_resources[] = {
1260 + [0] = {
1261 + .start = 0xb0130000,
1262 + .end = 0xb0133fff,
1263 + .flags = IORESOURCE_MEM,
1264 + },
1265 + [1] = {
1266 + .start = IRQ_SDC, /*FIXME*/
1267 + .end = IRQ_SDC, /*FIXME*/
1268 + .flags = IORESOURCE_IRQ,
1269 + },
1270 +};
1271 +
1272 +static struct platform_device mtk_sd_device = {
1273 + .name = "mtk-sd",
1274 + .id = 0,
1275 + .num_resources = ARRAY_SIZE(mtk_sd_resources),
1276 + .resource = mtk_sd_resources,
1277 +};
1278 +/* end of +++ */
1279 +
1280 +static int msdc_rsp[] = {
1281 + 0, /* RESP_NONE */
1282 + 1, /* RESP_R1 */
1283 + 2, /* RESP_R2 */
1284 + 3, /* RESP_R3 */
1285 + 4, /* RESP_R4 */
1286 + 1, /* RESP_R5 */
1287 + 1, /* RESP_R6 */
1288 + 1, /* RESP_R7 */
1289 + 7, /* RESP_R1b */
1290 +};
1291 +
1292 +/* For Inhanced DMA */
1293 +#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
1294 + do { \
1295 + ((gpd_t*)gpd)->extlen = extlen; \
1296 + ((gpd_t*)gpd)->cmd = cmd; \
1297 + ((gpd_t*)gpd)->arg = arg; \
1298 + ((gpd_t*)gpd)->blknum = blknum; \
1299 + }while(0)
1300 +
1301 +#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
1302 + do { \
1303 + BUG_ON(dlen > 0xFFFFUL); \
1304 + ((bd_t*)bd)->blkpad = blkpad; \
1305 + ((bd_t*)bd)->dwpad = dwpad; \
1306 + ((bd_t*)bd)->ptr = (void*)dptr; \
1307 + ((bd_t*)bd)->buflen = dlen; \
1308 + }while(0)
1309 +
1310 +#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
1311 +#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
1312 +#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
1313 +#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
1314 +#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
1315 +#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
1316 +
1317 +
1318 +#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
1319 +#define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
1320 +
1321 +#define msdc_retry(expr,retry,cnt) \
1322 + do { \
1323 + int backup = cnt; \
1324 + while (retry) { \
1325 + if (!(expr)) break; \
1326 + if (cnt-- == 0) { \
1327 + retry--; mdelay(1); cnt = backup; \
1328 + } \
1329 + } \
1330 + WARN_ON(retry == 0); \
1331 + } while(0)
1332 +
1333 +#if 0 /* +/- chhung */
1334 +#define msdc_reset() \
1335 + do { \
1336 + int retry = 3, cnt = 1000; \
1337 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
1338 + dsb(); \
1339 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
1340 + } while(0)
1341 +#else
1342 +#define msdc_reset() \
1343 + do { \
1344 + int retry = 3, cnt = 1000; \
1345 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
1346 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
1347 + } while(0)
1348 +#endif /* end of +/- */
1349 +
1350 +#define msdc_clr_int() \
1351 + do { \
1352 + volatile u32 val = sdr_read32(MSDC_INT); \
1353 + sdr_write32(MSDC_INT, val); \
1354 + } while(0)
1355 +
1356 +#define msdc_clr_fifo() \
1357 + do { \
1358 + int retry = 3, cnt = 1000; \
1359 + sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
1360 + msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
1361 + } while(0)
1362 +
1363 +#define msdc_irq_save(val) \
1364 + do { \
1365 + val = sdr_read32(MSDC_INTEN); \
1366 + sdr_clr_bits(MSDC_INTEN, val); \
1367 + } while(0)
1368 +
1369 +#define msdc_irq_restore(val) \
1370 + do { \
1371 + sdr_set_bits(MSDC_INTEN, val); \
1372 + } while(0)
1373 +
1374 +/* clock source for host: global */
1375 +static u32 hclks[] = {48000000}; /* +/- by chhung */
1376 +
1377 +//============================================
1378 +// the power for msdc host controller: global
1379 +// always keep the VMC on.
1380 +//============================================
1381 +#define msdc_vcore_on(host) \
1382 + do { \
1383 + printk("[+]VMC ref. count<%d>\n", ++host->pwr_ref); \
1384 + (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
1385 + } while (0)
1386 +#define msdc_vcore_off(host) \
1387 + do { \
1388 + printk("[-]VMC ref. count<%d>\n", --host->pwr_ref); \
1389 + (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
1390 + } while (0)
1391 +
1392 +//====================================
1393 +// the vdd output for card: global
1394 +// always keep the VMCH on.
1395 +//====================================
1396 +#define msdc_vdd_on(host) \
1397 + do { \
1398 + (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
1399 + } while (0)
1400 +#define msdc_vdd_off(host) \
1401 + do { \
1402 + (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
1403 + } while (0)
1404 +
1405 +#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
1406 +#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
1407 +
1408 +#define sdc_send_cmd(cmd,arg) \
1409 + do { \
1410 + sdr_write32(SDC_ARG, (arg)); \
1411 + sdr_write32(SDC_CMD, (cmd)); \
1412 + } while(0)
1413 +
1414 +// can modify to read h/w register.
1415 +//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
1416 +#define is_card_present(h) (((struct msdc_host*)(h))->card_inserted)
1417 +
1418 +/* +++ chhung */
1419 +#ifndef __ASSEMBLY__
1420 +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
1421 +#else
1422 +#define PHYSADDR(a) ((a) & 0x1fffffff)
1423 +#endif
1424 +/* end of +++ */
1425 +static unsigned int msdc_do_command(struct msdc_host *host,
1426 + struct mmc_command *cmd,
1427 + int tune,
1428 + unsigned long timeout);
1429 +
1430 +static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
1431 +
1432 +#ifdef MT6575_SD_DEBUG
1433 +static void msdc_dump_card_status(struct msdc_host *host, u32 status)
1434 +{
1435 + static char *state[] = {
1436 + "Idle", /* 0 */
1437 + "Ready", /* 1 */
1438 + "Ident", /* 2 */
1439 + "Stby", /* 3 */
1440 + "Tran", /* 4 */
1441 + "Data", /* 5 */
1442 + "Rcv", /* 6 */
1443 + "Prg", /* 7 */
1444 + "Dis", /* 8 */
1445 + "Reserved", /* 9 */
1446 + "Reserved", /* 10 */
1447 + "Reserved", /* 11 */
1448 + "Reserved", /* 12 */
1449 + "Reserved", /* 13 */
1450 + "Reserved", /* 14 */
1451 + "I/O mode", /* 15 */
1452 + };
1453 + if (status & R1_OUT_OF_RANGE)
1454 + printk("[CARD_STATUS] Out of Range\n");
1455 + if (status & R1_ADDRESS_ERROR)
1456 + printk("[CARD_STATUS] Address Error\n");
1457 + if (status & R1_BLOCK_LEN_ERROR)
1458 + printk("[CARD_STATUS] Block Len Error\n");
1459 + if (status & R1_ERASE_SEQ_ERROR)
1460 + printk("[CARD_STATUS] Erase Seq Error\n");
1461 + if (status & R1_ERASE_PARAM)
1462 + printk("[CARD_STATUS] Erase Param\n");
1463 + if (status & R1_WP_VIOLATION)
1464 + printk("[CARD_STATUS] WP Violation\n");
1465 + if (status & R1_CARD_IS_LOCKED)
1466 + printk("[CARD_STATUS] Card is Locked\n");
1467 + if (status & R1_LOCK_UNLOCK_FAILED)
1468 + printk("[CARD_STATUS] Lock/Unlock Failed\n");
1469 + if (status & R1_COM_CRC_ERROR)
1470 + printk("[CARD_STATUS] Command CRC Error\n");
1471 + if (status & R1_ILLEGAL_COMMAND)
1472 + printk("[CARD_STATUS] Illegal Command\n");
1473 + if (status & R1_CARD_ECC_FAILED)
1474 + printk("[CARD_STATUS] Card ECC Failed\n");
1475 + if (status & R1_CC_ERROR)
1476 + printk("[CARD_STATUS] CC Error\n");
1477 + if (status & R1_ERROR)
1478 + printk("[CARD_STATUS] Error\n");
1479 + if (status & R1_UNDERRUN)
1480 + printk("[CARD_STATUS] Underrun\n");
1481 + if (status & R1_OVERRUN)
1482 + printk("[CARD_STATUS] Overrun\n");
1483 + if (status & R1_CID_CSD_OVERWRITE)
1484 + printk("[CARD_STATUS] CID/CSD Overwrite\n");
1485 + if (status & R1_WP_ERASE_SKIP)
1486 + printk("[CARD_STATUS] WP Eraser Skip\n");
1487 + if (status & R1_CARD_ECC_DISABLED)
1488 + printk("[CARD_STATUS] Card ECC Disabled\n");
1489 + if (status & R1_ERASE_RESET)
1490 + printk("[CARD_STATUS] Erase Reset\n");
1491 + if (status & R1_READY_FOR_DATA)
1492 + printk("[CARD_STATUS] Ready for Data\n");
1493 + if (status & R1_SWITCH_ERROR)
1494 + printk("[CARD_STATUS] Switch error\n");
1495 + if (status & R1_APP_CMD)
1496 + printk("[CARD_STATUS] App Command\n");
1497 +
1498 + printk("[CARD_STATUS] '%s' State\n", state[R1_CURRENT_STATE(status)]);
1499 +}
1500 +
1501 +static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
1502 +{
1503 + if (resp & (1 << 7))
1504 + printk("[OCR] Low Voltage Range\n");
1505 + if (resp & (1 << 15))
1506 + printk("[OCR] 2.7-2.8 volt\n");
1507 + if (resp & (1 << 16))
1508 + printk("[OCR] 2.8-2.9 volt\n");
1509 + if (resp & (1 << 17))
1510 + printk("[OCR] 2.9-3.0 volt\n");
1511 + if (resp & (1 << 18))
1512 + printk("[OCR] 3.0-3.1 volt\n");
1513 + if (resp & (1 << 19))
1514 + printk("[OCR] 3.1-3.2 volt\n");
1515 + if (resp & (1 << 20))
1516 + printk("[OCR] 3.2-3.3 volt\n");
1517 + if (resp & (1 << 21))
1518 + printk("[OCR] 3.3-3.4 volt\n");
1519 + if (resp & (1 << 22))
1520 + printk("[OCR] 3.4-3.5 volt\n");
1521 + if (resp & (1 << 23))
1522 + printk("[OCR] 3.5-3.6 volt\n");
1523 + if (resp & (1 << 24))
1524 + printk("[OCR] Switching to 1.8V Accepted (S18A)\n");
1525 + if (resp & (1 << 30))
1526 + printk("[OCR] Card Capacity Status (CCS)\n");
1527 + if (resp & (1 << 31))
1528 + printk("[OCR] Card Power Up Status (Idle)\n");
1529 + else
1530 + printk("[OCR] Card Power Up Status (Busy)\n");
1531 +}
1532 +
1533 +static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
1534 +{
1535 + u32 status = (((resp >> 15) & 0x1) << 23) |
1536 + (((resp >> 14) & 0x1) << 22) |
1537 + (((resp >> 13) & 0x1) << 19) |
1538 + (resp & 0x1fff);
1539 +
1540 + printk("[RCA] 0x%.4x\n", resp >> 16);
1541 +
1542 + msdc_dump_card_status(host, status);
1543 +}
1544 +
1545 +static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
1546 +{
1547 + u32 flags = (resp >> 8) & 0xFF;
1548 + char *state[] = {"DIS", "CMD", "TRN", "RFU"};
1549 +
1550 + if (flags & (1 << 7))
1551 + printk("[IO] COM_CRC_ERR\n");
1552 + if (flags & (1 << 6))
1553 + printk("[IO] Illgal command\n");
1554 + if (flags & (1 << 3))
1555 + printk("[IO] Error\n");
1556 + if (flags & (1 << 2))
1557 + printk("[IO] RFU\n");
1558 + if (flags & (1 << 1))
1559 + printk("[IO] Function number error\n");
1560 + if (flags & (1 << 0))
1561 + printk("[IO] Out of range\n");
1562 +
1563 + printk("[IO] State: %s, Data:0x%x\n", state[(resp >> 12) & 0x3], resp & 0xFF);
1564 +}
1565 +#endif
1566 +
1567 +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
1568 +{
1569 + u32 base = host->base;
1570 + u32 timeout, clk_ns;
1571 +
1572 + host->timeout_ns = ns;
1573 + host->timeout_clks = clks;
1574 +
1575 + clk_ns = 1000000000UL / host->sclk;
1576 + timeout = ns / clk_ns + clks;
1577 + timeout = timeout >> 16; /* in 65536 sclk cycle unit */
1578 + timeout = timeout > 1 ? timeout - 1 : 0;
1579 + timeout = timeout > 255 ? 255 : timeout;
1580 +
1581 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
1582 +
1583 +/* printk("Set read data timeout: %dns %dclks -> %d x 65536 cycles\n",
1584 + ns, clks, timeout + 1);*/
1585 +}
1586 +
1587 +static void msdc_eirq_sdio(void *data)
1588 +{
1589 + struct msdc_host *host = (struct msdc_host *)data;
1590 +
1591 +// printk("SDIO EINT\n");
1592 +
1593 + mmc_signal_sdio_irq(host->mmc);
1594 +}
1595 +
1596 +static void msdc_eirq_cd(void *data)
1597 +{
1598 + struct msdc_host *host = (struct msdc_host *)data;
1599 +
1600 +// printk("CD EINT\n");
1601 +
1602 + tasklet_hi_schedule(&host->card_tasklet);
1603 +}
1604 +
1605 +static void msdc_tasklet_card(unsigned long arg)
1606 +{
1607 + struct msdc_host *host = (struct msdc_host *)arg;
1608 + struct msdc_hw *hw = host->hw;
1609 + u32 base = host->base;
1610 + u32 inserted;
1611 + u32 status = 0;
1612 +
1613 + spin_lock(&host->lock);
1614 +
1615 + if (hw->get_cd_status) {
1616 + inserted = hw->get_cd_status();
1617 + } else {
1618 + status = sdr_read32(MSDC_PS);
1619 + inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
1620 + }
1621 +
1622 + host->card_inserted = inserted;
1623 +
1624 + if (!host->suspend) {
1625 + host->mmc->f_max = HOST_MAX_MCLK;
1626 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
1627 + }
1628 +
1629 +// printk("card found<%s>\n", inserted ? "inserted" : "removed");
1630 +
1631 + spin_unlock(&host->lock);
1632 +}
1633 +
1634 +static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
1635 +{
1636 + u32 base = host->base;
1637 + u32 hclk = host->hclk;
1638 + u32 mode, flags, div, sclk;
1639 +
1640 + if (!hz) {
1641 +// printk("set mclk to 0!!!\n");
1642 + msdc_reset();
1643 + return;
1644 + }
1645 +
1646 + msdc_irq_save(flags);
1647 +
1648 + if (ddr) {
1649 + mode = 0x2;
1650 + if (hz >= (hclk >> 2)) {
1651 + div = 1;
1652 + sclk = hclk >> 2;
1653 + } else {
1654 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
1655 + sclk = (hclk >> 2) / div;
1656 + }
1657 + } else if (hz >= hclk) {
1658 + mode = 0x1;
1659 + div = 0;
1660 + sclk = hclk;
1661 + } else {
1662 + mode = 0x0;
1663 + if (hz >= (hclk >> 1)) {
1664 + div = 0;
1665 + sclk = hclk >> 1;
1666 + } else {
1667 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
1668 + sclk = (hclk >> 2) / div;
1669 + }
1670 + }
1671 +
1672 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
1673 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
1674 +
1675 + while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
1676 +
1677 + host->sclk = sclk;
1678 + host->mclk = hz;
1679 + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
1680 +
1681 +/* printk("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>\n",
1682 + hz / 1000, hclk / 1000, sclk / 1000);
1683 +*/
1684 + msdc_irq_restore(flags);
1685 +}
1686 +
1687 +static void msdc_abort_data(struct msdc_host *host)
1688 +{
1689 + u32 base = host->base;
1690 + struct mmc_command *stop = host->mrq->stop;
1691 +
1692 +// printk("Need to Abort. dma<%d>\n", host->dma_xfer);
1693 +
1694 + msdc_reset();
1695 + msdc_clr_fifo();
1696 + msdc_clr_int();
1697 +
1698 + if (stop) {
1699 +// printk("stop when abort CMD<%d>\n", stop->opcode);
1700 + msdc_do_command(host, stop, 0, CMD_TIMEOUT);
1701 + }
1702 +}
1703 +
1704 +static unsigned int msdc_command_start(struct msdc_host *host,
1705 + struct mmc_command *cmd, int tune, unsigned long timeout)
1706 +{
1707 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
1708 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
1709 + MSDC_INT_ACMD19_DONE;
1710 + u32 base = host->base;
1711 + u32 opcode = cmd->opcode;
1712 + u32 rawcmd;
1713 + u32 resp;
1714 + unsigned long tmo;
1715 +
1716 + if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
1717 + resp = RESP_R3;
1718 + else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
1719 + resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
1720 + else if (opcode == MMC_FAST_IO)
1721 + resp = RESP_R4;
1722 + else if (opcode == MMC_GO_IRQ_STATE)
1723 + resp = RESP_R5;
1724 + else if (opcode == MMC_SELECT_CARD)
1725 + resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
1726 + else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
1727 + resp = RESP_R1;
1728 + else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
1729 + resp = RESP_R1;
1730 + else {
1731 + switch (mmc_resp_type(cmd)) {
1732 + case MMC_RSP_R1:
1733 + resp = RESP_R1;
1734 + break;
1735 + case MMC_RSP_R1B:
1736 + resp = RESP_R1B;
1737 + break;
1738 + case MMC_RSP_R2:
1739 + resp = RESP_R2;
1740 + break;
1741 + case MMC_RSP_R3:
1742 + resp = RESP_R3;
1743 + break;
1744 + case MMC_RSP_NONE:
1745 + default:
1746 + resp = RESP_NONE;
1747 + break;
1748 + }
1749 + }
1750 +
1751 + cmd->error = 0;
1752 + rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
1753 +
1754 + if (opcode == MMC_READ_MULTIPLE_BLOCK) {
1755 + rawcmd |= (2 << 11);
1756 + } else if (opcode == MMC_READ_SINGLE_BLOCK) {
1757 + rawcmd |= (1 << 11);
1758 + } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
1759 + rawcmd |= ((2 << 11) | (1 << 13));
1760 + } else if (opcode == MMC_WRITE_BLOCK) {
1761 + rawcmd |= ((1 << 11) | (1 << 13));
1762 + } else if (opcode == SD_IO_RW_EXTENDED) {
1763 + if (cmd->data->flags & MMC_DATA_WRITE)
1764 + rawcmd |= (1 << 13);
1765 + if (cmd->data->blocks > 1)
1766 + rawcmd |= (2 << 11);
1767 + else
1768 + rawcmd |= (1 << 11);
1769 + } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
1770 + rawcmd |= (1 << 14);
1771 + } else if ((opcode == SD_APP_SEND_SCR) ||
1772 + (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
1773 + (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
1774 + (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
1775 + (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
1776 + rawcmd |= (1 << 11);
1777 + } else if (opcode == MMC_STOP_TRANSMISSION) {
1778 + rawcmd |= (1 << 14);
1779 + rawcmd &= ~(0x0FFF << 16);
1780 + }
1781 +
1782 +// printk("CMD<%d><0x%.8x> Arg<0x%.8x>\n", opcode , rawcmd, cmd->arg);
1783 +
1784 + tmo = jiffies + timeout;
1785 +
1786 + if (opcode == MMC_SEND_STATUS) {
1787 + for (;;) {
1788 + if (!sdc_is_cmd_busy())
1789 + break;
1790 +
1791 + if (time_after(jiffies, tmo)) {
1792 + //printk("XXX cmd_busy timeout: before CMD<%d>\n", opcode);
1793 + cmd->error = (unsigned int)-ETIMEDOUT;
1794 + msdc_reset();
1795 + goto end;
1796 + }
1797 + }
1798 + } else {
1799 + for (;;) {
1800 + if (!sdc_is_busy())
1801 + break;
1802 + if (time_after(jiffies, tmo)) {
1803 + //printk("XXX sdc_busy timeout: before CMD<%d>\n", opcode);
1804 + cmd->error = (unsigned int)-ETIMEDOUT;
1805 + msdc_reset();
1806 + goto end;
1807 + }
1808 + }
1809 + }
1810 +
1811 + //BUG_ON(in_interrupt());
1812 + host->cmd = cmd;
1813 + host->cmd_rsp = resp;
1814 + init_completion(&host->cmd_done);
1815 + sdr_set_bits(MSDC_INTEN, wints);
1816 + sdc_send_cmd(rawcmd, cmd->arg);
1817 +
1818 +end:
1819 + return cmd->error;
1820 +}
1821 +
1822 +static unsigned int msdc_command_resp(struct msdc_host *host, struct mmc_command *cmd,
1823 + int tune, unsigned long timeout)
1824 +{
1825 + u32 base = host->base;
1826 + //u32 opcode = cmd->opcode;
1827 + u32 resp;
1828 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
1829 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
1830 + MSDC_INT_ACMD19_DONE;
1831 +
1832 + resp = host->cmd_rsp;
1833 +
1834 + BUG_ON(in_interrupt());
1835 + spin_unlock(&host->lock);
1836 + if (!wait_for_completion_timeout(&host->cmd_done, 10*timeout)) {
1837 + //printk("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>\n", opcode, cmd->arg);
1838 + cmd->error = (unsigned int)-ETIMEDOUT;
1839 + msdc_reset();
1840 + }
1841 + spin_lock(&host->lock);
1842 +
1843 + sdr_clr_bits(MSDC_INTEN, wints);
1844 + host->cmd = NULL;
1845 +
1846 + if (!tune)
1847 + return cmd->error;
1848 +
1849 + /* memory card CRC */
1850 + if (host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
1851 + if (sdr_read32(SDC_CMD) & 0x1800) {
1852 + msdc_abort_data(host);
1853 + } else {
1854 + msdc_reset();
1855 + msdc_clr_fifo();
1856 + msdc_clr_int();
1857 + }
1858 + cmd->error = msdc_tune_cmdrsp(host,cmd);
1859 + }
1860 +
1861 + return cmd->error;
1862 +}
1863 +
1864 +static unsigned int msdc_do_command(struct msdc_host *host, struct mmc_command *cmd,
1865 + int tune, unsigned long timeout)
1866 +{
1867 + if (!msdc_command_start(host, cmd, tune, timeout))
1868 + msdc_command_resp(host, cmd, tune, timeout);
1869 +
1870 + //printk(" return<%d> resp<0x%.8x>\n", cmd->error, cmd->resp[0]);
1871 + return cmd->error;
1872 +}
1873 +
1874 +static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
1875 +{
1876 + u32 base = host->base;
1877 + int ret = 0;
1878 +
1879 + if (atomic_read(&host->abort))
1880 + ret = 1;
1881 +
1882 + if (time_after(jiffies, tmo)) {
1883 + data->error = (unsigned int)-ETIMEDOUT;
1884 + //printk("XXX PIO Data Timeout: CMD<%d>\n", host->mrq->cmd->opcode);
1885 + ret = 1;
1886 + }
1887 +
1888 + if (ret) {
1889 + msdc_reset();
1890 + msdc_clr_fifo();
1891 + msdc_clr_int();
1892 + //printk("msdc pio find abort\n");
1893 + }
1894 +
1895 + return ret;
1896 +}
1897 +
1898 +static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
1899 +{
1900 + struct scatterlist *sg = data->sg;
1901 + u32 base = host->base;
1902 + u32 num = data->sg_len;
1903 + u32 *ptr;
1904 + u8 *u8ptr;
1905 + u32 left;
1906 + u32 count, size = 0;
1907 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1908 + unsigned long tmo = jiffies + DAT_TIMEOUT;
1909 +
1910 + sdr_set_bits(MSDC_INTEN, wints);
1911 + while (num) {
1912 + left = sg_dma_len(sg);
1913 + ptr = sg_virt(sg);
1914 + while (left) {
1915 + if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
1916 + count = MSDC_FIFO_THD >> 2;
1917 + do {
1918 + *ptr++ = msdc_fifo_read32();
1919 + } while (--count);
1920 + left -= MSDC_FIFO_THD;
1921 + } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
1922 + while (left > 3) {
1923 + *ptr++ = msdc_fifo_read32();
1924 + left -= 4;
1925 + }
1926 +
1927 + u8ptr = (u8 *)ptr;
1928 + while(left) {
1929 + * u8ptr++ = msdc_fifo_read8();
1930 + left--;
1931 + }
1932 + }
1933 +
1934 + if (msdc_pio_abort(host, data, tmo))
1935 + goto end;
1936 + }
1937 + size += sg_dma_len(sg);
1938 + sg = sg_next(sg); num--;
1939 + }
1940 +end:
1941 + data->bytes_xfered += size;
1942 + //printk(" PIO Read<%d>bytes\n", size);
1943 +
1944 + sdr_clr_bits(MSDC_INTEN, wints);
1945 + if(data->error)
1946 + printk("read pio data->error<%d> left<%d> size<%d>\n", data->error, left, size);
1947 +
1948 + return data->error;
1949 +}
1950 +
1951 +static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
1952 +{
1953 + u32 base = host->base;
1954 + struct scatterlist *sg = data->sg;
1955 + u32 num = data->sg_len;
1956 + u32 *ptr;
1957 + u8 *u8ptr;
1958 + u32 left;
1959 + u32 count, size = 0;
1960 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
1961 + unsigned long tmo = jiffies + DAT_TIMEOUT;
1962 +
1963 + sdr_set_bits(MSDC_INTEN, wints);
1964 + while (num) {
1965 + left = sg_dma_len(sg);
1966 + ptr = sg_virt(sg);
1967 +
1968 + while (left) {
1969 + if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
1970 + count = MSDC_FIFO_SZ >> 2;
1971 + do {
1972 + msdc_fifo_write32(*ptr); ptr++;
1973 + } while (--count);
1974 + left -= MSDC_FIFO_SZ;
1975 + } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
1976 + while (left > 3) {
1977 + msdc_fifo_write32(*ptr); ptr++;
1978 + left -= 4;
1979 + }
1980 +
1981 + u8ptr = (u8*)ptr;
1982 + while( left) {
1983 + msdc_fifo_write8(*u8ptr);
1984 + u8ptr++;
1985 + left--;
1986 + }
1987 + }
1988 +
1989 + if (msdc_pio_abort(host, data, tmo))
1990 + goto end;
1991 + }
1992 + size += sg_dma_len(sg);
1993 + sg = sg_next(sg); num--;
1994 + }
1995 +end:
1996 + data->bytes_xfered += size;
1997 + //printk(" PIO Write<%d>bytes\n", size);
1998 + if(data->error)
1999 + printk("write pio data->error<%d>\n", data->error);
2000 +
2001 + sdr_clr_bits(MSDC_INTEN, wints);
2002 +
2003 + return data->error;
2004 +}
2005 +
2006 +static void msdc_dma_start(struct msdc_host *host)
2007 +{
2008 + u32 base = host->base;
2009 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
2010 +
2011 + sdr_set_bits(MSDC_INTEN, wints);
2012 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
2013 +
2014 + //printk("DMA start\n");
2015 +}
2016 +
2017 +static void msdc_dma_stop(struct msdc_host *host)
2018 +{
2019 + u32 base = host->base;
2020 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
2021 +
2022 + //printk("DMA status: 0x%.8x\n",sdr_read32(MSDC_DMA_CFG));
2023 +
2024 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
2025 + while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
2026 + sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
2027 +
2028 + //printk("DMA stop\n");
2029 +}
2030 +
2031 +static u8 msdc_dma_calcs(u8 *buf, u32 len)
2032 +{
2033 + u32 i, sum = 0;
2034 +
2035 + for (i = 0; i < len; i++)
2036 + sum += buf[i];
2037 +
2038 + return 0xFF - (u8)sum;
2039 +}
2040 +
2041 +static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
2042 +{
2043 + u32 base = host->base;
2044 + u32 sglen = dma->sglen;
2045 + u32 j, num, bdlen;
2046 + u8 blkpad, dwpad, chksum;
2047 + struct scatterlist *sg = dma->sg;
2048 + gpd_t *gpd;
2049 + bd_t *bd;
2050 +
2051 + switch (dma->mode) {
2052 + case MSDC_MODE_DMA_BASIC:
2053 + BUG_ON(dma->xfersz > 65535);
2054 + BUG_ON(dma->sglen != 1);
2055 + sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
2056 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
2057 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
2058 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
2059 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
2060 + break;
2061 +
2062 + case MSDC_MODE_DMA_DESC:
2063 + blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
2064 + dwpad = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
2065 + chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
2066 +
2067 + num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
2068 + BUG_ON(num !=1 );
2069 +
2070 + gpd = dma->gpd;
2071 + bd = dma->bd;
2072 + bdlen = sglen;
2073 +
2074 + gpd->hwo = 1; /* hw will clear it */
2075 + gpd->bdp = 1;
2076 + gpd->chksum = 0; /* need to clear first. */
2077 + gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
2078 +
2079 + for (j = 0; j < bdlen; j++) {
2080 + msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
2081 + if( j == bdlen - 1)
2082 + bd[j].eol = 1;
2083 + else
2084 + bd[j].eol = 0;
2085 + bd[j].chksum = 0; /* checksume need to clear first */
2086 + bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
2087 + sg++;
2088 + }
2089 +
2090 + dma->used_gpd += 2;
2091 + dma->used_bd += bdlen;
2092 +
2093 + sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
2094 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
2095 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
2096 + sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
2097 + break;
2098 + }
2099 +
2100 +// printk("DMA_CTRL = 0x%x\n", sdr_read32(MSDC_DMA_CTRL));
2101 +// printk("DMA_CFG = 0x%x\n", sdr_read32(MSDC_DMA_CFG));
2102 +// printk("DMA_SA = 0x%x\n", sdr_read32(MSDC_DMA_SA));
2103 +
2104 + return 0;
2105 +}
2106 +
2107 +static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
2108 + struct scatterlist *sg, unsigned int sglen)
2109 +{
2110 + BUG_ON(sglen > MAX_BD_NUM);
2111 +
2112 + dma->sg = sg;
2113 + dma->flags = DMA_FLAG_EN_CHKSUM;
2114 + dma->sglen = sglen;
2115 + dma->xfersz = host->xfer_size;
2116 + dma->burstsz = MSDC_BRUST_64B;
2117 +
2118 + if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
2119 + dma->mode = MSDC_MODE_DMA_BASIC;
2120 + else
2121 + dma->mode = MSDC_MODE_DMA_DESC;
2122 +
2123 +// printk("DMA mode<%d> sglen<%d> xfersz<%d>\n", dma->mode, dma->sglen, dma->xfersz);
2124 +
2125 + msdc_dma_config(host, dma);
2126 +}
2127 +
2128 +static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
2129 +{
2130 + u32 base = host->base;
2131 +
2132 + sdr_write32(SDC_BLK_NUM, blknum);
2133 +}
2134 +
2135 +static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
2136 +{
2137 + struct msdc_host *host = mmc_priv(mmc);
2138 + struct mmc_command *cmd;
2139 + struct mmc_data *data;
2140 + u32 base = host->base;
2141 + unsigned int left=0;
2142 + int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
2143 +
2144 +#define SND_DAT 0
2145 +#define SND_CMD 1
2146 +
2147 + BUG_ON(mmc == NULL);
2148 + BUG_ON(mrq == NULL);
2149 +
2150 + host->error = 0;
2151 + atomic_set(&host->abort, 0);
2152 +
2153 + cmd = mrq->cmd;
2154 + data = mrq->cmd->data;
2155 +
2156 + if (!data) {
2157 + send_type = SND_CMD;
2158 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
2159 + goto done;
2160 + } else {
2161 + BUG_ON(data->blksz > HOST_MAX_BLKSZ);
2162 + send_type=SND_DAT;
2163 +
2164 + data->error = 0;
2165 + read = data->flags & MMC_DATA_READ ? 1 : 0;
2166 + host->data = data;
2167 + host->xfer_size = data->blocks * data->blksz;
2168 + host->blksz = data->blksz;
2169 +
2170 + host->dma_xfer = dma = ((host->xfer_size >= 512) ? 1 : 0);
2171 +
2172 + if (read)
2173 + if ((host->timeout_ns != data->timeout_ns) ||
2174 + (host->timeout_clks != data->timeout_clks))
2175 + msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
2176 +
2177 + msdc_set_blknum(host, data->blocks);
2178 +
2179 + if (dma) {
2180 + msdc_dma_on();
2181 + init_completion(&host->xfer_done);
2182 +
2183 + if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
2184 + goto done;
2185 +
2186 + dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2187 + dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
2188 + msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
2189 +
2190 + if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
2191 + goto done;
2192 +
2193 + msdc_dma_start(host);
2194 +
2195 + spin_unlock(&host->lock);
2196 + if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) {
2197 + /*printk("XXX CMD<%d> wait xfer_done<%d> timeout!!\n", cmd->opcode, data->blocks * data->blksz);
2198 + printk(" DMA_SA = 0x%x\n", sdr_read32(MSDC_DMA_SA));
2199 + printk(" DMA_CA = 0x%x\n", sdr_read32(MSDC_DMA_CA));
2200 + printk(" DMA_CTRL = 0x%x\n", sdr_read32(MSDC_DMA_CTRL));
2201 + printk(" DMA_CFG = 0x%x\n", sdr_read32(MSDC_DMA_CFG));*/
2202 + data->error = (unsigned int)-ETIMEDOUT;
2203 +
2204 + msdc_reset();
2205 + msdc_clr_fifo();
2206 + msdc_clr_int();
2207 + }
2208 + spin_lock(&host->lock);
2209 + msdc_dma_stop(host);
2210 + } else {
2211 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
2212 + goto done;
2213 +
2214 + if (read) {
2215 + if (msdc_pio_read(host, data))
2216 + goto done;
2217 + } else {
2218 + if (msdc_pio_write(host, data))
2219 + goto done;
2220 + }
2221 +
2222 + if (!read) {
2223 + while (1) {
2224 + left = msdc_txfifocnt();
2225 + if (left == 0) {
2226 + break;
2227 + }
2228 + if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
2229 + break;
2230 + /* Fix me: what about if data error, when stop ? how to? */
2231 + }
2232 + }
2233 + } else {
2234 + /* Fix me: read case: need to check CRC error */
2235 + }
2236 +
2237 + /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
2238 + For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
2239 + */
2240 +
2241 + /* try not to wait xfer_comp interrupt.
2242 + the next command will check SDC_BUSY.
2243 + SDC_BUSY means xfer_comp assert
2244 + */
2245 +
2246 + } // PIO mode
2247 +
2248 + /* Last: stop transfer */
2249 + if (data->stop){
2250 + if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
2251 + goto done;
2252 + }
2253 + }
2254 + }
2255 +
2256 +done:
2257 + if (data != NULL) {
2258 + host->data = NULL;
2259 + host->dma_xfer = 0;
2260 + if (dma != 0) {
2261 + msdc_dma_off();
2262 + host->dma.used_bd = 0;
2263 + host->dma.used_gpd = 0;
2264 + dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
2265 + }
2266 + host->blksz = 0;
2267 +
2268 + // printk("CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio\n"),
2269 + // (read ? "read ":"write") ,data->blksz, data->blocks, data->error);
2270 + }
2271 +
2272 + if (mrq->cmd->error) host->error = 0x001;
2273 + if (mrq->data && mrq->data->error) host->error |= 0x010;
2274 + if (mrq->stop && mrq->stop->error) host->error |= 0x100;
2275 +
2276 + //if (host->error) printk("host->error<%d>\n", host->error);
2277 +
2278 + return host->error;
2279 +}
2280 +
2281 +static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
2282 +{
2283 + struct mmc_command cmd;
2284 + struct mmc_request mrq;
2285 + u32 err;
2286 +
2287 + memset(&cmd, 0, sizeof(struct mmc_command));
2288 + cmd.opcode = MMC_APP_CMD;
2289 +#if 0 /* bug: we meet mmc->card is null when ACMD6 */
2290 + cmd.arg = mmc->card->rca << 16;
2291 +#else
2292 + cmd.arg = host->app_cmd_arg;
2293 +#endif
2294 + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
2295 +
2296 + memset(&mrq, 0, sizeof(struct mmc_request));
2297 + mrq.cmd = &cmd; cmd.mrq = &mrq;
2298 + cmd.data = NULL;
2299 +
2300 + err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
2301 + return err;
2302 +}
2303 +
2304 +static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
2305 +{
2306 + int result = -1;
2307 + u32 base = host->base;
2308 + u32 rsmpl, cur_rsmpl, orig_rsmpl;
2309 + u32 rrdly, cur_rrdly = 0, orig_rrdly;
2310 + u32 skip = 1;
2311 +
2312 + /* ==== don't support 3.0 now ====
2313 + 1: R_SMPL[1]
2314 + 2: PAD_CMD_RESP_RXDLY[26:22]
2315 + ==========================*/
2316 +
2317 + // save the previous tune result
2318 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
2319 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
2320 +
2321 + rrdly = 0;
2322 + do {
2323 + for (rsmpl = 0; rsmpl < 2; rsmpl++) {
2324 + /* Lv1: R_SMPL[1] */
2325 + cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
2326 + if (skip == 1) {
2327 + skip = 0;
2328 + continue;
2329 + }
2330 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
2331 +
2332 + if (host->app_cmd) {
2333 + result = msdc_app_cmd(host->mmc, host);
2334 + if (result) {
2335 + //printk("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>\n",
2336 + // host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
2337 + continue;
2338 + }
2339 + }
2340 + result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
2341 + //printk("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>\n", cmd->opcode,
2342 +// (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
2343 +
2344 + if (result == 0) {
2345 + return 0;
2346 + }
2347 + if (result != (unsigned int)(-EIO)) {
2348 + // printk("TUNE_CMD<%d> Error<%d> not -EIO\n", cmd->opcode, result);
2349 + return result;
2350 + }
2351 +
2352 + /* should be EIO */
2353 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
2354 + msdc_abort_data(host);
2355 + }
2356 + }
2357 +
2358 + /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
2359 + cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
2360 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
2361 + }while (++rrdly < 32);
2362 +
2363 + return result;
2364 +}
2365 +
2366 +/* Support SD2.0 Only */
2367 +static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
2368 +{
2369 + struct msdc_host *host = mmc_priv(mmc);
2370 + u32 base = host->base;
2371 + u32 ddr=0;
2372 + u32 dcrc = 0;
2373 + u32 rxdly, cur_rxdly0, cur_rxdly1;
2374 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
2375 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
2376 + u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
2377 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
2378 + u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
2379 + int result = -1;
2380 + u32 skip = 1;
2381 +
2382 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
2383 +
2384 + /* Tune Method 2. */
2385 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
2386 +
2387 + rxdly = 0;
2388 + do {
2389 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
2390 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
2391 + if (skip == 1) {
2392 + skip = 0;
2393 + continue;
2394 + }
2395 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
2396 +
2397 + if (host->app_cmd) {
2398 + result = msdc_app_cmd(host->mmc, host);
2399 + if (result) {
2400 + //printk("TUNE_BREAD app_cmd<%d> failed\n", host->mrq->cmd->opcode);
2401 + continue;
2402 + }
2403 + }
2404 + result = msdc_do_request(mmc,mrq);
2405 +
2406 + sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
2407 + if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
2408 + //printk("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>\n",
2409 + // (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
2410 + // sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
2411 +
2412 + /* Fix me: result is 0, but dcrc is still exist */
2413 + if (result == 0 && dcrc == 0) {
2414 + goto done;
2415 + } else {
2416 + /* there is a case: command timeout, and data phase not processed */
2417 + if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
2418 + //printk("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\n",
2419 + // result, mrq->cmd->error, mrq->data->error);
2420 + goto done;
2421 + }
2422 + }
2423 + }
2424 +
2425 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
2426 + cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
2427 +
2428 + /* E1 ECO. YD: Reverse */
2429 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2430 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
2431 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
2432 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
2433 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
2434 + orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
2435 + orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
2436 + orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
2437 + orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
2438 + } else {
2439 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
2440 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
2441 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
2442 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
2443 + orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
2444 + orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
2445 + orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
2446 + orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
2447 + }
2448 +
2449 + if (ddr) {
2450 + cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
2451 + cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
2452 + cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
2453 + cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
2454 + } else {
2455 + cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
2456 + cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
2457 + cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
2458 + cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
2459 + }
2460 + cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
2461 + cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
2462 + cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
2463 + cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
2464 +
2465 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
2466 + cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
2467 +
2468 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
2469 + sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
2470 +
2471 + } while (++rxdly < 32);
2472 +
2473 +done:
2474 + return result;
2475 +}
2476 +
2477 +static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
2478 +{
2479 + struct msdc_host *host = mmc_priv(mmc);
2480 + u32 base = host->base;
2481 +
2482 + u32 wrrdly, cur_wrrdly = 0, orig_wrrdly;
2483 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
2484 + u32 rxdly, cur_rxdly0;
2485 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
2486 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
2487 + int result = -1;
2488 + u32 skip = 1;
2489 +
2490 + // MSDC_IOCON_DDR50CKD need to check. [Fix me]
2491 +
2492 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
2493 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl );
2494 +
2495 + /* Tune Method 2. just DAT0 */
2496 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
2497 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
2498 +
2499 + /* E1 ECO. YD: Reverse */
2500 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2501 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
2502 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
2503 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
2504 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
2505 + } else {
2506 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
2507 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
2508 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
2509 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
2510 + }
2511 +
2512 + rxdly = 0;
2513 + do {
2514 + wrrdly = 0;
2515 + do {
2516 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
2517 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
2518 + if (skip == 1) {
2519 + skip = 0;
2520 + continue;
2521 + }
2522 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
2523 +
2524 + if (host->app_cmd) {
2525 + result = msdc_app_cmd(host->mmc, host);
2526 + if (result) {
2527 + //printk("TUNE_BWRITE app_cmd<%d> failed\n", host->mrq->cmd->opcode);
2528 + continue;
2529 + }
2530 + }
2531 + result = msdc_do_request(mmc,mrq);
2532 +
2533 + //printk("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>\n",
2534 + // result == 0 ? "PASS" : "FAIL",
2535 + // cur_dsmpl, cur_wrrdly, cur_rxdly0);
2536 +
2537 + if (result == 0) {
2538 + goto done;
2539 + }
2540 + else {
2541 + /* there is a case: command timeout, and data phase not processed */
2542 + if (mrq->data->error != (unsigned int)(-EIO)) {
2543 + //printk("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\n",
2544 + // && result, mrq->cmd->error, mrq->data->error);
2545 + goto done;
2546 + }
2547 + }
2548 + }
2549 + cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
2550 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
2551 + } while (++wrrdly < 32);
2552 +
2553 + cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
2554 + cur_dat1 = orig_dat1;
2555 + cur_dat2 = orig_dat2;
2556 + cur_dat3 = orig_dat3;
2557 +
2558 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
2559 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
2560 + } while (++rxdly < 32);
2561 +
2562 +done:
2563 + return result;
2564 +}
2565 +
2566 +static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
2567 +{
2568 + struct mmc_command cmd;
2569 + struct mmc_request mrq;
2570 + u32 err;
2571 +
2572 + memset(&cmd, 0, sizeof(struct mmc_command));
2573 + cmd.opcode = MMC_SEND_STATUS;
2574 + if (mmc->card) {
2575 + cmd.arg = mmc->card->rca << 16;
2576 + } else {
2577 + //printk("cmd13 mmc card is null\n");
2578 + cmd.arg = host->app_cmd_arg;
2579 + }
2580 + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
2581 +
2582 + memset(&mrq, 0, sizeof(struct mmc_request));
2583 + mrq.cmd = &cmd; cmd.mrq = &mrq;
2584 + cmd.data = NULL;
2585 +
2586 + err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
2587 +
2588 + if (status)
2589 + *status = cmd.resp[0];
2590 +
2591 + return err;
2592 +}
2593 +
2594 +static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
2595 +{
2596 + u32 err = 0;
2597 + u32 status = 0;
2598 +
2599 + do {
2600 + err = msdc_get_card_status(mmc, host, &status);
2601 + if (err)
2602 + return err;
2603 + /* need cmd12? */
2604 + //printk("cmd<13> resp<0x%x>\n", status);
2605 + } while (R1_CURRENT_STATE(status) == 7);
2606 +
2607 + return err;
2608 +}
2609 +
2610 +static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
2611 +{
2612 + struct msdc_host *host = mmc_priv(mmc);
2613 + struct mmc_command *cmd;
2614 + struct mmc_data *data;
2615 + int ret=0, read;
2616 +
2617 + cmd = mrq->cmd;
2618 + data = mrq->cmd->data;
2619 +
2620 + read = data->flags & MMC_DATA_READ ? 1 : 0;
2621 +
2622 + if (read) {
2623 + if (data->error == (unsigned int)(-EIO))
2624 + ret = msdc_tune_bread(mmc,mrq);
2625 + } else {
2626 + ret = msdc_check_busy(mmc, host);
2627 + if (ret){
2628 + //printk("XXX cmd13 wait program done failed\n");
2629 + return ret;
2630 + }
2631 + /* CRC and TO */
2632 + /* Fix me: don't care card status? */
2633 + ret = msdc_tune_bwrite(mmc,mrq);
2634 + }
2635 +
2636 + return ret;
2637 +}
2638 +
2639 +static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
2640 +{
2641 + struct msdc_host *host = mmc_priv(mmc);
2642 +
2643 + if (host->mrq) {
2644 + //printk("XXX host->mrq<0x%.8x>\n", (int)host->mrq);
2645 + BUG();
2646 + }
2647 + if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
2648 + //printk("cmd<%d> card<%d> power<%d>\n", mrq->cmd->opcode, is_card_present(host), host->power_mode);
2649 + mrq->cmd->error = (unsigned int)-ENOMEDIUM;
2650 + mrq->done(mrq);
2651 + return;
2652 + }
2653 + spin_lock(&host->lock);
2654 +
2655 + host->mrq = mrq;
2656 +
2657 + if (msdc_do_request(mmc,mrq))
2658 + if(host->hw->flags & MSDC_REMOVABLE && mrq->data && mrq->data->error)
2659 + msdc_tune_request(mmc,mrq);
2660 +
2661 + if (mrq->cmd->opcode == MMC_APP_CMD) {
2662 + host->app_cmd = 1;
2663 + host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
2664 + } else {
2665 + host->app_cmd = 0;
2666 + }
2667 +
2668 + host->mrq = NULL;
2669 +
2670 + spin_unlock(&host->lock);
2671 +
2672 + mmc_request_done(mmc, mrq);
2673 +}
2674 +
2675 +/* called by ops.set_ios */
2676 +static void msdc_set_buswidth(struct msdc_host *host, u32 width)
2677 +{
2678 + u32 base = host->base;
2679 + u32 val = sdr_read32(SDC_CFG);
2680 +
2681 + val &= ~SDC_CFG_BUSWIDTH;
2682 +
2683 + switch (width) {
2684 + default:
2685 + case MMC_BUS_WIDTH_1:
2686 + width = 1;
2687 + val |= (MSDC_BUS_1BITS << 16);
2688 + break;
2689 + case MMC_BUS_WIDTH_4:
2690 + val |= (MSDC_BUS_4BITS << 16);
2691 + break;
2692 + case MMC_BUS_WIDTH_8:
2693 + val |= (MSDC_BUS_8BITS << 16);
2694 + break;
2695 + }
2696 +
2697 + sdr_write32(SDC_CFG, val);
2698 +
2699 + //printk("Bus Width = %d\n", width);
2700 +}
2701 +
2702 +/* ops.set_ios */
2703 +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2704 +{
2705 + struct msdc_host *host = mmc_priv(mmc);
2706 + struct msdc_hw *hw=host->hw;
2707 + u32 base = host->base;
2708 + u32 ddr = 0;
2709 +
2710 +#ifdef MT6575_SD_DEBUG
2711 + static char *vdd[] = {
2712 + "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
2713 + "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
2714 + "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
2715 + "3.40v", "3.50v", "3.60v"
2716 + };
2717 + static char *power_mode[] = {
2718 + "OFF", "UP", "ON"
2719 + };
2720 + static char *bus_mode[] = {
2721 + "UNKNOWN", "OPENDRAIN", "PUSHPULL"
2722 + };
2723 + static char *timing[] = {
2724 + "LEGACY", "MMC_HS", "SD_HS"
2725 + };
2726 +
2727 + /*printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)\n",
2728 + ios->clock / 1000, bus_mode[ios->bus_mode],
2729 + (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
2730 + power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);*/
2731 +#endif
2732 +
2733 + msdc_set_buswidth(host, ios->bus_width);
2734 +
2735 + /* Power control ??? */
2736 + switch (ios->power_mode) {
2737 + case MMC_POWER_OFF:
2738 + case MMC_POWER_UP:
2739 + // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
2740 + break;
2741 + case MMC_POWER_ON:
2742 + host->power_mode = MMC_POWER_ON;
2743 + break;
2744 + default:
2745 + break;
2746 + }
2747 +
2748 + /* Clock control */
2749 + if (host->mclk != ios->clock) {
2750 + if(ios->clock > 25000000) {
2751 + //printk("SD data latch edge<%d>\n", hw->data_edge);
2752 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
2753 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
2754 + } else {
2755 + sdr_write32(MSDC_IOCON, 0x00000000);
2756 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
2757 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
2758 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
2759 + }
2760 + msdc_set_mclk(host, ddr, ios->clock);
2761 + }
2762 +}
2763 +
2764 +/* ops.get_ro */
2765 +static int msdc_ops_get_ro(struct mmc_host *mmc)
2766 +{
2767 + struct msdc_host *host = mmc_priv(mmc);
2768 + u32 base = host->base;
2769 + unsigned long flags;
2770 + int ro = 0;
2771 +
2772 + if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
2773 + spin_lock_irqsave(&host->lock, flags);
2774 + ro = (sdr_read32(MSDC_PS) >> 31);
2775 + spin_unlock_irqrestore(&host->lock, flags);
2776 + }
2777 + return ro;
2778 +}
2779 +
2780 +/* ops.get_cd */
2781 +static int msdc_ops_get_cd(struct mmc_host *mmc)
2782 +{
2783 + struct msdc_host *host = mmc_priv(mmc);
2784 + u32 base = host->base;
2785 + unsigned long flags;
2786 + int present = 1;
2787 +
2788 + /* for sdio, MSDC_REMOVABLE not set, always return 1 */
2789 + if (!(host->hw->flags & MSDC_REMOVABLE)) {
2790 + /* For sdio, read H/W always get<1>, but may timeout some times */
2791 +#if 1
2792 + host->card_inserted = 1;
2793 + return 1;
2794 +#else
2795 + host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
2796 + printk("sdio ops_get_cd<%d>\n", host->card_inserted);
2797 + return host->card_inserted;
2798 +#endif
2799 + }
2800 +
2801 + /* MSDC_CD_PIN_EN set for card */
2802 + if (host->hw->flags & MSDC_CD_PIN_EN) {
2803 + spin_lock_irqsave(&host->lock, flags);
2804 +#if 0
2805 + present = host->card_inserted; /* why not read from H/W: Fix me*/
2806 +#else
2807 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
2808 + host->card_inserted = present;
2809 +#endif
2810 + spin_unlock_irqrestore(&host->lock, flags);
2811 + } else {
2812 + present = 0; /* TODO? Check DAT3 pins for card detection */
2813 + }
2814 +
2815 + //printk("ops_get_cd return<%d>\n", present);
2816 + return present;
2817 +}
2818 +
2819 +/* ops.enable_sdio_irq */
2820 +static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
2821 +{
2822 + struct msdc_host *host = mmc_priv(mmc);
2823 + struct msdc_hw *hw = host->hw;
2824 + u32 base = host->base;
2825 + u32 tmp;
2826 +
2827 + if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
2828 + if (enable) {
2829 + hw->enable_sdio_eirq(); /* combo_sdio_enable_eirq */
2830 + } else {
2831 + hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
2832 + }
2833 + } else {
2834 + //printk("XXX \n"); /* so never enter here */
2835 + tmp = sdr_read32(SDC_CFG);
2836 + /* FIXME. Need to interrupt gap detection */
2837 + if (enable) {
2838 + tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
2839 + } else {
2840 + tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
2841 + }
2842 + sdr_write32(SDC_CFG, tmp);
2843 + }
2844 +}
2845 +
2846 +static struct mmc_host_ops mt_msdc_ops = {
2847 + .request = msdc_ops_request,
2848 + .set_ios = msdc_ops_set_ios,
2849 + .get_ro = msdc_ops_get_ro,
2850 + .get_cd = msdc_ops_get_cd,
2851 + .enable_sdio_irq = msdc_ops_enable_sdio_irq,
2852 +};
2853 +
2854 +/*--------------------------------------------------------------------------*/
2855 +/* interrupt handler */
2856 +/*--------------------------------------------------------------------------*/
2857 +static irqreturn_t msdc_irq(int irq, void *dev_id)
2858 +{
2859 + struct msdc_host *host = (struct msdc_host *)dev_id;
2860 + struct mmc_data *data = host->data;
2861 + struct mmc_command *cmd = host->cmd;
2862 + u32 base = host->base;
2863 +
2864 + u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
2865 + MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
2866 + MSDC_INT_ACMD19_DONE;
2867 + u32 datsts = MSDC_INT_DATCRCERR |MSDC_INT_DATTMO;
2868 +
2869 + u32 intsts = sdr_read32(MSDC_INT);
2870 + u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
2871 +
2872 + sdr_write32(MSDC_INT, intsts); /* clear interrupts */
2873 + /* MSG will cause fatal error */
2874 +
2875 + /* card change interrupt */
2876 + if (intsts & MSDC_INT_CDSC){
2877 + //printk("MSDC_INT_CDSC irq<0x%.8x>\n", intsts);
2878 + tasklet_hi_schedule(&host->card_tasklet);
2879 + /* tuning when plug card ? */
2880 + }
2881 +
2882 + /* sdio interrupt */
2883 + if (intsts & MSDC_INT_SDIOIRQ){
2884 + //printk("XXX MSDC_INT_SDIOIRQ\n"); /* seems not sdio irq */
2885 + //mmc_signal_sdio_irq(host->mmc);
2886 + }
2887 +
2888 + /* transfer complete interrupt */
2889 + if (data != NULL) {
2890 + if (inten & MSDC_INT_XFER_COMPL) {
2891 + data->bytes_xfered = host->dma.xfersz;
2892 + complete(&host->xfer_done);
2893 + }
2894 +
2895 + if (intsts & datsts) {
2896 + /* do basic reset, or stop command will sdc_busy */
2897 + msdc_reset();
2898 + msdc_clr_fifo();
2899 + msdc_clr_int();
2900 + atomic_set(&host->abort, 1); /* For PIO mode exit */
2901 +
2902 + if (intsts & MSDC_INT_DATTMO){
2903 + //printk("XXX CMD<%d> MSDC_INT_DATTMO\n", host->mrq->cmd->opcode);
2904 + data->error = (unsigned int)-ETIMEDOUT;
2905 + }
2906 + else if (intsts & MSDC_INT_DATCRCERR){
2907 + //printk("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>\n", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
2908 + data->error = (unsigned int)-EIO;
2909 + }
2910 +
2911 + //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
2912 + if (host->dma_xfer) {
2913 + complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
2914 + } /* PIO mode can't do complete, because not init */
2915 + }
2916 + }
2917 +
2918 + /* command interrupts */
2919 + if ((cmd != NULL) && (intsts & cmdsts)) {
2920 + if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
2921 + (intsts & MSDC_INT_ACMD19_DONE)) {
2922 + u32 *rsp = &cmd->resp[0];
2923 +
2924 + switch (host->cmd_rsp) {
2925 + case RESP_NONE:
2926 + break;
2927 + case RESP_R2:
2928 + *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
2929 + *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
2930 + break;
2931 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
2932 + if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
2933 + *rsp = sdr_read32(SDC_ACMD_RESP);
2934 + } else {
2935 + *rsp = sdr_read32(SDC_RESP0);
2936 + }
2937 + break;
2938 + }
2939 + } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
2940 + if(intsts & MSDC_INT_ACMDCRCERR){
2941 + //printk("XXX CMD<%d> MSDC_INT_ACMDCRCERR\n",cmd->opcode);
2942 + }
2943 + else {
2944 + //printk("XXX CMD<%d> MSDC_INT_RSPCRCERR\n",cmd->opcode);
2945 + }
2946 + cmd->error = (unsigned int)-EIO;
2947 + } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
2948 + if(intsts & MSDC_INT_ACMDTMO){
2949 + //printk("XXX CMD<%d> MSDC_INT_ACMDTMO\n",cmd->opcode);
2950 + }
2951 + else {
2952 + //printk("XXX CMD<%d> MSDC_INT_CMDTMO\n",cmd->opcode);
2953 + }
2954 + cmd->error = (unsigned int)-ETIMEDOUT;
2955 + msdc_reset();
2956 + msdc_clr_fifo();
2957 + msdc_clr_int();
2958 + }
2959 + complete(&host->cmd_done);
2960 + }
2961 +
2962 + /* mmc irq interrupts */
2963 + if (intsts & MSDC_INT_MMCIRQ) {
2964 + //printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
2965 + }
2966 +
2967 +#ifdef MT6575_SD_DEBUG
2968 + {
2969 + msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
2970 + /*printk("IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)\n",
2971 + intsts,
2972 + int_reg->mmcirq,
2973 + int_reg->cdsc,
2974 + int_reg->atocmdrdy,
2975 + int_reg->atocmdtmo,
2976 + int_reg->atocmdcrc,
2977 + int_reg->atocmd19done);
2978 + printk("IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)\n",
2979 + intsts,
2980 + int_reg->sdioirq,
2981 + int_reg->cmdrdy,
2982 + int_reg->cmdtmo,
2983 + int_reg->rspcrc,
2984 + int_reg->csta);
2985 + printk("IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)\n",
2986 + intsts,
2987 + int_reg->xfercomp,
2988 + int_reg->dxferdone,
2989 + int_reg->dattmo,
2990 + int_reg->datcrc,
2991 + int_reg->dmaqempty);*/
2992 +
2993 + }
2994 +#endif
2995 +
2996 + return IRQ_HANDLED;
2997 +}
2998 +
2999 +/*--------------------------------------------------------------------------*/
3000 +/* platform_driver members */
3001 +/*--------------------------------------------------------------------------*/
3002 +/* called by msdc_drv_probe/remove */
3003 +static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
3004 +{
3005 + struct msdc_hw *hw = host->hw;
3006 + u32 base = host->base;
3007 +
3008 + /* for sdio, not set */
3009 + if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
3010 + /* Pull down card detection pin since it is not avaiable */
3011 + /*
3012 + if (hw->config_gpio_pin)
3013 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
3014 + */
3015 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
3016 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
3017 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
3018 + return;
3019 + }
3020 +
3021 + //printk("CD IRQ Eanable(%d)\n", enable);
3022 +
3023 + if (enable) {
3024 + if (hw->enable_cd_eirq) { /* not set, never enter */
3025 + hw->enable_cd_eirq();
3026 + } else {
3027 + /* card detection circuit relies on the core power so that the core power
3028 + * shouldn't be turned off. Here adds a reference count to keep
3029 + * the core power alive.
3030 + */
3031 + //msdc_vcore_on(host); //did in msdc_init_hw()
3032 +
3033 + if (hw->config_gpio_pin) /* NULL */
3034 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
3035 +
3036 + sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
3037 + sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
3038 + sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
3039 + sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
3040 + }
3041 + } else {
3042 + if (hw->disable_cd_eirq) {
3043 + hw->disable_cd_eirq();
3044 + } else {
3045 + if (hw->config_gpio_pin) /* NULL */
3046 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
3047 +
3048 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
3049 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
3050 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
3051 +
3052 + /* Here decreases a reference count to core power since card
3053 + * detection circuit is shutdown.
3054 + */
3055 + //msdc_vcore_off(host);
3056 + }
3057 + }
3058 +}
3059 +
3060 +/* called by msdc_drv_probe */
3061 +static void msdc_init_hw(struct msdc_host *host)
3062 +{
3063 + u32 base = host->base;
3064 + struct msdc_hw *hw = host->hw;
3065 +
3066 +#ifdef MT6575_SD_DEBUG
3067 + msdc_reg[host->id] = (struct msdc_regs *)host->base;
3068 +#endif
3069 +
3070 + /* Power on */
3071 +#if 0 /* --- chhung */
3072 + msdc_vcore_on(host);
3073 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
3074 + msdc_select_clksrc(host, hw->clk_src);
3075 + enable_clock(PERI_MSDC0_PDN + host->id, "SD");
3076 + msdc_vdd_on(host);
3077 +#endif /* end of --- */
3078 + /* Configure to MMC/SD mode */
3079 + sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
3080 +
3081 + /* Reset */
3082 + msdc_reset();
3083 + msdc_clr_fifo();
3084 +
3085 + /* Disable card detection */
3086 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
3087 +
3088 + /* Disable and clear all interrupts */
3089 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
3090 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
3091 +
3092 +#if 1
3093 + /* reset tuning parameter */
3094 + sdr_write32(MSDC_PAD_CTL0, 0x00090000);
3095 + sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
3096 + sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
3097 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
3098 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
3099 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
3100 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
3101 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
3102 + sdr_write32(MSDC_IOCON, 0x00000000);
3103 +#if 0 // use MT7620 default value: 0x403c004f
3104 + sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
3105 +#endif
3106 +
3107 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3108 + if (host->id == 1) {
3109 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
3110 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
3111 +
3112 + /* internal clock: latch read data */
3113 + sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
3114 + }
3115 + }
3116 +#endif
3117 +
3118 + /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
3119 + pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
3120 + set when kernel driver wants to use SDIO bus interrupt */
3121 + /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
3122 + sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
3123 +
3124 + /* disable detect SDIO device interupt function */
3125 + sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
3126 +
3127 + /* eneable SMT for glitch filter */
3128 + sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
3129 + sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
3130 + sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
3131 +
3132 +#if 1
3133 + /* set clk, cmd, dat pad driving */
3134 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
3135 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
3136 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
3137 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
3138 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
3139 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
3140 +#else
3141 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
3142 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
3143 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
3144 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
3145 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
3146 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
3147 +#endif
3148 +
3149 + /* set sampling edge */
3150 +
3151 + /* write crc timeout detection */
3152 + sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
3153 +
3154 + /* Configure to default data timeout */
3155 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
3156 +
3157 + msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
3158 +
3159 + //printk("init hardware done!\n");
3160 +}
3161 +
3162 +/* called by msdc_drv_remove */
3163 +static void msdc_deinit_hw(struct msdc_host *host)
3164 +{
3165 + u32 base = host->base;
3166 +
3167 + /* Disable and clear all interrupts */
3168 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
3169 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
3170 +
3171 + /* Disable card detection */
3172 + msdc_enable_cd_irq(host, 0);
3173 + // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
3174 +}
3175 +
3176 +/* init gpd and bd list in msdc_drv_probe */
3177 +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
3178 +{
3179 + gpd_t *gpd = dma->gpd;
3180 + bd_t *bd = dma->bd;
3181 + bd_t *ptr, *prev;
3182 +
3183 + /* we just support one gpd */
3184 + int bdlen = MAX_BD_PER_GPD;
3185 +
3186 + /* init the 2 gpd */
3187 + memset(gpd, 0, sizeof(gpd_t) * 2);
3188 + //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */
3189 + //gpd->next = (dma->gpd_addr + 1); /* bug */
3190 + gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));
3191 +
3192 + //gpd->intr = 0;
3193 + gpd->bdp = 1; /* hwo, cs, bd pointer */
3194 + //gpd->ptr = (void*)virt_to_phys(bd);
3195 + gpd->ptr = (void *)dma->bd_addr; /* physical address */
3196 +
3197 + memset(bd, 0, sizeof(bd_t) * bdlen);
3198 + ptr = bd + bdlen - 1;
3199 + //ptr->eol = 1; /* 0 or 1 [Fix me]*/
3200 + //ptr->next = 0;
3201 +
3202 + while (ptr != bd) {
3203 + prev = ptr - 1;
3204 + prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
3205 + ptr = prev;
3206 + }
3207 +}
3208 +
3209 +static int msdc_drv_probe(struct platform_device *pdev)
3210 +{
3211 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3212 + __iomem void *base;
3213 + struct mmc_host *mmc;
3214 + struct resource *mem;
3215 + struct msdc_host *host;
3216 + struct msdc_hw *hw;
3217 + int ret, irq;
3218 + pdev->dev.platform_data = &msdc0_hw;
3219 +
3220 + /* Allocate MMC host for this device */
3221 + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
3222 + if (!mmc) return -ENOMEM;
3223 +
3224 + hw = (struct msdc_hw*)pdev->dev.platform_data;
3225 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3226 + irq = platform_get_irq(pdev, 0);
3227 +
3228 + //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
3229 +
3230 + base = devm_request_and_ioremap(&pdev->dev, res);
3231 + if (IS_ERR(base))
3232 + return PTR_ERR(base);
3233 +
3234 +/* mem = request_mem_region(mem->start - 0xa0000000, (mem->end - mem->start + 1) - 0xa0000000, dev_name(&pdev->dev));
3235 + if (mem == NULL) {
3236 + mmc_free_host(mmc);
3237 + return -EBUSY;
3238 + }
3239 +*/
3240 + /* Set host parameters to mmc */
3241 + mmc->ops = &mt_msdc_ops;
3242 + mmc->f_min = HOST_MIN_MCLK;
3243 + mmc->f_max = HOST_MAX_MCLK;
3244 + mmc->ocr_avail = MSDC_OCR_AVAIL;
3245 +
3246 + /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
3247 + For sdio : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
3248 + if (hw->flags & MSDC_HIGHSPEED) {
3249 + mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
3250 + }
3251 + if (hw->data_pins == 4) { /* current data_pins are all 4*/
3252 + mmc->caps |= MMC_CAP_4_BIT_DATA;
3253 + } else if (hw->data_pins == 8) {
3254 + mmc->caps |= MMC_CAP_8_BIT_DATA;
3255 + }
3256 + if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
3257 + mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
3258 +
3259 + /* MMC core transfer sizes tunable parameters */
3260 + // mmc->max_hw_segs = MAX_HW_SGMTS;
3261 +// mmc->max_phys_segs = MAX_PHY_SGMTS;
3262 + mmc->max_seg_size = MAX_SGMT_SZ;
3263 + mmc->max_blk_size = HOST_MAX_BLKSZ;
3264 + mmc->max_req_size = MAX_REQ_SZ;
3265 + mmc->max_blk_count = mmc->max_req_size;
3266 +
3267 + host = mmc_priv(mmc);
3268 + host->hw = hw;
3269 + host->mmc = mmc;
3270 + host->id = pdev->id;
3271 + host->error = 0;
3272 + host->irq = irq;
3273 + host->base = (unsigned long) base;
3274 + host->mclk = 0; /* mclk: the request clock of mmc sub-system */
3275 + host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
3276 + host->sclk = 0; /* sclk: the really clock after divition */
3277 + host->pm_state = PMSG_RESUME;
3278 + host->suspend = 0;
3279 + host->core_clkon = 0;
3280 + host->card_clkon = 0;
3281 + host->core_power = 0;
3282 + host->power_mode = MMC_POWER_OFF;
3283 +// host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
3284 + host->timeout_ns = 0;
3285 + host->timeout_clks = DEFAULT_DTOC * 65536;
3286 +
3287 + host->mrq = NULL;
3288 + //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
3289 +
3290 + host->dma.used_gpd = 0;
3291 + host->dma.used_bd = 0;
3292 +
3293 + /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
3294 + host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL);
3295 + host->dma.bd = dma_alloc_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), &host->dma.bd_addr, GFP_KERNEL);
3296 + BUG_ON((!host->dma.gpd) || (!host->dma.bd));
3297 + msdc_init_gpd_bd(host, &host->dma);
3298 + /*for emmc*/
3299 + msdc_6575_host[pdev->id] = host;
3300 +
3301 + tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
3302 + spin_lock_init(&host->lock);
3303 + msdc_init_hw(host);
3304 +
3305 + ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
3306 + if (ret) goto release;
3307 + // mt65xx_irq_unmask(irq); /* --- by chhung */
3308 +
3309 + if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
3310 + if (hw->request_cd_eirq) { /* not set for MT6575 */
3311 + hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
3312 + }
3313 + }
3314 +
3315 + if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
3316 + hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
3317 +
3318 + if (hw->register_pm) {/* yes for sdio */
3319 + if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
3320 + //printk("MSDC_SYS_SUSPEND and register_pm both set\n");
3321 + }
3322 + //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
3323 + }
3324 +
3325 + platform_set_drvdata(pdev, mmc);
3326 +
3327 + ret = mmc_add_host(mmc);
3328 + if (ret) goto free_irq;
3329 +
3330 + /* Config card detection pin and enable interrupts */
3331 + if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
3332 + msdc_enable_cd_irq(host, 1);
3333 + } else {
3334 + msdc_enable_cd_irq(host, 0);
3335 + }
3336 +
3337 + return 0;
3338 +
3339 +free_irq:
3340 + free_irq(irq, host);
3341 +release:
3342 + platform_set_drvdata(pdev, NULL);
3343 + msdc_deinit_hw(host);
3344 +
3345 + tasklet_kill(&host->card_tasklet);
3346 +
3347 +/* if (mem)
3348 + release_mem_region(mem->start, mem->end - mem->start + 1);
3349 +*/
3350 + mmc_free_host(mmc);
3351 +
3352 + return ret;
3353 +}
3354 +
3355 +/* 4 device share one driver, using "drvdata" to show difference */
3356 +static int msdc_drv_remove(struct platform_device *pdev)
3357 +{
3358 + struct mmc_host *mmc;
3359 + struct msdc_host *host;
3360 + struct resource *mem;
3361 +
3362 +
3363 + mmc = platform_get_drvdata(pdev);
3364 + BUG_ON(!mmc);
3365 +
3366 + host = mmc_priv(mmc);
3367 + BUG_ON(!host);
3368 +
3369 + //printk("removed !!!\n");
3370 +
3371 + platform_set_drvdata(pdev, NULL);
3372 + mmc_remove_host(host->mmc);
3373 + msdc_deinit_hw(host);
3374 +
3375 + tasklet_kill(&host->card_tasklet);
3376 + free_irq(host->irq, host);
3377 +
3378 + dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
3379 + dma_free_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), host->dma.bd, host->dma.bd_addr);
3380 +
3381 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3382 +
3383 + if (mem)
3384 + release_mem_region(mem->start, mem->end - mem->start + 1);
3385 +
3386 + mmc_free_host(host->mmc);
3387 +
3388 + return 0;
3389 +}
3390 +
3391 +static const struct of_device_id mt7620a_sdhci_match[] = {
3392 + { .compatible = "ralink,mt7620a-sdhci" },
3393 + {},
3394 +};
3395 +MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
3396 +
3397 +/* Fix me: Power Flow */
3398 +static struct platform_driver mt_msdc_driver = {
3399 + .probe = msdc_drv_probe,
3400 + .remove = msdc_drv_remove,
3401 + .driver = {
3402 + .name = DRV_NAME,
3403 + .owner = THIS_MODULE,
3404 + .of_match_table = mt7620a_sdhci_match,
3405 +
3406 + },
3407 +};
3408 +
3409 +static int __init mt_msdc_init(void)
3410 +{
3411 + int ret;
3412 +/* +++ chhung */
3413 + unsigned int reg;
3414 +
3415 + mtk_sd_device.dev.platform_data = &msdc0_hw;
3416 + printk("MTK MSDC device init.\n");
3417 + reg = sdr_read32((__iomem void *) 0xb0000060) & ~(0x3<<18);
3418 + reg |= 0x1 << 18;
3419 + sdr_write32((__iomem void *) 0xb0000060, reg);
3420 +/* end of +++ */
3421 + ret = platform_driver_register(&mt_msdc_driver);
3422 + if (ret) {
3423 + printk(KERN_ERR DRV_NAME ": Can't register driver");
3424 + return ret;
3425 + }
3426 + printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
3427 +
3428 + //msdc_debug_proc_init();
3429 + return 0;
3430 +}
3431 +
3432 +static void __exit mt_msdc_exit(void)
3433 +{
3434 + platform_driver_unregister(&mt_msdc_driver);
3435 +}
3436 +
3437 +module_init(mt_msdc_init);
3438 +module_exit(mt_msdc_exit);
3439 +MODULE_LICENSE("GPL");
3440 +MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
3441 +MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
3442 +
3443 +EXPORT_SYMBOL(msdc_6575_host);
3444 --
3445 1.7.10.4
3446
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