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ralink: add 3.14 support
[openwrt/svn-archive/archive.git] / target / linux / ramips / patches-3.14 / 0026-MIPS-ralink-add-mt7628an-support.patch
1 From a375beba066516ecafddebc765454ac6ec599f3d Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 6 Aug 2014 18:26:08 +0200
4 Subject: [PATCH 26/57] MIPS: ralink: add mt7628an support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/include/asm/mach-ralink/mt7620.h | 11 ++
9 arch/mips/ralink/Kconfig | 2 +-
10 arch/mips/ralink/mt7620.c | 266 +++++++++++++++++++++++-----
11 3 files changed, 232 insertions(+), 47 deletions(-)
12
13 diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
14 index 27b2fa9..c8590df 100644
15 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
16 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
17 @@ -13,6 +13,13 @@
18 #ifndef _MT7620_REGS_H_
19 #define _MT7620_REGS_H_
20
21 +enum mt762x_soc_type {
22 + MT762X_SOC_UNKNOWN = 0,
23 + MT762X_SOC_MT7620A,
24 + MT762X_SOC_MT7620N,
25 + MT762X_SOC_MT7628AN,
26 +};
27 +
28 #define MT7620_SYSC_BASE 0x10000000
29
30 #define SYSC_REG_CHIP_NAME0 0x00
31 @@ -27,6 +34,7 @@
32
33 #define MT7620_CHIP_NAME0 0x3637544d
34 #define MT7620_CHIP_NAME1 0x20203032
35 +#define MT7628_CHIP_NAME1 0x20203832
36
37 #define SYSCFG0_XTAL_FREQ_SEL BIT(6)
38
39 @@ -71,6 +79,9 @@
40 #define SYSCFG0_DRAM_TYPE_DDR1 1
41 #define SYSCFG0_DRAM_TYPE_DDR2 2
42
43 +#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
44 +#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
45 +
46 #define MT7620_DRAM_BASE 0x0
47 #define MT7620_SDRAM_SIZE_MIN 2
48 #define MT7620_SDRAM_SIZE_MAX 64
49 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
50 index 9174dbc..f93835f 100644
51 --- a/arch/mips/ralink/Kconfig
52 +++ b/arch/mips/ralink/Kconfig
53 @@ -35,7 +35,7 @@ choice
54 select HW_HAS_PCI
55
56 config SOC_MT7620
57 - bool "MT7620"
58 + bool "MT7620/8"
59 select USB_ARCH_HAS_OHCI
60 select USB_ARCH_HAS_EHCI
61
62 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
63 index d68b8ff..e590ccf 100644
64 --- a/arch/mips/ralink/mt7620.c
65 +++ b/arch/mips/ralink/mt7620.c
66 @@ -42,6 +42,8 @@
67 #define CLKCFG_FFRAC_MASK 0x001f
68 #define CLKCFG_FFRAC_USB_VAL 0x0003
69
70 +enum mt762x_soc_type mt762x_soc;
71 +
72 /* does the board have sdram or ddram */
73 static int dram_type;
74
75 @@ -159,6 +161,125 @@ struct ralink_pinmux rt_gpio_pinmux = {
76 .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
77 };
78
79 +static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
80 + FUNC("sdcx", 3, 19, 1),
81 + FUNC("utif", 2, 19, 1),
82 + FUNC("gpio", 1, 19, 1),
83 + FUNC("pwm", 0, 19, 1),
84 +};
85 +
86 +static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
87 + FUNC("sdcx", 3, 18, 1),
88 + FUNC("utif", 2, 18, 1),
89 + FUNC("gpio", 1, 18, 1),
90 + FUNC("pwm", 0, 18, 1),
91 +};
92 +
93 +static struct rt2880_pmx_func uart2_grp_mt7628[] = {
94 + FUNC("sdcx", 3, 20, 2),
95 + FUNC("pwm", 2, 20, 2),
96 + FUNC("gpio", 1, 20, 2),
97 + FUNC("uart", 0, 20, 2),
98 +};
99 +
100 +static struct rt2880_pmx_func uart1_grp_mt7628[] = {
101 + FUNC("sdcx", 3, 45, 2),
102 + FUNC("pwm", 2, 45, 2),
103 + FUNC("gpio", 1, 45, 2),
104 + FUNC("uart", 0, 45, 2),
105 +};
106 +
107 +static struct rt2880_pmx_func i2c_grp_mt7628[] = {
108 + FUNC("-", 3, 4, 2),
109 + FUNC("debug", 2, 4, 2),
110 + FUNC("gpio", 1, 4, 2),
111 + FUNC("i2c", 0, 4, 2),
112 +};
113 +
114 +static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
115 +static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
116 +static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
117 +static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
118 +
119 +static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
120 + FUNC("jtag", 3, 22, 8),
121 + FUNC("utif", 2, 22, 8),
122 + FUNC("gpio", 1, 22, 8),
123 + FUNC("sdcx", 0, 22, 8),
124 +};
125 +
126 +static struct rt2880_pmx_func uart0_grp_mt7628[] = {
127 + FUNC("-", 3, 12, 2),
128 + FUNC("-", 2, 12, 2),
129 + FUNC("gpio", 1, 12, 2),
130 + FUNC("uart", 0, 12, 2),
131 +};
132 +
133 +static struct rt2880_pmx_func i2s_grp_mt7628[] = {
134 + FUNC("antenna", 3, 0, 4),
135 + FUNC("pcm", 2, 0, 4),
136 + FUNC("gpio", 1, 0, 4),
137 + FUNC("i2s", 0, 0, 4),
138 +};
139 +
140 +static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
141 + FUNC("-", 3, 6, 1),
142 + FUNC("refclk", 2, 6, 1),
143 + FUNC("gpio", 1, 6, 1),
144 + FUNC("spi", 0, 6, 1),
145 +};
146 +
147 +static struct rt2880_pmx_func spis_grp_mt7628[] = {
148 + FUNC("pwm", 3, 14, 4),
149 + FUNC("util", 2, 14, 4),
150 + FUNC("gpio", 1, 14, 4),
151 + FUNC("spis", 0, 14, 4),
152 +};
153 +
154 +static struct rt2880_pmx_func gpio_grp_mt7628[] = {
155 + FUNC("pcie", 3, 11, 1),
156 + FUNC("refclk", 2, 11, 1),
157 + FUNC("gpio", 1, 11, 1),
158 + FUNC("gpio", 0, 11, 1),
159 +};
160 +
161 +#define MT7628_GPIO_MODE_MASK 0x3
162 +
163 +#define MT7628_GPIO_MODE_PWM1 30
164 +#define MT7628_GPIO_MODE_PWM0 28
165 +#define MT7628_GPIO_MODE_UART2 26
166 +#define MT7628_GPIO_MODE_UART1 24
167 +#define MT7628_GPIO_MODE_I2C 20
168 +#define MT7628_GPIO_MODE_REFCLK 18
169 +#define MT7628_GPIO_MODE_PERST 16
170 +#define MT7628_GPIO_MODE_WDT 14
171 +#define MT7628_GPIO_MODE_SPI 12
172 +#define MT7628_GPIO_MODE_SDMODE 10
173 +#define MT7628_GPIO_MODE_UART0 8
174 +#define MT7628_GPIO_MODE_I2S 6
175 +#define MT7628_GPIO_MODE_CS1 4
176 +#define MT7628_GPIO_MODE_SPIS 2
177 +#define MT7628_GPIO_MODE_GPIO 0
178 +
179 +static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
180 + GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM1),
181 + GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM0),
182 + GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART2),
183 + GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART1),
184 + GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2C),
185 + GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
186 + GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
187 + GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
188 + GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
189 + GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SDMODE),
190 + GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART0),
191 + GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2S),
192 + GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_CS1),
193 + GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SPIS),
194 + GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_GPIO),
195 + { 0 }
196 +};
197 +
198 static __init u32
199 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
200 {
201 @@ -309,29 +430,42 @@ void __init ralink_clk_init(void)
202
203 xtal_rate = mt7620_get_xtal_rate();
204
205 - cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
206 - pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
207 -
208 - cpu_rate = mt7620_get_cpu_rate(pll_rate);
209 - dram_rate = mt7620_get_dram_rate(pll_rate);
210 - sys_rate = mt7620_get_sys_rate(cpu_rate);
211 - periph_rate = mt7620_get_periph_rate(xtal_rate);
212 -
213 #define RFMT(label) label ":%lu.%03luMHz "
214 #define RINT(x) ((x) / 1000000)
215 #define RFRAC(x) (((x) / 1000) % 1000)
216
217 - pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
218 - RINT(xtal_rate), RFRAC(xtal_rate),
219 - RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
220 - RINT(pll_rate), RFRAC(pll_rate));
221 + if (mt762x_soc == MT762X_SOC_MT7628AN) {
222 + if (xtal_rate == MHZ(40))
223 + cpu_rate = MHZ(580);
224 + else
225 + cpu_rate = MHZ(575);
226 + dram_rate = sys_rate = cpu_rate / 3;
227 + periph_rate = MHZ(40);
228 +
229 + ralink_clk_add("10000d00.uartlite", periph_rate);
230 + ralink_clk_add("10000e00.uartlite", periph_rate);
231 + } else {
232 + cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
233 + pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
234 +
235 + cpu_rate = mt7620_get_cpu_rate(pll_rate);
236 + dram_rate = mt7620_get_dram_rate(pll_rate);
237 + sys_rate = mt7620_get_sys_rate(cpu_rate);
238 + periph_rate = mt7620_get_periph_rate(xtal_rate);
239 +
240 + pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
241 + RINT(xtal_rate), RFRAC(xtal_rate),
242 + RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
243 + RINT(pll_rate), RFRAC(pll_rate));
244 +
245 + ralink_clk_add("10000500.uart", periph_rate);
246 + }
247
248 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
249 RINT(cpu_rate), RFRAC(cpu_rate),
250 RINT(dram_rate), RFRAC(dram_rate),
251 RINT(sys_rate), RFRAC(sys_rate),
252 RINT(periph_rate), RFRAC(periph_rate));
253 -
254 #undef RFRAC
255 #undef RINT
256 #undef RFMT
257 @@ -339,12 +473,11 @@ void __init ralink_clk_init(void)
258 ralink_clk_add("cpu", cpu_rate);
259 ralink_clk_add("10000100.timer", periph_rate);
260 ralink_clk_add("10000120.watchdog", periph_rate);
261 - ralink_clk_add("10000500.uart", periph_rate);
262 ralink_clk_add("10000b00.spi", sys_rate);
263 ralink_clk_add("10000c00.uartlite", periph_rate);
264 ralink_clk_add("10180000.wmac", xtal_rate);
265
266 - if (IS_ENABLED(CONFIG_USB)) {
267 + if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
268 /*
269 * When the CPU goes into sleep mode, the BUS clock will be too low for
270 * USB to function properly
271 @@ -367,6 +500,52 @@ void __init ralink_of_remap(void)
272 panic("Failed to remap core resources");
273 }
274
275 +static __init void
276 +mt7620_dram_init(struct ralink_soc_info *soc_info)
277 +{
278 + switch (dram_type) {
279 + case SYSCFG0_DRAM_TYPE_SDRAM:
280 + pr_info("Board has SDRAM\n");
281 + soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
282 + soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
283 + break;
284 +
285 + case SYSCFG0_DRAM_TYPE_DDR1:
286 + pr_info("Board has DDR1\n");
287 + soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
288 + soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
289 + break;
290 +
291 + case SYSCFG0_DRAM_TYPE_DDR2:
292 + pr_info("Board has DDR2\n");
293 + soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
294 + soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
295 + break;
296 + default:
297 + BUG();
298 + }
299 +}
300 +
301 +static __init void
302 +mt7628_dram_init(struct ralink_soc_info *soc_info)
303 +{
304 + switch (dram_type) {
305 + case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
306 + pr_info("Board has DDR1\n");
307 + soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
308 + soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
309 + break;
310 +
311 + case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
312 + pr_info("Board has DDR2\n");
313 + soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
314 + soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
315 + break;
316 + default:
317 + BUG();
318 + }
319 +}
320 +
321 void prom_soc_init(struct ralink_soc_info *soc_info)
322 {
323 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
324 @@ -384,18 +563,25 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
325 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
326 bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
327
328 - if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
329 - panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
330 -
331 - if (bga) {
332 - name = "MT7620A";
333 - soc_info->compatible = "ralink,mt7620a-soc";
334 - } else {
335 - name = "MT7620N";
336 - soc_info->compatible = "ralink,mt7620n-soc";
337 + if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
338 + if (bga) {
339 + mt762x_soc = MT762X_SOC_MT7620A;
340 + name = "MT7620A";
341 + soc_info->compatible = "ralink,mt7620a-soc";
342 + } else {
343 + mt762x_soc = MT762X_SOC_MT7620N;
344 + name = "MT7620N";
345 + soc_info->compatible = "ralink,mt7620n-soc";
346 #ifdef CONFIG_PCI
347 - panic("mt7620n is only supported for non pci kernels");
348 + panic("mt7620n is only supported for non pci kernels");
349 #endif
350 + }
351 + } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
352 + mt762x_soc = MT762X_SOC_MT7628AN;
353 + name = "MT7628AN";
354 + soc_info->compatible = "ralink,mt7628an-soc";
355 + } else {
356 + panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
357 }
358
359 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
360 @@ -407,28 +593,11 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
361 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
362 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
363
364 - switch (dram_type) {
365 - case SYSCFG0_DRAM_TYPE_SDRAM:
366 - pr_info("Board has SDRAM\n");
367 - soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
368 - soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
369 - break;
370 -
371 - case SYSCFG0_DRAM_TYPE_DDR1:
372 - pr_info("Board has DDR1\n");
373 - soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
374 - soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
375 - break;
376 -
377 - case SYSCFG0_DRAM_TYPE_DDR2:
378 - pr_info("Board has DDR2\n");
379 - soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
380 - soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
381 - break;
382 - default:
383 - BUG();
384 - }
385 soc_info->mem_base = MT7620_DRAM_BASE;
386 + if (mt762x_soc == MT762X_SOC_MT7628AN)
387 + mt7628_dram_init(soc_info);
388 + else
389 + mt7620_dram_init(soc_info);
390
391 pmu0 = __raw_readl(sysc + PMU0_CFG);
392 pmu1 = __raw_readl(sysc + PMU1_CFG);
393 @@ -437,4 +606,9 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
394 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
395 pr_info("Digital PMU set to %s control\n",
396 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
397 +
398 + if (mt762x_soc == MT762X_SOC_MT7628AN)
399 + rt2880_pinmux_data = mt7628an_pinmux_data;
400 + else
401 + rt2880_pinmux_data = mt7620a_pinmux_data;
402 }
403 --
404 1.7.10.4
405
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