target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch

   1 From 307b7a71a634ae3848fb7c5c05759d647e140e12 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 18 May 2013 22:06:15 +0200
   4 Subject: [PATCH 32/57] PCI: MIPS: adds mt7620a pcie driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/pci/Makefile      |    1 +
   9  arch/mips/pci/pci-mt7620a.c |  363 +++++++++++++++++++++++++++++++++++++++++++
  10  arch/mips/ralink/Kconfig    |    1 +
  11  3 files changed, 365 insertions(+)
  12  create mode 100644 arch/mips/pci/pci-mt7620a.c
  13
  14 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
  15 index 6a0f453..b140299 100644
  16 --- a/arch/mips/pci/Makefile
  17 +++ b/arch/mips/pci/Makefile
  18 @@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM)          += fixup-sni.o ops-sni.o
  19  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  20  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  21  obj-$(CONFIG_SOC_MT7621)       += pci-mt7621.o
  22 +obj-$(CONFIG_SOC_MT7620)       += pci-mt7620a.o
  23  obj-$(CONFIG_SOC_RT2880)       += pci-rt2880.o
  24  obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  25  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  26 diff --git a/arch/mips/pci/pci-mt7620a.c b/arch/mips/pci/pci-mt7620a.c
  27 new file mode 100644
  28 index 0000000..271763c
  29 --- /dev/null
  30 +++ b/arch/mips/pci/pci-mt7620a.c
  31 @@ -0,0 +1,363 @@
  32 +/*
  33 + *  Ralink MT7620A SoC PCI support
  34 + *
  35 + *  Copyright (C) 2007-2013 Bruce Chang
  36 + *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  37 + *
  38 + *  This program is free software; you can redistribute it and/or modify it
  39 + *  under the terms of the GNU General Public License version 2 as published
  40 + *  by the Free Software Foundation.
  41 + */
  42 +
  43 +#include <linux/types.h>
  44 +#include <linux/pci.h>
  45 +#include <linux/io.h>
  46 +#include <linux/init.h>
  47 +#include <linux/delay.h>
  48 +#include <linux/interrupt.h>
  49 +#include <linux/module.h>
  50 +#include <linux/of.h>
  51 +#include <linux/of_irq.h>
  52 +#include <linux/of_pci.h>
  53 +#include <linux/reset.h>
  54 +#include <linux/platform_device.h>
  55 +
  56 +#include <asm/mach-ralink/ralink_regs.h>
  57 +
  58 +#define RALINK_PCI_MM_MAP_BASE         0x20000000
  59 +#define RALINK_PCI_IO_MAP_BASE         0x10160000
  60 +
  61 +#define RALINK_INT_PCIE0               4
  62 +#define RALINK_SYSTEM_CONTROL_BASE     0xb0000000
  63 +#define RALINK_SYSCFG1                 0x14
  64 +#define RALINK_CLKCFG1                 0x30
  65 +#define RALINK_GPIOMODE                        0x60
  66 +#define RALINK_PCIE_CLK_GEN            0x7c
  67 +#define RALINK_PCIE_CLK_GEN1           0x80
  68 +#define PCIEPHY0_CFG                   0x90
  69 +#define PPLL_CFG1                      0x9c
  70 +#define PPLL_DRV                       0xa0
  71 +#define RALINK_PCI_HOST_MODE_EN                (1<<7)
  72 +#define RALINK_PCIE_RC_MODE_EN         (1<<8)
  73 +#define RALINK_PCIE_RST                        (1<<23)
  74 +#define RALINK_PCI_RST                 (1<<24)
  75 +#define RALINK_PCI_CLK_EN              (1<<19)
  76 +#define RALINK_PCIE_CLK_EN             (1<<21)
  77 +#define PCI_SLOTx2                     (1<<11)
  78 +#define PCI_SLOTx1                     (2<<11)
  79 +#define PDRV_SW_SET                    (1<<31)
  80 +#define LC_CKDRVPD_                    (1<<19)
  81 +
  82 +#define RALINK_PCI_CONFIG_ADDR         0x20
  83 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG     0x24
  84 +#define MEMORY_BASE                    0x0
  85 +#define RALINK_PCIE0_RST               (1<<26)
  86 +#define RALINK_PCI_BASE                        0xB0140000
  87 +#define RALINK_PCI_MEMBASE             0x28
  88 +#define RALINK_PCI_IOBASE              0x2C
  89 +
  90 +#define RT6855_PCIE0_OFFSET            0x2000
  91 +
  92 +#define RALINK_PCI_PCICFG_ADDR         0x00
  93 +#define RALINK_PCI0_BAR0SETUP_ADDR     0x10
  94 +#define RALINK_PCI0_IMBASEBAR0_ADDR    0x18
  95 +#define RALINK_PCI0_ID                 0x30
  96 +#define RALINK_PCI0_CLASS              0x34
  97 +#define RALINK_PCI0_SUBID              0x38
  98 +#define RALINK_PCI0_STATUS             0x50
  99 +#define RALINK_PCI_PCIMSK_ADDR         0x0C
 100 +
 101 +#define RALINK_PCIE0_CLK_EN            (1 << 26)
 102 +
 103 +#define BUSY                           0x80000000
 104 +#define WAITRETRY_MAX                  10
 105 +#define WRITE_MODE                     (1UL << 23)
 106 +#define DATA_SHIFT                     0
 107 +#define ADDR_SHIFT                     8
 108 +
 109 +
 110 +static void __iomem *bridge_base;
 111 +static void __iomem *pcie_base;
 112 +
 113 +static struct reset_control *rstpcie0;
 114 +
 115 +static inline void bridge_w32(u32 val, unsigned reg)
 116 +{
 117 +       iowrite32(val, bridge_base + reg);
 118 +}
 119 +
 120 +static inline u32 bridge_r32(unsigned reg)
 121 +{
 122 +       return ioread32(bridge_base + reg);
 123 +}
 124 +
 125 +static inline void pcie_w32(u32 val, unsigned reg)
 126 +{
 127 +       iowrite32(val, pcie_base + reg);
 128 +}
 129 +
 130 +static inline u32 pcie_r32(unsigned reg)
 131 +{
 132 +       return ioread32(pcie_base + reg);
 133 +}
 134 +
 135 +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
 136 +{
 137 +       u32 val = pcie_r32(reg);
 138 +       val &= ~clr;
 139 +       val |= set;
 140 +       pcie_w32(val, reg);
 141 +}
 142 +
 143 +int wait_pciephy_busy(void)
 144 +{
 145 +       unsigned long reg_value = 0x0, retry = 0;
 146 +
 147 +       while (1) {
 148 +               //reg_value = rareg(READMODE, PCIEPHY0_CFG, 0);
 149 +               reg_value = pcie_r32(PCIEPHY0_CFG);
 150 +
 151 +               if (reg_value & BUSY)
 152 +                       mdelay(100);
 153 +               else
 154 +                       break;
 155 +               if (retry++ > WAITRETRY_MAX){
 156 +                       printk("PCIE-PHY retry failed.\n");
 157 +                       return -1;
 158 +               }
 159 +       }
 160 +       return 0;
 161 +}
 162 +
 163 +static void pcie_phy(unsigned long addr, unsigned long val)
 164 +{
 165 +       wait_pciephy_busy();
 166 +       pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
 167 +       mdelay(1);
 168 +       wait_pciephy_busy();
 169 +}
 170 +
 171 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 172 +{
 173 +       unsigned int slot = PCI_SLOT(devfn);
 174 +       u8 func = PCI_FUNC(devfn);
 175 +       u32 address;
 176 +       u32 data;
 177 +
 178 +       address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 179 +       bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 180 +       data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 181 +
 182 +       switch (size) {
 183 +       case 1:
 184 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 185 +               break;
 186 +       case 2:
 187 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 188 +               break;
 189 +       case 4:
 190 +               *val = data;
 191 +               break;
 192 +       }
 193 +
 194 +       return PCIBIOS_SUCCESSFUL;
 195 +}
 196 +
 197 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 198 +{
 199 +       unsigned int slot = PCI_SLOT(devfn);
 200 +       u8 func = PCI_FUNC(devfn);
 201 +       u32 address;
 202 +       u32 data;
 203 +
 204 +       address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 205 +       bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
 206 +       data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 207 +
 208 +       switch (size) {
 209 +       case 1:
 210 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 211 +                       (val << ((where & 3) << 3));
 212 +               break;
 213 +       case 2:
 214 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 215 +                       (val << ((where & 3) << 3));
 216 +               break;
 217 +       case 4:
 218 +               data = val;
 219 +               break;
 220 +       }
 221 +
 222 +       bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 223 +
 224 +       return PCIBIOS_SUCCESSFUL;
 225 +}
 226 +
 227 +struct pci_ops mt7620a_pci_ops= {
 228 +       .read   = pci_config_read,
 229 +       .write  = pci_config_write,
 230 +};
 231 +
 232 +static struct resource mt7620a_res_pci_mem1 = {
 233 +       .name   = "pci memory",
 234 +       .start  = RALINK_PCI_MM_MAP_BASE,
 235 +       .end    = (u32) ((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
 236 +       .flags  = IORESOURCE_MEM,
 237 +};
 238 +static struct resource mt7620a_res_pci_io1 = {
 239 +       .name   = "pci io",
 240 +       .start  = RALINK_PCI_IO_MAP_BASE,
 241 +       .end    = (u32) ((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
 242 +       .flags  = IORESOURCE_IO,
 243 +};
 244 +
 245 +struct pci_controller mt7620a_controller = {
 246 +       .pci_ops        = &mt7620a_pci_ops,
 247 +       .mem_resource   = &mt7620a_res_pci_mem1,
 248 +       .io_resource    = &mt7620a_res_pci_io1,
 249 +       .mem_offset     = 0x00000000UL,
 250 +       .io_offset      = 0x00000000UL,
 251 +       .io_map_base    = 0xa0000000,
 252 +};
 253 +
 254 +static int mt7620a_pci_probe(struct platform_device *pdev)
 255 +{
 256 +       struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 257 +       struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 258 +
 259 +       rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
 260 +       if (IS_ERR(rstpcie0))
 261 +               return PTR_ERR(rstpcie0);
 262 +
 263 +       bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
 264 +        if (!bridge_base)
 265 +               return -ENOMEM;
 266 +
 267 +       pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
 268 +        if (!pcie_base)
 269 +               return -ENOMEM;
 270 +
 271 +       iomem_resource.start = 0;
 272 +       iomem_resource.end= ~0;
 273 +       ioport_resource.start= 0;
 274 +       ioport_resource.end = ~0;
 275 +
 276 +       /* PCIE: bypass PCIe DLL */
 277 +       pcie_phy(0x0, 0x80);
 278 +       pcie_phy(0x1, 0x04);
 279 +       /* PCIE: Elastic buffer control */
 280 +       pcie_phy(0x68, 0xB4);
 281 +
 282 +       reset_control_assert(rstpcie0);
 283 +       rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 284 +       rt_sysc_m32(1<<19, 1<<31, PPLL_DRV);
 285 +       rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
 286 +
 287 +       reset_control_deassert(rstpcie0);
 288 +       rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
 289 +
 290 +       mdelay(100);
 291 +
 292 +       if (!(rt_sysc_r32(PPLL_CFG1) & 1<<23)) {
 293 +               printk("MT7620 PPLL unlock\n");
 294 +               reset_control_assert(rstpcie0);
 295 +               rt_sysc_m32(BIT(26), 0, RALINK_CLKCFG1);
 296 +               return 0;
 297 +       }
 298 +       rt_sysc_m32((0x1<<18) | (0x1<<17), (0x1 << 19) | (0x1 << 31), PPLL_DRV);
 299 +
 300 +       mdelay(100);
 301 +       reset_control_assert(rstpcie0);
 302 +       rt_sysc_m32(0x30, 2 << 4, RALINK_SYSCFG1);
 303 +
 304 +       rt_sysc_m32(~0x7fffffff, 0x80000000, RALINK_PCIE_CLK_GEN);
 305 +       rt_sysc_m32(~0x80ffffff, 0xa << 24, RALINK_PCIE_CLK_GEN1);
 306 +
 307 +       mdelay(50);
 308 +       reset_control_deassert(rstpcie0);
 309 +       pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
 310 +       mdelay(100);
 311 +
 312 +       if (( pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
 313 +               reset_control_assert(rstpcie0);
 314 +               rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
 315 +               rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
 316 +               printk("PCIE0 no card, disable it(RST&CLK)\n");
 317 +       }
 318 +
 319 +       bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
 320 +       bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 321 +
 322 +       pcie_w32(0x7FFF0000, RALINK_PCI0_BAR0SETUP_ADDR);
 323 +       pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
 324 +       pcie_w32(0x08021814, RALINK_PCI0_ID);
 325 +       pcie_w32(0x06040001, RALINK_PCI0_CLASS);
 326 +       pcie_w32(0x28801814, RALINK_PCI0_SUBID);
 327 +       pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
 328 +
 329 +       register_pci_controller(&mt7620a_controller);
 330 +
 331 +       return 0;
 332 +}
 333 +
 334 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 335 +{
 336 +       const struct resource *res;
 337 +       u16 cmd;
 338 +       u32 val;
 339 +       int i, irq = 0;
 340 +
 341 +       if ((dev->bus->number == 0) && (slot == 0)) {
 342 +               pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
 343 +               pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
 344 +               pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
 345 +       } else if ((dev->bus->number == 1) && (slot == 0x0)) {
 346 +               irq = RALINK_INT_PCIE0;
 347 +       } else {
 348 +               printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
 349 +               return 0;
 350 +       }
 351 +
 352 +       for (i = 0; i < 6; i++) {
 353 +               res = &dev->resource[i];
 354 +       }
 355 +
 356 +       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 357 +       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 358 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 359 +
 360 +       // FIXME
 361 +       cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 362 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 363 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 364 +       //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
 365 +
 366 +       return irq;
 367 +}
 368 +
 369 +int pcibios_plat_dev_init(struct pci_dev *dev)
 370 +{
 371 +       return 0;
 372 +}
 373 +
 374 +static const struct of_device_id mt7620a_pci_ids[] = {
 375 +       { .compatible = "ralink,mt7620a-pci" },
 376 +       {},
 377 +};
 378 +MODULE_DEVICE_TABLE(of, mt7620a_pci_ids);
 379 +
 380 +static struct platform_driver mt7620a_pci_driver = {
 381 +       .probe = mt7620a_pci_probe,
 382 +       .driver = {
 383 +               .name = "mt7620a-pci",
 384 +               .owner = THIS_MODULE,
 385 +               .of_match_table = of_match_ptr(mt7620a_pci_ids),
 386 +       },
 387 +};
 388 +
 389 +static int __init mt7620a_pci_init(void)
 390 +{
 391 +       return platform_driver_register(&mt7620a_pci_driver);
 392 +}
 393 +
 394 +arch_initcall(mt7620a_pci_init);
 395 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
 396 index eb2b2cd..ce84aad 100644
 397 --- a/arch/mips/ralink/Kconfig
 398 +++ b/arch/mips/ralink/Kconfig
 399 @@ -39,6 +39,7 @@ choice
 400                 bool "MT7620/8"
 401                 select USB_ARCH_HAS_OHCI
 402                 select USB_ARCH_HAS_EHCI
 403 +               select HW_HAS_PCI
 404
 405         config SOC_MT7621
 406                 bool "MT7621"
 407 --
 408 1.7.10.4
 409