target/linux/ramips/patches-3.14/0054-DMA-ralink-add-rt2880-dma-engine.patch

   1 From cf93418a4bd5e69f069a65da92537bd4d6191223 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 09:29:51 +0100
   4 Subject: [PATCH 54/57] DMA: ralink: add rt2880 dma engine
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/dma/Kconfig       |    6 +
   9  drivers/dma/Makefile      |    1 +
  10  drivers/dma/dmaengine.c   |   26 ++
  11  drivers/dma/ralink-gdma.c |  577 +++++++++++++++++++++++++++++++++++++++++++++
  12  include/linux/dmaengine.h |    1 +
  13  5 files changed, 611 insertions(+)
  14  create mode 100644 drivers/dma/ralink-gdma.c
  15
  16 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
  17 index 605b016..a9b31ff 100644
  18 --- a/drivers/dma/Kconfig
  19 +++ b/drivers/dma/Kconfig
  20 @@ -351,6 +351,12 @@ config MOXART_DMA
  21         help
  22           Enable support for the MOXA ART SoC DMA controller.
  23
  24 +config DMA_RALINK
  25 +       tristate "RALINK DMA support"
  26 +       depends on RALINK && SOC_MT7620
  27 +       select DMA_ENGINE
  28 +       select DMA_VIRTUAL_CHANNELS
  29 +
  30  config DMA_ENGINE
  31         bool
  32
  33 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
  34 index a029d0f4..419ccc2 100644
  35 --- a/drivers/dma/Makefile
  36 +++ b/drivers/dma/Makefile
  37 @@ -44,3 +44,4 @@ obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
  38  obj-$(CONFIG_TI_CPPI41) += cppi41.o
  39  obj-$(CONFIG_K3_DMA) += k3dma.o
  40  obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
  41 +obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o
  42 diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
  43 index ed610b4..cc11e0b 100644
  44 --- a/drivers/dma/dmaengine.c
  45 +++ b/drivers/dma/dmaengine.c
  46 @@ -564,6 +564,32 @@ struct dma_chan *dma_get_any_slave_channel(struct dma_device *device)
  47  EXPORT_SYMBOL_GPL(dma_get_any_slave_channel);
  48
  49  /**
  50 + * dma_request_slave_channel - try to get specific channel exclusively
  51 + * @chan: target channel
  52 + */
  53 +struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
  54 +{
  55 +       int err = -EBUSY;
  56 +
  57 +       /* lock against __dma_request_channel */
  58 +       mutex_lock(&dma_list_mutex);
  59 +
  60 +       if (chan->client_count == 0) {
  61 +               err = dma_chan_get(chan);
  62 +               if (err)
  63 +                       pr_debug("%s: failed to get %s: (%d)\n",
  64 +                               __func__, dma_chan_name(chan), err);
  65 +       } else
  66 +               chan = NULL;
  67 +
  68 +       mutex_unlock(&dma_list_mutex);
  69 +
  70 +       return chan;
  71 +}
  72 +EXPORT_SYMBOL_GPL(dma_get_slave_channel);
  73 +
  74 +
  75 +/**
  76   * __dma_request_channel - try to allocate an exclusive channel
  77   * @mask: capabilities that the channel must satisfy
  78   * @fn: optional callback to disposition available channels
  79 diff --git a/drivers/dma/ralink-gdma.c b/drivers/dma/ralink-gdma.c
  80 new file mode 100644
  81 index 0000000..2c3cace
  82 --- /dev/null
  83 +++ b/drivers/dma/ralink-gdma.c
  84 @@ -0,0 +1,577 @@
  85 +/*
  86 + *  Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
  87 + *  GDMA4740 DMAC support
  88 + *
  89 + *  This program is free software; you can redistribute it and/or modify it
  90 + *  under  the terms of the GNU General         Public License as published by the
  91 + *  Free Software Foundation;  either version 2 of the License, or (at your
  92 + *  option) any later version.
  93 + *
  94 + *  You should have received a copy of the GNU General Public License along
  95 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  96 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  97 + *
  98 + */
  99 +
 100 +#include <linux/dmaengine.h>
 101 +#include <linux/dma-mapping.h>
 102 +#include <linux/err.h>
 103 +#include <linux/init.h>
 104 +#include <linux/list.h>
 105 +#include <linux/module.h>
 106 +#include <linux/platform_device.h>
 107 +#include <linux/slab.h>
 108 +#include <linux/spinlock.h>
 109 +#include <linux/irq.h>
 110 +#include <linux/of_dma.h>
 111 +
 112 +#include "virt-dma.h"
 113 +
 114 +#define GDMA_NR_CHANS                  16
 115 +
 116 +#define GDMA_REG_SRC_ADDR(x)           (0x00 + (x) * 0x10)
 117 +#define GDMA_REG_DST_ADDR(x)           (0x04 + (x) * 0x10)
 118 +
 119 +#define GDMA_REG_CTRL0(x)              (0x08 + (x) * 0x10)
 120 +#define GDMA_REG_CTRL0_TX_MASK         0xffff
 121 +#define GDMA_REG_CTRL0_TX_SHIFT                16
 122 +#define GDMA_REG_CTRL0_CURR_MASK       0xff
 123 +#define GDMA_REG_CTRL0_CURR_SHIFT      8
 124 +#define        GDMA_REG_CTRL0_SRC_ADDR_FIXED   BIT(7)
 125 +#define GDMA_REG_CTRL0_DST_ADDR_FIXED  BIT(6)
 126 +#define GDMA_REG_CTRL0_BURST_MASK      0x7
 127 +#define GDMA_REG_CTRL0_BURST_SHIFT     3
 128 +#define        GDMA_REG_CTRL0_DONE_INT         BIT(2)
 129 +#define        GDMA_REG_CTRL0_ENABLE           BIT(1)
 130 +#define        GDMA_REG_CTRL0_HW_MODE          0
 131 +
 132 +#define GDMA_REG_CTRL1(x)              (0x0c + (x) * 0x10)
 133 +#define GDMA_REG_CTRL1_SEG_MASK                0xf
 134 +#define GDMA_REG_CTRL1_SEG_SHIFT       22
 135 +#define GDMA_REG_CTRL1_REQ_MASK                0x3f
 136 +#define GDMA_REG_CTRL1_SRC_REQ_SHIFT   16
 137 +#define GDMA_REG_CTRL1_DST_REQ_SHIFT   8
 138 +#define GDMA_REG_CTRL1_CONTINOUS       BIT(14)
 139 +#define GDMA_REG_CTRL1_NEXT_MASK       0x1f
 140 +#define GDMA_REG_CTRL1_NEXT_SHIFT      3
 141 +#define GDMA_REG_CTRL1_COHERENT                BIT(2)
 142 +#define GDMA_REG_CTRL1_FAIL            BIT(1)
 143 +#define GDMA_REG_CTRL1_MASK            BIT(0)
 144 +
 145 +#define GDMA_REG_UNMASK_INT            0x200
 146 +#define GDMA_REG_DONE_INT              0x204
 147 +
 148 +#define GDMA_REG_GCT                   0x220
 149 +#define GDMA_REG_GCT_CHAN_MASK         0x3
 150 +#define GDMA_REG_GCT_CHAN_SHIFT                3
 151 +#define GDMA_REG_GCT_VER_MASK          0x3
 152 +#define GDMA_REG_GCT_VER_SHIFT         1
 153 +#define GDMA_REG_GCT_ARBIT_RR          BIT(0)
 154 +
 155 +enum gdma_dma_transfer_size {
 156 +       GDMA_TRANSFER_SIZE_4BYTE        = 0,
 157 +       GDMA_TRANSFER_SIZE_8BYTE        = 1,
 158 +       GDMA_TRANSFER_SIZE_16BYTE       = 2,
 159 +       GDMA_TRANSFER_SIZE_32BYTE       = 3,
 160 +};
 161 +
 162 +struct gdma_dma_sg {
 163 +       dma_addr_t addr;
 164 +       unsigned int len;
 165 +};
 166 +
 167 +struct gdma_dma_desc {
 168 +       struct virt_dma_desc vdesc;
 169 +
 170 +       enum dma_transfer_direction direction;
 171 +       bool cyclic;
 172 +
 173 +       unsigned int num_sgs;
 174 +       struct gdma_dma_sg sg[];
 175 +};
 176 +
 177 +struct gdma_dmaengine_chan {
 178 +       struct virt_dma_chan vchan;
 179 +       unsigned int id;
 180 +
 181 +       dma_addr_t fifo_addr;
 182 +       unsigned int transfer_shift;
 183 +
 184 +       struct gdma_dma_desc *desc;
 185 +       unsigned int next_sg;
 186 +};
 187 +
 188 +struct gdma_dma_dev {
 189 +       struct dma_device ddev;
 190 +       void __iomem *base;
 191 +       struct clk *clk;
 192 +
 193 +       struct gdma_dmaengine_chan chan[GDMA_NR_CHANS];
 194 +};
 195 +
 196 +static struct gdma_dma_dev *gdma_dma_chan_get_dev(
 197 +       struct gdma_dmaengine_chan *chan)
 198 +{
 199 +       return container_of(chan->vchan.chan.device, struct gdma_dma_dev,
 200 +               ddev);
 201 +}
 202 +
 203 +static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c)
 204 +{
 205 +       return container_of(c, struct gdma_dmaengine_chan, vchan.chan);
 206 +}
 207 +
 208 +static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc)
 209 +{
 210 +       return container_of(vdesc, struct gdma_dma_desc, vdesc);
 211 +}
 212 +
 213 +static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
 214 +       unsigned int reg)
 215 +{
 216 +       return readl(dma_dev->base + reg);
 217 +}
 218 +
 219 +static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
 220 +       unsigned reg, uint32_t val)
 221 +{
 222 +       //printk("gdma --> %p = 0x%08X\n", dma_dev->base + reg, val);
 223 +       writel(val, dma_dev->base + reg);
 224 +}
 225 +
 226 +static inline void gdma_dma_write_mask(struct gdma_dma_dev *dma_dev,
 227 +       unsigned int reg, uint32_t val, uint32_t mask)
 228 +{
 229 +       uint32_t tmp;
 230 +
 231 +       tmp = gdma_dma_read(dma_dev, reg);
 232 +       tmp &= ~mask;
 233 +       tmp |= val;
 234 +       gdma_dma_write(dma_dev, reg, tmp);
 235 +}
 236 +
 237 +static struct gdma_dma_desc *gdma_dma_alloc_desc(unsigned int num_sgs)
 238 +{
 239 +       return kzalloc(sizeof(struct gdma_dma_desc) +
 240 +               sizeof(struct gdma_dma_sg) * num_sgs, GFP_ATOMIC);
 241 +}
 242 +
 243 +static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst)
 244 +{
 245 +       if (maxburst <= 7)
 246 +               return GDMA_TRANSFER_SIZE_4BYTE;
 247 +       else if (maxburst <= 15)
 248 +               return GDMA_TRANSFER_SIZE_8BYTE;
 249 +       else if (maxburst <= 31)
 250 +               return GDMA_TRANSFER_SIZE_16BYTE;
 251 +
 252 +       return GDMA_TRANSFER_SIZE_32BYTE;
 253 +}
 254 +
 255 +static int gdma_dma_slave_config(struct dma_chan *c,
 256 +       const struct dma_slave_config *config)
 257 +{
 258 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 259 +       struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
 260 +       enum gdma_dma_transfer_size transfer_size;
 261 +       uint32_t flags;
 262 +       uint32_t ctrl0, ctrl1;
 263 +
 264 +       switch (config->direction) {
 265 +       case DMA_MEM_TO_DEV:
 266 +               ctrl1 = 32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
 267 +               ctrl1 |= config->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT;
 268 +               flags = GDMA_REG_CTRL0_DST_ADDR_FIXED;
 269 +               transfer_size = gdma_dma_maxburst(config->dst_maxburst);
 270 +               chan->fifo_addr = config->dst_addr;
 271 +               break;
 272 +
 273 +       case DMA_DEV_TO_MEM:
 274 +               ctrl1 = config->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
 275 +               ctrl1 |= 32 << GDMA_REG_CTRL1_DST_REQ_SHIFT;
 276 +               flags = GDMA_REG_CTRL0_SRC_ADDR_FIXED;
 277 +               transfer_size = gdma_dma_maxburst(config->src_maxburst);
 278 +               chan->fifo_addr = config->src_addr;
 279 +               break;
 280 +
 281 +       default:
 282 +               return -EINVAL;
 283 +       }
 284 +
 285 +       chan->transfer_shift = 1 + transfer_size;
 286 +
 287 +       ctrl0 = flags | GDMA_REG_CTRL0_HW_MODE;
 288 +       ctrl0 |= GDMA_REG_CTRL0_DONE_INT;
 289 +
 290 +       ctrl1 &= ~(GDMA_REG_CTRL1_NEXT_MASK << GDMA_REG_CTRL1_NEXT_SHIFT);
 291 +       ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
 292 +       ctrl1 |= GDMA_REG_CTRL1_FAIL;
 293 +       ctrl1 &= ~GDMA_REG_CTRL1_CONTINOUS;
 294 +       gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
 295 +       gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
 296 +
 297 +       return 0;
 298 +}
 299 +
 300 +static int gdma_dma_terminate_all(struct dma_chan *c)
 301 +{
 302 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 303 +       struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
 304 +       unsigned long flags;
 305 +       LIST_HEAD(head);
 306 +
 307 +       spin_lock_irqsave(&chan->vchan.lock, flags);
 308 +       gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
 309 +                       GDMA_REG_CTRL0_ENABLE);
 310 +       chan->desc = NULL;
 311 +       vchan_get_all_descriptors(&chan->vchan, &head);
 312 +       spin_unlock_irqrestore(&chan->vchan.lock, flags);
 313 +
 314 +       vchan_dma_desc_free_list(&chan->vchan, &head);
 315 +
 316 +       return 0;
 317 +}
 318 +
 319 +static int gdma_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 320 +       unsigned long arg)
 321 +{
 322 +       struct dma_slave_config *config = (struct dma_slave_config *)arg;
 323 +
 324 +       switch (cmd) {
 325 +       case DMA_SLAVE_CONFIG:
 326 +               return gdma_dma_slave_config(chan, config);
 327 +       case DMA_TERMINATE_ALL:
 328 +               return gdma_dma_terminate_all(chan);
 329 +       default:
 330 +               return -ENOSYS;
 331 +       }
 332 +}
 333 +
 334 +static int gdma_dma_start_transfer(struct gdma_dmaengine_chan *chan)
 335 +{
 336 +       struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
 337 +       dma_addr_t src_addr, dst_addr;
 338 +       struct virt_dma_desc *vdesc;
 339 +       struct gdma_dma_sg *sg;
 340 +
 341 +       gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
 342 +                       GDMA_REG_CTRL0_ENABLE);
 343 +
 344 +       if (!chan->desc) {
 345 +               vdesc = vchan_next_desc(&chan->vchan);
 346 +               if (!vdesc)
 347 +                       return 0;
 348 +               chan->desc = to_gdma_dma_desc(vdesc);
 349 +               chan->next_sg = 0;
 350 +       }
 351 +
 352 +       if (chan->next_sg == chan->desc->num_sgs)
 353 +               chan->next_sg = 0;
 354 +
 355 +       sg = &chan->desc->sg[chan->next_sg];
 356 +
 357 +       if (chan->desc->direction == DMA_MEM_TO_DEV) {
 358 +               src_addr = sg->addr;
 359 +               dst_addr = chan->fifo_addr;
 360 +       } else {
 361 +               src_addr = chan->fifo_addr;
 362 +               dst_addr = sg->addr;
 363 +       }
 364 +       gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
 365 +       gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
 366 +       gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id),
 367 +                       (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | GDMA_REG_CTRL0_ENABLE,
 368 +                       GDMA_REG_CTRL0_TX_MASK << GDMA_REG_CTRL0_TX_SHIFT);
 369 +       chan->next_sg++;
 370 +       gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL1(chan->id), 0, GDMA_REG_CTRL1_MASK);
 371 +
 372 +       return 0;
 373 +}
 374 +
 375 +static void gdma_dma_chan_irq(struct gdma_dmaengine_chan *chan)
 376 +{
 377 +       spin_lock(&chan->vchan.lock);
 378 +       if (chan->desc) {
 379 +               if (chan->desc && chan->desc->cyclic) {
 380 +                       vchan_cyclic_callback(&chan->desc->vdesc);
 381 +               } else {
 382 +                       if (chan->next_sg == chan->desc->num_sgs) {
 383 +                               chan->desc = NULL;
 384 +                               vchan_cookie_complete(&chan->desc->vdesc);
 385 +                       }
 386 +               }
 387 +       }
 388 +       gdma_dma_start_transfer(chan);
 389 +       spin_unlock(&chan->vchan.lock);
 390 +}
 391 +
 392 +static irqreturn_t gdma_dma_irq(int irq, void *devid)
 393 +{
 394 +       struct gdma_dma_dev *dma_dev = devid;
 395 +       uint32_t unmask, done;
 396 +       unsigned int i;
 397 +
 398 +       unmask = gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT);
 399 +       gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, unmask);
 400 +       done = gdma_dma_read(dma_dev, GDMA_REG_DONE_INT);
 401 +
 402 +       for (i = 0; i < GDMA_NR_CHANS; ++i)
 403 +               if (done & BIT(i))
 404 +                       gdma_dma_chan_irq(&dma_dev->chan[i]);
 405 +       gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, done);
 406 +
 407 +       return IRQ_HANDLED;
 408 +}
 409 +
 410 +static void gdma_dma_issue_pending(struct dma_chan *c)
 411 +{
 412 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 413 +       unsigned long flags;
 414 +
 415 +       spin_lock_irqsave(&chan->vchan.lock, flags);
 416 +       if (vchan_issue_pending(&chan->vchan) && !chan->desc)
 417 +               gdma_dma_start_transfer(chan);
 418 +       spin_unlock_irqrestore(&chan->vchan.lock, flags);
 419 +}
 420 +
 421 +static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg(
 422 +       struct dma_chan *c, struct scatterlist *sgl,
 423 +       unsigned int sg_len, enum dma_transfer_direction direction,
 424 +       unsigned long flags, void *context)
 425 +{
 426 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 427 +       struct gdma_dma_desc *desc;
 428 +       struct scatterlist *sg;
 429 +       unsigned int i;
 430 +
 431 +       desc = gdma_dma_alloc_desc(sg_len);
 432 +       if (!desc)
 433 +               return NULL;
 434 +
 435 +       for_each_sg(sgl, sg, sg_len, i) {
 436 +               desc->sg[i].addr = sg_dma_address(sg);
 437 +               desc->sg[i].len = sg_dma_len(sg);
 438 +       }
 439 +
 440 +       desc->num_sgs = sg_len;
 441 +       desc->direction = direction;
 442 +       desc->cyclic = false;
 443 +
 444 +       return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 445 +}
 446 +
 447 +static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic(
 448 +       struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
 449 +       size_t period_len, enum dma_transfer_direction direction,
 450 +       unsigned long flags, void *context)
 451 +{
 452 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 453 +       struct gdma_dma_desc *desc;
 454 +       unsigned int num_periods, i;
 455 +
 456 +       if (buf_len % period_len)
 457 +               return NULL;
 458 +
 459 +       num_periods = buf_len / period_len;
 460 +
 461 +       desc = gdma_dma_alloc_desc(num_periods);
 462 +       if (!desc)
 463 +               return NULL;
 464 +
 465 +       for (i = 0; i < num_periods; i++) {
 466 +               desc->sg[i].addr = buf_addr;
 467 +               desc->sg[i].len = period_len;
 468 +               buf_addr += period_len;
 469 +       }
 470 +
 471 +       desc->num_sgs = num_periods;
 472 +       desc->direction = direction;
 473 +       desc->cyclic = true;
 474 +
 475 +       return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 476 +}
 477 +
 478 +static size_t gdma_dma_desc_residue(struct gdma_dmaengine_chan *chan,
 479 +       struct gdma_dma_desc *desc, unsigned int next_sg)
 480 +{
 481 +       struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
 482 +       unsigned int residue, count;
 483 +       unsigned int i;
 484 +
 485 +       residue = 0;
 486 +
 487 +       for (i = next_sg; i < desc->num_sgs; i++)
 488 +               residue += desc->sg[i].len;
 489 +
 490 +       if (next_sg != 0) {
 491 +               count = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
 492 +               count >>= GDMA_REG_CTRL0_CURR_SHIFT;
 493 +               count &= GDMA_REG_CTRL0_CURR_MASK;
 494 +               residue += count << chan->transfer_shift;
 495 +       }
 496 +
 497 +       return residue;
 498 +}
 499 +
 500 +static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
 501 +       dma_cookie_t cookie, struct dma_tx_state *state)
 502 +{
 503 +       struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
 504 +       struct virt_dma_desc *vdesc;
 505 +       enum dma_status status;
 506 +       unsigned long flags;
 507 +
 508 +       status = dma_cookie_status(c, cookie, state);
 509 +       if (status == DMA_SUCCESS || !state)
 510 +               return status;
 511 +
 512 +       spin_lock_irqsave(&chan->vchan.lock, flags);
 513 +       vdesc = vchan_find_desc(&chan->vchan, cookie);
 514 +       if (cookie == chan->desc->vdesc.tx.cookie) {
 515 +               state->residue = gdma_dma_desc_residue(chan, chan->desc,
 516 +                               chan->next_sg);
 517 +       } else if (vdesc) {
 518 +               state->residue = gdma_dma_desc_residue(chan,
 519 +                               to_gdma_dma_desc(vdesc), 0);
 520 +       } else {
 521 +               state->residue = 0;
 522 +       }
 523 +       spin_unlock_irqrestore(&chan->vchan.lock, flags);
 524 +
 525 +       return status;
 526 +}
 527 +
 528 +static int gdma_dma_alloc_chan_resources(struct dma_chan *c)
 529 +{
 530 +       return 0;
 531 +}
 532 +
 533 +static void gdma_dma_free_chan_resources(struct dma_chan *c)
 534 +{
 535 +       vchan_free_chan_resources(to_virt_chan(c));
 536 +}
 537 +
 538 +static void gdma_dma_desc_free(struct virt_dma_desc *vdesc)
 539 +{
 540 +       kfree(container_of(vdesc, struct gdma_dma_desc, vdesc));
 541 +}
 542 +
 543 +static struct dma_chan *
 544 +of_dma_xlate_by_chan_id(struct of_phandle_args *dma_spec,
 545 +                       struct of_dma *ofdma)
 546 +{
 547 +       struct gdma_dma_dev *dma_dev = ofdma->of_dma_data;
 548 +       unsigned int request = dma_spec->args[0];
 549 +
 550 +       if (request >= GDMA_NR_CHANS)
 551 +               return NULL;
 552 +
 553 +       return dma_get_slave_channel(&(dma_dev->chan[request].vchan.chan));
 554 +}
 555 +
 556 +static int gdma_dma_probe(struct platform_device *pdev)
 557 +{
 558 +       struct gdma_dmaengine_chan *chan;
 559 +       struct gdma_dma_dev *dma_dev;
 560 +       struct dma_device *dd;
 561 +       unsigned int i;
 562 +       struct resource *res;
 563 +       uint32_t gct;
 564 +       int ret;
 565 +       int irq;
 566 +
 567 +
 568 +       dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev), GFP_KERNEL);
 569 +       if (!dma_dev)
 570 +               return -EINVAL;
 571 +
 572 +       dd = &dma_dev->ddev;
 573 +
 574 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 575 +       dma_dev->base = devm_ioremap_resource(&pdev->dev, res);
 576 +       if (IS_ERR(dma_dev->base))
 577 +               return PTR_ERR(dma_dev->base);
 578 +
 579 +       dma_cap_set(DMA_SLAVE, dd->cap_mask);
 580 +       dma_cap_set(DMA_CYCLIC, dd->cap_mask);
 581 +       dd->device_alloc_chan_resources = gdma_dma_alloc_chan_resources;
 582 +       dd->device_free_chan_resources = gdma_dma_free_chan_resources;
 583 +       dd->device_tx_status = gdma_dma_tx_status;
 584 +       dd->device_issue_pending = gdma_dma_issue_pending;
 585 +       dd->device_prep_slave_sg = gdma_dma_prep_slave_sg;
 586 +       dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic;
 587 +       dd->device_control = gdma_dma_control;
 588 +       dd->dev = &pdev->dev;
 589 +       dd->chancnt = GDMA_NR_CHANS;
 590 +       INIT_LIST_HEAD(&dd->channels);
 591 +
 592 +       for (i = 0; i < dd->chancnt; i++) {
 593 +               chan = &dma_dev->chan[i];
 594 +               chan->id = i;
 595 +               chan->vchan.desc_free = gdma_dma_desc_free;
 596 +               vchan_init(&chan->vchan, dd);
 597 +       }
 598 +
 599 +       ret = dma_async_device_register(dd);
 600 +       if (ret)
 601 +               return ret;
 602 +
 603 +       ret = of_dma_controller_register(pdev->dev.of_node,
 604 +               of_dma_xlate_by_chan_id, dma_dev);
 605 +       if (ret)
 606 +               goto err_unregister;
 607 +
 608 +       irq = platform_get_irq(pdev, 0);
 609 +       ret = request_irq(irq, gdma_dma_irq, 0, dev_name(&pdev->dev), dma_dev);
 610 +       if (ret)
 611 +               goto err_unregister;
 612 +
 613 +       gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, 0);
 614 +       gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, BIT(dd->chancnt) - 1);
 615 +
 616 +       gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
 617 +       dev_info(&pdev->dev, "revision: %d, channels: %d\n",
 618 +               (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
 619 +               8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) & GDMA_REG_GCT_CHAN_MASK));
 620 +       platform_set_drvdata(pdev, dma_dev);
 621 +
 622 +       gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR);
 623 +
 624 +       return 0;
 625 +
 626 +err_unregister:
 627 +       dma_async_device_unregister(dd);
 628 +       return ret;
 629 +}
 630 +
 631 +static int gdma_dma_remove(struct platform_device *pdev)
 632 +{
 633 +       struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev);
 634 +       int irq = platform_get_irq(pdev, 0);
 635 +
 636 +       free_irq(irq, dma_dev);
 637 +        of_dma_controller_free(pdev->dev.of_node);
 638 +       dma_async_device_unregister(&dma_dev->ddev);
 639 +
 640 +       return 0;
 641 +}
 642 +
 643 +static const struct of_device_id gdma_of_match_table[] = {
 644 +       { .compatible = "ralink,rt2880-gdma" },
 645 +       { },
 646 +};
 647 +
 648 +static struct platform_driver gdma_dma_driver = {
 649 +       .probe = gdma_dma_probe,
 650 +       .remove = gdma_dma_remove,
 651 +       .driver = {
 652 +               .name = "gdma-rt2880",
 653 +               .owner = THIS_MODULE,
 654 +               .of_match_table = gdma_of_match_table,
 655 +       },
 656 +};
 657 +module_platform_driver(gdma_dma_driver);
 658 +
 659 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 660 +MODULE_DESCRIPTION("GDMA4740 DMA driver");
 661 +MODULE_LICENSE("GPLv2");
 662 diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
 663 index c5c92d5..482131e 100644
 664 --- a/include/linux/dmaengine.h
 665 +++ b/include/linux/dmaengine.h
 666 @@ -1072,6 +1072,7 @@ struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
 667                                                   const char *name);
 668  struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
 669  void dma_release_channel(struct dma_chan *chan);
 670 +struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
 671  #else
 672  static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
 673  {
 674 --
 675 1.7.10.4
 676