target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch

   1 --- a/drivers/spi/Kconfig
   2 +++ b/drivers/spi/Kconfig
   3 @@ -439,6 +439,12 @@
   4         help
   5           This selects a driver for the Ralink RT288x/RT305x SPI Controller.
   6
   7 +config SPI_MT7621
   8 +       tristate "MediaTek MT7621 SPI Controller"
   9 +       depends on RALINK
  10 +       help
  11 +         This selects a driver for the MediaTek MT7621 SPI Controller.
  12 +
  13  config SPI_S3C24XX
  14         tristate "Samsung S3C24XX series SPI"
  15         depends on ARCH_S3C24XX
  16 --- a/drivers/spi/Makefile
  17 +++ b/drivers/spi/Makefile
  18 @@ -46,6 +46,7 @@
  19  obj-$(CONFIG_SPI_MPC512x_PSC)          += spi-mpc512x-psc.o
  20  obj-$(CONFIG_SPI_MPC52xx_PSC)          += spi-mpc52xx-psc.o
  21  obj-$(CONFIG_SPI_MPC52xx)              += spi-mpc52xx.o
  22 +obj-$(CONFIG_SPI_MT7621)               += spi-mt7621.o
  23  obj-$(CONFIG_SPI_MXS)                  += spi-mxs.o
  24  obj-$(CONFIG_SPI_NUC900)               += spi-nuc900.o
  25  obj-$(CONFIG_SPI_OC_TINY)              += spi-oc-tiny.o
  26 --- /dev/null
  27 +++ b/drivers/spi/spi-mt7621.c
  28 @@ -0,0 +1,480 @@
  29 +/*
  30 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
  31 + *
  32 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  33 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  34 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@openwrt.org>
  35 + *
  36 + * Some parts are based on spi-orion.c:
  37 + *   Author: Shadi Ammouri <shadi@marvell.com>
  38 + *   Copyright (C) 2007-2008 Marvell Ltd.
  39 + *
  40 + * This program is free software; you can redistribute it and/or modify
  41 + * it under the terms of the GNU General Public License version 2 as
  42 + * published by the Free Software Foundation.
  43 + */
  44 +
  45 +#include <linux/init.h>
  46 +#include <linux/module.h>
  47 +#include <linux/clk.h>
  48 +#include <linux/err.h>
  49 +#include <linux/delay.h>
  50 +#include <linux/io.h>
  51 +#include <linux/reset.h>
  52 +#include <linux/spi/spi.h>
  53 +#include <linux/of_device.h>
  54 +#include <linux/platform_device.h>
  55 +#include <linux/swab.h>
  56 +
  57 +#include <ralink_regs.h>
  58 +
  59 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
  60 +
  61 +#define DRIVER_NAME                    "spi-mt7621"
  62 +/* in usec */
  63 +#define RALINK_SPI_WAIT_MAX_LOOP       2000
  64 +
  65 +/* SPISTAT register bit field */
  66 +#define SPISTAT_BUSY                   BIT(0)
  67 +
  68 +#define MT7621_SPI_TRANS       0x00
  69 +#define SPITRANS_BUSY          BIT(16)
  70 +
  71 +#define MT7621_SPI_OPCODE      0x04
  72 +#define MT7621_SPI_DATA0       0x08
  73 +#define MT7621_SPI_DATA4       0x18
  74 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
  75 +#define SPI_CTL_START          BIT(8)
  76 +
  77 +#define MT7621_SPI_POLAR       0x38
  78 +#define MT7621_SPI_MASTER      0x28
  79 +#define MT7621_SPI_MOREBUF     0x2c
  80 +#define MT7621_SPI_SPACE       0x3c
  81 +
  82 +#define MT7621_CPHA            BIT(5)
  83 +#define MT7621_CPOL            BIT(4)
  84 +#define MT7621_LSB_FIRST       BIT(3)
  85 +
  86 +#define RT2880_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
  87 +
  88 +struct mt7621_spi;
  89 +
  90 +struct mt7621_spi {
  91 +       struct spi_master       *master;
  92 +       void __iomem            *base;
  93 +       unsigned int            sys_freq;
  94 +       unsigned int            speed;
  95 +       struct clk              *clk;
  96 +       spinlock_t              lock;
  97 +
  98 +       struct mt7621_spi_ops   *ops;
  99 +};
 100 +
 101 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
 102 +{
 103 +       return spi_master_get_devdata(spi->master);
 104 +}
 105 +
 106 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
 107 +{
 108 +       return ioread32(rs->base + reg);
 109 +}
 110 +
 111 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
 112 +{
 113 +       iowrite32(val, rs->base + reg);
 114 +}
 115 +
 116 +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
 117 +{
 118 +       u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
 119 +
 120 +       master |= 7 << 29;
 121 +       master |= 1 << 2;
 122 +       if (duplex)
 123 +               master |= 1 << 10;
 124 +       else
 125 +               master &= ~(1 << 10);
 126 +
 127 +       mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
 128 +}
 129 +
 130 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
 131 +{
 132 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 133 +       int cs = spi->chip_select;
 134 +       u32 polar = 0;
 135 +
 136 +        mt7621_spi_reset(rs, cs);
 137 +       if (enable)
 138 +               polar = BIT(cs);
 139 +       mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
 140 +}
 141 +
 142 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
 143 +{
 144 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 145 +       u32 rate;
 146 +       u32 reg;
 147 +
 148 +       dev_dbg(&spi->dev, "speed:%u\n", speed);
 149 +
 150 +       rate = DIV_ROUND_UP(rs->sys_freq, speed);
 151 +       dev_dbg(&spi->dev, "rate-1:%u\n", rate);
 152 +
 153 +       if (rate > 4097)
 154 +               return -EINVAL;
 155 +
 156 +       if (rate < 2)
 157 +               rate = 2;
 158 +
 159 +       reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
 160 +       reg &= ~(0xfff << 16);
 161 +       reg |= (rate - 2) << 16;
 162 +       rs->speed = speed;
 163 +
 164 +       reg &= ~MT7621_LSB_FIRST;
 165 +       if (spi->mode & SPI_LSB_FIRST)
 166 +               reg |= MT7621_LSB_FIRST;
 167 +
 168 +       reg &= ~(MT7621_CPHA | MT7621_CPOL);
 169 +       switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
 170 +               case SPI_MODE_0:
 171 +                       break;
 172 +               case SPI_MODE_1:
 173 +                       reg |= MT7621_CPHA;
 174 +                       break;
 175 +               case SPI_MODE_2:
 176 +                       reg |= MT7621_CPOL;
 177 +                       break;
 178 +               case SPI_MODE_3:
 179 +                       reg |= MT7621_CPOL | MT7621_CPHA;
 180 +                       break;
 181 +       }
 182 +       mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
 183 +
 184 +       return 0;
 185 +}
 186 +
 187 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
 188 +{
 189 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 190 +       int i;
 191 +
 192 +       for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 193 +               u32 status;
 194 +
 195 +               status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 196 +               if ((status & SPITRANS_BUSY) == 0) {
 197 +                       return 0;
 198 +               }
 199 +               cpu_relax();
 200 +               udelay(1);
 201 +       }
 202 +
 203 +       return -ETIMEDOUT;
 204 +}
 205 +
 206 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
 207 +                                          struct spi_message *m)
 208 +{
 209 +       struct mt7621_spi *rs = spi_master_get_devdata(master);
 210 +       struct spi_device *spi = m->spi;
 211 +       unsigned int speed = spi->max_speed_hz;
 212 +       struct spi_transfer *t = NULL;
 213 +       int status = 0;
 214 +       int i, len = 0;
 215 +       int rx_len = 0;
 216 +       u32 data[9] = { 0 };
 217 +       u32 val;
 218 +
 219 +       mt7621_spi_wait_till_ready(spi);
 220 +
 221 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 222 +               const u8 *buf = t->tx_buf;
 223 +
 224 +               if (t->rx_buf)
 225 +                       rx_len += t->len;
 226 +
 227 +               if (!buf)
 228 +                       continue;
 229 +
 230 +               if (WARN_ON(len + t->len > 36)) {
 231 +                       status = -EIO;
 232 +                       goto msg_done;
 233 +               }
 234 +
 235 +               for (i = 0; i < t->len; i++, len++)
 236 +                       data[len / 4] |= buf[i] << (8 * (len & 3));
 237 +       }
 238 +
 239 +       if (WARN_ON(rx_len > 32)) {
 240 +               status = -EIO;
 241 +               goto msg_done;
 242 +       }
 243 +
 244 +       if (mt7621_spi_prepare(spi, speed)) {
 245 +               status = -EIO;
 246 +               goto msg_done;
 247 +       }
 248 +       data[0] = swab32(data[0]);
 249 +       if (len < 4)
 250 +               data[0] >>= (4 - len) * 8;
 251 +
 252 +       for (i = 0; i < len; i += 4)
 253 +               mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
 254 +
 255 +       val = (min_t(int, len, 4) * 8) << 24;
 256 +       if (len > 4)
 257 +               val |= (len - 4) * 8;
 258 +       val |= (rx_len * 8) << 12;
 259 +       mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
 260 +
 261 +       mt7621_spi_set_cs(spi, 1);
 262 +
 263 +       val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 264 +       val |= SPI_CTL_START;
 265 +       mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
 266 +
 267 +       mt7621_spi_wait_till_ready(spi);
 268 +
 269 +       mt7621_spi_set_cs(spi, 0);
 270 +
 271 +       for (i = 0; i < rx_len; i += 4)
 272 +               data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
 273 +
 274 +       m->actual_length = len + rx_len;
 275 +
 276 +       len = 0;
 277 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 278 +               u8 *buf = t->rx_buf;
 279 +
 280 +               if (!buf)
 281 +                       continue;
 282 +
 283 +               for (i = 0; i < t->len; i++, len++)
 284 +                       buf[i] = data[len / 4] >> (8 * (len & 3));
 285 +       }
 286 +
 287 +msg_done:
 288 +       m->status = status;
 289 +       spi_finalize_current_message(master);
 290 +
 291 +       return 0;
 292 +}
 293 +
 294 +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
 295 +                                          struct spi_message *m)
 296 +{
 297 +       struct mt7621_spi *rs = spi_master_get_devdata(master);
 298 +       struct spi_device *spi = m->spi;
 299 +       unsigned int speed = spi->max_speed_hz;
 300 +       struct spi_transfer *t = NULL;
 301 +       int status = 0;
 302 +       int i, len = 0;
 303 +       int rx_len = 0;
 304 +       u32 data[9] = { 0 };
 305 +       u32 val = 0;
 306 +
 307 +       mt7621_spi_wait_till_ready(spi);
 308 +
 309 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 310 +               const u8 *buf = t->tx_buf;
 311 +
 312 +               if (t->rx_buf)
 313 +                       rx_len += t->len;
 314 +
 315 +               if (!buf)
 316 +                       continue;
 317 +
 318 +               if (WARN_ON(len + t->len > 16)) {
 319 +                       status = -EIO;
 320 +                       goto msg_done;
 321 +               }
 322 +
 323 +               for (i = 0; i < t->len; i++, len++)
 324 +                       data[len / 4] |= buf[i] << (8 * (len & 3));
 325 +               if (speed > t->speed_hz)
 326 +                       speed = t->speed_hz;
 327 +       }
 328 +
 329 +       if (WARN_ON(rx_len > 16)) {
 330 +               status = -EIO;
 331 +               goto msg_done;
 332 +       }
 333 +
 334 +       if (mt7621_spi_prepare(spi, speed)) {
 335 +               status = -EIO;
 336 +               goto msg_done;
 337 +       }
 338 +
 339 +       for (i = 0; i < len; i += 4)
 340 +               mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
 341 +
 342 +       val |= len * 8;
 343 +       val |= (rx_len * 8) << 12;
 344 +       mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
 345 +
 346 +       mt7621_spi_set_cs(spi, 1);
 347 +
 348 +       val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 349 +       val |= SPI_CTL_START;
 350 +       mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
 351 +
 352 +       mt7621_spi_wait_till_ready(spi);
 353 +
 354 +       mt7621_spi_set_cs(spi, 0);
 355 +
 356 +       for (i = 0; i < rx_len; i += 4)
 357 +               data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
 358 +
 359 +       m->actual_length = rx_len;
 360 +
 361 +       len = 0;
 362 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 363 +               u8 *buf = t->rx_buf;
 364 +
 365 +               if (!buf)
 366 +                       continue;
 367 +
 368 +               for (i = 0; i < t->len; i++, len++)
 369 +                       buf[i] = data[len / 4] >> (8 * (len & 3));
 370 +       }
 371 +
 372 +msg_done:
 373 +       m->status = status;
 374 +       spi_finalize_current_message(master);
 375 +
 376 +       return 0;
 377 +}
 378 +
 379 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
 380 +                                          struct spi_message *m)
 381 +{
 382 +       struct spi_device *spi = m->spi;
 383 +       int cs = spi->chip_select;
 384 +
 385 +       if (cs)
 386 +               return mt7621_spi_transfer_full_duplex(master, m);
 387 +       return mt7621_spi_transfer_half_duplex(master, m);
 388 +}
 389 +
 390 +static int mt7621_spi_setup(struct spi_device *spi)
 391 +{
 392 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 393 +
 394 +       if ((spi->max_speed_hz == 0) ||
 395 +               (spi->max_speed_hz > (rs->sys_freq / 2)))
 396 +               spi->max_speed_hz = (rs->sys_freq / 2);
 397 +
 398 +       if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
 399 +               dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
 400 +                       spi->max_speed_hz);
 401 +               return -EINVAL;
 402 +       }
 403 +
 404 +       return 0;
 405 +}
 406 +
 407 +static const struct of_device_id mt7621_spi_match[] = {
 408 +       { .compatible = "ralink,mt7621-spi" },
 409 +       {},
 410 +};
 411 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
 412 +
 413 +static int mt7621_spi_probe(struct platform_device *pdev)
 414 +{
 415 +       const struct of_device_id *match;
 416 +       struct spi_master *master;
 417 +       struct mt7621_spi *rs;
 418 +       unsigned long flags;
 419 +       void __iomem *base;
 420 +       struct resource *r;
 421 +       int status = 0;
 422 +       struct clk *clk;
 423 +       struct mt7621_spi_ops *ops;
 424 +
 425 +       match = of_match_device(mt7621_spi_match, &pdev->dev);
 426 +       if (!match)
 427 +               return -EINVAL;
 428 +       ops = (struct mt7621_spi_ops *)match->data;
 429 +
 430 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 431 +       base = devm_ioremap_resource(&pdev->dev, r);
 432 +       if (IS_ERR(base))
 433 +               return PTR_ERR(base);
 434 +
 435 +       clk = devm_clk_get(&pdev->dev, NULL);
 436 +       if (IS_ERR(clk)) {
 437 +               dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
 438 +                       status);
 439 +               return PTR_ERR(clk);
 440 +       }
 441 +
 442 +       status = clk_prepare_enable(clk);
 443 +       if (status)
 444 +               return status;
 445 +
 446 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 447 +       if (master == NULL) {
 448 +               dev_info(&pdev->dev, "master allocation failed\n");
 449 +               return -ENOMEM;
 450 +       }
 451 +
 452 +       master->mode_bits = RT2880_SPI_MODE_BITS;
 453 +
 454 +       master->setup = mt7621_spi_setup;
 455 +       master->transfer_one_message = mt7621_spi_transfer_one_message;
 456 +       master->bits_per_word_mask = SPI_BPW_MASK(8);
 457 +       master->dev.of_node = pdev->dev.of_node;
 458 +       master->num_chipselect = 2;
 459 +
 460 +       dev_set_drvdata(&pdev->dev, master);
 461 +
 462 +       rs = spi_master_get_devdata(master);
 463 +       rs->base = base;
 464 +       rs->clk = clk;
 465 +       rs->master = master;
 466 +       rs->sys_freq = clk_get_rate(rs->clk);
 467 +       rs->ops = ops;
 468 +       dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
 469 +       spin_lock_irqsave(&rs->lock, flags);
 470 +
 471 +       device_reset(&pdev->dev);
 472 +
 473 +       mt7621_spi_reset(rs, 0);
 474 +
 475 +       return spi_register_master(master);
 476 +}
 477 +
 478 +static int mt7621_spi_remove(struct platform_device *pdev)
 479 +{
 480 +       struct spi_master *master;
 481 +       struct mt7621_spi *rs;
 482 +
 483 +       master = dev_get_drvdata(&pdev->dev);
 484 +       rs = spi_master_get_devdata(master);
 485 +
 486 +       clk_disable(rs->clk);
 487 +       spi_unregister_master(master);
 488 +
 489 +       return 0;
 490 +}
 491 +
 492 +MODULE_ALIAS("platform:" DRIVER_NAME);
 493 +
 494 +static struct platform_driver mt7621_spi_driver = {
 495 +       .driver = {
 496 +               .name = DRIVER_NAME,
 497 +               .owner = THIS_MODULE,
 498 +               .of_match_table = mt7621_spi_match,
 499 +       },
 500 +       .probe = mt7621_spi_probe,
 501 +       .remove = mt7621_spi_remove,
 502 +};
 503 +
 504 +module_platform_driver(mt7621_spi_driver);
 505 +
 506 +MODULE_DESCRIPTION("MT7621 SPI driver");
 507 +MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
 508 +MODULE_LICENSE("GPL");