target/linux/ramips/patches-3.8/0107-MIPS-ralink-adds-support-for-RT2880-SoC-family.patch

   1 From f63a0ea6c115e7b78bce70d78aaa813615e3d434 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jan 2013 09:17:20 +0100
   4 Subject: [PATCH 107/121] MIPS: ralink: adds support for RT2880 SoC family
   5
   6 Add support code for rt2880 SOC.
   7
   8 The code detects the SoC and registers the clk / pinmux settings.
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 ---
  12  arch/mips/Kconfig                          |    2 +-
  13  arch/mips/include/asm/mach-ralink/rt288x.h |   49 ++++++++++
  14  arch/mips/ralink/Kconfig                   |    3 +
  15  arch/mips/ralink/Makefile                  |    1 +
  16  arch/mips/ralink/Platform                  |    5 +
  17  arch/mips/ralink/rt288x.c                  |  141 ++++++++++++++++++++++++++++
  18  6 files changed, 200 insertions(+), 1 deletion(-)
  19  create mode 100644 arch/mips/include/asm/mach-ralink/rt288x.h
  20  create mode 100644 arch/mips/ralink/rt288x.c
  21
  22 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
  23 index cd2e21f..490d769 100644
  24 --- a/arch/mips/Kconfig
  25 +++ b/arch/mips/Kconfig
  26 @@ -1152,7 +1152,7 @@ config BOOT_ELF32
  27
  28  config MIPS_L1_CACHE_SHIFT
  29         int
  30 -       default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
  31 +       default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
  32         default "6" if MIPS_CPU_SCACHE
  33         default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
  34         default "5"
  35 diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
  36 new file mode 100644
  37 index 0000000..ad8b42d
  38 --- /dev/null
  39 +++ b/arch/mips/include/asm/mach-ralink/rt288x.h
  40 @@ -0,0 +1,49 @@
  41 +/*
  42 + * This program is free software; you can redistribute it and/or modify it
  43 + * under the terms of the GNU General Public License version 2 as published
  44 + * by the Free Software Foundation.
  45 + *
  46 + * Parts of this file are based on Ralink's 2.6.21 BSP
  47 + *
  48 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  49 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  50 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  51 + */
  52 +
  53 +#ifndef _RT288X_REGS_H_
  54 +#define _RT288X_REGS_H_
  55 +
  56 +#define RT2880_SYSC_BASE               0x00300000
  57 +
  58 +#define SYSC_REG_CHIP_NAME0            0x00
  59 +#define SYSC_REG_CHIP_NAME1            0x04
  60 +#define SYSC_REG_CHIP_ID               0x0c
  61 +#define SYSC_REG_SYSTEM_CONFIG         0x10
  62 +#define SYSC_REG_CLKCFG                        0x30
  63 +
  64 +#define RT2880_CHIP_NAME0              0x38325452
  65 +#define RT2880_CHIP_NAME1              0x20203038
  66 +
  67 +#define CHIP_ID_ID_MASK                        0xff
  68 +#define CHIP_ID_ID_SHIFT               8
  69 +#define CHIP_ID_REV_MASK               0xff
  70 +
  71 +#define SYSTEM_CONFIG_CPUCLK_SHIFT     20
  72 +#define SYSTEM_CONFIG_CPUCLK_MASK      0x3
  73 +#define SYSTEM_CONFIG_CPUCLK_250       0x0
  74 +#define SYSTEM_CONFIG_CPUCLK_266       0x1
  75 +#define SYSTEM_CONFIG_CPUCLK_280       0x2
  76 +#define SYSTEM_CONFIG_CPUCLK_300       0x3
  77 +
  78 +#define RT2880_GPIO_MODE_I2C           BIT(0)
  79 +#define RT2880_GPIO_MODE_UART0         BIT(1)
  80 +#define RT2880_GPIO_MODE_SPI           BIT(2)
  81 +#define RT2880_GPIO_MODE_UART1         BIT(3)
  82 +#define RT2880_GPIO_MODE_JTAG          BIT(4)
  83 +#define RT2880_GPIO_MODE_MDIO          BIT(5)
  84 +#define RT2880_GPIO_MODE_SDRAM         BIT(6)
  85 +#define RT2880_GPIO_MODE_PCI           BIT(7)
  86 +
  87 +#define CLKCFG_SRAM_CS_N_WDT           BIT(9)
  88 +
  89 +#endif
  90 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
  91 index a0b0197..6723b94 100644
  92 --- a/arch/mips/ralink/Kconfig
  93 +++ b/arch/mips/ralink/Kconfig
  94 @@ -6,6 +6,9 @@ choice
  95         help
  96           Select Ralink MIPS SoC type.
  97
  98 +       config SOC_RT288X
  99 +               bool "RT288x"
 100 +
 101         config SOC_RT305X
 102                 bool "RT305x"
 103                 select USB_ARCH_HAS_HCD
 104 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
 105 index 39ef249..ce83bfc 100644
 106 --- a/arch/mips/ralink/Makefile
 107 +++ b/arch/mips/ralink/Makefile
 108 @@ -8,6 +8,7 @@
 109
 110  obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
 111
 112 +obj-$(CONFIG_SOC_RT288X) += rt288x.o
 113  obj-$(CONFIG_SOC_RT305X) += rt305x.o
 114
 115  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 116 diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
 117 index 6babd65..3f49e51 100644
 118 --- a/arch/mips/ralink/Platform
 119 +++ b/arch/mips/ralink/Platform
 120 @@ -5,6 +5,11 @@ core-$(CONFIG_RALINK)          += arch/mips/ralink/
 121  cflags-$(CONFIG_RALINK)                += -I$(srctree)/arch/mips/include/asm/mach-ralink
 122
 123  #
 124 +# Ralink RT288x
 125 +#
 126 +load-$(CONFIG_SOC_RT288X)      += 0xffffffff88000000
 127 +
 128 +#
 129  # Ralink RT305x
 130  #
 131  load-$(CONFIG_SOC_RT305X)      += 0xffffffff80000000
 132 diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
 133 new file mode 100644
 134 index 0000000..37faff0
 135 --- /dev/null
 136 +++ b/arch/mips/ralink/rt288x.c
 137 @@ -0,0 +1,141 @@
 138 +/*
 139 + * This program is free software; you can redistribute it and/or modify it
 140 + * under the terms of the GNU General Public License version 2 as published
 141 + * by the Free Software Foundation.
 142 + *
 143 + * Parts of this file are based on Ralink's 2.6.21 BSP
 144 + *
 145 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 146 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 147 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 148 + */
 149 +
 150 +#include <linux/kernel.h>
 151 +#include <linux/init.h>
 152 +#include <linux/module.h>
 153 +
 154 +#include <asm/mipsregs.h>
 155 +#include <asm/mach-ralink/ralink_regs.h>
 156 +#include <asm/mach-ralink/rt288x.h>
 157 +
 158 +#include "common.h"
 159 +
 160 +struct ralink_pinmux_grp mode_mux[] = {
 161 +       {
 162 +               .name = "i2c",
 163 +               .mask = RT2880_GPIO_MODE_I2C,
 164 +               .gpio_first = 1,
 165 +               .gpio_last = 2,
 166 +       }, {
 167 +               .name = "spi",
 168 +               .mask = RT2880_GPIO_MODE_SPI,
 169 +               .gpio_first = 3,
 170 +               .gpio_last = 6,
 171 +       }, {
 172 +               .name = "uartlite",
 173 +               .mask = RT2880_GPIO_MODE_UART0,
 174 +               .gpio_first = 7,
 175 +               .gpio_last = 14,
 176 +       }, {
 177 +               .name = "jtag",
 178 +               .mask = RT2880_GPIO_MODE_JTAG,
 179 +               .gpio_first = 17,
 180 +               .gpio_last = 21,
 181 +       }, {
 182 +               .name = "mdio",
 183 +               .mask = RT2880_GPIO_MODE_MDIO,
 184 +               .gpio_first = 22,
 185 +               .gpio_last = 23,
 186 +       }, {
 187 +               .name = "sdram",
 188 +               .mask = RT2880_GPIO_MODE_SDRAM,
 189 +               .gpio_first = 24,
 190 +               .gpio_last = 39,
 191 +       }, {
 192 +               .name = "pci",
 193 +               .mask = RT2880_GPIO_MODE_PCI,
 194 +               .gpio_first = 40,
 195 +               .gpio_last = 71,
 196 +       }, {0}
 197 +};
 198 +
 199 +void rt288x_wdt_reset(void)
 200 +{
 201 +       u32 t;
 202 +
 203 +       /* enable WDT reset output on pin SRAM_CS_N */
 204 +       t = rt_sysc_r32(SYSC_REG_CLKCFG);
 205 +       t |= CLKCFG_SRAM_CS_N_WDT;
 206 +       rt_sysc_w32(t, SYSC_REG_CLKCFG);
 207 +}
 208 +
 209 +struct ralink_pinmux rt_pinmux = {
 210 +       .mode = mode_mux,
 211 +       .wdt_reset = rt288x_wdt_reset,
 212 +};
 213 +
 214 +void ralink_usb_platform(void)
 215 +{
 216 +}
 217 +
 218 +void __init ralink_clk_init(void)
 219 +{
 220 +       unsigned long cpu_rate;
 221 +       u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
 222 +       t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
 223 +
 224 +       switch (t) {
 225 +       case SYSTEM_CONFIG_CPUCLK_250:
 226 +               cpu_rate = 250000000;
 227 +               break;
 228 +       case SYSTEM_CONFIG_CPUCLK_266:
 229 +               cpu_rate = 266666667;
 230 +               break;
 231 +       case SYSTEM_CONFIG_CPUCLK_280:
 232 +               cpu_rate = 280000000;
 233 +               break;
 234 +       case SYSTEM_CONFIG_CPUCLK_300:
 235 +               cpu_rate = 300000000;
 236 +               break;
 237 +       }
 238 +
 239 +       ralink_clk_add("cpu", cpu_rate);
 240 +       ralink_clk_add("10000100.timer", cpu_rate / 2);
 241 +       ralink_clk_add("10000500.uart", cpu_rate / 2);
 242 +       ralink_clk_add("10000c00.uartlite", cpu_rate / 2);
 243 +}
 244 +
 245 +void __init ralink_of_remap(void)
 246 +{
 247 +       rt_sysc_membase = plat_of_remap_node("ralink,rt288x-sysc");
 248 +       rt_memc_membase = plat_of_remap_node("ralink,rt288x-memc");
 249 +
 250 +       if (!rt_sysc_membase || !rt_memc_membase)
 251 +               panic("Failed to remap core resources");
 252 +}
 253 +
 254 +void prom_soc_init(struct ralink_soc_info *soc_info)
 255 +{
 256 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
 257 +       const char *name;
 258 +       u32 n0;
 259 +       u32 n1;
 260 +       u32 id;
 261 +
 262 +       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 263 +       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 264 +       id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
 265 +
 266 +       if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
 267 +               soc_info->compatible = "ralink,r2880-soc";
 268 +               name = "RT2880";
 269 +       } else {
 270 +               panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
 271 +       }
 272 +
 273 +       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 274 +               "Ralink %s id:%u rev:%u",
 275 +               name,
 276 +               (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 277 +               (id & CHIP_ID_REV_MASK));
 278 +}
 279 --
 280 1.7.10.4
 281