target/linux/ramips/patches-3.9/0113-MIPS-ralink-adds-support-for-MT7620-SoC-family.patch

   1 From 878887d15bdee87366b7d3952d1c74c4b68a0782 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 17:49:02 +0100
   4 Subject: [PATCH 113/164] MIPS: ralink: adds support for MT7620 SoC family
   5
   6 Add support code for mt7620 SOC.
   7
   8 The code detects the SoC and registers the clk / pinmux settings.
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Acked-by: Gabor Juhos <juhosg@openwrt.org>
  12 Patchwork: http://patchwork.linux-mips.org/patch/5177/
  13 ---
  14  arch/mips/include/asm/mach-ralink/mt7620.h |   76 ++++++++++
  15  arch/mips/ralink/Kconfig                   |    3 +
  16  arch/mips/ralink/Makefile                  |    1 +
  17  arch/mips/ralink/Platform                  |    5 +
  18  arch/mips/ralink/mt7620.c                  |  214 ++++++++++++++++++++++++++++
  19  5 files changed, 299 insertions(+)
  20  create mode 100644 arch/mips/include/asm/mach-ralink/mt7620.h
  21  create mode 100644 arch/mips/ralink/mt7620.c
  22
  23 diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
  24 new file mode 100644
  25 index 0000000..b272649
  26 --- /dev/null
  27 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
  28 @@ -0,0 +1,76 @@
  29 +/*
  30 + * This program is free software; you can redistribute it and/or modify it
  31 + * under the terms of the GNU General Public License version 2 as published
  32 + * by the Free Software Foundation.
  33 + *
  34 + * Parts of this file are based on Ralink's 2.6.21 BSP
  35 + *
  36 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  37 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  38 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  39 + */
  40 +
  41 +#ifndef _MT7620_REGS_H_
  42 +#define _MT7620_REGS_H_
  43 +
  44 +#define MT7620_SYSC_BASE               0x10000000
  45 +
  46 +#define SYSC_REG_CHIP_NAME0            0x00
  47 +#define SYSC_REG_CHIP_NAME1            0x04
  48 +#define SYSC_REG_CHIP_REV              0x0c
  49 +#define SYSC_REG_SYSTEM_CONFIG0                0x10
  50 +#define SYSC_REG_SYSTEM_CONFIG1                0x14
  51 +#define SYSC_REG_CPLL_CONFIG0          0x54
  52 +#define SYSC_REG_CPLL_CONFIG1          0x58
  53 +
  54 +#define MT7620N_CHIP_NAME0             0x33365452
  55 +#define MT7620N_CHIP_NAME1             0x20203235
  56 +
  57 +#define MT7620A_CHIP_NAME0             0x3637544d
  58 +#define MT7620A_CHIP_NAME1             0x20203032
  59 +
  60 +#define CHIP_REV_PKG_MASK              0x1
  61 +#define CHIP_REV_PKG_SHIFT             16
  62 +#define CHIP_REV_VER_MASK              0xf
  63 +#define CHIP_REV_VER_SHIFT             8
  64 +#define CHIP_REV_ECO_MASK              0xf
  65 +
  66 +#define CPLL_SW_CONFIG_SHIFT           31
  67 +#define CPLL_SW_CONFIG_MASK            0x1
  68 +#define CPLL_CPU_CLK_SHIFT             24
  69 +#define CPLL_CPU_CLK_MASK              0x1
  70 +#define CPLL_MULT_RATIO_SHIFT           16
  71 +#define CPLL_MULT_RATIO                 0x7
  72 +#define CPLL_DIV_RATIO_SHIFT            10
  73 +#define CPLL_DIV_RATIO                  0x3
  74 +
  75 +#define SYSCFG0_DRAM_TYPE_MASK         0x3
  76 +#define SYSCFG0_DRAM_TYPE_SHIFT                4
  77 +#define SYSCFG0_DRAM_TYPE_SDRAM                0
  78 +#define SYSCFG0_DRAM_TYPE_DDR1         1
  79 +#define SYSCFG0_DRAM_TYPE_DDR2         2
  80 +
  81 +#define MT7620_GPIO_MODE_I2C           BIT(0)
  82 +#define MT7620_GPIO_MODE_UART0_SHIFT   2
  83 +#define MT7620_GPIO_MODE_UART0_MASK    0x7
  84 +#define MT7620_GPIO_MODE_UART0(x)      ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
  85 +#define MT7620_GPIO_MODE_UARTF         0x0
  86 +#define MT7620_GPIO_MODE_PCM_UARTF     0x1
  87 +#define MT7620_GPIO_MODE_PCM_I2S       0x2
  88 +#define MT7620_GPIO_MODE_I2S_UARTF     0x3
  89 +#define MT7620_GPIO_MODE_PCM_GPIO      0x4
  90 +#define MT7620_GPIO_MODE_GPIO_UARTF    0x5
  91 +#define MT7620_GPIO_MODE_GPIO_I2S      0x6
  92 +#define MT7620_GPIO_MODE_GPIO          0x7
  93 +#define MT7620_GPIO_MODE_UART1         BIT(5)
  94 +#define MT7620_GPIO_MODE_MDIO          BIT(8)
  95 +#define MT7620_GPIO_MODE_RGMII1                BIT(9)
  96 +#define MT7620_GPIO_MODE_RGMII2                BIT(10)
  97 +#define MT7620_GPIO_MODE_SPI           BIT(11)
  98 +#define MT7620_GPIO_MODE_SPI_REF_CLK   BIT(12)
  99 +#define MT7620_GPIO_MODE_WLED          BIT(13)
 100 +#define MT7620_GPIO_MODE_JTAG          BIT(15)
 101 +#define MT7620_GPIO_MODE_EPHY          BIT(15)
 102 +#define MT7620_GPIO_MODE_WDT           BIT(22)
 103 +
 104 +#endif
 105 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
 106 index ce57d3e..86f6c77 100644
 107 --- a/arch/mips/ralink/Kconfig
 108 +++ b/arch/mips/ralink/Kconfig
 109 @@ -20,6 +20,9 @@ choice
 110                 select USB_ARCH_HAS_OHCI
 111                 select USB_ARCH_HAS_EHCI
 112
 113 +       config SOC_MT7620
 114 +               bool "MT7620"
 115 +
 116  endchoice
 117
 118  choice
 119 diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
 120 index ba9669c..38cf1a8 100644
 121 --- a/arch/mips/ralink/Makefile
 122 +++ b/arch/mips/ralink/Makefile
 123 @@ -11,6 +11,7 @@ obj-y := prom.o of.o reset.o clk.o irq.o
 124  obj-$(CONFIG_SOC_RT288X) += rt288x.o
 125  obj-$(CONFIG_SOC_RT305X) += rt305x.o
 126  obj-$(CONFIG_SOC_RT3883) += rt3883.o
 127 +obj-$(CONFIG_SOC_MT7620) += mt7620.o
 128
 129  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 130
 131 diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
 132 index f67c08d..b2cbf16 100644
 133 --- a/arch/mips/ralink/Platform
 134 +++ b/arch/mips/ralink/Platform
 135 @@ -18,3 +18,8 @@ load-$(CONFIG_SOC_RT305X)     += 0xffffffff80000000
 136  # Ralink RT3883
 137  #
 138  load-$(CONFIG_SOC_RT3883)      += 0xffffffff80000000
 139 +
 140 +#
 141 +# Ralink MT7620
 142 +#
 143 +load-$(CONFIG_SOC_MT7620)      += 0xffffffff80000000
 144 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
 145 new file mode 100644
 146 index 0000000..eb00ab8
 147 --- /dev/null
 148 +++ b/arch/mips/ralink/mt7620.c
 149 @@ -0,0 +1,214 @@
 150 +/*
 151 + * This program is free software; you can redistribute it and/or modify it
 152 + * under the terms of the GNU General Public License version 2 as published
 153 + * by the Free Software Foundation.
 154 + *
 155 + * Parts of this file are based on Ralink's 2.6.21 BSP
 156 + *
 157 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 158 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 159 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 160 + */
 161 +
 162 +#include <linux/kernel.h>
 163 +#include <linux/init.h>
 164 +#include <linux/module.h>
 165 +
 166 +#include <asm/mipsregs.h>
 167 +#include <asm/mach-ralink/ralink_regs.h>
 168 +#include <asm/mach-ralink/mt7620.h>
 169 +
 170 +#include "common.h"
 171 +
 172 +/* does the board have sdram or ddram */
 173 +static int dram_type;
 174 +
 175 +/* the pll dividers */
 176 +static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
 177 +
 178 +static struct ralink_pinmux_grp mode_mux[] = {
 179 +       {
 180 +               .name = "i2c",
 181 +               .mask = MT7620_GPIO_MODE_I2C,
 182 +               .gpio_first = 1,
 183 +               .gpio_last = 2,
 184 +       }, {
 185 +               .name = "spi",
 186 +               .mask = MT7620_GPIO_MODE_SPI,
 187 +               .gpio_first = 3,
 188 +               .gpio_last = 6,
 189 +       }, {
 190 +               .name = "uartlite",
 191 +               .mask = MT7620_GPIO_MODE_UART1,
 192 +               .gpio_first = 15,
 193 +               .gpio_last = 16,
 194 +       }, {
 195 +               .name = "wdt",
 196 +               .mask = MT7620_GPIO_MODE_WDT,
 197 +               .gpio_first = 17,
 198 +               .gpio_last = 17,
 199 +       }, {
 200 +               .name = "mdio",
 201 +               .mask = MT7620_GPIO_MODE_MDIO,
 202 +               .gpio_first = 22,
 203 +               .gpio_last = 23,
 204 +       }, {
 205 +               .name = "rgmii1",
 206 +               .mask = MT7620_GPIO_MODE_RGMII1,
 207 +               .gpio_first = 24,
 208 +               .gpio_last = 35,
 209 +       }, {
 210 +               .name = "spi refclk",
 211 +               .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
 212 +               .gpio_first = 37,
 213 +               .gpio_last = 39,
 214 +       }, {
 215 +               .name = "jtag",
 216 +               .mask = MT7620_GPIO_MODE_JTAG,
 217 +               .gpio_first = 40,
 218 +               .gpio_last = 44,
 219 +       }, {
 220 +               /* shared lines with jtag */
 221 +               .name = "ephy",
 222 +               .mask = MT7620_GPIO_MODE_EPHY,
 223 +               .gpio_first = 40,
 224 +               .gpio_last = 44,
 225 +       }, {
 226 +               .name = "nand",
 227 +               .mask = MT7620_GPIO_MODE_JTAG,
 228 +               .gpio_first = 45,
 229 +               .gpio_last = 59,
 230 +       }, {
 231 +               .name = "rgmii2",
 232 +               .mask = MT7620_GPIO_MODE_RGMII2,
 233 +               .gpio_first = 60,
 234 +               .gpio_last = 71,
 235 +       }, {
 236 +               .name = "wled",
 237 +               .mask = MT7620_GPIO_MODE_WLED,
 238 +               .gpio_first = 72,
 239 +               .gpio_last = 72,
 240 +       }, {0}
 241 +};
 242 +
 243 +static struct ralink_pinmux_grp uart_mux[] = {
 244 +       {
 245 +               .name = "uartf",
 246 +               .mask = MT7620_GPIO_MODE_UARTF,
 247 +               .gpio_first = 7,
 248 +               .gpio_last = 14,
 249 +       }, {
 250 +               .name = "pcm uartf",
 251 +               .mask = MT7620_GPIO_MODE_PCM_UARTF,
 252 +               .gpio_first = 7,
 253 +               .gpio_last = 14,
 254 +       }, {
 255 +               .name = "pcm i2s",
 256 +               .mask = MT7620_GPIO_MODE_PCM_I2S,
 257 +               .gpio_first = 7,
 258 +               .gpio_last = 14,
 259 +       }, {
 260 +               .name = "i2s uartf",
 261 +               .mask = MT7620_GPIO_MODE_I2S_UARTF,
 262 +               .gpio_first = 7,
 263 +               .gpio_last = 14,
 264 +       }, {
 265 +               .name = "pcm gpio",
 266 +               .mask = MT7620_GPIO_MODE_PCM_GPIO,
 267 +               .gpio_first = 11,
 268 +               .gpio_last = 14,
 269 +       }, {
 270 +               .name = "gpio uartf",
 271 +               .mask = MT7620_GPIO_MODE_GPIO_UARTF,
 272 +               .gpio_first = 7,
 273 +               .gpio_last = 10,
 274 +       }, {
 275 +               .name = "gpio i2s",
 276 +               .mask = MT7620_GPIO_MODE_GPIO_I2S,
 277 +               .gpio_first = 7,
 278 +               .gpio_last = 10,
 279 +       }, {
 280 +               .name = "gpio",
 281 +               .mask = MT7620_GPIO_MODE_GPIO,
 282 +       }, {0}
 283 +};
 284 +
 285 +struct ralink_pinmux rt_gpio_pinmux = {
 286 +       .mode = mode_mux,
 287 +       .uart = uart_mux,
 288 +       .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
 289 +       .uart_mask = MT7620_GPIO_MODE_GPIO,
 290 +};
 291 +
 292 +void __init ralink_clk_init(void)
 293 +{
 294 +       unsigned long cpu_rate, sys_rate;
 295 +       u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
 296 +       u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
 297 +       u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
 298 +       u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
 299 +
 300 +       if (cpu_clk) {
 301 +               cpu_rate = 480000000;
 302 +       } else if (!swconfig) {
 303 +               cpu_rate = 600000000;
 304 +       } else {
 305 +               u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
 306 +               u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
 307 +
 308 +               cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
 309 +       }
 310 +
 311 +       if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
 312 +               sys_rate = cpu_rate / 4;
 313 +       else
 314 +               sys_rate = cpu_rate / 3;
 315 +
 316 +       ralink_clk_add("cpu", cpu_rate);
 317 +       ralink_clk_add("10000100.timer", 40000000);
 318 +       ralink_clk_add("10000500.uart", 40000000);
 319 +       ralink_clk_add("10000c00.uartlite", 40000000);
 320 +}
 321 +
 322 +void __init ralink_of_remap(void)
 323 +{
 324 +       rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
 325 +       rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
 326 +
 327 +       if (!rt_sysc_membase || !rt_memc_membase)
 328 +               panic("Failed to remap core resources");
 329 +}
 330 +
 331 +void prom_soc_init(struct ralink_soc_info *soc_info)
 332 +{
 333 +       void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
 334 +       unsigned char *name = NULL;
 335 +       u32 n0;
 336 +       u32 n1;
 337 +       u32 rev;
 338 +       u32 cfg0;
 339 +
 340 +       n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 341 +       n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 342 +
 343 +       if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
 344 +               name = "MT7620N";
 345 +               soc_info->compatible = "ralink,mt7620n-soc";
 346 +       } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
 347 +               name = "MT7620A";
 348 +               soc_info->compatible = "ralink,mt7620a-soc";
 349 +       } else {
 350 +               panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
 351 +       }
 352 +
 353 +       rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
 354 +
 355 +       snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 356 +               "Ralink %s ver:%u eco:%u",
 357 +               name,
 358 +               (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
 359 +               (rev & CHIP_REV_ECO_MASK));
 360 +
 361 +       cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
 362 +       dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
 363 +}
 364 --
 365 1.7.10.4
 366