target/linux/ramips/patches-3.9/0143-GPIO-MIPS-ralink-adds-ralink-gpio-support.patch

   1 From 82a24aa01752a87c571e47323f0e141c818e531b Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 22 Jan 2013 18:24:34 +0100
   4 Subject: [PATCH 143/164] GPIO: MIPS: ralink: adds ralink gpio support
   5
   6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
   7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  arch/mips/Kconfig                        |    1 +
  12  arch/mips/include/asm/mach-ralink/gpio.h |   24 +++
  13  drivers/gpio/Kconfig                     |    6 +
  14  drivers/gpio/Makefile                    |    1 +
  15  drivers/gpio/gpio-ralink.c               |  326 ++++++++++++++++++++++++++++++
  16  5 files changed, 358 insertions(+)
  17  create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
  18  create mode 100644 drivers/gpio/gpio-ralink.c
  19
  20 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
  21 index e4da4f8..b237c50 100644
  22 --- a/arch/mips/Kconfig
  23 +++ b/arch/mips/Kconfig
  24 @@ -443,6 +443,7 @@ config RALINK
  25         select SYS_HAS_EARLY_PRINTK
  26         select HAVE_MACH_CLKDEV
  27         select CLKDEV_LOOKUP
  28 +       select ARCH_REQUIRE_GPIOLIB
  29
  30  config SGI_IP22
  31         bool "SGI IP22 (Indy/Indigo2)"
  32 diff --git a/arch/mips/include/asm/mach-ralink/gpio.h b/arch/mips/include/asm/mach-ralink/gpio.h
  33 new file mode 100644
  34 index 0000000..f68ee16
  35 --- /dev/null
  36 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
  37 @@ -0,0 +1,24 @@
  38 +/*
  39 + *  Ralink SoC GPIO API support
  40 + *
  41 + *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  42 + *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  43 + *
  44 + *  This program is free software; you can redistribute it and/or modify it
  45 + *  under the terms of the GNU General Public License version 2 as published
  46 + *  by the Free Software Foundation.
  47 + *
  48 + */
  49 +
  50 +#ifndef __ASM_MACH_RALINK_GPIO_H
  51 +#define __ASM_MACH_RALINK_GPIO_H
  52 +
  53 +#define ARCH_NR_GPIOS  128
  54 +#include <asm-generic/gpio.h>
  55 +
  56 +#define gpio_get_value __gpio_get_value
  57 +#define gpio_set_value __gpio_set_value
  58 +#define gpio_cansleep  __gpio_cansleep
  59 +#define gpio_to_irq    __gpio_to_irq
  60 +
  61 +#endif /* __ASM_MACH_RALINK_GPIO_H */
  62 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
  63 index 93aaadf..29add97 100644
  64 --- a/drivers/gpio/Kconfig
  65 +++ b/drivers/gpio/Kconfig
  66 @@ -204,6 +204,12 @@ config GPIO_PXA
  67         help
  68           Say yes here to support the PXA GPIO device
  69
  70 +config GPIO_RALINK
  71 +       bool "Ralink GPIO Support"
  72 +       depends on RALINK
  73 +       help
  74 +         Say yes here to support the Ralink SoC GPIO device
  75 +
  76  config GPIO_SPEAR_SPICS
  77         bool "ST SPEAr13xx SPI Chip Select as GPIO support"
  78         depends on PLAT_SPEAR
  79 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
  80 index 22e07bc..f7b6603 100644
  81 --- a/drivers/gpio/Makefile
  82 +++ b/drivers/gpio/Makefile
  83 @@ -55,6 +55,7 @@ obj-$(CONFIG_GPIO_PCF857X)    += gpio-pcf857x.o
  84  obj-$(CONFIG_GPIO_PCH)         += gpio-pch.o
  85  obj-$(CONFIG_GPIO_PL061)       += gpio-pl061.o
  86  obj-$(CONFIG_GPIO_PXA)         += gpio-pxa.o
  87 +obj-$(CONFIG_GPIO_RALINK)      += gpio-ralink.o
  88  obj-$(CONFIG_GPIO_RC5T583)     += gpio-rc5t583.o
  89  obj-$(CONFIG_GPIO_RDC321X)     += gpio-rdc321x.o
  90  obj-$(CONFIG_PLAT_SAMSUNG)     += gpio-samsung.o
  91 diff --git a/drivers/gpio/gpio-ralink.c b/drivers/gpio/gpio-ralink.c
  92 new file mode 100644
  93 index 0000000..12984f1
  94 --- /dev/null
  95 +++ b/drivers/gpio/gpio-ralink.c
  96 @@ -0,0 +1,326 @@
  97 +/*
  98 + * This program is free software; you can redistribute it and/or modify it
  99 + * under the terms of the GNU General Public License version 2 as published
 100 + * by the Free Software Foundation.
 101 + *
 102 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 103 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 104 + */
 105 +
 106 +#include <linux/module.h>
 107 +#include <linux/io.h>
 108 +#include <linux/gpio.h>
 109 +#include <linux/spinlock.h>
 110 +#include <linux/platform_device.h>
 111 +#include <linux/of_irq.h>
 112 +#include <linux/irqdomain.h>
 113 +#include <linux/interrupt.h>
 114 +
 115 +enum ralink_gpio_reg {
 116 +       GPIO_REG_INT = 0,
 117 +       GPIO_REG_EDGE,
 118 +       GPIO_REG_RENA,
 119 +       GPIO_REG_FENA,
 120 +       GPIO_REG_DATA,
 121 +       GPIO_REG_DIR,
 122 +       GPIO_REG_POL,
 123 +       GPIO_REG_SET,
 124 +       GPIO_REG_RESET,
 125 +       GPIO_REG_TOGGLE,
 126 +       GPIO_REG_MAX
 127 +};
 128 +
 129 +struct ralink_gpio_chip {
 130 +       struct gpio_chip chip;
 131 +       u8 regs[GPIO_REG_MAX];
 132 +
 133 +       spinlock_t lock;
 134 +       void __iomem *membase;
 135 +       struct irq_domain *domain;
 136 +       int irq;
 137 +
 138 +       u32 rising;
 139 +       u32 falling;
 140 +};
 141 +
 142 +#define MAP_MAX        4
 143 +static struct irq_domain *irq_map[MAP_MAX];
 144 +static int irq_map_count;
 145 +static atomic_t irq_refcount = ATOMIC_INIT(0);
 146 +
 147 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
 148 +{
 149 +       struct ralink_gpio_chip *rg;
 150 +
 151 +       rg = container_of(chip, struct ralink_gpio_chip, chip);
 152 +
 153 +       return rg;
 154 +}
 155 +
 156 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
 157 +{
 158 +       iowrite32(val, rg->membase + rg->regs[reg]);
 159 +}
 160 +
 161 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
 162 +{
 163 +       return ioread32(rg->membase + rg->regs[reg]);
 164 +}
 165 +
 166 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 167 +{
 168 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 169 +
 170 +       rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
 171 +}
 172 +
 173 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
 174 +{
 175 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 176 +
 177 +       return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 178 +}
 179 +
 180 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 181 +{
 182 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 183 +       unsigned long flags;
 184 +       u32 t;
 185 +
 186 +       spin_lock_irqsave(&rg->lock, flags);
 187 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 188 +       t &= ~BIT(offset);
 189 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 190 +       spin_unlock_irqrestore(&rg->lock, flags);
 191 +
 192 +       return 0;
 193 +}
 194 +
 195 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
 196 +                                       unsigned offset, int value)
 197 +{
 198 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 199 +       unsigned long flags;
 200 +       u32 t;
 201 +
 202 +       spin_lock_irqsave(&rg->lock, flags);
 203 +       ralink_gpio_set(chip, offset, value);
 204 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 205 +       t |= BIT(offset);
 206 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 207 +       spin_unlock_irqrestore(&rg->lock, flags);
 208 +
 209 +       return 0;
 210 +}
 211 +
 212 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 213 +{
 214 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 215 +
 216 +       if (rg->irq < 1)
 217 +               return -1;
 218 +
 219 +       ralink_gpio_direction_input(chip, pin);
 220 +
 221 +       return irq_create_mapping(rg->domain, pin);
 222 +}
 223 +
 224 +static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 225 +{
 226 +       int i;
 227 +
 228 +       for (i = 0; i < irq_map_count; i++) {
 229 +               struct irq_domain *domain = irq_map[i];
 230 +               struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) domain->host_data;
 231 +               unsigned long pending = rt_gpio_r32(rg, GPIO_REG_INT);
 232 +               int bit;
 233 +
 234 +               for_each_set_bit(bit, &pending, rg->chip.ngpio) {
 235 +                       u32 map = irq_find_mapping(domain, bit);
 236 +                       generic_handle_irq(map);
 237 +                       rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
 238 +               }
 239 +       }
 240 +}
 241 +
 242 +static void ralink_gpio_irq_unmask(struct irq_data *d)
 243 +{
 244 +       struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
 245 +       u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
 246 +       unsigned long flags;
 247 +
 248 +       spin_lock_irqsave(&rg->lock, flags);
 249 +       rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
 250 +       rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
 251 +       spin_unlock_irqrestore(&rg->lock, flags);
 252 +}
 253 +
 254 +static void ralink_gpio_irq_mask(struct irq_data *d)
 255 +{
 256 +       struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
 257 +       u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
 258 +       unsigned long flags;
 259 +
 260 +       spin_lock_irqsave(&rg->lock, flags);
 261 +       rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
 262 +       rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
 263 +       spin_unlock_irqrestore(&rg->lock, flags);
 264 +}
 265 +
 266 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
 267 +{
 268 +       struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
 269 +       u32 mask = BIT(d->hwirq);
 270 +
 271 +       if (type == IRQ_TYPE_PROBE) {
 272 +               if ((rg->rising | rg->falling) & mask)
 273 +                       return 0;
 274 +
 275 +               type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_RISING;
 276 +       }
 277 +
 278 +       if (type & IRQ_TYPE_EDGE_RISING)
 279 +               rg->rising |= mask;
 280 +       else
 281 +               rg->rising &= mask;
 282 +
 283 +       if (type & IRQ_TYPE_EDGE_RISING)
 284 +               rg->falling |= mask;
 285 +       else
 286 +               rg->falling &= mask;
 287 +
 288 +       return 0;
 289 +}
 290 +
 291 +static struct irq_chip ralink_gpio_irq_chip = {
 292 +       .name           = "GPIO",
 293 +       .irq_unmask     = ralink_gpio_irq_unmask,
 294 +       .irq_mask       = ralink_gpio_irq_mask,
 295 +       .irq_mask_ack   = ralink_gpio_irq_mask,
 296 +       .irq_set_type   = ralink_gpio_irq_type,
 297 +};
 298 +
 299 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 300 +{
 301 +       irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
 302 +       irq_set_handler_data(irq, d);
 303 +
 304 +       return 0;
 305 +}
 306 +
 307 +static const struct irq_domain_ops irq_domain_ops = {
 308 +       .xlate = irq_domain_xlate_onecell,
 309 +       .map = gpio_map,
 310 +};
 311 +
 312 +static void ralink_gpio_irq_init(struct device_node *np, struct ralink_gpio_chip *rg)
 313 +{
 314 +       if (irq_map_count >= MAP_MAX)
 315 +               return;
 316 +
 317 +       rg->irq = irq_of_parse_and_map(np, 0);
 318 +       if (!rg->irq)
 319 +               return;
 320 +
 321 +       rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, &irq_domain_ops, rg);
 322 +       if (!rg->domain) {
 323 +               dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
 324 +               return;
 325 +       }
 326 +
 327 +       irq_map[irq_map_count++] = rg->domain;
 328 +
 329 +       rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
 330 +       rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
 331 +
 332 +       if (!atomic_read(&irq_refcount))
 333 +               irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
 334 +       atomic_inc(&irq_refcount);
 335 +
 336 +       dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
 337 +}
 338 +
 339 +static int ralink_gpio_probe(struct platform_device *pdev)
 340 +{
 341 +       struct device_node *np = pdev->dev.of_node;
 342 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 343 +       struct ralink_gpio_chip *rg;
 344 +       const __be32 *ngpio, *gpiobase;
 345 +
 346 +       if (!res) {
 347 +               dev_err(&pdev->dev, "failed to find resource\n");
 348 +               return -ENOMEM;
 349 +       }
 350 +
 351 +       rg = devm_kzalloc(&pdev->dev,
 352 +                       sizeof(struct ralink_gpio_chip), GFP_KERNEL);
 353 +       if (!rg)
 354 +               return -ENOMEM;
 355 +
 356 +       rg->membase = devm_request_and_ioremap(&pdev->dev, res);
 357 +       if (!rg->membase) {
 358 +               dev_err(&pdev->dev, "cannot remap I/O memory region\n");
 359 +               return -ENOMEM;
 360 +       }
 361 +
 362 +       if (of_property_read_u8_array(np, "ralink,register-map",
 363 +                       rg->regs, GPIO_REG_MAX)) {
 364 +               dev_err(&pdev->dev, "failed to read register definition\n");
 365 +               return -EINVAL;
 366 +       }
 367 +
 368 +       ngpio = of_get_property(np, "ralink,num-gpios", NULL);
 369 +       if (!ngpio) {
 370 +               dev_err(&pdev->dev, "failed to read number of pins\n");
 371 +               return -EINVAL;
 372 +       }
 373 +
 374 +       gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
 375 +       if (gpiobase)
 376 +               rg->chip.base = be32_to_cpu(*gpiobase);
 377 +       else
 378 +               rg->chip.base = -1;
 379 +
 380 +       spin_lock_init(&rg->lock);
 381 +
 382 +       rg->chip.dev = &pdev->dev;
 383 +       rg->chip.label = dev_name(&pdev->dev);
 384 +       rg->chip.of_node = np;
 385 +       rg->chip.ngpio = be32_to_cpu(*ngpio);
 386 +       rg->chip.direction_input = ralink_gpio_direction_input;
 387 +       rg->chip.direction_output = ralink_gpio_direction_output;
 388 +       rg->chip.get = ralink_gpio_get;
 389 +       rg->chip.set = ralink_gpio_set;
 390 +       rg->chip.to_irq = ralink_gpio_to_irq;
 391 +
 392 +       /* set polarity to low for all lines */
 393 +       rt_gpio_w32(rg, GPIO_REG_POL, 0);
 394 +
 395 +       dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
 396 +
 397 +       ralink_gpio_irq_init(np, rg);
 398 +
 399 +       return gpiochip_add(&rg->chip);
 400 +}
 401 +
 402 +static const struct of_device_id ralink_gpio_match[] = {
 403 +       { .compatible = "ralink,rt2880-gpio" },
 404 +       {},
 405 +};
 406 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
 407 +
 408 +static struct platform_driver ralink_gpio_driver = {
 409 +       .probe = ralink_gpio_probe,
 410 +       .driver = {
 411 +               .name = "rt2880_gpio",
 412 +               .owner = THIS_MODULE,
 413 +               .of_match_table = ralink_gpio_match,
 414 +       },
 415 +};
 416 +
 417 +static int __init ralink_gpio_init(void)
 418 +{
 419 +       return platform_driver_register(&ralink_gpio_driver);
 420 +}
 421 +
 422 +subsys_initcall(ralink_gpio_init);
 423 --
 424 1.7.10.4
 425