target/linux/ramips/patches-4.3/0043-spi-add-mt7621-support.patch

   1 From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 09:49:07 +0100
   4 Subject: [PATCH 43/53] spi: add mt7621 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/spi/Kconfig      |    6 +
   9  drivers/spi/Makefile     |    1 +
  10  drivers/spi/spi-mt7621.c |  480 ++++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 487 insertions(+)
  12  create mode 100644 drivers/spi/spi-mt7621.c
  13
  14 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
  15 index 7c592ce..2f05c85 100644
  16 --- a/drivers/spi/Kconfig
  17 +++ b/drivers/spi/Kconfig
  18 @@ -463,6 +463,12 @@ config SPI_RT2880
  19         help
  20           This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  21
  22 +config SPI_MT7621
  23 +       tristate "MediaTek MT7621 SPI Controller"
  24 +       depends on RALINK
  25 +       help
  26 +         This selects a driver for the MediaTek MT7621 SPI Controller.
  27 +
  28  config SPI_S3C24XX
  29         tristate "Samsung S3C24XX series SPI"
  30         depends on ARCH_S3C24XX
  31 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
  32 index 3d690ef..5389710 100644
  33 --- a/drivers/spi/Makefile
  34 +++ b/drivers/spi/Makefile
  35 @@ -49,6 +49,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC)         += spi-mpc512x-psc.o
  36  obj-$(CONFIG_SPI_MPC52xx_PSC)          += spi-mpc52xx-psc.o
  37  obj-$(CONFIG_SPI_MPC52xx)              += spi-mpc52xx.o
  38  obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
  39 +obj-$(CONFIG_SPI_MT7621)               += spi-mt7621.o
  40  obj-$(CONFIG_SPI_MXS)                  += spi-mxs.o
  41  obj-$(CONFIG_SPI_NUC900)               += spi-nuc900.o
  42  obj-$(CONFIG_SPI_OC_TINY)              += spi-oc-tiny.o
  43 diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c
  44 new file mode 100644
  45 index 0000000..dedf4a1
  46 --- /dev/null
  47 +++ b/drivers/spi/spi-mt7621.c
  48 @@ -0,0 +1,480 @@
  49 +/*
  50 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
  51 + *
  52 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  53 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  54 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@openwrt.org>
  55 + *
  56 + * Some parts are based on spi-orion.c:
  57 + *   Author: Shadi Ammouri <shadi@marvell.com>
  58 + *   Copyright (C) 2007-2008 Marvell Ltd.
  59 + *
  60 + * This program is free software; you can redistribute it and/or modify
  61 + * it under the terms of the GNU General Public License version 2 as
  62 + * published by the Free Software Foundation.
  63 + */
  64 +
  65 +#include <linux/init.h>
  66 +#include <linux/module.h>
  67 +#include <linux/clk.h>
  68 +#include <linux/err.h>
  69 +#include <linux/delay.h>
  70 +#include <linux/io.h>
  71 +#include <linux/reset.h>
  72 +#include <linux/spi/spi.h>
  73 +#include <linux/of_device.h>
  74 +#include <linux/platform_device.h>
  75 +#include <linux/swab.h>
  76 +
  77 +#include <ralink_regs.h>
  78 +
  79 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
  80 +
  81 +#define DRIVER_NAME                    "spi-mt7621"
  82 +/* in usec */
  83 +#define RALINK_SPI_WAIT_MAX_LOOP       2000
  84 +
  85 +/* SPISTAT register bit field */
  86 +#define SPISTAT_BUSY                   BIT(0)
  87 +
  88 +#define MT7621_SPI_TRANS       0x00
  89 +#define SPITRANS_BUSY          BIT(16)
  90 +
  91 +#define MT7621_SPI_OPCODE      0x04
  92 +#define MT7621_SPI_DATA0       0x08
  93 +#define MT7621_SPI_DATA4       0x18
  94 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
  95 +#define SPI_CTL_START          BIT(8)
  96 +
  97 +#define MT7621_SPI_POLAR       0x38
  98 +#define MT7621_SPI_MASTER      0x28
  99 +#define MT7621_SPI_MOREBUF     0x2c
 100 +#define MT7621_SPI_SPACE       0x3c
 101 +
 102 +#define MT7621_CPHA            BIT(5)
 103 +#define MT7621_CPOL            BIT(4)
 104 +#define MT7621_LSB_FIRST       BIT(3)
 105 +
 106 +#define RT2880_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
 107 +
 108 +struct mt7621_spi;
 109 +
 110 +struct mt7621_spi {
 111 +       struct spi_master       *master;
 112 +       void __iomem            *base;
 113 +       unsigned int            sys_freq;
 114 +       unsigned int            speed;
 115 +       struct clk              *clk;
 116 +       spinlock_t              lock;
 117 +
 118 +       struct mt7621_spi_ops   *ops;
 119 +};
 120 +
 121 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
 122 +{
 123 +       return spi_master_get_devdata(spi->master);
 124 +}
 125 +
 126 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
 127 +{
 128 +       return ioread32(rs->base + reg);
 129 +}
 130 +
 131 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
 132 +{
 133 +       iowrite32(val, rs->base + reg);
 134 +}
 135 +
 136 +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
 137 +{
 138 +       u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
 139 +
 140 +       master |= 7 << 29;
 141 +       master |= 1 << 2;
 142 +       if (duplex)
 143 +               master |= 1 << 10;
 144 +       else
 145 +               master &= ~(1 << 10);
 146 +
 147 +       mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
 148 +}
 149 +
 150 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
 151 +{
 152 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 153 +       int cs = spi->chip_select;
 154 +       u32 polar = 0;
 155 +
 156 +        mt7621_spi_reset(rs, cs);
 157 +       if (enable)
 158 +               polar = BIT(cs);
 159 +       mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
 160 +}
 161 +
 162 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
 163 +{
 164 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 165 +       u32 rate;
 166 +       u32 reg;
 167 +
 168 +       dev_dbg(&spi->dev, "speed:%u\n", speed);
 169 +
 170 +       rate = DIV_ROUND_UP(rs->sys_freq, speed);
 171 +       dev_dbg(&spi->dev, "rate-1:%u\n", rate);
 172 +
 173 +       if (rate > 4097)
 174 +               return -EINVAL;
 175 +
 176 +       if (rate < 2)
 177 +               rate = 2;
 178 +
 179 +       reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
 180 +       reg &= ~(0xfff << 16);
 181 +       reg |= (rate - 2) << 16;
 182 +       rs->speed = speed;
 183 +
 184 +       reg &= ~MT7621_LSB_FIRST;
 185 +       if (spi->mode & SPI_LSB_FIRST)
 186 +               reg |= MT7621_LSB_FIRST;
 187 +
 188 +       reg &= ~(MT7621_CPHA | MT7621_CPOL);
 189 +       switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
 190 +               case SPI_MODE_0:
 191 +                       break;
 192 +               case SPI_MODE_1:
 193 +                       reg |= MT7621_CPHA;
 194 +                       break;
 195 +               case SPI_MODE_2:
 196 +                       reg |= MT7621_CPOL;
 197 +                       break;
 198 +               case SPI_MODE_3:
 199 +                       reg |= MT7621_CPOL | MT7621_CPHA;
 200 +                       break;
 201 +       }
 202 +       mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
 203 +
 204 +       return 0;
 205 +}
 206 +
 207 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
 208 +{
 209 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 210 +       int i;
 211 +
 212 +       for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 213 +               u32 status;
 214 +
 215 +               status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 216 +               if ((status & SPITRANS_BUSY) == 0) {
 217 +                       return 0;
 218 +               }
 219 +               cpu_relax();
 220 +               udelay(1);
 221 +       }
 222 +
 223 +       return -ETIMEDOUT;
 224 +}
 225 +
 226 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
 227 +                                          struct spi_message *m)
 228 +{
 229 +       struct mt7621_spi *rs = spi_master_get_devdata(master);
 230 +       struct spi_device *spi = m->spi;
 231 +       unsigned int speed = spi->max_speed_hz;
 232 +       struct spi_transfer *t = NULL;
 233 +       int status = 0;
 234 +       int i, len = 0;
 235 +       int rx_len = 0;
 236 +       u32 data[9] = { 0 };
 237 +       u32 val;
 238 +
 239 +       mt7621_spi_wait_till_ready(spi);
 240 +
 241 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 242 +               const u8 *buf = t->tx_buf;
 243 +
 244 +               if (t->rx_buf)
 245 +                       rx_len += t->len;
 246 +
 247 +               if (!buf)
 248 +                       continue;
 249 +
 250 +               if (WARN_ON(len + t->len > 36)) {
 251 +                       status = -EIO;
 252 +                       goto msg_done;
 253 +               }
 254 +
 255 +               for (i = 0; i < t->len; i++, len++)
 256 +                       data[len / 4] |= buf[i] << (8 * (len & 3));
 257 +       }
 258 +
 259 +       if (WARN_ON(rx_len > 32)) {
 260 +               status = -EIO;
 261 +               goto msg_done;
 262 +       }
 263 +
 264 +       if (mt7621_spi_prepare(spi, speed)) {
 265 +               status = -EIO;
 266 +               goto msg_done;
 267 +       }
 268 +       data[0] = swab32(data[0]);
 269 +       if (len < 4)
 270 +               data[0] >>= (4 - len) * 8;
 271 +
 272 +       for (i = 0; i < len; i += 4)
 273 +               mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
 274 +
 275 +       val = (min_t(int, len, 4) * 8) << 24;
 276 +       if (len > 4)
 277 +               val |= (len - 4) * 8;
 278 +       val |= (rx_len * 8) << 12;
 279 +       mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
 280 +
 281 +       mt7621_spi_set_cs(spi, 1);
 282 +
 283 +       val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 284 +       val |= SPI_CTL_START;
 285 +       mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
 286 +
 287 +       mt7621_spi_wait_till_ready(spi);
 288 +
 289 +       mt7621_spi_set_cs(spi, 0);
 290 +
 291 +       for (i = 0; i < rx_len; i += 4)
 292 +               data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
 293 +
 294 +       m->actual_length = len + rx_len;
 295 +
 296 +       len = 0;
 297 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 298 +               u8 *buf = t->rx_buf;
 299 +
 300 +               if (!buf)
 301 +                       continue;
 302 +
 303 +               for (i = 0; i < t->len; i++, len++)
 304 +                       buf[i] = data[len / 4] >> (8 * (len & 3));
 305 +       }
 306 +
 307 +msg_done:
 308 +       m->status = status;
 309 +       spi_finalize_current_message(master);
 310 +
 311 +       return 0;
 312 +}
 313 +
 314 +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
 315 +                                          struct spi_message *m)
 316 +{
 317 +       struct mt7621_spi *rs = spi_master_get_devdata(master);
 318 +       struct spi_device *spi = m->spi;
 319 +       unsigned int speed = spi->max_speed_hz;
 320 +       struct spi_transfer *t = NULL;
 321 +       int status = 0;
 322 +       int i, len = 0;
 323 +       int rx_len = 0;
 324 +       u32 data[9] = { 0 };
 325 +       u32 val = 0;
 326 +
 327 +       mt7621_spi_wait_till_ready(spi);
 328 +
 329 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 330 +               const u8 *buf = t->tx_buf;
 331 +
 332 +               if (t->rx_buf)
 333 +                       rx_len += t->len;
 334 +
 335 +               if (!buf)
 336 +                       continue;
 337 +
 338 +               if (WARN_ON(len + t->len > 16)) {
 339 +                       status = -EIO;
 340 +                       goto msg_done;
 341 +               }
 342 +
 343 +               for (i = 0; i < t->len; i++, len++)
 344 +                       data[len / 4] |= buf[i] << (8 * (len & 3));
 345 +               if (speed > t->speed_hz)
 346 +                       speed = t->speed_hz;
 347 +       }
 348 +
 349 +       if (WARN_ON(rx_len > 16)) {
 350 +               status = -EIO;
 351 +               goto msg_done;
 352 +       }
 353 +
 354 +       if (mt7621_spi_prepare(spi, speed)) {
 355 +               status = -EIO;
 356 +               goto msg_done;
 357 +       }
 358 +
 359 +       for (i = 0; i < len; i += 4)
 360 +               mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
 361 +
 362 +       val |= len * 8;
 363 +       val |= (rx_len * 8) << 12;
 364 +       mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
 365 +
 366 +       mt7621_spi_set_cs(spi, 1);
 367 +
 368 +       val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 369 +       val |= SPI_CTL_START;
 370 +       mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
 371 +
 372 +       mt7621_spi_wait_till_ready(spi);
 373 +
 374 +       mt7621_spi_set_cs(spi, 0);
 375 +
 376 +       for (i = 0; i < rx_len; i += 4)
 377 +               data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
 378 +
 379 +       m->actual_length = rx_len;
 380 +
 381 +       len = 0;
 382 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 383 +               u8 *buf = t->rx_buf;
 384 +
 385 +               if (!buf)
 386 +                       continue;
 387 +
 388 +               for (i = 0; i < t->len; i++, len++)
 389 +                       buf[i] = data[len / 4] >> (8 * (len & 3));
 390 +       }
 391 +
 392 +msg_done:
 393 +       m->status = status;
 394 +       spi_finalize_current_message(master);
 395 +
 396 +       return 0;
 397 +}
 398 +
 399 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
 400 +                                          struct spi_message *m)
 401 +{
 402 +       struct spi_device *spi = m->spi;
 403 +       int cs = spi->chip_select;
 404 +
 405 +       if (cs)
 406 +               return mt7621_spi_transfer_full_duplex(master, m);
 407 +       return mt7621_spi_transfer_half_duplex(master, m);
 408 +}
 409 +
 410 +static int mt7621_spi_setup(struct spi_device *spi)
 411 +{
 412 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 413 +
 414 +       if ((spi->max_speed_hz == 0) ||
 415 +               (spi->max_speed_hz > (rs->sys_freq / 2)))
 416 +               spi->max_speed_hz = (rs->sys_freq / 2);
 417 +
 418 +       if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
 419 +               dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
 420 +                       spi->max_speed_hz);
 421 +               return -EINVAL;
 422 +       }
 423 +
 424 +       return 0;
 425 +}
 426 +
 427 +static const struct of_device_id mt7621_spi_match[] = {
 428 +       { .compatible = "ralink,mt7621-spi" },
 429 +       {},
 430 +};
 431 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
 432 +
 433 +static int mt7621_spi_probe(struct platform_device *pdev)
 434 +{
 435 +       const struct of_device_id *match;
 436 +       struct spi_master *master;
 437 +       struct mt7621_spi *rs;
 438 +       unsigned long flags;
 439 +       void __iomem *base;
 440 +       struct resource *r;
 441 +       int status = 0;
 442 +       struct clk *clk;
 443 +       struct mt7621_spi_ops *ops;
 444 +
 445 +       match = of_match_device(mt7621_spi_match, &pdev->dev);
 446 +       if (!match)
 447 +               return -EINVAL;
 448 +       ops = (struct mt7621_spi_ops *)match->data;
 449 +
 450 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 451 +       base = devm_ioremap_resource(&pdev->dev, r);
 452 +       if (IS_ERR(base))
 453 +               return PTR_ERR(base);
 454 +
 455 +       clk = devm_clk_get(&pdev->dev, NULL);
 456 +       if (IS_ERR(clk)) {
 457 +               dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
 458 +                       status);
 459 +               return PTR_ERR(clk);
 460 +       }
 461 +
 462 +       status = clk_prepare_enable(clk);
 463 +       if (status)
 464 +               return status;
 465 +
 466 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 467 +       if (master == NULL) {
 468 +               dev_info(&pdev->dev, "master allocation failed\n");
 469 +               return -ENOMEM;
 470 +       }
 471 +
 472 +       master->mode_bits = RT2880_SPI_MODE_BITS;
 473 +
 474 +       master->setup = mt7621_spi_setup;
 475 +       master->transfer_one_message = mt7621_spi_transfer_one_message;
 476 +       master->bits_per_word_mask = SPI_BPW_MASK(8);
 477 +       master->dev.of_node = pdev->dev.of_node;
 478 +       master->num_chipselect = 2;
 479 +
 480 +       dev_set_drvdata(&pdev->dev, master);
 481 +
 482 +       rs = spi_master_get_devdata(master);
 483 +       rs->base = base;
 484 +       rs->clk = clk;
 485 +       rs->master = master;
 486 +       rs->sys_freq = clk_get_rate(rs->clk);
 487 +       rs->ops = ops;
 488 +       dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
 489 +       spin_lock_irqsave(&rs->lock, flags);
 490 +
 491 +       device_reset(&pdev->dev);
 492 +
 493 +       mt7621_spi_reset(rs, 0);
 494 +
 495 +       return spi_register_master(master);
 496 +}
 497 +
 498 +static int mt7621_spi_remove(struct platform_device *pdev)
 499 +{
 500 +       struct spi_master *master;
 501 +       struct mt7621_spi *rs;
 502 +
 503 +       master = dev_get_drvdata(&pdev->dev);
 504 +       rs = spi_master_get_devdata(master);
 505 +
 506 +       clk_disable(rs->clk);
 507 +       spi_unregister_master(master);
 508 +
 509 +       return 0;
 510 +}
 511 +
 512 +MODULE_ALIAS("platform:" DRIVER_NAME);
 513 +
 514 +static struct platform_driver mt7621_spi_driver = {
 515 +       .driver = {
 516 +               .name = DRIVER_NAME,
 517 +               .owner = THIS_MODULE,
 518 +               .of_match_table = mt7621_spi_match,
 519 +       },
 520 +       .probe = mt7621_spi_probe,
 521 +       .remove = mt7621_spi_remove,
 522 +};
 523 +
 524 +module_platform_driver(mt7621_spi_driver);
 525 +
 526 +MODULE_DESCRIPTION("MT7621 SPI driver");
 527 +MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
 528 +MODULE_LICENSE("GPL");
 529 --
 530 1.7.10.4
 531