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first round of rb532 cleanup
[openwrt/svn-archive/archive.git] / target / linux / rb532-2.6 / patches / 100-rb5xx_support.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2006-11-29 22:57:37.000000000 +0100
3 +++ linux.dev/arch/mips/Kconfig 2006-12-14 04:09:50.000000000 +0100
4 @@ -728,6 +728,19 @@
5 select SYS_SUPPORTS_BIG_ENDIAN
6 select TOSHIBA_BOARDS
7
8 +config MIKROTIK_RB500
9 + bool "Support for RB5xx boards"
10 + select HW_HAS_PCI
11 + select IRQ_CPU
12 + select SYS_HAS_CPU_MIPS32_R1
13 + select SYS_SUPPORTS_LITTLE_ENDIAN
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SWAP_IO_SPACE
16 + select DMA_NONCOHERENT
17 + help
18 + Support the Mikrotik(tm) Routerboard 500 series,
19 + such as the RB532.
20 +
21 config TOSHIBA_RBTX4927
22 bool "Toshiba TBTX49[23]7 board"
23 select DMA_NONCOHERENT
24 @@ -1015,7 +1028,7 @@
25
26 config MIPS_L1_CACHE_SHIFT
27 int
28 - default "4" if MACH_DECSTATION
29 + default "4" if MACH_DECSTATION || MIKROTIK_RB500
30 default "7" if SGI_IP27
31 default "5"
32
33 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
34 --- linux.old/arch/mips/Makefile 2006-12-14 03:13:55.000000000 +0100
35 +++ linux.dev/arch/mips/Makefile 2006-12-14 04:09:50.000000000 +0100
36 @@ -586,6 +586,13 @@
37 load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
38
39 #
40 +# Routerboard 532 board
41 +#
42 +core-$(CONFIG_MIKROTIK_RB500) += arch/mips/rb500/
43 +cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
44 +load-$(CONFIG_MIKROTIK_RB500) += 0xffffffff80101000
45 +
46 +#
47 # Toshiba RBTX4927 board or
48 # Toshiba RBTX4937 board
49 #
50 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
51 --- linux.old/arch/mips/mm/tlbex.c 2006-11-29 22:57:37.000000000 +0100
52 +++ linux.dev/arch/mips/mm/tlbex.c 2006-12-14 04:09:50.000000000 +0100
53 @@ -874,7 +874,6 @@
54 case CPU_R10000:
55 case CPU_R12000:
56 case CPU_R14000:
57 - case CPU_4KC:
58 case CPU_SB1:
59 case CPU_SB1A:
60 case CPU_4KSC:
61 @@ -902,6 +901,7 @@
62 tlbw(p);
63 break;
64
65 + case CPU_4KC:
66 case CPU_4KEC:
67 case CPU_24K:
68 case CPU_34K:
69 diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
70 --- linux.old/arch/mips/pci/fixup-rb500.c 1970-01-01 01:00:00.000000000 +0100
71 +++ linux.dev/arch/mips/pci/fixup-rb500.c 2006-12-14 04:09:50.000000000 +0100
72 @@ -0,0 +1,49 @@
73 +/*
74 + * Copyright 2001 MontaVista Software Inc.
75 + * Author: MontaVista Software, Inc.
76 + * stevel@mvista.com or source@mvista.com
77 + *
78 + * This program is free software; you can redistribute it and/or modify it
79 + * under the terms of the GNU General Public License as published by the
80 + * Free Software Foundation; either version 2 of the License, or (at your
81 + * option) any later version.
82 + *
83 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
84 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
85 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
86 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
87 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
88 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
89 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
90 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
91 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
92 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 + *
94 + * You should have received a copy of the GNU General Public License along
95 + * with this program; if not, write to the Free Software Foundation, Inc.,
96 + * 675 Mass Ave, Cambridge, MA 02139, USA.
97 + */
98 +
99 +#include <linux/autoconf.h>
100 +#include <linux/types.h>
101 +#include <linux/pci.h>
102 +#include <linux/kernel.h>
103 +#include <linux/init.h>
104 +
105 +#include <asm/rc32434/rc32434.h>
106 +
107 +static int __devinitdata irq_map[2][12] = {
108 + { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
109 + { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
110 +};
111 +
112 +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
113 +{
114 + int irq = 0;
115 +
116 + if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
117 + irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
118 + }
119 + return irq + GROUP4_IRQ_BASE + 4;
120 +}
121 +
122 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
123 --- linux.old/arch/mips/pci/Makefile 2006-11-29 22:57:37.000000000 +0100
124 +++ linux.dev/arch/mips/pci/Makefile 2006-12-14 04:09:50.000000000 +0100
125 @@ -53,3 +53,4 @@
126 obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
127 obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
128 obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
129 +obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o
130 diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
131 --- linux.old/arch/mips/pci/ops-rc32434.c 1970-01-01 01:00:00.000000000 +0100
132 +++ linux.dev/arch/mips/pci/ops-rc32434.c 2006-12-14 04:09:50.000000000 +0100
133 @@ -0,0 +1,195 @@
134 +/**************************************************************************
135 + *
136 + * BRIEF MODULE DESCRIPTION
137 + * pci_ops for IDT EB434 board
138 + *
139 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
140 + *
141 + * This program is free software; you can redistribute it and/or modify it
142 + * under the terms of the GNU General Public License as published by the
143 + * Free Software Foundation; either version 2 of the License, or (at your
144 + * option) any later version.
145 + *
146 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
147 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
148 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
149 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
150 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
151 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
152 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
153 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
154 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
155 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
156 + *
157 + * You should have received a copy of the GNU General Public License along
158 + * with this program; if not, write to the Free Software Foundation, Inc.,
159 + * 675 Mass Ave, Cambridge, MA 02139, USA.
160 + *
161 + *
162 + **************************************************************************
163 + * May 2004 rkt, neb
164 + *
165 + * Initial Release
166 + *
167 + *
168 + *
169 + **************************************************************************
170 + */
171 +
172 +#include <linux/autoconf.h>
173 +#include <linux/init.h>
174 +#include <linux/pci.h>
175 +#include <linux/types.h>
176 +#include <linux/delay.h>
177 +
178 +#include <asm/cpu.h>
179 +#include <asm/io.h>
180 +
181 +#include <asm/rc32434/rc32434.h>
182 +#include <asm/rc32434/pci.h>
183 +
184 +#define PCI_ACCESS_READ 0
185 +#define PCI_ACCESS_WRITE 1
186 +
187 +
188 +#define PCI_CFG_SET(bus,slot,func,off) \
189 + (rc32434_pci->pcicfga = (0x80000000 | \
190 + ((bus) << 16) | ((slot)<<11) | \
191 + ((func)<<8) | (off)))
192 +
193 +static inline int config_access(unsigned char access_type, struct pci_bus *bus,
194 + unsigned int devfn, unsigned char where,
195 + u32 * data)
196 +{
197 + unsigned int slot = PCI_SLOT(devfn);
198 + u8 func = PCI_FUNC(devfn);
199 +
200 + /* Setup address */
201 + PCI_CFG_SET(bus->number, slot, func, where);
202 + rc32434_sync();
203 +
204 + if (access_type == PCI_ACCESS_WRITE)
205 + rc32434_pci->pcicfgd = *data;
206 + else
207 + *data = rc32434_pci->pcicfgd;
208 +
209 + rc32434_sync();
210 +
211 + return 0;
212 +}
213 +
214 +
215 +/*
216 + * We can't address 8 and 16 bit words directly. Instead we have to
217 + * read/write a 32bit word and mask/modify the data we actually want.
218 + */
219 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
220 + int where, u8 * val)
221 +{
222 + u32 data;
223 + int ret;
224 +
225 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
226 + *val = (data >> ((where & 3) << 3)) & 0xff;
227 + return ret;
228 +}
229 +
230 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
231 + int where, u16 * val)
232 +{
233 + u32 data;
234 + int ret;
235 +
236 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
237 + *val = (data >> ((where & 3) << 3)) & 0xffff;
238 + return ret;
239 +}
240 +
241 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
242 + int where, u32 * val)
243 +{
244 + int ret;
245 +
246 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
247 + return ret;
248 +}
249 +
250 +static int
251 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
252 + u8 val)
253 +{
254 + u32 data = 0;
255 +
256 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
257 + return -1;
258 +
259 + data = (data & ~(0xff << ((where & 3) << 3))) |
260 + (val << ((where & 3) << 3));
261 +
262 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
263 + return -1;
264 +
265 + return PCIBIOS_SUCCESSFUL;
266 +}
267 +
268 +
269 +static int
270 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
271 + u16 val)
272 +{
273 + u32 data = 0;
274 +
275 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
276 + return -1;
277 +
278 + data = (data & ~(0xffff << ((where & 3) << 3))) |
279 + (val << ((where & 3) << 3));
280 +
281 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
282 + return -1;
283 +
284 +
285 + return PCIBIOS_SUCCESSFUL;
286 +}
287 +
288 +
289 +static int
290 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
291 + u32 val)
292 +{
293 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
294 + return -1;
295 +
296 + return PCIBIOS_SUCCESSFUL;
297 +}
298 +
299 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
300 + int where, int size, u32 * val)
301 +{
302 + switch (size) {
303 + case 1:
304 + return read_config_byte(bus, devfn, where, (u8 *) val);
305 + case 2:
306 + return read_config_word(bus, devfn, where, (u16 *) val);
307 + default:
308 + return read_config_dword(bus, devfn, where, val);
309 + }
310 +}
311 +
312 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
313 + int where, int size, u32 val)
314 +{
315 + switch (size) {
316 + case 1:
317 + return write_config_byte(bus, devfn, where, (u8) val);
318 + case 2:
319 + return write_config_word(bus, devfn, where, (u16) val);
320 + default:
321 + return write_config_dword(bus, devfn, where, val);
322 + }
323 +}
324 +
325 +struct pci_ops rc32434_pci_ops = {
326 + .read = pci_config_read,
327 + .write = pci_config_write,
328 +};
329 diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
330 --- linux.old/arch/mips/pci/pci-rc32434.c 1970-01-01 01:00:00.000000000 +0100
331 +++ linux.dev/arch/mips/pci/pci-rc32434.c 2006-12-14 04:09:50.000000000 +0100
332 @@ -0,0 +1,234 @@
333 +/**************************************************************************
334 + *
335 + * BRIEF MODULE DESCRIPTION
336 + * PCI initialization for IDT EB434 board
337 + *
338 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
339 + *
340 + * This program is free software; you can redistribute it and/or modify it
341 + * under the terms of the GNU General Public License as published by the
342 + * Free Software Foundation; either version 2 of the License, or (at your
343 + * option) any later version.
344 + *
345 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
346 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
347 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
348 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
349 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
350 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
351 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
352 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
353 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
354 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
355 + *
356 + * You should have received a copy of the GNU General Public License along
357 + * with this program; if not, write to the Free Software Foundation, Inc.,
358 + * 675 Mass Ave, Cambridge, MA 02139, USA.
359 + *
360 + *
361 + **************************************************************************
362 + * May 2004 rkt, neb
363 + *
364 + * Initial Release
365 + *
366 + *
367 + *
368 + **************************************************************************
369 + */
370 +
371 +#include <linux/autoconf.h>
372 +#include <linux/types.h>
373 +#include <linux/pci.h>
374 +#include <linux/kernel.h>
375 +#include <linux/init.h>
376 +
377 +#include <asm/rc32434/rc32434.h>
378 +#include <asm/rc32434/pci.h>
379 +
380 +#define PCI_ACCESS_READ 0
381 +#define PCI_ACCESS_WRITE 1
382 +
383 +/* define an unsigned array for the PCI registers */
384 +unsigned int korinaCnfgRegs[25] = {
385 + KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
386 + KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
387 + KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
388 + KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
389 + KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
390 + KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
391 +};
392 +static struct resource rc32434_res_pci_mem1;
393 +static struct resource rc32434_res_pci_mem2;
394 +
395 +static struct resource rc32434_res_pci_mem1 = {
396 + .name = "PCI MEM1",
397 + .start = 0x50000000,
398 + .end = 0x5FFFFFFF,
399 + .flags = IORESOURCE_MEM,
400 + .parent = &rc32434_res_pci_mem1,
401 + .sibling = NULL,
402 + .child = &rc32434_res_pci_mem2
403 +};
404 +
405 +static struct resource rc32434_res_pci_mem2 = {
406 + .name = "PCI Mem2",
407 + .start = 0x60000000,
408 + .end = 0x6FFFFFFF,
409 + .flags = IORESOURCE_MEM,
410 + .parent = &rc32434_res_pci_mem1,
411 + .sibling = NULL,
412 + .child = NULL
413 +};
414 +
415 +static struct resource rc32434_res_pci_io1 = {
416 + .name = "PCI I/O1",
417 + .start = 0x18800000,
418 + .end = 0x188FFFFF,
419 + .flags = IORESOURCE_IO,
420 +};
421 +
422 +extern struct pci_ops rc32434_pci_ops;
423 +
424 +#define PCI_MEM1_START PCI_ADDR_START
425 +#define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
426 +#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
427 +#define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1
428 +#define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
429 +#define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
430 +#define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
431 +#define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
432 +
433 +
434 +struct pci_controller rc32434_controller2;
435 +
436 +struct pci_controller rc32434_controller = {
437 + .pci_ops = &rc32434_pci_ops,
438 + .mem_resource = &rc32434_res_pci_mem1,
439 + .io_resource = &rc32434_res_pci_io1,
440 + .mem_offset = 0,
441 + .io_offset = 0,
442 +
443 +};
444 +
445 +#ifdef __MIPSEB__
446 +#define PCI_ENDIAN_FLAG PCILBAC_sb_m
447 +#else
448 +#define PCI_ENDIAN_FLAG 0
449 +#endif
450 +
451 +static int __init rc32434_pcibridge_init(void)
452 +{
453 + unsigned int pcicValue, pcicData = 0;
454 + unsigned int dummyRead, pciCntlVal;
455 + int loopCount;
456 + unsigned int pciConfigAddr;
457 +
458 + pcicValue = rc32434_pci->pcic;
459 + pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
460 + if (!((pcicValue == PCIM_H_EA) ||
461 + (pcicValue == PCIM_H_IA_FIX) ||
462 + (pcicValue == PCIM_H_IA_RR))) {
463 + printk("PCI init error!!!\n");
464 + /* Not in Host Mode, return ERROR */
465 + return -1;
466 + }
467 + /* Enables the Idle Grant mode, Arbiter Parking */
468 + pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
469 + rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
470 + /* Zero out the PCI status & PCI Status Mask */
471 + for(;;)
472 + {
473 + pcicData = rc32434_pci->pcis;
474 + if (!(pcicData & PCIS_rip_m))
475 + break;
476 + }
477 +
478 + rc32434_pci->pcis = 0;
479 + rc32434_pci->pcism = 0xFFFFFFFF;
480 + /* Zero out the PCI decoupled registers */
481 + rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
482 + rc32434_pci->pcidas=0; /* clear the status */
483 + rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
484 + /* Mask PCI Messaging Interrupts */
485 + rc32434_pci_msg->pciiic = 0;
486 + rc32434_pci_msg->pciiim = 0xFFFFFFFF;
487 + rc32434_pci_msg->pciioic = 0;
488 + rc32434_pci_msg->pciioim = 0;
489 +
490 +
491 + /* Setup PCILB0 as Memory Window */
492 + rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
493 +
494 + /* setup the PCI map address as same as the local address */
495 +
496 + rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
497 +
498 +
499 + /* Setup PCILBA1 as MEM */
500 + rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
501 + dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
502 + rc32434_pci->pcilba[1].a = 0x60000000;
503 + rc32434_pci->pcilba[1].m = 0x60000000;
504 +
505 + /* setup PCILBA2 as IO Window*/
506 + rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
507 + dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
508 + rc32434_pci->pcilba[2].a = 0x18C00000;
509 + rc32434_pci->pcilba[2].m = 0x18FFFFFF;
510 +
511 + /* setup PCILBA2 as IO Window*/
512 + rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
513 + dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
514 +
515 + /* Setup PCILBA3 as IO Window */
516 + rc32434_pci->pcilba[3].a = 0x18800000;
517 + rc32434_pci->pcilba[3].m = 0x18800000;
518 + rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
519 + dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
520 +
521 + pciConfigAddr=(unsigned int)(0x80000004);
522 + for(loopCount=0;loopCount<24;loopCount++){
523 + rc32434_pci->pcicfga=pciConfigAddr;
524 + dummyRead=rc32434_pci->pcicfga;
525 + rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
526 + dummyRead=rc32434_pci->pcicfgd;
527 + pciConfigAddr += 4;
528 + }
529 + rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
530 + | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
531 +
532 + pciCntlVal=rc32434_pci->pcic;
533 + pciCntlVal &=~(PCIC_tnr_m);
534 + rc32434_pci->pcic = pciCntlVal;
535 + pciCntlVal=rc32434_pci->pcic;
536 + return 0;
537 +}
538 +
539 +/* Do platform specific device initialization at pci_enable_device() time */
540 +int pcibios_plat_dev_init(struct pci_dev *dev)
541 +{
542 + if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
543 + /* disable prefetched memory range */
544 + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
545 + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
546 +
547 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
548 + }
549 + return 0;
550 +}
551 +
552 +static int __init rc32434_pci_init(void)
553 +{
554 + printk("PCI: Initializing PCI\n");
555 +
556 + ioport_resource.start = rc32434_res_pci_io1.start;
557 + ioport_resource.end = rc32434_res_pci_io1.end;
558 +
559 + rc32434_pcibridge_init();
560 +
561 + register_pci_controller(&rc32434_controller);
562 + rc32434_sync();
563 +}
564 +
565 +arch_initcall(rc32434_pci_init);
566 +
567 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
568 --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
569 +++ linux.dev/arch/mips/rb500/devices.c 2006-12-14 04:09:50.000000000 +0100
570 @@ -0,0 +1,210 @@
571 +/*
572 + * RouterBoard 500 Platform devices
573 + *
574 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
575 + *
576 + * This program is free software; you can redistribute it and/or modify
577 + * it under the terms of the GNU General Public License as published by
578 + * the Free Software Foundation; either version 2 of the License, or
579 + * (at your option) any later version.
580 + *
581 + * This program is distributed in the hope that it will be useful,
582 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
583 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
584 + * GNU General Public License for more details.
585 + *
586 + * $Id$
587 + */
588 +#include <linux/kernel.h>
589 +#include <linux/init.h>
590 +#include <linux/module.h>
591 +#include <linux/ctype.h>
592 +#include <linux/string.h>
593 +#include <linux/platform_device.h>
594 +#include <asm/unaligned.h>
595 +#include <asm/io.h>
596 +
597 +#include <asm/rc32434/rc32434.h>
598 +#include <asm/rc32434/dma.h>
599 +#include <asm/rc32434/dma_v.h>
600 +#include <asm/rc32434/eth.h>
601 +#include <asm/rc32434/rb.h>
602 +
603 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
604 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
605 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
606 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
607 +
608 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
609 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
610 +
611 +static struct resource korina_dev0_res[] = {
612 + {
613 + .name = "korina_regs",
614 + .start = ETH0_PhysicalAddress,
615 + .end = ETH0_PhysicalAddress + sizeof(ETH_t),
616 + .flags = IORESOURCE_MEM,
617 + },
618 + {
619 + .name = "korina_rx",
620 + .start = ETH0_DMA_RX_IRQ,
621 + .end = ETH0_DMA_RX_IRQ,
622 + .flags = IORESOURCE_IRQ
623 + },
624 + {
625 + .name = "korina_tx",
626 + .start = ETH0_DMA_TX_IRQ,
627 + .end = ETH0_DMA_TX_IRQ,
628 + .flags = IORESOURCE_IRQ
629 + },
630 + {
631 + .name = "korina_ovr",
632 + .start = ETH0_RX_OVR_IRQ,
633 + .end = ETH0_RX_OVR_IRQ,
634 + .flags = IORESOURCE_IRQ
635 + },
636 + {
637 + .name = "korina_und",
638 + .start = ETH0_TX_UND_IRQ,
639 + .end = ETH0_TX_UND_IRQ,
640 + .flags = IORESOURCE_IRQ
641 + },
642 + {
643 + .name = "korina_dma_rx",
644 + .start = ETH0_RX_DMA_ADDR,
645 + .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
646 + .flags = IORESOURCE_MEM,
647 + },
648 + {
649 + .name = "korina_dma_tx",
650 + .start = ETH0_TX_DMA_ADDR,
651 + .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
652 + .flags = IORESOURCE_MEM,
653 + }
654 +};
655 +
656 +static struct korina_device korina_dev0_data = {
657 + .name = "korina0",
658 + .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee }
659 +};
660 +
661 +static struct platform_device korina_dev0 = {
662 + .id = 0,
663 + .name = "korina",
664 + .dev.platform_data = &korina_dev0_data,
665 + .resource = korina_dev0_res,
666 + .num_resources = ARRAY_SIZE(korina_dev0_res),
667 +};
668 +
669 +
670 +#define CF_GPIO_NUM 13
671 +
672 +static struct resource cf_slot0_res[] = {
673 + {
674 + .name = "cf_membase",
675 + .flags = IORESOURCE_MEM
676 + },
677 + {
678 + .name = "cf_irq",
679 + .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
680 + .end = (8 + 4 * 32 + CF_GPIO_NUM),
681 + .flags = IORESOURCE_IRQ
682 + }
683 +};
684 +
685 +static struct cf_device cf_slot0_data = {
686 + .gpio_pin = 13
687 +};
688 +
689 +static struct platform_device cf_slot0 = {
690 + .id = 0,
691 + .name = "rb500-cf",
692 + .dev.platform_data = &cf_slot0_data,
693 + .resource = cf_slot0_res,
694 + .num_resources = ARRAY_SIZE(cf_slot0_res),
695 +};
696 +
697 +/* Resources and device for NAND. There is no data needed and no irqs, so just define the memory used. */
698 +static struct resource nand_slot0_res[] = {
699 + {
700 + .name = "nand_membase",
701 + .flags = IORESOURCE_MEM
702 + }
703 +};
704 +
705 +static struct platform_device nand_slot0 = {
706 + .id = 0,
707 + .name = "rb500-nand",
708 + .resource = nand_slot0_res,
709 + .num_resources = ARRAY_SIZE(nand_slot0_res),
710 +};
711 +
712 +
713 +static struct platform_device *rb500_devs[] = {
714 + &korina_dev0,
715 + &nand_slot0,
716 + &cf_slot0
717 +};
718 +
719 +static void __init parse_mac_addr(char* macstr)
720 +{
721 + int i, j;
722 + unsigned char result, value;
723 +
724 + for (i=0; i<6; i++) {
725 + result = 0;
726 + if (i != 5 && *(macstr+2) != ':') {
727 + return;
728 + }
729 + for (j=0; j<2; j++) {
730 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
731 + toupper(*macstr)-'A'+10) < 16) {
732 + result = result*16 + value;
733 + macstr++;
734 + }
735 + else return;
736 + }
737 +
738 + macstr++;
739 + korina_dev0_data.mac[i] = result;
740 + }
741 +}
742 +
743 +
744 +/* DEVICE CONTROLLER 1 */
745 +#define CFG_DC_DEV1 (void*)0xb8010010
746 +#define CFG_DC_DEV2 (void*)0xb8010020
747 +#define CFG_DC_DEVBASE 0x0
748 +#define CFG_DC_DEVMASK 0x4
749 +#define CFG_DC_DEVC 0x8
750 +#define CFG_DC_DEVTC 0xC
751 +
752 +
753 +static int __init plat_setup_devices(void)
754 +{
755 + /* Look for the CF card reader */
756 + if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
757 + rb500_devs[1] = NULL;
758 + else {
759 + cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
760 + cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
761 + }
762 +
763 + /* There is always a NAND device */
764 + nand_slot0_res[0].start = readl( CFG_DC_DEV2 + CFG_DC_DEVBASE);
765 + nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
766 +
767 + return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
768 +}
769 +
770 +static int __init setup_kmac(char *s)
771 +{
772 + printk("korina mac = %s\n",s);
773 + parse_mac_addr(s);
774 + return 0;
775 +}
776 +
777 +__setup("kmac=", setup_kmac);
778 +arch_initcall(plat_setup_devices);
779 +
780 +
781 diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
782 --- linux.old/arch/mips/rb500/irq.c 1970-01-01 01:00:00.000000000 +0100
783 +++ linux.dev/arch/mips/rb500/irq.c 2006-12-14 04:14:16.000000000 +0100
784 @@ -0,0 +1,264 @@
785 +/*
786 + * BRIEF MODULE DESCRIPTION
787 + * RC32434 interrupt routines.
788 + *
789 + * Copyright 2002 MontaVista Software Inc.
790 + * Author: MontaVista Software, Inc.
791 + * stevel@mvista.com or source@mvista.com
792 + *
793 + * This program is free software; you can redistribute it and/or modify it
794 + * under the terms of the GNU General Public License as published by the
795 + * Free Software Foundation; either version 2 of the License, or (at your
796 + * option) any later version.
797 + *
798 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
799 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
800 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
801 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
802 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
803 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
804 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
805 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
806 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
807 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
808 + *
809 + * You should have received a copy of the GNU General Public License along
810 + * with this program; if not, write to the Free Software Foundation, Inc.,
811 + * 675 Mass Ave, Cambridge, MA 02139, USA.
812 + */
813 +
814 +#include <linux/errno.h>
815 +#include <linux/init.h>
816 +#include <linux/kernel_stat.h>
817 +#include <linux/module.h>
818 +#include <linux/signal.h>
819 +#include <linux/sched.h>
820 +#include <linux/types.h>
821 +#include <linux/interrupt.h>
822 +#include <linux/ioport.h>
823 +#include <linux/timex.h>
824 +#include <linux/slab.h>
825 +#include <linux/random.h>
826 +#include <linux/delay.h>
827 +
828 +#include <asm/bitops.h>
829 +#include <asm/bootinfo.h>
830 +#include <asm/io.h>
831 +#include <asm/irq.h>
832 +#include <asm/time.h>
833 +#include <asm/mipsregs.h>
834 +#include <asm/system.h>
835 +#include <asm/rc32434/rc32434.h>
836 +#include <asm/rc32434/gpio.h>
837 +
838 +extern void set_debug_traps(void);
839 +extern irq_cpustat_t irq_stat [NR_CPUS];
840 +unsigned int local_bh_count[NR_CPUS];
841 +unsigned int local_irq_count[NR_CPUS];
842 +
843 +static unsigned int startup_irq(unsigned int irq);
844 +static void rb500_end_irq(unsigned int irq_nr);
845 +static void mask_and_ack_irq(unsigned int irq_nr);
846 +static void rb500_enable_irq(unsigned int irq_nr);
847 +static void rb500_disable_irq(unsigned int irq_nr);
848 +
849 +extern void __init init_generic_irq(void);
850 +
851 +typedef struct {
852 + u32 mask; /* mask of valid bits in pending/mask registers */
853 + volatile u32 *base_addr;
854 +} intr_group_t;
855 +
856 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
857 +
858 +#if (NR_IRQS < RC32434_NR_IRQS)
859 +#error Too little irqs defined. Did you override <asm/irq.h> ?
860 +#endif
861 +
862 +static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
863 + { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
864 + { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
865 + { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
866 + { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
867 + { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
868 +};
869 +
870 +#define READ_PEND(base) (*(base))
871 +#define READ_MASK(base) (*(base + 2))
872 +#define WRITE_MASK(base, val) (*(base + 2) = (val))
873 +
874 +static inline int irq_to_group(unsigned int irq_nr)
875 +{
876 + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
877 +}
878 +
879 +static inline int group_to_ip(unsigned int group)
880 +{
881 + return group + 2;
882 +}
883 +
884 +static inline void enable_local_irq(unsigned int ip)
885 +{
886 + int ipnum = 0x100 << ip;
887 + clear_c0_cause(ipnum);
888 + set_c0_status(ipnum);
889 +}
890 +
891 +static inline void disable_local_irq(unsigned int ip)
892 +{
893 + int ipnum = 0x100 << ip;
894 + clear_c0_status(ipnum);
895 +}
896 +
897 +static inline void ack_local_irq(unsigned int ip)
898 +{
899 + int ipnum = 0x100 << ip;
900 + clear_c0_cause(ipnum);
901 +}
902 +
903 +static void rb500_enable_irq(unsigned int irq_nr)
904 +{
905 + int ip = irq_nr - GROUP0_IRQ_BASE;
906 + unsigned int group, intr_bit;
907 + volatile unsigned int *addr;
908 +
909 +
910 + if (ip < 0)
911 + enable_local_irq(irq_nr);
912 + else {
913 + group = ip >> 5;
914 +
915 + ip &= (1<<5)-1;
916 + intr_bit = 1 << ip;
917 +
918 + enable_local_irq(group_to_ip(group));
919 +
920 + addr = intr_group[group].base_addr;
921 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
922 + }
923 +}
924 +
925 +static void rb500_disable_irq(unsigned int irq_nr)
926 +{
927 + int ip = irq_nr - GROUP0_IRQ_BASE;
928 + unsigned int group, intr_bit, mask;
929 + volatile unsigned int *addr;
930 +
931 + if (ip < 0) {
932 + disable_local_irq(irq_nr);
933 + }else{
934 + group = ip >> 5;
935 +
936 + ip &= (1<<5) -1;
937 + intr_bit = 1 << ip;
938 + addr = intr_group[group].base_addr;
939 + mask = READ_MASK(addr);
940 + mask |= intr_bit;
941 + WRITE_MASK(addr,mask);
942 +
943 + /*
944 + * if there are no more interrupts enabled in this
945 + * group, disable corresponding IP
946 + */
947 + if (mask == intr_group[group].mask)
948 + disable_local_irq(group_to_ip(group));
949 + }
950 +}
951 +
952 +static unsigned int startup_irq(unsigned int irq_nr)
953 +{
954 + rb500_enable_irq(irq_nr);
955 + return 0;
956 +}
957 +
958 +static void shutdown_irq(unsigned int irq_nr)
959 +{
960 + rb500_disable_irq(irq_nr);
961 + return;
962 +}
963 +
964 +static void mask_and_ack_irq(unsigned int irq_nr)
965 +{
966 + rb500_disable_irq(irq_nr);
967 + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
968 +}
969 +
970 +static void rb500_end_irq(unsigned int irq_nr)
971 +{
972 +
973 + int ip = irq_nr - GROUP0_IRQ_BASE;
974 + unsigned int intr_bit, group;
975 + volatile unsigned int *addr;
976 +
977 + if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
978 + printk("warning: end_irq %d did not enable (%x)\n",
979 + irq_nr, irq_desc[irq_nr].status);
980 + return;
981 + }
982 +
983 + if (ip < 0) {
984 + enable_local_irq(irq_nr);
985 + } else {
986 + group = ip >> 5;
987 +
988 + ip &= (1 << 5) - 1;
989 + intr_bit = 1 << ip;
990 +
991 + if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
992 + gpio->gpioistat = gpio->gpioistat & ~intr_bit;
993 + }
994 +
995 + enable_local_irq(group_to_ip(group));
996 +
997 + addr = intr_group[group].base_addr;
998 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
999 + }
1000 +}
1001 +
1002 +static struct hw_interrupt_type rc32434_irq_type = {
1003 + .typename = "RB500",
1004 + .startup = startup_irq,
1005 + .shutdown = shutdown_irq,
1006 + .enable = rb500_enable_irq,
1007 + .disable = rb500_disable_irq,
1008 + .ack = mask_and_ack_irq,
1009 + .end = rb500_end_irq,
1010 +};
1011 +
1012 +
1013 +void __init arch_init_irq(void)
1014 +{
1015 + int i;
1016 +
1017 + printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
1018 + memset(irq_desc, 0, sizeof(irq_desc));
1019 +
1020 + for (i = 0; i < RC32434_NR_IRQS; i++) {
1021 + irq_desc[i].status = IRQ_DISABLED;
1022 + irq_desc[i].action = NULL;
1023 + irq_desc[i].depth = 1;
1024 + irq_desc[i].chip = &rc32434_irq_type;
1025 + spin_lock_init(&irq_desc[i].lock);
1026 + }
1027 +}
1028 +
1029 +/* Main Interrupt dispatcher */
1030 +asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
1031 +{
1032 + unsigned int ip, pend, group;
1033 + volatile unsigned int *addr;
1034 + unsigned int cp0_cause = read_c0_cause() & read_c0_status();
1035 +
1036 + if (cp0_cause & CAUSEF_IP7) {
1037 + ll_timer_interrupt(7);
1038 + } else if ((ip = (cp0_cause & 0x7c00))) {
1039 + group = 21 - rc32434_clz(ip);
1040 +
1041 + addr = intr_group[group].base_addr;
1042 +
1043 + pend = READ_PEND(addr);
1044 + pend &= ~READ_MASK(addr); // only unmasked interrupts
1045 + pend = 39 - rc32434_clz(pend);
1046 + do_IRQ((group << 5) + pend);
1047 + }
1048 +}
1049 diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
1050 --- linux.old/arch/mips/rb500/Makefile 1970-01-01 01:00:00.000000000 +0100
1051 +++ linux.dev/arch/mips/rb500/Makefile 2006-12-14 04:09:50.000000000 +0100
1052 @@ -0,0 +1,5 @@
1053 +#
1054 +# Makefile for the RB500 board specific parts of the kernel
1055 +#
1056 +
1057 +obj-y += irq.o time.o setup.o serial.o prom.o misc.o devices.o
1058 diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
1059 --- linux.old/arch/mips/rb500/misc.c 1970-01-01 01:00:00.000000000 +0100
1060 +++ linux.dev/arch/mips/rb500/misc.c 2006-12-14 04:09:50.000000000 +0100
1061 @@ -0,0 +1,56 @@
1062 +#include <linux/module.h>
1063 +#include <linux/kernel.h> /* printk() */
1064 +#include <linux/types.h> /* size_t */
1065 +#include <linux/pci.h>
1066 +#include <linux/spinlock.h>
1067 +#include <asm/rc32434/rb.h>
1068 +
1069 +#define GPIO_BADDR 0xb8050000
1070 +
1071 +
1072 +static volatile unsigned char *devCtl3Base = 0;
1073 +static unsigned char latchU5State = 0;
1074 +static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
1075 +
1076 +void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) {
1077 + unsigned flags, data;
1078 + unsigned i = 0;
1079 + spin_lock_irqsave(&clu5Lock, flags);
1080 + data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
1081 + for (i = 0; i != len; ++i) {
1082 + if (val & (1 << i)) data |= (1 << (i + bit));
1083 + else data &= ~(1 << (i + bit));
1084 + }
1085 + *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
1086 + spin_unlock_irqrestore(&clu5Lock, flags);
1087 +}
1088 +
1089 +void changeLatchU5(unsigned char orMask, unsigned char nandMask) {
1090 + unsigned flags;
1091 + spin_lock_irqsave(&clu5Lock, flags);
1092 + latchU5State = (latchU5State | orMask) & ~nandMask;
1093 + if( !devCtl3Base) devCtl3Base = (volatile unsigned char *)
1094 + KSEG1ADDR(*(volatile unsigned *) KSEG1ADDR(0x18010030));
1095 + *devCtl3Base = latchU5State;
1096 + spin_unlock_irqrestore(&clu5Lock, flags);
1097 +}
1098 +
1099 +u32 gpio_get(gpio_func func)
1100 +{
1101 + return readl((void *) GPIO_BADDR + func);
1102 +}
1103 +
1104 +void gpio_set(gpio_func func, u32 mask, u32 value)
1105 +{
1106 + u32 val = readl((void *) GPIO_BADDR + func);
1107 +
1108 + val &= ~mask;
1109 + val |= value & mask;
1110 +
1111 + writel(val, (void *) GPIO_BADDR + func);
1112 +}
1113 +
1114 +EXPORT_SYMBOL(gpio_set);
1115 +EXPORT_SYMBOL(gpio_get);
1116 +EXPORT_SYMBOL(set434Reg);
1117 +EXPORT_SYMBOL(changeLatchU5);
1118 diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
1119 --- linux.old/arch/mips/rb500/prom.c 1970-01-01 01:00:00.000000000 +0100
1120 +++ linux.dev/arch/mips/rb500/prom.c 2006-12-14 05:15:05.000000000 +0100
1121 @@ -0,0 +1,161 @@
1122 +/*
1123 +* prom.c
1124 +**********************************************************************
1125 +* P . Sadik Oct 10, 2003
1126 +*
1127 +* Started change log
1128 +* idt_cpu_freq is make a kernel configuration parameter
1129 +* idt_cpu_freq is exported so that other modules can use it.
1130 +* Code cleanup
1131 +**********************************************************************
1132 +* P. Sadik Oct 20, 2003
1133 +*
1134 +* Removed NVRAM code from here, since they are already available under
1135 +* nvram directory.
1136 +* Added serial port initialisation.
1137 +**********************************************************************
1138 +**********************************************************************
1139 +* P. Sadik Oct 30, 2003
1140 +*
1141 +* Added reset_cons_port
1142 +**********************************************************************
1143 +
1144 + P.Christeas, 2005-2006
1145 + Port to 2.6, add 2.6 cmdline parsing
1146 +
1147 +*/
1148 +
1149 +#include <linux/autoconf.h>
1150 +#include <linux/init.h>
1151 +#include <linux/mm.h>
1152 +#include <linux/module.h>
1153 +#include <linux/string.h>
1154 +#include <linux/console.h>
1155 +#include <asm/bootinfo.h>
1156 +#include <linux/bootmem.h>
1157 +#include <linux/ioport.h>
1158 +#include <linux/blkdev.h>
1159 +#include <asm/rc32434/ddr.h>
1160 +
1161 +#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
1162 +extern void __init setup_serial_port(void);
1163 +
1164 +unsigned int idt_cpu_freq = 132000000;
1165 +EXPORT_SYMBOL(idt_cpu_freq);
1166 +unsigned int board_type = 500;
1167 +EXPORT_SYMBOL(board_type);
1168 +unsigned int gpio_bootup_state = 0;
1169 +EXPORT_SYMBOL(gpio_bootup_state);
1170 +
1171 +
1172 +char mips_mac_address[18] = "08:00:06:05:40:01";
1173 +EXPORT_SYMBOL(mips_mac_address);
1174 +
1175 +/* what to append to cmdline when button is [not] pressed */
1176 +#define GPIO_INIT_NOBUTTON ""
1177 +#define GPIO_INIT_BUTTON " 2"
1178 +
1179 +#ifdef CONFIG_MIKROTIK_RB500
1180 +unsigned soft_reboot = 0;
1181 +EXPORT_SYMBOL(soft_reboot);
1182 +#endif
1183 +
1184 +#define SR_NMI 0x00180000 /* NMI */
1185 +#define SERIAL_SPEED_ENTRY 0x00000001
1186 +
1187 +#ifdef CONFIG_REMOTE_DEBUG
1188 +extern int remote_debug;
1189 +#endif
1190 +
1191 +extern unsigned long mips_machgroup;
1192 +extern unsigned long mips_machtype;
1193 +
1194 +#define FREQ_TAG "HZ="
1195 +#define GPIO_TAG "gpio="
1196 +#define KMAC_TAG "kmac="
1197 +#define MEM_TAG "mem="
1198 +#define BOARD_TAG "board="
1199 +#define IGNORE_CMDLINE_MEM 1
1200 +#define DEBUG_DDR
1201 +
1202 +void parse_soft_settings(unsigned *ptr, unsigned size);
1203 +void parse_hard_settings(unsigned *ptr, unsigned size);
1204 +
1205 +void __init prom_setup_cmdline(void);
1206 +
1207 +void __init prom_init(void)
1208 +{
1209 + DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
1210 + phys_t memsize = 0-ddr->ddrmask;
1211 +
1212 + /* this should be the very first message, even before serial is properly initialized */
1213 + prom_setup_cmdline();
1214 + setup_serial_port();
1215 +
1216 + mips_machgroup = MACH_GROUP_MIKROTIK;
1217 + soft_reboot = read_c0_status() & SR_NMI;
1218 + pm_power_off = NULL;
1219 +
1220 + /*
1221 + * give all RAM to boot allocator,
1222 + * except for the first 0x400 and the last 0x200 bytes
1223 + */
1224 + add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
1225 +}
1226 +
1227 +void prom_free_prom_memory(void)
1228 +{
1229 + /* FIXME: STUB */
1230 +}
1231 +
1232 +void __init prom_setup_cmdline(void){
1233 + char cmd_line[CL_SIZE];
1234 + char *cp;
1235 + int prom_argc;
1236 + char **prom_argv, **prom_envp;
1237 + int i;
1238 +
1239 + prom_argc = fw_arg0;
1240 + prom_argv = (char **) fw_arg1;
1241 + prom_envp = (char **) fw_arg2;
1242 +
1243 + cp=cmd_line;
1244 + /* Note: it is common that parameters start at argv[1] and not argv[0],
1245 + however, our elf loader starts at [0] */
1246 + for(i=0;i<prom_argc;i++){
1247 + if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) {
1248 + idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10);
1249 + continue;
1250 + }
1251 +#ifdef IGNORE_CMDLINE_MEM
1252 + /* parses out the "mem=xx" arg */
1253 + if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) {
1254 + continue;
1255 + }
1256 +#endif
1257 + if (i>0) *(cp++) = ' ';
1258 + if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
1259 + board_type = simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10);
1260 + }
1261 + if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {
1262 + gpio_bootup_state = simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10);
1263 + }
1264 + strcpy(cp,prom_argv[i]);
1265 + cp+=strlen(prom_argv[i]);
1266 + }
1267 +
1268 + i=strlen(arcs_cmdline);
1269 + if (i>0){
1270 + *(cp++) = ' ';
1271 + strcpy(cp,arcs_cmdline);
1272 + cp+=strlen(arcs_cmdline);
1273 + }
1274 + if (gpio_bootup_state&0x02)
1275 + strcpy(cp,GPIO_INIT_NOBUTTON);
1276 + else
1277 + strcpy(cp,GPIO_INIT_BUTTON);
1278 + cmd_line[CL_SIZE-1] = '\0';
1279 +
1280 + strcpy(arcs_cmdline,cmd_line);
1281 +}
1282 +
1283 diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
1284 --- linux.old/arch/mips/rb500/serial.c 1970-01-01 01:00:00.000000000 +0100
1285 +++ linux.dev/arch/mips/rb500/serial.c 2006-12-14 04:09:50.000000000 +0100
1286 @@ -0,0 +1,77 @@
1287 +/**************************************************************************
1288 + *
1289 + * BRIEF MODULE DESCRIPTION
1290 + * Serial port initialisation.
1291 + *
1292 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1293 + *
1294 + * This program is free software; you can redistribute it and/or modify it
1295 + * under the terms of the GNU General Public License as published by the
1296 + * Free Software Foundation; either version 2 of the License, or (at your
1297 + * option) any later version.
1298 + *
1299 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1300 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1301 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1302 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1303 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1304 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1305 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1306 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1307 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1308 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1309 + *
1310 + * You should have received a copy of the GNU General Public License along
1311 + * with this program; if not, write to the Free Software Foundation, Inc.,
1312 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1313 + *
1314 + *
1315 + **************************************************************************
1316 + * May 2004 rkt, neb
1317 + *
1318 + * Initial Release
1319 + *
1320 + *
1321 + *
1322 + **************************************************************************
1323 + */
1324 +
1325 +
1326 +#include <linux/autoconf.h>
1327 +#include <linux/init.h>
1328 +#include <linux/sched.h>
1329 +#include <linux/pci.h>
1330 +#include <linux/interrupt.h>
1331 +#include <linux/tty.h>
1332 +#include <linux/serial.h>
1333 +#include <linux/serial_core.h>
1334 +
1335 +#include <asm/time.h>
1336 +#include <asm/cpu.h>
1337 +#include <asm/bootinfo.h>
1338 +#include <asm/irq.h>
1339 +#include <asm/serial.h>
1340 +#include <asm/rc32434/rc32434.h>
1341 +
1342 +extern unsigned int idt_cpu_freq;
1343 +
1344 +static struct uart_port serial_req = {
1345 + .type = PORT_16550A,
1346 + .line = 0,
1347 + .irq = RC32434_UART0_IRQ,
1348 + .flags = STD_COM_FLAGS,
1349 + .iotype = UPIO_MEM,
1350 + .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
1351 +// .fifosize = 14
1352 + .regshift = 2
1353 +};
1354 +
1355 +int __init setup_serial_port(void)
1356 +{
1357 + serial_req.uartclk = idt_cpu_freq;
1358 +
1359 + if (early_serial_setup(&serial_req))
1360 + return -ENODEV;
1361 +
1362 + return(0);
1363 +}
1364 diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
1365 --- linux.old/arch/mips/rb500/setup.c 1970-01-01 01:00:00.000000000 +0100
1366 +++ linux.dev/arch/mips/rb500/setup.c 2006-12-14 04:51:12.000000000 +0100
1367 @@ -0,0 +1,81 @@
1368 +/*
1369 + * setup.c - boot time setup code
1370 + */
1371 +
1372 +#include <linux/init.h>
1373 +#include <linux/mm.h>
1374 +#include <linux/sched.h>
1375 +#include <linux/irq.h>
1376 +#include <linux/ioport.h>
1377 +#include <linux/pm.h>
1378 +#include <asm/bootinfo.h>
1379 +#include <asm/mipsregs.h>
1380 +#include <asm/pgtable.h>
1381 +#include <asm/reboot.h>
1382 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
1383 +#include <asm/time.h>
1384 +#include <asm/io.h>
1385 +#include <asm/rc32434/rc32434.h>
1386 +#include <asm/rc32434/pci.h>
1387 +
1388 +#ifdef CONFIG_PCI
1389 +extern void *rc32434_time_init(void);
1390 +extern int __init rc32434_pcibridge_init(void);
1391 +#endif
1392 +
1393 +#define epldMask ((volatile unsigned char *)0xB900000d)
1394 +
1395 +static void rb_machine_restart(char *command)
1396 +{
1397 + /* just jump to the reset vector */
1398 + * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
1399 + ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
1400 +}
1401 +
1402 +static void rb_machine_halt(void)
1403 +{
1404 + for(;;) continue;
1405 +}
1406 +
1407 +#ifdef CONFIG_CPU_HAS_WB
1408 +void (*__wbflush) (void);
1409 +
1410 +static void rb_write_buffer_flush(void)
1411 +{
1412 + __asm__ __volatile__
1413 + ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
1414 +}
1415 +#endif
1416 +
1417 +void __init plat_mem_setup(void)
1418 +{
1419 + unsigned int pciCntlVal;
1420 +
1421 + board_time_init = rc32434_time_init;
1422 +
1423 +#ifdef CONFIG_CPU_HAS_WB
1424 + __wbflush = rb_write_buffer_flush;
1425 +#endif
1426 + _machine_restart = rb_machine_restart;
1427 + _machine_halt = rb_machine_halt;
1428 + /*_machine_power_off = rb_machine_power_halt;*/
1429 + pm_power_off = rb_machine_halt;
1430 +
1431 + set_io_port_base(KSEG1);
1432 +
1433 + pciCntlVal=rc32434_pci->pcic;
1434 + pciCntlVal &= 0xFFFFFF7;
1435 + rc32434_pci->pcic = pciCntlVal;
1436 +
1437 +#ifdef CONFIG_PCI
1438 + /* Enable PCI interrupts in EPLD Mask register */
1439 + *epldMask = 0x0;
1440 + *(epldMask + 1) = 0x0;
1441 +#endif
1442 + write_c0_wired(0);
1443 +}
1444 +
1445 +const char *get_system_type(void)
1446 +{
1447 + return "MIPS RB500";
1448 +}
1449 diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
1450 --- linux.old/arch/mips/rb500/time.c 1970-01-01 01:00:00.000000000 +0100
1451 +++ linux.dev/arch/mips/rb500/time.c 2006-12-14 04:48:33.000000000 +0100
1452 @@ -0,0 +1,93 @@
1453 +/*
1454 +****************************************************************************
1455 +* Carsten Langgaard, carstenl@mips.com
1456 +* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1457 +*
1458 +***************************************************************************
1459 +*
1460 +* This program is free software; you can distribute it and/or modify it
1461 +* under the terms of the GNU General Public License (Version 2) as
1462 +* published by the Free Software Foundation.
1463 +*
1464 +* This program is distributed in the hope it will be useful, but WITHOUT
1465 +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1466 +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1467 +* for more details.
1468 +*
1469 +* You should have received a copy of the GNU General Public License along
1470 +* with this program; if not, write to the Free Software Foundation, Inc.,
1471 +* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1472 +*
1473 +****************************************************************************
1474 +*
1475 +* Setting up the clock on the MIPS boards.
1476 +*
1477 +****************************************************************************
1478 +* P. Sadik Oct 10, 2003
1479 +*
1480 +* Started change log.
1481 +* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
1482 +* Code cleanup
1483 +****************************************************************************
1484 +*/
1485 +
1486 +#include <linux/autoconf.h>
1487 +#include <linux/init.h>
1488 +#include <linux/kernel_stat.h>
1489 +#include <linux/sched.h>
1490 +#include <linux/spinlock.h>
1491 +#include <linux/mc146818rtc.h>
1492 +#include <linux/irq.h>
1493 +#include <linux/timex.h>
1494 +
1495 +#include <asm/mipsregs.h>
1496 +#include <asm/ptrace.h>
1497 +#include <asm/debug.h>
1498 +#include <asm/rc32434/rc32434.h>
1499 +
1500 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1501 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1502 +extern unsigned int mips_hpt_frequency;
1503 +extern unsigned int idt_cpu_freq;
1504 +
1505 +/*
1506 + * Figure out the r4k offset, the amount to increment the compare
1507 + * register for each time tick. There is no RTC available.
1508 + *
1509 + * The RC32434 counts at half the CPU *core* speed.
1510 + */
1511 +static unsigned long __init cal_r4koff(void)
1512 +{
1513 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1514 + return (mips_hpt_frequency / HZ);
1515 +}
1516 +
1517 +
1518 +void __init rc32434_time_init(void)
1519 +{
1520 + unsigned int est_freq, flags;
1521 +
1522 + local_irq_save(flags);
1523 +
1524 + printk("calculating r4koff... ");
1525 + r4k_offset = cal_r4koff();
1526 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1527 +
1528 + est_freq = 2*r4k_offset*HZ;
1529 + est_freq += 5000; /* round */
1530 + est_freq -= est_freq%10000;
1531 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1532 + (est_freq%1000000)*100/1000000);
1533 + local_irq_restore(flags);
1534 +}
1535 +
1536 +void __init plat_timer_setup(struct irqaction *irq)
1537 +{
1538 + /* we are using the cpu counter for timer interrupts */
1539 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1540 +
1541 + /* to generate the first timer interrupt */
1542 + r4k_cur = (read_c0_count() + r4k_offset);
1543 + write_c0_compare(r4k_cur);
1544 +}
1545 +
1546 diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
1547 --- linux.old/drivers/pci/Makefile 2006-11-29 22:57:37.000000000 +0100
1548 +++ linux.dev/drivers/pci/Makefile 2006-12-14 04:09:50.000000000 +0100
1549 @@ -16,6 +16,7 @@
1550
1551 # Build the PCI MSI interrupt support
1552 obj-$(CONFIG_PCI_MSI) += msi.o
1553 +obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
1554
1555 # Build the Hypertransport interrupt support
1556 obj-$(CONFIG_HT_IRQ) += htirq.o
1557 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1558 --- linux.old/include/asm-mips/bootinfo.h 2006-11-29 22:57:37.000000000 +0100
1559 +++ linux.dev/include/asm-mips/bootinfo.h 2006-12-14 04:09:50.000000000 +0100
1560 @@ -212,6 +212,8 @@
1561 #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
1562 #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
1563
1564 +#define MACH_GROUP_MIKROTIK 24 /* Mikrotik Boards */
1565 +
1566 #define CL_SIZE COMMAND_LINE_SIZE
1567
1568 const char *get_system_type(void);
1569 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
1570 --- linux.old/include/asm-mips/cpu.h 2006-11-29 22:57:37.000000000 +0100
1571 +++ linux.dev/include/asm-mips/cpu.h 2006-12-14 04:09:50.000000000 +0100
1572 @@ -200,7 +200,8 @@
1573 #define CPU_SB1A 62
1574 #define CPU_74K 63
1575 #define CPU_R14000 64
1576 -#define CPU_LAST 64
1577 +#define CPU_RC32300 65
1578 +#define CPU_LAST 65
1579
1580 /*
1581 * ISA Level encodings
1582 diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
1583 --- linux.old/include/asm-mips/rc32434/ddr.h 1970-01-01 01:00:00.000000000 +0100
1584 +++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-12-14 04:09:50.000000000 +0100
1585 @@ -0,0 +1,173 @@
1586 +#ifndef __IDT_DDR_H__
1587 +#define __IDT_DDR_H__
1588 +
1589 +/*******************************************************************************
1590 + *
1591 + * Copyright 2002 Integrated Device Technology, Inc.
1592 + * All rights reserved.
1593 + *
1594 + * DDR register definition.
1595 + *
1596 + * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1597 + *
1598 + * Author : ryan.holmQVist@idt.com
1599 + * Date : 20011005
1600 + * Update :
1601 + * $Log: ddr.h,v $
1602 + * Revision 1.2 2002/06/06 18:34:03 astichte
1603 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
1604 + *
1605 + * Revision 1.1 2002/05/29 17:33:21 sysarch
1606 + * jba File moved from vcode/include/idt/acacia
1607 + *
1608 + *
1609 + ******************************************************************************/
1610 +
1611 +enum
1612 +{
1613 + DDR0_PhysicalAddress = 0x18018000,
1614 + DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
1615 +
1616 + DDR0_VirtualAddress = 0xb8018000,
1617 + DDR_VirtualAddress = DDR0_VirtualAddress, // Default
1618 +} ;
1619 +
1620 +typedef struct DDR_s
1621 +{
1622 + u32 ddrbase ;
1623 + u32 ddrmask ;
1624 + u32 res1;
1625 + u32 res2;
1626 + u32 ddrc ;
1627 + u32 ddrabase ;
1628 + u32 ddramask ;
1629 + u32 ddramap ;
1630 + u32 ddrcust;
1631 + u32 ddrrdc;
1632 + u32 ddrspare;
1633 +} volatile *DDR_t ;
1634 +
1635 +enum
1636 +{
1637 + DDR0BASE_baseaddr_b = 16,
1638 + DDR0BASE_baseaddr_m = 0xffff0000,
1639 +
1640 + DDR0MASK_mask_b = 16,
1641 + DDR0MASK_mask_m = 0xffff0000,
1642 +
1643 + DDR1BASE_baseaddr_b = 16,
1644 + DDR1BASE_baseaddr_m = 0xffff0000,
1645 +
1646 + DDR1MASK_mask_b = 16,
1647 + DDR1MASK_mask_m = 0xffff0000,
1648 +
1649 + DDRC_ata_b = 5,
1650 + DDRC_ata_m = 0x000000E0,
1651 + DDRC_dbw_b = 8,
1652 + DDRC_dbw_m = 0x00000100,
1653 + DDRC_wr_b = 9,
1654 + DDRC_wr_m = 0x00000600,
1655 + DDRC_ps_b = 11,
1656 + DDRC_ps_m = 0x00001800,
1657 + DDRC_dtype_b = 13,
1658 + DDRC_dtype_m = 0x0000e000,
1659 + DDRC_rfc_b = 16,
1660 + DDRC_rfc_m = 0x000f0000,
1661 + DDRC_rp_b = 20,
1662 + DDRC_rp_m = 0x00300000,
1663 + DDRC_ap_b = 22,
1664 + DDRC_ap_m = 0x00400000,
1665 + DDRC_rcd_b = 23,
1666 + DDRC_rcd_m = 0x01800000,
1667 + DDRC_cl_b = 25,
1668 + DDRC_cl_m = 0x06000000,
1669 + DDRC_dbm_b = 27,
1670 + DDRC_dbm_m = 0x08000000,
1671 + DDRC_sds_b = 28,
1672 + DDRC_sds_m = 0x10000000,
1673 + DDRC_atp_b = 29,
1674 + DDRC_atp_m = 0x60000000,
1675 + DDRC_re_b = 31,
1676 + DDRC_re_m = 0x80000000,
1677 +
1678 + DDRRDC_ces_b = 0,
1679 + DDRRDC_ces_m = 0x00000001,
1680 + DDRRDC_ace_b = 1,
1681 + DDRRDC_ace_m = 0x00000002,
1682 +
1683 + DDRABASE_baseaddr_b = 16,
1684 + DDRABASE_baseaddr_m = 0xffff0000,
1685 +
1686 + DDRAMASK_mask_b = 16,
1687 + DDRAMASK_mask_m = 0xffff0000,
1688 +
1689 + DDRAMAP_map_b = 16,
1690 + DDRAMAP_map_m = 0xffff0000,
1691 +
1692 + DDRCUST_cs_b = 0,
1693 + DDRCUST_cs_m = 0x00000003,
1694 + DDRCUST_we_b = 2,
1695 + DDRCUST_we_m = 0x00000004,
1696 + DDRCUST_ras_b = 3,
1697 + DDRCUST_ras_m = 0x00000008,
1698 + DDRCUST_cas_b = 4,
1699 + DDRCUST_cas_m = 0x00000010,
1700 + DDRCUST_cke_b = 5,
1701 + DDRCUST_cke_m = 0x00000020,
1702 + DDRCUST_ba_b = 6,
1703 + DDRCUST_ba_m = 0x000000c0,
1704 +
1705 + RCOUNT_rcount_b = 0,
1706 + RCOUNT_rcount_m = 0x0000ffff,
1707 +
1708 + RCOMPARE_rcompare_b = 0,
1709 + RCOMPARE_rcompare_m = 0x0000ffff,
1710 +
1711 + RTC_ce_b = 0,
1712 + RTC_ce_m = 0x00000001,
1713 + RTC_to_b = 1,
1714 + RTC_to_m = 0x00000002,
1715 + RTC_rqe_b = 2,
1716 + RTC_rqe_m = 0x00000004,
1717 +
1718 + DDRDQSC_dm_b = 0,
1719 + DDRDQSC_dm_m = 0x00000003,
1720 + DDRDQSC_dqsbs_b = 2,
1721 + DDRDQSC_dqsbs_m = 0x000000fc,
1722 + DDRDQSC_db_b = 8,
1723 + DDRDQSC_db_m = 0x00000100,
1724 + DDRDQSC_dbsp_b = 9,
1725 + DDRDQSC_dbsp_m = 0x01fffe00,
1726 + DDRDQSC_bdp_b = 25,
1727 + DDRDQSC_bdp_m = 0x7e000000,
1728 +
1729 + DDRDLLC_eao_b = 0,
1730 + DDRDLLC_eao_m = 0x00000001,
1731 + DDRDLLC_eo_b = 1,
1732 + DDRDLLC_eo_m = 0x0000003e,
1733 + DDRDLLC_fs_b = 6,
1734 + DDRDLLC_fs_m = 0x000000c0,
1735 + DDRDLLC_as_b = 8,
1736 + DDRDLLC_as_m = 0x00000700,
1737 + DDRDLLC_sp_b = 11,
1738 + DDRDLLC_sp_m = 0x001ff800,
1739 +
1740 + DDRDLLFC_men_b = 0,
1741 + DDRDLLFC_men_m = 0x00000001,
1742 + DDRDLLFC_aen_b = 1,
1743 + DDRDLLFC_aen_m = 0x00000002,
1744 + DDRDLLFC_ff_b = 2,
1745 + DDRDLLFC_ff_m = 0x00000004,
1746 +
1747 + DDRDLLTA_addr_b = 2,
1748 + DDRDLLTA_addr_m = 0xfffffffc,
1749 +
1750 + DDRDLLED_dbe_b = 0,
1751 + DDRDLLED_dbe_m = 0x00000001,
1752 + DDRDLLED_dte_b = 1,
1753 + DDRDLLED_dte_m = 0x00000002,
1754 +
1755 +
1756 +} ;
1757 +
1758 +#endif // __IDT_DDR_H__
1759 diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h
1760 --- linux.old/include/asm-mips/rc32434/dev.h 1970-01-01 01:00:00.000000000 +0100
1761 +++ linux.dev/include/asm-mips/rc32434/dev.h 2006-12-14 04:09:50.000000000 +0100
1762 @@ -0,0 +1,132 @@
1763 +#ifndef __IDT_DEV_H__
1764 +#define __IDT_DEV_H__
1765 +
1766 +/*******************************************************************************
1767 + *
1768 + * Copyright 2002 Integrated Device Technology, Inc.
1769 + * All rights reserved.
1770 + *
1771 + * Device Controller register definition.
1772 + *
1773 + * File : $Id: dev.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1774 + *
1775 + * Author : John.Ahrens@idt.com
1776 + * Date : 200112013
1777 + * Update :
1778 + * $Log: dev.h,v $
1779 + * Revision 1.2 2002/06/06 18:34:03 astichte
1780 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
1781 + *
1782 + * Revision 1.1 2002/05/29 17:33:21 sysarch
1783 + * jba File moved from vcode/include/idt/acacia
1784 + *
1785 + *
1786 + ******************************************************************************/
1787 +
1788 +enum
1789 +{
1790 + DEV0_PhysicalAddress = 0x18010000,
1791 + DEV_PhysicalAddress = DEV0_PhysicalAddress, // Default
1792 +
1793 + DEV0_VirtualAddress = 0xb8010000,
1794 + DEV_VirtualAddress = DEV0_VirtualAddress, // Default
1795 +} ;
1796 +
1797 +typedef struct DEVICE_s
1798 +{
1799 + u32 devbase ; // Device Base
1800 + u32 devmask ; // Device Mask
1801 + u32 devc ; // Device Control
1802 + u32 devtc ; // Device Timing Control
1803 +} volatile *DEVICE_t ;
1804 +
1805 +enum
1806 +{
1807 + DEV_Count = 3,
1808 +} ;
1809 +
1810 +typedef struct DEV_s
1811 +{
1812 + struct DEVICE_s dev [DEV_Count] ;
1813 + u32 btcs ; // Bus timeout control / status
1814 + u32 btcompare ; // Compare
1815 + u32 btaddr ; // Timeout address.
1816 + u32 devdacs ; // Decoupled access control.
1817 + u32 devdaa ; // Decoupled access address.
1818 + u32 devdad ; // Decoupled access address.
1819 + u32 devspare ; // spare.
1820 +} volatile *DEV_t ;
1821 +
1822 +enum
1823 +{
1824 + DEVBASE_baseaddr_b = 16,
1825 + DEVBASE_baseaddr_m = 0xffff0000,
1826 + DEVMASK_mask_b = 16,
1827 + DEVMASK_mask_m = 0xffff0000,
1828 +
1829 + DEVC_ds_b = 0,
1830 + DEVC_ds_m = 0x00000003,
1831 + DEVC_ds_8_v = 0, // 8-bit device.
1832 + DEVC_ds_16_v = 1, // reserved
1833 + DEVC_ds_res_v = 2, // reserved.
1834 + DEVC_ds_res2_v = 3, // reserved.
1835 + DEVC_be_b = 2,
1836 + DEVC_be_m = 0x00000004,
1837 + DEVC_wp_b = 3,
1838 + DEVC_wp_m = 0x00000008,
1839 + DEVC_csd_b = 4,
1840 + DEVC_csd_m = 0x000000f0,
1841 + DEVC_oed_b = 8,
1842 + DEVC_oed_m = 0x00000f00,
1843 + DEVC_bwd_b = 12,
1844 + DEVC_bwd_m = 0x0000f000,
1845 + DEVC_rws_b = 16,
1846 + DEVC_rws_m = 0x003f0000,
1847 + DEVC_wws_b = 22,
1848 + DEVC_wws_m = 0x0fc00000,
1849 + DEVC_bre_b = 28,
1850 + DEVC_bre_m = 0x10000000,
1851 + DEVC_bwe_b = 29,
1852 + DEVC_bwe_m = 0x20000000,
1853 + DEVC_wam_b = 30,
1854 + DEVC_wam_m = 0x40000000,
1855 +
1856 + DEVTC_prd_b = 0,
1857 + DEVTC_prd_m = 0x0000000f,
1858 + DEVTC_pwd_b = 4,
1859 + DEVTC_pwd_m = 0x000000f0,
1860 + DEVTC_wdh_b = 8,
1861 + DEVTC_wdh_m = 0x00000700,
1862 + DEVTC_csh_b = 11,
1863 + DEVTC_csh_m = 0x00001800,
1864 +
1865 + BTCS_tt_b = 0,
1866 + BTCS_tt_m = 0x00000001,
1867 + BTCS_tt_write = 0,
1868 + BTCS_tt_read = 1,
1869 + BTCS_bto_b = 1, // In btcs
1870 + BTCS_bto_m = 0x00000002, // In btcs
1871 + BTCS_bte_b = 2, // In btcs
1872 + BTCS_bte_m = 0x00000004, // In btcs
1873 +
1874 + BTCOMPARE_compare_b = 0, // In btcompare
1875 + BTCOMPARE_compare_m = 0x0000ffff, // In btcompare
1876 +
1877 + DEVDACS_op_b = 0, // In devdacs
1878 + DEVDACS_op_m = 0x00000001, // In devdacs
1879 + DEVDACS_op_write_v = 0,
1880 + DEVDACS_op_read_v = 1,
1881 + DEVDACS_size_b = 1, // In devdacs
1882 + DEVDACS_size_m = 0x00000006, // In devdacs
1883 + DEVDACS_size_byte_v = 0,
1884 + DEVDACS_size_halfword = 1,
1885 + DEVDACS_size_triplebyte = 2,
1886 + DEVDACS_size_word = 3,
1887 + DEVDACS_err_b = 3, // In devdacs
1888 + DEVDACS_err_m = 0x00000008, // In devdacs
1889 + DEVDACS_f_b = 4, // In devdacs
1890 + DEVDACS_f_m = 0x00000010, // In devdacs
1891 +} ;
1892 +
1893 +#endif //__IDT_DEV_H__
1894 +
1895 diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
1896 --- linux.old/include/asm-mips/rc32434/dma.h 1970-01-01 01:00:00.000000000 +0100
1897 +++ linux.dev/include/asm-mips/rc32434/dma.h 2006-12-14 04:09:50.000000000 +0100
1898 @@ -0,0 +1,201 @@
1899 +#ifndef __IDT_DMA_H__
1900 +#define __IDT_DMA_H__
1901 +
1902 +/*******************************************************************************
1903 + *
1904 + * Copyright 2002 Integrated Device Technology, Inc.
1905 + * All rights reserved.
1906 + *
1907 + * DMA register definition.
1908 + *
1909 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
1910 + *
1911 + * Author : ryan.holmQVist@idt.com
1912 + * Date : 20011005
1913 + * Update :
1914 + * $Log: dma.h,v $
1915 + * Revision 1.3 2002/06/06 18:34:03 astichte
1916 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
1917 + *
1918 + * Revision 1.2 2002/06/05 18:30:46 astichte
1919 + * Removed IDTField
1920 + *
1921 + * Revision 1.1 2002/05/29 17:33:21 sysarch
1922 + * jba File moved from vcode/include/idt/acacia
1923 + *
1924 + *
1925 + ******************************************************************************/
1926 +
1927 +enum
1928 +{
1929 + DMA0_PhysicalAddress = 0x18040000,
1930 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
1931 +
1932 + DMA0_VirtualAddress = 0xb8040000,
1933 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
1934 +} ;
1935 +
1936 +/*
1937 + * DMA descriptor (in physical memory).
1938 + */
1939 +
1940 +typedef struct DMAD_s
1941 +{
1942 + u32 control ; // Control. use DMAD_*
1943 + u32 ca ; // Current Address.
1944 + u32 devcs ; // Device control and status.
1945 + u32 link ; // Next descriptor in chain.
1946 +} volatile *DMAD_t ;
1947 +
1948 +enum
1949 +{
1950 + DMAD_size = sizeof (struct DMAD_s),
1951 + DMAD_count_b = 0, // in DMAD_t -> control
1952 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
1953 + DMAD_ds_b = 20, // in DMAD_t -> control
1954 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
1955 + DMAD_ds_ethRcv_v = 0,
1956 + DMAD_ds_ethXmt_v = 0,
1957 + DMAD_ds_memToFifo_v = 0,
1958 + DMAD_ds_fifoToMem_v = 0,
1959 + DMAD_ds_pciToMem_v = 0,
1960 + DMAD_ds_memToPci_v = 0,
1961 +
1962 + DMAD_devcmd_b = 22, // in DMAD_t -> control
1963 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
1964 + DMAD_devcmd_byte_v = 0, //memory-to-memory
1965 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
1966 + DMAD_devcmd_word_v = 2, //memory-to-memory
1967 + DMAD_devcmd_2words_v = 3, //memory-to-memory
1968 + DMAD_devcmd_4words_v = 4, //memory-to-memory
1969 + DMAD_devcmd_6words_v = 5, //memory-to-memory
1970 + DMAD_devcmd_8words_v = 6, //memory-to-memory
1971 + DMAD_devcmd_16words_v = 7, //memory-to-memory
1972 + DMAD_cof_b = 25, // chain on finished
1973 + DMAD_cof_m = 0x02000000, //
1974 + DMAD_cod_b = 26, // chain on done
1975 + DMAD_cod_m = 0x04000000, //
1976 + DMAD_iof_b = 27, // interrupt on finished
1977 + DMAD_iof_m = 0x08000000, //
1978 + DMAD_iod_b = 28, // interrupt on done
1979 + DMAD_iod_m = 0x10000000, //
1980 + DMAD_t_b = 29, // terminated
1981 + DMAD_t_m = 0x20000000, //
1982 + DMAD_d_b = 30, // done
1983 + DMAD_d_m = 0x40000000, //
1984 + DMAD_f_b = 31, // finished
1985 + DMAD_f_m = 0x80000000, //
1986 +} ;
1987 +
1988 +/*
1989 + * DMA register (within Internal Register Map).
1990 + */
1991 +
1992 +struct DMA_Chan_s
1993 +{
1994 + u32 dmac ; // Control.
1995 + u32 dmas ; // Status.
1996 + u32 dmasm ; // Mask.
1997 + u32 dmadptr ; // Descriptor pointer.
1998 + u32 dmandptr ; // Next descriptor pointer.
1999 +};
2000 +
2001 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
2002 +
2003 +//DMA_Channels use DMACH_count instead
2004 +
2005 +enum
2006 +{
2007 + DMAC_run_b = 0, //
2008 + DMAC_run_m = 0x00000001, //
2009 + DMAC_dm_b = 1, // done mask
2010 + DMAC_dm_m = 0x00000002, //
2011 + DMAC_mode_b = 2, //
2012 + DMAC_mode_m = 0x0000000c, //
2013 + DMAC_mode_auto_v = 0,
2014 + DMAC_mode_burst_v = 1,
2015 + DMAC_mode_transfer_v = 2, //usually used
2016 + DMAC_mode_reserved_v = 3,
2017 + DMAC_a_b = 4, //
2018 + DMAC_a_m = 0x00000010, //
2019 +
2020 + DMAS_f_b = 0, // finished (sticky)
2021 + DMAS_f_m = 0x00000001, //
2022 + DMAS_d_b = 1, // done (sticky)
2023 + DMAS_d_m = 0x00000002, //
2024 + DMAS_c_b = 2, // chain (sticky)
2025 + DMAS_c_m = 0x00000004, //
2026 + DMAS_e_b = 3, // error (sticky)
2027 + DMAS_e_m = 0x00000008, //
2028 + DMAS_h_b = 4, // halt (sticky)
2029 + DMAS_h_m = 0x00000010, //
2030 +
2031 + DMASM_f_b = 0, // finished (1=mask)
2032 + DMASM_f_m = 0x00000001, //
2033 + DMASM_d_b = 1, // done (1=mask)
2034 + DMASM_d_m = 0x00000002, //
2035 + DMASM_c_b = 2, // chain (1=mask)
2036 + DMASM_c_m = 0x00000004, //
2037 + DMASM_e_b = 3, // error (1=mask)
2038 + DMASM_e_m = 0x00000008, //
2039 + DMASM_h_b = 4, // halt (1=mask)
2040 + DMASM_h_m = 0x00000010, //
2041 +} ;
2042 +
2043 +/*
2044 + * DMA channel definitions
2045 + */
2046 +
2047 +enum
2048 +{
2049 + DMACH_ethRcv = 0,
2050 + DMACH_ethXmt = 1,
2051 + DMACH_memToFifo = 2,
2052 + DMACH_fifoToMem = 3,
2053 + DMACH_pciToMem = 4,
2054 + DMACH_memToPci = 5,
2055 +
2056 + DMACH_count //must be last
2057 +};
2058 +
2059 +
2060 +typedef struct DMAC_s
2061 +{
2062 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
2063 +} volatile *DMA_t ;
2064 +
2065 +
2066 +/*
2067 + * External DMA parameters
2068 +*/
2069 +#if 0
2070 +enum
2071 +{
2072 + DMADEVCMD_ts_b = 0, // ts field in devcmd
2073 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
2074 + DMADEVCMD_ts_byte_v = 0,
2075 + DMADEVCMD_ts_halfword_v = 1,
2076 + DMADEVCMD_ts_word_v = 2,
2077 + DMADEVCMD_ts_2word_v = 3,
2078 + DMADEVCMD_ts_4word_v = 4,
2079 + DMADEVCMD_ts_6word_v = 5,
2080 + DMADEVCMD_ts_8word_v = 6,
2081 + DMADEVCMD_ts_16word_v = 7
2082 +};
2083 +#endif
2084 +
2085 +#if 1 // aws - Compatibility.
2086 +# define EXTDMA_ts_b DMADEVCMD_ts_b
2087 +# define EXTDMA_ts_m DMADEVCMD_ts_m
2088 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
2089 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
2090 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
2091 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
2092 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
2093 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
2094 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
2095 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
2096 +#endif // aws - Compatibility.
2097 +
2098 +#endif // __IDT_DMA_H__
2099 +
2100 diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
2101 --- linux.old/include/asm-mips/rc32434/dma_v.h 1970-01-01 01:00:00.000000000 +0100
2102 +++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-12-14 04:09:50.000000000 +0100
2103 @@ -0,0 +1,72 @@
2104 +#ifndef __IDT_DMA_V_H__
2105 +#define __IDT_DMA_V_H__
2106 +
2107 +/*******************************************************************************
2108 + *
2109 + * Copyright 2002 Integrated Device Technology, Inc.
2110 + * All rights reserved.
2111 + *
2112 + * DMA register definition.
2113 + *
2114 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2115 + *
2116 + * Author : ryan.holmQVist@idt.com
2117 + * Date : 20011005
2118 + * Update :
2119 + * $Log: dma.h,v $
2120 + * Revision 1.3 2002/06/06 18:34:03 astichte
2121 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2122 + *
2123 + * Revision 1.2 2002/06/05 18:30:46 astichte
2124 + * Removed IDTField
2125 + *
2126 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2127 + * jba File moved from vcode/include/idt/acacia
2128 + *
2129 + *
2130 + ******************************************************************************/
2131 +#include <asm/rc32434/dma.h>
2132 +#include <asm/rc32434/rc32434.h>
2133 +#define DMA_CHAN_OFFSET 0x14
2134 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
2135 +#define DMA_COUNT(count) \
2136 + ((count) & DMAD_count_m)
2137 +
2138 +#define DMA_HALT_TIMEOUT 500
2139 +
2140 +
2141 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
2142 +{
2143 + int timeout=1;
2144 + if (local_readl(&ch->dmac) & DMAC_run_m) {
2145 + local_writel(0, &ch->dmac);
2146 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
2147 + if (local_readl(&ch->dmas) & DMAS_h_m) {
2148 + local_writel(0, &ch->dmas);
2149 + break;
2150 + }
2151 + }
2152 + }
2153 +
2154 + return timeout ? 0 : 1;
2155 +}
2156 +
2157 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
2158 +{
2159 + local_writel(0, &ch->dmandptr);
2160 + local_writel(dma_addr, &ch->dmadptr);
2161 +}
2162 +
2163 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
2164 +{
2165 + local_writel(dma_addr, &ch->dmandptr);
2166 +}
2167 +
2168 +#endif // __IDT_DMA_V_H__
2169 +
2170 +
2171 +
2172 +
2173 +
2174 +
2175 +
2176 diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
2177 --- linux.old/include/asm-mips/rc32434/eth.h 1970-01-01 01:00:00.000000000 +0100
2178 +++ linux.dev/include/asm-mips/rc32434/eth.h 2006-12-14 04:09:50.000000000 +0100
2179 @@ -0,0 +1,320 @@
2180 +#ifndef __IDT_ETH_H__
2181 +#define __IDT_ETH_H__
2182 +
2183 +/*******************************************************************************
2184 + *
2185 + * Copyright 2002 Integrated Device Technology, Inc.
2186 + * All rights reserved.
2187 + *
2188 + * Ethernet register definition.
2189 + *
2190 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2191 + *
2192 + * Author : Allen.Stichter@idt.com
2193 + * Date : 20020605
2194 + * Update :
2195 + * $Log: eth.h,v $
2196 + * Revision 1.3 2002/06/06 18:34:04 astichte
2197 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2198 + *
2199 + * Revision 1.2 2002/06/05 18:19:46 astichte
2200 + * Added
2201 + *
2202 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2203 + * jba File moved from vcode/include/idt/acacia
2204 + *
2205 + ******************************************************************************/
2206 +
2207 +enum
2208 +{
2209 + ETH0_PhysicalAddress = 0x18060000,
2210 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
2211 +
2212 + ETH0_VirtualAddress = 0xb8060000,
2213 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
2214 +} ;
2215 +
2216 +typedef struct
2217 +{
2218 + u32 ethintfc ;
2219 + u32 ethfifott ;
2220 + u32 etharc ;
2221 + u32 ethhash0 ;
2222 + u32 ethhash1 ;
2223 + u32 ethu0 [4] ; // Reserved.
2224 + u32 ethpfs ;
2225 + u32 ethmcp ;
2226 + u32 eth_u1 [10] ; // Reserved.
2227 + u32 ethspare ;
2228 + u32 eth_u2 [42] ; // Reserved.
2229 + u32 ethsal0 ;
2230 + u32 ethsah0 ;
2231 + u32 ethsal1 ;
2232 + u32 ethsah1 ;
2233 + u32 ethsal2 ;
2234 + u32 ethsah2 ;
2235 + u32 ethsal3 ;
2236 + u32 ethsah3 ;
2237 + u32 ethrbc ;
2238 + u32 ethrpc ;
2239 + u32 ethrupc ;
2240 + u32 ethrfc ;
2241 + u32 ethtbc ;
2242 + u32 ethgpf ;
2243 + u32 eth_u9 [50] ; // Reserved.
2244 + u32 ethmac1 ;
2245 + u32 ethmac2 ;
2246 + u32 ethipgt ;
2247 + u32 ethipgr ;
2248 + u32 ethclrt ;
2249 + u32 ethmaxf ;
2250 + u32 eth_u10 ; // Reserved.
2251 + u32 ethmtest ;
2252 + u32 miimcfg ;
2253 + u32 miimcmd ;
2254 + u32 miimaddr ;
2255 + u32 miimwtd ;
2256 + u32 miimrdd ;
2257 + u32 miimind ;
2258 + u32 eth_u11 ; // Reserved.
2259 + u32 eth_u12 ; // Reserved.
2260 + u32 ethcfsa0 ;
2261 + u32 ethcfsa1 ;
2262 + u32 ethcfsa2 ;
2263 +} volatile *ETH_t;
2264 +
2265 +enum
2266 +{
2267 + ETHINTFC_en_b = 0,
2268 + ETHINTFC_en_m = 0x00000001,
2269 + ETHINTFC_its_b = 1,
2270 + ETHINTFC_its_m = 0x00000002,
2271 + ETHINTFC_rip_b = 2,
2272 + ETHINTFC_rip_m = 0x00000004,
2273 + ETHINTFC_jam_b = 3,
2274 + ETHINTFC_jam_m = 0x00000008,
2275 + ETHINTFC_ovr_b = 4,
2276 + ETHINTFC_ovr_m = 0x00000010,
2277 + ETHINTFC_und_b = 5,
2278 + ETHINTFC_und_m = 0x00000020,
2279 + ETHINTFC_iom_b = 6,
2280 + ETHINTFC_iom_m = 0x000000c0,
2281 +
2282 + ETHFIFOTT_tth_b = 0,
2283 + ETHFIFOTT_tth_m = 0x0000007f,
2284 +
2285 + ETHARC_pro_b = 0,
2286 + ETHARC_pro_m = 0x00000001,
2287 + ETHARC_am_b = 1,
2288 + ETHARC_am_m = 0x00000002,
2289 + ETHARC_afm_b = 2,
2290 + ETHARC_afm_m = 0x00000004,
2291 + ETHARC_ab_b = 3,
2292 + ETHARC_ab_m = 0x00000008,
2293 +
2294 + ETHSAL_byte5_b = 0,
2295 + ETHSAL_byte5_m = 0x000000ff,
2296 + ETHSAL_byte4_b = 8,
2297 + ETHSAL_byte4_m = 0x0000ff00,
2298 + ETHSAL_byte3_b = 16,
2299 + ETHSAL_byte3_m = 0x00ff0000,
2300 + ETHSAL_byte2_b = 24,
2301 + ETHSAL_byte2_m = 0xff000000,
2302 +
2303 + ETHSAH_byte1_b = 0,
2304 + ETHSAH_byte1_m = 0x000000ff,
2305 + ETHSAH_byte0_b = 8,
2306 + ETHSAH_byte0_m = 0x0000ff00,
2307 +
2308 + ETHGPF_ptv_b = 0,
2309 + ETHGPF_ptv_m = 0x0000ffff,
2310 +
2311 + ETHPFS_pfd_b = 0,
2312 + ETHPFS_pfd_m = 0x00000001,
2313 +
2314 + ETHCFSA0_cfsa4_b = 0,
2315 + ETHCFSA0_cfsa4_m = 0x000000ff,
2316 + ETHCFSA0_cfsa5_b = 8,
2317 + ETHCFSA0_cfsa5_m = 0x0000ff00,
2318 +
2319 + ETHCFSA1_cfsa2_b = 0,
2320 + ETHCFSA1_cfsa2_m = 0x000000ff,
2321 + ETHCFSA1_cfsa3_b = 8,
2322 + ETHCFSA1_cfsa3_m = 0x0000ff00,
2323 +
2324 + ETHCFSA2_cfsa0_b = 0,
2325 + ETHCFSA2_cfsa0_m = 0x000000ff,
2326 + ETHCFSA2_cfsa1_b = 8,
2327 + ETHCFSA2_cfsa1_m = 0x0000ff00,
2328 +
2329 + ETHMAC1_re_b = 0,
2330 + ETHMAC1_re_m = 0x00000001,
2331 + ETHMAC1_paf_b = 1,
2332 + ETHMAC1_paf_m = 0x00000002,
2333 + ETHMAC1_rfc_b = 2,
2334 + ETHMAC1_rfc_m = 0x00000004,
2335 + ETHMAC1_tfc_b = 3,
2336 + ETHMAC1_tfc_m = 0x00000008,
2337 + ETHMAC1_lb_b = 4,
2338 + ETHMAC1_lb_m = 0x00000010,
2339 + ETHMAC1_mr_b = 31,
2340 + ETHMAC1_mr_m = 0x80000000,
2341 +
2342 + ETHMAC2_fd_b = 0,
2343 + ETHMAC2_fd_m = 0x00000001,
2344 + ETHMAC2_flc_b = 1,
2345 + ETHMAC2_flc_m = 0x00000002,
2346 + ETHMAC2_hfe_b = 2,
2347 + ETHMAC2_hfe_m = 0x00000004,
2348 + ETHMAC2_dc_b = 3,
2349 + ETHMAC2_dc_m = 0x00000008,
2350 + ETHMAC2_cen_b = 4,
2351 + ETHMAC2_cen_m = 0x00000010,
2352 + ETHMAC2_pe_b = 5,
2353 + ETHMAC2_pe_m = 0x00000020,
2354 + ETHMAC2_vpe_b = 6,
2355 + ETHMAC2_vpe_m = 0x00000040,
2356 + ETHMAC2_ape_b = 7,
2357 + ETHMAC2_ape_m = 0x00000080,
2358 + ETHMAC2_ppe_b = 8,
2359 + ETHMAC2_ppe_m = 0x00000100,
2360 + ETHMAC2_lpe_b = 9,
2361 + ETHMAC2_lpe_m = 0x00000200,
2362 + ETHMAC2_nb_b = 12,
2363 + ETHMAC2_nb_m = 0x00001000,
2364 + ETHMAC2_bp_b = 13,
2365 + ETHMAC2_bp_m = 0x00002000,
2366 + ETHMAC2_ed_b = 14,
2367 + ETHMAC2_ed_m = 0x00004000,
2368 +
2369 + ETHIPGT_ipgt_b = 0,
2370 + ETHIPGT_ipgt_m = 0x0000007f,
2371 +
2372 + ETHIPGR_ipgr2_b = 0,
2373 + ETHIPGR_ipgr2_m = 0x0000007f,
2374 + ETHIPGR_ipgr1_b = 8,
2375 + ETHIPGR_ipgr1_m = 0x00007f00,
2376 +
2377 + ETHCLRT_maxret_b = 0,
2378 + ETHCLRT_maxret_m = 0x0000000f,
2379 + ETHCLRT_colwin_b = 8,
2380 + ETHCLRT_colwin_m = 0x00003f00,
2381 +
2382 + ETHMAXF_maxf_b = 0,
2383 + ETHMAXF_maxf_m = 0x0000ffff,
2384 +
2385 + ETHMTEST_tb_b = 2,
2386 + ETHMTEST_tb_m = 0x00000004,
2387 +
2388 + ETHMCP_div_b = 0,
2389 + ETHMCP_div_m = 0x000000ff,
2390 +
2391 + MIIMCFG_rsv_b = 0,
2392 + MIIMCFG_rsv_m = 0x0000000c,
2393 +
2394 + MIIMCMD_rd_b = 0,
2395 + MIIMCMD_rd_m = 0x00000001,
2396 + MIIMCMD_scn_b = 1,
2397 + MIIMCMD_scn_m = 0x00000002,
2398 +
2399 + MIIMADDR_regaddr_b = 0,
2400 + MIIMADDR_regaddr_m = 0x0000001f,
2401 + MIIMADDR_phyaddr_b = 8,
2402 + MIIMADDR_phyaddr_m = 0x00001f00,
2403 +
2404 + MIIMWTD_wdata_b = 0,
2405 + MIIMWTD_wdata_m = 0x0000ffff,
2406 +
2407 + MIIMRDD_rdata_b = 0,
2408 + MIIMRDD_rdata_m = 0x0000ffff,
2409 +
2410 + MIIMIND_bsy_b = 0,
2411 + MIIMIND_bsy_m = 0x00000001,
2412 + MIIMIND_scn_b = 1,
2413 + MIIMIND_scn_m = 0x00000002,
2414 + MIIMIND_nv_b = 2,
2415 + MIIMIND_nv_m = 0x00000004,
2416 +
2417 +} ;
2418 +
2419 +/*
2420 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
2421 + */
2422 +enum
2423 +{
2424 + ETHRX_fd_b = 0,
2425 + ETHRX_fd_m = 0x00000001,
2426 + ETHRX_ld_b = 1,
2427 + ETHRX_ld_m = 0x00000002,
2428 + ETHRX_rok_b = 2,
2429 + ETHRX_rok_m = 0x00000004,
2430 + ETHRX_fm_b = 3,
2431 + ETHRX_fm_m = 0x00000008,
2432 + ETHRX_mp_b = 4,
2433 + ETHRX_mp_m = 0x00000010,
2434 + ETHRX_bp_b = 5,
2435 + ETHRX_bp_m = 0x00000020,
2436 + ETHRX_vlt_b = 6,
2437 + ETHRX_vlt_m = 0x00000040,
2438 + ETHRX_cf_b = 7,
2439 + ETHRX_cf_m = 0x00000080,
2440 + ETHRX_ovr_b = 8,
2441 + ETHRX_ovr_m = 0x00000100,
2442 + ETHRX_crc_b = 9,
2443 + ETHRX_crc_m = 0x00000200,
2444 + ETHRX_cv_b = 10,
2445 + ETHRX_cv_m = 0x00000400,
2446 + ETHRX_db_b = 11,
2447 + ETHRX_db_m = 0x00000800,
2448 + ETHRX_le_b = 12,
2449 + ETHRX_le_m = 0x00001000,
2450 + ETHRX_lor_b = 13,
2451 + ETHRX_lor_m = 0x00002000,
2452 + ETHRX_ces_b = 14,
2453 + ETHRX_ces_m = 0x00004000,
2454 + ETHRX_length_b = 16,
2455 + ETHRX_length_m = 0xffff0000,
2456 +
2457 + ETHTX_fd_b = 0,
2458 + ETHTX_fd_m = 0x00000001,
2459 + ETHTX_ld_b = 1,
2460 + ETHTX_ld_m = 0x00000002,
2461 + ETHTX_oen_b = 2,
2462 + ETHTX_oen_m = 0x00000004,
2463 + ETHTX_pen_b = 3,
2464 + ETHTX_pen_m = 0x00000008,
2465 + ETHTX_cen_b = 4,
2466 + ETHTX_cen_m = 0x00000010,
2467 + ETHTX_hen_b = 5,
2468 + ETHTX_hen_m = 0x00000020,
2469 + ETHTX_tok_b = 6,
2470 + ETHTX_tok_m = 0x00000040,
2471 + ETHTX_mp_b = 7,
2472 + ETHTX_mp_m = 0x00000080,
2473 + ETHTX_bp_b = 8,
2474 + ETHTX_bp_m = 0x00000100,
2475 + ETHTX_und_b = 9,
2476 + ETHTX_und_m = 0x00000200,
2477 + ETHTX_of_b = 10,
2478 + ETHTX_of_m = 0x00000400,
2479 + ETHTX_ed_b = 11,
2480 + ETHTX_ed_m = 0x00000800,
2481 + ETHTX_ec_b = 12,
2482 + ETHTX_ec_m = 0x00001000,
2483 + ETHTX_lc_b = 13,
2484 + ETHTX_lc_m = 0x00002000,
2485 + ETHTX_td_b = 14,
2486 + ETHTX_td_m = 0x00004000,
2487 + ETHTX_crc_b = 15,
2488 + ETHTX_crc_m = 0x00008000,
2489 + ETHTX_le_b = 16,
2490 + ETHTX_le_m = 0x00010000,
2491 + ETHTX_cc_b = 17,
2492 + ETHTX_cc_m = 0x001E0000,
2493 +} ;
2494 +
2495 +#endif // __IDT_ETH_H__
2496 +
2497 +
2498 +
2499 +
2500 diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
2501 --- linux.old/include/asm-mips/rc32434/eth_v.h 1970-01-01 01:00:00.000000000 +0100
2502 +++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-12-14 04:09:50.000000000 +0100
2503 @@ -0,0 +1,63 @@
2504 +#ifndef __IDT_ETH_V_H__
2505 +#define __IDT_ETH_V_H__
2506 +
2507 +/*******************************************************************************
2508 + *
2509 + * Copyright 2002 Integrated Device Technology, Inc.
2510 + * All rights reserved.
2511 + *
2512 + * Ethernet register definition.
2513 + *
2514 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2515 + *
2516 + * Author : Allen.Stichter@idt.com
2517 + * Date : 20020605
2518 + * Update :
2519 + * $Log: eth.h,v $
2520 + * Revision 1.3 2002/06/06 18:34:04 astichte
2521 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2522 + *
2523 + * Revision 1.2 2002/06/05 18:19:46 astichte
2524 + * Added
2525 + *
2526 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2527 + * jba File moved from vcode/include/idt/acacia
2528 + *
2529 + ******************************************************************************/
2530 +
2531 +#include <asm/rc32434/eth.h>
2532 +
2533 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
2534 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
2535 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
2536 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
2537 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
2538 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
2539 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
2540 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
2541 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
2542 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
2543 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
2544 +
2545 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
2546 +
2547 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
2548 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
2549 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
2550 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
2551 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
2552 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
2553 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
2554 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
2555 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
2556 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
2557 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
2558 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
2559 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
2560 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
2561 +#endif // __IDT_ETH_V_H__
2562 +
2563 +
2564 +
2565 +
2566 +
2567 diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
2568 --- linux.old/include/asm-mips/rc32434/gpio.h 1970-01-01 01:00:00.000000000 +0100
2569 +++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-12-14 04:09:50.000000000 +0100
2570 @@ -0,0 +1,181 @@
2571 +#ifndef __IDT_GPIO_H__
2572 +#define __IDT_GPIO_H__
2573 +
2574 +/*******************************************************************************
2575 + *
2576 + * Copyright 2002 Integrated Device Technology, Inc.
2577 + * All rights reserved.
2578 + *
2579 + * GPIO register definition.
2580 + *
2581 + * File : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
2582 + *
2583 + * Author : ryan.holmQVist@idt.com
2584 + * Date : 20011005
2585 + * Update :
2586 + * $Log: gpio.h,v $
2587 + * Revision 1.2 2002/06/06 18:34:04 astichte
2588 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2589 + *
2590 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2591 + * jba File moved from vcode/include/idt/acacia
2592 + *
2593 + *
2594 + ******************************************************************************/
2595 +
2596 +enum
2597 +{
2598 + GPIO0_PhysicalAddress = 0x18050000,
2599 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
2600 +
2601 + GPIO0_VirtualAddress = 0xb8050000,
2602 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
2603 +} ;
2604 +
2605 +typedef struct
2606 +{
2607 + u32 gpiofunc; /* GPIO Function Register
2608 + * gpiofunc[x]==0 bit = gpio
2609 + * func[x]==1 bit = altfunc
2610 + */
2611 + u32 gpiocfg; /* GPIO Configuration Register
2612 + * gpiocfg[x]==0 bit = input
2613 + * gpiocfg[x]==1 bit = output
2614 + */
2615 + u32 gpiod; /* GPIO Data Register
2616 + * gpiod[x] read/write gpio pinX status
2617 + */
2618 + u32 gpioilevel; /* GPIO Interrupt Status Register
2619 + * interrupt level (see gpioistat)
2620 + */
2621 + u32 gpioistat; /* Gpio Interrupt Status Register
2622 + * istat[x] = (gpiod[x] == level[x])
2623 + * cleared in ISR (STICKY bits)
2624 + */
2625 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
2626 +} volatile * GPIO_t ;
2627 +
2628 +typedef enum
2629 +{
2630 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
2631 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
2632 + GPIO_input_v = 0, // gpiocfg use pin as input.
2633 + GPIO_output_v = 1, // gpiocfg use pin as output.
2634 + GPIO_pin0_b = 0,
2635 + GPIO_pin0_m = 0x00000001,
2636 + GPIO_pin1_b = 1,
2637 + GPIO_pin1_m = 0x00000002,
2638 + GPIO_pin2_b = 2,
2639 + GPIO_pin2_m = 0x00000004,
2640 + GPIO_pin3_b = 3,
2641 + GPIO_pin3_m = 0x00000008,
2642 + GPIO_pin4_b = 4,
2643 + GPIO_pin4_m = 0x00000010,
2644 + GPIO_pin5_b = 5,
2645 + GPIO_pin5_m = 0x00000020,
2646 + GPIO_pin6_b = 6,
2647 + GPIO_pin6_m = 0x00000040,
2648 + GPIO_pin7_b = 7,
2649 + GPIO_pin7_m = 0x00000080,
2650 + GPIO_pin8_b = 8,
2651 + GPIO_pin8_m = 0x00000100,
2652 + GPIO_pin9_b = 9,
2653 + GPIO_pin9_m = 0x00000200,
2654 + GPIO_pin10_b = 10,
2655 + GPIO_pin10_m = 0x00000400,
2656 + GPIO_pin11_b = 11,
2657 + GPIO_pin11_m = 0x00000800,
2658 + GPIO_pin12_b = 12,
2659 + GPIO_pin12_m = 0x00001000,
2660 + GPIO_pin13_b = 13,
2661 + GPIO_pin13_m = 0x00002000,
2662 + GPIO_pin14_b = 14,
2663 + GPIO_pin14_m = 0x00004000,
2664 + GPIO_pin15_b = 15,
2665 + GPIO_pin15_m = 0x00008000,
2666 + GPIO_pin16_b = 16,
2667 + GPIO_pin16_m = 0x00010000,
2668 + GPIO_pin17_b = 17,
2669 + GPIO_pin17_m = 0x00020000,
2670 + GPIO_pin18_b = 18,
2671 + GPIO_pin18_m = 0x00040000,
2672 + GPIO_pin19_b = 19,
2673 + GPIO_pin19_m = 0x00080000,
2674 + GPIO_pin20_b = 20,
2675 + GPIO_pin20_m = 0x00100000,
2676 + GPIO_pin21_b = 21,
2677 + GPIO_pin21_m = 0x00200000,
2678 + GPIO_pin22_b = 22,
2679 + GPIO_pin22_m = 0x00400000,
2680 + GPIO_pin23_b = 23,
2681 + GPIO_pin23_m = 0x00800000,
2682 + GPIO_pin24_b = 24,
2683 + GPIO_pin24_m = 0x01000000,
2684 + GPIO_pin25_b = 25,
2685 + GPIO_pin25_m = 0x02000000,
2686 + GPIO_pin26_b = 26,
2687 + GPIO_pin26_m = 0x04000000,
2688 + GPIO_pin27_b = 27,
2689 + GPIO_pin27_m = 0x08000000,
2690 + GPIO_pin28_b = 28,
2691 + GPIO_pin28_m = 0x10000000,
2692 + GPIO_pin29_b = 29,
2693 + GPIO_pin29_m = 0x20000000,
2694 + GPIO_pin30_b = 30,
2695 + GPIO_pin30_m = 0x40000000,
2696 + GPIO_pin31_b = 31,
2697 + GPIO_pin31_m = 0x80000000,
2698 +
2699 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
2700 +
2701 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
2702 + GPIO_u0sout_m = GPIO_pin0_m,
2703 + GPIO_u0sout_cfg_v = GPIO_output_v,
2704 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
2705 + GPIO_u0sinp_m = GPIO_pin1_m,
2706 + GPIO_u0sinp_cfg_v = GPIO_input_v,
2707 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
2708 + GPIO_u0rtsn_m = GPIO_pin2_m,
2709 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
2710 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
2711 + GPIO_u0ctsn_m = GPIO_pin3_m,
2712 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
2713 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
2714 + GPIO_maddr22_m = GPIO_pin4_m,
2715 + GPIO_maddr22_cfg_v = GPIO_output_v,
2716 +
2717 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
2718 + GPIO_maddr23_m = GPIO_pin5_m,
2719 + GPIO_maddr23_cfg_v = GPIO_output_v,
2720 +
2721 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
2722 + GPIO_maddr24_m = GPIO_pin6_m,
2723 + GPIO_maddr24_cfg_v = GPIO_output_v,
2724 +
2725 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
2726 + GPIO_maddr25_m = GPIO_pin7_m,
2727 + GPIO_maddr25_cfg_v = GPIO_output_v,
2728 +
2729 + GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25.
2730 + GPIO_cpu_m = GPIO_pin8_m,
2731 + GPIO_cpu_cfg_v = GPIO_output_v,
2732 + GPIO_afspare6_b = GPIO_pin9_b, // reserved.
2733 + GPIO_afspare6_m = GPIO_pin9_m,
2734 + GPIO_afspare6_cfg_v = GPIO_input_v,
2735 + GPIO_afspare4_b = GPIO_pin10_b, // reserved.
2736 + GPIO_afspare4_m = GPIO_pin10_m,
2737 + GPIO_afspare4_cfg_v = GPIO_input_v,
2738 + GPIO_afspare3_b = GPIO_pin11_b, // reserved.
2739 + GPIO_afspare3_m = GPIO_pin11_m,
2740 + GPIO_afspare3_cfg_v = GPIO_input_v,
2741 + GPIO_afspare2_b = GPIO_pin12_b, // reserved.
2742 + GPIO_afspare2_m = GPIO_pin12_m,
2743 + GPIO_afspare2_cfg_v = GPIO_input_v,
2744 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
2745 + GPIO_pcimuintn_m = GPIO_pin13_m,
2746 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
2747 +
2748 +} GPIO_DEFS_t;
2749 +
2750 +#endif // __IDT_GPIO_H__
2751 +
2752 diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
2753 --- linux.old/include/asm-mips/rc32434/irq.h 1970-01-01 01:00:00.000000000 +0100
2754 +++ linux.dev/include/asm-mips/rc32434/irq.h 2006-12-14 04:09:50.000000000 +0100
2755 @@ -0,0 +1,8 @@
2756 +#ifndef __ASM_MACH_MIPS_IRQ_H
2757 +#define __ASM_MACH_MIPS_IRQ_H
2758 +
2759 +#include <linux/autoconf.h>
2760 +
2761 +#define NR_IRQS 256
2762 +
2763 +#endif /* __ASM_MACH_MIPS_IRQ_H */
2764 diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
2765 --- linux.old/include/asm-mips/rc32434/pci.h 1970-01-01 01:00:00.000000000 +0100
2766 +++ linux.dev/include/asm-mips/rc32434/pci.h 2006-12-14 04:09:50.000000000 +0100
2767 @@ -0,0 +1,695 @@
2768 +/**************************************************************************
2769 + *
2770 + * BRIEF MODULE DESCRIPTION
2771 + * PCI register definitio
2772 + *
2773 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2774 + *
2775 + * This program is free software; you can redistribute it and/or modify it
2776 + * under the terms of the GNU General Public License as published by the
2777 + * Free Software Foundation; either version 2 of the License, or (at your
2778 + * option) any later version.
2779 + *
2780 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2781 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2782 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2783 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2784 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2785 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2786 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2787 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2788 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2789 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2790 + *
2791 + * You should have received a copy of the GNU General Public License along
2792 + * with this program; if not, write to the Free Software Foundation, Inc.,
2793 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2794 + *
2795 + *
2796 + **************************************************************************
2797 + * May 2004 rkt, neb.
2798 + *
2799 + * Initial Release
2800 + *
2801 + *
2802 + *
2803 + **************************************************************************
2804 + */
2805 +
2806 +#ifndef __IDT_PCI_H__
2807 +#define __IDT_PCI_H__
2808 +
2809 +enum
2810 +{
2811 + PCI0_PhysicalAddress = 0x18080000,
2812 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
2813 +
2814 + PCI0_VirtualAddress = 0xB8080000,
2815 + PCI_VirtualAddress = PCI0_VirtualAddress,
2816 +} ;
2817 +
2818 +enum
2819 +{
2820 + PCI_LbaCount = 4, // Local base addresses.
2821 +} ;
2822 +
2823 +typedef struct
2824 +{
2825 + u32 a ; // Address.
2826 + u32 c ; // Control.
2827 + u32 m ; // mapping.
2828 +} PCI_Map_s ;
2829 +
2830 +typedef struct
2831 +{
2832 + u32 pcic ;
2833 + u32 pcis ;
2834 + u32 pcism ;
2835 + u32 pcicfga ;
2836 + u32 pcicfgd ;
2837 + PCI_Map_s pcilba [PCI_LbaCount] ;
2838 + u32 pcidac ;
2839 + u32 pcidas ;
2840 + u32 pcidasm ;
2841 + u32 pcidad ;
2842 + u32 pcidma8c ;
2843 + u32 pcidma9c ;
2844 + u32 pcitc ;
2845 +} volatile *PCI_t ;
2846 +
2847 +// PCI messaging unit.
2848 +enum
2849 +{
2850 + PCIM_Count = 2,
2851 +} ;
2852 +typedef struct
2853 +{
2854 + u32 pciim [PCIM_Count] ;
2855 + u32 pciom [PCIM_Count] ;
2856 + u32 pciid ;
2857 + u32 pciiic ;
2858 + u32 pciiim ;
2859 + u32 pciiod ;
2860 + u32 pciioic ;
2861 + u32 pciioim ;
2862 +} volatile *PCIM_t ;
2863 +
2864 +/*******************************************************************************
2865 + *
2866 + * PCI Control Register
2867 + *
2868 + ******************************************************************************/
2869 +enum
2870 +{
2871 + PCIC_en_b = 0,
2872 + PCIC_en_m = 0x00000001,
2873 + PCIC_tnr_b = 1,
2874 + PCIC_tnr_m = 0x00000002,
2875 + PCIC_sce_b = 2,
2876 + PCIC_sce_m = 0x00000004,
2877 + PCIC_ien_b = 3,
2878 + PCIC_ien_m = 0x00000008,
2879 + PCIC_aaa_b = 4,
2880 + PCIC_aaa_m = 0x00000010,
2881 + PCIC_eap_b = 5,
2882 + PCIC_eap_m = 0x00000020,
2883 + PCIC_pcim_b = 6,
2884 + PCIC_pcim_m = 0x000001c0,
2885 + PCIC_pcim_disabled_v = 0,
2886 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
2887 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
2888 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
2889 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
2890 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
2891 + PCIC_pcim_reserved6_v = 6,
2892 + PCIC_pcim_reserved7_v = 7,
2893 + PCIC_igm_b = 9,
2894 + PCIC_igm_m = 0x00000200,
2895 +} ;
2896 +
2897 +/*******************************************************************************
2898 + *
2899 + * PCI Status Register
2900 + *
2901 + ******************************************************************************/
2902 +enum {
2903 + PCIS_eed_b = 0,
2904 + PCIS_eed_m = 0x00000001,
2905 + PCIS_wr_b = 1,
2906 + PCIS_wr_m = 0x00000002,
2907 + PCIS_nmi_b = 2,
2908 + PCIS_nmi_m = 0x00000004,
2909 + PCIS_ii_b = 3,
2910 + PCIS_ii_m = 0x00000008,
2911 + PCIS_cwe_b = 4,
2912 + PCIS_cwe_m = 0x00000010,
2913 + PCIS_cre_b = 5,
2914 + PCIS_cre_m = 0x00000020,
2915 + PCIS_mdpe_b = 6,
2916 + PCIS_mdpe_m = 0x00000040,
2917 + PCIS_sta_b = 7,
2918 + PCIS_sta_m = 0x00000080,
2919 + PCIS_rta_b = 8,
2920 + PCIS_rta_m = 0x00000100,
2921 + PCIS_rma_b = 9,
2922 + PCIS_rma_m = 0x00000200,
2923 + PCIS_sse_b = 10,
2924 + PCIS_sse_m = 0x00000400,
2925 + PCIS_ose_b = 11,
2926 + PCIS_ose_m = 0x00000800,
2927 + PCIS_pe_b = 12,
2928 + PCIS_pe_m = 0x00001000,
2929 + PCIS_tae_b = 13,
2930 + PCIS_tae_m = 0x00002000,
2931 + PCIS_rle_b = 14,
2932 + PCIS_rle_m = 0x00004000,
2933 + PCIS_bme_b = 15,
2934 + PCIS_bme_m = 0x00008000,
2935 + PCIS_prd_b = 16,
2936 + PCIS_prd_m = 0x00010000,
2937 + PCIS_rip_b = 17,
2938 + PCIS_rip_m = 0x00020000,
2939 +} ;
2940 +
2941 +/*******************************************************************************
2942 + *
2943 + * PCI Status Mask Register
2944 + *
2945 + ******************************************************************************/
2946 +enum {
2947 + PCISM_eed_b = 0,
2948 + PCISM_eed_m = 0x00000001,
2949 + PCISM_wr_b = 1,
2950 + PCISM_wr_m = 0x00000002,
2951 + PCISM_nmi_b = 2,
2952 + PCISM_nmi_m = 0x00000004,
2953 + PCISM_ii_b = 3,
2954 + PCISM_ii_m = 0x00000008,
2955 + PCISM_cwe_b = 4,
2956 + PCISM_cwe_m = 0x00000010,
2957 + PCISM_cre_b = 5,
2958 + PCISM_cre_m = 0x00000020,
2959 + PCISM_mdpe_b = 6,
2960 + PCISM_mdpe_m = 0x00000040,
2961 + PCISM_sta_b = 7,
2962 + PCISM_sta_m = 0x00000080,
2963 + PCISM_rta_b = 8,
2964 + PCISM_rta_m = 0x00000100,
2965 + PCISM_rma_b = 9,
2966 + PCISM_rma_m = 0x00000200,
2967 + PCISM_sse_b = 10,
2968 + PCISM_sse_m = 0x00000400,
2969 + PCISM_ose_b = 11,
2970 + PCISM_ose_m = 0x00000800,
2971 + PCISM_pe_b = 12,
2972 + PCISM_pe_m = 0x00001000,
2973 + PCISM_tae_b = 13,
2974 + PCISM_tae_m = 0x00002000,
2975 + PCISM_rle_b = 14,
2976 + PCISM_rle_m = 0x00004000,
2977 + PCISM_bme_b = 15,
2978 + PCISM_bme_m = 0x00008000,
2979 + PCISM_prd_b = 16,
2980 + PCISM_prd_m = 0x00010000,
2981 + PCISM_rip_b = 17,
2982 + PCISM_rip_m = 0x00020000,
2983 +} ;
2984 +
2985 +/*******************************************************************************
2986 + *
2987 + * PCI Configuration Address Register
2988 + *
2989 + ******************************************************************************/
2990 +enum {
2991 + PCICFGA_reg_b = 2,
2992 + PCICFGA_reg_m = 0x000000fc,
2993 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
2994 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
2995 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
2996 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
2997 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
2998 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
2999 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
3000 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
3001 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
3002 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
3003 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
3004 + PCICFGA_reg_pba0m_v = 0x48>>2,
3005 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
3006 + PCICFGA_reg_pba1m_v = 0x50>>2,
3007 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
3008 + PCICFGA_reg_pba2m_v = 0x58>>2,
3009 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
3010 + PCICFGA_reg_pba3m_v = 0x60>>2,
3011 + PCICFGA_reg_pmgt_v = 0x64>>2,
3012 + PCICFGA_func_b = 8,
3013 + PCICFGA_func_m = 0x00000700,
3014 + PCICFGA_dev_b = 11,
3015 + PCICFGA_dev_m = 0x0000f800,
3016 + PCICFGA_dev_internal_v = 0,
3017 + PCICFGA_bus_b = 16,
3018 + PCICFGA_bus_m = 0x00ff0000,
3019 + PCICFGA_bus_type0_v = 0, //local bus
3020 + PCICFGA_en_b = 31, // read only
3021 + PCICFGA_en_m = 0x80000000,
3022 +} ;
3023 +
3024 +enum {
3025 + PCFGID_vendor_b = 0,
3026 + PCFGID_vendor_m = 0x0000ffff,
3027 + PCFGID_vendor_IDT_v = 0x111d,
3028 + PCFGID_device_b = 16,
3029 + PCFGID_device_m = 0xffff0000,
3030 + PCFGID_device_Korinade_v = 0x0214,
3031 +
3032 + PCFG04_command_ioena_b = 1,
3033 + PCFG04_command_ioena_m = 0x00000001,
3034 + PCFG04_command_memena_b = 2,
3035 + PCFG04_command_memena_m = 0x00000002,
3036 + PCFG04_command_bmena_b = 3,
3037 + PCFG04_command_bmena_m = 0x00000004,
3038 + PCFG04_command_mwinv_b = 5,
3039 + PCFG04_command_mwinv_m = 0x00000010,
3040 + PCFG04_command_parena_b = 7,
3041 + PCFG04_command_parena_m = 0x00000040,
3042 + PCFG04_command_serrena_b = 9,
3043 + PCFG04_command_serrena_m = 0x00000100,
3044 + PCFG04_command_fastbbena_b = 10,
3045 + PCFG04_command_fastbbena_m = 0x00000200,
3046 + PCFG04_status_b = 16,
3047 + PCFG04_status_m = 0xffff0000,
3048 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
3049 + PCFG04_status_66MHz_m = 0x00200000,
3050 + PCFG04_status_fbb_b = 23,
3051 + PCFG04_status_fbb_m = 0x00800000,
3052 + PCFG04_status_mdpe_b = 24,
3053 + PCFG04_status_mdpe_m = 0x01000000,
3054 + PCFG04_status_dst_b = 25,
3055 + PCFG04_status_dst_m = 0x06000000,
3056 + PCFG04_status_sta_b = 27,
3057 + PCFG04_status_sta_m = 0x08000000,
3058 + PCFG04_status_rta_b = 28,
3059 + PCFG04_status_rta_m = 0x10000000,
3060 + PCFG04_status_rma_b = 29,
3061 + PCFG04_status_rma_m = 0x20000000,
3062 + PCFG04_status_sse_b = 30,
3063 + PCFG04_status_sse_m = 0x40000000,
3064 + PCFG04_status_pe_b = 31,
3065 + PCFG04_status_pe_m = 0x40000000,
3066 +
3067 + PCFG08_revId_b = 0,
3068 + PCFG08_revId_m = 0x000000ff,
3069 + PCFG08_classCode_b = 0,
3070 + PCFG08_classCode_m = 0xffffff00,
3071 + PCFG08_classCode_bridge_v = 06,
3072 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
3073 + PCFG0C_cacheline_b = 0,
3074 + PCFG0C_cacheline_m = 0x000000ff,
3075 + PCFG0C_masterLatency_b = 8,
3076 + PCFG0C_masterLatency_m = 0x0000ff00,
3077 + PCFG0C_headerType_b = 16,
3078 + PCFG0C_headerType_m = 0x00ff0000,
3079 + PCFG0C_bist_b = 24,
3080 + PCFG0C_bist_m = 0xff000000,
3081 +
3082 + PCIPBA_msi_b = 0,
3083 + PCIPBA_msi_m = 0x00000001,
3084 + PCIPBA_p_b = 3,
3085 + PCIPBA_p_m = 0x00000004,
3086 + PCIPBA_baddr_b = 8,
3087 + PCIPBA_baddr_m = 0xffffff00,
3088 +
3089 + PCFGSS_vendorId_b = 0,
3090 + PCFGSS_vendorId_m = 0x0000ffff,
3091 + PCFGSS_id_b = 16,
3092 + PCFGSS_id_m = 0xffff0000,
3093 +
3094 + PCFG3C_interruptLine_b = 0,
3095 + PCFG3C_interruptLine_m = 0x000000ff,
3096 + PCFG3C_interruptPin_b = 8,
3097 + PCFG3C_interruptPin_m = 0x0000ff00,
3098 + PCFG3C_minGrant_b = 16,
3099 + PCFG3C_minGrant_m = 0x00ff0000,
3100 + PCFG3C_maxLat_b = 24,
3101 + PCFG3C_maxLat_m = 0xff000000,
3102 +
3103 + PCIPBAC_msi_b = 0,
3104 + PCIPBAC_msi_m = 0x00000001,
3105 + PCIPBAC_p_b = 1,
3106 + PCIPBAC_p_m = 0x00000002,
3107 + PCIPBAC_size_b = 2,
3108 + PCIPBAC_size_m = 0x0000007c,
3109 + PCIPBAC_sb_b = 7,
3110 + PCIPBAC_sb_m = 0x00000080,
3111 + PCIPBAC_pp_b = 8,
3112 + PCIPBAC_pp_m = 0x00000100,
3113 + PCIPBAC_mr_b = 9,
3114 + PCIPBAC_mr_m = 0x00000600,
3115 + PCIPBAC_mr_read_v =0, //no prefetching
3116 + PCIPBAC_mr_readLine_v =1,
3117 + PCIPBAC_mr_readMult_v =2,
3118 + PCIPBAC_mrl_b = 11,
3119 + PCIPBAC_mrl_m = 0x00000800,
3120 + PCIPBAC_mrm_b = 12,
3121 + PCIPBAC_mrm_m = 0x00001000,
3122 + PCIPBAC_trp_b = 13,
3123 + PCIPBAC_trp_m = 0x00002000,
3124 +
3125 + PCFG40_trdyTimeout_b = 0,
3126 + PCFG40_trdyTimeout_m = 0x000000ff,
3127 + PCFG40_retryLim_b = 8,
3128 + PCFG40_retryLim_m = 0x0000ff00,
3129 +};
3130 +
3131 +/*******************************************************************************
3132 + *
3133 + * PCI Local Base Address [0|1|2|3] Register
3134 + *
3135 + ******************************************************************************/
3136 +enum {
3137 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
3138 + PCILBA_baddr_m = 0xffffff00,
3139 +} ;
3140 +/*******************************************************************************
3141 + *
3142 + * PCI Local Base Address Control Register
3143 + *
3144 + ******************************************************************************/
3145 +enum {
3146 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
3147 + PCILBAC_msi_m = 0x00000001,
3148 + PCILBAC_msi_mem_v = 0,
3149 + PCILBAC_msi_io_v = 1,
3150 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
3151 + PCILBAC_size_m = 0x0000007c,
3152 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
3153 + PCILBAC_sb_m = 0x00000080,
3154 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
3155 + PCILBAC_rt_m = 0x00000100,
3156 + PCILBAC_rt_noprefetch_v = 0, // mem read
3157 + PCILBAC_rt_prefetch_v = 1, // mem readline
3158 +} ;
3159 +
3160 +/*******************************************************************************
3161 + *
3162 + * PCI Local Base Address [0|1|2|3] Mapping Register
3163 + *
3164 + ******************************************************************************/
3165 +enum {
3166 + PCILBAM_maddr_b = 8,
3167 + PCILBAM_maddr_m = 0xffffff00,
3168 +} ;
3169 +
3170 +/*******************************************************************************
3171 + *
3172 + * PCI Decoupled Access Control Register
3173 + *
3174 + ******************************************************************************/
3175 +enum {
3176 + PCIDAC_den_b = 0,
3177 + PCIDAC_den_m = 0x00000001,
3178 +} ;
3179 +
3180 +/*******************************************************************************
3181 + *
3182 + * PCI Decoupled Access Status Register
3183 + *
3184 + ******************************************************************************/
3185 +enum {
3186 + PCIDAS_d_b = 0,
3187 + PCIDAS_d_m = 0x00000001,
3188 + PCIDAS_b_b = 1,
3189 + PCIDAS_b_m = 0x00000002,
3190 + PCIDAS_e_b = 2,
3191 + PCIDAS_e_m = 0x00000004,
3192 + PCIDAS_ofe_b = 3,
3193 + PCIDAS_ofe_m = 0x00000008,
3194 + PCIDAS_off_b = 4,
3195 + PCIDAS_off_m = 0x00000010,
3196 + PCIDAS_ife_b = 5,
3197 + PCIDAS_ife_m = 0x00000020,
3198 + PCIDAS_iff_b = 6,
3199 + PCIDAS_iff_m = 0x00000040,
3200 +} ;
3201 +
3202 +/*******************************************************************************
3203 + *
3204 + * PCI DMA Channel 8 Configuration Register
3205 + *
3206 + ******************************************************************************/
3207 +enum
3208 +{
3209 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
3210 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
3211 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
3212 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
3213 +} ;
3214 +
3215 +/*******************************************************************************
3216 + *
3217 + * PCI DMA Channel 9 Configuration Register
3218 + *
3219 + ******************************************************************************/
3220 +enum
3221 +{
3222 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
3223 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
3224 +} ;
3225 +
3226 +/*******************************************************************************
3227 + *
3228 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
3229 + *
3230 + ******************************************************************************/
3231 +enum {
3232 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
3233 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
3234 + // These are for reads (DMA channel 8)
3235 + PCIDMAD_devcmd_mr_v = 0, //memory read
3236 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
3237 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
3238 + PCIDMAD_devcmd_ior_v = 3, //I/O read
3239 + // These are for writes (DMA channel 9)
3240 + PCIDMAD_devcmd_mw_v = 0, //memory write
3241 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
3242 + PCIDMAD_devcmd_iow_v = 3, //I/O write
3243 +
3244 + // Swap byte field applies to both DMA channel 8 and 9
3245 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
3246 + PCIDMAD_sb_m = 0x01000000, // swap byte field
3247 +} ;
3248 +
3249 +
3250 +/*******************************************************************************
3251 + *
3252 + * PCI Target Control Register
3253 + *
3254 + ******************************************************************************/
3255 +enum
3256 +{
3257 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
3258 + PCITC_rtimer_m = 0x000000ff,
3259 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
3260 + PCITC_dtimer_m = 0x0000ff00,
3261 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
3262 + PCITC_rdr_m = 0x00040000,
3263 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
3264 + PCITC_ddt_m = 0x00080000,
3265 +} ;
3266 +/*******************************************************************************
3267 + *
3268 + * PCI messaging unit [applies to both inbound and outbound registers ]
3269 + *
3270 + ******************************************************************************/
3271 +enum
3272 +{
3273 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3274 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
3275 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3276 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
3277 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3278 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
3279 +};
3280 +
3281 +
3282 +
3283 +
3284 +
3285 +
3286 +#define PCI_MSG_VirtualAddress 0xB8088010
3287 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
3288 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
3289 +
3290 +#define PCIM_SHFT 0x6
3291 +#define PCIM_BIT_LEN 0x7
3292 +#define PCIM_H_EA 0x3
3293 +#define PCIM_H_IA_FIX 0x4
3294 +#define PCIM_H_IA_RR 0x5
3295 +#if 0
3296 +#define PCI_ADDR_START 0x13000000
3297 +#endif
3298 +
3299 +#define PCI_ADDR_START 0x50000000
3300 +
3301 +#define CPUTOPCI_MEM_WIN 0x02000000
3302 +#define CPUTOPCI_IO_WIN 0x00100000
3303 +#define PCILBA_SIZE_SHFT 2
3304 +#define PCILBA_SIZE_MASK 0x1F
3305 +#define SIZE_256MB 0x1C
3306 +#define SIZE_128MB 0x1B
3307 +#define SIZE_64MB 0x1A
3308 +#define SIZE_32MB 0x19
3309 +#define SIZE_16MB 0x18
3310 +#define SIZE_4MB 0x16
3311 +#define SIZE_2MB 0x15
3312 +#define SIZE_1MB 0x14
3313 +#define KORINA_CONFIG0_ADDR 0x80000000
3314 +#define KORINA_CONFIG1_ADDR 0x80000004
3315 +#define KORINA_CONFIG2_ADDR 0x80000008
3316 +#define KORINA_CONFIG3_ADDR 0x8000000C
3317 +#define KORINA_CONFIG4_ADDR 0x80000010
3318 +#define KORINA_CONFIG5_ADDR 0x80000014
3319 +#define KORINA_CONFIG6_ADDR 0x80000018
3320 +#define KORINA_CONFIG7_ADDR 0x8000001C
3321 +#define KORINA_CONFIG8_ADDR 0x80000020
3322 +#define KORINA_CONFIG9_ADDR 0x80000024
3323 +#define KORINA_CONFIG10_ADDR 0x80000028
3324 +#define KORINA_CONFIG11_ADDR 0x8000002C
3325 +#define KORINA_CONFIG12_ADDR 0x80000030
3326 +#define KORINA_CONFIG13_ADDR 0x80000034
3327 +#define KORINA_CONFIG14_ADDR 0x80000038
3328 +#define KORINA_CONFIG15_ADDR 0x8000003C
3329 +#define KORINA_CONFIG16_ADDR 0x80000040
3330 +#define KORINA_CONFIG17_ADDR 0x80000044
3331 +#define KORINA_CONFIG18_ADDR 0x80000048
3332 +#define KORINA_CONFIG19_ADDR 0x8000004C
3333 +#define KORINA_CONFIG20_ADDR 0x80000050
3334 +#define KORINA_CONFIG21_ADDR 0x80000054
3335 +#define KORINA_CONFIG22_ADDR 0x80000058
3336 +#define KORINA_CONFIG23_ADDR 0x8000005C
3337 +#define KORINA_CONFIG24_ADDR 0x80000060
3338 +#define KORINA_CONFIG25_ADDR 0x80000064
3339 +#define KORINA_CMD (PCFG04_command_ioena_m | \
3340 + PCFG04_command_memena_m | \
3341 + PCFG04_command_bmena_m | \
3342 + PCFG04_command_mwinv_m | \
3343 + PCFG04_command_parena_m | \
3344 + PCFG04_command_serrena_m )
3345 +
3346 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
3347 + PCFG04_status_sta_m | \
3348 + PCFG04_status_rta_m | \
3349 + PCFG04_status_rma_m | \
3350 + PCFG04_status_sse_m | \
3351 + PCFG04_status_pe_m)
3352 +
3353 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
3354 +
3355 +#define KORINA_REVID 0
3356 +#define KORINA_CLASS_CODE 0
3357 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
3358 + KORINA_REVID)
3359 +
3360 +#define KORINA_CACHE_LINE_SIZE 4
3361 +#define KORINA_MASTER_LAT 0x3c
3362 +#define KORINA_HEADER_TYPE 0
3363 +#define KORINA_BIST 0
3364 +
3365 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
3366 + (KORINA_HEADER_TYPE<<16) | \
3367 + (KORINA_MASTER_LAT<<8) | \
3368 + KORINA_CACHE_LINE_SIZE )
3369 +
3370 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
3371 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
3372 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
3373 + internal Registers */
3374 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
3375 +
3376 +#define KORINA_CNFG4 KORINA_BAR0
3377 +#define KORINA_CNFG5 KORINA_BAR1
3378 +#define KORINA_CNFG6 KORINA_BAR2
3379 +#define KORINA_CNFG7 KORINA_BAR3
3380 +
3381 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
3382 +#define KORINA_SUBSYSTEM_ID 0x0214
3383 +#define KORINA_CNFG8 0
3384 +#define KORINA_CNFG9 0
3385 +#define KORINA_CNFG10 0
3386 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
3387 + KORINA_SUBSYSTEM_ID)
3388 +#define KORINA_INT_LINE 1
3389 +#define KORINA_INT_PIN 1
3390 +#define KORINA_MIN_GNT 8
3391 +#define KORINA_MAX_LAT 0x38
3392 +#define KORINA_CNFG12 0
3393 +#define KORINA_CNFG13 0
3394 +#define KORINA_CNFG14 0
3395 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
3396 + (KORINA_MIN_GNT<<16) | \
3397 + (KORINA_INT_PIN<<8) | \
3398 + KORINA_INT_LINE)
3399 +#define KORINA_RETRY_LIMIT 0x80
3400 +#define KORINA_TRDY_LIMIT 0x80
3401 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
3402 + KORINA_TRDY_LIMIT)
3403 +#define PCI_PBAxC_R 0x0
3404 +#define PCI_PBAxC_RL 0x1
3405 +#define PCI_PBAxC_RM 0x2
3406 +#define SIZE_SHFT 2
3407 +
3408 +#if defined(__MIPSEB__)
3409 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
3410 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
3411 + PCIPBAC_pp_m | \
3412 + (SIZE_128MB<<SIZE_SHFT) | \
3413 + PCIPBAC_p_m)
3414 +#else
3415 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
3416 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
3417 + PCIPBAC_pp_m | \
3418 + (SIZE_128MB<<SIZE_SHFT) | \
3419 + PCIPBAC_p_m)
3420 +#endif
3421 +#define KORINA_CNFG17 KORINA_PBA0C
3422 +#define KORINA_PBA0M 0x0
3423 +#define KORINA_CNFG18 KORINA_PBA0M
3424 +
3425 +#if defined(__MIPSEB__)
3426 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
3427 + PCIPBAC_msi_m)
3428 +#else
3429 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
3430 + PCIPBAC_msi_m)
3431 +#endif
3432 +#define KORINA_CNFG19 KORINA_PBA1C
3433 +#define KORINA_PBA1M 0x0
3434 +#define KORINA_CNFG20 KORINA_PBA1M
3435 +
3436 +#if defined(__MIPSEB__)
3437 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
3438 + PCIPBAC_msi_m)
3439 +#else
3440 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
3441 + PCIPBAC_msi_m)
3442 +#endif
3443 +#define KORINA_CNFG21 KORINA_PBA2C
3444 +#define KORINA_PBA2M 0x18000000
3445 +#define KORINA_CNFG22 KORINA_PBA2M
3446 +#define KORINA_PBA3C 0
3447 +#define KORINA_CNFG23 KORINA_PBA3C
3448 +#define KORINA_PBA3M 0
3449 +#define KORINA_CNFG24 KORINA_PBA3M
3450 +
3451 +
3452 +
3453 +#define PCITC_DTIMER_VAL 8
3454 +#define PCITC_RTIMER_VAL 0x10
3455 +
3456 +
3457 +
3458 +
3459 +#endif // __IDT_PCI_H__
3460 +
3461 +
3462 +
3463 diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
3464 --- linux.old/include/asm-mips/rc32434/rb.h 1970-01-01 01:00:00.000000000 +0100
3465 +++ linux.dev/include/asm-mips/rc32434/rb.h 2006-12-14 04:09:50.000000000 +0100
3466 @@ -0,0 +1,84 @@
3467 +/*
3468 + * Copyright (C) 2004 IDT Inc.
3469 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
3470 + *
3471 + * This program is free software; you can redistribute it and/or modify
3472 + * it under the terms of the GNU General Public License as published by
3473 + * the Free Software Foundation; either version 2 of the License, or
3474 + * (at your option) any later version.
3475 + *
3476 + * This program is distributed in the hope that it will be useful,
3477 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3478 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3479 + * GNU General Public License for more details.
3480 + *
3481 + */
3482 +#ifndef __MIPS_RB_H__
3483 +#define __MIPS_RB_H__
3484 +#include <linux/genhd.h>
3485 +
3486 +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
3487 +#define DEV0BASE 0x010000
3488 +#define DEV0MASK 0x010004
3489 +#define DEV0C 0x010008
3490 +#define DEV0TC 0x01000C
3491 +#define DEV1BASE 0x010010
3492 +#define DEV1MASK 0x010014
3493 +#define DEV1C 0x010018
3494 +#define DEV1TC 0x01001C
3495 +#define DEV2BASE 0x010020
3496 +#define DEV2MASK 0x010024
3497 +#define DEV2C 0x010028
3498 +#define DEV2TC 0x01002C
3499 +#define DEV3BASE 0x010030
3500 +#define DEV3MASK 0x010034
3501 +#define DEV3C 0x010038
3502 +#define DEV3TC 0x01003C
3503 +#define BTCS 0x010040
3504 +#define BTCOMPARE 0x010044
3505 +#define GPIOFUNC 0x050000
3506 +#define GPIOCFG 0x050004
3507 +#define GPIOD 0x050008
3508 +#define GPIOILEVEL 0x05000C
3509 +#define GPIOISTAT 0x050010
3510 +#define GPIONMIEN 0x050014
3511 +#define IMASK6 0x038038
3512 +
3513 +#define LO_WPX (1 << 0)
3514 +#define LO_ALE (1 << 1)
3515 +#define LO_CLE (1 << 2)
3516 +#define LO_CEX (1 << 3)
3517 +#define LO_FOFF (1 << 5)
3518 +#define LO_SPICS (1 << 6)
3519 +#define LO_ULED (1 << 7)
3520 +
3521 +typedef enum {
3522 + FUNC = 0x00,
3523 + CFG = 0x04,
3524 + DATA = 0x08,
3525 + ILEVEL = 0x0c,
3526 + ISTAT = 0x10,
3527 + NMIEN = 0x14
3528 +} gpio_func;
3529 +
3530 +extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
3531 +extern unsigned get434Reg(unsigned regOffs);
3532 +extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
3533 +extern void gpio_set(gpio_func func, u32 mask, u32 value);
3534 +extern u32 gpio_get(gpio_func func);
3535 +
3536 +#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
3537 +
3538 +struct korina_device {
3539 + char *name;
3540 + unsigned char mac[6];
3541 + struct net_device *dev;
3542 +};
3543 +
3544 +struct cf_device {
3545 + int gpio_pin;
3546 + void *dev;
3547 + struct gendisk *gd;
3548 +};
3549 +
3550 +#endif
3551 diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h
3552 --- linux.old/include/asm-mips/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
3553 +++ linux.dev/include/asm-mips/rc32434/rc32434.h 2006-12-14 04:09:50.000000000 +0100
3554 @@ -0,0 +1,122 @@
3555 +/*
3556 + ***************************************************************************
3557 + * Definitions for IDT RC323434 CPU.
3558 + *
3559 + ****************************************************************************
3560 + * Kiran Rao
3561 + *
3562 + * Original form
3563 + ****************************************************************************
3564 + * P. Sadik Oct 08, 2003
3565 + *
3566 + * Started revision history
3567 + * Made IDT_BUS_FREQ a kernel configuration parameter
3568 + ****************************************************************************
3569 + * P. Sadik Oct 10, 2003
3570 + *
3571 + * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
3572 + * idt_cpu_freq is used everywhere
3573 + ****************************************************************************
3574 + * P. Sadik Oct 20, 2003
3575 + *
3576 + * Removed RC32434_BASE_BAUD
3577 + ****************************************************************************
3578 +*/
3579 +#ifndef _RC32434_H_
3580 +#define _RC32434_H_
3581 +
3582 +#include <linux/autoconf.h>
3583 +#include <linux/delay.h>
3584 +#include <asm/io.h>
3585 +
3586 +#define RC32434_REG_BASE 0x18000000
3587 +
3588 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
3589 +#define gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
3590 +
3591 +
3592 +#define IDT_CLOCK_MULT 2
3593 +#define MIPS_CPU_TIMER_IRQ 7
3594 +/* Interrupt Controller */
3595 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
3596 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
3597 +#define IC_GROUP_OFFSET 0x0C
3598 +
3599 +#define NUM_INTR_GROUPS 5
3600 +/* 16550 UARTs */
3601 +
3602 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
3603 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
3604 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
3605 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
3606 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
3607 +
3608 +
3609 +#ifdef __MIPSEB__
3610 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
3611 +#else
3612 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
3613 +#endif
3614 +
3615 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
3616 +// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
3617 +
3618 +#define local_readl(addr) __raw_readl(addr)
3619 +#define local_writel(l,addr) __raw_writel(l,addr)
3620 +
3621 +/* cpu pipeline flush */
3622 +static inline void rc32434_sync(void)
3623 +{
3624 + __asm__ volatile ("sync");
3625 +}
3626 +
3627 +static inline void rc32434_sync_udelay(int us)
3628 +{
3629 + __asm__ volatile ("sync");
3630 + udelay(us);
3631 +}
3632 +
3633 +static inline void rc32434_sync_delay(int ms)
3634 +{
3635 + __asm__ volatile ("sync");
3636 + mdelay(ms);
3637 +}
3638 +
3639 +/*
3640 + * C access to CLZ and CLO instructions
3641 + * (count leading zeroes/ones).
3642 + */
3643 +static inline int rc32434_clz(unsigned long val)
3644 +{
3645 + int ret;
3646 + __asm__ volatile (
3647 + ".set\tnoreorder\n\t"
3648 + ".set\tnoat\n\t"
3649 + ".set\tmips32\n\t"
3650 + "clz\t%0,%1\n\t"
3651 + ".set\tmips0\n\t"
3652 + ".set\tat\n\t"
3653 + ".set\treorder"
3654 + : "=r" (ret)
3655 + : "r" (val));
3656 +
3657 + return ret;
3658 +}
3659 +static inline int rc32434_clo(unsigned long val)
3660 +{
3661 + int ret;
3662 + __asm__ volatile (
3663 + ".set\tnoreorder\n\t"
3664 + ".set\tnoat\n\t"
3665 + ".set\tmips32\n\t"
3666 + "clo\t%0,%1\n\t"
3667 + ".set\tmips0\n\t"
3668 + ".set\tat\n\t"
3669 + ".set\treorder"
3670 + : "=r" (ret)
3671 + : "r" (val));
3672 +
3673 + return ret;
3674 +}
3675 +
3676 +#endif /* _RC32434_H_ */
3677
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