target/linux/rb532/files/arch/mips/rb500/gpio.c

   1 /*
   2  *  Miscellaneous functions for IDT EB434 board
   3  *
   4  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   5  *  Copyright 2006 Phil Sutter <n0-1@freewrt.org>
   6  *  Copyright 2007 Florian Fainelli <florian@openwrt.org>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28
  29 #include <linux/kernel.h>
  30 #include <linux/init.h>
  31 #include <linux/types.h>
  32 #include <linux/pci.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/io.h>
  35 #include <linux/platform_device.h>
  36
  37 #include <asm/addrspace.h>
  38 #include <asm/gpio.h>
  39
  40 #include <asm/rc32434/rb.h>
  41
  42 #define GPIO_BADDR  0xb8050000
  43
  44 static volatile unsigned char *devCtl3Base;
  45 static unsigned char latchU5State;
  46 static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
  47
  48 struct rb500_gpio_reg __iomem *rb500_gpio_reg0;
  49 EXPORT_SYMBOL(rb500_gpio_reg0);
  50
  51 static struct resource rb500_gpio_reg0_res[] = {
  52         {
  53                 .name   = "gpio_reg0",
  54                 .start  = GPIO_BADDR,
  55                 .end    = GPIO_BADDR + sizeof(struct rb500_gpio_reg),
  56                 .flags  = IORESOURCE_MEM,
  57         }
  58 };
  59
  60 void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val)
  61 {
  62         unsigned flags, data;
  63         unsigned i = 0;
  64
  65         spin_lock_irqsave(&clu5Lock, flags);
  66         data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
  67         for (i = 0; i != len; ++i) {
  68                 if (val & (1 << i))
  69                         data |= (1 << (i + bit));
  70                 else
  71                         data &= ~(1 << (i + bit));
  72         }
  73         *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
  74         spin_unlock_irqrestore(&clu5Lock, flags);
  75 }
  76
  77 EXPORT_SYMBOL(set434Reg);
  78
  79 void changeLatchU5(unsigned char orMask, unsigned char nandMask)
  80 {
  81         unsigned flags;
  82
  83         spin_lock_irqsave(&clu5Lock, flags);
  84         latchU5State = (latchU5State | orMask) & ~nandMask;
  85         if (!devCtl3Base)
  86                 devCtl3Base = (volatile unsigned char *)
  87                     KSEG1ADDR(*(volatile unsigned *)
  88                               KSEG1ADDR(0x18010030));
  89         *devCtl3Base = latchU5State;
  90         spin_unlock_irqrestore(&clu5Lock, flags);
  91 }
  92
  93 EXPORT_SYMBOL(changeLatchU5);
  94
  95 unsigned char getLatchU5State(void)
  96 {
  97         return latchU5State;
  98 }
  99
 100 EXPORT_SYMBOL(getLatchU5State);
 101
 102 int rb500_gpio_get_value(unsigned gpio)
 103 {
 104         u32 reg;
 105
 106         reg = readl(&rb500_gpio_reg0->gpiod);
 107         return (reg & (1 << gpio));
 108 }
 109
 110 EXPORT_SYMBOL(rb500_gpio_get_value);
 111
 112 void rb500_gpio_set_value(unsigned gpio, int value)
 113 {
 114         u32 reg;
 115
 116         reg = (u32)&rb500_gpio_reg0->gpiod;
 117
 118         writel(value, (void *)(reg & (1 << gpio)));
 119 }
 120
 121 EXPORT_SYMBOL(rb500_gpio_set_value);
 122
 123 int rb500_gpio_direction_input(unsigned gpio)
 124 {
 125         u32 reg;
 126
 127         reg = (u32)&rb500_gpio_reg0->gpiocfg;
 128         writel(0, (void *)(reg & (1 << gpio)));
 129
 130         return 0;
 131 }
 132
 133 EXPORT_SYMBOL(rb500_gpio_direction_input);
 134
 135 int rb500_gpio_direction_output(unsigned gpio, int value)
 136 {
 137         u32 reg;
 138
 139         reg = (u32)&rb500_gpio_reg0->gpiocfg;
 140         if (value)
 141                 writel(1, (void *)(reg & (1 << gpio)));
 142
 143         return 0;
 144 }
 145
 146 EXPORT_SYMBOL(rb500_gpio_direction_output);
 147
 148 int __init rb500_gpio_init(void)
 149 {
 150         rb500_gpio_reg0 = ioremap_nocache(rb500_gpio_reg0_res[0].start,
 151                                 rb500_gpio_reg0_res[0].end - rb500_gpio_reg0_res[0].start);
 152
 153         if (!rb500_gpio_reg0) {
 154                 printk(KERN_ERR "rb500: cannot remap GPIO register 0\n");
 155                 return -ENXIO;
 156         }
 157
 158         return 0;
 159 }