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[openwrt/svn-archive/archive.git] / target / linux / rdc / files / drivers / net / r6040.c
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
49
50 #include <asm/processor.h>
51
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.18"
54 #define DRV_RELDATE "13Jun2008"
55
56 /* define bits of a debug mask */
57 #define DBG_PHY (1<< 0) /*!< show PHY read/write */
58 #define DBG_FREE_BUFS (1<< 1) /*!< show calls to r6040_free_*bufs */
59 #define DBG_RING (1<< 2) /*!< debug init./freeing of descr rings */
60 #define DBG_RX_BUF (1<< 3) /*!< show alloc. of new rx buf (in IRQ context !) */
61 #define DBG_TX_BUF (1<< 4) /*!< show arrival of new tx buf */
62 #define DBG_RX_IRQ (1<< 5) /*!< show RX IRQ handling */
63 #define DBG_TX_IRQ (1<< 6) /*!< debug TX done IRQ */
64 #define DBG_RX_DESCR (1<< 7) /*!< debug rx descr to be processed */
65 #define DBG_RX_DATA (1<< 8) /*!< show some user data of incoming packet */
66 #define DBG_EXIT (1<< 9) /*!< show exit code calls */
67 #define DBG_INIT (1<<10) /*!< show init. code calls */
68 #define DBG_TX_RING_DUMP (1<<11) /*!< dump the tx ring after creation */
69 #define DBG_RX_RING_DUMP (1<<12) /*!< dump the rx ring after creation */
70 #define DBG_TX_DESCR (1<<13) /*!< dump the setting of a descr for tx */
71 #define DBG_TX_DATA (1<<14) /*!< dump some tx data */
72 #define DBG_IRQ (1<<15) /*!< print inside the irq handler */
73 #define DBG_POLL (1<<16) /*!< dump info on poll procedure */
74 #define DBG_MAC_ADDR (1<<17) /*!< debug mac address setting */
75 #define DBG_OPEN (1<<18) /*!< debug open proc. */
76
77 static int debug = 0;
78 module_param(debug, int, 0);
79 MODULE_PARM_DESC(debug, "debug mask (-1 for all)");
80
81 /* define wcd hich debugs are left in the code during compilation */
82 #define DEBUG (-1) /* all debugs */
83
84 #define dbg(l, f, ...) \
85 do { \
86 if ((DEBUG & l) && (debug & l)) { \
87 printk(KERN_INFO DRV_NAME " %s: " f, __FUNCTION__, ## __VA_ARGS__); \
88 } \
89 } while (0)
90
91 #define err(f, ...) printk(KERN_WARNING DRV_NAME " %s: " f, __FUNCTION__, ## __VA_ARGS__)
92
93 /* PHY CHIP Address */
94 #define PHY1_ADDR 1 /* For MAC1 */
95 #define PHY2_ADDR 2 /* For MAC2 */
96 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
97 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
98
99 /* Time in jiffies before concluding the transmitter is hung. */
100 #define TX_TIMEOUT (6000 * HZ / 1000)
101
102 /* RDC MAC I/O Size */
103 #define R6040_IO_SIZE 256
104
105 /* MAX RDC MAC */
106 #define MAX_MAC 2
107
108 /* MAC registers */
109 #define MCR0 0x00 /* Control register 0 */
110 #define MCR1 0x04 /* Control register 1 */
111 #define MAC_RST 0x0001 /* Reset the MAC */
112 #define MBCR 0x08 /* Bus control */
113 #define MT_ICR 0x0C /* TX interrupt control */
114 #define MR_ICR 0x10 /* RX interrupt control */
115 #define MTPR 0x14 /* TX poll command register */
116 #define MR_BSR 0x18 /* RX buffer size */
117 #define MR_DCR 0x1A /* RX descriptor control */
118 #define MLSR 0x1C /* Last status */
119 #define MMDIO 0x20 /* MDIO control register */
120 #define MDIO_WRITE 0x4000 /* MDIO write */
121 #define MDIO_READ 0x2000 /* MDIO read */
122 #define MMRD 0x24 /* MDIO read data register */
123 #define MMWD 0x28 /* MDIO write data register */
124 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
125 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
126 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
127 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
128 #define MISR 0x3C /* Status register */
129 #define MIER 0x40 /* INT enable register */
130 #define MSK_INT 0x0000 /* Mask off interrupts */
131 #define ME_CISR 0x44 /* Event counter INT status */
132 #define ME_CIER 0x48 /* Event counter INT enable */
133 #define MR_CNT 0x50 /* Successfully received packet counter */
134 #define ME_CNT0 0x52 /* Event counter 0 */
135 #define ME_CNT1 0x54 /* Event counter 1 */
136 #define ME_CNT2 0x56 /* Event counter 2 */
137 #define ME_CNT3 0x58 /* Event counter 3 */
138 #define MT_CNT 0x5A /* Successfully transmit packet counter */
139 #define ME_CNT4 0x5C /* Event counter 4 */
140 #define MP_CNT 0x5E /* Pause frame counter register */
141 #define MAR0 0x60 /* Hash table 0 */
142 #define MAR1 0x62 /* Hash table 1 */
143 #define MAR2 0x64 /* Hash table 2 */
144 #define MAR3 0x66 /* Hash table 3 */
145 #define MID_0L 0x68 /* Multicast address MID0 Low */
146 #define MID_0M 0x6A /* Multicast address MID0 Medium */
147 #define MID_0H 0x6C /* Multicast address MID0 High */
148 #define MID_1L 0x70 /* MID1 Low */
149 #define MID_1M 0x72 /* MID1 Medium */
150 #define MID_1H 0x74 /* MID1 High */
151 #define MID_2L 0x78 /* MID2 Low */
152 #define MID_2M 0x7A /* MID2 Medium */
153 #define MID_2H 0x7C /* MID2 High */
154 #define MID_3L 0x80 /* MID3 Low */
155 #define MID_3M 0x82 /* MID3 Medium */
156 #define MID_3H 0x84 /* MID3 High */
157 #define PHY_CC 0x88 /* PHY status change configuration register */
158 #define PHY_ST 0x8A /* PHY status register */
159 #define MAC_SM 0xAC /* MAC status machine */
160 #define MAC_ID 0xBE /* Identifier register */
161
162 #define TX_DCNT 0x80 /* TX descriptor count */
163 #define RX_DCNT 0x80 /* RX descriptor count */
164 #define MAX_BUF_SIZE 0x600
165 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
166 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
167 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
168 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
169
170 /* PHY settings */
171 #define ICPLUS_PHY_ID 0x0243
172
173 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
174 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
175 "Florian Fainelli <florian@openwrt.org>");
176 MODULE_LICENSE("GPL");
177 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
178
179 #define RX_INT 0x0001
180 #define TX_INT 0x0010
181 #define RX_NO_DESC_INT 0x0002
182 #define INT_MASK (RX_INT | TX_INT)
183
184 struct r6040_descriptor {
185 u16 status, len; /* 0-3 */
186 __le32 buf; /* 4-7 */
187 __le32 ndesc; /* 8-B */
188 u32 rev1; /* C-F */
189 char *vbufp; /* 10-13 */
190 struct r6040_descriptor *vndescp; /* 14-17 */
191 struct sk_buff *skb_ptr; /* 18-1B */
192 u32 rev2; /* 1C-1F */
193 } __attribute__((aligned(32)));
194
195 struct r6040_private {
196 spinlock_t lock; /* driver lock */
197 struct timer_list timer;
198 struct pci_dev *pdev;
199 struct r6040_descriptor *rx_insert_ptr;
200 struct r6040_descriptor *rx_remove_ptr;
201 struct r6040_descriptor *tx_insert_ptr;
202 struct r6040_descriptor *tx_remove_ptr;
203 struct r6040_descriptor *rx_ring;
204 struct r6040_descriptor *tx_ring;
205 dma_addr_t rx_ring_dma;
206 dma_addr_t tx_ring_dma;
207 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
208 u16 mcr0, mcr1;
209 u16 switch_sig;
210 struct net_device *dev;
211 struct mii_if_info mii_if;
212 struct napi_struct napi;
213 void __iomem *base;
214 };
215
216 static char version[] __devinitdata = KERN_INFO DRV_NAME
217 ": RDC R6040 NAPI net driver,"
218 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
219
220 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
221
222 /* jal2: comment out to get more symbols for debugging */
223 //#define STATIC static
224 #define STATIC
225
226 #if DEBUG
227 /*! hexdump an memory area into a string. delim is taken as the delimiter between two bytes.
228 It is omitted if delim == '\0' */
229 STATIC char *hex2str(void *addr, char *buf, int nr_bytes, int delim)
230 {
231 unsigned char *dst = addr;
232 char *outb = buf;
233
234 #define BIN2HEXDIGIT(x) ((x) < 10 ? '0'+(x) : 'A'-10+(x))
235
236 while (nr_bytes > 0) {
237 *outb++ = BIN2HEXDIGIT(*dst>>4);
238 *outb++ = BIN2HEXDIGIT(*dst&0xf);
239 if (delim)
240 *outb++ = delim;
241 nr_bytes--;
242 dst++;
243 }
244
245 if (delim)
246 dst--;
247 *dst = '\0';
248 return buf;
249 }
250
251 #endif /* #if DEBUG */
252
253 /* Read a word data from PHY Chip */
254 STATIC int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
255 {
256 int limit = 2048;
257 u16 cmd;
258 int rc;
259
260 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
261 /* Wait for the read bit to be cleared */
262 while (limit--) {
263 cmd = ioread16(ioaddr + MMDIO);
264 if (cmd & MDIO_READ)
265 break;
266 }
267
268 if (limit <= 0)
269 err("phy addr x%x reg x%x timed out\n",
270 phy_addr, reg);
271
272 rc=ioread16(ioaddr + MMRD);
273
274 dbg(DBG_PHY, "phy addr x%x reg x%x val x%x\n", phy_addr, reg, rc);
275 return rc;
276 }
277
278 /* Write a word data from PHY Chip */
279 STATIC void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
280 {
281 int limit = 2048;
282 u16 cmd;
283
284 dbg(DBG_PHY, "phy addr x%x reg x%x val x%x\n", phy_addr, reg, val);
285
286 iowrite16(val, ioaddr + MMWD);
287 /* Write the command to the MDIO bus */
288 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
289 /* Wait for the write bit to be cleared */
290 while (limit--) {
291 cmd = ioread16(ioaddr + MMDIO);
292 if (cmd & MDIO_WRITE)
293 break;
294 }
295 if (limit <= 0)
296 err("phy addr x%x reg x%x val x%x timed out\n",
297 phy_addr, reg, val);
298 }
299
300 STATIC int mdio_read(struct net_device *dev, int mii_id, int reg)
301 {
302 struct r6040_private *lp = netdev_priv(dev);
303 void __iomem *ioaddr = lp->base;
304
305 return (phy_read(ioaddr, lp->phy_addr, reg));
306 }
307
308 STATIC void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
309 {
310 struct r6040_private *lp = netdev_priv(dev);
311 void __iomem *ioaddr = lp->base;
312
313 phy_write(ioaddr, lp->phy_addr, reg, val);
314 }
315
316 void r6040_free_txbufs(struct net_device *dev)
317 {
318 struct r6040_private *lp = netdev_priv(dev);
319 int i;
320
321 dbg(DBG_FREE_BUFS, "ENTER\n");
322 for (i = 0; i < TX_DCNT; i++) {
323 if (lp->tx_insert_ptr->skb_ptr) {
324 pci_unmap_single(lp->pdev,
325 le32_to_cpu(lp->tx_insert_ptr->buf),
326 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
327 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
328 lp->rx_insert_ptr->skb_ptr = NULL;
329 }
330 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
331 }
332 dbg(DBG_FREE_BUFS, "EXIT\n");
333 }
334
335 void r6040_free_rxbufs(struct net_device *dev)
336 {
337 struct r6040_private *lp = netdev_priv(dev);
338 int i;
339
340 dbg(DBG_FREE_BUFS, "ENTER\n");
341 for (i = 0; i < RX_DCNT; i++) {
342 if (lp->rx_insert_ptr->skb_ptr) {
343 pci_unmap_single(lp->pdev,
344 le32_to_cpu(lp->rx_insert_ptr->buf),
345 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
346 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
347 lp->rx_insert_ptr->skb_ptr = NULL;
348 }
349 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
350 }
351 dbg(DBG_FREE_BUFS, "EXIT\n");
352
353 }
354
355 void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
356 dma_addr_t desc_dma, int size)
357 {
358 struct r6040_descriptor *desc = desc_ring;
359 dma_addr_t mapping = desc_dma;
360
361 dbg(DBG_RING, "desc_ring %p desc_dma %08x size x%x\n",
362 desc_ring, desc_dma, size);
363
364 while (size-- > 0) {
365 mapping += sizeof(sizeof(*desc));
366 desc->ndesc = cpu_to_le32(mapping);
367 desc->vndescp = desc + 1;
368 desc++;
369 }
370 desc--;
371 desc->ndesc = cpu_to_le32(desc_dma);
372 desc->vndescp = desc_ring;
373 }
374
375 /* Allocate skb buffer for rx descriptor */
376 STATIC void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
377 {
378 struct r6040_descriptor *descptr;
379 void __iomem *ioaddr = lp->base;
380
381 dbg(DBG_RX_BUF, "rx_insert %p rx_free_desc x%x dev %p\n",
382 lp->rx_insert_ptr, lp->rx_free_desc, dev);
383
384 descptr = lp->rx_insert_ptr;
385 while (lp->rx_free_desc < RX_DCNT) {
386 descptr->skb_ptr = netdev_alloc_skb(dev, MAX_BUF_SIZE);
387
388 dbg(DBG_RX_BUF, "alloc'ed skb %p for rx descptr %p\n",
389 descptr->skb_ptr, descptr);
390
391 if (!descptr->skb_ptr)
392 break;
393 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
394 descptr->skb_ptr->data,
395 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
396 descptr->status = 0x8000;
397 /* debug before descptr goes to next ! */
398 dbg(DBG_RX_BUF, "descptr %p skb->data %p buf %08x rx_free_desc x%x\n",
399 descptr, descptr->skb_ptr->data, descptr->buf, lp->rx_free_desc);
400 descptr = descptr->vndescp;
401 lp->rx_free_desc++;
402 /* Trigger RX DMA */
403 iowrite16(lp->mcr0 | 0x0002, ioaddr);
404 }
405 lp->rx_insert_ptr = descptr;
406 }
407
408 #if (DEBUG & DBG_TX_RING_DUMP)
409 /*! dump the tx ring to syslog */
410 STATIC void
411 dump_tx_ring(struct r6040_private *lp)
412 {
413 int i;
414 struct r6040_descriptor *ptr;
415
416 printk(KERN_INFO "%s: nr_desc x%x tx_ring %p tx_ring_dma %08x "
417 "tx_insert %p tx_remove %p\n",
418 DRV_NAME, TX_DCNT, lp->tx_ring, lp->tx_ring_dma,
419 lp->tx_insert_ptr, lp->tx_remove_ptr);
420
421 if (lp->tx_ring) {
422 for(i=0, ptr=lp->tx_ring; i < TX_DCNT; i++, ptr++) {
423 printk(KERN_INFO "%s: %d. descr: status x%x len x%x "
424 "ndesc %08x vbufp %p vndescp %p skb_ptr %p\n",
425 DRV_NAME, i, ptr->status, ptr->len,
426 ptr->ndesc, ptr->vbufp, ptr->vndescp, ptr->skb_ptr);
427 }
428 }
429 }
430 #endif /* #if (DEBUG & DBG_TX_RING_DUMP) */
431
432 void r6040_alloc_txbufs(struct net_device *dev)
433 {
434 struct r6040_private *lp = netdev_priv(dev);
435 void __iomem *ioaddr = lp->base;
436
437 lp->tx_free_desc = TX_DCNT;
438
439 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
440 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
441
442 #if (DEBUG & DBG_TX_RING_DUMP)
443 if (debug & DBG_TX_RING_DUMP) {
444 dump_tx_ring(lp);
445 }
446 #endif
447 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
448 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
449 }
450
451 #if (DEBUG & DBG_RX_RING_DUMP)
452 /*! dump the rx ring to syslog */
453 STATIC void
454 dump_rx_ring(struct r6040_private *lp)
455 {
456 int i;
457 struct r6040_descriptor *ptr;
458
459 printk(KERN_INFO "%s: nr_desc x%x rx_ring %p rx_ring_dma %08x "
460 "rx_insert %p rx_remove %p\n",
461 DRV_NAME, RX_DCNT, lp->rx_ring, lp->rx_ring_dma,
462 lp->rx_insert_ptr, lp->rx_remove_ptr);
463
464 if (lp->rx_ring) {
465 for(i=0, ptr=lp->rx_ring; i < RX_DCNT; i++, ptr++) {
466 printk(KERN_INFO "%s: %d. descr: status x%x len x%x "
467 "ndesc %08x vbufp %p vndescp %p skb_ptr %p\n",
468 DRV_NAME, i, ptr->status, ptr->len,
469 ptr->ndesc, ptr->vbufp, ptr->vndescp, ptr->skb_ptr);
470 }
471 }
472 }
473 #endif /* #if (DEBUG & DBG_TX_RING_DUMP) */
474
475 void r6040_alloc_rxbufs(struct net_device *dev)
476 {
477 struct r6040_private *lp = netdev_priv(dev);
478 void __iomem *ioaddr = lp->base;
479
480 lp->rx_free_desc = 0;
481
482 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
483 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
484
485 rx_buf_alloc(lp, dev);
486
487 #if (DEBUG & DBG_RX_RING_DUMP)
488 if (debug & DBG_RX_RING_DUMP) {
489 dump_rx_ring(lp);
490 }
491 #endif
492
493 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
494 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
495 }
496
497 void r6040_tx_timeout(struct net_device *dev)
498 {
499 struct r6040_private *priv = netdev_priv(dev);
500 void __iomem *ioaddr = priv->base;
501
502 printk(KERN_WARNING "%s: transmit timed out, status %4.4x, PHY status "
503 "%4.4x\n",
504 dev->name, ioread16(ioaddr + MIER),
505 mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
506
507 disable_irq(dev->irq);
508 napi_disable(&priv->napi);
509 spin_lock(&priv->lock);
510 /* Clear all descriptors */
511 r6040_free_txbufs(dev);
512 r6040_free_rxbufs(dev);
513 r6040_alloc_txbufs(dev);
514 r6040_alloc_rxbufs(dev);
515
516 /* Reset MAC */
517 iowrite16(MAC_RST, ioaddr + MCR1);
518 spin_unlock(&priv->lock);
519 enable_irq(dev->irq);
520
521 dev->stats.tx_errors++;
522 netif_wake_queue(dev);
523 }
524
525 struct net_device_stats *r6040_get_stats(struct net_device *dev)
526 {
527 struct r6040_private *priv = netdev_priv(dev);
528 void __iomem *ioaddr = priv->base;
529 unsigned long flags;
530
531 spin_lock_irqsave(&priv->lock, flags);
532 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
533 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
534 spin_unlock_irqrestore(&priv->lock, flags);
535
536 return &dev->stats;
537 }
538
539 /* Stop RDC MAC and Free the allocated resource */
540 void r6040_down(struct net_device *dev)
541 {
542 struct r6040_private *lp = netdev_priv(dev);
543 void __iomem *ioaddr = lp->base;
544 struct pci_dev *pdev = lp->pdev;
545 int limit = 2048;
546 u16 *adrp;
547 u16 cmd;
548
549 dbg(DBG_EXIT, "ENTER\n");
550
551 /* Stop MAC */
552 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
553 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
554 while (limit--) {
555 cmd = ioread16(ioaddr + MCR1);
556 if (cmd & 0x1)
557 break;
558 }
559
560 if (limit <= 0)
561 err("timeout while waiting for reset\n");
562
563 /* Restore MAC Address to MIDx */
564 adrp = (u16 *) dev->dev_addr;
565 iowrite16(adrp[0], ioaddr + MID_0L);
566 iowrite16(adrp[1], ioaddr + MID_0M);
567 iowrite16(adrp[2], ioaddr + MID_0H);
568 free_irq(dev->irq, dev);
569
570 /* Free RX buffer */
571 r6040_free_rxbufs(dev);
572
573 /* Free TX buffer */
574 r6040_free_txbufs(dev);
575
576 /* Free Descriptor memory */
577 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
578 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
579
580 dbg(DBG_EXIT, "EXIT\n");
581 }
582
583 int r6040_close(struct net_device *dev)
584 {
585 struct r6040_private *lp = netdev_priv(dev);
586
587 dbg(DBG_EXIT, "ENTER\n");
588
589 /* deleted timer */
590 del_timer_sync(&lp->timer);
591
592 spin_lock_irq(&lp->lock);
593 netif_stop_queue(dev);
594 r6040_down(dev);
595 spin_unlock_irq(&lp->lock);
596
597 dbg(DBG_EXIT, "EXIT\n");
598 return 0;
599 }
600
601 /* Status of PHY CHIP. Returns 0x8000 for full duplex, 0 for half duplex */
602 STATIC int phy_mode_chk(struct net_device *dev)
603 {
604 struct r6040_private *lp = netdev_priv(dev);
605 void __iomem *ioaddr = lp->base;
606 int phy_dat;
607
608 /* PHY Link Status Check */
609 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
610 if (!(phy_dat & 0x4))
611 phy_dat = 0x8000; /* Link Failed, full duplex */
612
613 /* PHY Chip Auto-Negotiation Status */
614 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
615 if (phy_dat & 0x0020) {
616 /* Auto Negotiation Mode */
617 phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
618 phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
619 if (phy_dat & 0x140)
620 /* Force full duplex */
621 phy_dat = 0x8000;
622 else
623 phy_dat = 0;
624 } else {
625 /* Force Mode */
626 phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
627 if (phy_dat & 0x100)
628 phy_dat = 0x8000;
629 else
630 phy_dat = 0x0000;
631 }
632
633 dbg(DBG_PHY, "RETURN x%x\n", phy_dat);
634 return phy_dat;
635 };
636
637 void r6040_set_carrier(struct mii_if_info *mii)
638 {
639 if (phy_mode_chk(mii->dev)) {
640 /* autoneg is off: Link is always assumed to be up */
641 if (!netif_carrier_ok(mii->dev))
642 netif_carrier_on(mii->dev);
643 } else
644 phy_mode_chk(mii->dev);
645 }
646
647 int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
648 {
649 struct r6040_private *lp = netdev_priv(dev);
650 struct mii_ioctl_data *data = if_mii(rq);
651 int rc;
652
653 if (!netif_running(dev))
654 return -EINVAL;
655 spin_lock_irq(&lp->lock);
656 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
657 spin_unlock_irq(&lp->lock);
658 r6040_set_carrier(&lp->mii_if);
659 return rc;
660 }
661
662 int r6040_rx(struct net_device *dev, int limit)
663 {
664 struct r6040_private *priv = netdev_priv(dev);
665 int count;
666 void __iomem *ioaddr = priv->base;
667 u16 err;
668
669 for (count = 0; count < limit; ++count) {
670 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
671 struct sk_buff *skb_ptr;
672
673 /* Disable RX interrupt */
674 iowrite16(ioread16(ioaddr + MIER) & (~RX_INT), ioaddr + MIER);
675 descptr = priv->rx_remove_ptr;
676
677 /* Check for errors */
678 err = ioread16(ioaddr + MLSR);
679 if (err & 0x0400)
680 dev->stats.rx_errors++;
681 /* RX FIFO over-run */
682 if (err & 0x8000)
683 dev->stats.rx_fifo_errors++;
684 /* RX descriptor unavailable */
685 if (err & 0x0080)
686 dev->stats.rx_frame_errors++;
687 /* Received packet with length over buffer lenght */
688 if (err & 0x0020)
689 dev->stats.rx_over_errors++;
690 /* Received packet with too long or short */
691 if (err & (0x0010 | 0x0008))
692 dev->stats.rx_length_errors++;
693 /* Received packet with CRC errors */
694 if (err & 0x0004) {
695 spin_lock(&priv->lock);
696 dev->stats.rx_crc_errors++;
697 spin_unlock(&priv->lock);
698 }
699
700 dbg(DBG_RX_IRQ, "descptr %p status x%x err x%x\n",
701 descptr, descptr->status, err);
702
703 while (priv->rx_free_desc) {
704 /* No RX packet */
705 if (descptr->status & 0x8000)
706 break;
707 skb_ptr = descptr->skb_ptr;
708 if (!skb_ptr) {
709 printk(KERN_ERR "%s: Inconsistent RX"
710 "descriptor chain\n",
711 dev->name);
712 break;
713 }
714 descptr->skb_ptr = NULL;
715 skb_ptr->dev = priv->dev;
716 /* Do not count the CRC */
717 skb_put(skb_ptr, descptr->len - 4);
718 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
719 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
720 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
721
722 dbg(DBG_RX_DESCR, "descptr %p status x%x err x%x data len x%x\n",
723 descptr, descptr->status, err, descptr->len);
724
725 {
726 char obuf[2*32+1] __attribute__ ((unused));
727 dbg(DBG_RX_DATA, "rx len x%x: %s...\n",
728 descptr->len,
729 hex2str(skb_ptr->data, obuf, sizeof(obuf)/2, '\0'));
730 }
731
732 /* Send to upper layer */
733 netif_receive_skb(skb_ptr);
734 dev->last_rx = jiffies;
735 dev->stats.rx_packets++;
736 dev->stats.rx_bytes += descptr->len;
737 /* To next descriptor */
738 descptr = descptr->vndescp;
739 priv->rx_free_desc--;
740 }
741 priv->rx_remove_ptr = descptr;
742 }
743 /* Allocate new RX buffer */
744 if (priv->rx_free_desc < RX_DCNT)
745 rx_buf_alloc(priv, priv->dev);
746
747 return count;
748 }
749
750 void r6040_tx(struct net_device *dev)
751 {
752 struct r6040_private *priv = netdev_priv(dev);
753 struct r6040_descriptor *descptr;
754 void __iomem *ioaddr = priv->base;
755 struct sk_buff *skb_ptr;
756 u16 err;
757
758 spin_lock(&priv->lock);
759 descptr = priv->tx_remove_ptr;
760 while (priv->tx_free_desc < TX_DCNT) {
761 /* Check for errors */
762 err = ioread16(ioaddr + MLSR);
763
764 if (err & 0x0200)
765 dev->stats.rx_fifo_errors++;
766 if (err & (0x2000 | 0x4000))
767 dev->stats.tx_carrier_errors++;
768
769 dbg(DBG_TX_IRQ, "descptr %p status x%x err x%x\n",
770 descptr, descptr->status, err);
771
772 if (descptr->status & 0x8000)
773 break; /* Not complete */
774 skb_ptr = descptr->skb_ptr;
775 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
776 skb_ptr->len, PCI_DMA_TODEVICE);
777 /* Free buffer */
778 dev_kfree_skb_irq(skb_ptr);
779 descptr->skb_ptr = NULL;
780 /* To next descriptor */
781 descptr = descptr->vndescp;
782 priv->tx_free_desc++;
783 }
784 priv->tx_remove_ptr = descptr;
785
786 if (priv->tx_free_desc)
787 netif_wake_queue(dev);
788 spin_unlock(&priv->lock);
789 }
790
791 int r6040_poll(struct napi_struct *napi, int budget)
792 {
793 struct r6040_private *priv =
794 container_of(napi, struct r6040_private, napi);
795 struct net_device *dev = priv->dev;
796 void __iomem *ioaddr = priv->base;
797 int work_done;
798
799 work_done = r6040_rx(dev, budget);
800
801 dbg(DBG_POLL, "budget x%x done x%x\n", budget, work_done);
802
803 if (work_done < budget) {
804 netif_rx_complete(dev, napi);
805 /* Enable RX interrupt */
806 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
807 }
808 return work_done;
809 }
810
811 /* The RDC interrupt handler. */
812 irqreturn_t r6040_interrupt(int irq, void *dev_id)
813 {
814 struct net_device *dev = dev_id;
815 struct r6040_private *lp = netdev_priv(dev);
816 void __iomem *ioaddr = lp->base;
817 u16 status;
818
819 /* Mask off RDC MAC interrupt */
820 iowrite16(MSK_INT, ioaddr + MIER);
821 /* Read MISR status and clear */
822 status = ioread16(ioaddr + MISR);
823
824 dbg(DBG_IRQ, "status x%x\n", status);
825
826 if (status == 0x0000 || status == 0xffff)
827 return IRQ_NONE;
828
829 /* RX interrupt request */
830 if (status & 0x01) {
831 netif_rx_schedule(dev, &lp->napi);
832 iowrite16(TX_INT, ioaddr + MIER);
833 }
834
835 /* TX interrupt request */
836 if (status & 0x10)
837 r6040_tx(dev);
838
839 return IRQ_HANDLED;
840 }
841
842 #ifdef CONFIG_NET_POLL_CONTROLLER
843 void r6040_poll_controller(struct net_device *dev)
844 {
845 disable_irq(dev->irq);
846 r6040_interrupt(dev->irq, dev);
847 enable_irq(dev->irq);
848 }
849 #endif
850
851 /* Init RDC MAC */
852 void r6040_up(struct net_device *dev)
853 {
854 struct r6040_private *lp = netdev_priv(dev);
855 void __iomem *ioaddr = lp->base;
856
857 dbg(DBG_INIT, "ENTER\n");
858
859 /* Initialise and alloc RX/TX buffers */
860 r6040_alloc_txbufs(dev);
861 r6040_alloc_rxbufs(dev);
862
863 /* Buffer Size Register */
864 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
865 /* Read the PHY ID */
866 lp->switch_sig = phy_read(ioaddr, 0, 2);
867
868 if (lp->switch_sig == ICPLUS_PHY_ID) {
869 phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
870 lp->phy_mode = 0x8000;
871 } else {
872 /* PHY Mode Check */
873 phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
874 phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
875
876 if (PHY_MODE == 0x3100)
877 lp->phy_mode = phy_mode_chk(dev);
878 else
879 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
880 }
881 /* MAC Bus Control Register */
882 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
883
884 /* MAC TX/RX Enable */
885 lp->mcr0 |= lp->phy_mode;
886 iowrite16(lp->mcr0, ioaddr);
887
888 /* set interrupt waiting time and packet numbers */
889 iowrite16(0x0F06, ioaddr + MT_ICR);
890 iowrite16(0x0F06, ioaddr + MR_ICR);
891
892 /* improve performance (by RDC guys) */
893 phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
894 phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
895 phy_write(ioaddr, 0, 19, 0x0000);
896 phy_write(ioaddr, 0, 30, 0x01F0);
897
898 /* Interrupt Mask Register */
899 iowrite16(INT_MASK, ioaddr + MIER);
900 }
901
902 /*
903 A periodic timer routine
904 Polling PHY Chip Link Status
905 */
906 void r6040_timer(unsigned long data)
907 {
908 struct net_device *dev = (struct net_device *)data;
909 struct r6040_private *lp = netdev_priv(dev);
910 void __iomem *ioaddr = lp->base;
911 u16 phy_mode;
912
913 /* Polling PHY Chip Status */
914 if (PHY_MODE == 0x3100)
915 phy_mode = phy_mode_chk(dev);
916 else
917 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
918
919 if (phy_mode != lp->phy_mode) {
920 lp->phy_mode = phy_mode;
921 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
922 iowrite16(lp->mcr0, ioaddr);
923 printk(KERN_INFO "Link Change x%x \n", ioread16(ioaddr));
924 }
925
926 /* Timer active again */
927 mod_timer(&lp->timer, jiffies + round_jiffies(HZ));
928 }
929
930 /* Read/set MAC address routines */
931 void r6040_mac_address(struct net_device *dev)
932 {
933 struct r6040_private *lp = netdev_priv(dev);
934 void __iomem *ioaddr = lp->base;
935 u16 *adrp;
936
937 /* MAC operation register */
938 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
939 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
940 iowrite16(0, ioaddr + MAC_SM);
941 udelay(5000);
942
943 /* Restore MAC Address */
944 adrp = (u16 *) dev->dev_addr;
945 iowrite16(adrp[0], ioaddr + MID_0L);
946 iowrite16(adrp[1], ioaddr + MID_0M);
947 iowrite16(adrp[2], ioaddr + MID_0H);
948
949 {
950 char obuf[3*ETH_ALEN] __attribute__ ((unused));
951 dbg(DBG_MAC_ADDR, "set MAC addr %s\n",
952 hex2str(dev->dev_addr, obuf, ETH_ALEN, ':'));
953 }
954 }
955
956 int r6040_open(struct net_device *dev)
957 {
958 struct r6040_private *lp = netdev_priv(dev);
959 int ret;
960
961 dbg(DBG_OPEN, "ENTER\n");
962 /* Request IRQ and Register interrupt handler */
963 ret = request_irq(dev->irq, &r6040_interrupt,
964 IRQF_SHARED, dev->name, dev);
965 if (ret)
966 return ret;
967
968 dbg(DBG_OPEN, "got irq %d\n", dev->irq);
969
970 /* Set MAC address */
971 r6040_mac_address(dev);
972
973 /* Allocate Descriptor memory */
974 lp->rx_ring =
975 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
976 if (!lp->rx_ring)
977 return -ENOMEM;
978
979 dbg(DBG_OPEN, "allocated rx ring\n");
980
981 lp->tx_ring =
982 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
983 if (!lp->tx_ring) {
984 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
985 lp->rx_ring_dma);
986 return -ENOMEM;
987 }
988
989 dbg(DBG_OPEN, "allocated tx ring\n");
990
991 r6040_up(dev);
992
993 napi_enable(&lp->napi);
994 netif_start_queue(dev);
995
996 /* set and active a timer process */
997 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
998 if (lp->switch_sig != ICPLUS_PHY_ID)
999 mod_timer(&lp->timer, jiffies + HZ);
1000 return 0;
1001 }
1002
1003 int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
1004 {
1005 struct r6040_private *lp = netdev_priv(dev);
1006 struct r6040_descriptor *descptr;
1007 void __iomem *ioaddr = lp->base;
1008 unsigned long flags;
1009 int ret = NETDEV_TX_OK;
1010
1011 /* Critical Section */
1012 spin_lock_irqsave(&lp->lock, flags);
1013
1014 /* TX resource check */
1015 if (!lp->tx_free_desc) {
1016 spin_unlock_irqrestore(&lp->lock, flags);
1017 netif_stop_queue(dev);
1018 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
1019 ret = NETDEV_TX_BUSY;
1020 return ret;
1021 }
1022
1023 /* Statistic Counter */
1024 dev->stats.tx_packets++;
1025 dev->stats.tx_bytes += skb->len;
1026 /* Set TX descriptor & Transmit it */
1027 lp->tx_free_desc--;
1028 descptr = lp->tx_insert_ptr;
1029 if (skb->len < MISR)
1030 descptr->len = MISR;
1031 else
1032 descptr->len = skb->len;
1033
1034 descptr->skb_ptr = skb;
1035 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
1036 skb->data, skb->len, PCI_DMA_TODEVICE));
1037
1038 dbg(DBG_TX_DESCR, "desc @ %p: len x%x buf %08x skb->data %p skb->len x%x\n",
1039 descptr, descptr->len, descptr->buf, skb->data, skb->len);
1040
1041 {
1042 char obuf[2*32+1];
1043 dbg(DBG_TX_DATA, "tx len x%x: %s\n",
1044 descptr->len, hex2str(skb->data, obuf, sizeof(obuf)/2, '\0'));
1045 }
1046
1047 descptr->status = 0x8000;
1048 /* Trigger the MAC to check the TX descriptor */
1049 iowrite16(0x01, ioaddr + MTPR);
1050 lp->tx_insert_ptr = descptr->vndescp;
1051
1052 /* If no tx resource, stop */
1053 if (!lp->tx_free_desc)
1054 netif_stop_queue(dev);
1055
1056 dev->trans_start = jiffies;
1057 spin_unlock_irqrestore(&lp->lock, flags);
1058 return ret;
1059 }
1060
1061 void r6040_multicast_list(struct net_device *dev)
1062 {
1063 struct r6040_private *lp = netdev_priv(dev);
1064 void __iomem *ioaddr = lp->base;
1065 u16 *adrp;
1066 u16 reg;
1067 unsigned long flags;
1068 struct dev_mc_list *dmi = dev->mc_list;
1069 int i;
1070
1071 /* MAC Address */
1072 adrp = (u16 *)dev->dev_addr;
1073 iowrite16(adrp[0], ioaddr + MID_0L);
1074 iowrite16(adrp[1], ioaddr + MID_0M);
1075 iowrite16(adrp[2], ioaddr + MID_0H);
1076
1077 /* Promiscous Mode */
1078 spin_lock_irqsave(&lp->lock, flags);
1079
1080 /* Clear AMCP & PROM bits */
1081 reg = ioread16(ioaddr) & ~0x0120;
1082 if (dev->flags & IFF_PROMISC) {
1083 reg |= 0x0020;
1084 lp->mcr0 |= 0x0020;
1085 }
1086 /* Too many multicast addresses
1087 * accept all traffic */
1088 else if ((dev->mc_count > MCAST_MAX)
1089 || (dev->flags & IFF_ALLMULTI))
1090 reg |= 0x0020;
1091
1092 iowrite16(reg, ioaddr);
1093 spin_unlock_irqrestore(&lp->lock, flags);
1094
1095 /* Build the hash table */
1096 if (dev->mc_count > MCAST_MAX) {
1097 u16 hash_table[4];
1098 u32 crc;
1099
1100 for (i = 0; i < 4; i++)
1101 hash_table[i] = 0;
1102
1103 for (i = 0; i < dev->mc_count; i++) {
1104 char *addrs = dmi->dmi_addr;
1105
1106 dmi = dmi->next;
1107
1108 if (!(*addrs & 1))
1109 continue;
1110
1111 crc = ether_crc_le(6, addrs);
1112 crc >>= 26;
1113 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1114 }
1115 /* Write the index of the hash table */
1116 for (i = 0; i < 4; i++)
1117 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
1118 /* Fill the MAC hash tables with their values */
1119 iowrite16(hash_table[0], ioaddr + MAR0);
1120 iowrite16(hash_table[1], ioaddr + MAR1);
1121 iowrite16(hash_table[2], ioaddr + MAR2);
1122 iowrite16(hash_table[3], ioaddr + MAR3);
1123 }
1124 /* Multicast Address 1~4 case */
1125 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
1126 adrp = (u16 *)dmi->dmi_addr;
1127 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
1128 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
1129 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
1130 dmi = dmi->next;
1131 }
1132 for (i = dev->mc_count; i < MCAST_MAX; i++) {
1133 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
1134 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
1135 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
1136 }
1137 }
1138
1139 STATIC void netdev_get_drvinfo(struct net_device *dev,
1140 struct ethtool_drvinfo *info)
1141 {
1142 struct r6040_private *rp = netdev_priv(dev);
1143
1144 strcpy(info->driver, DRV_NAME);
1145 strcpy(info->version, DRV_VERSION);
1146 strcpy(info->bus_info, pci_name(rp->pdev));
1147 }
1148
1149 STATIC int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1150 {
1151 struct r6040_private *rp = netdev_priv(dev);
1152 int rc;
1153
1154 spin_lock_irq(&rp->lock);
1155 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1156 spin_unlock_irq(&rp->lock);
1157
1158 return rc;
1159 }
1160
1161 STATIC int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1162 {
1163 struct r6040_private *rp = netdev_priv(dev);
1164 int rc;
1165
1166 spin_lock_irq(&rp->lock);
1167 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1168 spin_unlock_irq(&rp->lock);
1169 r6040_set_carrier(&rp->mii_if);
1170
1171 return rc;
1172 }
1173
1174 STATIC u32 netdev_get_link(struct net_device *dev)
1175 {
1176 struct r6040_private *rp = netdev_priv(dev);
1177
1178 return mii_link_ok(&rp->mii_if);
1179 }
1180
1181 static struct ethtool_ops netdev_ethtool_ops = {
1182 .get_drvinfo = netdev_get_drvinfo,
1183 .get_settings = netdev_get_settings,
1184 .set_settings = netdev_set_settings,
1185 .get_link = netdev_get_link,
1186 };
1187
1188 int __devinit r6040_init_one(struct pci_dev *pdev,
1189 const struct pci_device_id *ent)
1190 {
1191 struct net_device *dev;
1192 struct r6040_private *lp;
1193 void __iomem *ioaddr;
1194 int err, io_size = R6040_IO_SIZE;
1195 static int card_idx = -1;
1196 int bar = 0;
1197 long pioaddr;
1198 u16 *adrp;
1199
1200 printk(KERN_INFO "%s\n", version);
1201 printk(KERN_INFO DRV_NAME ": debug %x\n", debug);
1202
1203 err = pci_enable_device(pdev);
1204 if (err)
1205 return err;
1206
1207 /* this should always be supported */
1208 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1209 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1210 "not supported by the card\n");
1211 return -ENODEV;
1212 }
1213 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1214 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1215 "not supported by the card\n");
1216 return -ENODEV;
1217 }
1218
1219 /* IO Size check */
1220 if (pci_resource_len(pdev, 0) < io_size) {
1221 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1222 return -EIO;
1223 }
1224
1225 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1226 pci_set_master(pdev);
1227
1228 dev = alloc_etherdev(sizeof(struct r6040_private));
1229 if (!dev) {
1230 printk(KERN_ERR "Failed to allocate etherdev\n");
1231 return -ENOMEM;
1232 }
1233 SET_NETDEV_DEV(dev, &pdev->dev);
1234 lp = netdev_priv(dev);
1235 lp->pdev = pdev;
1236
1237 if (pci_request_regions(pdev, DRV_NAME)) {
1238 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1239 err = -ENODEV;
1240 goto err_out_disable;
1241 }
1242
1243 ioaddr = pci_iomap(pdev, bar, io_size);
1244 if (!ioaddr) {
1245 printk(KERN_ERR "ioremap failed for device %s\n",
1246 pci_name(pdev));
1247 return -EIO;
1248 }
1249
1250 /* Init system & device */
1251 lp->base = ioaddr;
1252 dev->irq = pdev->irq;
1253
1254 spin_lock_init(&lp->lock);
1255 pci_set_drvdata(pdev, dev);
1256
1257 /* Set MAC address */
1258 card_idx++;
1259
1260 adrp = (u16 *)dev->dev_addr;
1261 adrp[0] = ioread16(ioaddr + MID_0L);
1262 adrp[1] = ioread16(ioaddr + MID_0M);
1263 adrp[2] = ioread16(ioaddr + MID_0H);
1264
1265 /* Link new device into r6040_root_dev */
1266 lp->pdev = pdev;
1267
1268 /* Init RDC private data */
1269 lp->mcr0 = 0x1002;
1270 lp->phy_addr = phy_table[card_idx];
1271 lp->switch_sig = 0;
1272
1273 /* The RDC-specific entries in the device structure. */
1274 dev->open = &r6040_open;
1275 dev->hard_start_xmit = &r6040_start_xmit;
1276 dev->stop = &r6040_close;
1277 dev->get_stats = r6040_get_stats;
1278 dev->set_multicast_list = &r6040_multicast_list;
1279 dev->do_ioctl = &r6040_ioctl;
1280 dev->ethtool_ops = &netdev_ethtool_ops;
1281 dev->tx_timeout = &r6040_tx_timeout;
1282 dev->watchdog_timeo = TX_TIMEOUT;
1283
1284 {
1285 /* jal2: added for debugging only: set fixed mac address.
1286 Otherwise we need to call "ifconfig ethX hw ether XX:XX:..."
1287 before we can invoke "ifconfig ethX up" */
1288 static const u8 dflt_addr[ETH_ALEN] = {0,0x50,0xfc,2,3,4};
1289 memcpy(dev->dev_addr, dflt_addr, ETH_ALEN);
1290 }
1291
1292 #ifdef CONFIG_NET_POLL_CONTROLLER
1293 dev->poll_controller = r6040_poll_controller;
1294 #endif
1295 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1296 lp->mii_if.dev = dev;
1297 lp->mii_if.mdio_read = mdio_read;
1298 lp->mii_if.mdio_write = mdio_write;
1299 lp->mii_if.phy_id = lp->phy_addr;
1300 lp->mii_if.phy_id_mask = 0x1f;
1301 lp->mii_if.reg_num_mask = 0x1f;
1302
1303 /* Register net device. After this dev->name assign */
1304 err = register_netdev(dev);
1305 if (err) {
1306 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1307 goto err_out_res;
1308 }
1309
1310 dbg(DBG_INIT, "%s successfully registered\n", dev->name);
1311 return 0;
1312
1313 err_out_res:
1314 pci_release_regions(pdev);
1315 err_out_disable:
1316 pci_disable_device(pdev);
1317 pci_set_drvdata(pdev, NULL);
1318 free_netdev(dev);
1319
1320 return err;
1321 }
1322
1323 void __devexit r6040_remove_one(struct pci_dev *pdev)
1324 {
1325 struct net_device *dev = pci_get_drvdata(pdev);
1326
1327 unregister_netdev(dev);
1328 pci_release_regions(pdev);
1329 free_netdev(dev);
1330 pci_disable_device(pdev);
1331 pci_set_drvdata(pdev, NULL);
1332 }
1333
1334
1335 static struct pci_device_id r6040_pci_tbl[] = {
1336 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1337 { 0 }
1338 };
1339 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1340
1341 static struct pci_driver r6040_driver = {
1342 .name = DRV_NAME,
1343 .id_table = r6040_pci_tbl,
1344 .probe = r6040_init_one,
1345 .remove = __devexit_p(r6040_remove_one),
1346 };
1347
1348
1349 static int __init r6040_init(void)
1350 {
1351 return pci_register_driver(&r6040_driver);
1352 }
1353
1354
1355 static void __exit r6040_cleanup(void)
1356 {
1357 pci_unregister_driver(&r6040_driver);
1358 }
1359
1360 module_init(r6040_init);
1361 module_exit(r6040_cleanup);
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