target/linux/s3c24xx/patches-2.6.28/001-merge-openmoko.patch

   1 Merge OpenMoko kernel patches
   2 git://git.openmoko.org/git/kernel.git#andy-tracking
   3
   4 mb@homer   Thu Jan  1 22:58:51 UTC 2009
   5
   6 ---
   7
   8 --- a/arch/arm/common/vic.c
   9 +++ b/arch/arm/common/vic.c
  10 @@ -69,12 +69,12 @@ void __init vic_init(void __iomem *base,
  11         /*
  12          * Make sure we clear all existing interrupts
  13          */
  14 -       writel(0, base + VIC_VECT_ADDR);
  15 +       writel(0, base + VIC_PL190_VECT_ADDR);
  16         for (i = 0; i < 19; i++) {
  17                 unsigned int value;
  18
  19 -               value = readl(base + VIC_VECT_ADDR);
  20 -               writel(value, base + VIC_VECT_ADDR);
  21 +               value = readl(base + VIC_PL190_VECT_ADDR);
  22 +               writel(value, base + VIC_PL190_VECT_ADDR);
  23         }
  24
  25         for (i = 0; i < 16; i++) {
  26 @@ -82,7 +82,7 @@ void __init vic_init(void __iomem *base,
  27                 writel(VIC_VECT_CNTL_ENABLE | i, reg);
  28         }
  29
  30 -       writel(32, base + VIC_DEF_VECT_ADDR);
  31 +       writel(32, base + VIC_PL190_DEF_VECT_ADDR);
  32
  33         for (i = 0; i < 32; i++) {
  34                 unsigned int irq = irq_start + i;
  35 --- /dev/null
  36 +++ b/arch/arm/configs/gta02-moredrivers-defconfig
  37 @@ -0,0 +1,2107 @@
  38 +#
  39 +# Automatically generated make config: don't edit
  40 +# Linux kernel version: 2.6.28-rc4
  41 +# Mon Dec 29 12:13:48 2008
  42 +#
  43 +CONFIG_ARM=y
  44 +CONFIG_HAVE_PWM=y
  45 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
  46 +CONFIG_GENERIC_GPIO=y
  47 +# CONFIG_GENERIC_TIME is not set
  48 +# CONFIG_GENERIC_CLOCKEVENTS is not set
  49 +CONFIG_MMU=y
  50 +CONFIG_NO_IOPORT=y
  51 +CONFIG_GENERIC_HARDIRQS=y
  52 +CONFIG_STACKTRACE_SUPPORT=y
  53 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
  54 +CONFIG_LOCKDEP_SUPPORT=y
  55 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
  56 +CONFIG_HARDIRQS_SW_RESEND=y
  57 +CONFIG_GENERIC_IRQ_PROBE=y
  58 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
  59 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
  60 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
  61 +CONFIG_GENERIC_HWEIGHT=y
  62 +CONFIG_GENERIC_CALIBRATE_DELAY=y
  63 +CONFIG_FIQ=y
  64 +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
  65 +CONFIG_VECTORS_BASE=0xffff0000
  66 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
  67 +
  68 +#
  69 +# General setup
  70 +#
  71 +CONFIG_EXPERIMENTAL=y
  72 +CONFIG_BROKEN_ON_SMP=y
  73 +CONFIG_LOCK_KERNEL=y
  74 +CONFIG_INIT_ENV_ARG_LIMIT=32
  75 +CONFIG_LOCALVERSION="-mokodev"
  76 +# CONFIG_LOCALVERSION_AUTO is not set
  77 +CONFIG_SWAP=y
  78 +CONFIG_SYSVIPC=y
  79 +CONFIG_SYSVIPC_SYSCTL=y
  80 +# CONFIG_POSIX_MQUEUE is not set
  81 +# CONFIG_BSD_PROCESS_ACCT is not set
  82 +# CONFIG_TASKSTATS is not set
  83 +# CONFIG_AUDIT is not set
  84 +CONFIG_IKCONFIG=y
  85 +CONFIG_IKCONFIG_PROC=y
  86 +CONFIG_LOG_BUF_SHIFT=18
  87 +# CONFIG_CGROUPS is not set
  88 +# CONFIG_GROUP_SCHED is not set
  89 +CONFIG_SYSFS_DEPRECATED=y
  90 +CONFIG_SYSFS_DEPRECATED_V2=y
  91 +# CONFIG_RELAY is not set
  92 +CONFIG_NAMESPACES=y
  93 +# CONFIG_UTS_NS is not set
  94 +# CONFIG_IPC_NS is not set
  95 +# CONFIG_USER_NS is not set
  96 +# CONFIG_PID_NS is not set
  97 +CONFIG_BLK_DEV_INITRD=y
  98 +CONFIG_INITRAMFS_SOURCE=""
  99 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 100 +CONFIG_SYSCTL=y
 101 +# CONFIG_EMBEDDED is not set
 102 +CONFIG_UID16=y
 103 +CONFIG_SYSCTL_SYSCALL=y
 104 +CONFIG_KALLSYMS=y
 105 +CONFIG_KALLSYMS_ALL=y
 106 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
 107 +CONFIG_HOTPLUG=y
 108 +CONFIG_PRINTK=y
 109 +CONFIG_BUG=y
 110 +CONFIG_ELF_CORE=y
 111 +CONFIG_COMPAT_BRK=y
 112 +CONFIG_BASE_FULL=y
 113 +CONFIG_FUTEX=y
 114 +CONFIG_ANON_INODES=y
 115 +CONFIG_EPOLL=y
 116 +CONFIG_SIGNALFD=y
 117 +CONFIG_TIMERFD=y
 118 +CONFIG_EVENTFD=y
 119 +CONFIG_SHMEM=y
 120 +CONFIG_AIO=y
 121 +CONFIG_ASHMEM=y
 122 +CONFIG_VM_EVENT_COUNTERS=y
 123 +CONFIG_SLAB=y
 124 +# CONFIG_SLUB is not set
 125 +# CONFIG_SLOB is not set
 126 +# CONFIG_PROFILING is not set
 127 +CONFIG_MARKERS=y
 128 +CONFIG_HAVE_OPROFILE=y
 129 +# CONFIG_KPROBES is not set
 130 +CONFIG_HAVE_KPROBES=y
 131 +CONFIG_HAVE_KRETPROBES=y
 132 +CONFIG_HAVE_CLK=y
 133 +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 134 +CONFIG_SLABINFO=y
 135 +CONFIG_RT_MUTEXES=y
 136 +# CONFIG_TINY_SHMEM is not set
 137 +CONFIG_BASE_SMALL=0
 138 +CONFIG_MODULES=y
 139 +# CONFIG_MODULE_FORCE_LOAD is not set
 140 +CONFIG_MODULE_UNLOAD=y
 141 +CONFIG_MODULE_FORCE_UNLOAD=y
 142 +# CONFIG_MODVERSIONS is not set
 143 +# CONFIG_MODULE_SRCVERSION_ALL is not set
 144 +CONFIG_KMOD=y
 145 +CONFIG_BLOCK=y
 146 +# CONFIG_LBD is not set
 147 +# CONFIG_BLK_DEV_IO_TRACE is not set
 148 +# CONFIG_LSF is not set
 149 +# CONFIG_BLK_DEV_BSG is not set
 150 +# CONFIG_BLK_DEV_INTEGRITY is not set
 151 +
 152 +#
 153 +# IO Schedulers
 154 +#
 155 +CONFIG_IOSCHED_NOOP=y
 156 +CONFIG_IOSCHED_AS=m
 157 +CONFIG_IOSCHED_DEADLINE=y
 158 +CONFIG_IOSCHED_CFQ=m
 159 +# CONFIG_DEFAULT_AS is not set
 160 +CONFIG_DEFAULT_DEADLINE=y
 161 +# CONFIG_DEFAULT_CFQ is not set
 162 +# CONFIG_DEFAULT_NOOP is not set
 163 +CONFIG_DEFAULT_IOSCHED="deadline"
 164 +CONFIG_CLASSIC_RCU=y
 165 +CONFIG_FREEZER=y
 166 +
 167 +#
 168 +# System Type
 169 +#
 170 +# CONFIG_ARCH_AAEC2000 is not set
 171 +# CONFIG_ARCH_INTEGRATOR is not set
 172 +# CONFIG_ARCH_REALVIEW is not set
 173 +# CONFIG_ARCH_VERSATILE is not set
 174 +# CONFIG_ARCH_AT91 is not set
 175 +# CONFIG_ARCH_CLPS7500 is not set
 176 +# CONFIG_ARCH_CLPS711X is not set
 177 +# CONFIG_ARCH_EBSA110 is not set
 178 +# CONFIG_ARCH_EP93XX is not set
 179 +# CONFIG_ARCH_FOOTBRIDGE is not set
 180 +# CONFIG_ARCH_NETX is not set
 181 +# CONFIG_ARCH_H720X is not set
 182 +# CONFIG_ARCH_IMX is not set
 183 +# CONFIG_ARCH_IOP13XX is not set
 184 +# CONFIG_ARCH_IOP32X is not set
 185 +# CONFIG_ARCH_IOP33X is not set
 186 +# CONFIG_ARCH_IXP23XX is not set
 187 +# CONFIG_ARCH_IXP2000 is not set
 188 +# CONFIG_ARCH_IXP4XX is not set
 189 +# CONFIG_ARCH_L7200 is not set
 190 +# CONFIG_ARCH_KIRKWOOD is not set
 191 +# CONFIG_ARCH_KS8695 is not set
 192 +# CONFIG_ARCH_NS9XXX is not set
 193 +# CONFIG_ARCH_LOKI is not set
 194 +# CONFIG_ARCH_MV78XX0 is not set
 195 +# CONFIG_ARCH_MXC is not set
 196 +# CONFIG_ARCH_ORION5X is not set
 197 +# CONFIG_ARCH_PNX4008 is not set
 198 +# CONFIG_ARCH_PXA is not set
 199 +# CONFIG_ARCH_RPC is not set
 200 +# CONFIG_ARCH_SA1100 is not set
 201 +CONFIG_ARCH_S3C2410=y
 202 +# CONFIG_ARCH_S3C64XX is not set
 203 +# CONFIG_ARCH_SHARK is not set
 204 +# CONFIG_ARCH_LH7A40X is not set
 205 +# CONFIG_ARCH_DAVINCI is not set
 206 +# CONFIG_ARCH_OMAP is not set
 207 +# CONFIG_ARCH_MSM is not set
 208 +CONFIG_PLAT_S3C24XX=y
 209 +CONFIG_S3C2410_CLOCK=y
 210 +CONFIG_CPU_S3C244X=y
 211 +CONFIG_S3C24XX_PWM=y
 212 +CONFIG_S3C2410_DMA=y
 213 +# CONFIG_S3C2410_DMA_DEBUG is not set
 214 +CONFIG_MACH_SMDK=y
 215 +CONFIG_MACH_NEO1973=y
 216 +CONFIG_PLAT_S3C=y
 217 +CONFIG_CPU_LLSERIAL_S3C2410=y
 218 +CONFIG_CPU_LLSERIAL_S3C2440=y
 219 +
 220 +#
 221 +# Boot options
 222 +#
 223 +# CONFIG_S3C_BOOT_WATCHDOG is not set
 224 +# CONFIG_S3C_BOOT_ERROR_RESET is not set
 225 +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
 226 +
 227 +#
 228 +# Power management
 229 +#
 230 +# CONFIG_S3C2410_PM_DEBUG is not set
 231 +# CONFIG_S3C2410_PM_CHECK is not set
 232 +CONFIG_S3C_LOWLEVEL_UART_PORT=2
 233 +CONFIG_S3C_GPIO_SPACE=0
 234 +CONFIG_S3C_GPIO_TRACK=y
 235 +
 236 +#
 237 +# S3C2400 Machines
 238 +#
 239 +CONFIG_CPU_S3C2410=y
 240 +CONFIG_CPU_S3C2410_DMA=y
 241 +CONFIG_S3C2410_PM=y
 242 +CONFIG_S3C2410_GPIO=y
 243 +CONFIG_S3C2410_PWM=y
 244 +
 245 +#
 246 +# S3C2410 Machines
 247 +#
 248 +# CONFIG_ARCH_SMDK2410 is not set
 249 +# CONFIG_ARCH_H1940 is not set
 250 +# CONFIG_MACH_N30 is not set
 251 +# CONFIG_ARCH_BAST is not set
 252 +# CONFIG_MACH_OTOM is not set
 253 +# CONFIG_MACH_AML_M5900 is not set
 254 +# CONFIG_MACH_TCT_HAMMER is not set
 255 +# CONFIG_MACH_VR1000 is not set
 256 +CONFIG_MACH_QT2410=y
 257 +# CONFIG_MACH_NEO1973_GTA01 is not set
 258 +
 259 +#
 260 +# S3C2412 Machines
 261 +#
 262 +# CONFIG_MACH_JIVE is not set
 263 +# CONFIG_MACH_SMDK2413 is not set
 264 +# CONFIG_MACH_SMDK2412 is not set
 265 +# CONFIG_MACH_VSTMS is not set
 266 +CONFIG_CPU_S3C2440=y
 267 +CONFIG_S3C2440_DMA=y
 268 +CONFIG_S3C2440_C_FIQ=y
 269 +
 270 +#
 271 +# S3C2440 Machines
 272 +#
 273 +# CONFIG_MACH_ANUBIS is not set
 274 +# CONFIG_MACH_OSIRIS is not set
 275 +# CONFIG_MACH_RX3715 is not set
 276 +CONFIG_ARCH_S3C2440=y
 277 +# CONFIG_MACH_NEXCODER_2440 is not set
 278 +CONFIG_SMDK2440_CPU2440=y
 279 +# CONFIG_MACH_AT2440EVB is not set
 280 +CONFIG_MACH_NEO1973_GTA02=y
 281 +# CONFIG_NEO1973_GTA02_2440 is not set
 282 +CONFIG_CPU_S3C2442=y
 283 +
 284 +#
 285 +# S3C2442 Machines
 286 +#
 287 +CONFIG_SMDK2440_CPU2442=y
 288 +
 289 +#
 290 +# S3C2443 Machines
 291 +#
 292 +# CONFIG_MACH_SMDK2443 is not set
 293 +
 294 +#
 295 +# Processor Type
 296 +#
 297 +CONFIG_CPU_32=y
 298 +CONFIG_CPU_ARM920T=y
 299 +CONFIG_CPU_32v4T=y
 300 +CONFIG_CPU_ABRT_EV4T=y
 301 +CONFIG_CPU_PABRT_NOIFAR=y
 302 +CONFIG_CPU_CACHE_V4WT=y
 303 +CONFIG_CPU_CACHE_VIVT=y
 304 +CONFIG_CPU_COPY_V4WB=y
 305 +CONFIG_CPU_TLB_V4WBI=y
 306 +CONFIG_CPU_CP15=y
 307 +CONFIG_CPU_CP15_MMU=y
 308 +
 309 +#
 310 +# Processor Features
 311 +#
 312 +CONFIG_ARM_THUMB=y
 313 +# CONFIG_CPU_ICACHE_DISABLE is not set
 314 +# CONFIG_CPU_DCACHE_DISABLE is not set
 315 +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 316 +# CONFIG_OUTER_CACHE is not set
 317 +
 318 +#
 319 +# Bus support
 320 +#
 321 +# CONFIG_PCI_SYSCALL is not set
 322 +# CONFIG_ARCH_SUPPORTS_MSI is not set
 323 +# CONFIG_PCCARD is not set
 324 +
 325 +#
 326 +# Kernel Features
 327 +#
 328 +CONFIG_VMSPLIT_3G=y
 329 +# CONFIG_VMSPLIT_2G is not set
 330 +# CONFIG_VMSPLIT_1G is not set
 331 +CONFIG_PAGE_OFFSET=0xC0000000
 332 +CONFIG_PREEMPT=y
 333 +CONFIG_HZ=200
 334 +CONFIG_AEABI=y
 335 +CONFIG_OABI_COMPAT=y
 336 +CONFIG_ARCH_FLATMEM_HAS_HOLES=y
 337 +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 338 +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 339 +CONFIG_SELECT_MEMORY_MODEL=y
 340 +CONFIG_FLATMEM_MANUAL=y
 341 +# CONFIG_DISCONTIGMEM_MANUAL is not set
 342 +# CONFIG_SPARSEMEM_MANUAL is not set
 343 +CONFIG_FLATMEM=y
 344 +CONFIG_FLAT_NODE_MEM_MAP=y
 345 +CONFIG_PAGEFLAGS_EXTENDED=y
 346 +CONFIG_SPLIT_PTLOCK_CPUS=4096
 347 +# CONFIG_RESOURCES_64BIT is not set
 348 +# CONFIG_PHYS_ADDR_T_64BIT is not set
 349 +CONFIG_ZONE_DMA_FLAG=0
 350 +CONFIG_VIRT_TO_BUS=y
 351 +CONFIG_UNEVICTABLE_LRU=y
 352 +CONFIG_ALIGNMENT_TRAP=y
 353 +
 354 +#
 355 +# Boot options
 356 +#
 357 +CONFIG_ZBOOT_ROM_TEXT=0x0
 358 +CONFIG_ZBOOT_ROM_BSS=0x0
 359 +CONFIG_CMDLINE="unused -- bootloader passes ATAG list"
 360 +# CONFIG_XIP_KERNEL is not set
 361 +CONFIG_KEXEC=y
 362 +CONFIG_ATAGS_PROC=y
 363 +
 364 +#
 365 +# CPU Power Management
 366 +#
 367 +CONFIG_CPU_IDLE=y
 368 +CONFIG_CPU_IDLE_GOV_LADDER=y
 369 +
 370 +#
 371 +# Floating point emulation
 372 +#
 373 +
 374 +#
 375 +# At least one emulation must be selected
 376 +#
 377 +CONFIG_FPE_NWFPE=y
 378 +# CONFIG_FPE_NWFPE_XP is not set
 379 +# CONFIG_FPE_FASTFPE is not set
 380 +
 381 +#
 382 +# Userspace binary formats
 383 +#
 384 +CONFIG_BINFMT_ELF=y
 385 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 386 +CONFIG_HAVE_AOUT=y
 387 +# CONFIG_BINFMT_AOUT is not set
 388 +# CONFIG_BINFMT_MISC is not set
 389 +
 390 +#
 391 +# Power management options
 392 +#
 393 +CONFIG_PM=y
 394 +# CONFIG_PM_DEBUG is not set
 395 +CONFIG_PM_SLEEP=y
 396 +CONFIG_SUSPEND=y
 397 +CONFIG_SUSPEND_FREEZER=y
 398 +CONFIG_APM_EMULATION=y
 399 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
 400 +CONFIG_NET=y
 401 +
 402 +#
 403 +# Networking options
 404 +#
 405 +CONFIG_PACKET=y
 406 +CONFIG_PACKET_MMAP=y
 407 +CONFIG_UNIX=y
 408 +CONFIG_XFRM=y
 409 +# CONFIG_XFRM_USER is not set
 410 +# CONFIG_XFRM_SUB_POLICY is not set
 411 +CONFIG_XFRM_MIGRATE=y
 412 +# CONFIG_XFRM_STATISTICS is not set
 413 +CONFIG_XFRM_IPCOMP=m
 414 +CONFIG_NET_KEY=m
 415 +CONFIG_NET_KEY_MIGRATE=y
 416 +CONFIG_INET=y
 417 +CONFIG_IP_MULTICAST=y
 418 +CONFIG_IP_ADVANCED_ROUTER=y
 419 +CONFIG_ASK_IP_FIB_HASH=y
 420 +# CONFIG_IP_FIB_TRIE is not set
 421 +CONFIG_IP_FIB_HASH=y
 422 +CONFIG_IP_MULTIPLE_TABLES=y
 423 +# CONFIG_IP_ROUTE_MULTIPATH is not set
 424 +# CONFIG_IP_ROUTE_VERBOSE is not set
 425 +CONFIG_IP_PNP=y
 426 +# CONFIG_IP_PNP_DHCP is not set
 427 +# CONFIG_IP_PNP_BOOTP is not set
 428 +# CONFIG_IP_PNP_RARP is not set
 429 +CONFIG_NET_IPIP=m
 430 +CONFIG_NET_IPGRE=m
 431 +# CONFIG_NET_IPGRE_BROADCAST is not set
 432 +# CONFIG_IP_MROUTE is not set
 433 +# CONFIG_ARPD is not set
 434 +CONFIG_SYN_COOKIES=y
 435 +CONFIG_INET_AH=m
 436 +CONFIG_INET_ESP=m
 437 +CONFIG_INET_IPCOMP=m
 438 +CONFIG_INET_XFRM_TUNNEL=m
 439 +CONFIG_INET_TUNNEL=m
 440 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
 441 +CONFIG_INET_XFRM_MODE_TUNNEL=m
 442 +CONFIG_INET_XFRM_MODE_BEET=m
 443 +# CONFIG_INET_LRO is not set
 444 +CONFIG_INET_DIAG=y
 445 +CONFIG_INET_TCP_DIAG=y
 446 +# CONFIG_TCP_CONG_ADVANCED is not set
 447 +CONFIG_TCP_CONG_CUBIC=y
 448 +CONFIG_DEFAULT_TCP_CONG="cubic"
 449 +CONFIG_TCP_MD5SIG=y
 450 +CONFIG_IPV6=m
 451 +# CONFIG_IPV6_PRIVACY is not set
 452 +# CONFIG_IPV6_ROUTER_PREF is not set
 453 +# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 454 +CONFIG_INET6_AH=m
 455 +CONFIG_INET6_ESP=m
 456 +CONFIG_INET6_IPCOMP=m
 457 +# CONFIG_IPV6_MIP6 is not set
 458 +CONFIG_INET6_XFRM_TUNNEL=m
 459 +CONFIG_INET6_TUNNEL=m
 460 +CONFIG_INET6_XFRM_MODE_TRANSPORT=m
 461 +CONFIG_INET6_XFRM_MODE_TUNNEL=m
 462 +CONFIG_INET6_XFRM_MODE_BEET=m
 463 +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
 464 +CONFIG_IPV6_SIT=m
 465 +CONFIG_IPV6_NDISC_NODETYPE=y
 466 +CONFIG_IPV6_TUNNEL=m
 467 +# CONFIG_IPV6_MULTIPLE_TABLES is not set
 468 +# CONFIG_IPV6_MROUTE is not set
 469 +# CONFIG_NETWORK_SECMARK is not set
 470 +CONFIG_NETFILTER=y
 471 +# CONFIG_NETFILTER_DEBUG is not set
 472 +CONFIG_NETFILTER_ADVANCED=y
 473 +CONFIG_BRIDGE_NETFILTER=y
 474 +
 475 +#
 476 +# Core Netfilter Configuration
 477 +#
 478 +CONFIG_NETFILTER_NETLINK=m
 479 +CONFIG_NETFILTER_NETLINK_QUEUE=m
 480 +CONFIG_NETFILTER_NETLINK_LOG=m
 481 +CONFIG_NF_CONNTRACK=y
 482 +# CONFIG_NF_CT_ACCT is not set
 483 +# CONFIG_NF_CONNTRACK_MARK is not set
 484 +# CONFIG_NF_CONNTRACK_EVENTS is not set
 485 +# CONFIG_NF_CT_PROTO_DCCP is not set
 486 +# CONFIG_NF_CT_PROTO_SCTP is not set
 487 +# CONFIG_NF_CT_PROTO_UDPLITE is not set
 488 +# CONFIG_NF_CONNTRACK_AMANDA is not set
 489 +# CONFIG_NF_CONNTRACK_FTP is not set
 490 +# CONFIG_NF_CONNTRACK_H323 is not set
 491 +# CONFIG_NF_CONNTRACK_IRC is not set
 492 +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
 493 +# CONFIG_NF_CONNTRACK_PPTP is not set
 494 +# CONFIG_NF_CONNTRACK_SANE is not set
 495 +# CONFIG_NF_CONNTRACK_SIP is not set
 496 +# CONFIG_NF_CONNTRACK_TFTP is not set
 497 +# CONFIG_NF_CT_NETLINK is not set
 498 +# CONFIG_NETFILTER_TPROXY is not set
 499 +CONFIG_NETFILTER_XTABLES=m
 500 +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 501 +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
 502 +CONFIG_NETFILTER_XT_TARGET_DSCP=m
 503 +CONFIG_NETFILTER_XT_TARGET_MARK=m
 504 +CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 505 +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
 506 +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
 507 +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 508 +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
 509 +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
 510 +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
 511 +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
 512 +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
 513 +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
 514 +CONFIG_NETFILTER_XT_MATCH_DCCP=m
 515 +CONFIG_NETFILTER_XT_MATCH_DSCP=m
 516 +CONFIG_NETFILTER_XT_MATCH_ESP=m
 517 +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 518 +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
 519 +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
 520 +CONFIG_NETFILTER_XT_MATCH_LENGTH=m
 521 +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 522 +CONFIG_NETFILTER_XT_MATCH_MAC=m
 523 +CONFIG_NETFILTER_XT_MATCH_MARK=m
 524 +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
 525 +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
 526 +CONFIG_NETFILTER_XT_MATCH_POLICY=m
 527 +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
 528 +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
 529 +CONFIG_NETFILTER_XT_MATCH_QUOTA=m
 530 +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
 531 +CONFIG_NETFILTER_XT_MATCH_REALM=m
 532 +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
 533 +CONFIG_NETFILTER_XT_MATCH_SCTP=m
 534 +# CONFIG_NETFILTER_XT_MATCH_STATE is not set
 535 +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 536 +CONFIG_NETFILTER_XT_MATCH_STRING=m
 537 +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 538 +# CONFIG_NETFILTER_XT_MATCH_TIME is not set
 539 +# CONFIG_NETFILTER_XT_MATCH_U32 is not set
 540 +# CONFIG_IP_VS is not set
 541 +
 542 +#
 543 +# IP: Netfilter Configuration
 544 +#
 545 +CONFIG_NF_DEFRAG_IPV4=y
 546 +CONFIG_NF_CONNTRACK_IPV4=y
 547 +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
 548 +# CONFIG_IP_NF_QUEUE is not set
 549 +CONFIG_IP_NF_IPTABLES=m
 550 +CONFIG_IP_NF_MATCH_ADDRTYPE=m
 551 +CONFIG_IP_NF_MATCH_AH=m
 552 +CONFIG_IP_NF_MATCH_ECN=m
 553 +CONFIG_IP_NF_MATCH_TTL=m
 554 +CONFIG_IP_NF_FILTER=m
 555 +CONFIG_IP_NF_TARGET_REJECT=m
 556 +CONFIG_IP_NF_TARGET_LOG=m
 557 +CONFIG_IP_NF_TARGET_ULOG=m
 558 +CONFIG_NF_NAT=m
 559 +CONFIG_NF_NAT_NEEDED=y
 560 +CONFIG_IP_NF_TARGET_MASQUERADE=m
 561 +# CONFIG_IP_NF_TARGET_NETMAP is not set
 562 +# CONFIG_IP_NF_TARGET_REDIRECT is not set
 563 +# CONFIG_NF_NAT_SNMP_BASIC is not set
 564 +# CONFIG_NF_NAT_FTP is not set
 565 +# CONFIG_NF_NAT_IRC is not set
 566 +# CONFIG_NF_NAT_TFTP is not set
 567 +# CONFIG_NF_NAT_AMANDA is not set
 568 +# CONFIG_NF_NAT_PPTP is not set
 569 +# CONFIG_NF_NAT_H323 is not set
 570 +# CONFIG_NF_NAT_SIP is not set
 571 +CONFIG_IP_NF_MANGLE=m
 572 +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
 573 +CONFIG_IP_NF_TARGET_ECN=m
 574 +CONFIG_IP_NF_TARGET_TTL=m
 575 +# CONFIG_IP_NF_RAW is not set
 576 +# CONFIG_IP_NF_ARPTABLES is not set
 577 +
 578 +#
 579 +# IPv6: Netfilter Configuration
 580 +#
 581 +CONFIG_NF_CONNTRACK_IPV6=m
 582 +# CONFIG_IP6_NF_QUEUE is not set
 583 +CONFIG_IP6_NF_IPTABLES=m
 584 +CONFIG_IP6_NF_MATCH_AH=m
 585 +CONFIG_IP6_NF_MATCH_EUI64=m
 586 +CONFIG_IP6_NF_MATCH_FRAG=m
 587 +CONFIG_IP6_NF_MATCH_OPTS=m
 588 +CONFIG_IP6_NF_MATCH_HL=m
 589 +CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 590 +CONFIG_IP6_NF_MATCH_MH=m
 591 +CONFIG_IP6_NF_MATCH_RT=m
 592 +CONFIG_IP6_NF_TARGET_LOG=m
 593 +CONFIG_IP6_NF_FILTER=m
 594 +CONFIG_IP6_NF_TARGET_REJECT=m
 595 +CONFIG_IP6_NF_MANGLE=m
 596 +CONFIG_IP6_NF_TARGET_HL=m
 597 +# CONFIG_IP6_NF_RAW is not set
 598 +CONFIG_BRIDGE_NF_EBTABLES=m
 599 +CONFIG_BRIDGE_EBT_BROUTE=m
 600 +CONFIG_BRIDGE_EBT_T_FILTER=m
 601 +CONFIG_BRIDGE_EBT_T_NAT=m
 602 +CONFIG_BRIDGE_EBT_802_3=m
 603 +CONFIG_BRIDGE_EBT_AMONG=m
 604 +CONFIG_BRIDGE_EBT_ARP=m
 605 +CONFIG_BRIDGE_EBT_IP=m
 606 +# CONFIG_BRIDGE_EBT_IP6 is not set
 607 +CONFIG_BRIDGE_EBT_LIMIT=m
 608 +CONFIG_BRIDGE_EBT_MARK=m
 609 +CONFIG_BRIDGE_EBT_PKTTYPE=m
 610 +CONFIG_BRIDGE_EBT_STP=m
 611 +CONFIG_BRIDGE_EBT_VLAN=m
 612 +CONFIG_BRIDGE_EBT_ARPREPLY=m
 613 +CONFIG_BRIDGE_EBT_DNAT=m
 614 +CONFIG_BRIDGE_EBT_MARK_T=m
 615 +CONFIG_BRIDGE_EBT_REDIRECT=m
 616 +CONFIG_BRIDGE_EBT_SNAT=m
 617 +CONFIG_BRIDGE_EBT_LOG=m
 618 +CONFIG_BRIDGE_EBT_ULOG=m
 619 +# CONFIG_BRIDGE_EBT_NFLOG is not set
 620 +# CONFIG_IP_DCCP is not set
 621 +# CONFIG_IP_SCTP is not set
 622 +# CONFIG_TIPC is not set
 623 +# CONFIG_ATM is not set
 624 +CONFIG_STP=y
 625 +CONFIG_BRIDGE=y
 626 +# CONFIG_NET_DSA is not set
 627 +# CONFIG_VLAN_8021Q is not set
 628 +# CONFIG_DECNET is not set
 629 +CONFIG_LLC=y
 630 +# CONFIG_LLC2 is not set
 631 +# CONFIG_IPX is not set
 632 +# CONFIG_ATALK is not set
 633 +# CONFIG_X25 is not set
 634 +# CONFIG_LAPB is not set
 635 +# CONFIG_ECONET is not set
 636 +# CONFIG_WAN_ROUTER is not set
 637 +CONFIG_NET_SCHED=y
 638 +
 639 +#
 640 +# Queueing/Scheduling
 641 +#
 642 +CONFIG_NET_SCH_CBQ=m
 643 +CONFIG_NET_SCH_HTB=m
 644 +CONFIG_NET_SCH_HFSC=m
 645 +CONFIG_NET_SCH_PRIO=m
 646 +# CONFIG_NET_SCH_MULTIQ is not set
 647 +CONFIG_NET_SCH_RED=m
 648 +CONFIG_NET_SCH_SFQ=m
 649 +CONFIG_NET_SCH_TEQL=m
 650 +CONFIG_NET_SCH_TBF=m
 651 +CONFIG_NET_SCH_GRED=m
 652 +CONFIG_NET_SCH_DSMARK=m
 653 +CONFIG_NET_SCH_NETEM=m
 654 +
 655 +#
 656 +# Classification
 657 +#
 658 +CONFIG_NET_CLS=y
 659 +CONFIG_NET_CLS_BASIC=m
 660 +CONFIG_NET_CLS_TCINDEX=m
 661 +CONFIG_NET_CLS_ROUTE4=m
 662 +CONFIG_NET_CLS_ROUTE=y
 663 +CONFIG_NET_CLS_FW=m
 664 +CONFIG_NET_CLS_U32=m
 665 +CONFIG_CLS_U32_PERF=y
 666 +CONFIG_CLS_U32_MARK=y
 667 +CONFIG_NET_CLS_RSVP=m
 668 +CONFIG_NET_CLS_RSVP6=m
 669 +# CONFIG_NET_CLS_FLOW is not set
 670 +# CONFIG_NET_EMATCH is not set
 671 +# CONFIG_NET_CLS_ACT is not set
 672 +# CONFIG_NET_CLS_IND is not set
 673 +CONFIG_NET_SCH_FIFO=y
 674 +
 675 +#
 676 +# Network testing
 677 +#
 678 +# CONFIG_NET_PKTGEN is not set
 679 +# CONFIG_HAMRADIO is not set
 680 +# CONFIG_CAN is not set
 681 +# CONFIG_IRDA is not set
 682 +CONFIG_BT=y
 683 +CONFIG_BT_L2CAP=y
 684 +CONFIG_BT_SCO=y
 685 +CONFIG_BT_RFCOMM=y
 686 +CONFIG_BT_RFCOMM_TTY=y
 687 +CONFIG_BT_BNEP=y
 688 +CONFIG_BT_BNEP_MC_FILTER=y
 689 +CONFIG_BT_BNEP_PROTO_FILTER=y
 690 +CONFIG_BT_HIDP=y
 691 +
 692 +#
 693 +# Bluetooth device drivers
 694 +#
 695 +CONFIG_BT_HCIBTUSB=y
 696 +# CONFIG_BT_HCIBTSDIO is not set
 697 +# CONFIG_BT_HCIUART is not set
 698 +# CONFIG_BT_HCIBCM203X is not set
 699 +# CONFIG_BT_HCIBPA10X is not set
 700 +# CONFIG_BT_HCIBFUSB is not set
 701 +# CONFIG_BT_HCIVHCI is not set
 702 +# CONFIG_AF_RXRPC is not set
 703 +# CONFIG_PHONET is not set
 704 +CONFIG_FIB_RULES=y
 705 +CONFIG_WIRELESS=y
 706 +# CONFIG_CFG80211 is not set
 707 +# CONFIG_WIRELESS_OLD_REGULATORY is not set
 708 +CONFIG_WIRELESS_EXT=y
 709 +CONFIG_WIRELESS_EXT_SYSFS=y
 710 +# CONFIG_MAC80211 is not set
 711 +# CONFIG_IEEE80211 is not set
 712 +CONFIG_RFKILL=y
 713 +CONFIG_RFKILL_INPUT=y
 714 +CONFIG_RFKILL_LEDS=y
 715 +# CONFIG_NET_9P is not set
 716 +
 717 +#
 718 +# Device Drivers
 719 +#
 720 +
 721 +#
 722 +# Generic Driver Options
 723 +#
 724 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 725 +CONFIG_STANDALONE=y
 726 +CONFIG_PREVENT_FIRMWARE_BUILD=y
 727 +CONFIG_FW_LOADER=y
 728 +# CONFIG_FIRMWARE_IN_KERNEL is not set
 729 +CONFIG_EXTRA_FIRMWARE=""
 730 +# CONFIG_DEBUG_DRIVER is not set
 731 +# CONFIG_DEBUG_DEVRES is not set
 732 +# CONFIG_SYS_HYPERVISOR is not set
 733 +CONFIG_CONNECTOR=m
 734 +CONFIG_MTD=y
 735 +# CONFIG_MTD_DEBUG is not set
 736 +CONFIG_MTD_CONCAT=y
 737 +CONFIG_MTD_PARTITIONS=y
 738 +# CONFIG_MTD_REDBOOT_PARTS is not set
 739 +CONFIG_MTD_CMDLINE_PARTS=y
 740 +# CONFIG_MTD_AFS_PARTS is not set
 741 +# CONFIG_MTD_AR7_PARTS is not set
 742 +
 743 +#
 744 +# User Modules And Translation Layers
 745 +#
 746 +CONFIG_MTD_CHAR=y
 747 +CONFIG_MTD_BLKDEVS=y
 748 +CONFIG_MTD_BLOCK=y
 749 +# CONFIG_FTL is not set
 750 +# CONFIG_NFTL is not set
 751 +# CONFIG_INFTL is not set
 752 +# CONFIG_RFD_FTL is not set
 753 +# CONFIG_SSFDC is not set
 754 +# CONFIG_MTD_OOPS is not set
 755 +
 756 +#
 757 +# RAM/ROM/Flash chip drivers
 758 +#
 759 +CONFIG_MTD_CFI=y
 760 +# CONFIG_MTD_JEDECPROBE is not set
 761 +CONFIG_MTD_GEN_PROBE=y
 762 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
 763 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
 764 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
 765 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
 766 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
 767 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
 768 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
 769 +CONFIG_MTD_CFI_I1=y
 770 +CONFIG_MTD_CFI_I2=y
 771 +# CONFIG_MTD_CFI_I4 is not set
 772 +# CONFIG_MTD_CFI_I8 is not set
 773 +CONFIG_MTD_CFI_INTELEXT=y
 774 +# CONFIG_MTD_CFI_AMDSTD is not set
 775 +# CONFIG_MTD_CFI_STAA is not set
 776 +CONFIG_MTD_CFI_UTIL=y
 777 +# CONFIG_MTD_RAM is not set
 778 +CONFIG_MTD_ROM=y
 779 +CONFIG_MTD_ABSENT=y
 780 +
 781 +#
 782 +# Mapping drivers for chip access
 783 +#
 784 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
 785 +CONFIG_MTD_PHYSMAP=y
 786 +CONFIG_MTD_PHYSMAP_START=0x0
 787 +CONFIG_MTD_PHYSMAP_LEN=0
 788 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 789 +# CONFIG_MTD_ARM_INTEGRATOR is not set
 790 +# CONFIG_MTD_PLATRAM is not set
 791 +
 792 +#
 793 +# Self-contained MTD device drivers
 794 +#
 795 +# CONFIG_MTD_DATAFLASH is not set
 796 +# CONFIG_MTD_M25P80 is not set
 797 +# CONFIG_MTD_SLRAM is not set
 798 +# CONFIG_MTD_PHRAM is not set
 799 +# CONFIG_MTD_MTDRAM is not set
 800 +# CONFIG_MTD_BLOCK2MTD is not set
 801 +
 802 +#
 803 +# Disk-On-Chip Device Drivers
 804 +#
 805 +# CONFIG_MTD_DOC2000 is not set
 806 +# CONFIG_MTD_DOC2001 is not set
 807 +# CONFIG_MTD_DOC2001PLUS is not set
 808 +CONFIG_MTD_NAND=y
 809 +CONFIG_MTD_NAND_VERIFY_WRITE=y
 810 +# CONFIG_MTD_NAND_ECC_SMC is not set
 811 +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 812 +# CONFIG_MTD_NAND_GPIO is not set
 813 +CONFIG_MTD_NAND_IDS=y
 814 +CONFIG_MTD_NAND_S3C2410=y
 815 +CONFIG_MTD_NAND_S3C2410_DEBUG=y
 816 +CONFIG_MTD_NAND_S3C2410_HWECC=y
 817 +# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
 818 +# CONFIG_MTD_NAND_DISKONCHIP is not set
 819 +# CONFIG_MTD_NAND_NANDSIM is not set
 820 +# CONFIG_MTD_NAND_PLATFORM is not set
 821 +# CONFIG_MTD_ALAUDA is not set
 822 +# CONFIG_MTD_ONENAND is not set
 823 +
 824 +#
 825 +# UBI - Unsorted block images
 826 +#
 827 +# CONFIG_MTD_UBI is not set
 828 +# CONFIG_PARPORT is not set
 829 +CONFIG_BLK_DEV=y
 830 +# CONFIG_BLK_DEV_COW_COMMON is not set
 831 +CONFIG_BLK_DEV_LOOP=m
 832 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
 833 +# CONFIG_BLK_DEV_NBD is not set
 834 +CONFIG_BLK_DEV_UB=m
 835 +CONFIG_BLK_DEV_RAM=y
 836 +CONFIG_BLK_DEV_RAM_COUNT=16
 837 +CONFIG_BLK_DEV_RAM_SIZE=4096
 838 +# CONFIG_BLK_DEV_XIP is not set
 839 +# CONFIG_CDROM_PKTCDVD is not set
 840 +# CONFIG_ATA_OVER_ETH is not set
 841 +CONFIG_MISC_DEVICES=y
 842 +# CONFIG_EEPROM_93CX6 is not set
 843 +CONFIG_LOW_MEMORY_KILLER=y
 844 +# CONFIG_ENCLOSURE_SERVICES is not set
 845 +CONFIG_HAVE_IDE=y
 846 +# CONFIG_IDE is not set
 847 +
 848 +#
 849 +# SCSI device support
 850 +#
 851 +# CONFIG_RAID_ATTRS is not set
 852 +CONFIG_SCSI=y
 853 +CONFIG_SCSI_DMA=y
 854 +# CONFIG_SCSI_TGT is not set
 855 +# CONFIG_SCSI_NETLINK is not set
 856 +CONFIG_SCSI_PROC_FS=y
 857 +
 858 +#
 859 +# SCSI support type (disk, tape, CD-ROM)
 860 +#
 861 +CONFIG_BLK_DEV_SD=y
 862 +# CONFIG_CHR_DEV_ST is not set
 863 +# CONFIG_CHR_DEV_OSST is not set
 864 +CONFIG_BLK_DEV_SR=y
 865 +# CONFIG_BLK_DEV_SR_VENDOR is not set
 866 +CONFIG_CHR_DEV_SG=y
 867 +# CONFIG_CHR_DEV_SCH is not set
 868 +
 869 +#
 870 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 871 +#
 872 +CONFIG_SCSI_MULTI_LUN=y
 873 +# CONFIG_SCSI_CONSTANTS is not set
 874 +# CONFIG_SCSI_LOGGING is not set
 875 +CONFIG_SCSI_SCAN_ASYNC=y
 876 +CONFIG_SCSI_WAIT_SCAN=m
 877 +
 878 +#
 879 +# SCSI Transports
 880 +#
 881 +# CONFIG_SCSI_SPI_ATTRS is not set
 882 +# CONFIG_SCSI_FC_ATTRS is not set
 883 +# CONFIG_SCSI_ISCSI_ATTRS is not set
 884 +# CONFIG_SCSI_SAS_LIBSAS is not set
 885 +# CONFIG_SCSI_SRP_ATTRS is not set
 886 +CONFIG_SCSI_LOWLEVEL=y
 887 +# CONFIG_ISCSI_TCP is not set
 888 +# CONFIG_SCSI_DEBUG is not set
 889 +# CONFIG_SCSI_DH is not set
 890 +# CONFIG_ATA is not set
 891 +CONFIG_MD=y
 892 +# CONFIG_BLK_DEV_MD is not set
 893 +CONFIG_BLK_DEV_DM=m
 894 +# CONFIG_DM_DEBUG is not set
 895 +CONFIG_DM_CRYPT=m
 896 +CONFIG_DM_SNAPSHOT=m
 897 +# CONFIG_DM_MIRROR is not set
 898 +# CONFIG_DM_ZERO is not set
 899 +# CONFIG_DM_MULTIPATH is not set
 900 +# CONFIG_DM_DELAY is not set
 901 +# CONFIG_DM_UEVENT is not set
 902 +CONFIG_NETDEVICES=y
 903 +# CONFIG_DUMMY is not set
 904 +# CONFIG_BONDING is not set
 905 +# CONFIG_MACVLAN is not set
 906 +# CONFIG_EQUALIZER is not set
 907 +CONFIG_TUN=y
 908 +# CONFIG_VETH is not set
 909 +# CONFIG_PHYLIB is not set
 910 +CONFIG_NET_ETHERNET=y
 911 +CONFIG_MII=y
 912 +# CONFIG_AX88796 is not set
 913 +# CONFIG_SMC91X is not set
 914 +# CONFIG_DM9000 is not set
 915 +# CONFIG_ENC28J60 is not set
 916 +# CONFIG_SMC911X is not set
 917 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
 918 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
 919 +# CONFIG_IBM_NEW_EMAC_TAH is not set
 920 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 921 +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
 922 +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 923 +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 924 +# CONFIG_B44 is not set
 925 +# CONFIG_NETDEV_1000 is not set
 926 +# CONFIG_NETDEV_10000 is not set
 927 +
 928 +#
 929 +# Wireless LAN
 930 +#
 931 +# CONFIG_WLAN_PRE80211 is not set
 932 +# CONFIG_WLAN_80211 is not set
 933 +# CONFIG_IWLWIFI_LEDS is not set
 934 +
 935 +#
 936 +# USB Network Adapters
 937 +#
 938 +CONFIG_USB_CATC=m
 939 +CONFIG_USB_KAWETH=m
 940 +CONFIG_USB_PEGASUS=m
 941 +CONFIG_USB_RTL8150=m
 942 +CONFIG_USB_USBNET=y
 943 +CONFIG_USB_NET_AX8817X=m
 944 +CONFIG_USB_NET_CDCETHER=y
 945 +CONFIG_USB_NET_DM9601=m
 946 +# CONFIG_USB_NET_SMSC95XX is not set
 947 +CONFIG_USB_NET_GL620A=m
 948 +CONFIG_USB_NET_NET1080=m
 949 +CONFIG_USB_NET_PLUSB=m
 950 +CONFIG_USB_NET_MCS7830=m
 951 +CONFIG_USB_NET_RNDIS_HOST=y
 952 +CONFIG_USB_NET_CDC_SUBSET=m
 953 +CONFIG_USB_ALI_M5632=y
 954 +CONFIG_USB_AN2720=y
 955 +CONFIG_USB_BELKIN=y
 956 +CONFIG_USB_ARMLINUX=y
 957 +CONFIG_USB_EPSON2888=y
 958 +CONFIG_USB_KC2190=y
 959 +CONFIG_USB_NET_ZAURUS=m
 960 +# CONFIG_USB_HSO is not set
 961 +# CONFIG_WAN is not set
 962 +CONFIG_PPP=y
 963 +CONFIG_PPP_MULTILINK=y
 964 +CONFIG_PPP_FILTER=y
 965 +CONFIG_PPP_ASYNC=y
 966 +CONFIG_PPP_SYNC_TTY=y
 967 +CONFIG_PPP_DEFLATE=y
 968 +CONFIG_PPP_BSDCOMP=y
 969 +CONFIG_PPP_MPPE=y
 970 +# CONFIG_PPPOE is not set
 971 +# CONFIG_PPPOL2TP is not set
 972 +# CONFIG_SLIP is not set
 973 +CONFIG_SLHC=y
 974 +# CONFIG_NETCONSOLE is not set
 975 +# CONFIG_NETPOLL is not set
 976 +# CONFIG_NET_POLL_CONTROLLER is not set
 977 +# CONFIG_ISDN is not set
 978 +
 979 +#
 980 +# Input device support
 981 +#
 982 +CONFIG_INPUT=y
 983 +# CONFIG_INPUT_FF_MEMLESS is not set
 984 +# CONFIG_INPUT_POLLDEV is not set
 985 +
 986 +#
 987 +# Userland interfaces
 988 +#
 989 +CONFIG_INPUT_MOUSEDEV=y
 990 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 991 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
 992 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=640
 993 +# CONFIG_INPUT_JOYDEV is not set
 994 +CONFIG_INPUT_EVDEV=y
 995 +# CONFIG_INPUT_EVBUG is not set
 996 +
 997 +#
 998 +# Input Device Drivers
 999 +#
1000 +CONFIG_INPUT_KEYBOARD=y
1001 +# CONFIG_KEYBOARD_ATKBD is not set
1002 +# CONFIG_KEYBOARD_SUNKBD is not set
1003 +# CONFIG_KEYBOARD_LKKBD is not set
1004 +# CONFIG_KEYBOARD_XTKBD is not set
1005 +# CONFIG_KEYBOARD_NEWTON is not set
1006 +CONFIG_KEYBOARD_STOWAWAY=m
1007 +CONFIG_KEYBOARD_GPIO=m
1008 +CONFIG_KEYBOARD_NEO1973=y
1009 +CONFIG_KEYBOARD_QT2410=y
1010 +CONFIG_INPUT_MOUSE=y
1011 +# CONFIG_MOUSE_PS2 is not set
1012 +# CONFIG_MOUSE_SERIAL is not set
1013 +# CONFIG_MOUSE_APPLETOUCH is not set
1014 +# CONFIG_MOUSE_BCM5974 is not set
1015 +# CONFIG_MOUSE_VSXXXAA is not set
1016 +# CONFIG_MOUSE_GPIO is not set
1017 +# CONFIG_INPUT_JOYSTICK is not set
1018 +# CONFIG_INPUT_TABLET is not set
1019 +CONFIG_INPUT_TOUCHSCREEN=y
1020 +CONFIG_TOUCHSCREEN_FILTER=y
1021 +CONFIG_TOUCHSCREEN_FILTER_GROUP=y
1022 +CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y
1023 +CONFIG_TOUCHSCREEN_FILTER_MEAN=y
1024 +CONFIG_TOUCHSCREEN_FILTER_LINEAR=y
1025 +# CONFIG_TOUCHSCREEN_ADS7846 is not set
1026 +# CONFIG_TOUCHSCREEN_FUJITSU is not set
1027 +CONFIG_TOUCHSCREEN_S3C2410=y
1028 +# CONFIG_TOUCHSCREEN_S3C2410_DEBUG is not set
1029 +# CONFIG_TOUCHSCREEN_GUNZE is not set
1030 +# CONFIG_TOUCHSCREEN_ELO is not set
1031 +# CONFIG_TOUCHSCREEN_MTOUCH is not set
1032 +# CONFIG_TOUCHSCREEN_INEXIO is not set
1033 +# CONFIG_TOUCHSCREEN_MK712 is not set
1034 +# CONFIG_TOUCHSCREEN_PENMOUNT is not set
1035 +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
1036 +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
1037 +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
1038 +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
1039 +# CONFIG_TOUCHSCREEN_PCAP7200 is not set
1040 +CONFIG_INPUT_MISC=y
1041 +# CONFIG_INPUT_ATI_REMOTE is not set
1042 +# CONFIG_INPUT_ATI_REMOTE2 is not set
1043 +# CONFIG_INPUT_KEYSPAN_REMOTE is not set
1044 +# CONFIG_INPUT_POWERMATE is not set
1045 +# CONFIG_INPUT_YEALINK is not set
1046 +# CONFIG_INPUT_CM109 is not set
1047 +CONFIG_INPUT_UINPUT=m
1048 +CONFIG_INPUT_LIS302DL=y
1049 +CONFIG_INPUT_PCF50633_PMU=y
1050 +
1051 +#
1052 +# Hardware I/O ports
1053 +#
1054 +CONFIG_SERIO=y
1055 +# CONFIG_SERIO_SERPORT is not set
1056 +# CONFIG_SERIO_RAW is not set
1057 +# CONFIG_GAMEPORT is not set
1058 +
1059 +#
1060 +# Character devices
1061 +#
1062 +CONFIG_VT=y
1063 +CONFIG_CONSOLE_TRANSLATIONS=y
1064 +CONFIG_VT_CONSOLE=y
1065 +CONFIG_NR_TTY_DEVICES=6
1066 +CONFIG_HW_CONSOLE=y
1067 +CONFIG_VT_HW_CONSOLE_BINDING=y
1068 +# CONFIG_DEVKMEM is not set
1069 +# CONFIG_SERIAL_NONSTANDARD is not set
1070 +
1071 +#
1072 +# Serial drivers
1073 +#
1074 +# CONFIG_SERIAL_8250 is not set
1075 +
1076 +#
1077 +# Non-8250 serial port support
1078 +#
1079 +CONFIG_SERIAL_SAMSUNG=y
1080 +CONFIG_SERIAL_SAMSUNG_UARTS=3
1081 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y
1082 +CONFIG_SERIAL_S3C2410=y
1083 +CONFIG_SERIAL_S3C2440=y
1084 +CONFIG_SERIAL_CORE=y
1085 +CONFIG_SERIAL_CORE_CONSOLE=y
1086 +CONFIG_UNIX98_PTYS=y
1087 +# CONFIG_LEGACY_PTYS is not set
1088 +# CONFIG_IPMI_HANDLER is not set
1089 +# CONFIG_HW_RANDOM is not set
1090 +# CONFIG_NVRAM is not set
1091 +# CONFIG_R3964 is not set
1092 +# CONFIG_RAW_DRIVER is not set
1093 +# CONFIG_TCG_TPM is not set
1094 +CONFIG_I2C=y
1095 +CONFIG_I2C_BOARDINFO=y
1096 +CONFIG_I2C_CHARDEV=y
1097 +CONFIG_I2C_HELPER_AUTO=y
1098 +
1099 +#
1100 +# I2C Hardware Bus support
1101 +#
1102 +
1103 +#
1104 +# I2C system bus drivers (mostly embedded / system-on-chip)
1105 +#
1106 +# CONFIG_I2C_GPIO is not set
1107 +# CONFIG_I2C_OCORES is not set
1108 +CONFIG_I2C_S3C2410=y
1109 +# CONFIG_I2C_SIMTEC is not set
1110 +
1111 +#
1112 +# External I2C/SMBus adapter drivers
1113 +#
1114 +# CONFIG_I2C_PARPORT_LIGHT is not set
1115 +# CONFIG_I2C_TAOS_EVM is not set
1116 +# CONFIG_I2C_TINY_USB is not set
1117 +
1118 +#
1119 +# Other I2C/SMBus bus drivers
1120 +#
1121 +# CONFIG_I2C_PCA_PLATFORM is not set
1122 +# CONFIG_I2C_STUB is not set
1123 +
1124 +#
1125 +# Miscellaneous I2C Chip support
1126 +#
1127 +# CONFIG_DS1682 is not set
1128 +# CONFIG_AT24 is not set
1129 +# CONFIG_SENSORS_EEPROM is not set
1130 +# CONFIG_SENSORS_PCF50606 is not set
1131 +# CONFIG_SENSORS_PCF50633 is not set
1132 +# CONFIG_SENSORS_PCF8574 is not set
1133 +# CONFIG_PCF8575 is not set
1134 +# CONFIG_SENSORS_PCA9539 is not set
1135 +# CONFIG_SENSORS_PCF8591 is not set
1136 +# CONFIG_TPS65010 is not set
1137 +# CONFIG_SENSORS_MAX6875 is not set
1138 +# CONFIG_SENSORS_TSL2550 is not set
1139 +# CONFIG_SENSORS_TSL256X is not set
1140 +CONFIG_PCA9632=y
1141 +# CONFIG_I2C_DEBUG_CORE is not set
1142 +# CONFIG_I2C_DEBUG_ALGO is not set
1143 +# CONFIG_I2C_DEBUG_BUS is not set
1144 +# CONFIG_I2C_DEBUG_CHIP is not set
1145 +CONFIG_SPI=y
1146 +# CONFIG_SPI_DEBUG is not set
1147 +CONFIG_SPI_MASTER=y
1148 +
1149 +#
1150 +# SPI Master Controller Drivers
1151 +#
1152 +CONFIG_SPI_BITBANG=y
1153 +# CONFIG_SPI_S3C24XX is not set
1154 +CONFIG_SPI_S3C24XX_GPIO=y
1155 +
1156 +#
1157 +# SPI Protocol Masters
1158 +#
1159 +# CONFIG_SPI_AT25 is not set
1160 +# CONFIG_SPI_SPIDEV is not set
1161 +# CONFIG_SPI_TLE62X0 is not set
1162 +CONFIG_ARCH_REQUIRE_GPIOLIB=y
1163 +CONFIG_GPIOLIB=y
1164 +CONFIG_DEBUG_GPIO=y
1165 +CONFIG_GPIO_SYSFS=y
1166 +
1167 +#
1168 +# I2C GPIO expanders:
1169 +#
1170 +# CONFIG_GPIO_MAX732X is not set
1171 +# CONFIG_GPIO_PCA953X is not set
1172 +# CONFIG_GPIO_PCF857X is not set
1173 +
1174 +#
1175 +# PCI GPIO expanders:
1176 +#
1177 +
1178 +#
1179 +# SPI GPIO expanders:
1180 +#
1181 +# CONFIG_GPIO_MAX7301 is not set
1182 +# CONFIG_GPIO_MCP23S08 is not set
1183 +# CONFIG_W1 is not set
1184 +CONFIG_POWER_SUPPLY=y
1185 +CONFIG_POWER_SUPPLY_DEBUG=y
1186 +CONFIG_PDA_POWER=y
1187 +CONFIG_APM_POWER=y
1188 +# CONFIG_BATTERY_DS2760 is not set
1189 +# CONFIG_BATTERY_BQ27x00 is not set
1190 +CONFIG_BATTERY_BQ27000_HDQ=y
1191 +CONFIG_GTA02_HDQ=y
1192 +CONFIG_CHARGER_PCF50633=y
1193 +CONFIG_HWMON=y
1194 +# CONFIG_HWMON_VID is not set
1195 +# CONFIG_SENSORS_AD7414 is not set
1196 +# CONFIG_SENSORS_AD7418 is not set
1197 +# CONFIG_SENSORS_ADCXX is not set
1198 +# CONFIG_SENSORS_ADM1021 is not set
1199 +# CONFIG_SENSORS_ADM1025 is not set
1200 +# CONFIG_SENSORS_ADM1026 is not set
1201 +# CONFIG_SENSORS_ADM1029 is not set
1202 +# CONFIG_SENSORS_ADM1031 is not set
1203 +# CONFIG_SENSORS_ADM9240 is not set
1204 +# CONFIG_SENSORS_ADT7470 is not set
1205 +# CONFIG_SENSORS_ADT7473 is not set
1206 +# CONFIG_SENSORS_ATXP1 is not set
1207 +# CONFIG_SENSORS_DS1621 is not set
1208 +# CONFIG_SENSORS_F71805F is not set
1209 +# CONFIG_SENSORS_F71882FG is not set
1210 +# CONFIG_SENSORS_F75375S is not set
1211 +# CONFIG_SENSORS_GL518SM is not set
1212 +# CONFIG_SENSORS_GL520SM is not set
1213 +# CONFIG_SENSORS_IT87 is not set
1214 +# CONFIG_SENSORS_LM63 is not set
1215 +# CONFIG_SENSORS_LM70 is not set
1216 +# CONFIG_SENSORS_LM75 is not set
1217 +# CONFIG_SENSORS_LM77 is not set
1218 +# CONFIG_SENSORS_LM78 is not set
1219 +# CONFIG_SENSORS_LM80 is not set
1220 +# CONFIG_SENSORS_LM83 is not set
1221 +# CONFIG_SENSORS_LM85 is not set
1222 +# CONFIG_SENSORS_LM87 is not set
1223 +# CONFIG_SENSORS_LM90 is not set
1224 +# CONFIG_SENSORS_LM92 is not set
1225 +# CONFIG_SENSORS_LM93 is not set
1226 +# CONFIG_SENSORS_MAX1111 is not set
1227 +# CONFIG_SENSORS_MAX1619 is not set
1228 +# CONFIG_SENSORS_MAX6650 is not set
1229 +# CONFIG_SENSORS_PC87360 is not set
1230 +# CONFIG_SENSORS_PC87427 is not set
1231 +# CONFIG_SENSORS_DME1737 is not set
1232 +# CONFIG_SENSORS_SMSC47M1 is not set
1233 +# CONFIG_SENSORS_SMSC47M192 is not set
1234 +# CONFIG_SENSORS_SMSC47B397 is not set
1235 +# CONFIG_SENSORS_ADS7828 is not set
1236 +# CONFIG_SENSORS_THMC50 is not set
1237 +# CONFIG_SENSORS_VT1211 is not set
1238 +# CONFIG_SENSORS_W83781D is not set
1239 +# CONFIG_SENSORS_W83791D is not set
1240 +# CONFIG_SENSORS_W83792D is not set
1241 +# CONFIG_SENSORS_W83793 is not set
1242 +# CONFIG_SENSORS_W83L785TS is not set
1243 +# CONFIG_SENSORS_W83L786NG is not set
1244 +# CONFIG_SENSORS_W83627HF is not set
1245 +# CONFIG_SENSORS_W83627EHF is not set
1246 +# CONFIG_HWMON_DEBUG_CHIP is not set
1247 +# CONFIG_THERMAL is not set
1248 +# CONFIG_THERMAL_HWMON is not set
1249 +CONFIG_WATCHDOG=y
1250 +# CONFIG_WATCHDOG_NOWAYOUT is not set
1251 +
1252 +#
1253 +# Watchdog Device Drivers
1254 +#
1255 +# CONFIG_SOFT_WATCHDOG is not set
1256 +CONFIG_S3C2410_WATCHDOG=m
1257 +
1258 +#
1259 +# USB-based Watchdog Cards
1260 +#
1261 +# CONFIG_USBPCWATCHDOG is not set
1262 +
1263 +#
1264 +# Sonics Silicon Backplane
1265 +#
1266 +CONFIG_SSB_POSSIBLE=y
1267 +# CONFIG_SSB is not set
1268 +
1269 +#
1270 +# Multifunction device drivers
1271 +#
1272 +# CONFIG_MFD_CORE is not set
1273 +# CONFIG_MFD_SM501 is not set
1274 +# CONFIG_MFD_ASIC3 is not set
1275 +# CONFIG_HTC_EGPIO is not set
1276 +# CONFIG_HTC_PASIC3 is not set
1277 +# CONFIG_MFD_TMIO is not set
1278 +# CONFIG_MFD_T7L66XB is not set
1279 +# CONFIG_MFD_TC6387XB is not set
1280 +# CONFIG_MFD_TC6393XB is not set
1281 +# CONFIG_PMIC_DA903X is not set
1282 +# CONFIG_MFD_WM8400 is not set
1283 +# CONFIG_MFD_WM8350_I2C is not set
1284 +CONFIG_MFD_PCF50633=y
1285 +CONFIG_PCF50633_ADC=y
1286 +CONFIG_PCF50633_GPIO=y
1287 +# CONFIG_MFD_PCF50606 is not set
1288 +CONFIG_MFD_GLAMO=y
1289 +CONFIG_MFD_GLAMO_FB=y
1290 +CONFIG_MFD_GLAMO_SPI_GPIO=y
1291 +CONFIG_MFD_GLAMO_SPI_FB=y
1292 +CONFIG_MFD_GLAMO_MCI=y
1293 +
1294 +#
1295 +# Multimedia devices
1296 +#
1297 +
1298 +#
1299 +# Multimedia core support
1300 +#
1301 +# CONFIG_VIDEO_DEV is not set
1302 +# CONFIG_DVB_CORE is not set
1303 +# CONFIG_VIDEO_MEDIA is not set
1304 +
1305 +#
1306 +# Multimedia drivers
1307 +#
1308 +CONFIG_DAB=y
1309 +# CONFIG_USB_DABUSB is not set
1310 +
1311 +#
1312 +# Graphics support
1313 +#
1314 +# CONFIG_VGASTATE is not set
1315 +CONFIG_VIDEO_OUTPUT_CONTROL=y
1316 +CONFIG_FB=y
1317 +# CONFIG_FIRMWARE_EDID is not set
1318 +# CONFIG_FB_DDC is not set
1319 +# CONFIG_FB_BOOT_VESA_SUPPORT is not set
1320 +CONFIG_FB_CFB_FILLRECT=y
1321 +CONFIG_FB_CFB_COPYAREA=y
1322 +CONFIG_FB_CFB_IMAGEBLIT=y
1323 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
1324 +# CONFIG_FB_SYS_FILLRECT is not set
1325 +# CONFIG_FB_SYS_COPYAREA is not set
1326 +# CONFIG_FB_SYS_IMAGEBLIT is not set
1327 +# CONFIG_FB_FOREIGN_ENDIAN is not set
1328 +# CONFIG_FB_SYS_FOPS is not set
1329 +# CONFIG_FB_SVGALIB is not set
1330 +# CONFIG_FB_MACMODES is not set
1331 +# CONFIG_FB_BACKLIGHT is not set
1332 +# CONFIG_FB_MODE_HELPERS is not set
1333 +# CONFIG_FB_TILEBLITTING is not set
1334 +
1335 +#
1336 +# Frame buffer hardware drivers
1337 +#
1338 +# CONFIG_FB_UVESA is not set
1339 +# CONFIG_FB_S1D13XXX is not set
1340 +CONFIG_FB_S3C2410=y
1341 +# CONFIG_FB_S3C2410_DEBUG is not set
1342 +# CONFIG_FB_VIRTUAL is not set
1343 +# CONFIG_FB_METRONOME is not set
1344 +# CONFIG_FB_MB862XX is not set
1345 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
1346 +CONFIG_LCD_CLASS_DEVICE=y
1347 +CONFIG_LCD_LTV350QV=y
1348 +# CONFIG_LCD_ILI9320 is not set
1349 +# CONFIG_LCD_TDO24M is not set
1350 +# CONFIG_LCD_VGG2432A4 is not set
1351 +# CONFIG_LCD_PLATFORM is not set
1352 +CONFIG_BACKLIGHT_CLASS_DEVICE=y
1353 +CONFIG_BACKLIGHT_CORGI=y
1354 +# CONFIG_BACKLIGHT_PWM is not set
1355 +
1356 +#
1357 +# Display device support
1358 +#
1359 +CONFIG_DISPLAY_SUPPORT=y
1360 +
1361 +#
1362 +# Display hardware drivers
1363 +#
1364 +CONFIG_DISPLAY_JBT6K74=y
1365 +
1366 +#
1367 +# Console display driver support
1368 +#
1369 +# CONFIG_VGA_CONSOLE is not set
1370 +CONFIG_DUMMY_CONSOLE=y
1371 +CONFIG_FRAMEBUFFER_CONSOLE=y
1372 +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
1373 +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
1374 +CONFIG_FONTS=y
1375 +# CONFIG_FONT_8x8 is not set
1376 +# CONFIG_FONT_8x16 is not set
1377 +CONFIG_FONT_6x11=y
1378 +# CONFIG_FONT_7x14 is not set
1379 +# CONFIG_FONT_PEARL_8x8 is not set
1380 +# CONFIG_FONT_ACORN_8x8 is not set
1381 +# CONFIG_FONT_MINI_4x6 is not set
1382 +# CONFIG_FONT_SUN8x16 is not set
1383 +# CONFIG_FONT_SUN12x22 is not set
1384 +# CONFIG_FONT_10x18 is not set
1385 +# CONFIG_LOGO is not set
1386 +CONFIG_SOUND=y
1387 +CONFIG_SOUND_OSS_CORE=y
1388 +CONFIG_SND=y
1389 +CONFIG_SND_TIMER=y
1390 +CONFIG_SND_PCM=y
1391 +CONFIG_SND_HWDEP=m
1392 +CONFIG_SND_RAWMIDI=m
1393 +# CONFIG_SND_SEQUENCER is not set
1394 +CONFIG_SND_OSSEMUL=y
1395 +CONFIG_SND_MIXER_OSS=y
1396 +CONFIG_SND_PCM_OSS=y
1397 +CONFIG_SND_PCM_OSS_PLUGINS=y
1398 +# CONFIG_SND_DYNAMIC_MINORS is not set
1399 +CONFIG_SND_SUPPORT_OLD_API=y
1400 +CONFIG_SND_VERBOSE_PROCFS=y
1401 +# CONFIG_SND_VERBOSE_PRINTK is not set
1402 +CONFIG_SND_DEBUG=y
1403 +# CONFIG_SND_DEBUG_VERBOSE is not set
1404 +CONFIG_SND_PCM_XRUN_DEBUG=y
1405 +CONFIG_SND_DRIVERS=y
1406 +# CONFIG_SND_DUMMY is not set
1407 +# CONFIG_SND_MTPAV is not set
1408 +# CONFIG_SND_SERIAL_U16550 is not set
1409 +# CONFIG_SND_MPU401 is not set
1410 +CONFIG_SND_ARM=y
1411 +# CONFIG_SND_SPI is not set
1412 +CONFIG_SND_USB=y
1413 +CONFIG_SND_USB_AUDIO=m
1414 +# CONFIG_SND_USB_CAIAQ is not set
1415 +CONFIG_SND_SOC=y
1416 +CONFIG_SND_S3C24XX_SOC=y
1417 +CONFIG_SND_S3C24XX_SOC_I2S=y
1418 +CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753=y
1419 +# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set
1420 +# CONFIG_SND_SOC_ALL_CODECS is not set
1421 +CONFIG_SND_SOC_WM8753=y
1422 +# CONFIG_SOUND_PRIME is not set
1423 +CONFIG_HID_SUPPORT=y
1424 +CONFIG_HID=y
1425 +# CONFIG_HID_DEBUG is not set
1426 +# CONFIG_HIDRAW is not set
1427 +
1428 +#
1429 +# USB Input Devices
1430 +#
1431 +CONFIG_USB_HID=y
1432 +CONFIG_HID_PID=y
1433 +# CONFIG_USB_HIDDEV is not set
1434 +
1435 +#
1436 +# Special HID drivers
1437 +#
1438 +CONFIG_HID_COMPAT=y
1439 +CONFIG_HID_A4TECH=y
1440 +CONFIG_HID_APPLE=y
1441 +CONFIG_HID_BELKIN=y
1442 +CONFIG_HID_BRIGHT=y
1443 +CONFIG_HID_CHERRY=y
1444 +CONFIG_HID_CHICONY=y
1445 +CONFIG_HID_CYPRESS=y
1446 +CONFIG_HID_DELL=y
1447 +CONFIG_HID_EZKEY=y
1448 +CONFIG_HID_GYRATION=y
1449 +CONFIG_HID_LOGITECH=y
1450 +# CONFIG_LOGITECH_FF is not set
1451 +# CONFIG_LOGIRUMBLEPAD2_FF is not set
1452 +CONFIG_HID_MICROSOFT=y
1453 +CONFIG_HID_MONTEREY=y
1454 +CONFIG_HID_PANTHERLORD=y
1455 +# CONFIG_PANTHERLORD_FF is not set
1456 +CONFIG_HID_PETALYNX=y
1457 +CONFIG_HID_SAMSUNG=y
1458 +CONFIG_HID_SONY=y
1459 +CONFIG_HID_SUNPLUS=y
1460 +# CONFIG_THRUSTMASTER_FF is not set
1461 +# CONFIG_ZEROPLUS_FF is not set
1462 +CONFIG_USB_SUPPORT=y
1463 +CONFIG_USB_ARCH_HAS_HCD=y
1464 +CONFIG_USB_ARCH_HAS_OHCI=y
1465 +# CONFIG_USB_ARCH_HAS_EHCI is not set
1466 +CONFIG_USB=y
1467 +# CONFIG_USB_DEBUG is not set
1468 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1469 +
1470 +#
1471 +# Miscellaneous USB options
1472 +#
1473 +CONFIG_USB_DEVICEFS=y
1474 +CONFIG_USB_DEVICE_CLASS=y
1475 +# CONFIG_USB_DYNAMIC_MINORS is not set
1476 +CONFIG_USB_SUSPEND=y
1477 +# CONFIG_USB_OTG is not set
1478 +CONFIG_USB_MON=y
1479 +# CONFIG_USB_WUSB is not set
1480 +# CONFIG_USB_WUSB_CBAF is not set
1481 +
1482 +#
1483 +# USB Host Controller Drivers
1484 +#
1485 +# CONFIG_USB_C67X00_HCD is not set
1486 +# CONFIG_USB_ISP116X_HCD is not set
1487 +# CONFIG_USB_ISP1760_HCD is not set
1488 +CONFIG_USB_OHCI_HCD=y
1489 +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1490 +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1491 +CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1492 +# CONFIG_USB_SL811_HCD is not set
1493 +# CONFIG_USB_R8A66597_HCD is not set
1494 +# CONFIG_USB_HWA_HCD is not set
1495 +# CONFIG_USB_MUSB_HDRC is not set
1496 +# CONFIG_USB_GADGET_MUSB_HDRC is not set
1497 +
1498 +#
1499 +# USB Device Class drivers
1500 +#
1501 +CONFIG_USB_ACM=y
1502 +CONFIG_USB_PRINTER=m
1503 +# CONFIG_USB_WDM is not set
1504 +CONFIG_USB_TMC=m
1505 +
1506 +#
1507 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1508 +#
1509 +
1510 +#
1511 +# may also be needed; see USB_STORAGE Help for more information
1512 +#
1513 +CONFIG_USB_STORAGE=y
1514 +# CONFIG_USB_STORAGE_DEBUG is not set
1515 +CONFIG_USB_STORAGE_DATAFAB=y
1516 +CONFIG_USB_STORAGE_FREECOM=y
1517 +# CONFIG_USB_STORAGE_ISD200 is not set
1518 +CONFIG_USB_STORAGE_DPCM=y
1519 +CONFIG_USB_STORAGE_USBAT=y
1520 +CONFIG_USB_STORAGE_SDDR09=y
1521 +CONFIG_USB_STORAGE_SDDR55=y
1522 +CONFIG_USB_STORAGE_JUMPSHOT=y
1523 +CONFIG_USB_STORAGE_ALAUDA=y
1524 +# CONFIG_USB_STORAGE_ONETOUCH is not set
1525 +CONFIG_USB_STORAGE_KARMA=y
1526 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1527 +CONFIG_USB_LIBUSUAL=y
1528 +
1529 +#
1530 +# USB Imaging devices
1531 +#
1532 +# CONFIG_USB_MDC800 is not set
1533 +# CONFIG_USB_MICROTEK is not set
1534 +
1535 +#
1536 +# USB port drivers
1537 +#
1538 +CONFIG_USB_SERIAL=y
1539 +CONFIG_USB_SERIAL_CONSOLE=y
1540 +CONFIG_USB_EZUSB=y
1541 +CONFIG_USB_SERIAL_GENERIC=y
1542 +CONFIG_USB_SERIAL_AIRCABLE=m
1543 +CONFIG_USB_SERIAL_ARK3116=m
1544 +CONFIG_USB_SERIAL_BELKIN=m
1545 +# CONFIG_USB_SERIAL_CH341 is not set
1546 +CONFIG_USB_SERIAL_WHITEHEAT=m
1547 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1548 +CONFIG_USB_SERIAL_CP2101=m
1549 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1550 +CONFIG_USB_SERIAL_EMPEG=m
1551 +CONFIG_USB_SERIAL_FTDI_SIO=m
1552 +CONFIG_USB_SERIAL_FUNSOFT=m
1553 +CONFIG_USB_SERIAL_VISOR=m
1554 +CONFIG_USB_SERIAL_IPAQ=m
1555 +CONFIG_USB_SERIAL_IR=m
1556 +CONFIG_USB_SERIAL_EDGEPORT=m
1557 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1558 +CONFIG_USB_SERIAL_GARMIN=m
1559 +CONFIG_USB_SERIAL_IPW=m
1560 +# CONFIG_USB_SERIAL_IUU is not set
1561 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1562 +CONFIG_USB_SERIAL_KEYSPAN=m
1563 +CONFIG_USB_SERIAL_KLSI=m
1564 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1565 +CONFIG_USB_SERIAL_MCT_U232=m
1566 +CONFIG_USB_SERIAL_MOS7720=m
1567 +CONFIG_USB_SERIAL_MOS7840=m
1568 +# CONFIG_USB_SERIAL_MOTOROLA is not set
1569 +CONFIG_USB_SERIAL_NAVMAN=m
1570 +CONFIG_USB_SERIAL_PL2303=m
1571 +# CONFIG_USB_SERIAL_OTI6858 is not set
1572 +# CONFIG_USB_SERIAL_SPCP8X5 is not set
1573 +CONFIG_USB_SERIAL_HP4X=m
1574 +CONFIG_USB_SERIAL_SAFE=m
1575 +CONFIG_USB_SERIAL_SAFE_PADDED=y
1576 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1577 +CONFIG_USB_SERIAL_TI=m
1578 +CONFIG_USB_SERIAL_CYBERJACK=m
1579 +CONFIG_USB_SERIAL_XIRCOM=m
1580 +CONFIG_USB_SERIAL_OPTION=y
1581 +CONFIG_USB_SERIAL_OMNINET=m
1582 +# CONFIG_USB_SERIAL_DEBUG is not set
1583 +
1584 +#
1585 +# USB Miscellaneous drivers
1586 +#
1587 +# CONFIG_USB_EMI62 is not set
1588 +# CONFIG_USB_EMI26 is not set
1589 +# CONFIG_USB_ADUTUX is not set
1590 +# CONFIG_USB_SEVSEG is not set
1591 +# CONFIG_USB_RIO500 is not set
1592 +# CONFIG_USB_LEGOTOWER is not set
1593 +# CONFIG_USB_LCD is not set
1594 +CONFIG_USB_BERRY_CHARGE=m
1595 +# CONFIG_USB_LED is not set
1596 +# CONFIG_USB_CYPRESS_CY7C63 is not set
1597 +# CONFIG_USB_CYTHERM is not set
1598 +# CONFIG_USB_PHIDGET is not set
1599 +# CONFIG_USB_IDMOUSE is not set
1600 +# CONFIG_USB_FTDI_ELAN is not set
1601 +# CONFIG_USB_APPLEDISPLAY is not set
1602 +# CONFIG_USB_LD is not set
1603 +CONFIG_USB_TRANCEVIBRATOR=m
1604 +CONFIG_USB_IOWARRIOR=m
1605 +# CONFIG_USB_TEST is not set
1606 +# CONFIG_USB_ISIGHTFW is not set
1607 +# CONFIG_USB_VST is not set
1608 +CONFIG_USB_GADGET=y
1609 +# CONFIG_USB_GADGET_DEBUG is not set
1610 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
1611 +# CONFIG_USB_GADGET_DEBUG_FS is not set
1612 +CONFIG_USB_GADGET_VBUS_DRAW=500
1613 +CONFIG_USB_GADGET_SELECTED=y
1614 +# CONFIG_USB_GADGET_AT91 is not set
1615 +# CONFIG_USB_GADGET_ATMEL_USBA is not set
1616 +# CONFIG_USB_GADGET_FSL_USB2 is not set
1617 +# CONFIG_USB_GADGET_LH7A40X is not set
1618 +# CONFIG_USB_GADGET_OMAP is not set
1619 +# CONFIG_USB_GADGET_PXA25X is not set
1620 +# CONFIG_USB_GADGET_PXA27X is not set
1621 +CONFIG_USB_GADGET_S3C2410=y
1622 +CONFIG_USB_S3C2410=y
1623 +CONFIG_USB_S3C2410_DEBUG=y
1624 +# CONFIG_USB_GADGET_M66592 is not set
1625 +# CONFIG_USB_GADGET_AMD5536UDC is not set
1626 +# CONFIG_USB_GADGET_FSL_QE is not set
1627 +# CONFIG_USB_GADGET_NET2280 is not set
1628 +# CONFIG_USB_GADGET_GOKU is not set
1629 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
1630 +# CONFIG_USB_GADGET_DUALSPEED is not set
1631 +# CONFIG_USB_ZERO is not set
1632 +CONFIG_USB_ETH=y
1633 +CONFIG_USB_ETH_RNDIS=y
1634 +# CONFIG_USB_GADGETFS is not set
1635 +# CONFIG_USB_FILE_STORAGE is not set
1636 +# CONFIG_USB_G_SERIAL is not set
1637 +# CONFIG_USB_MIDI_GADGET is not set
1638 +# CONFIG_USB_G_PRINTER is not set
1639 +# CONFIG_USB_CDC_COMPOSITE is not set
1640 +CONFIG_AR6000_WLAN=y
1641 +CONFIG_MMC=y
1642 +# CONFIG_MMC_DEBUG is not set
1643 +CONFIG_MMC_UNSAFE_RESUME=y
1644 +
1645 +#
1646 +# MMC/SD/SDIO Card Drivers
1647 +#
1648 +CONFIG_MMC_BLOCK=y
1649 +CONFIG_MMC_BLOCK_BOUNCE=y
1650 +# CONFIG_SDIO_UART is not set
1651 +# CONFIG_MMC_TEST is not set
1652 +
1653 +#
1654 +# MMC/SD/SDIO Host Controller Drivers
1655 +#
1656 +CONFIG_MMC_SDHCI=y
1657 +CONFIG_MMC_SDHCI_S3C=y
1658 +# CONFIG_MMC_SPI is not set
1659 +CONFIG_MMC_S3C=y
1660 +# CONFIG_MEMSTICK is not set
1661 +# CONFIG_ACCESSIBILITY is not set
1662 +CONFIG_NEW_LEDS=y
1663 +CONFIG_LEDS_CLASS=y
1664 +
1665 +#
1666 +# LED drivers
1667 +#
1668 +CONFIG_LEDS_S3C24XX=m
1669 +# CONFIG_LEDS_PCA9532 is not set
1670 +CONFIG_LEDS_GPIO=y
1671 +# CONFIG_LEDS_PCA955X is not set
1672 +CONFIG_LEDS_NEO1973_VIBRATOR=y
1673 +CONFIG_LEDS_NEO1973_GTA02=y
1674 +
1675 +#
1676 +# LED Triggers
1677 +#
1678 +CONFIG_LEDS_TRIGGERS=y
1679 +CONFIG_LEDS_TRIGGER_TIMER=y
1680 +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
1681 +CONFIG_LEDS_TRIGGER_BACKLIGHT=y
1682 +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
1683 +CONFIG_RTC_LIB=y
1684 +CONFIG_RTC_CLASS=y
1685 +CONFIG_RTC_HCTOSYS=y
1686 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1687 +CONFIG_RTC_DEBUG=y
1688 +
1689 +#
1690 +# RTC interfaces
1691 +#
1692 +CONFIG_RTC_INTF_SYSFS=y
1693 +CONFIG_RTC_INTF_PROC=y
1694 +CONFIG_RTC_INTF_DEV=y
1695 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1696 +# CONFIG_RTC_DRV_TEST is not set
1697 +
1698 +#
1699 +# I2C RTC drivers
1700 +#
1701 +# CONFIG_RTC_DRV_DS1307 is not set
1702 +# CONFIG_RTC_DRV_DS1374 is not set
1703 +# CONFIG_RTC_DRV_DS1672 is not set
1704 +# CONFIG_RTC_DRV_MAX6900 is not set
1705 +# CONFIG_RTC_DRV_RS5C372 is not set
1706 +# CONFIG_RTC_DRV_ISL1208 is not set
1707 +# CONFIG_RTC_DRV_X1205 is not set
1708 +# CONFIG_RTC_DRV_PCF8563 is not set
1709 +# CONFIG_RTC_DRV_PCF8583 is not set
1710 +CONFIG_RTC_DRV_PCF50633=y
1711 +# CONFIG_RTC_DRV_PCF50606 is not set
1712 +# CONFIG_RTC_DRV_M41T80 is not set
1713 +# CONFIG_RTC_DRV_S35390A is not set
1714 +# CONFIG_RTC_DRV_FM3130 is not set
1715 +
1716 +#
1717 +# SPI RTC drivers
1718 +#
1719 +# CONFIG_RTC_DRV_M41T94 is not set
1720 +# CONFIG_RTC_DRV_DS1305 is not set
1721 +# CONFIG_RTC_DRV_MAX6902 is not set
1722 +# CONFIG_RTC_DRV_R9701 is not set
1723 +# CONFIG_RTC_DRV_RS5C348 is not set
1724 +# CONFIG_RTC_DRV_DS3234 is not set
1725 +
1726 +#
1727 +# Platform RTC drivers
1728 +#
1729 +# CONFIG_RTC_DRV_CMOS is not set
1730 +# CONFIG_RTC_DRV_DS1286 is not set
1731 +# CONFIG_RTC_DRV_DS1511 is not set
1732 +# CONFIG_RTC_DRV_DS1553 is not set
1733 +# CONFIG_RTC_DRV_DS1742 is not set
1734 +# CONFIG_RTC_DRV_STK17TA8 is not set
1735 +# CONFIG_RTC_DRV_M48T86 is not set
1736 +# CONFIG_RTC_DRV_M48T35 is not set
1737 +# CONFIG_RTC_DRV_M48T59 is not set
1738 +# CONFIG_RTC_DRV_BQ4802 is not set
1739 +# CONFIG_RTC_DRV_V3020 is not set
1740 +
1741 +#
1742 +# on-CPU RTC drivers
1743 +#
1744 +CONFIG_RTC_DRV_S3C=m
1745 +CONFIG_DMADEVICES=y
1746 +
1747 +#
1748 +# DMA Devices
1749 +#
1750 +
1751 +#
1752 +# Android
1753 +#
1754 +CONFIG_ANDROID_BINDER_IPC=y
1755 +CONFIG_ANDROID_POWER=y
1756 +CONFIG_ANDROID_POWER_STAT=y
1757 +CONFIG_ANDROID_POWER_ALARM=y
1758 +CONFIG_ANDROID_LOGGER=y
1759 +# CONFIG_ANDROID_RAM_CONSOLE is not set
1760 +# CONFIG_ANDROID_TIMED_GPIO is not set
1761 +# CONFIG_ANDROID_PARANOID_NETWORK is not set
1762 +CONFIG_REGULATOR=y
1763 +CONFIG_REGULATOR_DEBUG=y
1764 +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1765 +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1766 +# CONFIG_REGULATOR_BQ24022 is not set
1767 +CONFIG_REGULATOR_PCF50633=y
1768 +CONFIG_UIO=y
1769 +CONFIG_UIO_PDRV=y
1770 +# CONFIG_UIO_PDRV_GENIRQ is not set
1771 +# CONFIG_UIO_SMX is not set
1772 +# CONFIG_UIO_SERCOS3 is not set
1773 +
1774 +#
1775 +# File systems
1776 +#
1777 +CONFIG_EXT2_FS=y
1778 +# CONFIG_EXT2_FS_XATTR is not set
1779 +# CONFIG_EXT2_FS_XIP is not set
1780 +CONFIG_EXT3_FS=y
1781 +# CONFIG_EXT3_FS_XATTR is not set
1782 +CONFIG_EXT4_FS=y
1783 +CONFIG_EXT4DEV_COMPAT=y
1784 +CONFIG_EXT4_FS_XATTR=y
1785 +# CONFIG_EXT4_FS_POSIX_ACL is not set
1786 +CONFIG_EXT4_FS_SECURITY=y
1787 +CONFIG_JBD=y
1788 +# CONFIG_JBD_DEBUG is not set
1789 +CONFIG_JBD2=y
1790 +# CONFIG_JBD2_DEBUG is not set
1791 +CONFIG_FS_MBCACHE=y
1792 +# CONFIG_REISERFS_FS is not set
1793 +# CONFIG_JFS_FS is not set
1794 +CONFIG_FS_POSIX_ACL=y
1795 +CONFIG_FILE_LOCKING=y
1796 +# CONFIG_XFS_FS is not set
1797 +# CONFIG_OCFS2_FS is not set
1798 +CONFIG_DNOTIFY=y
1799 +CONFIG_INOTIFY=y
1800 +CONFIG_INOTIFY_USER=y
1801 +# CONFIG_QUOTA is not set
1802 +# CONFIG_AUTOFS_FS is not set
1803 +# CONFIG_AUTOFS4_FS is not set
1804 +CONFIG_FUSE_FS=m
1805 +
1806 +#
1807 +# CD-ROM/DVD Filesystems
1808 +#
1809 +CONFIG_ISO9660_FS=m
1810 +CONFIG_JOLIET=y
1811 +# CONFIG_ZISOFS is not set
1812 +# CONFIG_UDF_FS is not set
1813 +
1814 +#
1815 +# DOS/FAT/NT Filesystems
1816 +#
1817 +CONFIG_FAT_FS=y
1818 +CONFIG_MSDOS_FS=y
1819 +CONFIG_VFAT_FS=y
1820 +CONFIG_FAT_DEFAULT_CODEPAGE=437
1821 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1822 +# CONFIG_NTFS_FS is not set
1823 +
1824 +#
1825 +# Pseudo filesystems
1826 +#
1827 +CONFIG_PROC_FS=y
1828 +CONFIG_PROC_SYSCTL=y
1829 +CONFIG_PROC_PAGE_MONITOR=y
1830 +CONFIG_SYSFS=y
1831 +CONFIG_TMPFS=y
1832 +# CONFIG_TMPFS_POSIX_ACL is not set
1833 +# CONFIG_HUGETLB_PAGE is not set
1834 +CONFIG_CONFIGFS_FS=m
1835 +
1836 +#
1837 +# Miscellaneous filesystems
1838 +#
1839 +# CONFIG_ADFS_FS is not set
1840 +# CONFIG_AFFS_FS is not set
1841 +# CONFIG_HFS_FS is not set
1842 +# CONFIG_HFSPLUS_FS is not set
1843 +# CONFIG_BEFS_FS is not set
1844 +# CONFIG_BFS_FS is not set
1845 +# CONFIG_EFS_FS is not set
1846 +CONFIG_JFFS2_FS=y
1847 +CONFIG_JFFS2_FS_DEBUG=0
1848 +CONFIG_JFFS2_FS_WRITEBUFFER=y
1849 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1850 +CONFIG_JFFS2_SUMMARY=y
1851 +# CONFIG_JFFS2_FS_XATTR is not set
1852 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1853 +CONFIG_JFFS2_ZLIB=y
1854 +# CONFIG_JFFS2_LZO is not set
1855 +CONFIG_JFFS2_RTIME=y
1856 +# CONFIG_JFFS2_RUBIN is not set
1857 +CONFIG_CRAMFS=y
1858 +# CONFIG_VXFS_FS is not set
1859 +# CONFIG_MINIX_FS is not set
1860 +# CONFIG_OMFS_FS is not set
1861 +# CONFIG_HPFS_FS is not set
1862 +# CONFIG_QNX4FS_FS is not set
1863 +CONFIG_ROMFS_FS=y
1864 +# CONFIG_SYSV_FS is not set
1865 +# CONFIG_UFS_FS is not set
1866 +CONFIG_NETWORK_FILESYSTEMS=y
1867 +# CONFIG_NFS_FS is not set
1868 +CONFIG_NFSD=y
1869 +CONFIG_NFSD_V2_ACL=y
1870 +CONFIG_NFSD_V3=y
1871 +CONFIG_NFSD_V3_ACL=y
1872 +# CONFIG_NFSD_V4 is not set
1873 +CONFIG_LOCKD=y
1874 +CONFIG_LOCKD_V4=y
1875 +CONFIG_EXPORTFS=y
1876 +CONFIG_NFS_ACL_SUPPORT=y
1877 +CONFIG_NFS_COMMON=y
1878 +CONFIG_SUNRPC=y
1879 +# CONFIG_SUNRPC_REGISTER_V4 is not set
1880 +# CONFIG_RPCSEC_GSS_KRB5 is not set
1881 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
1882 +# CONFIG_SMB_FS is not set
1883 +CONFIG_CIFS=m
1884 +# CONFIG_CIFS_STATS is not set
1885 +# CONFIG_CIFS_WEAK_PW_HASH is not set
1886 +# CONFIG_CIFS_XATTR is not set
1887 +# CONFIG_CIFS_DEBUG2 is not set
1888 +# CONFIG_CIFS_EXPERIMENTAL is not set
1889 +# CONFIG_NCP_FS is not set
1890 +# CONFIG_CODA_FS is not set
1891 +# CONFIG_AFS_FS is not set
1892 +
1893 +#
1894 +# Partition Types
1895 +#
1896 +CONFIG_PARTITION_ADVANCED=y
1897 +# CONFIG_ACORN_PARTITION is not set
1898 +# CONFIG_OSF_PARTITION is not set
1899 +# CONFIG_AMIGA_PARTITION is not set
1900 +# CONFIG_ATARI_PARTITION is not set
1901 +# CONFIG_MAC_PARTITION is not set
1902 +CONFIG_MSDOS_PARTITION=y
1903 +# CONFIG_BSD_DISKLABEL is not set
1904 +# CONFIG_MINIX_SUBPARTITION is not set
1905 +# CONFIG_SOLARIS_X86_PARTITION is not set
1906 +# CONFIG_UNIXWARE_DISKLABEL is not set
1907 +# CONFIG_LDM_PARTITION is not set
1908 +# CONFIG_SGI_PARTITION is not set
1909 +# CONFIG_ULTRIX_PARTITION is not set
1910 +# CONFIG_SUN_PARTITION is not set
1911 +# CONFIG_KARMA_PARTITION is not set
1912 +# CONFIG_EFI_PARTITION is not set
1913 +# CONFIG_SYSV68_PARTITION is not set
1914 +CONFIG_NLS=y
1915 +CONFIG_NLS_DEFAULT="iso8859-1"
1916 +CONFIG_NLS_CODEPAGE_437=y
1917 +# CONFIG_NLS_CODEPAGE_737 is not set
1918 +# CONFIG_NLS_CODEPAGE_775 is not set
1919 +CONFIG_NLS_CODEPAGE_850=m
1920 +# CONFIG_NLS_CODEPAGE_852 is not set
1921 +# CONFIG_NLS_CODEPAGE_855 is not set
1922 +# CONFIG_NLS_CODEPAGE_857 is not set
1923 +# CONFIG_NLS_CODEPAGE_860 is not set
1924 +# CONFIG_NLS_CODEPAGE_861 is not set
1925 +# CONFIG_NLS_CODEPAGE_862 is not set
1926 +# CONFIG_NLS_CODEPAGE_863 is not set
1927 +# CONFIG_NLS_CODEPAGE_864 is not set
1928 +# CONFIG_NLS_CODEPAGE_865 is not set
1929 +# CONFIG_NLS_CODEPAGE_866 is not set
1930 +# CONFIG_NLS_CODEPAGE_869 is not set
1931 +CONFIG_NLS_CODEPAGE_936=m
1932 +CONFIG_NLS_CODEPAGE_950=m
1933 +# CONFIG_NLS_CODEPAGE_932 is not set
1934 +# CONFIG_NLS_CODEPAGE_949 is not set
1935 +# CONFIG_NLS_CODEPAGE_874 is not set
1936 +# CONFIG_NLS_ISO8859_8 is not set
1937 +# CONFIG_NLS_CODEPAGE_1250 is not set
1938 +# CONFIG_NLS_CODEPAGE_1251 is not set
1939 +# CONFIG_NLS_ASCII is not set
1940 +CONFIG_NLS_ISO8859_1=y
1941 +# CONFIG_NLS_ISO8859_2 is not set
1942 +# CONFIG_NLS_ISO8859_3 is not set
1943 +# CONFIG_NLS_ISO8859_4 is not set
1944 +# CONFIG_NLS_ISO8859_5 is not set
1945 +# CONFIG_NLS_ISO8859_6 is not set
1946 +# CONFIG_NLS_ISO8859_7 is not set
1947 +# CONFIG_NLS_ISO8859_9 is not set
1948 +# CONFIG_NLS_ISO8859_13 is not set
1949 +# CONFIG_NLS_ISO8859_14 is not set
1950 +# CONFIG_NLS_ISO8859_15 is not set
1951 +# CONFIG_NLS_KOI8_R is not set
1952 +# CONFIG_NLS_KOI8_U is not set
1953 +CONFIG_NLS_UTF8=m
1954 +# CONFIG_DLM is not set
1955 +
1956 +#
1957 +# Kernel hacking
1958 +#
1959 +CONFIG_PRINTK_TIME=y
1960 +CONFIG_ENABLE_WARN_DEPRECATED=y
1961 +CONFIG_ENABLE_MUST_CHECK=y
1962 +CONFIG_FRAME_WARN=1024
1963 +CONFIG_MAGIC_SYSRQ=y
1964 +# CONFIG_UNUSED_SYMBOLS is not set
1965 +CONFIG_DEBUG_FS=y
1966 +# CONFIG_HEADERS_CHECK is not set
1967 +CONFIG_DEBUG_KERNEL=y
1968 +CONFIG_DEBUG_SHIRQ=y
1969 +CONFIG_DETECT_SOFTLOCKUP=y
1970 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
1971 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
1972 +CONFIG_SCHED_DEBUG=y
1973 +CONFIG_SCHEDSTATS=y
1974 +CONFIG_TIMER_STATS=y
1975 +# CONFIG_DEBUG_OBJECTS is not set
1976 +# CONFIG_DEBUG_SLAB is not set
1977 +CONFIG_DEBUG_PREEMPT=y
1978 +# CONFIG_DEBUG_RT_MUTEXES is not set
1979 +# CONFIG_RT_MUTEX_TESTER is not set
1980 +CONFIG_DEBUG_SPINLOCK=y
1981 +CONFIG_DEBUG_MUTEXES=y
1982 +CONFIG_DEBUG_LOCK_ALLOC=y
1983 +# CONFIG_PROVE_LOCKING is not set
1984 +CONFIG_LOCKDEP=y
1985 +CONFIG_LOCK_STAT=y
1986 +CONFIG_DEBUG_LOCKDEP=y
1987 +CONFIG_DEBUG_SPINLOCK_SLEEP=y
1988 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1989 +CONFIG_STACKTRACE=y
1990 +# CONFIG_DEBUG_KOBJECT is not set
1991 +CONFIG_DEBUG_BUGVERBOSE=y
1992 +CONFIG_DEBUG_INFO=y
1993 +# CONFIG_DEBUG_VM is not set
1994 +# CONFIG_DEBUG_WRITECOUNT is not set
1995 +CONFIG_DEBUG_MEMORY_INIT=y
1996 +# CONFIG_DEBUG_LIST is not set
1997 +CONFIG_DEBUG_SG=y
1998 +CONFIG_FRAME_POINTER=y
1999 +# CONFIG_BOOT_PRINTK_DELAY is not set
2000 +# CONFIG_RCU_TORTURE_TEST is not set
2001 +CONFIG_RCU_CPU_STALL_DETECTOR=y
2002 +# CONFIG_BACKTRACE_SELF_TEST is not set
2003 +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
2004 +# CONFIG_FAULT_INJECTION is not set
2005 +CONFIG_LATENCYTOP=y
2006 +CONFIG_SYSCTL_SYSCALL_CHECK=y
2007 +CONFIG_HAVE_FUNCTION_TRACER=y
2008 +
2009 +#
2010 +# Tracers
2011 +#
2012 +# CONFIG_FUNCTION_TRACER is not set
2013 +# CONFIG_SCHED_TRACER is not set
2014 +# CONFIG_CONTEXT_SWITCH_TRACER is not set
2015 +# CONFIG_BOOT_TRACER is not set
2016 +# CONFIG_STACK_TRACER is not set
2017 +CONFIG_DYNAMIC_PRINTK_DEBUG=y
2018 +# CONFIG_SAMPLES is not set
2019 +CONFIG_HAVE_ARCH_KGDB=y
2020 +# CONFIG_KGDB is not set
2021 +# CONFIG_DEBUG_USER is not set
2022 +CONFIG_DEBUG_ERRORS=y
2023 +# CONFIG_DEBUG_STACK_USAGE is not set
2024 +# CONFIG_DEBUG_LL is not set
2025 +CONFIG_DEBUG_S3C_UART=2
2026 +
2027 +#
2028 +# Security options
2029 +#
2030 +# CONFIG_KEYS is not set
2031 +# CONFIG_SECURITY is not set
2032 +CONFIG_SECURITYFS=y
2033 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
2034 +CONFIG_CRYPTO=y
2035 +
2036 +#
2037 +# Crypto core or helper
2038 +#
2039 +CONFIG_CRYPTO_FIPS=y
2040 +CONFIG_CRYPTO_ALGAPI=y
2041 +CONFIG_CRYPTO_AEAD=y
2042 +CONFIG_CRYPTO_BLKCIPHER=y
2043 +CONFIG_CRYPTO_HASH=y
2044 +CONFIG_CRYPTO_RNG=y
2045 +CONFIG_CRYPTO_MANAGER=y
2046 +CONFIG_CRYPTO_GF128MUL=m
2047 +CONFIG_CRYPTO_NULL=m
2048 +# CONFIG_CRYPTO_CRYPTD is not set
2049 +CONFIG_CRYPTO_AUTHENC=m
2050 +CONFIG_CRYPTO_TEST=m
2051 +
2052 +#
2053 +# Authenticated Encryption with Associated Data
2054 +#
2055 +# CONFIG_CRYPTO_CCM is not set
2056 +# CONFIG_CRYPTO_GCM is not set
2057 +# CONFIG_CRYPTO_SEQIV is not set
2058 +
2059 +#
2060 +# Block modes
2061 +#
2062 +CONFIG_CRYPTO_CBC=y
2063 +# CONFIG_CRYPTO_CTR is not set
2064 +# CONFIG_CRYPTO_CTS is not set
2065 +CONFIG_CRYPTO_ECB=y
2066 +CONFIG_CRYPTO_LRW=m
2067 +CONFIG_CRYPTO_PCBC=m
2068 +# CONFIG_CRYPTO_XTS is not set
2069 +
2070 +#
2071 +# Hash modes
2072 +#
2073 +CONFIG_CRYPTO_HMAC=y
2074 +CONFIG_CRYPTO_XCBC=m
2075 +
2076 +#
2077 +# Digest
2078 +#
2079 +CONFIG_CRYPTO_CRC32C=m
2080 +CONFIG_CRYPTO_MD4=m
2081 +CONFIG_CRYPTO_MD5=y
2082 +CONFIG_CRYPTO_MICHAEL_MIC=m
2083 +# CONFIG_CRYPTO_RMD128 is not set
2084 +# CONFIG_CRYPTO_RMD160 is not set
2085 +# CONFIG_CRYPTO_RMD256 is not set
2086 +# CONFIG_CRYPTO_RMD320 is not set
2087 +CONFIG_CRYPTO_SHA1=y
2088 +CONFIG_CRYPTO_SHA256=m
2089 +CONFIG_CRYPTO_SHA512=m
2090 +CONFIG_CRYPTO_TGR192=m
2091 +CONFIG_CRYPTO_WP512=m
2092 +
2093 +#
2094 +# Ciphers
2095 +#
2096 +CONFIG_CRYPTO_AES=y
2097 +CONFIG_CRYPTO_ANUBIS=m
2098 +CONFIG_CRYPTO_ARC4=y
2099 +CONFIG_CRYPTO_BLOWFISH=m
2100 +CONFIG_CRYPTO_CAMELLIA=m
2101 +CONFIG_CRYPTO_CAST5=m
2102 +CONFIG_CRYPTO_CAST6=m
2103 +CONFIG_CRYPTO_DES=y
2104 +CONFIG_CRYPTO_FCRYPT=m
2105 +CONFIG_CRYPTO_KHAZAD=m
2106 +# CONFIG_CRYPTO_SALSA20 is not set
2107 +# CONFIG_CRYPTO_SEED is not set
2108 +CONFIG_CRYPTO_SERPENT=m
2109 +CONFIG_CRYPTO_TEA=m
2110 +CONFIG_CRYPTO_TWOFISH=m
2111 +CONFIG_CRYPTO_TWOFISH_COMMON=m
2112 +
2113 +#
2114 +# Compression
2115 +#
2116 +CONFIG_CRYPTO_DEFLATE=m
2117 +# CONFIG_CRYPTO_LZO is not set
2118 +
2119 +#
2120 +# Random Number Generation
2121 +#
2122 +CONFIG_CRYPTO_ANSI_CPRNG=y
2123 +CONFIG_CRYPTO_HW=y
2124 +
2125 +#
2126 +# Library routines
2127 +#
2128 +CONFIG_BITREVERSE=y
2129 +CONFIG_CRC_CCITT=y
2130 +CONFIG_CRC16=y
2131 +CONFIG_CRC_T10DIF=y
2132 +# CONFIG_CRC_ITU_T is not set
2133 +CONFIG_CRC32=y
2134 +# CONFIG_CRC7 is not set
2135 +CONFIG_LIBCRC32C=m
2136 +CONFIG_ZLIB_INFLATE=y
2137 +CONFIG_ZLIB_DEFLATE=y
2138 +CONFIG_TEXTSEARCH=y
2139 +CONFIG_TEXTSEARCH_KMP=m
2140 +CONFIG_TEXTSEARCH_BM=m
2141 +CONFIG_TEXTSEARCH_FSM=m
2142 +CONFIG_PLIST=y
2143 +CONFIG_HAS_IOMEM=y
2144 +CONFIG_HAS_DMA=y
2145 --- /dev/null
2146 +++ b/arch/arm/configs/gta02-packaging-defconfig
2147 @@ -0,0 +1,2111 @@
2148 +#
2149 +# Automatically generated make config: don't edit
2150 +# Linux kernel version: 2.6.28-rc4
2151 +# Wed Dec 10 11:09:39 2008
2152 +#
2153 +CONFIG_ARM=y
2154 +CONFIG_HAVE_PWM=y
2155 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
2156 +CONFIG_GENERIC_GPIO=y
2157 +# CONFIG_GENERIC_TIME is not set
2158 +# CONFIG_GENERIC_CLOCKEVENTS is not set
2159 +CONFIG_MMU=y
2160 +CONFIG_NO_IOPORT=y
2161 +CONFIG_GENERIC_HARDIRQS=y
2162 +CONFIG_STACKTRACE_SUPPORT=y
2163 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
2164 +CONFIG_LOCKDEP_SUPPORT=y
2165 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
2166 +CONFIG_HARDIRQS_SW_RESEND=y
2167 +CONFIG_GENERIC_IRQ_PROBE=y
2168 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
2169 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
2170 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
2171 +CONFIG_GENERIC_HWEIGHT=y
2172 +CONFIG_GENERIC_CALIBRATE_DELAY=y
2173 +CONFIG_FIQ=y
2174 +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
2175 +CONFIG_VECTORS_BASE=0xffff0000
2176 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
2177 +
2178 +#
2179 +# General setup
2180 +#
2181 +CONFIG_EXPERIMENTAL=y
2182 +CONFIG_BROKEN_ON_SMP=y
2183 +CONFIG_LOCK_KERNEL=y
2184 +CONFIG_INIT_ENV_ARG_LIMIT=32
2185 +CONFIG_LOCALVERSION="-mokodev"
2186 +# CONFIG_LOCALVERSION_AUTO is not set
2187 +CONFIG_SWAP=y
2188 +CONFIG_SYSVIPC=y
2189 +CONFIG_SYSVIPC_SYSCTL=y
2190 +# CONFIG_POSIX_MQUEUE is not set
2191 +# CONFIG_BSD_PROCESS_ACCT is not set
2192 +# CONFIG_TASKSTATS is not set
2193 +# CONFIG_AUDIT is not set
2194 +CONFIG_IKCONFIG=y
2195 +CONFIG_IKCONFIG_PROC=y
2196 +CONFIG_LOG_BUF_SHIFT=18
2197 +# CONFIG_CGROUPS is not set
2198 +# CONFIG_GROUP_SCHED is not set
2199 +CONFIG_SYSFS_DEPRECATED=y
2200 +CONFIG_SYSFS_DEPRECATED_V2=y
2201 +# CONFIG_RELAY is not set
2202 +CONFIG_NAMESPACES=y
2203 +# CONFIG_UTS_NS is not set
2204 +# CONFIG_IPC_NS is not set
2205 +# CONFIG_USER_NS is not set
2206 +# CONFIG_PID_NS is not set
2207 +CONFIG_BLK_DEV_INITRD=y
2208 +CONFIG_INITRAMFS_SOURCE=""
2209 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
2210 +CONFIG_SYSCTL=y
2211 +# CONFIG_EMBEDDED is not set
2212 +CONFIG_UID16=y
2213 +CONFIG_SYSCTL_SYSCALL=y
2214 +CONFIG_KALLSYMS=y
2215 +CONFIG_KALLSYMS_ALL=y
2216 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
2217 +CONFIG_HOTPLUG=y
2218 +CONFIG_PRINTK=y
2219 +CONFIG_BUG=y
2220 +CONFIG_ELF_CORE=y
2221 +CONFIG_COMPAT_BRK=y
2222 +CONFIG_BASE_FULL=y
2223 +CONFIG_FUTEX=y
2224 +CONFIG_ANON_INODES=y
2225 +CONFIG_EPOLL=y
2226 +CONFIG_SIGNALFD=y
2227 +CONFIG_TIMERFD=y
2228 +CONFIG_EVENTFD=y
2229 +CONFIG_SHMEM=y
2230 +CONFIG_AIO=y
2231 +CONFIG_ASHMEM=y
2232 +CONFIG_VM_EVENT_COUNTERS=y
2233 +CONFIG_SLAB=y
2234 +# CONFIG_SLUB is not set
2235 +# CONFIG_SLOB is not set
2236 +# CONFIG_PROFILING is not set
2237 +CONFIG_MARKERS=y
2238 +CONFIG_HAVE_OPROFILE=y
2239 +# CONFIG_KPROBES is not set
2240 +CONFIG_HAVE_KPROBES=y
2241 +CONFIG_HAVE_KRETPROBES=y
2242 +CONFIG_HAVE_CLK=y
2243 +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
2244 +CONFIG_SLABINFO=y
2245 +CONFIG_RT_MUTEXES=y
2246 +# CONFIG_TINY_SHMEM is not set
2247 +CONFIG_BASE_SMALL=0
2248 +CONFIG_MODULES=y
2249 +# CONFIG_MODULE_FORCE_LOAD is not set
2250 +CONFIG_MODULE_UNLOAD=y
2251 +CONFIG_MODULE_FORCE_UNLOAD=y
2252 +# CONFIG_MODVERSIONS is not set
2253 +# CONFIG_MODULE_SRCVERSION_ALL is not set
2254 +CONFIG_KMOD=y
2255 +CONFIG_BLOCK=y
2256 +# CONFIG_LBD is not set
2257 +# CONFIG_BLK_DEV_IO_TRACE is not set
2258 +# CONFIG_LSF is not set
2259 +# CONFIG_BLK_DEV_BSG is not set
2260 +# CONFIG_BLK_DEV_INTEGRITY is not set
2261 +
2262 +#
2263 +# IO Schedulers
2264 +#
2265 +CONFIG_IOSCHED_NOOP=y
2266 +CONFIG_IOSCHED_AS=m
2267 +CONFIG_IOSCHED_DEADLINE=y
2268 +CONFIG_IOSCHED_CFQ=m
2269 +# CONFIG_DEFAULT_AS is not set
2270 +CONFIG_DEFAULT_DEADLINE=y
2271 +# CONFIG_DEFAULT_CFQ is not set
2272 +# CONFIG_DEFAULT_NOOP is not set
2273 +CONFIG_DEFAULT_IOSCHED="deadline"
2274 +CONFIG_CLASSIC_RCU=y
2275 +CONFIG_FREEZER=y
2276 +
2277 +#
2278 +# System Type
2279 +#
2280 +# CONFIG_ARCH_AAEC2000 is not set
2281 +# CONFIG_ARCH_INTEGRATOR is not set
2282 +# CONFIG_ARCH_REALVIEW is not set
2283 +# CONFIG_ARCH_VERSATILE is not set
2284 +# CONFIG_ARCH_AT91 is not set
2285 +# CONFIG_ARCH_CLPS7500 is not set
2286 +# CONFIG_ARCH_CLPS711X is not set
2287 +# CONFIG_ARCH_EBSA110 is not set
2288 +# CONFIG_ARCH_EP93XX is not set
2289 +# CONFIG_ARCH_FOOTBRIDGE is not set
2290 +# CONFIG_ARCH_NETX is not set
2291 +# CONFIG_ARCH_H720X is not set
2292 +# CONFIG_ARCH_IMX is not set
2293 +# CONFIG_ARCH_IOP13XX is not set
2294 +# CONFIG_ARCH_IOP32X is not set
2295 +# CONFIG_ARCH_IOP33X is not set
2296 +# CONFIG_ARCH_IXP23XX is not set
2297 +# CONFIG_ARCH_IXP2000 is not set
2298 +# CONFIG_ARCH_IXP4XX is not set
2299 +# CONFIG_ARCH_L7200 is not set
2300 +# CONFIG_ARCH_KIRKWOOD is not set
2301 +# CONFIG_ARCH_KS8695 is not set
2302 +# CONFIG_ARCH_NS9XXX is not set
2303 +# CONFIG_ARCH_LOKI is not set
2304 +# CONFIG_ARCH_MV78XX0 is not set
2305 +# CONFIG_ARCH_MXC is not set
2306 +# CONFIG_ARCH_ORION5X is not set
2307 +# CONFIG_ARCH_PNX4008 is not set
2308 +# CONFIG_ARCH_PXA is not set
2309 +# CONFIG_ARCH_RPC is not set
2310 +# CONFIG_ARCH_SA1100 is not set
2311 +CONFIG_ARCH_S3C2410=y
2312 +# CONFIG_ARCH_S3C64XX is not set
2313 +# CONFIG_ARCH_SHARK is not set
2314 +# CONFIG_ARCH_LH7A40X is not set
2315 +# CONFIG_ARCH_DAVINCI is not set
2316 +# CONFIG_ARCH_OMAP is not set
2317 +# CONFIG_ARCH_MSM is not set
2318 +CONFIG_PLAT_S3C24XX=y
2319 +CONFIG_S3C2410_CLOCK=y
2320 +CONFIG_CPU_S3C244X=y
2321 +CONFIG_S3C24XX_PWM=y
2322 +CONFIG_S3C2410_DMA=y
2323 +# CONFIG_S3C2410_DMA_DEBUG is not set
2324 +CONFIG_MACH_SMDK=y
2325 +CONFIG_MACH_NEO1973=y
2326 +CONFIG_PLAT_S3C=y
2327 +CONFIG_CPU_LLSERIAL_S3C2410=y
2328 +CONFIG_CPU_LLSERIAL_S3C2440=y
2329 +
2330 +#
2331 +# Boot options
2332 +#
2333 +# CONFIG_S3C_BOOT_WATCHDOG is not set
2334 +# CONFIG_S3C_BOOT_ERROR_RESET is not set
2335 +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
2336 +
2337 +#
2338 +# Power management
2339 +#
2340 +# CONFIG_S3C2410_PM_DEBUG is not set
2341 +# CONFIG_S3C2410_PM_CHECK is not set
2342 +CONFIG_S3C_LOWLEVEL_UART_PORT=2
2343 +CONFIG_S3C_GPIO_SPACE=0
2344 +CONFIG_S3C_GPIO_TRACK=y
2345 +
2346 +#
2347 +# S3C2400 Machines
2348 +#
2349 +CONFIG_CPU_S3C2410=y
2350 +CONFIG_CPU_S3C2410_DMA=y
2351 +CONFIG_S3C2410_PM=y
2352 +CONFIG_S3C2410_GPIO=y
2353 +CONFIG_S3C2410_PWM=y
2354 +
2355 +#
2356 +# S3C2410 Machines
2357 +#
2358 +# CONFIG_ARCH_SMDK2410 is not set
2359 +# CONFIG_ARCH_H1940 is not set
2360 +# CONFIG_MACH_N30 is not set
2361 +# CONFIG_ARCH_BAST is not set
2362 +# CONFIG_MACH_OTOM is not set
2363 +# CONFIG_MACH_AML_M5900 is not set
2364 +# CONFIG_MACH_TCT_HAMMER is not set
2365 +# CONFIG_MACH_VR1000 is not set
2366 +CONFIG_MACH_QT2410=y
2367 +# CONFIG_MACH_NEO1973_GTA01 is not set
2368 +
2369 +#
2370 +# S3C2412 Machines
2371 +#
2372 +# CONFIG_MACH_JIVE is not set
2373 +# CONFIG_MACH_SMDK2413 is not set
2374 +# CONFIG_MACH_SMDK2412 is not set
2375 +# CONFIG_MACH_VSTMS is not set
2376 +CONFIG_CPU_S3C2440=y
2377 +CONFIG_S3C2440_DMA=y
2378 +CONFIG_S3C2440_C_FIQ=y
2379 +
2380 +#
2381 +# S3C2440 Machines
2382 +#
2383 +# CONFIG_MACH_ANUBIS is not set
2384 +# CONFIG_MACH_OSIRIS is not set
2385 +# CONFIG_MACH_RX3715 is not set
2386 +CONFIG_ARCH_S3C2440=y
2387 +# CONFIG_MACH_NEXCODER_2440 is not set
2388 +CONFIG_SMDK2440_CPU2440=y
2389 +# CONFIG_MACH_AT2440EVB is not set
2390 +CONFIG_MACH_NEO1973_GTA02=y
2391 +# CONFIG_NEO1973_GTA02_2440 is not set
2392 +CONFIG_CPU_S3C2442=y
2393 +
2394 +#
2395 +# S3C2442 Machines
2396 +#
2397 +CONFIG_SMDK2440_CPU2442=y
2398 +
2399 +#
2400 +# S3C2443 Machines
2401 +#
2402 +# CONFIG_MACH_SMDK2443 is not set
2403 +
2404 +#
2405 +# Processor Type
2406 +#
2407 +CONFIG_CPU_32=y
2408 +CONFIG_CPU_ARM920T=y
2409 +CONFIG_CPU_32v4T=y
2410 +CONFIG_CPU_ABRT_EV4T=y
2411 +CONFIG_CPU_PABRT_NOIFAR=y
2412 +CONFIG_CPU_CACHE_V4WT=y
2413 +CONFIG_CPU_CACHE_VIVT=y
2414 +CONFIG_CPU_COPY_V4WB=y
2415 +CONFIG_CPU_TLB_V4WBI=y
2416 +CONFIG_CPU_CP15=y
2417 +CONFIG_CPU_CP15_MMU=y
2418 +
2419 +#
2420 +# Processor Features
2421 +#
2422 +CONFIG_ARM_THUMB=y
2423 +# CONFIG_CPU_ICACHE_DISABLE is not set
2424 +# CONFIG_CPU_DCACHE_DISABLE is not set
2425 +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
2426 +# CONFIG_OUTER_CACHE is not set
2427 +
2428 +#
2429 +# Bus support
2430 +#
2431 +# CONFIG_PCI_SYSCALL is not set
2432 +# CONFIG_ARCH_SUPPORTS_MSI is not set
2433 +# CONFIG_PCCARD is not set
2434 +
2435 +#
2436 +# Kernel Features
2437 +#
2438 +CONFIG_VMSPLIT_3G=y
2439 +# CONFIG_VMSPLIT_2G is not set
2440 +# CONFIG_VMSPLIT_1G is not set
2441 +CONFIG_PAGE_OFFSET=0xC0000000
2442 +CONFIG_PREEMPT=y
2443 +CONFIG_HZ=200
2444 +CONFIG_AEABI=y
2445 +CONFIG_OABI_COMPAT=y
2446 +CONFIG_ARCH_FLATMEM_HAS_HOLES=y
2447 +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
2448 +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
2449 +CONFIG_SELECT_MEMORY_MODEL=y
2450 +CONFIG_FLATMEM_MANUAL=y
2451 +# CONFIG_DISCONTIGMEM_MANUAL is not set
2452 +# CONFIG_SPARSEMEM_MANUAL is not set
2453 +CONFIG_FLATMEM=y
2454 +CONFIG_FLAT_NODE_MEM_MAP=y
2455 +CONFIG_PAGEFLAGS_EXTENDED=y
2456 +CONFIG_SPLIT_PTLOCK_CPUS=4096
2457 +# CONFIG_RESOURCES_64BIT is not set
2458 +# CONFIG_PHYS_ADDR_T_64BIT is not set
2459 +CONFIG_ZONE_DMA_FLAG=0
2460 +CONFIG_VIRT_TO_BUS=y
2461 +CONFIG_UNEVICTABLE_LRU=y
2462 +CONFIG_ALIGNMENT_TRAP=y
2463 +
2464 +#
2465 +# Boot options
2466 +#
2467 +CONFIG_ZBOOT_ROM_TEXT=0x0
2468 +CONFIG_ZBOOT_ROM_BSS=0x0
2469 +CONFIG_CMDLINE="unused -- bootloader passes ATAG list"
2470 +# CONFIG_XIP_KERNEL is not set
2471 +CONFIG_KEXEC=y
2472 +CONFIG_ATAGS_PROC=y
2473 +
2474 +#
2475 +# CPU Power Management
2476 +#
2477 +CONFIG_CPU_IDLE=y
2478 +CONFIG_CPU_IDLE_GOV_LADDER=y
2479 +
2480 +#
2481 +# Floating point emulation
2482 +#
2483 +
2484 +#
2485 +# At least one emulation must be selected
2486 +#
2487 +CONFIG_FPE_NWFPE=y
2488 +# CONFIG_FPE_NWFPE_XP is not set
2489 +# CONFIG_FPE_FASTFPE is not set
2490 +
2491 +#
2492 +# Userspace binary formats
2493 +#
2494 +CONFIG_BINFMT_ELF=y
2495 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
2496 +CONFIG_HAVE_AOUT=y
2497 +# CONFIG_BINFMT_AOUT is not set
2498 +# CONFIG_BINFMT_MISC is not set
2499 +
2500 +#
2501 +# Power management options
2502 +#
2503 +CONFIG_PM=y
2504 +# CONFIG_PM_DEBUG is not set
2505 +CONFIG_PM_SLEEP=y
2506 +CONFIG_SUSPEND=y
2507 +CONFIG_SUSPEND_FREEZER=y
2508 +CONFIG_APM_EMULATION=y
2509 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
2510 +CONFIG_NET=y
2511 +
2512 +#
2513 +# Networking options
2514 +#
2515 +CONFIG_PACKET=y
2516 +CONFIG_PACKET_MMAP=y
2517 +CONFIG_UNIX=y
2518 +CONFIG_XFRM=y
2519 +# CONFIG_XFRM_USER is not set
2520 +# CONFIG_XFRM_SUB_POLICY is not set
2521 +CONFIG_XFRM_MIGRATE=y
2522 +# CONFIG_XFRM_STATISTICS is not set
2523 +CONFIG_XFRM_IPCOMP=m
2524 +CONFIG_NET_KEY=m
2525 +CONFIG_NET_KEY_MIGRATE=y
2526 +CONFIG_INET=y
2527 +CONFIG_IP_MULTICAST=y
2528 +CONFIG_IP_ADVANCED_ROUTER=y
2529 +CONFIG_ASK_IP_FIB_HASH=y
2530 +# CONFIG_IP_FIB_TRIE is not set
2531 +CONFIG_IP_FIB_HASH=y
2532 +CONFIG_IP_MULTIPLE_TABLES=y
2533 +# CONFIG_IP_ROUTE_MULTIPATH is not set
2534 +# CONFIG_IP_ROUTE_VERBOSE is not set
2535 +CONFIG_IP_PNP=y
2536 +# CONFIG_IP_PNP_DHCP is not set
2537 +# CONFIG_IP_PNP_BOOTP is not set
2538 +# CONFIG_IP_PNP_RARP is not set
2539 +CONFIG_NET_IPIP=m
2540 +CONFIG_NET_IPGRE=m
2541 +# CONFIG_NET_IPGRE_BROADCAST is not set
2542 +# CONFIG_IP_MROUTE is not set
2543 +# CONFIG_ARPD is not set
2544 +CONFIG_SYN_COOKIES=y
2545 +CONFIG_INET_AH=m
2546 +CONFIG_INET_ESP=m
2547 +CONFIG_INET_IPCOMP=m
2548 +CONFIG_INET_XFRM_TUNNEL=m
2549 +CONFIG_INET_TUNNEL=m
2550 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
2551 +CONFIG_INET_XFRM_MODE_TUNNEL=m
2552 +CONFIG_INET_XFRM_MODE_BEET=m
2553 +# CONFIG_INET_LRO is not set
2554 +CONFIG_INET_DIAG=y
2555 +CONFIG_INET_TCP_DIAG=y
2556 +# CONFIG_TCP_CONG_ADVANCED is not set
2557 +CONFIG_TCP_CONG_CUBIC=y
2558 +CONFIG_DEFAULT_TCP_CONG="cubic"
2559 +CONFIG_TCP_MD5SIG=y
2560 +CONFIG_IPV6=m
2561 +# CONFIG_IPV6_PRIVACY is not set
2562 +# CONFIG_IPV6_ROUTER_PREF is not set
2563 +# CONFIG_IPV6_OPTIMISTIC_DAD is not set
2564 +CONFIG_INET6_AH=m
2565 +CONFIG_INET6_ESP=m
2566 +CONFIG_INET6_IPCOMP=m
2567 +# CONFIG_IPV6_MIP6 is not set
2568 +CONFIG_INET6_XFRM_TUNNEL=m
2569 +CONFIG_INET6_TUNNEL=m
2570 +CONFIG_INET6_XFRM_MODE_TRANSPORT=m
2571 +CONFIG_INET6_XFRM_MODE_TUNNEL=m
2572 +CONFIG_INET6_XFRM_MODE_BEET=m
2573 +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
2574 +CONFIG_IPV6_SIT=m
2575 +CONFIG_IPV6_NDISC_NODETYPE=y
2576 +CONFIG_IPV6_TUNNEL=m
2577 +# CONFIG_IPV6_MULTIPLE_TABLES is not set
2578 +# CONFIG_IPV6_MROUTE is not set
2579 +# CONFIG_NETWORK_SECMARK is not set
2580 +CONFIG_NETFILTER=y
2581 +# CONFIG_NETFILTER_DEBUG is not set
2582 +CONFIG_NETFILTER_ADVANCED=y
2583 +CONFIG_BRIDGE_NETFILTER=y
2584 +
2585 +#
2586 +# Core Netfilter Configuration
2587 +#
2588 +CONFIG_NETFILTER_NETLINK=m
2589 +CONFIG_NETFILTER_NETLINK_QUEUE=m
2590 +CONFIG_NETFILTER_NETLINK_LOG=m
2591 +CONFIG_NF_CONNTRACK=m
2592 +CONFIG_NF_CT_ACCT=y
2593 +CONFIG_NF_CONNTRACK_MARK=y
2594 +# CONFIG_NF_CONNTRACK_EVENTS is not set
2595 +# CONFIG_NF_CT_PROTO_DCCP is not set
2596 +CONFIG_NF_CT_PROTO_GRE=m
2597 +CONFIG_NF_CT_PROTO_SCTP=m
2598 +# CONFIG_NF_CT_PROTO_UDPLITE is not set
2599 +# CONFIG_NF_CONNTRACK_AMANDA is not set
2600 +CONFIG_NF_CONNTRACK_FTP=m
2601 +CONFIG_NF_CONNTRACK_H323=m
2602 +CONFIG_NF_CONNTRACK_IRC=m
2603 +CONFIG_NF_CONNTRACK_NETBIOS_NS=m
2604 +CONFIG_NF_CONNTRACK_PPTP=m
2605 +CONFIG_NF_CONNTRACK_SANE=m
2606 +CONFIG_NF_CONNTRACK_SIP=m
2607 +CONFIG_NF_CONNTRACK_TFTP=m
2608 +CONFIG_NF_CT_NETLINK=m
2609 +# CONFIG_NETFILTER_TPROXY is not set
2610 +CONFIG_NETFILTER_XTABLES=m
2611 +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
2612 +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
2613 +CONFIG_NETFILTER_XT_TARGET_DSCP=m
2614 +CONFIG_NETFILTER_XT_TARGET_MARK=m
2615 +CONFIG_NETFILTER_XT_TARGET_NFLOG=m
2616 +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
2617 +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
2618 +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
2619 +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
2620 +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
2621 +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
2622 +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
2623 +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
2624 +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
2625 +CONFIG_NETFILTER_XT_MATCH_DCCP=m
2626 +CONFIG_NETFILTER_XT_MATCH_DSCP=m
2627 +CONFIG_NETFILTER_XT_MATCH_ESP=m
2628 +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
2629 +CONFIG_NETFILTER_XT_MATCH_HELPER=m
2630 +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
2631 +CONFIG_NETFILTER_XT_MATCH_LENGTH=m
2632 +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
2633 +CONFIG_NETFILTER_XT_MATCH_MAC=m
2634 +CONFIG_NETFILTER_XT_MATCH_MARK=m
2635 +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
2636 +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
2637 +CONFIG_NETFILTER_XT_MATCH_POLICY=m
2638 +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
2639 +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
2640 +CONFIG_NETFILTER_XT_MATCH_QUOTA=m
2641 +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
2642 +CONFIG_NETFILTER_XT_MATCH_REALM=m
2643 +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
2644 +CONFIG_NETFILTER_XT_MATCH_SCTP=m
2645 +CONFIG_NETFILTER_XT_MATCH_STATE=m
2646 +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
2647 +CONFIG_NETFILTER_XT_MATCH_STRING=m
2648 +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
2649 +# CONFIG_NETFILTER_XT_MATCH_TIME is not set
2650 +# CONFIG_NETFILTER_XT_MATCH_U32 is not set
2651 +# CONFIG_IP_VS is not set
2652 +
2653 +#
2654 +# IP: Netfilter Configuration
2655 +#
2656 +CONFIG_NF_DEFRAG_IPV4=m
2657 +CONFIG_NF_CONNTRACK_IPV4=m
2658 +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
2659 +# CONFIG_IP_NF_QUEUE is not set
2660 +CONFIG_IP_NF_IPTABLES=m
2661 +CONFIG_IP_NF_MATCH_ADDRTYPE=m
2662 +CONFIG_IP_NF_MATCH_AH=m
2663 +CONFIG_IP_NF_MATCH_ECN=m
2664 +CONFIG_IP_NF_MATCH_TTL=m
2665 +CONFIG_IP_NF_FILTER=m
2666 +CONFIG_IP_NF_TARGET_REJECT=m
2667 +CONFIG_IP_NF_TARGET_LOG=m
2668 +CONFIG_IP_NF_TARGET_ULOG=m
2669 +CONFIG_NF_NAT=m
2670 +CONFIG_NF_NAT_NEEDED=y
2671 +CONFIG_IP_NF_TARGET_MASQUERADE=m
2672 +CONFIG_IP_NF_TARGET_NETMAP=m
2673 +CONFIG_IP_NF_TARGET_REDIRECT=m
2674 +CONFIG_NF_NAT_SNMP_BASIC=m
2675 +CONFIG_NF_NAT_PROTO_GRE=m
2676 +CONFIG_NF_NAT_PROTO_SCTP=m
2677 +CONFIG_NF_NAT_FTP=m
2678 +CONFIG_NF_NAT_IRC=m
2679 +CONFIG_NF_NAT_TFTP=m
2680 +# CONFIG_NF_NAT_AMANDA is not set
2681 +CONFIG_NF_NAT_PPTP=m
2682 +CONFIG_NF_NAT_H323=m
2683 +CONFIG_NF_NAT_SIP=m
2684 +CONFIG_IP_NF_MANGLE=m
2685 +CONFIG_IP_NF_TARGET_CLUSTERIP=m
2686 +CONFIG_IP_NF_TARGET_ECN=m
2687 +CONFIG_IP_NF_TARGET_TTL=m
2688 +# CONFIG_IP_NF_RAW is not set
2689 +# CONFIG_IP_NF_ARPTABLES is not set
2690 +
2691 +#
2692 +# IPv6: Netfilter Configuration
2693 +#
2694 +CONFIG_NF_CONNTRACK_IPV6=m
2695 +# CONFIG_IP6_NF_QUEUE is not set
2696 +CONFIG_IP6_NF_IPTABLES=m
2697 +CONFIG_IP6_NF_MATCH_AH=m
2698 +CONFIG_IP6_NF_MATCH_EUI64=m
2699 +CONFIG_IP6_NF_MATCH_FRAG=m
2700 +CONFIG_IP6_NF_MATCH_OPTS=m
2701 +CONFIG_IP6_NF_MATCH_HL=m
2702 +CONFIG_IP6_NF_MATCH_IPV6HEADER=m
2703 +CONFIG_IP6_NF_MATCH_MH=m
2704 +CONFIG_IP6_NF_MATCH_RT=m
2705 +CONFIG_IP6_NF_TARGET_LOG=m
2706 +CONFIG_IP6_NF_FILTER=m
2707 +CONFIG_IP6_NF_TARGET_REJECT=m
2708 +CONFIG_IP6_NF_MANGLE=m
2709 +CONFIG_IP6_NF_TARGET_HL=m
2710 +# CONFIG_IP6_NF_RAW is not set
2711 +CONFIG_BRIDGE_NF_EBTABLES=m
2712 +CONFIG_BRIDGE_EBT_BROUTE=m
2713 +CONFIG_BRIDGE_EBT_T_FILTER=m
2714 +CONFIG_BRIDGE_EBT_T_NAT=m
2715 +CONFIG_BRIDGE_EBT_802_3=m
2716 +CONFIG_BRIDGE_EBT_AMONG=m
2717 +CONFIG_BRIDGE_EBT_ARP=m
2718 +CONFIG_BRIDGE_EBT_IP=m
2719 +# CONFIG_BRIDGE_EBT_IP6 is not set
2720 +CONFIG_BRIDGE_EBT_LIMIT=m
2721 +CONFIG_BRIDGE_EBT_MARK=m
2722 +CONFIG_BRIDGE_EBT_PKTTYPE=m
2723 +CONFIG_BRIDGE_EBT_STP=m
2724 +CONFIG_BRIDGE_EBT_VLAN=m
2725 +CONFIG_BRIDGE_EBT_ARPREPLY=m
2726 +CONFIG_BRIDGE_EBT_DNAT=m
2727 +CONFIG_BRIDGE_EBT_MARK_T=m
2728 +CONFIG_BRIDGE_EBT_REDIRECT=m
2729 +CONFIG_BRIDGE_EBT_SNAT=m
2730 +CONFIG_BRIDGE_EBT_LOG=m
2731 +CONFIG_BRIDGE_EBT_ULOG=m
2732 +# CONFIG_BRIDGE_EBT_NFLOG is not set
2733 +# CONFIG_IP_DCCP is not set
2734 +# CONFIG_IP_SCTP is not set
2735 +# CONFIG_TIPC is not set
2736 +# CONFIG_ATM is not set
2737 +CONFIG_STP=y
2738 +CONFIG_BRIDGE=y
2739 +# CONFIG_NET_DSA is not set
2740 +# CONFIG_VLAN_8021Q is not set
2741 +# CONFIG_DECNET is not set
2742 +CONFIG_LLC=y
2743 +# CONFIG_LLC2 is not set
2744 +# CONFIG_IPX is not set
2745 +# CONFIG_ATALK is not set
2746 +# CONFIG_X25 is not set
2747 +# CONFIG_LAPB is not set
2748 +# CONFIG_ECONET is not set
2749 +# CONFIG_WAN_ROUTER is not set
2750 +CONFIG_NET_SCHED=y
2751 +
2752 +#
2753 +# Queueing/Scheduling
2754 +#
2755 +CONFIG_NET_SCH_CBQ=m
2756 +CONFIG_NET_SCH_HTB=m
2757 +CONFIG_NET_SCH_HFSC=m
2758 +CONFIG_NET_SCH_PRIO=m
2759 +# CONFIG_NET_SCH_MULTIQ is not set
2760 +CONFIG_NET_SCH_RED=m
2761 +CONFIG_NET_SCH_SFQ=m
2762 +CONFIG_NET_SCH_TEQL=m
2763 +CONFIG_NET_SCH_TBF=m
2764 +CONFIG_NET_SCH_GRED=m
2765 +CONFIG_NET_SCH_DSMARK=m
2766 +CONFIG_NET_SCH_NETEM=m
2767 +
2768 +#
2769 +# Classification
2770 +#
2771 +CONFIG_NET_CLS=y
2772 +CONFIG_NET_CLS_BASIC=m
2773 +CONFIG_NET_CLS_TCINDEX=m
2774 +CONFIG_NET_CLS_ROUTE4=m
2775 +CONFIG_NET_CLS_ROUTE=y
2776 +CONFIG_NET_CLS_FW=m
2777 +CONFIG_NET_CLS_U32=m
2778 +CONFIG_CLS_U32_PERF=y
2779 +CONFIG_CLS_U32_MARK=y
2780 +CONFIG_NET_CLS_RSVP=m
2781 +CONFIG_NET_CLS_RSVP6=m
2782 +# CONFIG_NET_CLS_FLOW is not set
2783 +# CONFIG_NET_EMATCH is not set
2784 +# CONFIG_NET_CLS_ACT is not set
2785 +# CONFIG_NET_CLS_IND is not set
2786 +CONFIG_NET_SCH_FIFO=y
2787 +
2788 +#
2789 +# Network testing
2790 +#
2791 +# CONFIG_NET_PKTGEN is not set
2792 +# CONFIG_HAMRADIO is not set
2793 +# CONFIG_CAN is not set
2794 +# CONFIG_IRDA is not set
2795 +CONFIG_BT=m
2796 +CONFIG_BT_L2CAP=m
2797 +CONFIG_BT_SCO=m
2798 +CONFIG_BT_RFCOMM=m
2799 +CONFIG_BT_RFCOMM_TTY=y
2800 +CONFIG_BT_BNEP=m
2801 +CONFIG_BT_BNEP_MC_FILTER=y
2802 +CONFIG_BT_BNEP_PROTO_FILTER=y
2803 +CONFIG_BT_HIDP=m
2804 +
2805 +#
2806 +# Bluetooth device drivers
2807 +#
2808 +CONFIG_BT_HCIBTUSB=m
2809 +# CONFIG_BT_HCIBTSDIO is not set
2810 +# CONFIG_BT_HCIUART is not set
2811 +# CONFIG_BT_HCIBCM203X is not set
2812 +# CONFIG_BT_HCIBPA10X is not set
2813 +# CONFIG_BT_HCIBFUSB is not set
2814 +# CONFIG_BT_HCIVHCI is not set
2815 +# CONFIG_AF_RXRPC is not set
2816 +# CONFIG_PHONET is not set
2817 +CONFIG_FIB_RULES=y
2818 +CONFIG_WIRELESS=y
2819 +# CONFIG_CFG80211 is not set
2820 +# CONFIG_WIRELESS_OLD_REGULATORY is not set
2821 +CONFIG_WIRELESS_EXT=y
2822 +CONFIG_WIRELESS_EXT_SYSFS=y
2823 +# CONFIG_MAC80211 is not set
2824 +# CONFIG_IEEE80211 is not set
2825 +CONFIG_RFKILL=y
2826 +CONFIG_RFKILL_INPUT=y
2827 +CONFIG_RFKILL_LEDS=y
2828 +# CONFIG_NET_9P is not set
2829 +
2830 +#
2831 +# Device Drivers
2832 +#
2833 +
2834 +#
2835 +# Generic Driver Options
2836 +#
2837 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
2838 +CONFIG_STANDALONE=y
2839 +CONFIG_PREVENT_FIRMWARE_BUILD=y
2840 +CONFIG_FW_LOADER=y
2841 +# CONFIG_FIRMWARE_IN_KERNEL is not set
2842 +CONFIG_EXTRA_FIRMWARE=""
2843 +# CONFIG_DEBUG_DRIVER is not set
2844 +# CONFIG_DEBUG_DEVRES is not set
2845 +# CONFIG_SYS_HYPERVISOR is not set
2846 +CONFIG_CONNECTOR=m
2847 +CONFIG_MTD=y
2848 +# CONFIG_MTD_DEBUG is not set
2849 +CONFIG_MTD_CONCAT=y
2850 +CONFIG_MTD_PARTITIONS=y
2851 +# CONFIG_MTD_REDBOOT_PARTS is not set
2852 +CONFIG_MTD_CMDLINE_PARTS=y
2853 +# CONFIG_MTD_AFS_PARTS is not set
2854 +# CONFIG_MTD_AR7_PARTS is not set
2855 +
2856 +#
2857 +# User Modules And Translation Layers
2858 +#
2859 +CONFIG_MTD_CHAR=y
2860 +CONFIG_MTD_BLKDEVS=y
2861 +CONFIG_MTD_BLOCK=y
2862 +# CONFIG_FTL is not set
2863 +# CONFIG_NFTL is not set
2864 +# CONFIG_INFTL is not set
2865 +# CONFIG_RFD_FTL is not set
2866 +# CONFIG_SSFDC is not set
2867 +# CONFIG_MTD_OOPS is not set
2868 +
2869 +#
2870 +# RAM/ROM/Flash chip drivers
2871 +#
2872 +CONFIG_MTD_CFI=y
2873 +# CONFIG_MTD_JEDECPROBE is not set
2874 +CONFIG_MTD_GEN_PROBE=y
2875 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
2876 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
2877 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
2878 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
2879 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
2880 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
2881 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
2882 +CONFIG_MTD_CFI_I1=y
2883 +CONFIG_MTD_CFI_I2=y
2884 +# CONFIG_MTD_CFI_I4 is not set
2885 +# CONFIG_MTD_CFI_I8 is not set
2886 +CONFIG_MTD_CFI_INTELEXT=y
2887 +# CONFIG_MTD_CFI_AMDSTD is not set
2888 +# CONFIG_MTD_CFI_STAA is not set
2889 +CONFIG_MTD_CFI_UTIL=y
2890 +# CONFIG_MTD_RAM is not set
2891 +CONFIG_MTD_ROM=y
2892 +CONFIG_MTD_ABSENT=y
2893 +
2894 +#
2895 +# Mapping drivers for chip access
2896 +#
2897 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
2898 +CONFIG_MTD_PHYSMAP=y
2899 +CONFIG_MTD_PHYSMAP_START=0x0
2900 +CONFIG_MTD_PHYSMAP_LEN=0
2901 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2
2902 +# CONFIG_MTD_ARM_INTEGRATOR is not set
2903 +# CONFIG_MTD_PLATRAM is not set
2904 +
2905 +#
2906 +# Self-contained MTD device drivers
2907 +#
2908 +# CONFIG_MTD_DATAFLASH is not set
2909 +# CONFIG_MTD_M25P80 is not set
2910 +# CONFIG_MTD_SLRAM is not set
2911 +# CONFIG_MTD_PHRAM is not set
2912 +# CONFIG_MTD_MTDRAM is not set
2913 +# CONFIG_MTD_BLOCK2MTD is not set
2914 +
2915 +#
2916 +# Disk-On-Chip Device Drivers
2917 +#
2918 +# CONFIG_MTD_DOC2000 is not set
2919 +# CONFIG_MTD_DOC2001 is not set
2920 +# CONFIG_MTD_DOC2001PLUS is not set
2921 +CONFIG_MTD_NAND=y
2922 +CONFIG_MTD_NAND_VERIFY_WRITE=y
2923 +# CONFIG_MTD_NAND_ECC_SMC is not set
2924 +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
2925 +# CONFIG_MTD_NAND_GPIO is not set
2926 +CONFIG_MTD_NAND_IDS=y
2927 +CONFIG_MTD_NAND_S3C2410=y
2928 +CONFIG_MTD_NAND_S3C2410_DEBUG=y
2929 +CONFIG_MTD_NAND_S3C2410_HWECC=y
2930 +# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
2931 +# CONFIG_MTD_NAND_DISKONCHIP is not set
2932 +# CONFIG_MTD_NAND_NANDSIM is not set
2933 +# CONFIG_MTD_NAND_PLATFORM is not set
2934 +# CONFIG_MTD_ALAUDA is not set
2935 +# CONFIG_MTD_ONENAND is not set
2936 +
2937 +#
2938 +# UBI - Unsorted block images
2939 +#
2940 +# CONFIG_MTD_UBI is not set
2941 +# CONFIG_PARPORT is not set
2942 +CONFIG_BLK_DEV=y
2943 +# CONFIG_BLK_DEV_COW_COMMON is not set
2944 +CONFIG_BLK_DEV_LOOP=m
2945 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
2946 +# CONFIG_BLK_DEV_NBD is not set
2947 +CONFIG_BLK_DEV_UB=m
2948 +CONFIG_BLK_DEV_RAM=y
2949 +CONFIG_BLK_DEV_RAM_COUNT=16
2950 +CONFIG_BLK_DEV_RAM_SIZE=4096
2951 +# CONFIG_BLK_DEV_XIP is not set
2952 +# CONFIG_CDROM_PKTCDVD is not set
2953 +# CONFIG_ATA_OVER_ETH is not set
2954 +CONFIG_MISC_DEVICES=y
2955 +# CONFIG_EEPROM_93CX6 is not set
2956 +CONFIG_LOW_MEMORY_KILLER=y
2957 +# CONFIG_ENCLOSURE_SERVICES is not set
2958 +CONFIG_HAVE_IDE=y
2959 +# CONFIG_IDE is not set
2960 +
2961 +#
2962 +# SCSI device support
2963 +#
2964 +# CONFIG_RAID_ATTRS is not set
2965 +CONFIG_SCSI=m
2966 +CONFIG_SCSI_DMA=y
2967 +# CONFIG_SCSI_TGT is not set
2968 +# CONFIG_SCSI_NETLINK is not set
2969 +CONFIG_SCSI_PROC_FS=y
2970 +
2971 +#
2972 +# SCSI support type (disk, tape, CD-ROM)
2973 +#
2974 +CONFIG_BLK_DEV_SD=m
2975 +# CONFIG_CHR_DEV_ST is not set
2976 +# CONFIG_CHR_DEV_OSST is not set
2977 +CONFIG_BLK_DEV_SR=m
2978 +# CONFIG_BLK_DEV_SR_VENDOR is not set
2979 +CONFIG_CHR_DEV_SG=m
2980 +# CONFIG_CHR_DEV_SCH is not set
2981 +
2982 +#
2983 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
2984 +#
2985 +CONFIG_SCSI_MULTI_LUN=y
2986 +# CONFIG_SCSI_CONSTANTS is not set
2987 +# CONFIG_SCSI_LOGGING is not set
2988 +CONFIG_SCSI_SCAN_ASYNC=y
2989 +CONFIG_SCSI_WAIT_SCAN=m
2990 +
2991 +#
2992 +# SCSI Transports
2993 +#
2994 +# CONFIG_SCSI_SPI_ATTRS is not set
2995 +# CONFIG_SCSI_FC_ATTRS is not set
2996 +# CONFIG_SCSI_ISCSI_ATTRS is not set
2997 +# CONFIG_SCSI_SAS_LIBSAS is not set
2998 +# CONFIG_SCSI_SRP_ATTRS is not set
2999 +CONFIG_SCSI_LOWLEVEL=y
3000 +# CONFIG_ISCSI_TCP is not set
3001 +# CONFIG_SCSI_DEBUG is not set
3002 +# CONFIG_SCSI_DH is not set
3003 +# CONFIG_ATA is not set
3004 +CONFIG_MD=y
3005 +# CONFIG_BLK_DEV_MD is not set
3006 +CONFIG_BLK_DEV_DM=m
3007 +# CONFIG_DM_DEBUG is not set
3008 +CONFIG_DM_CRYPT=m
3009 +CONFIG_DM_SNAPSHOT=m
3010 +# CONFIG_DM_MIRROR is not set
3011 +# CONFIG_DM_ZERO is not set
3012 +# CONFIG_DM_MULTIPATH is not set
3013 +# CONFIG_DM_DELAY is not set
3014 +# CONFIG_DM_UEVENT is not set
3015 +CONFIG_NETDEVICES=y
3016 +# CONFIG_DUMMY is not set
3017 +# CONFIG_BONDING is not set
3018 +# CONFIG_MACVLAN is not set
3019 +# CONFIG_EQUALIZER is not set
3020 +CONFIG_TUN=m
3021 +# CONFIG_VETH is not set
3022 +# CONFIG_PHYLIB is not set
3023 +CONFIG_NET_ETHERNET=y
3024 +CONFIG_MII=y
3025 +# CONFIG_AX88796 is not set
3026 +# CONFIG_SMC91X is not set
3027 +# CONFIG_DM9000 is not set
3028 +# CONFIG_ENC28J60 is not set
3029 +# CONFIG_SMC911X is not set
3030 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
3031 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
3032 +# CONFIG_IBM_NEW_EMAC_TAH is not set
3033 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
3034 +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
3035 +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
3036 +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
3037 +# CONFIG_B44 is not set
3038 +# CONFIG_NETDEV_1000 is not set
3039 +# CONFIG_NETDEV_10000 is not set
3040 +
3041 +#
3042 +# Wireless LAN
3043 +#
3044 +# CONFIG_WLAN_PRE80211 is not set
3045 +# CONFIG_WLAN_80211 is not set
3046 +# CONFIG_IWLWIFI_LEDS is not set
3047 +
3048 +#
3049 +# USB Network Adapters
3050 +#
3051 +CONFIG_USB_CATC=m
3052 +CONFIG_USB_KAWETH=m
3053 +CONFIG_USB_PEGASUS=m
3054 +CONFIG_USB_RTL8150=m
3055 +CONFIG_USB_USBNET=y
3056 +CONFIG_USB_NET_AX8817X=m
3057 +CONFIG_USB_NET_CDCETHER=m
3058 +CONFIG_USB_NET_DM9601=m
3059 +# CONFIG_USB_NET_SMSC95XX is not set
3060 +CONFIG_USB_NET_GL620A=m
3061 +CONFIG_USB_NET_NET1080=m
3062 +CONFIG_USB_NET_PLUSB=m
3063 +CONFIG_USB_NET_MCS7830=m
3064 +CONFIG_USB_NET_RNDIS_HOST=m
3065 +CONFIG_USB_NET_CDC_SUBSET=m
3066 +CONFIG_USB_ALI_M5632=y
3067 +CONFIG_USB_AN2720=y
3068 +CONFIG_USB_BELKIN=y
3069 +CONFIG_USB_ARMLINUX=y
3070 +CONFIG_USB_EPSON2888=y
3071 +CONFIG_USB_KC2190=y
3072 +CONFIG_USB_NET_ZAURUS=m
3073 +# CONFIG_USB_HSO is not set
3074 +# CONFIG_WAN is not set
3075 +CONFIG_PPP=m
3076 +CONFIG_PPP_MULTILINK=y
3077 +CONFIG_PPP_FILTER=y
3078 +CONFIG_PPP_ASYNC=m
3079 +CONFIG_PPP_SYNC_TTY=m
3080 +CONFIG_PPP_DEFLATE=m
3081 +CONFIG_PPP_BSDCOMP=m
3082 +CONFIG_PPP_MPPE=m
3083 +# CONFIG_PPPOE is not set
3084 +# CONFIG_PPPOL2TP is not set
3085 +# CONFIG_SLIP is not set
3086 +CONFIG_SLHC=m
3087 +# CONFIG_NETCONSOLE is not set
3088 +# CONFIG_NETPOLL is not set
3089 +# CONFIG_NET_POLL_CONTROLLER is not set
3090 +# CONFIG_ISDN is not set
3091 +
3092 +#
3093 +# Input device support
3094 +#
3095 +CONFIG_INPUT=y
3096 +# CONFIG_INPUT_FF_MEMLESS is not set
3097 +# CONFIG_INPUT_POLLDEV is not set
3098 +
3099 +#
3100 +# Userland interfaces
3101 +#
3102 +CONFIG_INPUT_MOUSEDEV=y
3103 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
3104 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
3105 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=640
3106 +# CONFIG_INPUT_JOYDEV is not set
3107 +CONFIG_INPUT_EVDEV=y
3108 +# CONFIG_INPUT_EVBUG is not set
3109 +
3110 +#
3111 +# Input Device Drivers
3112 +#
3113 +CONFIG_INPUT_KEYBOARD=y
3114 +# CONFIG_KEYBOARD_ATKBD is not set
3115 +# CONFIG_KEYBOARD_SUNKBD is not set
3116 +# CONFIG_KEYBOARD_LKKBD is not set
3117 +# CONFIG_KEYBOARD_XTKBD is not set
3118 +# CONFIG_KEYBOARD_NEWTON is not set
3119 +CONFIG_KEYBOARD_STOWAWAY=m
3120 +CONFIG_KEYBOARD_GPIO=m
3121 +CONFIG_KEYBOARD_NEO1973=y
3122 +CONFIG_KEYBOARD_QT2410=y
3123 +CONFIG_INPUT_MOUSE=y
3124 +# CONFIG_MOUSE_PS2 is not set
3125 +# CONFIG_MOUSE_SERIAL is not set
3126 +# CONFIG_MOUSE_APPLETOUCH is not set
3127 +# CONFIG_MOUSE_BCM5974 is not set
3128 +# CONFIG_MOUSE_VSXXXAA is not set
3129 +# CONFIG_MOUSE_GPIO is not set
3130 +# CONFIG_INPUT_JOYSTICK is not set
3131 +# CONFIG_INPUT_TABLET is not set
3132 +CONFIG_INPUT_TOUCHSCREEN=y
3133 +CONFIG_TOUCHSCREEN_FILTER=y
3134 +CONFIG_TOUCHSCREEN_FILTER_GROUP=y
3135 +CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y
3136 +CONFIG_TOUCHSCREEN_FILTER_MEAN=y
3137 +CONFIG_TOUCHSCREEN_FILTER_LINEAR=y
3138 +# CONFIG_TOUCHSCREEN_ADS7846 is not set
3139 +# CONFIG_TOUCHSCREEN_FUJITSU is not set
3140 +CONFIG_TOUCHSCREEN_S3C2410=y
3141 +# CONFIG_TOUCHSCREEN_S3C2410_DEBUG is not set
3142 +# CONFIG_TOUCHSCREEN_GUNZE is not set
3143 +# CONFIG_TOUCHSCREEN_ELO is not set
3144 +# CONFIG_TOUCHSCREEN_MTOUCH is not set
3145 +# CONFIG_TOUCHSCREEN_INEXIO is not set
3146 +# CONFIG_TOUCHSCREEN_MK712 is not set
3147 +# CONFIG_TOUCHSCREEN_PENMOUNT is not set
3148 +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
3149 +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
3150 +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
3151 +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
3152 +# CONFIG_TOUCHSCREEN_PCAP7200 is not set
3153 +CONFIG_INPUT_MISC=y
3154 +# CONFIG_INPUT_ATI_REMOTE is not set
3155 +# CONFIG_INPUT_ATI_REMOTE2 is not set
3156 +# CONFIG_INPUT_KEYSPAN_REMOTE is not set
3157 +# CONFIG_INPUT_POWERMATE is not set
3158 +# CONFIG_INPUT_YEALINK is not set
3159 +# CONFIG_INPUT_CM109 is not set
3160 +CONFIG_INPUT_UINPUT=m
3161 +CONFIG_INPUT_LIS302DL=y
3162 +CONFIG_INPUT_PCF50633_PMU=y
3163 +
3164 +#
3165 +# Hardware I/O ports
3166 +#
3167 +CONFIG_SERIO=y
3168 +# CONFIG_SERIO_SERPORT is not set
3169 +# CONFIG_SERIO_RAW is not set
3170 +# CONFIG_GAMEPORT is not set
3171 +
3172 +#
3173 +# Character devices
3174 +#
3175 +CONFIG_VT=y
3176 +CONFIG_CONSOLE_TRANSLATIONS=y
3177 +CONFIG_VT_CONSOLE=y
3178 +CONFIG_NR_TTY_DEVICES=6
3179 +CONFIG_HW_CONSOLE=y
3180 +CONFIG_VT_HW_CONSOLE_BINDING=y
3181 +# CONFIG_DEVKMEM is not set
3182 +# CONFIG_SERIAL_NONSTANDARD is not set
3183 +
3184 +#
3185 +# Serial drivers
3186 +#
3187 +# CONFIG_SERIAL_8250 is not set
3188 +
3189 +#
3190 +# Non-8250 serial port support
3191 +#
3192 +CONFIG_SERIAL_SAMSUNG=y
3193 +CONFIG_SERIAL_SAMSUNG_UARTS=3
3194 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y
3195 +CONFIG_SERIAL_S3C2410=y
3196 +CONFIG_SERIAL_S3C2440=y
3197 +CONFIG_SERIAL_CORE=y
3198 +CONFIG_SERIAL_CORE_CONSOLE=y
3199 +CONFIG_UNIX98_PTYS=y
3200 +# CONFIG_LEGACY_PTYS is not set
3201 +# CONFIG_IPMI_HANDLER is not set
3202 +# CONFIG_HW_RANDOM is not set
3203 +# CONFIG_NVRAM is not set
3204 +# CONFIG_R3964 is not set
3205 +# CONFIG_RAW_DRIVER is not set
3206 +# CONFIG_TCG_TPM is not set
3207 +CONFIG_I2C=y
3208 +CONFIG_I2C_BOARDINFO=y
3209 +CONFIG_I2C_CHARDEV=y
3210 +CONFIG_I2C_HELPER_AUTO=y
3211 +
3212 +#
3213 +# I2C Hardware Bus support
3214 +#
3215 +
3216 +#
3217 +# I2C system bus drivers (mostly embedded / system-on-chip)
3218 +#
3219 +# CONFIG_I2C_GPIO is not set
3220 +# CONFIG_I2C_OCORES is not set
3221 +CONFIG_I2C_S3C2410=y
3222 +# CONFIG_I2C_SIMTEC is not set
3223 +
3224 +#
3225 +# External I2C/SMBus adapter drivers
3226 +#
3227 +# CONFIG_I2C_PARPORT_LIGHT is not set
3228 +# CONFIG_I2C_TAOS_EVM is not set
3229 +# CONFIG_I2C_TINY_USB is not set
3230 +
3231 +#
3232 +# Other I2C/SMBus bus drivers
3233 +#
3234 +# CONFIG_I2C_PCA_PLATFORM is not set
3235 +# CONFIG_I2C_STUB is not set
3236 +
3237 +#
3238 +# Miscellaneous I2C Chip support
3239 +#
3240 +# CONFIG_DS1682 is not set
3241 +# CONFIG_AT24 is not set
3242 +# CONFIG_SENSORS_EEPROM is not set
3243 +# CONFIG_SENSORS_PCF50606 is not set
3244 +# CONFIG_SENSORS_PCF50633 is not set
3245 +# CONFIG_SENSORS_PCF8574 is not set
3246 +# CONFIG_PCF8575 is not set
3247 +# CONFIG_SENSORS_PCA9539 is not set
3248 +# CONFIG_SENSORS_PCF8591 is not set
3249 +# CONFIG_TPS65010 is not set
3250 +# CONFIG_SENSORS_MAX6875 is not set
3251 +# CONFIG_SENSORS_TSL2550 is not set
3252 +# CONFIG_SENSORS_TSL256X is not set
3253 +CONFIG_PCA9632=y
3254 +# CONFIG_I2C_DEBUG_CORE is not set
3255 +# CONFIG_I2C_DEBUG_ALGO is not set
3256 +# CONFIG_I2C_DEBUG_BUS is not set
3257 +# CONFIG_I2C_DEBUG_CHIP is not set
3258 +CONFIG_SPI=y
3259 +# CONFIG_SPI_DEBUG is not set
3260 +CONFIG_SPI_MASTER=y
3261 +
3262 +#
3263 +# SPI Master Controller Drivers
3264 +#
3265 +CONFIG_SPI_BITBANG=y
3266 +# CONFIG_SPI_S3C24XX is not set
3267 +CONFIG_SPI_S3C24XX_GPIO=y
3268 +
3269 +#
3270 +# SPI Protocol Masters
3271 +#
3272 +# CONFIG_SPI_AT25 is not set
3273 +# CONFIG_SPI_SPIDEV is not set
3274 +# CONFIG_SPI_TLE62X0 is not set
3275 +CONFIG_ARCH_REQUIRE_GPIOLIB=y
3276 +CONFIG_GPIOLIB=y
3277 +CONFIG_DEBUG_GPIO=y
3278 +CONFIG_GPIO_SYSFS=y
3279 +
3280 +#
3281 +# I2C GPIO expanders:
3282 +#
3283 +# CONFIG_GPIO_MAX732X is not set
3284 +# CONFIG_GPIO_PCA953X is not set
3285 +# CONFIG_GPIO_PCF857X is not set
3286 +
3287 +#
3288 +# PCI GPIO expanders:
3289 +#
3290 +
3291 +#
3292 +# SPI GPIO expanders:
3293 +#
3294 +# CONFIG_GPIO_MAX7301 is not set
3295 +# CONFIG_GPIO_MCP23S08 is not set
3296 +# CONFIG_W1 is not set
3297 +CONFIG_POWER_SUPPLY=y
3298 +CONFIG_POWER_SUPPLY_DEBUG=y
3299 +CONFIG_PDA_POWER=y
3300 +CONFIG_APM_POWER=y
3301 +# CONFIG_BATTERY_DS2760 is not set
3302 +# CONFIG_BATTERY_BQ27x00 is not set
3303 +CONFIG_BATTERY_BQ27000_HDQ=y
3304 +CONFIG_GTA02_HDQ=y
3305 +CONFIG_CHARGER_PCF50633=y
3306 +CONFIG_HWMON=y
3307 +# CONFIG_HWMON_VID is not set
3308 +# CONFIG_SENSORS_AD7414 is not set
3309 +# CONFIG_SENSORS_AD7418 is not set
3310 +# CONFIG_SENSORS_ADCXX is not set
3311 +# CONFIG_SENSORS_ADM1021 is not set
3312 +# CONFIG_SENSORS_ADM1025 is not set
3313 +# CONFIG_SENSORS_ADM1026 is not set
3314 +# CONFIG_SENSORS_ADM1029 is not set
3315 +# CONFIG_SENSORS_ADM1031 is not set
3316 +# CONFIG_SENSORS_ADM9240 is not set
3317 +# CONFIG_SENSORS_ADT7470 is not set
3318 +# CONFIG_SENSORS_ADT7473 is not set
3319 +# CONFIG_SENSORS_ATXP1 is not set
3320 +# CONFIG_SENSORS_DS1621 is not set
3321 +# CONFIG_SENSORS_F71805F is not set
3322 +# CONFIG_SENSORS_F71882FG is not set
3323 +# CONFIG_SENSORS_F75375S is not set
3324 +# CONFIG_SENSORS_GL518SM is not set
3325 +# CONFIG_SENSORS_GL520SM is not set
3326 +# CONFIG_SENSORS_IT87 is not set
3327 +# CONFIG_SENSORS_LM63 is not set
3328 +# CONFIG_SENSORS_LM70 is not set
3329 +# CONFIG_SENSORS_LM75 is not set
3330 +# CONFIG_SENSORS_LM77 is not set
3331 +# CONFIG_SENSORS_LM78 is not set
3332 +# CONFIG_SENSORS_LM80 is not set
3333 +# CONFIG_SENSORS_LM83 is not set
3334 +# CONFIG_SENSORS_LM85 is not set
3335 +# CONFIG_SENSORS_LM87 is not set
3336 +# CONFIG_SENSORS_LM90 is not set
3337 +# CONFIG_SENSORS_LM92 is not set
3338 +# CONFIG_SENSORS_LM93 is not set
3339 +# CONFIG_SENSORS_MAX1111 is not set
3340 +# CONFIG_SENSORS_MAX1619 is not set
3341 +# CONFIG_SENSORS_MAX6650 is not set
3342 +# CONFIG_SENSORS_PC87360 is not set
3343 +# CONFIG_SENSORS_PC87427 is not set
3344 +# CONFIG_SENSORS_DME1737 is not set
3345 +# CONFIG_SENSORS_SMSC47M1 is not set
3346 +# CONFIG_SENSORS_SMSC47M192 is not set
3347 +# CONFIG_SENSORS_SMSC47B397 is not set
3348 +# CONFIG_SENSORS_ADS7828 is not set
3349 +# CONFIG_SENSORS_THMC50 is not set
3350 +# CONFIG_SENSORS_VT1211 is not set
3351 +# CONFIG_SENSORS_W83781D is not set
3352 +# CONFIG_SENSORS_W83791D is not set
3353 +# CONFIG_SENSORS_W83792D is not set
3354 +# CONFIG_SENSORS_W83793 is not set
3355 +# CONFIG_SENSORS_W83L785TS is not set
3356 +# CONFIG_SENSORS_W83L786NG is not set
3357 +# CONFIG_SENSORS_W83627HF is not set
3358 +# CONFIG_SENSORS_W83627EHF is not set
3359 +# CONFIG_HWMON_DEBUG_CHIP is not set
3360 +# CONFIG_THERMAL is not set
3361 +# CONFIG_THERMAL_HWMON is not set
3362 +CONFIG_WATCHDOG=y
3363 +# CONFIG_WATCHDOG_NOWAYOUT is not set
3364 +
3365 +#
3366 +# Watchdog Device Drivers
3367 +#
3368 +# CONFIG_SOFT_WATCHDOG is not set
3369 +CONFIG_S3C2410_WATCHDOG=m
3370 +
3371 +#
3372 +# USB-based Watchdog Cards
3373 +#
3374 +# CONFIG_USBPCWATCHDOG is not set
3375 +
3376 +#
3377 +# Sonics Silicon Backplane
3378 +#
3379 +CONFIG_SSB_POSSIBLE=y
3380 +# CONFIG_SSB is not set
3381 +
3382 +#
3383 +# Multifunction device drivers
3384 +#
3385 +# CONFIG_MFD_CORE is not set
3386 +# CONFIG_MFD_SM501 is not set
3387 +# CONFIG_MFD_ASIC3 is not set
3388 +# CONFIG_HTC_EGPIO is not set
3389 +# CONFIG_HTC_PASIC3 is not set
3390 +# CONFIG_MFD_TMIO is not set
3391 +# CONFIG_MFD_T7L66XB is not set
3392 +# CONFIG_MFD_TC6387XB is not set
3393 +# CONFIG_MFD_TC6393XB is not set
3394 +# CONFIG_PMIC_DA903X is not set
3395 +# CONFIG_MFD_WM8400 is not set
3396 +# CONFIG_MFD_WM8350_I2C is not set
3397 +CONFIG_MFD_PCF50633=y
3398 +CONFIG_PCF50633_ADC=y
3399 +CONFIG_PCF50633_GPIO=y
3400 +# CONFIG_MFD_PCF50606 is not set
3401 +CONFIG_MFD_GLAMO=y
3402 +CONFIG_MFD_GLAMO_FB=y
3403 +CONFIG_MFD_GLAMO_SPI_GPIO=y
3404 +CONFIG_MFD_GLAMO_SPI_FB=y
3405 +CONFIG_MFD_GLAMO_MCI=y
3406 +
3407 +#
3408 +# Multimedia devices
3409 +#
3410 +
3411 +#
3412 +# Multimedia core support
3413 +#
3414 +# CONFIG_VIDEO_DEV is not set
3415 +# CONFIG_DVB_CORE is not set
3416 +# CONFIG_VIDEO_MEDIA is not set
3417 +
3418 +#
3419 +# Multimedia drivers
3420 +#
3421 +CONFIG_DAB=y
3422 +# CONFIG_USB_DABUSB is not set
3423 +
3424 +#
3425 +# Graphics support
3426 +#
3427 +# CONFIG_VGASTATE is not set
3428 +CONFIG_VIDEO_OUTPUT_CONTROL=y
3429 +CONFIG_FB=y
3430 +# CONFIG_FIRMWARE_EDID is not set
3431 +# CONFIG_FB_DDC is not set
3432 +# CONFIG_FB_BOOT_VESA_SUPPORT is not set
3433 +CONFIG_FB_CFB_FILLRECT=y
3434 +CONFIG_FB_CFB_COPYAREA=y
3435 +CONFIG_FB_CFB_IMAGEBLIT=y
3436 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
3437 +# CONFIG_FB_SYS_FILLRECT is not set
3438 +# CONFIG_FB_SYS_COPYAREA is not set
3439 +# CONFIG_FB_SYS_IMAGEBLIT is not set
3440 +# CONFIG_FB_FOREIGN_ENDIAN is not set
3441 +# CONFIG_FB_SYS_FOPS is not set
3442 +# CONFIG_FB_SVGALIB is not set
3443 +# CONFIG_FB_MACMODES is not set
3444 +# CONFIG_FB_BACKLIGHT is not set
3445 +# CONFIG_FB_MODE_HELPERS is not set
3446 +# CONFIG_FB_TILEBLITTING is not set
3447 +
3448 +#
3449 +# Frame buffer hardware drivers
3450 +#
3451 +# CONFIG_FB_UVESA is not set
3452 +# CONFIG_FB_S1D13XXX is not set
3453 +CONFIG_FB_S3C2410=y
3454 +# CONFIG_FB_S3C2410_DEBUG is not set
3455 +# CONFIG_FB_VIRTUAL is not set
3456 +# CONFIG_FB_METRONOME is not set
3457 +# CONFIG_FB_MB862XX is not set
3458 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
3459 +CONFIG_LCD_CLASS_DEVICE=y
3460 +CONFIG_LCD_LTV350QV=y
3461 +# CONFIG_LCD_ILI9320 is not set
3462 +# CONFIG_LCD_TDO24M is not set
3463 +# CONFIG_LCD_VGG2432A4 is not set
3464 +# CONFIG_LCD_PLATFORM is not set
3465 +CONFIG_BACKLIGHT_CLASS_DEVICE=y
3466 +CONFIG_BACKLIGHT_CORGI=y
3467 +# CONFIG_BACKLIGHT_PWM is not set
3468 +
3469 +#
3470 +# Display device support
3471 +#
3472 +CONFIG_DISPLAY_SUPPORT=y
3473 +
3474 +#
3475 +# Display hardware drivers
3476 +#
3477 +CONFIG_DISPLAY_JBT6K74=y
3478 +
3479 +#
3480 +# Console display driver support
3481 +#
3482 +# CONFIG_VGA_CONSOLE is not set
3483 +CONFIG_DUMMY_CONSOLE=y
3484 +CONFIG_FRAMEBUFFER_CONSOLE=y
3485 +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
3486 +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
3487 +CONFIG_FONTS=y
3488 +# CONFIG_FONT_8x8 is not set
3489 +# CONFIG_FONT_8x16 is not set
3490 +CONFIG_FONT_6x11=y
3491 +# CONFIG_FONT_7x14 is not set
3492 +# CONFIG_FONT_PEARL_8x8 is not set
3493 +# CONFIG_FONT_ACORN_8x8 is not set
3494 +# CONFIG_FONT_MINI_4x6 is not set
3495 +# CONFIG_FONT_SUN8x16 is not set
3496 +# CONFIG_FONT_SUN12x22 is not set
3497 +# CONFIG_FONT_10x18 is not set
3498 +# CONFIG_LOGO is not set
3499 +CONFIG_SOUND=y
3500 +CONFIG_SOUND_OSS_CORE=y
3501 +CONFIG_SND=m
3502 +CONFIG_SND_TIMER=m
3503 +CONFIG_SND_PCM=m
3504 +CONFIG_SND_HWDEP=m
3505 +CONFIG_SND_RAWMIDI=m
3506 +# CONFIG_SND_SEQUENCER is not set
3507 +CONFIG_SND_OSSEMUL=y
3508 +CONFIG_SND_MIXER_OSS=m
3509 +CONFIG_SND_PCM_OSS=m
3510 +CONFIG_SND_PCM_OSS_PLUGINS=y
3511 +# CONFIG_SND_DYNAMIC_MINORS is not set
3512 +CONFIG_SND_SUPPORT_OLD_API=y
3513 +CONFIG_SND_VERBOSE_PROCFS=y
3514 +# CONFIG_SND_VERBOSE_PRINTK is not set
3515 +CONFIG_SND_DEBUG=y
3516 +# CONFIG_SND_DEBUG_VERBOSE is not set
3517 +CONFIG_SND_PCM_XRUN_DEBUG=y
3518 +CONFIG_SND_DRIVERS=y
3519 +# CONFIG_SND_DUMMY is not set
3520 +# CONFIG_SND_MTPAV is not set
3521 +# CONFIG_SND_SERIAL_U16550 is not set
3522 +# CONFIG_SND_MPU401 is not set
3523 +CONFIG_SND_ARM=y
3524 +# CONFIG_SND_SPI is not set
3525 +CONFIG_SND_USB=y
3526 +CONFIG_SND_USB_AUDIO=m
3527 +# CONFIG_SND_USB_CAIAQ is not set
3528 +CONFIG_SND_SOC=m
3529 +CONFIG_SND_S3C24XX_SOC=m
3530 +CONFIG_SND_S3C24XX_SOC_I2S=m
3531 +CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753=m
3532 +# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set
3533 +# CONFIG_SND_SOC_ALL_CODECS is not set
3534 +CONFIG_SND_SOC_WM8753=m
3535 +# CONFIG_SOUND_PRIME is not set
3536 +CONFIG_HID_SUPPORT=y
3537 +CONFIG_HID=y
3538 +# CONFIG_HID_DEBUG is not set
3539 +# CONFIG_HIDRAW is not set
3540 +
3541 +#
3542 +# USB Input Devices
3543 +#
3544 +CONFIG_USB_HID=y
3545 +CONFIG_HID_PID=y
3546 +# CONFIG_USB_HIDDEV is not set
3547 +
3548 +#
3549 +# Special HID drivers
3550 +#
3551 +CONFIG_HID_COMPAT=y
3552 +CONFIG_HID_A4TECH=y
3553 +CONFIG_HID_APPLE=y
3554 +CONFIG_HID_BELKIN=y
3555 +CONFIG_HID_BRIGHT=y
3556 +CONFIG_HID_CHERRY=y
3557 +CONFIG_HID_CHICONY=y
3558 +CONFIG_HID_CYPRESS=y
3559 +CONFIG_HID_DELL=y
3560 +CONFIG_HID_EZKEY=y
3561 +CONFIG_HID_GYRATION=y
3562 +CONFIG_HID_LOGITECH=y
3563 +# CONFIG_LOGITECH_FF is not set
3564 +# CONFIG_LOGIRUMBLEPAD2_FF is not set
3565 +CONFIG_HID_MICROSOFT=y
3566 +CONFIG_HID_MONTEREY=y
3567 +CONFIG_HID_PANTHERLORD=y
3568 +# CONFIG_PANTHERLORD_FF is not set
3569 +CONFIG_HID_PETALYNX=y
3570 +CONFIG_HID_SAMSUNG=y
3571 +CONFIG_HID_SONY=y
3572 +CONFIG_HID_SUNPLUS=y
3573 +# CONFIG_THRUSTMASTER_FF is not set
3574 +# CONFIG_ZEROPLUS_FF is not set
3575 +CONFIG_USB_SUPPORT=y
3576 +CONFIG_USB_ARCH_HAS_HCD=y
3577 +CONFIG_USB_ARCH_HAS_OHCI=y
3578 +# CONFIG_USB_ARCH_HAS_EHCI is not set
3579 +CONFIG_USB=y
3580 +# CONFIG_USB_DEBUG is not set
3581 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
3582 +
3583 +#
3584 +# Miscellaneous USB options
3585 +#
3586 +CONFIG_USB_DEVICEFS=y
3587 +CONFIG_USB_DEVICE_CLASS=y
3588 +# CONFIG_USB_DYNAMIC_MINORS is not set
3589 +CONFIG_USB_SUSPEND=y
3590 +# CONFIG_USB_OTG is not set
3591 +CONFIG_USB_MON=y
3592 +# CONFIG_USB_WUSB is not set
3593 +# CONFIG_USB_WUSB_CBAF is not set
3594 +
3595 +#
3596 +# USB Host Controller Drivers
3597 +#
3598 +# CONFIG_USB_C67X00_HCD is not set
3599 +# CONFIG_USB_ISP116X_HCD is not set
3600 +# CONFIG_USB_ISP1760_HCD is not set
3601 +CONFIG_USB_OHCI_HCD=m
3602 +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
3603 +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
3604 +CONFIG_USB_OHCI_LITTLE_ENDIAN=y
3605 +# CONFIG_USB_SL811_HCD is not set
3606 +# CONFIG_USB_R8A66597_HCD is not set
3607 +# CONFIG_USB_HWA_HCD is not set
3608 +# CONFIG_USB_MUSB_HDRC is not set
3609 +# CONFIG_USB_GADGET_MUSB_HDRC is not set
3610 +
3611 +#
3612 +# USB Device Class drivers
3613 +#
3614 +CONFIG_USB_ACM=m
3615 +CONFIG_USB_PRINTER=m
3616 +# CONFIG_USB_WDM is not set
3617 +CONFIG_USB_TMC=m
3618 +
3619 +#
3620 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
3621 +#
3622 +
3623 +#
3624 +# may also be needed; see USB_STORAGE Help for more information
3625 +#
3626 +CONFIG_USB_STORAGE=m
3627 +# CONFIG_USB_STORAGE_DEBUG is not set
3628 +CONFIG_USB_STORAGE_DATAFAB=y
3629 +CONFIG_USB_STORAGE_FREECOM=y
3630 +# CONFIG_USB_STORAGE_ISD200 is not set
3631 +CONFIG_USB_STORAGE_DPCM=y
3632 +CONFIG_USB_STORAGE_USBAT=y
3633 +CONFIG_USB_STORAGE_SDDR09=y
3634 +CONFIG_USB_STORAGE_SDDR55=y
3635 +CONFIG_USB_STORAGE_JUMPSHOT=y
3636 +CONFIG_USB_STORAGE_ALAUDA=y
3637 +# CONFIG_USB_STORAGE_ONETOUCH is not set
3638 +CONFIG_USB_STORAGE_KARMA=y
3639 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
3640 +CONFIG_USB_LIBUSUAL=y
3641 +
3642 +#
3643 +# USB Imaging devices
3644 +#
3645 +# CONFIG_USB_MDC800 is not set
3646 +# CONFIG_USB_MICROTEK is not set
3647 +
3648 +#
3649 +# USB port drivers
3650 +#
3651 +CONFIG_USB_SERIAL=m
3652 +CONFIG_USB_EZUSB=y
3653 +CONFIG_USB_SERIAL_GENERIC=y
3654 +CONFIG_USB_SERIAL_AIRCABLE=m
3655 +CONFIG_USB_SERIAL_ARK3116=m
3656 +CONFIG_USB_SERIAL_BELKIN=m
3657 +# CONFIG_USB_SERIAL_CH341 is not set
3658 +CONFIG_USB_SERIAL_WHITEHEAT=m
3659 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
3660 +CONFIG_USB_SERIAL_CP2101=m
3661 +CONFIG_USB_SERIAL_CYPRESS_M8=m
3662 +CONFIG_USB_SERIAL_EMPEG=m
3663 +CONFIG_USB_SERIAL_FTDI_SIO=m
3664 +CONFIG_USB_SERIAL_FUNSOFT=m
3665 +CONFIG_USB_SERIAL_VISOR=m
3666 +CONFIG_USB_SERIAL_IPAQ=m
3667 +CONFIG_USB_SERIAL_IR=m
3668 +CONFIG_USB_SERIAL_EDGEPORT=m
3669 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
3670 +CONFIG_USB_SERIAL_GARMIN=m
3671 +CONFIG_USB_SERIAL_IPW=m
3672 +# CONFIG_USB_SERIAL_IUU is not set
3673 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
3674 +CONFIG_USB_SERIAL_KEYSPAN=m
3675 +CONFIG_USB_SERIAL_KLSI=m
3676 +CONFIG_USB_SERIAL_KOBIL_SCT=m
3677 +CONFIG_USB_SERIAL_MCT_U232=m
3678 +CONFIG_USB_SERIAL_MOS7720=m
3679 +CONFIG_USB_SERIAL_MOS7840=m
3680 +# CONFIG_USB_SERIAL_MOTOROLA is not set
3681 +CONFIG_USB_SERIAL_NAVMAN=m
3682 +CONFIG_USB_SERIAL_PL2303=m
3683 +# CONFIG_USB_SERIAL_OTI6858 is not set
3684 +# CONFIG_USB_SERIAL_SPCP8X5 is not set
3685 +CONFIG_USB_SERIAL_HP4X=m
3686 +CONFIG_USB_SERIAL_SAFE=m
3687 +CONFIG_USB_SERIAL_SAFE_PADDED=y
3688 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
3689 +CONFIG_USB_SERIAL_TI=m
3690 +CONFIG_USB_SERIAL_CYBERJACK=m
3691 +CONFIG_USB_SERIAL_XIRCOM=m
3692 +CONFIG_USB_SERIAL_OPTION=m
3693 +CONFIG_USB_SERIAL_OMNINET=m
3694 +# CONFIG_USB_SERIAL_DEBUG is not set
3695 +
3696 +#
3697 +# USB Miscellaneous drivers
3698 +#
3699 +# CONFIG_USB_EMI62 is not set
3700 +# CONFIG_USB_EMI26 is not set
3701 +# CONFIG_USB_ADUTUX is not set
3702 +# CONFIG_USB_SEVSEG is not set
3703 +# CONFIG_USB_RIO500 is not set
3704 +# CONFIG_USB_LEGOTOWER is not set
3705 +# CONFIG_USB_LCD is not set
3706 +CONFIG_USB_BERRY_CHARGE=m
3707 +# CONFIG_USB_LED is not set
3708 +# CONFIG_USB_CYPRESS_CY7C63 is not set
3709 +# CONFIG_USB_CYTHERM is not set
3710 +# CONFIG_USB_PHIDGET is not set
3711 +# CONFIG_USB_IDMOUSE is not set
3712 +# CONFIG_USB_FTDI_ELAN is not set
3713 +# CONFIG_USB_APPLEDISPLAY is not set
3714 +# CONFIG_USB_LD is not set
3715 +CONFIG_USB_TRANCEVIBRATOR=m
3716 +CONFIG_USB_IOWARRIOR=m
3717 +# CONFIG_USB_TEST is not set
3718 +# CONFIG_USB_ISIGHTFW is not set
3719 +# CONFIG_USB_VST is not set
3720 +CONFIG_USB_GADGET=y
3721 +# CONFIG_USB_GADGET_DEBUG is not set
3722 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
3723 +# CONFIG_USB_GADGET_DEBUG_FS is not set
3724 +CONFIG_USB_GADGET_VBUS_DRAW=500
3725 +CONFIG_USB_GADGET_SELECTED=y
3726 +# CONFIG_USB_GADGET_AT91 is not set
3727 +# CONFIG_USB_GADGET_ATMEL_USBA is not set
3728 +# CONFIG_USB_GADGET_FSL_USB2 is not set
3729 +# CONFIG_USB_GADGET_LH7A40X is not set
3730 +# CONFIG_USB_GADGET_OMAP is not set
3731 +# CONFIG_USB_GADGET_PXA25X is not set
3732 +# CONFIG_USB_GADGET_PXA27X is not set
3733 +CONFIG_USB_GADGET_S3C2410=y
3734 +CONFIG_USB_S3C2410=y
3735 +CONFIG_USB_S3C2410_DEBUG=y
3736 +# CONFIG_USB_GADGET_M66592 is not set
3737 +# CONFIG_USB_GADGET_AMD5536UDC is not set
3738 +# CONFIG_USB_GADGET_FSL_QE is not set
3739 +# CONFIG_USB_GADGET_NET2280 is not set
3740 +# CONFIG_USB_GADGET_GOKU is not set
3741 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
3742 +# CONFIG_USB_GADGET_DUALSPEED is not set
3743 +# CONFIG_USB_ZERO is not set
3744 +CONFIG_USB_ETH=m
3745 +CONFIG_USB_ETH_RNDIS=y
3746 +CONFIG_USB_GADGETFS=m
3747 +CONFIG_USB_FILE_STORAGE=m
3748 +# CONFIG_USB_FILE_STORAGE_TEST is not set
3749 +CONFIG_USB_G_SERIAL=m
3750 +CONFIG_USB_MIDI_GADGET=m
3751 +# CONFIG_USB_G_PRINTER is not set
3752 +# CONFIG_USB_CDC_COMPOSITE is not set
3753 +CONFIG_AR6000_WLAN=y
3754 +CONFIG_MMC=y
3755 +# CONFIG_MMC_DEBUG is not set
3756 +CONFIG_MMC_UNSAFE_RESUME=y
3757 +
3758 +#
3759 +# MMC/SD/SDIO Card Drivers
3760 +#
3761 +CONFIG_MMC_BLOCK=y
3762 +CONFIG_MMC_BLOCK_BOUNCE=y
3763 +# CONFIG_SDIO_UART is not set
3764 +# CONFIG_MMC_TEST is not set
3765 +
3766 +#
3767 +# MMC/SD/SDIO Host Controller Drivers
3768 +#
3769 +CONFIG_MMC_SDHCI=y
3770 +CONFIG_MMC_SDHCI_S3C=y
3771 +# CONFIG_MMC_SPI is not set
3772 +CONFIG_MMC_S3C=y
3773 +# CONFIG_MEMSTICK is not set
3774 +# CONFIG_ACCESSIBILITY is not set
3775 +CONFIG_NEW_LEDS=y
3776 +CONFIG_LEDS_CLASS=y
3777 +
3778 +#
3779 +# LED drivers
3780 +#
3781 +CONFIG_LEDS_S3C24XX=m
3782 +# CONFIG_LEDS_PCA9532 is not set
3783 +CONFIG_LEDS_GPIO=y
3784 +# CONFIG_LEDS_PCA955X is not set
3785 +CONFIG_LEDS_NEO1973_VIBRATOR=y
3786 +CONFIG_LEDS_NEO1973_GTA02=y
3787 +
3788 +#
3789 +# LED Triggers
3790 +#
3791 +CONFIG_LEDS_TRIGGERS=y
3792 +CONFIG_LEDS_TRIGGER_TIMER=y
3793 +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
3794 +CONFIG_LEDS_TRIGGER_BACKLIGHT=y
3795 +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
3796 +CONFIG_RTC_LIB=y
3797 +CONFIG_RTC_CLASS=y
3798 +CONFIG_RTC_HCTOSYS=y
3799 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
3800 +CONFIG_RTC_DEBUG=y
3801 +
3802 +#
3803 +# RTC interfaces
3804 +#
3805 +CONFIG_RTC_INTF_SYSFS=y
3806 +CONFIG_RTC_INTF_PROC=y
3807 +CONFIG_RTC_INTF_DEV=y
3808 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
3809 +# CONFIG_RTC_DRV_TEST is not set
3810 +
3811 +#
3812 +# I2C RTC drivers
3813 +#
3814 +# CONFIG_RTC_DRV_DS1307 is not set
3815 +# CONFIG_RTC_DRV_DS1374 is not set
3816 +# CONFIG_RTC_DRV_DS1672 is not set
3817 +# CONFIG_RTC_DRV_MAX6900 is not set
3818 +# CONFIG_RTC_DRV_RS5C372 is not set
3819 +# CONFIG_RTC_DRV_ISL1208 is not set
3820 +# CONFIG_RTC_DRV_X1205 is not set
3821 +# CONFIG_RTC_DRV_PCF8563 is not set
3822 +# CONFIG_RTC_DRV_PCF8583 is not set
3823 +CONFIG_RTC_DRV_PCF50633=y
3824 +# CONFIG_RTC_DRV_PCF50606 is not set
3825 +# CONFIG_RTC_DRV_M41T80 is not set
3826 +# CONFIG_RTC_DRV_S35390A is not set
3827 +# CONFIG_RTC_DRV_FM3130 is not set
3828 +
3829 +#
3830 +# SPI RTC drivers
3831 +#
3832 +# CONFIG_RTC_DRV_M41T94 is not set
3833 +# CONFIG_RTC_DRV_DS1305 is not set
3834 +# CONFIG_RTC_DRV_MAX6902 is not set
3835 +# CONFIG_RTC_DRV_R9701 is not set
3836 +# CONFIG_RTC_DRV_RS5C348 is not set
3837 +# CONFIG_RTC_DRV_DS3234 is not set
3838 +
3839 +#
3840 +# Platform RTC drivers
3841 +#
3842 +# CONFIG_RTC_DRV_CMOS is not set
3843 +# CONFIG_RTC_DRV_DS1286 is not set
3844 +# CONFIG_RTC_DRV_DS1511 is not set
3845 +# CONFIG_RTC_DRV_DS1553 is not set
3846 +# CONFIG_RTC_DRV_DS1742 is not set
3847 +# CONFIG_RTC_DRV_STK17TA8 is not set
3848 +# CONFIG_RTC_DRV_M48T86 is not set
3849 +# CONFIG_RTC_DRV_M48T35 is not set
3850 +# CONFIG_RTC_DRV_M48T59 is not set
3851 +# CONFIG_RTC_DRV_BQ4802 is not set
3852 +# CONFIG_RTC_DRV_V3020 is not set
3853 +
3854 +#
3855 +# on-CPU RTC drivers
3856 +#
3857 +CONFIG_RTC_DRV_S3C=m
3858 +CONFIG_DMADEVICES=y
3859 +
3860 +#
3861 +# DMA Devices
3862 +#
3863 +
3864 +#
3865 +# Android
3866 +#
3867 +CONFIG_ANDROID_BINDER_IPC=y
3868 +CONFIG_ANDROID_POWER=y
3869 +CONFIG_ANDROID_POWER_STAT=y
3870 +CONFIG_ANDROID_POWER_ALARM=y
3871 +CONFIG_ANDROID_LOGGER=y
3872 +# CONFIG_ANDROID_RAM_CONSOLE is not set
3873 +# CONFIG_ANDROID_TIMED_GPIO is not set
3874 +# CONFIG_ANDROID_PARANOID_NETWORK is not set
3875 +CONFIG_REGULATOR=y
3876 +CONFIG_REGULATOR_DEBUG=y
3877 +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
3878 +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
3879 +# CONFIG_REGULATOR_BQ24022 is not set
3880 +CONFIG_REGULATOR_PCF50633=y
3881 +CONFIG_UIO=y
3882 +CONFIG_UIO_PDRV=y
3883 +# CONFIG_UIO_PDRV_GENIRQ is not set
3884 +# CONFIG_UIO_SMX is not set
3885 +# CONFIG_UIO_SERCOS3 is not set
3886 +
3887 +#
3888 +# File systems
3889 +#
3890 +CONFIG_EXT2_FS=y
3891 +# CONFIG_EXT2_FS_XATTR is not set
3892 +# CONFIG_EXT2_FS_XIP is not set
3893 +CONFIG_EXT3_FS=y
3894 +# CONFIG_EXT3_FS_XATTR is not set
3895 +CONFIG_EXT4_FS=y
3896 +CONFIG_EXT4DEV_COMPAT=y
3897 +CONFIG_EXT4_FS_XATTR=y
3898 +# CONFIG_EXT4_FS_POSIX_ACL is not set
3899 +CONFIG_EXT4_FS_SECURITY=y
3900 +CONFIG_JBD=y
3901 +# CONFIG_JBD_DEBUG is not set
3902 +CONFIG_JBD2=y
3903 +# CONFIG_JBD2_DEBUG is not set
3904 +CONFIG_FS_MBCACHE=y
3905 +# CONFIG_REISERFS_FS is not set
3906 +# CONFIG_JFS_FS is not set
3907 +CONFIG_FS_POSIX_ACL=y
3908 +CONFIG_FILE_LOCKING=y
3909 +# CONFIG_XFS_FS is not set
3910 +# CONFIG_OCFS2_FS is not set
3911 +CONFIG_DNOTIFY=y
3912 +CONFIG_INOTIFY=y
3913 +CONFIG_INOTIFY_USER=y
3914 +# CONFIG_QUOTA is not set
3915 +# CONFIG_AUTOFS_FS is not set
3916 +CONFIG_AUTOFS4_FS=m
3917 +CONFIG_FUSE_FS=m
3918 +
3919 +#
3920 +# CD-ROM/DVD Filesystems
3921 +#
3922 +CONFIG_ISO9660_FS=m
3923 +CONFIG_JOLIET=y
3924 +# CONFIG_ZISOFS is not set
3925 +CONFIG_UDF_FS=m
3926 +CONFIG_UDF_NLS=y
3927 +
3928 +#
3929 +# DOS/FAT/NT Filesystems
3930 +#
3931 +CONFIG_FAT_FS=y
3932 +CONFIG_MSDOS_FS=y
3933 +CONFIG_VFAT_FS=y
3934 +CONFIG_FAT_DEFAULT_CODEPAGE=437
3935 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
3936 +# CONFIG_NTFS_FS is not set
3937 +
3938 +#
3939 +# Pseudo filesystems
3940 +#
3941 +CONFIG_PROC_FS=y
3942 +CONFIG_PROC_SYSCTL=y
3943 +CONFIG_PROC_PAGE_MONITOR=y
3944 +CONFIG_SYSFS=y
3945 +CONFIG_TMPFS=y
3946 +# CONFIG_TMPFS_POSIX_ACL is not set
3947 +# CONFIG_HUGETLB_PAGE is not set
3948 +CONFIG_CONFIGFS_FS=m
3949 +
3950 +#
3951 +# Miscellaneous filesystems
3952 +#
3953 +# CONFIG_ADFS_FS is not set
3954 +# CONFIG_AFFS_FS is not set
3955 +# CONFIG_HFS_FS is not set
3956 +# CONFIG_HFSPLUS_FS is not set
3957 +# CONFIG_BEFS_FS is not set
3958 +# CONFIG_BFS_FS is not set
3959 +# CONFIG_EFS_FS is not set
3960 +CONFIG_JFFS2_FS=y
3961 +CONFIG_JFFS2_FS_DEBUG=0
3962 +CONFIG_JFFS2_FS_WRITEBUFFER=y
3963 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
3964 +CONFIG_JFFS2_SUMMARY=y
3965 +# CONFIG_JFFS2_FS_XATTR is not set
3966 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
3967 +CONFIG_JFFS2_ZLIB=y
3968 +# CONFIG_JFFS2_LZO is not set
3969 +CONFIG_JFFS2_RTIME=y
3970 +# CONFIG_JFFS2_RUBIN is not set
3971 +CONFIG_CRAMFS=y
3972 +# CONFIG_VXFS_FS is not set
3973 +# CONFIG_MINIX_FS is not set
3974 +# CONFIG_OMFS_FS is not set
3975 +# CONFIG_HPFS_FS is not set
3976 +# CONFIG_QNX4FS_FS is not set
3977 +CONFIG_ROMFS_FS=y
3978 +# CONFIG_SYSV_FS is not set
3979 +# CONFIG_UFS_FS is not set
3980 +CONFIG_NETWORK_FILESYSTEMS=y
3981 +# CONFIG_NFS_FS is not set
3982 +CONFIG_NFSD=m
3983 +CONFIG_NFSD_V2_ACL=y
3984 +CONFIG_NFSD_V3=y
3985 +CONFIG_NFSD_V3_ACL=y
3986 +# CONFIG_NFSD_V4 is not set
3987 +CONFIG_LOCKD=m
3988 +CONFIG_LOCKD_V4=y
3989 +CONFIG_EXPORTFS=m
3990 +CONFIG_NFS_ACL_SUPPORT=m
3991 +CONFIG_NFS_COMMON=y
3992 +CONFIG_SUNRPC=m
3993 +# CONFIG_SUNRPC_REGISTER_V4 is not set
3994 +# CONFIG_RPCSEC_GSS_KRB5 is not set
3995 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
3996 +# CONFIG_SMB_FS is not set
3997 +CONFIG_CIFS=m
3998 +# CONFIG_CIFS_STATS is not set
3999 +# CONFIG_CIFS_WEAK_PW_HASH is not set
4000 +# CONFIG_CIFS_XATTR is not set
4001 +# CONFIG_CIFS_DEBUG2 is not set
4002 +# CONFIG_CIFS_EXPERIMENTAL is not set
4003 +# CONFIG_NCP_FS is not set
4004 +# CONFIG_CODA_FS is not set
4005 +# CONFIG_AFS_FS is not set
4006 +
4007 +#
4008 +# Partition Types
4009 +#
4010 +CONFIG_PARTITION_ADVANCED=y
4011 +# CONFIG_ACORN_PARTITION is not set
4012 +# CONFIG_OSF_PARTITION is not set
4013 +# CONFIG_AMIGA_PARTITION is not set
4014 +# CONFIG_ATARI_PARTITION is not set
4015 +# CONFIG_MAC_PARTITION is not set
4016 +CONFIG_MSDOS_PARTITION=y
4017 +# CONFIG_BSD_DISKLABEL is not set
4018 +# CONFIG_MINIX_SUBPARTITION is not set
4019 +# CONFIG_SOLARIS_X86_PARTITION is not set
4020 +# CONFIG_UNIXWARE_DISKLABEL is not set
4021 +# CONFIG_LDM_PARTITION is not set
4022 +# CONFIG_SGI_PARTITION is not set
4023 +# CONFIG_ULTRIX_PARTITION is not set
4024 +# CONFIG_SUN_PARTITION is not set
4025 +# CONFIG_KARMA_PARTITION is not set
4026 +# CONFIG_EFI_PARTITION is not set
4027 +# CONFIG_SYSV68_PARTITION is not set
4028 +CONFIG_NLS=y
4029 +CONFIG_NLS_DEFAULT="iso8859-1"
4030 +CONFIG_NLS_CODEPAGE_437=y
4031 +# CONFIG_NLS_CODEPAGE_737 is not set
4032 +# CONFIG_NLS_CODEPAGE_775 is not set
4033 +CONFIG_NLS_CODEPAGE_850=m
4034 +# CONFIG_NLS_CODEPAGE_852 is not set
4035 +# CONFIG_NLS_CODEPAGE_855 is not set
4036 +# CONFIG_NLS_CODEPAGE_857 is not set
4037 +# CONFIG_NLS_CODEPAGE_860 is not set
4038 +# CONFIG_NLS_CODEPAGE_861 is not set
4039 +# CONFIG_NLS_CODEPAGE_862 is not set
4040 +# CONFIG_NLS_CODEPAGE_863 is not set
4041 +# CONFIG_NLS_CODEPAGE_864 is not set
4042 +# CONFIG_NLS_CODEPAGE_865 is not set
4043 +# CONFIG_NLS_CODEPAGE_866 is not set
4044 +# CONFIG_NLS_CODEPAGE_869 is not set
4045 +CONFIG_NLS_CODEPAGE_936=m
4046 +CONFIG_NLS_CODEPAGE_950=m
4047 +# CONFIG_NLS_CODEPAGE_932 is not set
4048 +# CONFIG_NLS_CODEPAGE_949 is not set
4049 +# CONFIG_NLS_CODEPAGE_874 is not set
4050 +# CONFIG_NLS_ISO8859_8 is not set
4051 +# CONFIG_NLS_CODEPAGE_1250 is not set
4052 +# CONFIG_NLS_CODEPAGE_1251 is not set
4053 +# CONFIG_NLS_ASCII is not set
4054 +CONFIG_NLS_ISO8859_1=y
4055 +# CONFIG_NLS_ISO8859_2 is not set
4056 +# CONFIG_NLS_ISO8859_3 is not set
4057 +# CONFIG_NLS_ISO8859_4 is not set
4058 +# CONFIG_NLS_ISO8859_5 is not set
4059 +# CONFIG_NLS_ISO8859_6 is not set
4060 +# CONFIG_NLS_ISO8859_7 is not set
4061 +# CONFIG_NLS_ISO8859_9 is not set
4062 +# CONFIG_NLS_ISO8859_13 is not set
4063 +# CONFIG_NLS_ISO8859_14 is not set
4064 +# CONFIG_NLS_ISO8859_15 is not set
4065 +# CONFIG_NLS_KOI8_R is not set
4066 +# CONFIG_NLS_KOI8_U is not set
4067 +CONFIG_NLS_UTF8=m
4068 +# CONFIG_DLM is not set
4069 +
4070 +#
4071 +# Kernel hacking
4072 +#
4073 +CONFIG_PRINTK_TIME=y
4074 +CONFIG_ENABLE_WARN_DEPRECATED=y
4075 +CONFIG_ENABLE_MUST_CHECK=y
4076 +CONFIG_FRAME_WARN=1024
4077 +CONFIG_MAGIC_SYSRQ=y
4078 +# CONFIG_UNUSED_SYMBOLS is not set
4079 +CONFIG_DEBUG_FS=y
4080 +# CONFIG_HEADERS_CHECK is not set
4081 +CONFIG_DEBUG_KERNEL=y
4082 +CONFIG_DEBUG_SHIRQ=y
4083 +CONFIG_DETECT_SOFTLOCKUP=y
4084 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
4085 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
4086 +CONFIG_SCHED_DEBUG=y
4087 +CONFIG_SCHEDSTATS=y
4088 +CONFIG_TIMER_STATS=y
4089 +# CONFIG_DEBUG_OBJECTS is not set
4090 +# CONFIG_DEBUG_SLAB is not set
4091 +CONFIG_DEBUG_PREEMPT=y
4092 +# CONFIG_DEBUG_RT_MUTEXES is not set
4093 +# CONFIG_RT_MUTEX_TESTER is not set
4094 +CONFIG_DEBUG_SPINLOCK=y
4095 +CONFIG_DEBUG_MUTEXES=y
4096 +CONFIG_DEBUG_LOCK_ALLOC=y
4097 +# CONFIG_PROVE_LOCKING is not set
4098 +CONFIG_LOCKDEP=y
4099 +CONFIG_LOCK_STAT=y
4100 +CONFIG_DEBUG_LOCKDEP=y
4101 +CONFIG_DEBUG_SPINLOCK_SLEEP=y
4102 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
4103 +CONFIG_STACKTRACE=y
4104 +# CONFIG_DEBUG_KOBJECT is not set
4105 +CONFIG_DEBUG_BUGVERBOSE=y
4106 +CONFIG_DEBUG_INFO=y
4107 +# CONFIG_DEBUG_VM is not set
4108 +# CONFIG_DEBUG_WRITECOUNT is not set
4109 +CONFIG_DEBUG_MEMORY_INIT=y
4110 +# CONFIG_DEBUG_LIST is not set
4111 +CONFIG_DEBUG_SG=y
4112 +CONFIG_FRAME_POINTER=y
4113 +# CONFIG_BOOT_PRINTK_DELAY is not set
4114 +# CONFIG_RCU_TORTURE_TEST is not set
4115 +CONFIG_RCU_CPU_STALL_DETECTOR=y
4116 +# CONFIG_BACKTRACE_SELF_TEST is not set
4117 +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
4118 +# CONFIG_FAULT_INJECTION is not set
4119 +CONFIG_LATENCYTOP=y
4120 +CONFIG_SYSCTL_SYSCALL_CHECK=y
4121 +CONFIG_HAVE_FUNCTION_TRACER=y
4122 +
4123 +#
4124 +# Tracers
4125 +#
4126 +# CONFIG_FUNCTION_TRACER is not set
4127 +# CONFIG_SCHED_TRACER is not set
4128 +# CONFIG_CONTEXT_SWITCH_TRACER is not set
4129 +# CONFIG_BOOT_TRACER is not set
4130 +# CONFIG_STACK_TRACER is not set
4131 +CONFIG_DYNAMIC_PRINTK_DEBUG=y
4132 +# CONFIG_SAMPLES is not set
4133 +CONFIG_HAVE_ARCH_KGDB=y
4134 +# CONFIG_KGDB is not set
4135 +# CONFIG_DEBUG_USER is not set
4136 +CONFIG_DEBUG_ERRORS=y
4137 +# CONFIG_DEBUG_STACK_USAGE is not set
4138 +# CONFIG_DEBUG_LL is not set
4139 +CONFIG_DEBUG_S3C_UART=2
4140 +
4141 +#
4142 +# Security options
4143 +#
4144 +# CONFIG_KEYS is not set
4145 +# CONFIG_SECURITY is not set
4146 +CONFIG_SECURITYFS=y
4147 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
4148 +CONFIG_CRYPTO=y
4149 +
4150 +#
4151 +# Crypto core or helper
4152 +#
4153 +CONFIG_CRYPTO_FIPS=y
4154 +CONFIG_CRYPTO_ALGAPI=y
4155 +CONFIG_CRYPTO_AEAD=y
4156 +CONFIG_CRYPTO_BLKCIPHER=y
4157 +CONFIG_CRYPTO_HASH=y
4158 +CONFIG_CRYPTO_RNG=y
4159 +CONFIG_CRYPTO_MANAGER=y
4160 +CONFIG_CRYPTO_GF128MUL=m
4161 +CONFIG_CRYPTO_NULL=m
4162 +# CONFIG_CRYPTO_CRYPTD is not set
4163 +CONFIG_CRYPTO_AUTHENC=m
4164 +CONFIG_CRYPTO_TEST=m
4165 +
4166 +#
4167 +# Authenticated Encryption with Associated Data
4168 +#
4169 +# CONFIG_CRYPTO_CCM is not set
4170 +# CONFIG_CRYPTO_GCM is not set
4171 +# CONFIG_CRYPTO_SEQIV is not set
4172 +
4173 +#
4174 +# Block modes
4175 +#
4176 +CONFIG_CRYPTO_CBC=y
4177 +# CONFIG_CRYPTO_CTR is not set
4178 +# CONFIG_CRYPTO_CTS is not set
4179 +CONFIG_CRYPTO_ECB=m
4180 +CONFIG_CRYPTO_LRW=m
4181 +CONFIG_CRYPTO_PCBC=m
4182 +# CONFIG_CRYPTO_XTS is not set
4183 +
4184 +#
4185 +# Hash modes
4186 +#
4187 +CONFIG_CRYPTO_HMAC=y
4188 +CONFIG_CRYPTO_XCBC=m
4189 +
4190 +#
4191 +# Digest
4192 +#
4193 +CONFIG_CRYPTO_CRC32C=m
4194 +CONFIG_CRYPTO_MD4=m
4195 +CONFIG_CRYPTO_MD5=y
4196 +CONFIG_CRYPTO_MICHAEL_MIC=m
4197 +# CONFIG_CRYPTO_RMD128 is not set
4198 +# CONFIG_CRYPTO_RMD160 is not set
4199 +# CONFIG_CRYPTO_RMD256 is not set
4200 +# CONFIG_CRYPTO_RMD320 is not set
4201 +CONFIG_CRYPTO_SHA1=m
4202 +CONFIG_CRYPTO_SHA256=m
4203 +CONFIG_CRYPTO_SHA512=m
4204 +CONFIG_CRYPTO_TGR192=m
4205 +CONFIG_CRYPTO_WP512=m
4206 +
4207 +#
4208 +# Ciphers
4209 +#
4210 +CONFIG_CRYPTO_AES=y
4211 +CONFIG_CRYPTO_ANUBIS=m
4212 +CONFIG_CRYPTO_ARC4=m
4213 +CONFIG_CRYPTO_BLOWFISH=m
4214 +CONFIG_CRYPTO_CAMELLIA=m
4215 +CONFIG_CRYPTO_CAST5=m
4216 +CONFIG_CRYPTO_CAST6=m
4217 +CONFIG_CRYPTO_DES=y
4218 +CONFIG_CRYPTO_FCRYPT=m
4219 +CONFIG_CRYPTO_KHAZAD=m
4220 +# CONFIG_CRYPTO_SALSA20 is not set
4221 +# CONFIG_CRYPTO_SEED is not set
4222 +CONFIG_CRYPTO_SERPENT=m
4223 +CONFIG_CRYPTO_TEA=m
4224 +CONFIG_CRYPTO_TWOFISH=m
4225 +CONFIG_CRYPTO_TWOFISH_COMMON=m
4226 +
4227 +#
4228 +# Compression
4229 +#
4230 +CONFIG_CRYPTO_DEFLATE=m
4231 +# CONFIG_CRYPTO_LZO is not set
4232 +
4233 +#
4234 +# Random Number Generation
4235 +#
4236 +CONFIG_CRYPTO_ANSI_CPRNG=y
4237 +CONFIG_CRYPTO_HW=y
4238 +
4239 +#
4240 +# Library routines
4241 +#
4242 +CONFIG_BITREVERSE=y
4243 +CONFIG_CRC_CCITT=m
4244 +CONFIG_CRC16=y
4245 +CONFIG_CRC_T10DIF=y
4246 +CONFIG_CRC_ITU_T=m
4247 +CONFIG_CRC32=y
4248 +# CONFIG_CRC7 is not set
4249 +CONFIG_LIBCRC32C=m
4250 +CONFIG_ZLIB_INFLATE=y
4251 +CONFIG_ZLIB_DEFLATE=y
4252 +CONFIG_TEXTSEARCH=y
4253 +CONFIG_TEXTSEARCH_KMP=m
4254 +CONFIG_TEXTSEARCH_BM=m
4255 +CONFIG_TEXTSEARCH_FSM=m
4256 +CONFIG_PLIST=y
4257 +CONFIG_HAS_IOMEM=y
4258 +CONFIG_HAS_DMA=y
4259 --- /dev/null
4260 +++ b/arch/arm/configs/gta03_defconfig
4261 @@ -0,0 +1,1548 @@
4262 +#
4263 +# Automatically generated make config: don't edit
4264 +# Linux kernel version: 2.6.28-rc4
4265 +# Fri Dec 12 12:07:49 2008
4266 +#
4267 +CONFIG_ARM=y
4268 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
4269 +CONFIG_GENERIC_GPIO=y
4270 +# CONFIG_GENERIC_TIME is not set
4271 +# CONFIG_GENERIC_CLOCKEVENTS is not set
4272 +CONFIG_MMU=y
4273 +CONFIG_NO_IOPORT=y
4274 +CONFIG_GENERIC_HARDIRQS=y
4275 +CONFIG_STACKTRACE_SUPPORT=y
4276 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
4277 +CONFIG_LOCKDEP_SUPPORT=y
4278 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
4279 +CONFIG_HARDIRQS_SW_RESEND=y
4280 +CONFIG_GENERIC_IRQ_PROBE=y
4281 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
4282 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
4283 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
4284 +CONFIG_GENERIC_HWEIGHT=y
4285 +CONFIG_GENERIC_CALIBRATE_DELAY=y
4286 +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
4287 +CONFIG_VECTORS_BASE=0xffff0000
4288 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
4289 +
4290 +#
4291 +# General setup
4292 +#
4293 +CONFIG_EXPERIMENTAL=y
4294 +CONFIG_BROKEN_ON_SMP=y
4295 +CONFIG_INIT_ENV_ARG_LIMIT=32
4296 +CONFIG_LOCALVERSION=""
4297 +CONFIG_LOCALVERSION_AUTO=y
4298 +CONFIG_SWAP=y
4299 +# CONFIG_SYSVIPC is not set
4300 +# CONFIG_POSIX_MQUEUE is not set
4301 +# CONFIG_BSD_PROCESS_ACCT is not set
4302 +# CONFIG_TASKSTATS is not set
4303 +# CONFIG_AUDIT is not set
4304 +CONFIG_IKCONFIG=y
4305 +CONFIG_IKCONFIG_PROC=y
4306 +CONFIG_LOG_BUF_SHIFT=18
4307 +# CONFIG_CGROUPS is not set
4308 +# CONFIG_GROUP_SCHED is not set
4309 +CONFIG_SYSFS_DEPRECATED=y
4310 +CONFIG_SYSFS_DEPRECATED_V2=y
4311 +# CONFIG_RELAY is not set
4312 +CONFIG_NAMESPACES=y
4313 +# CONFIG_UTS_NS is not set
4314 +# CONFIG_USER_NS is not set
4315 +# CONFIG_PID_NS is not set
4316 +CONFIG_BLK_DEV_INITRD=y
4317 +CONFIG_INITRAMFS_SOURCE=""
4318 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
4319 +CONFIG_SYSCTL=y
4320 +# CONFIG_EMBEDDED is not set
4321 +CONFIG_UID16=y
4322 +CONFIG_SYSCTL_SYSCALL=y
4323 +CONFIG_KALLSYMS=y
4324 +CONFIG_KALLSYMS_ALL=y
4325 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
4326 +CONFIG_HOTPLUG=y
4327 +CONFIG_PRINTK=y
4328 +CONFIG_BUG=y
4329 +CONFIG_ELF_CORE=y
4330 +CONFIG_COMPAT_BRK=y
4331 +CONFIG_BASE_FULL=y
4332 +CONFIG_FUTEX=y
4333 +CONFIG_ANON_INODES=y
4334 +CONFIG_EPOLL=y
4335 +CONFIG_SIGNALFD=y
4336 +CONFIG_TIMERFD=y
4337 +CONFIG_EVENTFD=y
4338 +CONFIG_SHMEM=y
4339 +CONFIG_AIO=y
4340 +CONFIG_ASHMEM=y
4341 +CONFIG_VM_EVENT_COUNTERS=y
4342 +CONFIG_SLUB_DEBUG=y
4343 +# CONFIG_SLAB is not set
4344 +CONFIG_SLUB=y
4345 +# CONFIG_SLOB is not set
4346 +# CONFIG_PROFILING is not set
4347 +# CONFIG_MARKERS is not set
4348 +CONFIG_HAVE_OPROFILE=y
4349 +# CONFIG_KPROBES is not set
4350 +CONFIG_HAVE_KPROBES=y
4351 +CONFIG_HAVE_KRETPROBES=y
4352 +CONFIG_HAVE_CLK=y
4353 +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
4354 +CONFIG_SLABINFO=y
4355 +CONFIG_RT_MUTEXES=y
4356 +# CONFIG_TINY_SHMEM is not set
4357 +CONFIG_BASE_SMALL=0
4358 +CONFIG_MODULES=y
4359 +# CONFIG_MODULE_FORCE_LOAD is not set
4360 +CONFIG_MODULE_UNLOAD=y
4361 +# CONFIG_MODULE_FORCE_UNLOAD is not set
4362 +# CONFIG_MODVERSIONS is not set
4363 +# CONFIG_MODULE_SRCVERSION_ALL is not set
4364 +CONFIG_KMOD=y
4365 +CONFIG_BLOCK=y
4366 +CONFIG_LBD=y
4367 +# CONFIG_BLK_DEV_IO_TRACE is not set
4368 +CONFIG_LSF=y
4369 +# CONFIG_BLK_DEV_BSG is not set
4370 +# CONFIG_BLK_DEV_INTEGRITY is not set
4371 +
4372 +#
4373 +# IO Schedulers
4374 +#
4375 +CONFIG_IOSCHED_NOOP=y
4376 +CONFIG_IOSCHED_AS=y
4377 +CONFIG_IOSCHED_DEADLINE=y
4378 +CONFIG_IOSCHED_CFQ=y
4379 +# CONFIG_DEFAULT_AS is not set
4380 +# CONFIG_DEFAULT_DEADLINE is not set
4381 +CONFIG_DEFAULT_CFQ=y
4382 +# CONFIG_DEFAULT_NOOP is not set
4383 +CONFIG_DEFAULT_IOSCHED="cfq"
4384 +CONFIG_CLASSIC_RCU=y
4385 +CONFIG_FREEZER=y
4386 +
4387 +#
4388 +# System Type
4389 +#
4390 +# CONFIG_ARCH_AAEC2000 is not set
4391 +# CONFIG_ARCH_INTEGRATOR is not set
4392 +# CONFIG_ARCH_REALVIEW is not set
4393 +# CONFIG_ARCH_VERSATILE is not set
4394 +# CONFIG_ARCH_AT91 is not set
4395 +# CONFIG_ARCH_CLPS7500 is not set
4396 +# CONFIG_ARCH_CLPS711X is not set
4397 +# CONFIG_ARCH_EBSA110 is not set
4398 +# CONFIG_ARCH_EP93XX is not set
4399 +# CONFIG_ARCH_FOOTBRIDGE is not set
4400 +# CONFIG_ARCH_NETX is not set
4401 +# CONFIG_ARCH_H720X is not set
4402 +# CONFIG_ARCH_IMX is not set
4403 +# CONFIG_ARCH_IOP13XX is not set
4404 +# CONFIG_ARCH_IOP32X is not set
4405 +# CONFIG_ARCH_IOP33X is not set
4406 +# CONFIG_ARCH_IXP23XX is not set
4407 +# CONFIG_ARCH_IXP2000 is not set
4408 +# CONFIG_ARCH_IXP4XX is not set
4409 +# CONFIG_ARCH_L7200 is not set
4410 +# CONFIG_ARCH_KIRKWOOD is not set
4411 +# CONFIG_ARCH_KS8695 is not set
4412 +# CONFIG_ARCH_NS9XXX is not set
4413 +# CONFIG_ARCH_LOKI is not set
4414 +# CONFIG_ARCH_MV78XX0 is not set
4415 +# CONFIG_ARCH_MXC is not set
4416 +# CONFIG_ARCH_ORION5X is not set
4417 +# CONFIG_ARCH_PNX4008 is not set
4418 +# CONFIG_ARCH_PXA is not set
4419 +# CONFIG_ARCH_RPC is not set
4420 +# CONFIG_ARCH_SA1100 is not set
4421 +# CONFIG_ARCH_S3C2410 is not set
4422 +CONFIG_ARCH_S3C64XX=y
4423 +# CONFIG_ARCH_SHARK is not set
4424 +# CONFIG_ARCH_LH7A40X is not set
4425 +# CONFIG_ARCH_DAVINCI is not set
4426 +# CONFIG_ARCH_OMAP is not set
4427 +# CONFIG_ARCH_MSM is not set
4428 +CONFIG_MACH_NEO1973=y
4429 +CONFIG_PLAT_S3C64XX=y
4430 +CONFIG_CPU_S3C6400_INIT=y
4431 +CONFIG_CPU_S3C6400_CLOCK=y
4432 +CONFIG_S3C64XX_SETUP_I2C0=y
4433 +CONFIG_S3C64XX_SETUP_I2C1=y
4434 +CONFIG_S3C64XX_SETUP_FB_24BPP=y
4435 +CONFIG_PLAT_S3C=y
4436 +
4437 +#
4438 +# Boot options
4439 +#
4440 +CONFIG_S3C_BOOT_ERROR_RESET=y
4441 +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
4442 +
4443 +#
4444 +# Power management
4445 +#
4446 +# CONFIG_S3C2410_PM_DEBUG is not set
4447 +# CONFIG_S3C2410_PM_CHECK is not set
4448 +CONFIG_S3C_LOWLEVEL_UART_PORT=3
4449 +CONFIG_S3C_GPIO_SPACE=0
4450 +CONFIG_S3C_GPIO_TRACK=y
4451 +CONFIG_S3C_GPIO_PULL_UPDOWN=y
4452 +CONFIG_S3C_GPIO_CFG_S3C24XX=y
4453 +CONFIG_S3C_GPIO_CFG_S3C64XX=y
4454 +CONFIG_S3C_DEV_HSMMC=y
4455 +CONFIG_S3C_DEV_HSMMC1=y
4456 +CONFIG_S3C_DEV_I2C1=y
4457 +CONFIG_S3C_DEV_FB=y
4458 +CONFIG_CPU_S3C6410=y
4459 +CONFIG_S3C6410_SETUP_SDHCI=y
4460 +# CONFIG_MACH_SMDK6410 is not set
4461 +CONFIG_MACH_OPENMOKO_GTA03=y
4462 +
4463 +#
4464 +# Processor Type
4465 +#
4466 +CONFIG_CPU_32=y
4467 +CONFIG_CPU_V6=y
4468 +CONFIG_CPU_32v6K=y
4469 +CONFIG_CPU_32v6=y
4470 +CONFIG_CPU_ABRT_EV6=y
4471 +CONFIG_CPU_PABRT_NOIFAR=y
4472 +CONFIG_CPU_CACHE_V6=y
4473 +CONFIG_CPU_CACHE_VIPT=y
4474 +CONFIG_CPU_COPY_V6=y
4475 +CONFIG_CPU_TLB_V6=y
4476 +CONFIG_CPU_HAS_ASID=y
4477 +CONFIG_CPU_CP15=y
4478 +CONFIG_CPU_CP15_MMU=y
4479 +
4480 +#
4481 +# Processor Features
4482 +#
4483 +CONFIG_ARM_THUMB=y
4484 +# CONFIG_CPU_ICACHE_DISABLE is not set
4485 +# CONFIG_CPU_DCACHE_DISABLE is not set
4486 +# CONFIG_CPU_BPREDICT_DISABLE is not set
4487 +# CONFIG_OUTER_CACHE is not set
4488 +CONFIG_ARM_VIC=y
4489 +
4490 +#
4491 +# Bus support
4492 +#
4493 +# CONFIG_PCI_SYSCALL is not set
4494 +# CONFIG_ARCH_SUPPORTS_MSI is not set
4495 +# CONFIG_PCCARD is not set
4496 +
4497 +#
4498 +# Kernel Features
4499 +#
4500 +CONFIG_VMSPLIT_3G=y
4501 +# CONFIG_VMSPLIT_2G is not set
4502 +# CONFIG_VMSPLIT_1G is not set
4503 +CONFIG_PAGE_OFFSET=0xC0000000
4504 +# CONFIG_PREEMPT is not set
4505 +CONFIG_HZ=100
4506 +CONFIG_AEABI=y
4507 +CONFIG_OABI_COMPAT=y
4508 +CONFIG_ARCH_FLATMEM_HAS_HOLES=y
4509 +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
4510 +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
4511 +CONFIG_SELECT_MEMORY_MODEL=y
4512 +CONFIG_FLATMEM_MANUAL=y
4513 +# CONFIG_DISCONTIGMEM_MANUAL is not set
4514 +# CONFIG_SPARSEMEM_MANUAL is not set
4515 +CONFIG_FLATMEM=y
4516 +CONFIG_FLAT_NODE_MEM_MAP=y
4517 +CONFIG_PAGEFLAGS_EXTENDED=y
4518 +CONFIG_SPLIT_PTLOCK_CPUS=4
4519 +# CONFIG_RESOURCES_64BIT is not set
4520 +# CONFIG_PHYS_ADDR_T_64BIT is not set
4521 +CONFIG_ZONE_DMA_FLAG=0
4522 +CONFIG_VIRT_TO_BUS=y
4523 +CONFIG_UNEVICTABLE_LRU=y
4524 +CONFIG_ALIGNMENT_TRAP=y
4525 +
4526 +#
4527 +# Boot options
4528 +#
4529 +CONFIG_ZBOOT_ROM_TEXT=0
4530 +CONFIG_ZBOOT_ROM_BSS=0
4531 +CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M"
4532 +# CONFIG_XIP_KERNEL is not set
4533 +# CONFIG_KEXEC is not set
4534 +
4535 +#
4536 +# CPU Power Management
4537 +#
4538 +CONFIG_CPU_IDLE=y
4539 +CONFIG_CPU_IDLE_GOV_LADDER=y
4540 +
4541 +#
4542 +# Floating point emulation
4543 +#
4544 +
4545 +#
4546 +# At least one emulation must be selected
4547 +#
4548 +# CONFIG_FPE_NWFPE is not set
4549 +# CONFIG_FPE_FASTFPE is not set
4550 +CONFIG_VFP=y
4551 +
4552 +#
4553 +# Userspace binary formats
4554 +#
4555 +CONFIG_BINFMT_ELF=y
4556 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
4557 +CONFIG_HAVE_AOUT=y
4558 +# CONFIG_BINFMT_AOUT is not set
4559 +# CONFIG_BINFMT_MISC is not set
4560 +
4561 +#
4562 +# Power management options
4563 +#
4564 +CONFIG_PM=y
4565 +# CONFIG_PM_DEBUG is not set
4566 +CONFIG_PM_SLEEP=y
4567 +CONFIG_SUSPEND=y
4568 +CONFIG_SUSPEND_FREEZER=y
4569 +CONFIG_APM_EMULATION=y
4570 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
4571 +CONFIG_NET=y
4572 +
4573 +#
4574 +# Networking options
4575 +#
4576 +CONFIG_PACKET=y
4577 +CONFIG_PACKET_MMAP=y
4578 +CONFIG_UNIX=y
4579 +CONFIG_XFRM=y
4580 +# CONFIG_XFRM_USER is not set
4581 +# CONFIG_XFRM_SUB_POLICY is not set
4582 +CONFIG_XFRM_MIGRATE=y
4583 +# CONFIG_XFRM_STATISTICS is not set
4584 +# CONFIG_NET_KEY is not set
4585 +CONFIG_INET=y
4586 +CONFIG_IP_MULTICAST=y
4587 +CONFIG_IP_ADVANCED_ROUTER=y
4588 +CONFIG_ASK_IP_FIB_HASH=y
4589 +# CONFIG_IP_FIB_TRIE is not set
4590 +CONFIG_IP_FIB_HASH=y
4591 +CONFIG_IP_MULTIPLE_TABLES=y
4592 +# CONFIG_IP_ROUTE_MULTIPATH is not set
4593 +# CONFIG_IP_ROUTE_VERBOSE is not set
4594 +CONFIG_IP_PNP=y
4595 +# CONFIG_IP_PNP_DHCP is not set
4596 +# CONFIG_IP_PNP_BOOTP is not set
4597 +# CONFIG_IP_PNP_RARP is not set
4598 +# CONFIG_NET_IPIP is not set
4599 +# CONFIG_NET_IPGRE is not set
4600 +# CONFIG_IP_MROUTE is not set
4601 +# CONFIG_ARPD is not set
4602 +CONFIG_SYN_COOKIES=y
4603 +# CONFIG_INET_AH is not set
4604 +# CONFIG_INET_ESP is not set
4605 +# CONFIG_INET_IPCOMP is not set
4606 +# CONFIG_INET_XFRM_TUNNEL is not set
4607 +CONFIG_INET_TUNNEL=m
4608 +CONFIG_INET_XFRM_MODE_TRANSPORT=y
4609 +CONFIG_INET_XFRM_MODE_TUNNEL=y
4610 +CONFIG_INET_XFRM_MODE_BEET=y
4611 +# CONFIG_INET_LRO is not set
4612 +CONFIG_INET_DIAG=y
4613 +CONFIG_INET_TCP_DIAG=y
4614 +# CONFIG_TCP_CONG_ADVANCED is not set
4615 +CONFIG_TCP_CONG_CUBIC=y
4616 +CONFIG_DEFAULT_TCP_CONG="cubic"
4617 +CONFIG_TCP_MD5SIG=y
4618 +CONFIG_IPV6=m
4619 +# CONFIG_IPV6_PRIVACY is not set
4620 +# CONFIG_IPV6_ROUTER_PREF is not set
4621 +# CONFIG_IPV6_OPTIMISTIC_DAD is not set
4622 +# CONFIG_INET6_AH is not set
4623 +# CONFIG_INET6_ESP is not set
4624 +# CONFIG_INET6_IPCOMP is not set
4625 +# CONFIG_IPV6_MIP6 is not set
4626 +# CONFIG_INET6_XFRM_TUNNEL is not set
4627 +# CONFIG_INET6_TUNNEL is not set
4628 +CONFIG_INET6_XFRM_MODE_TRANSPORT=m
4629 +CONFIG_INET6_XFRM_MODE_TUNNEL=m
4630 +CONFIG_INET6_XFRM_MODE_BEET=m
4631 +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
4632 +CONFIG_IPV6_SIT=m
4633 +CONFIG_IPV6_NDISC_NODETYPE=y
4634 +# CONFIG_IPV6_TUNNEL is not set
4635 +# CONFIG_IPV6_MULTIPLE_TABLES is not set
4636 +# CONFIG_IPV6_MROUTE is not set
4637 +# CONFIG_NETWORK_SECMARK is not set
4638 +CONFIG_NETFILTER=y
4639 +# CONFIG_NETFILTER_DEBUG is not set
4640 +CONFIG_NETFILTER_ADVANCED=y
4641 +
4642 +#
4643 +# Core Netfilter Configuration
4644 +#
4645 +# CONFIG_NETFILTER_NETLINK_QUEUE is not set
4646 +# CONFIG_NETFILTER_NETLINK_LOG is not set
4647 +# CONFIG_NF_CONNTRACK is not set
4648 +CONFIG_NETFILTER_XTABLES=m
4649 +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
4650 +# CONFIG_NETFILTER_XT_TARGET_MARK is not set
4651 +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
4652 +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
4653 +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
4654 +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
4655 +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
4656 +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
4657 +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
4658 +# CONFIG_NETFILTER_XT_MATCH_ESP is not set
4659 +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
4660 +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
4661 +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
4662 +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
4663 +# CONFIG_NETFILTER_XT_MATCH_MAC is not set
4664 +# CONFIG_NETFILTER_XT_MATCH_MARK is not set
4665 +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
4666 +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
4667 +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
4668 +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
4669 +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
4670 +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
4671 +# CONFIG_NETFILTER_XT_MATCH_REALM is not set
4672 +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
4673 +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
4674 +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
4675 +# CONFIG_NETFILTER_XT_MATCH_STRING is not set
4676 +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
4677 +# CONFIG_NETFILTER_XT_MATCH_TIME is not set
4678 +# CONFIG_NETFILTER_XT_MATCH_U32 is not set
4679 +# CONFIG_IP_VS is not set
4680 +
4681 +#
4682 +# IP: Netfilter Configuration
4683 +#
4684 +# CONFIG_NF_DEFRAG_IPV4 is not set
4685 +# CONFIG_IP_NF_QUEUE is not set
4686 +# CONFIG_IP_NF_IPTABLES is not set
4687 +# CONFIG_IP_NF_ARPTABLES is not set
4688 +
4689 +#
4690 +# IPv6: Netfilter Configuration
4691 +#
4692 +# CONFIG_IP6_NF_QUEUE is not set
4693 +CONFIG_IP6_NF_IPTABLES=m
4694 +# CONFIG_IP6_NF_MATCH_AH is not set
4695 +# CONFIG_IP6_NF_MATCH_EUI64 is not set
4696 +# CONFIG_IP6_NF_MATCH_FRAG is not set
4697 +# CONFIG_IP6_NF_MATCH_OPTS is not set
4698 +# CONFIG_IP6_NF_MATCH_HL is not set
4699 +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
4700 +# CONFIG_IP6_NF_MATCH_MH is not set
4701 +# CONFIG_IP6_NF_MATCH_RT is not set
4702 +# CONFIG_IP6_NF_TARGET_LOG is not set
4703 +# CONFIG_IP6_NF_FILTER is not set
4704 +# CONFIG_IP6_NF_MANGLE is not set
4705 +# CONFIG_IP6_NF_RAW is not set
4706 +# CONFIG_IP_DCCP is not set
4707 +# CONFIG_IP_SCTP is not set
4708 +# CONFIG_TIPC is not set
4709 +# CONFIG_ATM is not set
4710 +# CONFIG_BRIDGE is not set
4711 +# CONFIG_NET_DSA is not set
4712 +# CONFIG_VLAN_8021Q is not set
4713 +# CONFIG_DECNET is not set
4714 +# CONFIG_LLC2 is not set
4715 +# CONFIG_IPX is not set
4716 +# CONFIG_ATALK is not set
4717 +# CONFIG_X25 is not set
4718 +# CONFIG_LAPB is not set
4719 +# CONFIG_ECONET is not set
4720 +# CONFIG_WAN_ROUTER is not set
4721 +# CONFIG_NET_SCHED is not set
4722 +
4723 +#
4724 +# Network testing
4725 +#
4726 +# CONFIG_NET_PKTGEN is not set
4727 +# CONFIG_HAMRADIO is not set
4728 +# CONFIG_CAN is not set
4729 +# CONFIG_IRDA is not set
4730 +# CONFIG_BT is not set
4731 +# CONFIG_AF_RXRPC is not set
4732 +# CONFIG_PHONET is not set
4733 +CONFIG_FIB_RULES=y
4734 +CONFIG_WIRELESS=y
4735 +CONFIG_CFG80211=y
4736 +CONFIG_NL80211=y
4737 +CONFIG_WIRELESS_OLD_REGULATORY=y
4738 +CONFIG_WIRELESS_EXT=y
4739 +CONFIG_WIRELESS_EXT_SYSFS=y
4740 +CONFIG_MAC80211=y
4741 +
4742 +#
4743 +# Rate control algorithm selection
4744 +#
4745 +CONFIG_MAC80211_RC_PID=y
4746 +# CONFIG_MAC80211_RC_MINSTREL is not set
4747 +CONFIG_MAC80211_RC_DEFAULT_PID=y
4748 +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
4749 +CONFIG_MAC80211_RC_DEFAULT="pid"
4750 +# CONFIG_MAC80211_MESH is not set
4751 +CONFIG_MAC80211_LEDS=y
4752 +# CONFIG_MAC80211_DEBUG_MENU is not set
4753 +# CONFIG_IEEE80211 is not set
4754 +# CONFIG_RFKILL is not set
4755 +# CONFIG_NET_9P is not set
4756 +
4757 +#
4758 +# Device Drivers
4759 +#
4760 +
4761 +#
4762 +# Generic Driver Options
4763 +#
4764 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
4765 +CONFIG_STANDALONE=y
4766 +CONFIG_PREVENT_FIRMWARE_BUILD=y
4767 +CONFIG_FW_LOADER=y
4768 +CONFIG_FIRMWARE_IN_KERNEL=y
4769 +CONFIG_EXTRA_FIRMWARE=""
4770 +# CONFIG_DEBUG_DRIVER is not set
4771 +# CONFIG_DEBUG_DEVRES is not set
4772 +# CONFIG_SYS_HYPERVISOR is not set
4773 +# CONFIG_CONNECTOR is not set
4774 +CONFIG_MTD=y
4775 +# CONFIG_MTD_DEBUG is not set
4776 +# CONFIG_MTD_CONCAT is not set
4777 +CONFIG_MTD_PARTITIONS=y
4778 +# CONFIG_MTD_REDBOOT_PARTS is not set
4779 +CONFIG_MTD_CMDLINE_PARTS=y
4780 +# CONFIG_MTD_AFS_PARTS is not set
4781 +# CONFIG_MTD_AR7_PARTS is not set
4782 +
4783 +#
4784 +# User Modules And Translation Layers
4785 +#
4786 +CONFIG_MTD_CHAR=y
4787 +CONFIG_MTD_BLKDEVS=y
4788 +CONFIG_MTD_BLOCK=y
4789 +# CONFIG_FTL is not set
4790 +# CONFIG_NFTL is not set
4791 +# CONFIG_INFTL is not set
4792 +# CONFIG_RFD_FTL is not set
4793 +# CONFIG_SSFDC is not set
4794 +# CONFIG_MTD_OOPS is not set
4795 +
4796 +#
4797 +# RAM/ROM/Flash chip drivers
4798 +#
4799 +# CONFIG_MTD_CFI is not set
4800 +# CONFIG_MTD_JEDECPROBE is not set
4801 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
4802 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
4803 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
4804 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
4805 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
4806 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
4807 +CONFIG_MTD_CFI_I1=y
4808 +CONFIG_MTD_CFI_I2=y
4809 +# CONFIG_MTD_CFI_I4 is not set
4810 +# CONFIG_MTD_CFI_I8 is not set
4811 +# CONFIG_MTD_RAM is not set
4812 +# CONFIG_MTD_ROM is not set
4813 +# CONFIG_MTD_ABSENT is not set
4814 +
4815 +#
4816 +# Mapping drivers for chip access
4817 +#
4818 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
4819 +# CONFIG_MTD_PLATRAM is not set
4820 +
4821 +#
4822 +# Self-contained MTD device drivers
4823 +#
4824 +# CONFIG_MTD_DATAFLASH is not set
4825 +# CONFIG_MTD_M25P80 is not set
4826 +# CONFIG_MTD_SLRAM is not set
4827 +# CONFIG_MTD_PHRAM is not set
4828 +# CONFIG_MTD_MTDRAM is not set
4829 +# CONFIG_MTD_BLOCK2MTD is not set
4830 +
4831 +#
4832 +# Disk-On-Chip Device Drivers
4833 +#
4834 +# CONFIG_MTD_DOC2000 is not set
4835 +# CONFIG_MTD_DOC2001 is not set
4836 +# CONFIG_MTD_DOC2001PLUS is not set
4837 +# CONFIG_MTD_NAND is not set
4838 +CONFIG_MTD_ONENAND=y
4839 +# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
4840 +CONFIG_MTD_ONENAND_GENERIC=y
4841 +# CONFIG_MTD_ONENAND_OTP is not set
4842 +# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
4843 +# CONFIG_MTD_ONENAND_SIM is not set
4844 +
4845 +#
4846 +# UBI - Unsorted block images
4847 +#
4848 +# CONFIG_MTD_UBI is not set
4849 +# CONFIG_PARPORT is not set
4850 +CONFIG_BLK_DEV=y
4851 +# CONFIG_BLK_DEV_COW_COMMON is not set
4852 +CONFIG_BLK_DEV_LOOP=y
4853 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
4854 +# CONFIG_BLK_DEV_NBD is not set
4855 +CONFIG_BLK_DEV_RAM=y
4856 +CONFIG_BLK_DEV_RAM_COUNT=16
4857 +CONFIG_BLK_DEV_RAM_SIZE=8192
4858 +# CONFIG_BLK_DEV_XIP is not set
4859 +# CONFIG_CDROM_PKTCDVD is not set
4860 +# CONFIG_ATA_OVER_ETH is not set
4861 +CONFIG_MISC_DEVICES=y
4862 +# CONFIG_EEPROM_93CX6 is not set
4863 +CONFIG_LOW_MEMORY_KILLER=y
4864 +# CONFIG_ENCLOSURE_SERVICES is not set
4865 +CONFIG_HAVE_IDE=y
4866 +# CONFIG_IDE is not set
4867 +
4868 +#
4869 +# SCSI device support
4870 +#
4871 +# CONFIG_RAID_ATTRS is not set
4872 +# CONFIG_SCSI is not set
4873 +# CONFIG_SCSI_DMA is not set
4874 +# CONFIG_SCSI_NETLINK is not set
4875 +# CONFIG_ATA is not set
4876 +# CONFIG_MD is not set
4877 +CONFIG_NETDEVICES=y
4878 +# CONFIG_DUMMY is not set
4879 +# CONFIG_BONDING is not set
4880 +# CONFIG_MACVLAN is not set
4881 +# CONFIG_EQUALIZER is not set
4882 +CONFIG_TUN=y
4883 +# CONFIG_VETH is not set
4884 +# CONFIG_NET_ETHERNET is not set
4885 +# CONFIG_NETDEV_1000 is not set
4886 +# CONFIG_NETDEV_10000 is not set
4887 +
4888 +#
4889 +# Wireless LAN
4890 +#
4891 +# CONFIG_WLAN_PRE80211 is not set
4892 +# CONFIG_WLAN_80211 is not set
4893 +# CONFIG_IWLWIFI_LEDS is not set
4894 +# CONFIG_WAN is not set
4895 +CONFIG_PPP=y
4896 +# CONFIG_PPP_MULTILINK is not set
4897 +# CONFIG_PPP_FILTER is not set
4898 +CONFIG_PPP_ASYNC=y
4899 +CONFIG_PPP_SYNC_TTY=y
4900 +CONFIG_PPP_DEFLATE=y
4901 +CONFIG_PPP_BSDCOMP=y
4902 +CONFIG_PPP_MPPE=y
4903 +# CONFIG_PPPOE is not set
4904 +# CONFIG_PPPOL2TP is not set
4905 +# CONFIG_SLIP is not set
4906 +CONFIG_SLHC=y
4907 +# CONFIG_NETCONSOLE is not set
4908 +# CONFIG_NETPOLL is not set
4909 +# CONFIG_NET_POLL_CONTROLLER is not set
4910 +# CONFIG_ISDN is not set
4911 +
4912 +#
4913 +# Input device support
4914 +#
4915 +CONFIG_INPUT=y
4916 +# CONFIG_INPUT_FF_MEMLESS is not set
4917 +# CONFIG_INPUT_POLLDEV is not set
4918 +
4919 +#
4920 +# Userland interfaces
4921 +#
4922 +CONFIG_INPUT_MOUSEDEV=y
4923 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
4924 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
4925 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
4926 +# CONFIG_INPUT_JOYDEV is not set
4927 +CONFIG_INPUT_EVDEV=y
4928 +# CONFIG_INPUT_EVBUG is not set
4929 +
4930 +#
4931 +# Input Device Drivers
4932 +#
4933 +CONFIG_INPUT_KEYBOARD=y
4934 +CONFIG_KEYBOARD_ATKBD=y
4935 +# CONFIG_KEYBOARD_SUNKBD is not set
4936 +# CONFIG_KEYBOARD_LKKBD is not set
4937 +# CONFIG_KEYBOARD_XTKBD is not set
4938 +# CONFIG_KEYBOARD_NEWTON is not set
4939 +# CONFIG_KEYBOARD_STOWAWAY is not set
4940 +# CONFIG_KEYBOARD_GPIO is not set
4941 +CONFIG_KEYBOARD_NEO1973=y
4942 +CONFIG_INPUT_MOUSE=y
4943 +CONFIG_MOUSE_PS2=y
4944 +CONFIG_MOUSE_PS2_ALPS=y
4945 +CONFIG_MOUSE_PS2_LOGIPS2PP=y
4946 +CONFIG_MOUSE_PS2_SYNAPTICS=y
4947 +CONFIG_MOUSE_PS2_LIFEBOOK=y
4948 +CONFIG_MOUSE_PS2_TRACKPOINT=y
4949 +# CONFIG_MOUSE_PS2_ELANTECH is not set
4950 +# CONFIG_MOUSE_PS2_TOUCHKIT is not set
4951 +# CONFIG_MOUSE_SERIAL is not set
4952 +# CONFIG_MOUSE_APPLETOUCH is not set
4953 +# CONFIG_MOUSE_BCM5974 is not set
4954 +# CONFIG_MOUSE_VSXXXAA is not set
4955 +# CONFIG_MOUSE_GPIO is not set
4956 +# CONFIG_INPUT_JOYSTICK is not set
4957 +# CONFIG_INPUT_TABLET is not set
4958 +CONFIG_INPUT_TOUCHSCREEN=y
4959 +CONFIG_TOUCHSCREEN_FILTER=y
4960 +CONFIG_TOUCHSCREEN_FILTER_GROUP=y
4961 +CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y
4962 +CONFIG_TOUCHSCREEN_FILTER_MEAN=y
4963 +# CONFIG_TOUCHSCREEN_ADS7846 is not set
4964 +# CONFIG_TOUCHSCREEN_FUJITSU is not set
4965 +# CONFIG_TOUCHSCREEN_GUNZE is not set
4966 +# CONFIG_TOUCHSCREEN_ELO is not set
4967 +# CONFIG_TOUCHSCREEN_MTOUCH is not set
4968 +# CONFIG_TOUCHSCREEN_INEXIO is not set
4969 +# CONFIG_TOUCHSCREEN_MK712 is not set
4970 +# CONFIG_TOUCHSCREEN_PENMOUNT is not set
4971 +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
4972 +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
4973 +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
4974 +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
4975 +CONFIG_INPUT_MISC=y
4976 +CONFIG_TOUCHSCREEN_PCAP7200=y
4977 +# CONFIG_INPUT_ATI_REMOTE is not set
4978 +# CONFIG_INPUT_ATI_REMOTE2 is not set
4979 +# CONFIG_INPUT_KEYSPAN_REMOTE is not set
4980 +# CONFIG_INPUT_POWERMATE is not set
4981 +# CONFIG_INPUT_YEALINK is not set
4982 +# CONFIG_INPUT_CM109 is not set
4983 +# CONFIG_INPUT_UINPUT is not set
4984 +CONFIG_INPUT_LIS302DL=y
4985 +CONFIG_INPUT_PCF50633_PMU=y
4986 +
4987 +#
4988 +# Hardware I/O ports
4989 +#
4990 +CONFIG_SERIO=y
4991 +CONFIG_SERIO_SERPORT=y
4992 +CONFIG_SERIO_LIBPS2=y
4993 +# CONFIG_SERIO_RAW is not set
4994 +# CONFIG_GAMEPORT is not set
4995 +
4996 +#
4997 +# Character devices
4998 +#
4999 +CONFIG_VT=y
5000 +CONFIG_CONSOLE_TRANSLATIONS=y
5001 +CONFIG_VT_CONSOLE=y
5002 +CONFIG_NR_TTY_DEVICES=6
5003 +CONFIG_HW_CONSOLE=y
5004 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
5005 +CONFIG_DEVKMEM=y
5006 +# CONFIG_SERIAL_NONSTANDARD is not set
5007 +
5008 +#
5009 +# Serial drivers
5010 +#
5011 +CONFIG_SERIAL_8250=y
5012 +# CONFIG_SERIAL_8250_CONSOLE is not set
5013 +CONFIG_SERIAL_8250_NR_UARTS=4
5014 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4
5015 +# CONFIG_SERIAL_8250_EXTENDED is not set
5016 +
5017 +#
5018 +# Non-8250 serial port support
5019 +#
5020 +CONFIG_SERIAL_SAMSUNG=y
5021 +CONFIG_SERIAL_SAMSUNG_UARTS=4
5022 +# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
5023 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y
5024 +CONFIG_SERIAL_S3C6400=y
5025 +CONFIG_SERIAL_CORE=y
5026 +CONFIG_SERIAL_CORE_CONSOLE=y
5027 +CONFIG_UNIX98_PTYS=y
5028 +CONFIG_LEGACY_PTYS=y
5029 +CONFIG_LEGACY_PTY_COUNT=256
5030 +# CONFIG_IPMI_HANDLER is not set
5031 +CONFIG_HW_RANDOM=y
5032 +# CONFIG_NVRAM is not set
5033 +# CONFIG_R3964 is not set
5034 +# CONFIG_RAW_DRIVER is not set
5035 +# CONFIG_TCG_TPM is not set
5036 +CONFIG_I2C=y
5037 +CONFIG_I2C_BOARDINFO=y
5038 +CONFIG_I2C_CHARDEV=y
5039 +CONFIG_I2C_HELPER_AUTO=y
5040 +
5041 +#
5042 +# I2C Hardware Bus support
5043 +#
5044 +
5045 +#
5046 +# I2C system bus drivers (mostly embedded / system-on-chip)
5047 +#
5048 +# CONFIG_I2C_GPIO is not set
5049 +# CONFIG_I2C_OCORES is not set
5050 +CONFIG_I2C_S3C2410=y
5051 +# CONFIG_I2C_SIMTEC is not set
5052 +
5053 +#
5054 +# External I2C/SMBus adapter drivers
5055 +#
5056 +# CONFIG_I2C_PARPORT_LIGHT is not set
5057 +# CONFIG_I2C_TAOS_EVM is not set
5058 +
5059 +#
5060 +# Other I2C/SMBus bus drivers
5061 +#
5062 +# CONFIG_I2C_PCA_PLATFORM is not set
5063 +# CONFIG_I2C_STUB is not set
5064 +
5065 +#
5066 +# Miscellaneous I2C Chip support
5067 +#
5068 +# CONFIG_DS1682 is not set
5069 +# CONFIG_AT24 is not set
5070 +# CONFIG_SENSORS_EEPROM is not set
5071 +# CONFIG_SENSORS_PCF50606 is not set
5072 +# CONFIG_SENSORS_PCF50633 is not set
5073 +# CONFIG_SENSORS_PCF8574 is not set
5074 +# CONFIG_PCF8575 is not set
5075 +# CONFIG_SENSORS_PCA9539 is not set
5076 +# CONFIG_SENSORS_PCF8591 is not set
5077 +# CONFIG_TPS65010 is not set
5078 +# CONFIG_SENSORS_MAX6875 is not set
5079 +# CONFIG_SENSORS_TSL2550 is not set
5080 +# CONFIG_SENSORS_TSL256X is not set
5081 +CONFIG_PCA9632=y
5082 +# CONFIG_I2C_DEBUG_CORE is not set
5083 +# CONFIG_I2C_DEBUG_ALGO is not set
5084 +# CONFIG_I2C_DEBUG_BUS is not set
5085 +# CONFIG_I2C_DEBUG_CHIP is not set
5086 +CONFIG_SPI=y
5087 +# CONFIG_SPI_DEBUG is not set
5088 +CONFIG_SPI_MASTER=y
5089 +
5090 +#
5091 +# SPI Master Controller Drivers
5092 +#
5093 +CONFIG_SPI_BITBANG=y
5094 +
5095 +#
5096 +# SPI Protocol Masters
5097 +#
5098 +# CONFIG_SPI_AT25 is not set
5099 +# CONFIG_SPI_SPIDEV is not set
5100 +# CONFIG_SPI_TLE62X0 is not set
5101 +CONFIG_ARCH_REQUIRE_GPIOLIB=y
5102 +CONFIG_GPIOLIB=y
5103 +# CONFIG_DEBUG_GPIO is not set
5104 +CONFIG_GPIO_SYSFS=y
5105 +
5106 +#
5107 +# I2C GPIO expanders:
5108 +#
5109 +# CONFIG_GPIO_MAX732X is not set
5110 +# CONFIG_GPIO_PCA953X is not set
5111 +# CONFIG_GPIO_PCF857X is not set
5112 +
5113 +#
5114 +# PCI GPIO expanders:
5115 +#
5116 +
5117 +#
5118 +# SPI GPIO expanders:
5119 +#
5120 +# CONFIG_GPIO_MAX7301 is not set
5121 +# CONFIG_GPIO_MCP23S08 is not set
5122 +# CONFIG_W1 is not set
5123 +CONFIG_POWER_SUPPLY=y
5124 +# CONFIG_POWER_SUPPLY_DEBUG is not set
5125 +# CONFIG_PDA_POWER is not set
5126 +# CONFIG_APM_POWER is not set
5127 +# CONFIG_BATTERY_DS2760 is not set
5128 +# CONFIG_BATTERY_BQ27x00 is not set
5129 +# CONFIG_BATTERY_BQ27000_HDQ is not set
5130 +CONFIG_CHARGER_PCF50633=y
5131 +CONFIG_HWMON=y
5132 +# CONFIG_HWMON_VID is not set
5133 +# CONFIG_SENSORS_AD7414 is not set
5134 +# CONFIG_SENSORS_AD7418 is not set
5135 +# CONFIG_SENSORS_ADCXX is not set
5136 +# CONFIG_SENSORS_ADM1021 is not set
5137 +# CONFIG_SENSORS_ADM1025 is not set
5138 +# CONFIG_SENSORS_ADM1026 is not set
5139 +# CONFIG_SENSORS_ADM1029 is not set
5140 +# CONFIG_SENSORS_ADM1031 is not set
5141 +# CONFIG_SENSORS_ADM9240 is not set
5142 +# CONFIG_SENSORS_ADT7470 is not set
5143 +# CONFIG_SENSORS_ADT7473 is not set
5144 +# CONFIG_SENSORS_ATXP1 is not set
5145 +# CONFIG_SENSORS_DS1621 is not set
5146 +# CONFIG_SENSORS_F71805F is not set
5147 +# CONFIG_SENSORS_F71882FG is not set
5148 +# CONFIG_SENSORS_F75375S is not set
5149 +# CONFIG_SENSORS_GL518SM is not set
5150 +# CONFIG_SENSORS_GL520SM is not set
5151 +# CONFIG_SENSORS_IT87 is not set
5152 +# CONFIG_SENSORS_LM63 is not set
5153 +# CONFIG_SENSORS_LM70 is not set
5154 +# CONFIG_SENSORS_LM75 is not set
5155 +# CONFIG_SENSORS_LM77 is not set
5156 +# CONFIG_SENSORS_LM78 is not set
5157 +# CONFIG_SENSORS_LM80 is not set
5158 +# CONFIG_SENSORS_LM83 is not set
5159 +# CONFIG_SENSORS_LM85 is not set
5160 +# CONFIG_SENSORS_LM87 is not set
5161 +# CONFIG_SENSORS_LM90 is not set
5162 +# CONFIG_SENSORS_LM92 is not set
5163 +# CONFIG_SENSORS_LM93 is not set
5164 +# CONFIG_SENSORS_MAX1111 is not set
5165 +# CONFIG_SENSORS_MAX1619 is not set
5166 +# CONFIG_SENSORS_MAX6650 is not set
5167 +# CONFIG_SENSORS_PC87360 is not set
5168 +# CONFIG_SENSORS_PC87427 is not set
5169 +# CONFIG_SENSORS_DME1737 is not set
5170 +# CONFIG_SENSORS_SMSC47M1 is not set
5171 +# CONFIG_SENSORS_SMSC47M192 is not set
5172 +# CONFIG_SENSORS_SMSC47B397 is not set
5173 +# CONFIG_SENSORS_ADS7828 is not set
5174 +# CONFIG_SENSORS_THMC50 is not set
5175 +# CONFIG_SENSORS_VT1211 is not set
5176 +# CONFIG_SENSORS_W83781D is not set
5177 +# CONFIG_SENSORS_W83791D is not set
5178 +# CONFIG_SENSORS_W83792D is not set
5179 +# CONFIG_SENSORS_W83793 is not set
5180 +# CONFIG_SENSORS_W83L785TS is not set
5181 +# CONFIG_SENSORS_W83L786NG is not set
5182 +# CONFIG_SENSORS_W83627HF is not set
5183 +# CONFIG_SENSORS_W83627EHF is not set
5184 +# CONFIG_HWMON_DEBUG_CHIP is not set
5185 +# CONFIG_THERMAL is not set
5186 +# CONFIG_THERMAL_HWMON is not set
5187 +# CONFIG_WATCHDOG is not set
5188 +
5189 +#
5190 +# Sonics Silicon Backplane
5191 +#
5192 +CONFIG_SSB_POSSIBLE=y
5193 +# CONFIG_SSB is not set
5194 +
5195 +#
5196 +# Multifunction device drivers
5197 +#
5198 +# CONFIG_MFD_CORE is not set
5199 +# CONFIG_MFD_SM501 is not set
5200 +# CONFIG_MFD_ASIC3 is not set
5201 +# CONFIG_HTC_EGPIO is not set
5202 +# CONFIG_HTC_PASIC3 is not set
5203 +# CONFIG_MFD_TMIO is not set
5204 +# CONFIG_MFD_T7L66XB is not set
5205 +# CONFIG_MFD_TC6387XB is not set
5206 +# CONFIG_MFD_TC6393XB is not set
5207 +# CONFIG_PMIC_DA903X is not set
5208 +# CONFIG_MFD_WM8400 is not set
5209 +# CONFIG_MFD_WM8350_I2C is not set
5210 +CONFIG_MFD_PCF50633=y
5211 +CONFIG_PCF50633_ADC=y
5212 +CONFIG_PCF50633_GPIO=y
5213 +# CONFIG_MFD_PCF50606 is not set
5214 +# CONFIG_MFD_GLAMO is not set
5215 +
5216 +#
5217 +# Multimedia devices
5218 +#
5219 +
5220 +#
5221 +# Multimedia core support
5222 +#
5223 +# CONFIG_VIDEO_DEV is not set
5224 +# CONFIG_DVB_CORE is not set
5225 +# CONFIG_VIDEO_MEDIA is not set
5226 +
5227 +#
5228 +# Multimedia drivers
5229 +#
5230 +# CONFIG_DAB is not set
5231 +
5232 +#
5233 +# Graphics support
5234 +#
5235 +# CONFIG_VGASTATE is not set
5236 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
5237 +CONFIG_FB=y
5238 +# CONFIG_FIRMWARE_EDID is not set
5239 +# CONFIG_FB_DDC is not set
5240 +# CONFIG_FB_BOOT_VESA_SUPPORT is not set
5241 +CONFIG_FB_CFB_FILLRECT=y
5242 +CONFIG_FB_CFB_COPYAREA=y
5243 +CONFIG_FB_CFB_IMAGEBLIT=y
5244 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
5245 +# CONFIG_FB_SYS_FILLRECT is not set
5246 +# CONFIG_FB_SYS_COPYAREA is not set
5247 +# CONFIG_FB_SYS_IMAGEBLIT is not set
5248 +# CONFIG_FB_FOREIGN_ENDIAN is not set
5249 +# CONFIG_FB_SYS_FOPS is not set
5250 +# CONFIG_FB_SVGALIB is not set
5251 +# CONFIG_FB_MACMODES is not set
5252 +# CONFIG_FB_BACKLIGHT is not set
5253 +CONFIG_FB_MODE_HELPERS=y
5254 +CONFIG_FB_TILEBLITTING=y
5255 +
5256 +#
5257 +# Frame buffer hardware drivers
5258 +#
5259 +# CONFIG_FB_S1D13XXX is not set
5260 +CONFIG_FB_S3C=y
5261 +# CONFIG_FB_S3C_DEBUG_REGWRITE is not set
5262 +# CONFIG_FB_VIRTUAL is not set
5263 +# CONFIG_FB_METRONOME is not set
5264 +# CONFIG_FB_MB862XX is not set
5265 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
5266 +CONFIG_LCD_CLASS_DEVICE=y
5267 +# CONFIG_LCD_LTV350QV is not set
5268 +# CONFIG_LCD_ILI9320 is not set
5269 +# CONFIG_LCD_TDO24M is not set
5270 +# CONFIG_LCD_VGG2432A4 is not set
5271 +CONFIG_LCD_PLATFORM=y
5272 +CONFIG_BACKLIGHT_CLASS_DEVICE=y
5273 +CONFIG_BACKLIGHT_CORGI=y
5274 +
5275 +#
5276 +# Display device support
5277 +#
5278 +# CONFIG_DISPLAY_SUPPORT is not set
5279 +# CONFIG_DISPLAY_JBT6K74 is not set
5280 +
5281 +#
5282 +# Console display driver support
5283 +#
5284 +# CONFIG_VGA_CONSOLE is not set
5285 +CONFIG_DUMMY_CONSOLE=y
5286 +CONFIG_FRAMEBUFFER_CONSOLE=y
5287 +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
5288 +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
5289 +CONFIG_FONTS=y
5290 +CONFIG_FONT_8x8=y
5291 +CONFIG_FONT_8x16=y
5292 +# CONFIG_FONT_6x11 is not set
5293 +# CONFIG_FONT_7x14 is not set
5294 +# CONFIG_FONT_PEARL_8x8 is not set
5295 +# CONFIG_FONT_ACORN_8x8 is not set
5296 +# CONFIG_FONT_MINI_4x6 is not set
5297 +# CONFIG_FONT_SUN8x16 is not set
5298 +# CONFIG_FONT_SUN12x22 is not set
5299 +# CONFIG_FONT_10x18 is not set
5300 +CONFIG_LOGO=y
5301 +CONFIG_LOGO_LINUX_MONO=y
5302 +CONFIG_LOGO_LINUX_VGA16=y
5303 +# CONFIG_LOGO_LINUX_CLUT224 is not set
5304 +CONFIG_SOUND=y
5305 +# CONFIG_SOUND_OSS_CORE is not set
5306 +CONFIG_SND=y
5307 +CONFIG_SND_TIMER=y
5308 +CONFIG_SND_PCM=y
5309 +# CONFIG_SND_SEQUENCER is not set
5310 +# CONFIG_SND_MIXER_OSS is not set
5311 +# CONFIG_SND_PCM_OSS is not set
5312 +# CONFIG_SND_DYNAMIC_MINORS is not set
5313 +CONFIG_SND_SUPPORT_OLD_API=y
5314 +CONFIG_SND_VERBOSE_PROCFS=y
5315 +# CONFIG_SND_VERBOSE_PRINTK is not set
5316 +# CONFIG_SND_DEBUG is not set
5317 +CONFIG_SND_DRIVERS=y
5318 +# CONFIG_SND_DUMMY is not set
5319 +# CONFIG_SND_MTPAV is not set
5320 +# CONFIG_SND_SERIAL_U16550 is not set
5321 +# CONFIG_SND_MPU401 is not set
5322 +CONFIG_SND_ARM=y
5323 +CONFIG_SND_SPI=y
5324 +CONFIG_SND_SOC=y
5325 +# CONFIG_SND_SOC_ALL_CODECS is not set
5326 +# CONFIG_SOUND_PRIME is not set
5327 +CONFIG_HID_SUPPORT=y
5328 +CONFIG_HID=y
5329 +CONFIG_HID_DEBUG=y
5330 +# CONFIG_HIDRAW is not set
5331 +# CONFIG_HID_PID is not set
5332 +
5333 +#
5334 +# Special HID drivers
5335 +#
5336 +# CONFIG_HID_COMPAT is not set
5337 +CONFIG_USB_SUPPORT=y
5338 +CONFIG_USB_ARCH_HAS_HCD=y
5339 +# CONFIG_USB_ARCH_HAS_OHCI is not set
5340 +# CONFIG_USB_ARCH_HAS_EHCI is not set
5341 +# CONFIG_USB is not set
5342 +
5343 +#
5344 +# Enable Host or Gadget support to see Inventra options
5345 +#
5346 +
5347 +#
5348 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
5349 +#
5350 +# CONFIG_USB_GADGET is not set
5351 +# CONFIG_AR6000_WLAN is not set
5352 +CONFIG_MMC=y
5353 +CONFIG_MMC_DEBUG=y
5354 +CONFIG_MMC_UNSAFE_RESUME=y
5355 +
5356 +#
5357 +# MMC/SD/SDIO Card Drivers
5358 +#
5359 +CONFIG_MMC_BLOCK=y
5360 +CONFIG_MMC_BLOCK_BOUNCE=y
5361 +CONFIG_SDIO_UART=y
5362 +# CONFIG_MMC_TEST is not set
5363 +
5364 +#
5365 +# MMC/SD/SDIO Host Controller Drivers
5366 +#
5367 +CONFIG_MMC_SDHCI=y
5368 +CONFIG_MMC_SDHCI_S3C=y
5369 +# CONFIG_MMC_SPI is not set
5370 +# CONFIG_MEMSTICK is not set
5371 +# CONFIG_ACCESSIBILITY is not set
5372 +CONFIG_NEW_LEDS=y
5373 +# CONFIG_LEDS_CLASS is not set
5374 +
5375 +#
5376 +# LED drivers
5377 +#
5378 +
5379 +#
5380 +# LED Triggers
5381 +#
5382 +CONFIG_LEDS_TRIGGERS=y
5383 +# CONFIG_LEDS_TRIGGER_TIMER is not set
5384 +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
5385 +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
5386 +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
5387 +CONFIG_RTC_LIB=y
5388 +CONFIG_RTC_CLASS=y
5389 +CONFIG_RTC_HCTOSYS=y
5390 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
5391 +# CONFIG_RTC_DEBUG is not set
5392 +
5393 +#
5394 +# RTC interfaces
5395 +#
5396 +CONFIG_RTC_INTF_SYSFS=y
5397 +CONFIG_RTC_INTF_PROC=y
5398 +CONFIG_RTC_INTF_DEV=y
5399 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
5400 +# CONFIG_RTC_DRV_TEST is not set
5401 +
5402 +#
5403 +# I2C RTC drivers
5404 +#
5405 +# CONFIG_RTC_DRV_DS1307 is not set
5406 +# CONFIG_RTC_DRV_DS1374 is not set
5407 +# CONFIG_RTC_DRV_DS1672 is not set
5408 +# CONFIG_RTC_DRV_MAX6900 is not set
5409 +# CONFIG_RTC_DRV_RS5C372 is not set
5410 +# CONFIG_RTC_DRV_ISL1208 is not set
5411 +# CONFIG_RTC_DRV_X1205 is not set
5412 +# CONFIG_RTC_DRV_PCF8563 is not set
5413 +# CONFIG_RTC_DRV_PCF8583 is not set
5414 +CONFIG_RTC_DRV_PCF50633=y
5415 +# CONFIG_RTC_DRV_PCF50606 is not set
5416 +# CONFIG_RTC_DRV_M41T80 is not set
5417 +# CONFIG_RTC_DRV_S35390A is not set
5418 +# CONFIG_RTC_DRV_FM3130 is not set
5419 +
5420 +#
5421 +# SPI RTC drivers
5422 +#
5423 +# CONFIG_RTC_DRV_M41T94 is not set
5424 +# CONFIG_RTC_DRV_DS1305 is not set
5425 +# CONFIG_RTC_DRV_MAX6902 is not set
5426 +# CONFIG_RTC_DRV_R9701 is not set
5427 +# CONFIG_RTC_DRV_RS5C348 is not set
5428 +# CONFIG_RTC_DRV_DS3234 is not set
5429 +
5430 +#
5431 +# Platform RTC drivers
5432 +#
5433 +# CONFIG_RTC_DRV_CMOS is not set
5434 +# CONFIG_RTC_DRV_DS1286 is not set
5435 +# CONFIG_RTC_DRV_DS1511 is not set
5436 +# CONFIG_RTC_DRV_DS1553 is not set
5437 +# CONFIG_RTC_DRV_DS1742 is not set
5438 +# CONFIG_RTC_DRV_STK17TA8 is not set
5439 +# CONFIG_RTC_DRV_M48T86 is not set
5440 +# CONFIG_RTC_DRV_M48T35 is not set
5441 +# CONFIG_RTC_DRV_M48T59 is not set
5442 +# CONFIG_RTC_DRV_BQ4802 is not set
5443 +# CONFIG_RTC_DRV_V3020 is not set
5444 +
5445 +#
5446 +# on-CPU RTC drivers
5447 +#
5448 +# CONFIG_DMADEVICES is not set
5449 +
5450 +#
5451 +# Android
5452 +#
5453 +CONFIG_ANDROID_BINDER_IPC=y
5454 +# CONFIG_ANDROID_POWER is not set
5455 +CONFIG_ANDROID_LOGGER=y
5456 +# CONFIG_ANDROID_RAM_CONSOLE is not set
5457 +# CONFIG_ANDROID_TIMED_GPIO is not set
5458 +# CONFIG_ANDROID_PARANOID_NETWORK is not set
5459 +CONFIG_REGULATOR=y
5460 +# CONFIG_REGULATOR_DEBUG is not set
5461 +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
5462 +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
5463 +# CONFIG_REGULATOR_BQ24022 is not set
5464 +CONFIG_REGULATOR_PCF50633=y
5465 +# CONFIG_UIO is not set
5466 +
5467 +#
5468 +# File systems
5469 +#
5470 +CONFIG_EXT2_FS=y
5471 +# CONFIG_EXT2_FS_XATTR is not set
5472 +# CONFIG_EXT2_FS_XIP is not set
5473 +CONFIG_EXT3_FS=y
5474 +CONFIG_EXT3_FS_XATTR=y
5475 +CONFIG_EXT3_FS_POSIX_ACL=y
5476 +CONFIG_EXT3_FS_SECURITY=y
5477 +# CONFIG_EXT4_FS is not set
5478 +CONFIG_JBD=y
5479 +CONFIG_FS_MBCACHE=y
5480 +# CONFIG_REISERFS_FS is not set
5481 +# CONFIG_JFS_FS is not set
5482 +CONFIG_FS_POSIX_ACL=y
5483 +CONFIG_FILE_LOCKING=y
5484 +# CONFIG_XFS_FS is not set
5485 +# CONFIG_GFS2_FS is not set
5486 +# CONFIG_OCFS2_FS is not set
5487 +CONFIG_DNOTIFY=y
5488 +CONFIG_INOTIFY=y
5489 +CONFIG_INOTIFY_USER=y
5490 +# CONFIG_QUOTA is not set
5491 +# CONFIG_AUTOFS_FS is not set
5492 +# CONFIG_AUTOFS4_FS is not set
5493 +# CONFIG_FUSE_FS is not set
5494 +CONFIG_GENERIC_ACL=y
5495 +
5496 +#
5497 +# CD-ROM/DVD Filesystems
5498 +#
5499 +# CONFIG_ISO9660_FS is not set
5500 +# CONFIG_UDF_FS is not set
5501 +
5502 +#
5503 +# DOS/FAT/NT Filesystems
5504 +#
5505 +CONFIG_FAT_FS=y
5506 +# CONFIG_MSDOS_FS is not set
5507 +CONFIG_VFAT_FS=y
5508 +CONFIG_FAT_DEFAULT_CODEPAGE=437
5509 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
5510 +# CONFIG_NTFS_FS is not set
5511 +
5512 +#
5513 +# Pseudo filesystems
5514 +#
5515 +CONFIG_PROC_FS=y
5516 +CONFIG_PROC_SYSCTL=y
5517 +CONFIG_PROC_PAGE_MONITOR=y
5518 +CONFIG_SYSFS=y
5519 +CONFIG_TMPFS=y
5520 +CONFIG_TMPFS_POSIX_ACL=y
5521 +# CONFIG_HUGETLB_PAGE is not set
5522 +# CONFIG_CONFIGFS_FS is not set
5523 +
5524 +#
5525 +# Miscellaneous filesystems
5526 +#
5527 +# CONFIG_ADFS_FS is not set
5528 +# CONFIG_AFFS_FS is not set
5529 +# CONFIG_HFS_FS is not set
5530 +# CONFIG_HFSPLUS_FS is not set
5531 +# CONFIG_BEFS_FS is not set
5532 +# CONFIG_BFS_FS is not set
5533 +# CONFIG_EFS_FS is not set
5534 +CONFIG_JFFS2_FS=y
5535 +CONFIG_JFFS2_FS_DEBUG=0
5536 +CONFIG_JFFS2_FS_WRITEBUFFER=y
5537 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
5538 +CONFIG_JFFS2_SUMMARY=y
5539 +# CONFIG_JFFS2_FS_XATTR is not set
5540 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
5541 +CONFIG_JFFS2_ZLIB=y
5542 +# CONFIG_JFFS2_LZO is not set
5543 +CONFIG_JFFS2_RTIME=y
5544 +# CONFIG_JFFS2_RUBIN is not set
5545 +CONFIG_CRAMFS=y
5546 +# CONFIG_VXFS_FS is not set
5547 +# CONFIG_MINIX_FS is not set
5548 +# CONFIG_OMFS_FS is not set
5549 +# CONFIG_HPFS_FS is not set
5550 +# CONFIG_QNX4FS_FS is not set
5551 +CONFIG_ROMFS_FS=y
5552 +# CONFIG_SYSV_FS is not set
5553 +# CONFIG_UFS_FS is not set
5554 +CONFIG_NETWORK_FILESYSTEMS=y
5555 +# CONFIG_NFS_FS is not set
5556 +# CONFIG_NFSD is not set
5557 +# CONFIG_SMB_FS is not set
5558 +# CONFIG_CIFS is not set
5559 +# CONFIG_NCP_FS is not set
5560 +# CONFIG_CODA_FS is not set
5561 +# CONFIG_AFS_FS is not set
5562 +
5563 +#
5564 +# Partition Types
5565 +#
5566 +CONFIG_PARTITION_ADVANCED=y
5567 +# CONFIG_ACORN_PARTITION is not set
5568 +# CONFIG_OSF_PARTITION is not set
5569 +# CONFIG_AMIGA_PARTITION is not set
5570 +# CONFIG_ATARI_PARTITION is not set
5571 +# CONFIG_MAC_PARTITION is not set
5572 +CONFIG_MSDOS_PARTITION=y
5573 +# CONFIG_BSD_DISKLABEL is not set
5574 +# CONFIG_MINIX_SUBPARTITION is not set
5575 +# CONFIG_SOLARIS_X86_PARTITION is not set
5576 +# CONFIG_UNIXWARE_DISKLABEL is not set
5577 +# CONFIG_LDM_PARTITION is not set
5578 +# CONFIG_SGI_PARTITION is not set
5579 +# CONFIG_ULTRIX_PARTITION is not set
5580 +# CONFIG_SUN_PARTITION is not set
5581 +# CONFIG_KARMA_PARTITION is not set
5582 +# CONFIG_EFI_PARTITION is not set
5583 +# CONFIG_SYSV68_PARTITION is not set
5584 +CONFIG_NLS=y
5585 +CONFIG_NLS_DEFAULT="iso8859-1"
5586 +CONFIG_NLS_CODEPAGE_437=y
5587 +# CONFIG_NLS_CODEPAGE_737 is not set
5588 +# CONFIG_NLS_CODEPAGE_775 is not set
5589 +# CONFIG_NLS_CODEPAGE_850 is not set
5590 +# CONFIG_NLS_CODEPAGE_852 is not set
5591 +# CONFIG_NLS_CODEPAGE_855 is not set
5592 +# CONFIG_NLS_CODEPAGE_857 is not set
5593 +# CONFIG_NLS_CODEPAGE_860 is not set
5594 +# CONFIG_NLS_CODEPAGE_861 is not set
5595 +# CONFIG_NLS_CODEPAGE_862 is not set
5596 +# CONFIG_NLS_CODEPAGE_863 is not set
5597 +# CONFIG_NLS_CODEPAGE_864 is not set
5598 +# CONFIG_NLS_CODEPAGE_865 is not set
5599 +# CONFIG_NLS_CODEPAGE_866 is not set
5600 +# CONFIG_NLS_CODEPAGE_869 is not set
5601 +# CONFIG_NLS_CODEPAGE_936 is not set
5602 +# CONFIG_NLS_CODEPAGE_950 is not set
5603 +# CONFIG_NLS_CODEPAGE_932 is not set
5604 +# CONFIG_NLS_CODEPAGE_949 is not set
5605 +# CONFIG_NLS_CODEPAGE_874 is not set
5606 +# CONFIG_NLS_ISO8859_8 is not set
5607 +# CONFIG_NLS_CODEPAGE_1250 is not set
5608 +# CONFIG_NLS_CODEPAGE_1251 is not set
5609 +# CONFIG_NLS_ASCII is not set
5610 +CONFIG_NLS_ISO8859_1=y
5611 +# CONFIG_NLS_ISO8859_2 is not set
5612 +# CONFIG_NLS_ISO8859_3 is not set
5613 +# CONFIG_NLS_ISO8859_4 is not set
5614 +# CONFIG_NLS_ISO8859_5 is not set
5615 +# CONFIG_NLS_ISO8859_6 is not set
5616 +# CONFIG_NLS_ISO8859_7 is not set
5617 +# CONFIG_NLS_ISO8859_9 is not set
5618 +# CONFIG_NLS_ISO8859_13 is not set
5619 +# CONFIG_NLS_ISO8859_14 is not set
5620 +# CONFIG_NLS_ISO8859_15 is not set
5621 +# CONFIG_NLS_KOI8_R is not set
5622 +# CONFIG_NLS_KOI8_U is not set
5623 +CONFIG_NLS_UTF8=y
5624 +# CONFIG_DLM is not set
5625 +
5626 +#
5627 +# Kernel hacking
5628 +#
5629 +CONFIG_PRINTK_TIME=y
5630 +CONFIG_ENABLE_WARN_DEPRECATED=y
5631 +CONFIG_ENABLE_MUST_CHECK=y
5632 +CONFIG_FRAME_WARN=1024
5633 +CONFIG_MAGIC_SYSRQ=y
5634 +# CONFIG_UNUSED_SYMBOLS is not set
5635 +# CONFIG_DEBUG_FS is not set
5636 +# CONFIG_HEADERS_CHECK is not set
5637 +CONFIG_DEBUG_KERNEL=y
5638 +# CONFIG_DEBUG_SHIRQ is not set
5639 +CONFIG_DETECT_SOFTLOCKUP=y
5640 +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
5641 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
5642 +CONFIG_SCHED_DEBUG=y
5643 +# CONFIG_SCHEDSTATS is not set
5644 +# CONFIG_TIMER_STATS is not set
5645 +# CONFIG_DEBUG_OBJECTS is not set
5646 +# CONFIG_SLUB_DEBUG_ON is not set
5647 +# CONFIG_SLUB_STATS is not set
5648 +CONFIG_DEBUG_RT_MUTEXES=y
5649 +CONFIG_DEBUG_PI_LIST=y
5650 +# CONFIG_RT_MUTEX_TESTER is not set
5651 +CONFIG_DEBUG_SPINLOCK=y
5652 +CONFIG_DEBUG_MUTEXES=y
5653 +# CONFIG_DEBUG_LOCK_ALLOC is not set
5654 +# CONFIG_PROVE_LOCKING is not set
5655 +# CONFIG_LOCK_STAT is not set
5656 +CONFIG_DEBUG_SPINLOCK_SLEEP=y
5657 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
5658 +# CONFIG_DEBUG_KOBJECT is not set
5659 +CONFIG_DEBUG_BUGVERBOSE=y
5660 +CONFIG_DEBUG_INFO=y
5661 +# CONFIG_DEBUG_VM is not set
5662 +# CONFIG_DEBUG_WRITECOUNT is not set
5663 +CONFIG_DEBUG_MEMORY_INIT=y
5664 +# CONFIG_DEBUG_LIST is not set
5665 +# CONFIG_DEBUG_SG is not set
5666 +CONFIG_FRAME_POINTER=y
5667 +# CONFIG_BOOT_PRINTK_DELAY is not set
5668 +# CONFIG_RCU_TORTURE_TEST is not set
5669 +# CONFIG_RCU_CPU_STALL_DETECTOR is not set
5670 +# CONFIG_BACKTRACE_SELF_TEST is not set
5671 +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
5672 +# CONFIG_FAULT_INJECTION is not set
5673 +# CONFIG_LATENCYTOP is not set
5674 +CONFIG_SYSCTL_SYSCALL_CHECK=y
5675 +CONFIG_HAVE_FUNCTION_TRACER=y
5676 +
5677 +#
5678 +# Tracers
5679 +#
5680 +# CONFIG_FUNCTION_TRACER is not set
5681 +# CONFIG_SCHED_TRACER is not set
5682 +# CONFIG_CONTEXT_SWITCH_TRACER is not set
5683 +# CONFIG_BOOT_TRACER is not set
5684 +# CONFIG_STACK_TRACER is not set
5685 +CONFIG_DYNAMIC_PRINTK_DEBUG=y
5686 +# CONFIG_SAMPLES is not set
5687 +CONFIG_HAVE_ARCH_KGDB=y
5688 +# CONFIG_KGDB is not set
5689 +CONFIG_DEBUG_USER=y
5690 +CONFIG_DEBUG_ERRORS=y
5691 +# CONFIG_DEBUG_STACK_USAGE is not set
5692 +CONFIG_DEBUG_LL=y
5693 +# CONFIG_DEBUG_ICEDCC is not set
5694 +CONFIG_DEBUG_S3C_PORT=y
5695 +CONFIG_DEBUG_S3C_UART=3
5696 +
5697 +#
5698 +# Security options
5699 +#
5700 +# CONFIG_KEYS is not set
5701 +# CONFIG_SECURITY is not set
5702 +# CONFIG_SECURITYFS is not set
5703 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
5704 +CONFIG_CRYPTO=y
5705 +
5706 +#
5707 +# Crypto core or helper
5708 +#
5709 +# CONFIG_CRYPTO_FIPS is not set
5710 +CONFIG_CRYPTO_ALGAPI=y
5711 +CONFIG_CRYPTO_AEAD=y
5712 +CONFIG_CRYPTO_BLKCIPHER=y
5713 +CONFIG_CRYPTO_HASH=y
5714 +CONFIG_CRYPTO_RNG=y
5715 +CONFIG_CRYPTO_MANAGER=y
5716 +# CONFIG_CRYPTO_GF128MUL is not set
5717 +# CONFIG_CRYPTO_NULL is not set
5718 +# CONFIG_CRYPTO_CRYPTD is not set
5719 +# CONFIG_CRYPTO_AUTHENC is not set
5720 +# CONFIG_CRYPTO_TEST is not set
5721 +
5722 +#
5723 +# Authenticated Encryption with Associated Data
5724 +#
5725 +# CONFIG_CRYPTO_CCM is not set
5726 +# CONFIG_CRYPTO_GCM is not set
5727 +# CONFIG_CRYPTO_SEQIV is not set
5728 +
5729 +#
5730 +# Block modes
5731 +#
5732 +# CONFIG_CRYPTO_CBC is not set
5733 +# CONFIG_CRYPTO_CTR is not set
5734 +# CONFIG_CRYPTO_CTS is not set
5735 +CONFIG_CRYPTO_ECB=y
5736 +# CONFIG_CRYPTO_LRW is not set
5737 +# CONFIG_CRYPTO_PCBC is not set
5738 +# CONFIG_CRYPTO_XTS is not set
5739 +
5740 +#
5741 +# Hash modes
5742 +#
5743 +# CONFIG_CRYPTO_HMAC is not set
5744 +# CONFIG_CRYPTO_XCBC is not set
5745 +
5746 +#
5747 +# Digest
5748 +#
5749 +# CONFIG_CRYPTO_CRC32C is not set
5750 +# CONFIG_CRYPTO_MD4 is not set
5751 +CONFIG_CRYPTO_MD5=y
5752 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
5753 +# CONFIG_CRYPTO_RMD128 is not set
5754 +# CONFIG_CRYPTO_RMD160 is not set
5755 +# CONFIG_CRYPTO_RMD256 is not set
5756 +# CONFIG_CRYPTO_RMD320 is not set
5757 +CONFIG_CRYPTO_SHA1=y
5758 +# CONFIG_CRYPTO_SHA256 is not set
5759 +# CONFIG_CRYPTO_SHA512 is not set
5760 +# CONFIG_CRYPTO_TGR192 is not set
5761 +# CONFIG_CRYPTO_WP512 is not set
5762 +
5763 +#
5764 +# Ciphers
5765 +#
5766 +CONFIG_CRYPTO_AES=y
5767 +# CONFIG_CRYPTO_ANUBIS is not set
5768 +CONFIG_CRYPTO_ARC4=y
5769 +# CONFIG_CRYPTO_BLOWFISH is not set
5770 +# CONFIG_CRYPTO_CAMELLIA is not set
5771 +# CONFIG_CRYPTO_CAST5 is not set
5772 +# CONFIG_CRYPTO_CAST6 is not set
5773 +# CONFIG_CRYPTO_DES is not set
5774 +# CONFIG_CRYPTO_FCRYPT is not set
5775 +# CONFIG_CRYPTO_KHAZAD is not set
5776 +# CONFIG_CRYPTO_SALSA20 is not set
5777 +# CONFIG_CRYPTO_SEED is not set
5778 +# CONFIG_CRYPTO_SERPENT is not set
5779 +# CONFIG_CRYPTO_TEA is not set
5780 +# CONFIG_CRYPTO_TWOFISH is not set
5781 +
5782 +#
5783 +# Compression
5784 +#
5785 +# CONFIG_CRYPTO_DEFLATE is not set
5786 +# CONFIG_CRYPTO_LZO is not set
5787 +
5788 +#
5789 +# Random Number Generation
5790 +#
5791 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
5792 +CONFIG_CRYPTO_HW=y
5793 +
5794 +#
5795 +# Library routines
5796 +#
5797 +CONFIG_BITREVERSE=y
5798 +CONFIG_CRC_CCITT=y
5799 +# CONFIG_CRC16 is not set
5800 +# CONFIG_CRC_T10DIF is not set
5801 +# CONFIG_CRC_ITU_T is not set
5802 +CONFIG_CRC32=y
5803 +# CONFIG_CRC7 is not set
5804 +# CONFIG_LIBCRC32C is not set
5805 +CONFIG_ZLIB_INFLATE=y
5806 +CONFIG_ZLIB_DEFLATE=y
5807 +CONFIG_PLIST=y
5808 +CONFIG_HAS_IOMEM=y
5809 +CONFIG_HAS_DMA=y
5810 --- /dev/null
5811 +++ b/arch/arm/configs/s3c6400_defconfig
5812 @@ -0,0 +1,845 @@
5813 +#
5814 +# Automatically generated make config: don't edit
5815 +# Linux kernel version: 2.6.28-rc3
5816 +# Mon Nov  3 10:10:30 2008
5817 +#
5818 +CONFIG_ARM=y
5819 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
5820 +CONFIG_GENERIC_GPIO=y
5821 +# CONFIG_GENERIC_TIME is not set
5822 +# CONFIG_GENERIC_CLOCKEVENTS is not set
5823 +CONFIG_MMU=y
5824 +CONFIG_NO_IOPORT=y
5825 +CONFIG_GENERIC_HARDIRQS=y
5826 +CONFIG_STACKTRACE_SUPPORT=y
5827 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
5828 +CONFIG_LOCKDEP_SUPPORT=y
5829 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
5830 +CONFIG_HARDIRQS_SW_RESEND=y
5831 +CONFIG_GENERIC_IRQ_PROBE=y
5832 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
5833 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
5834 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
5835 +CONFIG_GENERIC_HWEIGHT=y
5836 +CONFIG_GENERIC_CALIBRATE_DELAY=y
5837 +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
5838 +CONFIG_VECTORS_BASE=0xffff0000
5839 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
5840 +
5841 +#
5842 +# General setup
5843 +#
5844 +CONFIG_EXPERIMENTAL=y
5845 +CONFIG_BROKEN_ON_SMP=y
5846 +CONFIG_INIT_ENV_ARG_LIMIT=32
5847 +CONFIG_LOCALVERSION=""
5848 +CONFIG_LOCALVERSION_AUTO=y
5849 +CONFIG_SWAP=y
5850 +# CONFIG_SYSVIPC is not set
5851 +# CONFIG_BSD_PROCESS_ACCT is not set
5852 +# CONFIG_IKCONFIG is not set
5853 +CONFIG_LOG_BUF_SHIFT=17
5854 +# CONFIG_CGROUPS is not set
5855 +# CONFIG_GROUP_SCHED is not set
5856 +CONFIG_SYSFS_DEPRECATED=y
5857 +CONFIG_SYSFS_DEPRECATED_V2=y
5858 +# CONFIG_RELAY is not set
5859 +CONFIG_NAMESPACES=y
5860 +# CONFIG_UTS_NS is not set
5861 +# CONFIG_USER_NS is not set
5862 +# CONFIG_PID_NS is not set
5863 +CONFIG_BLK_DEV_INITRD=y
5864 +CONFIG_INITRAMFS_SOURCE=""
5865 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
5866 +CONFIG_SYSCTL=y
5867 +# CONFIG_EMBEDDED is not set
5868 +CONFIG_UID16=y
5869 +CONFIG_SYSCTL_SYSCALL=y
5870 +CONFIG_KALLSYMS=y
5871 +CONFIG_KALLSYMS_ALL=y
5872 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
5873 +CONFIG_HOTPLUG=y
5874 +CONFIG_PRINTK=y
5875 +CONFIG_BUG=y
5876 +CONFIG_ELF_CORE=y
5877 +CONFIG_COMPAT_BRK=y
5878 +CONFIG_BASE_FULL=y
5879 +CONFIG_FUTEX=y
5880 +CONFIG_ANON_INODES=y
5881 +CONFIG_EPOLL=y
5882 +CONFIG_SIGNALFD=y
5883 +CONFIG_TIMERFD=y
5884 +CONFIG_EVENTFD=y
5885 +CONFIG_SHMEM=y
5886 +CONFIG_AIO=y
5887 +CONFIG_VM_EVENT_COUNTERS=y
5888 +CONFIG_SLUB_DEBUG=y
5889 +# CONFIG_SLAB is not set
5890 +CONFIG_SLUB=y
5891 +# CONFIG_SLOB is not set
5892 +# CONFIG_PROFILING is not set
5893 +# CONFIG_MARKERS is not set
5894 +CONFIG_HAVE_OPROFILE=y
5895 +# CONFIG_KPROBES is not set
5896 +CONFIG_HAVE_KPROBES=y
5897 +CONFIG_HAVE_KRETPROBES=y
5898 +CONFIG_HAVE_CLK=y
5899 +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
5900 +CONFIG_SLABINFO=y
5901 +CONFIG_RT_MUTEXES=y
5902 +# CONFIG_TINY_SHMEM is not set
5903 +CONFIG_BASE_SMALL=0
5904 +CONFIG_MODULES=y
5905 +# CONFIG_MODULE_FORCE_LOAD is not set
5906 +CONFIG_MODULE_UNLOAD=y
5907 +# CONFIG_MODULE_FORCE_UNLOAD is not set
5908 +# CONFIG_MODVERSIONS is not set
5909 +# CONFIG_MODULE_SRCVERSION_ALL is not set
5910 +CONFIG_KMOD=y
5911 +CONFIG_BLOCK=y
5912 +CONFIG_LBD=y
5913 +# CONFIG_BLK_DEV_IO_TRACE is not set
5914 +CONFIG_LSF=y
5915 +# CONFIG_BLK_DEV_BSG is not set
5916 +# CONFIG_BLK_DEV_INTEGRITY is not set
5917 +
5918 +#
5919 +# IO Schedulers
5920 +#
5921 +CONFIG_IOSCHED_NOOP=y
5922 +CONFIG_IOSCHED_AS=y
5923 +CONFIG_IOSCHED_DEADLINE=y
5924 +CONFIG_IOSCHED_CFQ=y
5925 +# CONFIG_DEFAULT_AS is not set
5926 +# CONFIG_DEFAULT_DEADLINE is not set
5927 +CONFIG_DEFAULT_CFQ=y
5928 +# CONFIG_DEFAULT_NOOP is not set
5929 +CONFIG_DEFAULT_IOSCHED="cfq"
5930 +CONFIG_CLASSIC_RCU=y
5931 +# CONFIG_FREEZER is not set
5932 +
5933 +#
5934 +# System Type
5935 +#
5936 +# CONFIG_ARCH_AAEC2000 is not set
5937 +# CONFIG_ARCH_INTEGRATOR is not set
5938 +# CONFIG_ARCH_REALVIEW is not set
5939 +# CONFIG_ARCH_VERSATILE is not set
5940 +# CONFIG_ARCH_AT91 is not set
5941 +# CONFIG_ARCH_CLPS7500 is not set
5942 +# CONFIG_ARCH_CLPS711X is not set
5943 +# CONFIG_ARCH_EBSA110 is not set
5944 +# CONFIG_ARCH_EP93XX is not set
5945 +# CONFIG_ARCH_FOOTBRIDGE is not set
5946 +# CONFIG_ARCH_NETX is not set
5947 +# CONFIG_ARCH_H720X is not set
5948 +# CONFIG_ARCH_IMX is not set
5949 +# CONFIG_ARCH_IOP13XX is not set
5950 +# CONFIG_ARCH_IOP32X is not set
5951 +# CONFIG_ARCH_IOP33X is not set
5952 +# CONFIG_ARCH_IXP23XX is not set
5953 +# CONFIG_ARCH_IXP2000 is not set
5954 +# CONFIG_ARCH_IXP4XX is not set
5955 +# CONFIG_ARCH_L7200 is not set
5956 +# CONFIG_ARCH_KIRKWOOD is not set
5957 +# CONFIG_ARCH_KS8695 is not set
5958 +# CONFIG_ARCH_NS9XXX is not set
5959 +# CONFIG_ARCH_LOKI is not set
5960 +# CONFIG_ARCH_MV78XX0 is not set
5961 +# CONFIG_ARCH_MXC is not set
5962 +# CONFIG_ARCH_ORION5X is not set
5963 +# CONFIG_ARCH_PNX4008 is not set
5964 +# CONFIG_ARCH_PXA is not set
5965 +# CONFIG_ARCH_RPC is not set
5966 +# CONFIG_ARCH_SA1100 is not set
5967 +# CONFIG_ARCH_S3C2410 is not set
5968 +CONFIG_ARCH_S3C64XX=y
5969 +# CONFIG_ARCH_SHARK is not set
5970 +# CONFIG_ARCH_LH7A40X is not set
5971 +# CONFIG_ARCH_DAVINCI is not set
5972 +# CONFIG_ARCH_OMAP is not set
5973 +# CONFIG_ARCH_MSM is not set
5974 +CONFIG_PLAT_S3C64XX=y
5975 +CONFIG_CPU_S3C6400_INIT=y
5976 +CONFIG_CPU_S3C6400_CLOCK=y
5977 +CONFIG_S3C64XX_SETUP_I2C0=y
5978 +CONFIG_S3C64XX_SETUP_I2C1=y
5979 +CONFIG_PLAT_S3C=y
5980 +
5981 +#
5982 +# Boot options
5983 +#
5984 +CONFIG_S3C_BOOT_ERROR_RESET=y
5985 +
5986 +#
5987 +# Power management
5988 +#
5989 +CONFIG_S3C_LOWLEVEL_UART_PORT=0
5990 +CONFIG_S3C_GPIO_SPACE=0
5991 +CONFIG_S3C_GPIO_TRACK=y
5992 +CONFIG_S3C_GPIO_PULL_UPDOWN=y
5993 +CONFIG_S3C_GPIO_CFG_S3C24XX=y
5994 +CONFIG_S3C_GPIO_CFG_S3C64XX=y
5995 +CONFIG_S3C_DEV_HSMMC=y
5996 +CONFIG_S3C_DEV_HSMMC1=y
5997 +CONFIG_S3C_DEV_I2C1=y
5998 +CONFIG_CPU_S3C6410=y
5999 +CONFIG_S3C6410_SETUP_SDHCI=y
6000 +CONFIG_MACH_SMDK6410=y
6001 +CONFIG_SMDK6410_SD_CH0=y
6002 +# CONFIG_SMDK6410_SD_CH1 is not set
6003 +
6004 +#
6005 +# Processor Type
6006 +#
6007 +CONFIG_CPU_32=y
6008 +CONFIG_CPU_V6=y
6009 +CONFIG_CPU_32v6K=y
6010 +CONFIG_CPU_32v6=y
6011 +CONFIG_CPU_ABRT_EV6=y
6012 +CONFIG_CPU_PABRT_NOIFAR=y
6013 +CONFIG_CPU_CACHE_V6=y
6014 +CONFIG_CPU_CACHE_VIPT=y
6015 +CONFIG_CPU_COPY_V6=y
6016 +CONFIG_CPU_TLB_V6=y
6017 +CONFIG_CPU_HAS_ASID=y
6018 +CONFIG_CPU_CP15=y
6019 +CONFIG_CPU_CP15_MMU=y
6020 +
6021 +#
6022 +# Processor Features
6023 +#
6024 +CONFIG_ARM_THUMB=y
6025 +# CONFIG_CPU_ICACHE_DISABLE is not set
6026 +# CONFIG_CPU_DCACHE_DISABLE is not set
6027 +# CONFIG_CPU_BPREDICT_DISABLE is not set
6028 +# CONFIG_OUTER_CACHE is not set
6029 +CONFIG_ARM_VIC=y
6030 +
6031 +#
6032 +# Bus support
6033 +#
6034 +# CONFIG_PCI_SYSCALL is not set
6035 +# CONFIG_ARCH_SUPPORTS_MSI is not set
6036 +# CONFIG_PCCARD is not set
6037 +
6038 +#
6039 +# Kernel Features
6040 +#
6041 +CONFIG_VMSPLIT_3G=y
6042 +# CONFIG_VMSPLIT_2G is not set
6043 +# CONFIG_VMSPLIT_1G is not set
6044 +CONFIG_PAGE_OFFSET=0xC0000000
6045 +# CONFIG_PREEMPT is not set
6046 +CONFIG_HZ=100
6047 +CONFIG_AEABI=y
6048 +CONFIG_OABI_COMPAT=y
6049 +CONFIG_ARCH_FLATMEM_HAS_HOLES=y
6050 +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
6051 +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
6052 +CONFIG_SELECT_MEMORY_MODEL=y
6053 +CONFIG_FLATMEM_MANUAL=y
6054 +# CONFIG_DISCONTIGMEM_MANUAL is not set
6055 +# CONFIG_SPARSEMEM_MANUAL is not set
6056 +CONFIG_FLATMEM=y
6057 +CONFIG_FLAT_NODE_MEM_MAP=y
6058 +CONFIG_PAGEFLAGS_EXTENDED=y
6059 +CONFIG_SPLIT_PTLOCK_CPUS=4
6060 +# CONFIG_RESOURCES_64BIT is not set
6061 +# CONFIG_PHYS_ADDR_T_64BIT is not set
6062 +CONFIG_ZONE_DMA_FLAG=0
6063 +CONFIG_VIRT_TO_BUS=y
6064 +CONFIG_UNEVICTABLE_LRU=y
6065 +CONFIG_ALIGNMENT_TRAP=y
6066 +
6067 +#
6068 +# Boot options
6069 +#
6070 +CONFIG_ZBOOT_ROM_TEXT=0
6071 +CONFIG_ZBOOT_ROM_BSS=0
6072 +CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M"
6073 +# CONFIG_XIP_KERNEL is not set
6074 +# CONFIG_KEXEC is not set
6075 +
6076 +#
6077 +# CPU Power Management
6078 +#
6079 +# CONFIG_CPU_IDLE is not set
6080 +
6081 +#
6082 +# Floating point emulation
6083 +#
6084 +
6085 +#
6086 +# At least one emulation must be selected
6087 +#
6088 +# CONFIG_FPE_NWFPE is not set
6089 +# CONFIG_FPE_FASTFPE is not set
6090 +CONFIG_VFP=y
6091 +
6092 +#
6093 +# Userspace binary formats
6094 +#
6095 +CONFIG_BINFMT_ELF=y
6096 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
6097 +CONFIG_HAVE_AOUT=y
6098 +# CONFIG_BINFMT_AOUT is not set
6099 +# CONFIG_BINFMT_MISC is not set
6100 +
6101 +#
6102 +# Power management options
6103 +#
6104 +# CONFIG_PM is not set
6105 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
6106 +# CONFIG_NET is not set
6107 +
6108 +#
6109 +# Device Drivers
6110 +#
6111 +
6112 +#
6113 +# Generic Driver Options
6114 +#
6115 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
6116 +CONFIG_STANDALONE=y
6117 +CONFIG_PREVENT_FIRMWARE_BUILD=y
6118 +CONFIG_FW_LOADER=y
6119 +CONFIG_FIRMWARE_IN_KERNEL=y
6120 +CONFIG_EXTRA_FIRMWARE=""
6121 +# CONFIG_DEBUG_DRIVER is not set
6122 +# CONFIG_DEBUG_DEVRES is not set
6123 +# CONFIG_SYS_HYPERVISOR is not set
6124 +# CONFIG_MTD is not set
6125 +# CONFIG_PARPORT is not set
6126 +CONFIG_BLK_DEV=y
6127 +# CONFIG_BLK_DEV_COW_COMMON is not set
6128 +CONFIG_BLK_DEV_LOOP=y
6129 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
6130 +CONFIG_BLK_DEV_RAM=y
6131 +CONFIG_BLK_DEV_RAM_COUNT=16
6132 +CONFIG_BLK_DEV_RAM_SIZE=4096
6133 +# CONFIG_BLK_DEV_XIP is not set
6134 +# CONFIG_CDROM_PKTCDVD is not set
6135 +CONFIG_MISC_DEVICES=y
6136 +# CONFIG_EEPROM_93CX6 is not set
6137 +# CONFIG_ENCLOSURE_SERVICES is not set
6138 +CONFIG_HAVE_IDE=y
6139 +# CONFIG_IDE is not set
6140 +
6141 +#
6142 +# SCSI device support
6143 +#
6144 +# CONFIG_RAID_ATTRS is not set
6145 +# CONFIG_SCSI is not set
6146 +# CONFIG_SCSI_DMA is not set
6147 +# CONFIG_SCSI_NETLINK is not set
6148 +# CONFIG_ATA is not set
6149 +# CONFIG_MD is not set
6150 +
6151 +#
6152 +# Input device support
6153 +#
6154 +CONFIG_INPUT=y
6155 +# CONFIG_INPUT_FF_MEMLESS is not set
6156 +# CONFIG_INPUT_POLLDEV is not set
6157 +
6158 +#
6159 +# Userland interfaces
6160 +#
6161 +CONFIG_INPUT_MOUSEDEV=y
6162 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
6163 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
6164 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
6165 +# CONFIG_INPUT_JOYDEV is not set
6166 +# CONFIG_INPUT_EVDEV is not set
6167 +# CONFIG_INPUT_EVBUG is not set
6168 +
6169 +#
6170 +# Input Device Drivers
6171 +#
6172 +CONFIG_INPUT_KEYBOARD=y
6173 +CONFIG_KEYBOARD_ATKBD=y
6174 +# CONFIG_KEYBOARD_SUNKBD is not set
6175 +# CONFIG_KEYBOARD_LKKBD is not set
6176 +# CONFIG_KEYBOARD_XTKBD is not set
6177 +# CONFIG_KEYBOARD_NEWTON is not set
6178 +# CONFIG_KEYBOARD_STOWAWAY is not set
6179 +# CONFIG_KEYBOARD_GPIO is not set
6180 +CONFIG_INPUT_MOUSE=y
6181 +CONFIG_MOUSE_PS2=y
6182 +CONFIG_MOUSE_PS2_ALPS=y
6183 +CONFIG_MOUSE_PS2_LOGIPS2PP=y
6184 +CONFIG_MOUSE_PS2_SYNAPTICS=y
6185 +CONFIG_MOUSE_PS2_LIFEBOOK=y
6186 +CONFIG_MOUSE_PS2_TRACKPOINT=y
6187 +# CONFIG_MOUSE_PS2_ELANTECH is not set
6188 +# CONFIG_MOUSE_PS2_TOUCHKIT is not set
6189 +# CONFIG_MOUSE_SERIAL is not set
6190 +# CONFIG_MOUSE_APPLETOUCH is not set
6191 +# CONFIG_MOUSE_BCM5974 is not set
6192 +# CONFIG_MOUSE_VSXXXAA is not set
6193 +# CONFIG_MOUSE_GPIO is not set
6194 +# CONFIG_INPUT_JOYSTICK is not set
6195 +# CONFIG_INPUT_TABLET is not set
6196 +# CONFIG_INPUT_TOUCHSCREEN is not set
6197 +# CONFIG_INPUT_MISC is not set
6198 +
6199 +#
6200 +# Hardware I/O ports
6201 +#
6202 +CONFIG_SERIO=y
6203 +CONFIG_SERIO_SERPORT=y
6204 +CONFIG_SERIO_LIBPS2=y
6205 +# CONFIG_SERIO_RAW is not set
6206 +# CONFIG_GAMEPORT is not set
6207 +
6208 +#
6209 +# Character devices
6210 +#
6211 +CONFIG_VT=y
6212 +CONFIG_CONSOLE_TRANSLATIONS=y
6213 +CONFIG_VT_CONSOLE=y
6214 +CONFIG_HW_CONSOLE=y
6215 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
6216 +CONFIG_DEVKMEM=y
6217 +# CONFIG_SERIAL_NONSTANDARD is not set
6218 +
6219 +#
6220 +# Serial drivers
6221 +#
6222 +CONFIG_SERIAL_8250=y
6223 +# CONFIG_SERIAL_8250_CONSOLE is not set
6224 +CONFIG_SERIAL_8250_NR_UARTS=4
6225 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4
6226 +# CONFIG_SERIAL_8250_EXTENDED is not set
6227 +
6228 +#
6229 +# Non-8250 serial port support
6230 +#
6231 +CONFIG_SERIAL_SAMSUNG=y
6232 +CONFIG_SERIAL_SAMSUNG_UARTS=4
6233 +# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
6234 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y
6235 +CONFIG_SERIAL_S3C6400=y
6236 +CONFIG_SERIAL_CORE=y
6237 +CONFIG_SERIAL_CORE_CONSOLE=y
6238 +CONFIG_UNIX98_PTYS=y
6239 +CONFIG_LEGACY_PTYS=y
6240 +CONFIG_LEGACY_PTY_COUNT=256
6241 +# CONFIG_IPMI_HANDLER is not set
6242 +CONFIG_HW_RANDOM=y
6243 +# CONFIG_NVRAM is not set
6244 +# CONFIG_R3964 is not set
6245 +# CONFIG_RAW_DRIVER is not set
6246 +# CONFIG_TCG_TPM is not set
6247 +CONFIG_I2C=y
6248 +CONFIG_I2C_BOARDINFO=y
6249 +CONFIG_I2C_CHARDEV=y
6250 +CONFIG_I2C_HELPER_AUTO=y
6251 +
6252 +#
6253 +# I2C Hardware Bus support
6254 +#
6255 +
6256 +#
6257 +# I2C system bus drivers (mostly embedded / system-on-chip)
6258 +#
6259 +# CONFIG_I2C_GPIO is not set
6260 +# CONFIG_I2C_OCORES is not set
6261 +CONFIG_I2C_S3C2410=y
6262 +# CONFIG_I2C_SIMTEC is not set
6263 +
6264 +#
6265 +# External I2C/SMBus adapter drivers
6266 +#
6267 +# CONFIG_I2C_PARPORT_LIGHT is not set
6268 +# CONFIG_I2C_TAOS_EVM is not set
6269 +
6270 +#
6271 +# Other I2C/SMBus bus drivers
6272 +#
6273 +# CONFIG_I2C_PCA_PLATFORM is not set
6274 +# CONFIG_I2C_STUB is not set
6275 +
6276 +#
6277 +# Miscellaneous I2C Chip support
6278 +#
6279 +# CONFIG_DS1682 is not set
6280 +CONFIG_AT24=y
6281 +# CONFIG_SENSORS_EEPROM is not set
6282 +# CONFIG_SENSORS_PCF8574 is not set
6283 +# CONFIG_PCF8575 is not set
6284 +# CONFIG_SENSORS_PCA9539 is not set
6285 +# CONFIG_SENSORS_PCF8591 is not set
6286 +# CONFIG_TPS65010 is not set
6287 +# CONFIG_SENSORS_MAX6875 is not set
6288 +# CONFIG_SENSORS_TSL2550 is not set
6289 +# CONFIG_I2C_DEBUG_CORE is not set
6290 +# CONFIG_I2C_DEBUG_ALGO is not set
6291 +# CONFIG_I2C_DEBUG_BUS is not set
6292 +# CONFIG_I2C_DEBUG_CHIP is not set
6293 +# CONFIG_SPI is not set
6294 +CONFIG_ARCH_REQUIRE_GPIOLIB=y
6295 +CONFIG_GPIOLIB=y
6296 +# CONFIG_DEBUG_GPIO is not set
6297 +# CONFIG_GPIO_SYSFS is not set
6298 +
6299 +#
6300 +# I2C GPIO expanders:
6301 +#
6302 +# CONFIG_GPIO_MAX732X is not set
6303 +# CONFIG_GPIO_PCA953X is not set
6304 +# CONFIG_GPIO_PCF857X is not set
6305 +
6306 +#
6307 +# PCI GPIO expanders:
6308 +#
6309 +
6310 +#
6311 +# SPI GPIO expanders:
6312 +#
6313 +# CONFIG_W1 is not set
6314 +# CONFIG_POWER_SUPPLY is not set
6315 +CONFIG_HWMON=y
6316 +# CONFIG_HWMON_VID is not set
6317 +# CONFIG_SENSORS_AD7414 is not set
6318 +# CONFIG_SENSORS_AD7418 is not set
6319 +# CONFIG_SENSORS_ADM1021 is not set
6320 +# CONFIG_SENSORS_ADM1025 is not set
6321 +# CONFIG_SENSORS_ADM1026 is not set
6322 +# CONFIG_SENSORS_ADM1029 is not set
6323 +# CONFIG_SENSORS_ADM1031 is not set
6324 +# CONFIG_SENSORS_ADM9240 is not set
6325 +# CONFIG_SENSORS_ADT7470 is not set
6326 +# CONFIG_SENSORS_ADT7473 is not set
6327 +# CONFIG_SENSORS_ATXP1 is not set
6328 +# CONFIG_SENSORS_DS1621 is not set
6329 +# CONFIG_SENSORS_F71805F is not set
6330 +# CONFIG_SENSORS_F71882FG is not set
6331 +# CONFIG_SENSORS_F75375S is not set
6332 +# CONFIG_SENSORS_GL518SM is not set
6333 +# CONFIG_SENSORS_GL520SM is not set
6334 +# CONFIG_SENSORS_IT87 is not set
6335 +# CONFIG_SENSORS_LM63 is not set
6336 +# CONFIG_SENSORS_LM75 is not set
6337 +# CONFIG_SENSORS_LM77 is not set
6338 +# CONFIG_SENSORS_LM78 is not set
6339 +# CONFIG_SENSORS_LM80 is not set
6340 +# CONFIG_SENSORS_LM83 is not set
6341 +# CONFIG_SENSORS_LM85 is not set
6342 +# CONFIG_SENSORS_LM87 is not set
6343 +# CONFIG_SENSORS_LM90 is not set
6344 +# CONFIG_SENSORS_LM92 is not set
6345 +# CONFIG_SENSORS_LM93 is not set
6346 +# CONFIG_SENSORS_MAX1619 is not set
6347 +# CONFIG_SENSORS_MAX6650 is not set
6348 +# CONFIG_SENSORS_PC87360 is not set
6349 +# CONFIG_SENSORS_PC87427 is not set
6350 +# CONFIG_SENSORS_DME1737 is not set
6351 +# CONFIG_SENSORS_SMSC47M1 is not set
6352 +# CONFIG_SENSORS_SMSC47M192 is not set
6353 +# CONFIG_SENSORS_SMSC47B397 is not set
6354 +# CONFIG_SENSORS_ADS7828 is not set
6355 +# CONFIG_SENSORS_THMC50 is not set
6356 +# CONFIG_SENSORS_VT1211 is not set
6357 +# CONFIG_SENSORS_W83781D is not set
6358 +# CONFIG_SENSORS_W83791D is not set
6359 +# CONFIG_SENSORS_W83792D is not set
6360 +# CONFIG_SENSORS_W83793 is not set
6361 +# CONFIG_SENSORS_W83L785TS is not set
6362 +# CONFIG_SENSORS_W83L786NG is not set
6363 +# CONFIG_SENSORS_W83627HF is not set
6364 +# CONFIG_SENSORS_W83627EHF is not set
6365 +# CONFIG_HWMON_DEBUG_CHIP is not set
6366 +# CONFIG_THERMAL is not set
6367 +# CONFIG_THERMAL_HWMON is not set
6368 +# CONFIG_WATCHDOG is not set
6369 +
6370 +#
6371 +# Sonics Silicon Backplane
6372 +#
6373 +CONFIG_SSB_POSSIBLE=y
6374 +# CONFIG_SSB is not set
6375 +
6376 +#
6377 +# Multifunction device drivers
6378 +#
6379 +# CONFIG_MFD_CORE is not set
6380 +# CONFIG_MFD_SM501 is not set
6381 +# CONFIG_MFD_ASIC3 is not set
6382 +# CONFIG_HTC_EGPIO is not set
6383 +# CONFIG_HTC_PASIC3 is not set
6384 +# CONFIG_MFD_TMIO is not set
6385 +# CONFIG_MFD_T7L66XB is not set
6386 +# CONFIG_MFD_TC6387XB is not set
6387 +# CONFIG_MFD_TC6393XB is not set
6388 +# CONFIG_PMIC_DA903X is not set
6389 +# CONFIG_MFD_WM8400 is not set
6390 +# CONFIG_MFD_WM8350_I2C is not set
6391 +
6392 +#
6393 +# Multimedia devices
6394 +#
6395 +
6396 +#
6397 +# Multimedia core support
6398 +#
6399 +# CONFIG_VIDEO_DEV is not set
6400 +# CONFIG_VIDEO_MEDIA is not set
6401 +
6402 +#
6403 +# Multimedia drivers
6404 +#
6405 +# CONFIG_DAB is not set
6406 +
6407 +#
6408 +# Graphics support
6409 +#
6410 +# CONFIG_VGASTATE is not set
6411 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
6412 +# CONFIG_FB is not set
6413 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
6414 +
6415 +#
6416 +# Display device support
6417 +#
6418 +# CONFIG_DISPLAY_SUPPORT is not set
6419 +
6420 +#
6421 +# Console display driver support
6422 +#
6423 +# CONFIG_VGA_CONSOLE is not set
6424 +CONFIG_DUMMY_CONSOLE=y
6425 +# CONFIG_SOUND is not set
6426 +CONFIG_HID_SUPPORT=y
6427 +CONFIG_HID=y
6428 +CONFIG_HID_DEBUG=y
6429 +# CONFIG_HIDRAW is not set
6430 +# CONFIG_HID_PID is not set
6431 +
6432 +#
6433 +# Special HID drivers
6434 +#
6435 +# CONFIG_HID_COMPAT is not set
6436 +CONFIG_USB_SUPPORT=y
6437 +CONFIG_USB_ARCH_HAS_HCD=y
6438 +# CONFIG_USB_ARCH_HAS_OHCI is not set
6439 +# CONFIG_USB_ARCH_HAS_EHCI is not set
6440 +# CONFIG_USB is not set
6441 +
6442 +#
6443 +# Enable Host or Gadget support to see Inventra options
6444 +#
6445 +
6446 +#
6447 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
6448 +#
6449 +# CONFIG_USB_GADGET is not set
6450 +CONFIG_MMC=y
6451 +CONFIG_MMC_DEBUG=y
6452 +CONFIG_MMC_UNSAFE_RESUME=y
6453 +
6454 +#
6455 +# MMC/SD/SDIO Card Drivers
6456 +#
6457 +CONFIG_MMC_BLOCK=y
6458 +CONFIG_MMC_BLOCK_BOUNCE=y
6459 +CONFIG_SDIO_UART=y
6460 +# CONFIG_MMC_TEST is not set
6461 +
6462 +#
6463 +# MMC/SD/SDIO Host Controller Drivers
6464 +#
6465 +CONFIG_MMC_SDHCI=y
6466 +CONFIG_MMC_SDHCI_S3C=y
6467 +# CONFIG_MEMSTICK is not set
6468 +# CONFIG_ACCESSIBILITY is not set
6469 +# CONFIG_NEW_LEDS is not set
6470 +CONFIG_RTC_LIB=y
6471 +# CONFIG_RTC_CLASS is not set
6472 +# CONFIG_DMADEVICES is not set
6473 +
6474 +#
6475 +# Voltage and Current regulators
6476 +#
6477 +# CONFIG_REGULATOR is not set
6478 +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
6479 +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
6480 +# CONFIG_REGULATOR_BQ24022 is not set
6481 +# CONFIG_UIO is not set
6482 +
6483 +#
6484 +# File systems
6485 +#
6486 +CONFIG_EXT2_FS=y
6487 +# CONFIG_EXT2_FS_XATTR is not set
6488 +# CONFIG_EXT2_FS_XIP is not set
6489 +CONFIG_EXT3_FS=y
6490 +CONFIG_EXT3_FS_XATTR=y
6491 +CONFIG_EXT3_FS_POSIX_ACL=y
6492 +CONFIG_EXT3_FS_SECURITY=y
6493 +# CONFIG_EXT4_FS is not set
6494 +CONFIG_JBD=y
6495 +CONFIG_FS_MBCACHE=y
6496 +# CONFIG_REISERFS_FS is not set
6497 +# CONFIG_JFS_FS is not set
6498 +CONFIG_FS_POSIX_ACL=y
6499 +CONFIG_FILE_LOCKING=y
6500 +# CONFIG_XFS_FS is not set
6501 +# CONFIG_GFS2_FS is not set
6502 +CONFIG_DNOTIFY=y
6503 +CONFIG_INOTIFY=y
6504 +CONFIG_INOTIFY_USER=y
6505 +# CONFIG_QUOTA is not set
6506 +# CONFIG_AUTOFS_FS is not set
6507 +# CONFIG_AUTOFS4_FS is not set
6508 +# CONFIG_FUSE_FS is not set
6509 +CONFIG_GENERIC_ACL=y
6510 +
6511 +#
6512 +# CD-ROM/DVD Filesystems
6513 +#
6514 +# CONFIG_ISO9660_FS is not set
6515 +# CONFIG_UDF_FS is not set
6516 +
6517 +#
6518 +# DOS/FAT/NT Filesystems
6519 +#
6520 +# CONFIG_MSDOS_FS is not set
6521 +# CONFIG_VFAT_FS is not set
6522 +# CONFIG_NTFS_FS is not set
6523 +
6524 +#
6525 +# Pseudo filesystems
6526 +#
6527 +CONFIG_PROC_FS=y
6528 +CONFIG_PROC_SYSCTL=y
6529 +CONFIG_PROC_PAGE_MONITOR=y
6530 +CONFIG_SYSFS=y
6531 +CONFIG_TMPFS=y
6532 +CONFIG_TMPFS_POSIX_ACL=y
6533 +# CONFIG_HUGETLB_PAGE is not set
6534 +# CONFIG_CONFIGFS_FS is not set
6535 +
6536 +#
6537 +# Miscellaneous filesystems
6538 +#
6539 +# CONFIG_ADFS_FS is not set
6540 +# CONFIG_AFFS_FS is not set
6541 +# CONFIG_HFS_FS is not set
6542 +# CONFIG_HFSPLUS_FS is not set
6543 +# CONFIG_BEFS_FS is not set
6544 +# CONFIG_BFS_FS is not set
6545 +# CONFIG_EFS_FS is not set
6546 +CONFIG_CRAMFS=y
6547 +# CONFIG_VXFS_FS is not set
6548 +# CONFIG_MINIX_FS is not set
6549 +# CONFIG_OMFS_FS is not set
6550 +# CONFIG_HPFS_FS is not set
6551 +# CONFIG_QNX4FS_FS is not set
6552 +CONFIG_ROMFS_FS=y
6553 +# CONFIG_SYSV_FS is not set
6554 +# CONFIG_UFS_FS is not set
6555 +
6556 +#
6557 +# Partition Types
6558 +#
6559 +# CONFIG_PARTITION_ADVANCED is not set
6560 +CONFIG_MSDOS_PARTITION=y
6561 +# CONFIG_NLS is not set
6562 +
6563 +#
6564 +# Kernel hacking
6565 +#
6566 +# CONFIG_PRINTK_TIME is not set
6567 +CONFIG_ENABLE_WARN_DEPRECATED=y
6568 +CONFIG_ENABLE_MUST_CHECK=y
6569 +CONFIG_FRAME_WARN=1024
6570 +CONFIG_MAGIC_SYSRQ=y
6571 +# CONFIG_UNUSED_SYMBOLS is not set
6572 +# CONFIG_DEBUG_FS is not set
6573 +# CONFIG_HEADERS_CHECK is not set
6574 +CONFIG_DEBUG_KERNEL=y
6575 +# CONFIG_DEBUG_SHIRQ is not set
6576 +CONFIG_DETECT_SOFTLOCKUP=y
6577 +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
6578 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
6579 +CONFIG_SCHED_DEBUG=y
6580 +# CONFIG_SCHEDSTATS is not set
6581 +# CONFIG_TIMER_STATS is not set
6582 +# CONFIG_DEBUG_OBJECTS is not set
6583 +# CONFIG_SLUB_DEBUG_ON is not set
6584 +# CONFIG_SLUB_STATS is not set
6585 +CONFIG_DEBUG_RT_MUTEXES=y
6586 +CONFIG_DEBUG_PI_LIST=y
6587 +# CONFIG_RT_MUTEX_TESTER is not set
6588 +CONFIG_DEBUG_SPINLOCK=y
6589 +CONFIG_DEBUG_MUTEXES=y
6590 +# CONFIG_DEBUG_LOCK_ALLOC is not set
6591 +# CONFIG_PROVE_LOCKING is not set
6592 +# CONFIG_LOCK_STAT is not set
6593 +CONFIG_DEBUG_SPINLOCK_SLEEP=y
6594 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
6595 +# CONFIG_DEBUG_KOBJECT is not set
6596 +CONFIG_DEBUG_BUGVERBOSE=y
6597 +CONFIG_DEBUG_INFO=y
6598 +# CONFIG_DEBUG_VM is not set
6599 +# CONFIG_DEBUG_WRITECOUNT is not set
6600 +CONFIG_DEBUG_MEMORY_INIT=y
6601 +# CONFIG_DEBUG_LIST is not set
6602 +# CONFIG_DEBUG_SG is not set
6603 +CONFIG_FRAME_POINTER=y
6604 +# CONFIG_BOOT_PRINTK_DELAY is not set
6605 +# CONFIG_RCU_TORTURE_TEST is not set
6606 +# CONFIG_RCU_CPU_STALL_DETECTOR is not set
6607 +# CONFIG_BACKTRACE_SELF_TEST is not set
6608 +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
6609 +# CONFIG_FAULT_INJECTION is not set
6610 +# CONFIG_LATENCYTOP is not set
6611 +CONFIG_SYSCTL_SYSCALL_CHECK=y
6612 +CONFIG_HAVE_FUNCTION_TRACER=y
6613 +
6614 +#
6615 +# Tracers
6616 +#
6617 +# CONFIG_FUNCTION_TRACER is not set
6618 +# CONFIG_SCHED_TRACER is not set
6619 +# CONFIG_CONTEXT_SWITCH_TRACER is not set
6620 +# CONFIG_BOOT_TRACER is not set
6621 +# CONFIG_STACK_TRACER is not set
6622 +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
6623 +# CONFIG_SAMPLES is not set
6624 +CONFIG_HAVE_ARCH_KGDB=y
6625 +# CONFIG_KGDB is not set
6626 +CONFIG_DEBUG_USER=y
6627 +CONFIG_DEBUG_ERRORS=y
6628 +# CONFIG_DEBUG_STACK_USAGE is not set
6629 +CONFIG_DEBUG_LL=y
6630 +# CONFIG_DEBUG_ICEDCC is not set
6631 +CONFIG_DEBUG_S3C_PORT=y
6632 +CONFIG_DEBUG_S3C_UART=0
6633 +
6634 +#
6635 +# Security options
6636 +#
6637 +# CONFIG_KEYS is not set
6638 +# CONFIG_SECURITY is not set
6639 +# CONFIG_SECURITYFS is not set
6640 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
6641 +# CONFIG_CRYPTO is not set
6642 +
6643 +#
6644 +# Library routines
6645 +#
6646 +CONFIG_BITREVERSE=y
6647 +# CONFIG_CRC_CCITT is not set
6648 +# CONFIG_CRC16 is not set
6649 +# CONFIG_CRC_T10DIF is not set
6650 +# CONFIG_CRC_ITU_T is not set
6651 +CONFIG_CRC32=y
6652 +# CONFIG_CRC7 is not set
6653 +# CONFIG_LIBCRC32C is not set
6654 +CONFIG_ZLIB_INFLATE=y
6655 +CONFIG_PLIST=y
6656 +CONFIG_HAS_IOMEM=y
6657 +CONFIG_HAS_DMA=y
6658 --- a/arch/arm/Kconfig
6659 +++ b/arch/arm/Kconfig
6660 @@ -498,6 +498,13 @@ config ARCH_S3C2410
6661           BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
6662           the Samsung SMDK2410 development board (and derivatives).
6663
6664 +config ARCH_S3C64XX
6665 +       bool "Samsung S3C64XX"
6666 +       select GENERIC_GPIO
6667 +       select HAVE_CLK
6668 +       help
6669 +         Samsung S3C64XX series based systems
6670 +
6671  config ARCH_SHARK
6672         bool "Shark"
6673         select ISA
6674 @@ -590,6 +597,7 @@ source "arch/arm/mach-orion5x/Kconfig"
6675  source "arch/arm/mach-kirkwood/Kconfig"
6676
6677  source "arch/arm/plat-s3c24xx/Kconfig"
6678 +source "arch/arm/plat-s3c64xx/Kconfig"
6679  source "arch/arm/plat-s3c/Kconfig"
6680
6681  if ARCH_S3C2410
6682 @@ -601,6 +609,11 @@ source "arch/arm/mach-s3c2442/Kconfig"
6683  source "arch/arm/mach-s3c2443/Kconfig"
6684  endif
6685
6686 +if ARCH_S3C64XX
6687 +source "arch/arm/mach-s3c6400/Kconfig"
6688 +source "arch/arm/mach-s3c6410/Kconfig"
6689 +endif
6690 +
6691  source "arch/arm/mach-lh7a40x/Kconfig"
6692
6693  source "arch/arm/mach-imx/Kconfig"
6694 @@ -1256,6 +1269,8 @@ source "drivers/usb/Kconfig"
6695
6696  source "drivers/uwb/Kconfig"
6697
6698 +source "drivers/ar6000/Kconfig"
6699 +
6700  source "drivers/mmc/Kconfig"
6701
6702  source "drivers/memstick/Kconfig"
6703 @@ -1268,6 +1283,8 @@ source "drivers/rtc/Kconfig"
6704
6705  source "drivers/dma/Kconfig"
6706
6707 +source "drivers/android/Kconfig"
6708 +
6709  source "drivers/dca/Kconfig"
6710
6711  source "drivers/auxdisplay/Kconfig"
6712 --- a/arch/arm/kernel/vmlinux.lds.S
6713 +++ b/arch/arm/kernel/vmlinux.lds.S
6714 @@ -106,6 +106,8 @@ SECTIONS
6715                 *(.got)                 /* Global offset table          */
6716         }
6717
6718 +       NOTES
6719 +
6720         RODATA
6721
6722         _etext = .;                     /* End of text and rodata section */
6723 --- a/arch/arm/mach-s3c2410/clock.c
6724 +++ /dev/null
6725 @@ -1,276 +0,0 @@
6726 -/* linux/arch/arm/mach-s3c2410/clock.c
6727 - *
6728 - * Copyright (c) 2006 Simtec Electronics
6729 - *     Ben Dooks <ben@simtec.co.uk>
6730 - *
6731 - * S3C2410,S3C2440,S3C2442 Clock control support
6732 - *
6733 - * This program is free software; you can redistribute it and/or modify
6734 - * it under the terms of the GNU General Public License as published by
6735 - * the Free Software Foundation; either version 2 of the License, or
6736 - * (at your option) any later version.
6737 - *
6738 - * This program is distributed in the hope that it will be useful,
6739 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
6740 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6741 - * GNU General Public License for more details.
6742 - *
6743 - * You should have received a copy of the GNU General Public License
6744 - * along with this program; if not, write to the Free Software
6745 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6746 -*/
6747 -
6748 -#include <linux/init.h>
6749 -#include <linux/module.h>
6750 -#include <linux/kernel.h>
6751 -#include <linux/list.h>
6752 -#include <linux/errno.h>
6753 -#include <linux/err.h>
6754 -#include <linux/sysdev.h>
6755 -#include <linux/clk.h>
6756 -#include <linux/mutex.h>
6757 -#include <linux/delay.h>
6758 -#include <linux/serial_core.h>
6759 -#include <linux/io.h>
6760 -
6761 -#include <asm/mach/map.h>
6762 -
6763 -#include <mach/hardware.h>
6764 -
6765 -#include <plat/regs-serial.h>
6766 -#include <mach/regs-clock.h>
6767 -#include <mach/regs-gpio.h>
6768 -
6769 -#include <plat/s3c2410.h>
6770 -#include <plat/clock.h>
6771 -#include <plat/cpu.h>
6772 -
6773 -int s3c2410_clkcon_enable(struct clk *clk, int enable)
6774 -{
6775 -       unsigned int clocks = clk->ctrlbit;
6776 -       unsigned long clkcon;
6777 -
6778 -       clkcon = __raw_readl(S3C2410_CLKCON);
6779 -
6780 -       if (enable)
6781 -               clkcon |= clocks;
6782 -       else
6783 -               clkcon &= ~clocks;
6784 -
6785 -       /* ensure none of the special function bits set */
6786 -       clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
6787 -
6788 -       __raw_writel(clkcon, S3C2410_CLKCON);
6789 -
6790 -       return 0;
6791 -}
6792 -
6793 -static int s3c2410_upll_enable(struct clk *clk, int enable)
6794 -{
6795 -       unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
6796 -       unsigned long orig = clkslow;
6797 -
6798 -       if (enable)
6799 -               clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
6800 -       else
6801 -               clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
6802 -
6803 -       __raw_writel(clkslow, S3C2410_CLKSLOW);
6804 -
6805 -       /* if we started the UPLL, then allow to settle */
6806 -
6807 -       if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
6808 -               udelay(200);
6809 -
6810 -       return 0;
6811 -}
6812 -
6813 -/* standard clock definitions */
6814 -
6815 -static struct clk init_clocks_disable[] = {
6816 -       {
6817 -               .name           = "nand",
6818 -               .id             = -1,
6819 -               .parent         = &clk_h,
6820 -               .enable         = s3c2410_clkcon_enable,
6821 -               .ctrlbit        = S3C2410_CLKCON_NAND,
6822 -       }, {
6823 -               .name           = "sdi",
6824 -               .id             = -1,
6825 -               .parent         = &clk_p,
6826 -               .enable         = s3c2410_clkcon_enable,
6827 -               .ctrlbit        = S3C2410_CLKCON_SDI,
6828 -       }, {
6829 -               .name           = "adc",
6830 -               .id             = -1,
6831 -               .parent         = &clk_p,
6832 -               .enable         = s3c2410_clkcon_enable,
6833 -               .ctrlbit        = S3C2410_CLKCON_ADC,
6834 -       }, {
6835 -               .name           = "i2c",
6836 -               .id             = -1,
6837 -               .parent         = &clk_p,
6838 -               .enable         = s3c2410_clkcon_enable,
6839 -               .ctrlbit        = S3C2410_CLKCON_IIC,
6840 -       }, {
6841 -               .name           = "iis",
6842 -               .id             = -1,
6843 -               .parent         = &clk_p,
6844 -               .enable         = s3c2410_clkcon_enable,
6845 -               .ctrlbit        = S3C2410_CLKCON_IIS,
6846 -       }, {
6847 -               .name           = "spi",
6848 -               .id             = -1,
6849 -               .parent         = &clk_p,
6850 -               .enable         = s3c2410_clkcon_enable,
6851 -               .ctrlbit        = S3C2410_CLKCON_SPI,
6852 -       }
6853 -};
6854 -
6855 -static struct clk init_clocks[] = {
6856 -       {
6857 -               .name           = "lcd",
6858 -               .id             = -1,
6859 -               .parent         = &clk_h,
6860 -               .enable         = s3c2410_clkcon_enable,
6861 -               .ctrlbit        = S3C2410_CLKCON_LCDC,
6862 -       }, {
6863 -               .name           = "gpio",
6864 -               .id             = -1,
6865 -               .parent         = &clk_p,
6866 -               .enable         = s3c2410_clkcon_enable,
6867 -               .ctrlbit        = S3C2410_CLKCON_GPIO,
6868 -       }, {
6869 -               .name           = "usb-host",
6870 -               .id             = -1,
6871 -               .parent         = &clk_h,
6872 -               .enable         = s3c2410_clkcon_enable,
6873 -               .ctrlbit        = S3C2410_CLKCON_USBH,
6874 -       }, {
6875 -               .name           = "usb-device",
6876 -               .id             = -1,
6877 -               .parent         = &clk_h,
6878 -               .enable         = s3c2410_clkcon_enable,
6879 -               .ctrlbit        = S3C2410_CLKCON_USBD,
6880 -       }, {
6881 -               .name           = "timers",
6882 -               .id             = -1,
6883 -               .parent         = &clk_p,
6884 -               .enable         = s3c2410_clkcon_enable,
6885 -               .ctrlbit        = S3C2410_CLKCON_PWMT,
6886 -       }, {
6887 -               .name           = "uart",
6888 -               .id             = 0,
6889 -               .parent         = &clk_p,
6890 -               .enable         = s3c2410_clkcon_enable,
6891 -               .ctrlbit        = S3C2410_CLKCON_UART0,
6892 -       }, {
6893 -               .name           = "uart",
6894 -               .id             = 1,
6895 -               .parent         = &clk_p,
6896 -               .enable         = s3c2410_clkcon_enable,
6897 -               .ctrlbit        = S3C2410_CLKCON_UART1,
6898 -       }, {
6899 -               .name           = "uart",
6900 -               .id             = 2,
6901 -               .parent         = &clk_p,
6902 -               .enable         = s3c2410_clkcon_enable,
6903 -               .ctrlbit        = S3C2410_CLKCON_UART2,
6904 -       }, {
6905 -               .name           = "rtc",
6906 -               .id             = -1,
6907 -               .parent         = &clk_p,
6908 -               .enable         = s3c2410_clkcon_enable,
6909 -               .ctrlbit        = S3C2410_CLKCON_RTC,
6910 -       }, {
6911 -               .name           = "watchdog",
6912 -               .id             = -1,
6913 -               .parent         = &clk_p,
6914 -               .ctrlbit        = 0,
6915 -       }, {
6916 -               .name           = "usb-bus-host",
6917 -               .id             = -1,
6918 -               .parent         = &clk_usb_bus,
6919 -       }, {
6920 -               .name           = "usb-bus-gadget",
6921 -               .id             = -1,
6922 -               .parent         = &clk_usb_bus,
6923 -       },
6924 -};
6925 -
6926 -/* s3c2410_baseclk_add()
6927 - *
6928 - * Add all the clocks used by the s3c2410 or compatible CPUs
6929 - * such as the S3C2440 and S3C2442.
6930 - *
6931 - * We cannot use a system device as we are needed before any
6932 - * of the init-calls that initialise the devices are actually
6933 - * done.
6934 -*/
6935 -
6936 -int __init s3c2410_baseclk_add(void)
6937 -{
6938 -       unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
6939 -       unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
6940 -       struct clk *clkp;
6941 -       struct clk *xtal;
6942 -       int ret;
6943 -       int ptr;
6944 -
6945 -       clk_upll.enable = s3c2410_upll_enable;
6946 -
6947 -       if (s3c24xx_register_clock(&clk_usb_bus) < 0)
6948 -               printk(KERN_ERR "failed to register usb bus clock\n");
6949 -
6950 -       /* register clocks from clock array */
6951 -
6952 -       clkp = init_clocks;
6953 -       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
6954 -               /* ensure that we note the clock state */
6955 -
6956 -               clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
6957 -
6958 -               ret = s3c24xx_register_clock(clkp);
6959 -               if (ret < 0) {
6960 -                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
6961 -                              clkp->name, ret);
6962 -               }
6963 -       }
6964 -
6965 -       /* We must be careful disabling the clocks we are not intending to
6966 -        * be using at boot time, as subsystems such as the LCD which do
6967 -        * their own DMA requests to the bus can cause the system to lockup
6968 -        * if they where in the middle of requesting bus access.
6969 -        *
6970 -        * Disabling the LCD clock if the LCD is active is very dangerous,
6971 -        * and therefore the bootloader should be careful to not enable
6972 -        * the LCD clock if it is not needed.
6973 -       */
6974 -
6975 -       /* install (and disable) the clocks we do not need immediately */
6976 -
6977 -       clkp = init_clocks_disable;
6978 -       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
6979 -
6980 -               ret = s3c24xx_register_clock(clkp);
6981 -               if (ret < 0) {
6982 -                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
6983 -                              clkp->name, ret);
6984 -               }
6985 -
6986 -               s3c2410_clkcon_enable(clkp, 0);
6987 -       }
6988 -
6989 -       /* show the clock-slow value */
6990 -
6991 -       xtal = clk_get(NULL, "xtal");
6992 -
6993 -       printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
6994 -              print_mhz(clk_get_rate(xtal) /
6995 -                        ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
6996 -              (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
6997 -              (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
6998 -              (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
6999 -
7000 -       return 0;
7001 -}
7002 --- a/arch/arm/mach-s3c2410/dma.c
7003 +++ b/arch/arm/mach-s3c2410/dma.c
7004 @@ -25,12 +25,12 @@
7005
7006  #include <plat/regs-serial.h>
7007  #include <mach/regs-gpio.h>
7008 -#include <asm/plat-s3c/regs-ac97.h>
7009 +#include <plat/regs-ac97.h>
7010  #include <mach/regs-mem.h>
7011  #include <mach/regs-lcd.h>
7012  #include <mach/regs-sdi.h>
7013  #include <asm/plat-s3c24xx/regs-iis.h>
7014 -#include <asm/plat-s3c24xx/regs-spi.h>
7015 +#include <plat/regs-spi.h>
7016
7017  static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
7018         [DMACH_XD0] = {
7019 --- /dev/null
7020 +++ b/arch/arm/mach-s3c2410/include/mach/fiq_ipc_gta02.h
7021 @@ -0,0 +1,60 @@
7022 +#ifndef _LINUX_FIQ_IPC_H
7023 +#define _LINUX_FIQ_IPC_H
7024 +
7025 +/*
7026 + * this defines the struct which is used to communicate between the FIQ
7027 + * world and the normal linux kernel world.  One of these structs is
7028 + * statically defined for you in the monolithic kernel so the FIQ ISR code
7029 + * can safely touch it any any time.
7030 + *
7031 + * You also want to include this file in your kernel module that wants to
7032 + * communicate with your FIQ code.  Add any kinds of vars that are used by
7033 + * the FIQ ISR and the module in here.
7034 + *
7035 + * To get you started there is just an int that is incremented every FIQ
7036 + * you can remove this when you are ready to customize, but it is useful
7037 + * for testing
7038 + */
7039 +
7040 +#include <mach/pwm.h>
7041 +#include <plat/regs-timer.h>
7042 +
7043 +extern u8 fiq_ready;
7044 +
7045 +enum hdq_bitbang_states {
7046 +       HDQB_IDLE = 0,
7047 +       HDQB_TX_BREAK,
7048 +       HDQB_TX_BREAK_RECOVERY,
7049 +       HDQB_ADS_CALC,
7050 +       HDQB_ADS_LOW,
7051 +       HDQB_ADS_HIGH,
7052 +       HDQB_WAIT_RX,
7053 +       HDQB_DATA_RX_LOW,
7054 +       HDQB_DATA_RX_HIGH,
7055 +       HDQB_WAIT_TX,
7056 +};
7057 +
7058 +struct fiq_ipc {
7059 +       /* vibrator */
7060 +       unsigned long vib_gpio_pin; /* which pin to meddle with */
7061 +       u8 vib_pwm; /* 0 = OFF -- will ensure GPIO deasserted and stop FIQ */
7062 +       u8 vib_pwm_latched;
7063 +
7064 +       /* hdq */
7065 +       u8 hdq_probed; /* nonzero after HDQ driver probed */
7066 +       struct mutex hdq_lock; /* if you want to use hdq, you have to take lock */
7067 +       unsigned long hdq_gpio_pin; /* GTA02 = GPD14 which pin to meddle with */
7068 +       u8 hdq_ads; /* b7..b6 = register address, b0 = r/w */
7069 +       u8 hdq_tx_data; /* data to tx for write action */
7070 +       u8 hdq_rx_data; /* data received in read action */
7071 +       u8 hdq_request_ctr; /* incremented by "user" to request a transfer */
7072 +       u8 hdq_transaction_ctr; /* incremented after each transfer */
7073 +       u8 hdq_error; /* 0 = no error */
7074 +};
7075 +
7076 +/* actual definition lives in arch/arm/mach-s3c2440/fiq_c_isr.c */
7077 +extern struct fiq_ipc fiq_ipc;
7078 +extern unsigned long _fiq_count_fiqs;
7079 +extern void fiq_kick(void);  /* provoke a FIQ "immediately" */
7080 +
7081 +#endif /* _LINUX_FIQ_IPC_H */
7082 --- /dev/null
7083 +++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
7084 @@ -0,0 +1,21 @@
7085 +/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
7086 + *
7087 + * Copyright 2008 Openmoko, Inc.
7088 + * Copyright 2008 Simtec Electronics
7089 + *      Ben Dooks <ben@simtec.co.uk>
7090 + *      http://armlinux.simtec.co.uk/
7091 + *
7092 + * S3C2410 - GPIO core support
7093 + *
7094 + * This program is free software; you can redistribute it and/or modify
7095 + * it under the terms of the GNU General Public License version 2 as
7096 + * published by the Free Software Foundation.
7097 +*/
7098 +
7099 +#ifndef __ASM_ARCH_GPIO_CORE_H
7100 +#define __ASM_ARCH_GPIO_CORE_H __FILE__
7101 +
7102 +/* currently we just include the platform support */
7103 +#include <plat/gpio-core.h>
7104 +
7105 +#endif /* __ASM_ARCH_GPIO_CORE_H */
7106 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h
7107 +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
7108 @@ -15,4 +15,14 @@
7109  #define gpio_set_value __gpio_set_value
7110  #define gpio_cansleep  __gpio_cansleep
7111
7112 +/* These two defines should be removed as soon as the
7113 + * generic irq handling makes it upstream */
7114 +#include <mach/hardware.h>
7115 +#define gpio_to_irq(gpio)               s3c2410_gpio_getirq(gpio)
7116 +#define irq_to_gpio(irq)                s3c2410_gpio_irq2pin(irq)
7117 +/* -- cut to here when generic irq makes it */
7118 +
7119  #include <asm-generic/gpio.h>
7120 +#include <mach/gpio-nrs.h>
7121 +
7122 +#define S3C_GPIO_END   (S3C2410_GPIO_BANKH + 32)
7123 --- /dev/null
7124 +++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
7125 @@ -0,0 +1,23 @@
7126 +/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
7127 + *
7128 + * Copyright (c) 2008 Simtec Electronics
7129 + *     http://armlinux.simtec.co.uk/
7130 + *     Ben Dooks <ben@simtec.co.uk>
7131 + *
7132 + * S3C2410 - GPIO bank numbering
7133 + *
7134 + * This program is free software; you can redistribute it and/or modify
7135 + * it under the terms of the GNU General Public License version 2 as
7136 + * published by the Free Software Foundation.
7137 +*/
7138 +
7139 +#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
7140 +
7141 +#define S3C2410_GPIO_BANKA   (32*0)
7142 +#define S3C2410_GPIO_BANKB   (32*1)
7143 +#define S3C2410_GPIO_BANKC   (32*2)
7144 +#define S3C2410_GPIO_BANKD   (32*3)
7145 +#define S3C2410_GPIO_BANKE   (32*4)
7146 +#define S3C2410_GPIO_BANKF   (32*5)
7147 +#define S3C2410_GPIO_BANKG   (32*6)
7148 +#define S3C2410_GPIO_BANKH   (32*7)
7149 --- /dev/null
7150 +++ b/arch/arm/mach-s3c2410/include/mach/gta01.h
7151 @@ -0,0 +1,74 @@
7152 +#ifndef _GTA01_H
7153 +#define _GTA01_H
7154 +
7155 +#include <mach/regs-gpio.h>
7156 +#include <mach/irqs.h>
7157 +
7158 +/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
7159 +#define GTA01v3_SYSTEM_REV     0x00000130
7160 +#define GTA01v4_SYSTEM_REV     0x00000140
7161 +#define GTA01Bv2_SYSTEM_REV    0x00000220
7162 +#define GTA01Bv3_SYSTEM_REV    0x00000230
7163 +#define GTA01Bv4_SYSTEM_REV    0x00000240
7164 +
7165 +/* Backlight */
7166 +
7167 +extern void gta01bl_deferred_resume(void);
7168 +
7169 +struct gta01bl_machinfo {
7170 +       unsigned int default_intensity;
7171 +       unsigned int max_intensity;
7172 +       unsigned int limit_mask;
7173 +       unsigned int defer_resume_backlight;
7174 +};
7175 +
7176 +/* Definitions common to all revisions */
7177 +#define GTA01_GPIO_BACKLIGHT   S3C2410_GPB0
7178 +#define GTA01_GPIO_GPS_PWRON   S3C2410_GPB1
7179 +#define GTA01_GPIO_MODEM_RST   S3C2410_GPB6
7180 +#define GTA01_GPIO_MODEM_ON    S3C2410_GPB7
7181 +#define GTA01_GPIO_LCD_RESET   S3C2410_GPC6
7182 +#define GTA01_GPIO_PMU_IRQ     S3C2410_GPG8
7183 +#define GTA01_GPIO_JACK_INSERT S3C2410_GPF4
7184 +#define GTA01_GPIO_nSD_DETECT  S3C2410_GPF5
7185 +#define GTA01_GPIO_AUX_KEY     S3C2410_GPF6
7186 +#define GTA01_GPIO_HOLD_KEY    S3C2410_GPF7
7187 +#define GTA01_GPIO_VIBRATOR_ON S3C2410_GPG11
7188 +
7189 +#define GTA01_IRQ_MODEM                IRQ_EINT1
7190 +#define GTA01_IRQ_JACK_INSERT  IRQ_EINT4
7191 +#define GTA01_IRQ_nSD_DETECT   IRQ_EINT5
7192 +#define GTA01_IRQ_AUX_KEY      IRQ_EINT6
7193 +#define GTA01_IRQ_PCF50606      IRQ_EINT16
7194 +
7195 +/* GTA01v3 */
7196 +#define GTA01v3_GPIO_nGSM_EN   S3C2410_GPG9
7197 +
7198 +/* GTA01v4 */
7199 +#define GTA01_GPIO_MODEM_DNLOAD        S3C2410_GPG0
7200 +
7201 +/* GTA01Bv2 */
7202 +#define GTA01Bv2_GPIO_nGSM_EN  S3C2410_GPF2
7203 +#define GTA01Bv2_GPIO_VIBRATOR_ON S3C2410_GPB10
7204 +
7205 +/* GTA01Bv3 */
7206 +#define GTA01_GPIO_GPS_EN_3V3  S3C2410_GPG9
7207 +
7208 +#define GTA01_GPIO_SDMMC_ON    S3C2410_GPB2
7209 +#define GTA01_GPIO_BT_EN       S3C2410_GPB5
7210 +#define GTA01_GPIO_AB_DETECT   S3C2410_GPB8
7211 +#define GTA01_GPIO_USB_PULLUP  S3C2410_GPB9
7212 +#define GTA01_GPIO_USB_ATTACH  S3C2410_GPB10
7213 +
7214 +#define GTA01_GPIO_GPS_EN_2V8  S3C2410_GPG9
7215 +#define GTA01_GPIO_GPS_EN_3V   S3C2410_GPG10
7216 +#define GTA01_GPIO_GPS_RESET   S3C2410_GPC0
7217 +
7218 +/* GTA01Bv4 */
7219 +#define GTA01Bv4_GPIO_nNAND_WP S3C2410_GPA16
7220 +#define GTA01Bv4_GPIO_VIBRATOR_ON S3C2410_GPB3
7221 +#define GTA01Bv4_GPIO_PMU_IRQ  S3C2410_GPG1
7222 +
7223 +#define GTA01Bv4_IRQ_PCF50606  IRQ_EINT9
7224 +
7225 +#endif /* _GTA01_H */
7226 --- /dev/null
7227 +++ b/arch/arm/mach-s3c2410/include/mach/gta02.h
7228 @@ -0,0 +1,113 @@
7229 +#ifndef _GTA02_H
7230 +#define _GTA02_H
7231 +
7232 +#include <mach/regs-gpio.h>
7233 +#include <mach/irqs.h>
7234 +
7235 +#include <linux/mfd/pcf50633/core.h>
7236 +
7237 +/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
7238 +#define GTA02v1_SYSTEM_REV     0x00000310
7239 +#define GTA02v2_SYSTEM_REV     0x00000320
7240 +#define GTA02v3_SYSTEM_REV     0x00000330
7241 +#define GTA02v4_SYSTEM_REV     0x00000340
7242 +#define GTA02v5_SYSTEM_REV     0x00000350
7243 +#define GTA02v6_SYSTEM_REV     0x00000360
7244 +
7245 +#define GTA02_GPIO_n3DL_GSM    S3C2410_GPA13   /* v1 + v2 + v3 only */
7246 +
7247 +#define GTA02_GPIO_PWR_LED1    S3C2410_GPB0
7248 +#define GTA02_GPIO_PWR_LED2    S3C2410_GPB1
7249 +#define GTA02_GPIO_AUX_LED     S3C2410_GPB2
7250 +#define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB3
7251 +#define GTA02v1_GPIO_GPS_PWRON S3C2410_GPB4    /* v1 only */
7252 +#define GTA02_GPIO_MODEM_RST   S3C2410_GPB5
7253 +#define GTA02_GPIO_BT_EN       S3C2410_GPB6
7254 +#define GTA02_GPIO_MODEM_ON    S3C2410_GPB7
7255 +#define GTA02v1_GPIO_EN_AGPS3V S3C2410_GPB8    /* v1 only */
7256 +#define GTA02_GPIO_EXTINT8     S3C2410_GPB8
7257 +#define GTA02_GPIO_USB_PULLUP  S3C2410_GPB9
7258 +
7259 +#define GTA02v1_GPIO_nGPS_RST  S3C2410_GPC0    /* v1 only */
7260 +#define GTA02v12_GPIO_PIO3     S3C2410_GPC5    /* v1 + v2 only */
7261 +#define GTA02_GPIO_PIO5                S3C2410_GPC5    /* v3 + v4 only */
7262 +#define GTA02_GPIO_LCD_RESET   S3C2410_GPC6    /* v1 + v2 only */
7263 +#define GTA02v12_GPIO_PIO2     S3C2410_GPC7    /* v1 + v2 only */
7264 +#define GTA02v2_nUSB_FLT       S3C2410_GPC9    /* v2 only */
7265 +#define GTA02v2_nUSB_OC                S3C2410_GPC10   /* v2 only */
7266 +#define GTA02v2_nGSM_OC                S3C2410_GPC12   /* v2 only */
7267 +
7268 +#define GTA02v3_GPIO_nG1_CS    S3C2410_GPD12   /* v3 + v4 only */
7269 +#define GTA02v3_GPIO_nG2_CS    S3C2410_GPD13   /* v3 + v4 only */
7270 +#define GTA02v5_GPIO_HDQ       S3C2410_GPD14   /* v5 + */
7271 +
7272 +#define GTA02_GPIO_nG1_INT     S3C2410_GPF0
7273 +#define GTA02_GPIO_IO1         S3C2410_GPF1
7274 +#define GTA02v1_GPIO_nG2_INT   S3C2410_GPF2    /* v1 only */
7275 +#define GTA02_GPIO_PIO_2       S3C2410_GPF2    /* v2 + v3 + v4 only */
7276 +#define GTA02_GPIO_JACK_INSERT S3C2410_GPF4
7277 +#define GTA02v1_GPIO_nSD_DETECT        S3C2410_GPF5    /* v1 only */
7278 +#define GTA02_GPIO_WLAN_GPIO1  S3C2410_GPF5    /* v2 + v3 + v4 only */
7279 +#define GTA02_GPIO_AUX_KEY     S3C2410_GPF6
7280 +#define GTA02_GPIO_HOLD_KEY    S3C2410_GPF7
7281 +
7282 +#define GTA02_GPIO_3D_IRQ      S3C2410_GPG4
7283 +#define GTA02v1_GPIO_nG1_CS    S3C2410_GPG8    /* v1 only */
7284 +#define GTA02v2_GPIO_nG2_INT   S3C2410_GPG8    /* v2 + v3 + v4 only */
7285 +#define GTA02v3_GPIO_nUSB_OC   S3C2410_GPG9    /* v3 + v4 only */
7286 +#define GTA02v3_GPIO_nUSB_FLT  S3C2410_GPG10   /* v3 + v4 only */
7287 +#define GTA02v1_GPIO_nG2_CS    S3C2410_GPG11   /* v1 only */
7288 +#define GTA02v3_GPIO_nGSM_OC   S3C2410_GPG11   /* v3 + v4 only */
7289 +
7290 +#define GTA02v1_GPIO_3D_RESET  S3C2440_GPJ0    /* v1 only */
7291 +#define GTA02v2_GPIO_BAT_ID    S3C2440_GPJ0    /* v2 only */
7292 +#define GTA02v1_GPIO_WLAN_GPIO8        S3C2440_GPJ1    /* v1 only */
7293 +#define GTA02_GPIO_AMP_SHUT    S3C2440_GPJ1    /* v2 + v3 + v4 only */
7294 +#define GTA02v1_GPIO_WLAN_GPIO10       S3C2440_GPJ2
7295 +#define GTA02_GPIO_HP_IN       S3C2440_GPJ2    /* v2 + v3 + v4 only */
7296 +#define GTA02v1_GPIO_KEEPACT   S3C2440_GPJ3    /* v1 only */
7297 +#define GTA02_GPIO_INT0                S3C2440_GPJ3    /* v2 + v3 + v4 only */
7298 +#define GTA02_GPIO_nGSM_EN     S3C2440_GPJ4
7299 +#define GTA02_GPIO_3D_RESET    S3C2440_GPJ5
7300 +#define GTA02_GPIO_nDL_GSM     S3C2440_GPJ6    /* v4 + v5 only */
7301 +#define GTA02_GPIO_WLAN_GPIO0  S3C2440_GPJ7
7302 +#define GTA02v1_GPIO_BAT_ID    S3C2440_GPJ8
7303 +#define GTA02_GPIO_KEEPACT     S3C2440_GPJ8
7304 +#define GTA02v1_GPIO_AMP_SHUT  S3C2440_GPJ9    /* v1 only */
7305 +#define GTA02v2_nG1_CS         S3C2440_GPJ9    /* v2 only */
7306 +#define GTA02v1_GPIO_HP_IN     S3C2440_GPJ10
7307 +#define GTA02v2_nG2_CS         S3C2440_GPJ10   /* v2 only */
7308 +#define GTA02v1_GPIO_INT0      S3C2440_GPJ11   /* v1 only */
7309 +#define GTA02_CHIP_PWD         S3C2440_GPJ11   /* v2 + v3 + v4 only */
7310 +#define GTA02v1_GPIO_nGSM_EN   S3C2440_GPJ12   /* v1 only */
7311 +#define GTA02_GPIO_nWLAN_RESET S3C2440_GPJ12   /* v2 + v3 + v4 only */
7312 +
7313 +#define GTA02_IRQ_GSENSOR_1    IRQ_EINT0
7314 +#define GTA02_IRQ_MODEM                IRQ_EINT1
7315 +#define GTA02v1_IRQ_GSENSOR_2  IRQ_EINT2       /* v1 only */
7316 +#define GTA02_IRQ_PIO_2                IRQ_EINT2       /* v2 + v3 + v4 only */
7317 +#define GTA02_IRQ_nJACK_INSERT IRQ_EINT4
7318 +#define GTA02v1_IRQ_nSD_CD     IRQ_EINT5       /* v1 only */
7319 +#define GTA02_IRQ_WLAN_GPIO1   IRQ_EINT5
7320 +#define GTA02_IRQ_AUX          IRQ_EINT6
7321 +#define GTA02_IRQ_nHOLD                IRQ_EINT7
7322 +#define GTA02v1_IRQ_nSIM_CD    IRQ_EINT8       /* v1 only */
7323 +#define GTA02_IRQ_PCF50633     IRQ_EINT9
7324 +#define GTA02_IRQ_3D           IRQ_EINT12
7325 +#define GTA02_IRQ_GSENSOR_2    IRQ_EINT16      /* v2 + v3 + v4 only */
7326 +#define GTA02v3_IRQ_nUSB_OC    IRQ_EINT17      /* v3 + v4 only */
7327 +#define GTA02v3_IRQ_nUSB_FLT   IRQ_EINT18      /* v3 + v4 only */
7328 +#define GTA02v3_IRQ_nGSM_OC    IRQ_EINT19      /* v3 + v4 only */
7329 +
7330 +/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */
7331 +#define GTA02_PCB_ID1_0                S3C2410_GPC13
7332 +#define GTA02_PCB_ID1_1                S3C2410_GPC15
7333 +#define GTA02_PCB_ID1_2                S3C2410_GPD0
7334 +#define GTA02_PCB_ID2_0                S3C2410_GPD3
7335 +#define GTA02_PCB_ID2_1                S3C2410_GPD4
7336 +
7337 +int gta02_get_pcb_revision(void);
7338 +
7339 +extern struct pcf50633_platform_data gta02_pcf_pdata;
7340 +
7341 +#endif /* _GTA02_H */
7342 --- /dev/null
7343 +++ b/arch/arm/mach-s3c2410/include/mach/gta02-pm-wlan.h
7344 @@ -0,0 +1 @@
7345 +void gta02_wlan_power(int on);
7346 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h
7347 +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
7348 @@ -12,9 +12,9 @@
7349  #ifndef __ASM_ARCH_IRQS_H
7350  #define __ASM_ARCH_IRQS_H __FILE__
7351
7352 -#ifndef __ASM_ARM_IRQ_H
7353 -#error "Do not include this directly, instead #include <asm/irq.h>"
7354 -#endif
7355 +//#ifndef __ASM_ARM_IRQ_H
7356 +//#error "Do not include this directly, instead #include <asm/irq.h>"
7357 +//#endif
7358
7359  /* we keep the first set of CPU IRQs out of the range of
7360   * the ISA space, so that the PC104 has them to itself
7361 @@ -84,7 +84,7 @@
7362  #define IRQ_EINT22     S3C2410_IRQ(50)
7363  #define IRQ_EINT23     S3C2410_IRQ(51)
7364
7365 -
7366 +#define IRQ_EINT_BIT(x)        ((x) - IRQ_EINT4 + 4)
7367  #define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
7368
7369  #define IRQ_LCD_FIFO   S3C2410_IRQ(52)
7370 @@ -134,6 +134,8 @@
7371  #define IRQ_S3C2443_HSMMC      S3C2410_IRQ(20)         /* IRQ_SDI */
7372  #define IRQ_S3C2443_NAND       S3C2410_IRQ(24)         /* reserved */
7373
7374 +#define IRQ_HSMMC0             IRQ_S3C2443_HSMMC
7375 +
7376  #define IRQ_S3C2443_LCD1       S3C2410_IRQSUB(14)
7377  #define IRQ_S3C2443_LCD2       S3C2410_IRQSUB(15)
7378  #define IRQ_S3C2443_LCD3       S3C2410_IRQSUB(16)
7379 @@ -155,12 +157,47 @@
7380  #define IRQ_S3C2443_AC97       S3C2410_IRQSUB(28)
7381
7382  #ifdef CONFIG_CPU_S3C2443
7383 -#define NR_IRQS (IRQ_S3C2443_AC97+1)
7384 +#define _NR_IRQS (IRQ_S3C2443_AC97+1)
7385  #else
7386 -#define NR_IRQS (IRQ_S3C2440_AC97+1)
7387 +#define _NR_IRQS (IRQ_S3C2440_AC97+1)
7388  #endif
7389
7390 +/* compatibility define. */
7391 +#define IRQ_UART3              IRQ_S3C2443_UART3
7392 +#define IRQ_S3CUART_RX3                IRQ_S3C2443_RX3
7393 +#define IRQ_S3CUART_TX3                IRQ_S3C2443_TX3
7394 +#define IRQ_S3CUART_ERR3       IRQ_S3C2443_ERR3
7395 +
7396  /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
7397  #define FIQ_START              IRQ_EINT0
7398
7399 +
7400 +/*
7401 + * The next 16 interrupts are for board specific purposes.  Since
7402 + * the kernel can only run on one machine at a time, we can re-use
7403 + * these.  If you need more, increase IRQ_BOARD_END, but keep it
7404 + * within sensible limits.
7405 + */
7406 +#define IRQ_BOARD_START         _NR_IRQS
7407 +#define IRQ_BOARD_END           (_NR_IRQS + 10)
7408 +
7409 +#if defined(CONFIG_MACH_NEO1973_GTA02)
7410 +#define NR_IRQS                 (IRQ_BOARD_END)
7411 +#else
7412 +#define NR_IRQS                 (IRQ_BOARD_START)
7413 +#endif
7414 +
7415 +/* Neo1973 GTA02 interrupts */
7416 +#define NEO1973_GTA02_IRQ(x)    (IRQ_BOARD_START + (x))
7417 +#define IRQ_GLAMO(x)            NEO1973_GTA02_IRQ(x)
7418 +#define IRQ_GLAMO_HOSTBUS       IRQ_GLAMO(0)
7419 +#define IRQ_GLAMO_JPEG          IRQ_GLAMO(1)
7420 +#define IRQ_GLAMO_MPEG          IRQ_GLAMO(2)
7421 +#define IRQ_GLAMO_MPROC1        IRQ_GLAMO(3)
7422 +#define IRQ_GLAMO_MPROC0        IRQ_GLAMO(4)
7423 +#define IRQ_GLAMO_CMDQUEUE      IRQ_GLAMO(5)
7424 +#define IRQ_GLAMO_2D            IRQ_GLAMO(6)
7425 +#define IRQ_GLAMO_MMC           IRQ_GLAMO(7)
7426 +#define IRQ_GLAMO_RISC          IRQ_GLAMO(8)
7427 +
7428  #endif /* __ASM_ARCH_IRQ_H */
7429 --- a/arch/arm/mach-s3c2410/include/mach/map.h
7430 +++ b/arch/arm/mach-s3c2410/include/mach/map.h
7431 @@ -13,34 +13,20 @@
7432  #ifndef __ASM_ARCH_MAP_H
7433  #define __ASM_ARCH_MAP_H
7434
7435 +#include <plat/map-base.h>
7436  #include <plat/map.h>
7437
7438  #define S3C2410_ADDR(x)                S3C_ADDR(x)
7439
7440 -/* interrupt controller is the first thing we put in, to make
7441 - * the assembly code for the irq detection easier
7442 - */
7443 -#define S3C24XX_VA_IRQ    S3C_VA_IRQ
7444 -#define S3C2410_PA_IRQ    (0x4A000000)
7445 -#define S3C24XX_SZ_IRQ    SZ_1M
7446 -
7447 -/* memory controller registers */
7448 -#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
7449 -#define S3C2410_PA_MEMCTRL (0x48000000)
7450 -#define S3C24XX_SZ_MEMCTRL SZ_1M
7451 -
7452  /* USB host controller */
7453  #define S3C2410_PA_USBHOST (0x49000000)
7454 -#define S3C24XX_SZ_USBHOST SZ_1M
7455
7456  /* DMA controller */
7457  #define S3C2410_PA_DMA    (0x4B000000)
7458  #define S3C24XX_SZ_DMA    SZ_1M
7459
7460  /* Clock and Power management */
7461 -#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
7462  #define S3C2410_PA_CLKPWR  (0x4C000000)
7463 -#define S3C24XX_SZ_CLKPWR  SZ_1M
7464
7465  /* LCD controller */
7466  #define S3C2410_PA_LCD    (0x4D000000)
7467 @@ -48,48 +34,12 @@
7468
7469  /* NAND flash controller */
7470  #define S3C2410_PA_NAND           (0x4E000000)
7471 -#define S3C24XX_SZ_NAND           SZ_1M
7472 -
7473 -/* UARTs */
7474 -#define S3C24XX_VA_UART           S3C_VA_UART
7475 -#define S3C2410_PA_UART           (0x50000000)
7476 -#define S3C24XX_SZ_UART           SZ_1M
7477 -
7478 -/* Timers */
7479 -#define S3C24XX_VA_TIMER   S3C_VA_TIMER
7480 -#define S3C2410_PA_TIMER   (0x51000000)
7481 -#define S3C24XX_SZ_TIMER   SZ_1M
7482 -
7483 -/* USB Device port */
7484 -#define S3C2410_PA_USBDEV  (0x52000000)
7485 -#define S3C24XX_SZ_USBDEV  SZ_1M
7486 -
7487 -/* Watchdog */
7488 -#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
7489 -#define S3C2410_PA_WATCHDOG (0x53000000)
7490 -#define S3C24XX_SZ_WATCHDOG SZ_1M
7491
7492  /* IIC hardware controller */
7493  #define S3C2410_PA_IIC    (0x54000000)
7494 -#define S3C24XX_SZ_IIC    SZ_1M
7495
7496  /* IIS controller */
7497  #define S3C2410_PA_IIS    (0x55000000)
7498 -#define S3C24XX_SZ_IIS    SZ_1M
7499 -
7500 -/* GPIO ports */
7501 -
7502 -/* the calculation for the VA of this must ensure that
7503 - * it is the same distance apart from the UART in the
7504 - * phsyical address space, as the initial mapping for the IO
7505 - * is done as a 1:1 maping. This puts it (currently) at
7506 - * 0xFA800000, which is not in the way of any current mapping
7507 - * by the base system.
7508 -*/
7509 -
7510 -#define S3C2410_PA_GPIO           (0x56000000)
7511 -#define S3C24XX_VA_GPIO           ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
7512 -#define S3C24XX_SZ_GPIO           SZ_1M
7513
7514  /* RTC */
7515  #define S3C2410_PA_RTC    (0x57000000)
7516 @@ -97,15 +47,12 @@
7517
7518  /* ADC */
7519  #define S3C2410_PA_ADC    (0x58000000)
7520 -#define S3C24XX_SZ_ADC    SZ_1M
7521
7522  /* SPI */
7523  #define S3C2410_PA_SPI    (0x59000000)
7524 -#define S3C24XX_SZ_SPI    SZ_1M
7525
7526  /* SDI */
7527  #define S3C2410_PA_SDI    (0x5A000000)
7528 -#define S3C24XX_SZ_SDI    SZ_1M
7529
7530  /* CAMIF */
7531  #define S3C2440_PA_CAMIF   (0x4F000000)
7532 @@ -120,13 +67,6 @@
7533  #define S3C2443_PA_HSMMC   (0x4A800000)
7534  #define S3C2443_SZ_HSMMC   (256)
7535
7536 -/* ISA style IO, for each machine to sort out mappings for, if it
7537 - * implements it. We reserve two 16M regions for ISA.
7538 - */
7539 -
7540 -#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
7541 -#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
7542 -
7543  /* physical addresses of all the chip-select areas */
7544
7545  #define S3C2410_CS0 (0x00000000)
7546 @@ -152,27 +92,16 @@
7547  #define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
7548  #define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
7549  #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
7550 -#define S3C24XX_PA_IIC      S3C2410_PA_IIC
7551  #define S3C24XX_PA_IIS      S3C2410_PA_IIS
7552  #define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
7553  #define S3C24XX_PA_RTC      S3C2410_PA_RTC
7554  #define S3C24XX_PA_ADC      S3C2410_PA_ADC
7555  #define S3C24XX_PA_SPI      S3C2410_PA_SPI
7556 +#define S3C24XX_PA_SDI      S3C2410_PA_SDI
7557 +#define S3C24XX_PA_NAND            S3C2410_PA_NAND
7558
7559 -/* deal with the registers that move under the 2412/2413 */
7560 -
7561 -#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
7562 -#ifndef __ASSEMBLY__
7563 -extern void __iomem *s3c24xx_va_gpio2;
7564 -#endif
7565 -#ifdef CONFIG_CPU_S3C2412_ONLY
7566 -#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
7567 -#else
7568 -#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
7569 -#endif
7570 -#else
7571 -#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
7572 -#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
7573 -#endif
7574 +#define S3C_PA_IIC          S3C2410_PA_IIC
7575 +#define S3C_PA_UART        S3C24XX_PA_UART
7576 +#define S3C_PA_HSMMC0      S3C2443_PA_HSMMC
7577
7578  #endif /* __ASM_ARCH_MAP_H */
7579 --- /dev/null
7580 +++ b/arch/arm/mach-s3c2410/include/mach/mci.h
7581 @@ -0,0 +1,13 @@
7582 +#ifndef _ARCH_MCI_H
7583 +#define _ARCH_MCI_H
7584 +
7585 +struct s3c24xx_mci_pdata {
7586 +       unsigned int    gpio_detect;
7587 +       unsigned int    gpio_wprotect;
7588 +       unsigned long   ocr_avail;
7589 +       unsigned int    do_dma;
7590 +       void            (*set_power)(unsigned char power_mode,
7591 +                                    unsigned short vdd);
7592 +};
7593 +
7594 +#endif /* _ARCH_NCI_H */
7595 --- /dev/null
7596 +++ b/arch/arm/mach-s3c2410/include/mach/neo1973-pm-gsm.h
7597 @@ -0,0 +1 @@
7598 +extern int gta_gsm_interrupts;
7599 --- /dev/null
7600 +++ b/arch/arm/mach-s3c2410/include/mach/pwm.h
7601 @@ -0,0 +1,46 @@
7602 +#ifndef __S3C2410_PWM_H
7603 +#define __S3C2410_PWM_H
7604 +
7605 +#include <linux/err.h>
7606 +#include <linux/platform_device.h>
7607 +#include <linux/clk.h>
7608 +
7609 +#include <mach/io.h>
7610 +#include <mach/hardware.h>
7611 +#include <asm/mach-types.h>
7612 +#include <plat/regs-timer.h>
7613 +#include <mach/gta01.h>
7614 +
7615 +enum pwm_timer {
7616 +       PWM0,
7617 +       PWM1,
7618 +       PWM2,
7619 +       PWM3,
7620 +       PWM4
7621 +};
7622 +
7623 +struct s3c2410_pwm {
7624 +       enum pwm_timer timerid;
7625 +       struct clk *pclk;
7626 +       unsigned long pclk_rate;
7627 +       unsigned long prescaler;
7628 +       unsigned long divider;
7629 +       unsigned long counter;
7630 +       unsigned long comparer;
7631 +};
7632 +
7633 +struct s3c24xx_pwm_platform_data{
7634 +        /* callback to attach platform children (to enforce suspend / resume
7635 +         * ordering */
7636 +        void (*attach_child_devices)(struct device *parent_device);
7637 +};
7638 +
7639 +int s3c2410_pwm_init(struct s3c2410_pwm *s3c2410_pwm);
7640 +int s3c2410_pwm_enable(struct s3c2410_pwm *s3c2410_pwm);
7641 +int s3c2410_pwm_disable(struct s3c2410_pwm *s3c2410_pwm);
7642 +int s3c2410_pwm_start(struct s3c2410_pwm *s3c2410_pwm);
7643 +int s3c2410_pwm_stop(struct s3c2410_pwm *s3c2410_pwm);
7644 +int s3c2410_pwm_duty_cycle(int reg_value, struct s3c2410_pwm *s3c2410_pwm);
7645 +int s3c2410_pwm_dumpregs(void);
7646 +
7647 +#endif /* __S3C2410_PWM_H */
7648 --- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
7649 +++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
7650 @@ -42,13 +42,6 @@
7651  #define S3C2410_CLKCON_IIS          (1<<17)
7652  #define S3C2410_CLKCON_SPI          (1<<18)
7653
7654 -#define S3C2410_PLLCON_MDIVSHIFT     12
7655 -#define S3C2410_PLLCON_PDIVSHIFT     4
7656 -#define S3C2410_PLLCON_SDIVSHIFT     0
7657 -#define S3C2410_PLLCON_MDIVMASK             ((1<<(1+(19-12)))-1)
7658 -#define S3C2410_PLLCON_PDIVMASK             ((1<<5)-1)
7659 -#define S3C2410_PLLCON_SDIVMASK             3
7660 -
7661  /* DCLKCON register addresses in gpio.h */
7662
7663  #define S3C2410_DCLKCON_DCLK0EN             (1<<0)
7664 @@ -76,32 +69,6 @@
7665  #define S3C2410_CLKSLOW_SLOWVAL(x)     (x)
7666  #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
7667
7668 -#ifndef __ASSEMBLY__
7669 -
7670 -#include <asm/div64.h>
7671 -
7672 -static inline unsigned int
7673 -s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
7674 -{
7675 -       unsigned int mdiv, pdiv, sdiv;
7676 -       uint64_t fvco;
7677 -
7678 -       mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
7679 -       pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
7680 -       sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
7681 -
7682 -       mdiv &= S3C2410_PLLCON_MDIVMASK;
7683 -       pdiv &= S3C2410_PLLCON_PDIVMASK;
7684 -       sdiv &= S3C2410_PLLCON_SDIVMASK;
7685 -
7686 -       fvco = (uint64_t)baseclk * (mdiv + 8);
7687 -       do_div(fvco, (pdiv + 2) << sdiv);
7688 -
7689 -       return (unsigned int)fvco;
7690 -}
7691 -
7692 -#endif /* __ASSEMBLY__ */
7693 -
7694  #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
7695
7696  /* extra registers */
7697 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
7698 +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
7699 @@ -14,16 +14,7 @@
7700  #ifndef __ASM_ARCH_REGS_GPIO_H
7701  #define __ASM_ARCH_REGS_GPIO_H
7702
7703 -#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
7704 -
7705 -#define S3C2410_GPIO_BANKA   (32*0)
7706 -#define S3C2410_GPIO_BANKB   (32*1)
7707 -#define S3C2410_GPIO_BANKC   (32*2)
7708 -#define S3C2410_GPIO_BANKD   (32*3)
7709 -#define S3C2410_GPIO_BANKE   (32*4)
7710 -#define S3C2410_GPIO_BANKF   (32*5)
7711 -#define S3C2410_GPIO_BANKG   (32*6)
7712 -#define S3C2410_GPIO_BANKH   (32*7)
7713 +#include <mach/gpio-nrs.h>
7714
7715  #ifdef CONFIG_CPU_S3C2400
7716  #define S3C24XX_GPIO_BASE(x)  S3C2400_GPIO_BASE(x)
7717 @@ -1053,13 +1044,6 @@
7718  #define S3C24XX_EXTINT1           S3C24XX_GPIOREG2(0x8C)
7719  #define S3C24XX_EXTINT2           S3C24XX_GPIOREG2(0x90)
7720
7721 -/* values for S3C2410_EXTINT0/1/2 */
7722 -#define S3C2410_EXTINT_LOWLEV   (0x00)
7723 -#define S3C2410_EXTINT_HILEV    (0x01)
7724 -#define S3C2410_EXTINT_FALLEDGE         (0x02)
7725 -#define S3C2410_EXTINT_RISEEDGE         (0x04)
7726 -#define S3C2410_EXTINT_BOTHEDGE         (0x06)
7727 -
7728  /* interrupt filtering conrrol for EINT16..EINT23 */
7729  #define S3C2410_EINFLT0           S3C2410_GPIOREG(0x94)
7730  #define S3C2410_EINFLT1           S3C2410_GPIOREG(0x98)
7731 --- a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
7732 +++ b/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
7733 @@ -30,6 +30,7 @@
7734  #define S3C2410_SDIFSTA               (0x38)
7735
7736  #define S3C2410_SDIDATA               (0x3C)
7737 +#define S3C2410_SDIDATA_BYTE          (0x3C)
7738  #define S3C2410_SDIIMSK               (0x40)
7739
7740  #define S3C2440_SDIDATA               (0x40)
7741 @@ -37,6 +38,8 @@
7742
7743  #define S3C2440_SDICON_SDRESET        (1<<8)
7744  #define S3C2440_SDICON_MMCCLOCK       (1<<5)
7745 +#define S3C2440_SDIDATA_BYTE          (0x48)
7746 +
7747  #define S3C2410_SDICON_BYTEORDER      (1<<4)
7748  #define S3C2410_SDICON_SDIOIRQ        (1<<3)
7749  #define S3C2410_SDICON_RWAITEN        (1<<2)
7750 --- /dev/null
7751 +++ b/arch/arm/mach-s3c2410/include/mach/s3c24xx-serial.h
7752 @@ -0,0 +1,5 @@
7753 +#include <linux/resume-dependency.h>
7754 +
7755 +extern void s3c24xx_serial_console_set_silence(int silence);
7756 +extern void s3c24xx_serial_register_resume_dependency(struct resume_dependency *
7757 +                                            resume_dependency, int uart_index);
7758 --- a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
7759 +++ b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
7760 @@ -21,7 +21,15 @@ struct s3c2410_spigpio_info {
7761         int                      num_chipselect;
7762         int                      bus_num;
7763
7764 -       void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs);
7765 +       /*
7766 +        * FIXME: board_size and board_info DO NOT belong here.
7767 +        * These were already removed upstream... but we still rely on them
7768 +        * so leave for now and revisit this.
7769 +        */
7770 +       unsigned long            board_size;
7771 +       struct spi_board_info   *board_info;
7772 +
7773 +       void (*chip_select)(struct s3c2410_spigpio_info *spi, int csid, int cs);
7774  };
7775
7776
7777 --- a/arch/arm/mach-s3c2410/include/mach/spi.h
7778 +++ b/arch/arm/mach-s3c2410/include/mach/spi.h
7779 @@ -22,5 +22,12 @@ struct s3c2410_spi_info {
7780         void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
7781  };
7782
7783 +/* Standard setup / suspend routines for SPI GPIO pins. */
7784 +
7785 +extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
7786 +                                                int enable);
7787 +
7788 +extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
7789 +                                             int enable);
7790
7791  #endif /* __ASM_ARCH_SPI_H */
7792 --- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
7793 +++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
7794 @@ -13,7 +13,7 @@
7795  #include <mach/hardware.h>
7796  #include <linux/io.h>
7797
7798 -#include <asm/plat-s3c/regs-watchdog.h>
7799 +#include <plat/regs-watchdog.h>
7800  #include <mach/regs-clock.h>
7801
7802  #include <linux/clk.h>
7803 --- /dev/null
7804 +++ b/arch/arm/mach-s3c2410/include/mach/tick.h
7805 @@ -0,0 +1,15 @@
7806 +/* linux/arch/arm/mach-s3c2410/include/mach/tick.h
7807 + *
7808 + * Copyright 2008 Simtec Electronics
7809 + *      Ben Dooks <ben@simtec.co.uk>
7810 + *      http://armlinux.simtec.co.uk/
7811 + *
7812 + * S3C2410 - timer tick support
7813 + */
7814 +
7815 +#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
7816 +
7817 +static inline int s3c24xx_ostimer_pending(void)
7818 +{
7819 +       return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4;
7820 +}
7821 --- a/arch/arm/mach-s3c2410/include/mach/timex.h
7822 +++ /dev/null
7823 @@ -1,26 +0,0 @@
7824 -/* arch/arm/mach-s3c2410/include/mach/timex.h
7825 - *
7826 - * Copyright (c) 2003-2005 Simtec Electronics
7827 - *     Ben Dooks <ben@simtec.co.uk>
7828 - *
7829 - * S3C2410 - time parameters
7830 - *
7831 - * This program is free software; you can redistribute it and/or modify
7832 - * it under the terms of the GNU General Public License version 2 as
7833 - * published by the Free Software Foundation.
7834 -*/
7835 -
7836 -#ifndef __ASM_ARCH_TIMEX_H
7837 -#define __ASM_ARCH_TIMEX_H
7838 -
7839 -/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
7840 - * a variable is useless. It seems as long as we make our timers an
7841 - * exact multiple of HZ, any value that makes a 1->1 correspondence
7842 - * for the time conversion functions to/from jiffies is acceptable.
7843 -*/
7844 -
7845 -
7846 -#define CLOCK_TICK_RATE 12000000
7847 -
7848 -
7849 -#endif /* __ASM_ARCH_TIMEX_H */
7850 --- /dev/null
7851 +++ b/arch/arm/mach-s3c2410/include/mach/ts.h
7852 @@ -0,0 +1,35 @@
7853 +/* arch/arm/mach-s3c2410/include/mach/ts.h
7854 + *
7855 + * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
7856 + *
7857 + *
7858 + * This program is free software; you can redistribute it and/or modify
7859 + * it under the terms of the GNU General Public License version 2 as
7860 + * published by the Free Software Foundation.
7861 + *
7862 + *
7863 + *  Changelog:
7864 + *     24-Mar-2005     RTP     Created file
7865 + *     03-Aug-2005     RTP     Renamed to ts.h
7866 + */
7867 +
7868 +#ifndef __ASM_ARM_TS_H
7869 +#define __ASM_ARM_TS_H
7870 +
7871 +#include <linux/ts_filter.h>
7872 +
7873 +struct s3c2410_ts_mach_info {
7874 +        int delay;
7875 +        int presc;
7876 +        /* array of pointers to filter APIs we want to use, in order
7877 +         * ends on first NULL, all NULL is OK
7878 +         */
7879 +        struct ts_filter_api *filter_sequence[MAX_TS_FILTER_CHAIN];
7880 +        /* array of configuration ints, one for each filter above */
7881 +        void *filter_config[MAX_TS_FILTER_CHAIN];
7882 +};
7883 +
7884 +void set_s3c2410ts_info(struct s3c2410_ts_mach_info *hard_s3c2410ts_info);
7885 +
7886 +#endif /* __ASM_ARM_TS_H */
7887 +
7888 --- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
7889 +++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h
7890 @@ -1,3 +1,4 @@
7891 +
7892  /* arch/arm/mach-s3c2410/include/mach/uncompress.h
7893   *
7894   * Copyright (c) 2003, 2007 Simtec Electronics
7895 --- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h
7896 +++ /dev/null
7897 @@ -1,20 +0,0 @@
7898 -/* arch/arm/mach-s3c2410/include/mach/vmalloc.h
7899 - *
7900 - * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
7901 - *
7902 - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
7903 - *                   http://www.simtec.co.uk/products/SWLINUX/
7904 - *
7905 - * This program is free software; you can redistribute it and/or modify
7906 - * it under the terms of the GNU General Public License version 2 as
7907 - * published by the Free Software Foundation.
7908 - *
7909 - * S3C2410 vmalloc definition
7910 -*/
7911 -
7912 -#ifndef __ASM_ARCH_VMALLOC_H
7913 -#define __ASM_ARCH_VMALLOC_H
7914 -
7915 -#define VMALLOC_END      (0xE0000000)
7916 -
7917 -#endif /* __ASM_ARCH_VMALLOC_H */
7918 --- a/arch/arm/mach-s3c2410/Kconfig
7919 +++ b/arch/arm/mach-s3c2410/Kconfig
7920 @@ -9,6 +9,7 @@ config CPU_S3C2410
7921         depends on ARCH_S3C2410
7922         select S3C2410_CLOCK
7923         select S3C2410_GPIO
7924 +       select S3C2410_PWM
7925         select CPU_LLSERIAL_S3C2410
7926         select S3C2410_PM if PM
7927         help
7928 @@ -32,11 +33,6 @@ config S3C2410_GPIO
7929         help
7930           GPIO code for S3C2410 and similar processors
7931
7932 -config S3C2410_CLOCK
7933 -       bool
7934 -       help
7935 -         Clock code for the S3C2410, and similar processors
7936 -
7937  config SIMTEC_NOR
7938         bool
7939         help
7940 @@ -49,6 +45,12 @@ config MACH_BAST_IDE
7941           Internal node for machines with an BAST style IDE
7942           interface
7943
7944 +config S3C2410_PWM
7945 +       bool
7946 +       help
7947 +         PWM timer code for the S3C2410, and similar processors
7948 +
7949 +
7950  menu "S3C2410 Machines"
7951
7952  config ARCH_SMDK2410
7953 @@ -84,6 +86,7 @@ config ARCH_BAST
7954         select PM_SIMTEC if PM
7955         select SIMTEC_NOR
7956         select MACH_BAST_IDE
7957 +       select S3C24XX_DCLK
7958         select ISA
7959         help
7960           Say Y here if you are using the Simtec Electronics EB2410ITX
7961 @@ -121,6 +124,7 @@ config MACH_TCT_HAMMER
7962  config MACH_VR1000
7963         bool "Thorcom VR1000"
7964         select PM_SIMTEC if PM
7965 +       select S3C24XX_DCLK
7966         select SIMTEC_NOR
7967         select MACH_BAST_IDE
7968         select CPU_S3C2410
7969 @@ -130,7 +134,16 @@ config MACH_VR1000
7970  config MACH_QT2410
7971         bool "QT2410"
7972         select CPU_S3C2410
7973 +       select DISPLAY_JBT6K74
7974         help
7975            Say Y here if you are using the Armzone QT2410
7976
7977 +config MACH_NEO1973_GTA01
7978 +       bool "FIC Neo1973 GSM Phone (GTA01 Hardware)"
7979 +       select CPU_S3C2410
7980 +       select MACH_NEO1973
7981 +       select SENSORS_PCF50606
7982 +       help
7983 +          Say Y here if you are using the FIC Neo1973 GSM Phone
7984 +
7985  endmenu
7986 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c
7987 +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
7988 @@ -52,6 +52,7 @@
7989  #include <mach/regs-lcd.h>
7990  #include <mach/regs-gpio.h>
7991
7992 +#include <plat/iic.h>
7993  #include <plat/devs.h>
7994  #include <plat/cpu.h>
7995
7996 @@ -150,7 +151,7 @@ static struct platform_device *amlm5900_
7997  #endif
7998         &s3c_device_adc,
7999         &s3c_device_wdt,
8000 -       &s3c_device_i2c,
8001 +       &s3c_device_i2c0,
8002         &s3c_device_usb,
8003         &s3c_device_rtc,
8004         &s3c_device_usbgadget,
8005 @@ -233,6 +234,7 @@ static void __init amlm5900_init(void)
8006  #ifdef CONFIG_FB_S3C2410
8007         s3c24xx_fb_set_platdata(&amlm5900_fb_info);
8008  #endif
8009 +       s3c_i2c0_set_platdata(NULL);
8010         platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
8011  }
8012
8013 --- a/arch/arm/mach-s3c2410/mach-bast.c
8014 +++ b/arch/arm/mach-s3c2410/mach-bast.c
8015 @@ -44,8 +44,8 @@
8016  #include <mach/regs-mem.h>
8017  #include <mach/regs-lcd.h>
8018
8019 -#include <asm/plat-s3c/nand.h>
8020 -#include <asm/plat-s3c/iic.h>
8021 +#include <plat/nand.h>
8022 +#include <plat/iic.h>
8023  #include <mach/fb.h>
8024
8025  #include <linux/mtd/mtd.h>
8026 @@ -406,7 +406,7 @@ static struct platform_device bast_sio =
8027   * standard 100KHz i2c bus frequency
8028  */
8029
8030 -static struct s3c2410_platform_i2c bast_i2c_info = {
8031 +static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
8032         .flags          = 0,
8033         .slave_addr     = 0x10,
8034         .bus_freq       = 100*1000,
8035 @@ -553,7 +553,7 @@ static struct platform_device *bast_devi
8036         &s3c_device_usb,
8037         &s3c_device_lcd,
8038         &s3c_device_wdt,
8039 -       &s3c_device_i2c,
8040 +       &s3c_device_i2c0,
8041         &s3c_device_rtc,
8042         &s3c_device_nand,
8043         &bast_device_dm9k,
8044 @@ -588,7 +588,8 @@ static void __init bast_map_io(void)
8045         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
8046
8047         s3c_device_nand.dev.platform_data = &bast_nand_info;
8048 -       s3c_device_i2c.dev.platform_data = &bast_i2c_info;
8049 +
8050 +       s3c_i2c0_set_platdata(&bast_i2c_info);
8051
8052         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
8053         s3c24xx_init_clocks(0);
8054 --- /dev/null
8055 +++ b/arch/arm/mach-s3c2410/mach-gta01.c
8056 @@ -0,0 +1,786 @@
8057 +/*
8058 + * linux/arch/arm/mach-s3c2410/mach-gta01.c
8059 + *
8060 + * S3C2410 Machine Support for the FIC Neo1973 GTA01
8061 + *
8062 + * Copyright (C) 2006-2007 by Openmoko, Inc.
8063 + * Author: Harald Welte <laforge@openmoko.org>
8064 + * All rights reserved.
8065 + *
8066 + * This program is free software; you can redistribute it and/or
8067 + * modify it under the terms of the GNU General Public License as
8068 + * published by the Free Software Foundation; either version 2 of
8069 + * the License, or (at your option) any later version.
8070 + *
8071 + * This program is distributed in the hope that it will be useful,
8072 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8073 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8074 + * GNU General Public License for more details.
8075 + *
8076 + * You should have received a copy of the GNU General Public License
8077 + * along with this program; if not, write to the Free Software
8078 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
8079 + * MA 02111-1307 USA
8080 + *
8081 + */
8082 +
8083 +#include <linux/kernel.h>
8084 +#include <linux/types.h>
8085 +#include <linux/interrupt.h>
8086 +#include <linux/list.h>
8087 +#include <linux/timer.h>
8088 +#include <linux/init.h>
8089 +#include <linux/workqueue.h>
8090 +#include <linux/platform_device.h>
8091 +#include <linux/i2c.h>
8092 +#include <linux/serial_core.h>
8093 +#include <mach/ts.h>
8094 +#include <linux/spi/spi.h>
8095 +#include <linux/spi/spi_bitbang.h>
8096 +#include <linux/mmc/mmc.h>
8097 +#include <linux/mmc/host.h>
8098 +
8099 +#include <linux/mtd/mtd.h>
8100 +#include <linux/mtd/nand.h>
8101 +#include <linux/mtd/nand_ecc.h>
8102 +#include <linux/mtd/partitions.h>
8103 +
8104 +#include <linux/mmc/host.h>
8105 +
8106 +#include <linux/pcf50606.h>
8107 +
8108 +#include <asm/mach/arch.h>
8109 +#include <asm/mach/map.h>
8110 +#include <asm/mach/irq.h>
8111 +
8112 +#include <mach/hardware.h>
8113 +#include <mach/io.h>
8114 +#include <asm/irq.h>
8115 +#include <asm/mach-types.h>
8116 +
8117 +#include <mach/regs-gpio.h>
8118 +#include <mach/fb.h>
8119 +#include <mach/mci.h>
8120 +#include <mach/spi.h>
8121 +#include <mach/spi-gpio.h>
8122 +#include <mach/usb-control.h>
8123 +
8124 +#include <mach/gta01.h>
8125 +
8126 +#include <plat/regs-serial.h>
8127 +#include <plat/nand.h>
8128 +#include <plat/devs.h>
8129 +#include <plat/cpu.h>
8130 +#include <plat/pm.h>
8131 +#include <plat/udc.h>
8132 +#include <plat/iic.h>
8133 +#include <asm/plat-s3c24xx/neo1973.h>
8134 +#include <mach/neo1973-pm-gsm.h>
8135 +
8136 +#include <linux/jbt6k74.h>
8137 +
8138 +#include <linux/ts_filter_mean.h>
8139 +#include <linux/ts_filter_median.h>
8140 +
8141 +
8142 +static struct map_desc gta01_iodesc[] __initdata = {
8143 +       {
8144 +               .virtual        = 0xe0000000,
8145 +               .pfn            = __phys_to_pfn(S3C2410_CS3+0x01000000),
8146 +               .length         = SZ_1M,
8147 +               .type           = MT_DEVICE
8148 +       },
8149 +};
8150 +
8151 +#define UCON S3C2410_UCON_DEFAULT
8152 +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
8153 +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
8154 +/* UFCON for the gta01 sets the FIFO trigger level at 4, not 8 */
8155 +#define UFCON_GTA01_PORT0 S3C2410_UFCON_FIFOMODE
8156 +
8157 +static struct s3c2410_uartcfg gta01_uartcfgs[] = {
8158 +       [0] = {
8159 +               .hwport      = 0,
8160 +               .flags       = 0,
8161 +               .ucon        = UCON,
8162 +               .ulcon       = ULCON,
8163 +               .ufcon       = UFCON_GTA01_PORT0,
8164 +       },
8165 +       [1] = {
8166 +               .hwport      = 1,
8167 +               .flags       = 0,
8168 +               .ucon        = UCON,
8169 +               .ulcon       = ULCON,
8170 +               .ufcon       = UFCON,
8171 +       },
8172 +};
8173 +
8174 +/* PMU driver info */
8175 +
8176 +static int pmu_callback(struct device *dev, unsigned int feature,
8177 +                       enum pmu_event event)
8178 +{
8179 +       switch (feature) {
8180 +       case PCF50606_FEAT_ACD:
8181 +               switch (event) {
8182 +               case PMU_EVT_INSERT:
8183 +                       pcf50606_charge_fast(pcf50606_global, 1);
8184 +                       break;
8185 +               case PMU_EVT_REMOVE:
8186 +                       pcf50606_charge_fast(pcf50606_global, 0);
8187 +                       break;
8188 +               default:
8189 +                       break;
8190 +               }
8191 +               break;
8192 +       default:
8193 +               break;
8194 +       }
8195 +
8196 +       return 0;
8197 +}
8198 +
8199 +static struct pcf50606_platform_data gta01_pcf_pdata = {
8200 +       .used_features  = PCF50606_FEAT_EXTON |
8201 +                         PCF50606_FEAT_MBC |
8202 +                         PCF50606_FEAT_BBC |
8203 +                         PCF50606_FEAT_RTC |
8204 +                         PCF50606_FEAT_WDT |
8205 +                         PCF50606_FEAT_CHGCUR |
8206 +                         PCF50606_FEAT_BATVOLT |
8207 +                         PCF50606_FEAT_BATTEMP,
8208 +       .onkey_seconds_required = 3,
8209 +       .cb             = &pmu_callback,
8210 +       .r_fix_batt     = 10000,
8211 +       .r_fix_batt_par = 10000,
8212 +       .r_sense_milli  = 220,
8213 +       .rails  = {
8214 +               [PCF50606_REGULATOR_D1REG] = {
8215 +                       .name           = "bt_3v15",
8216 +                       .voltage        = {
8217 +                               .init   = 3150,
8218 +                               .max    = 3150,
8219 +                       },
8220 +               },
8221 +               [PCF50606_REGULATOR_D2REG] = {
8222 +                       .name           = "gl_2v5",
8223 +                       .voltage        = {
8224 +                               .init   = 2500,
8225 +                               .max    = 2500,
8226 +                       },
8227 +               },
8228 +               [PCF50606_REGULATOR_D3REG] = {
8229 +                       .name           = "stby_1v8",
8230 +                       .flags          = PMU_VRAIL_F_SUSPEND_ON,
8231 +                       .voltage        = {
8232 +                               .init   = 1800,
8233 +                               .max    = 2100,
8234 +                       },
8235 +               },
8236 +               [PCF50606_REGULATOR_DCD] = {
8237 +                       .name           = "gl_1v5",
8238 +                       .voltage        = {
8239 +                               .init   = 1500,
8240 +                               .max    = 1500,
8241 +                       },
8242 +               },
8243 +               [PCF50606_REGULATOR_DCDE] = {
8244 +                       .name           = "io_3v3",
8245 +                       .flags          = PMU_VRAIL_F_SUSPEND_ON,
8246 +                       .voltage        = {
8247 +                               .init   = 3300,
8248 +                               .max    = 3330,
8249 +                       },
8250 +               },
8251 +               [PCF50606_REGULATOR_DCUD] = {
8252 +                       .name           = "core_1v8",
8253 +                       .flags          = PMU_VRAIL_F_SUSPEND_ON,
8254 +                       .voltage        = {
8255 +                               .init   = 2100,
8256 +                               .max    = 2100,
8257 +                       },
8258 +               },
8259 +               [PCF50606_REGULATOR_IOREG] = {
8260 +                       .name           = "codec_3v3",
8261 +                       .voltage        = {
8262 +                               .init   = 3300,
8263 +                               .max    = 3300,
8264 +                       },
8265 +               },
8266 +               [PCF50606_REGULATOR_LPREG] = {
8267 +                       .name           = "lcm_3v3",
8268 +                       .voltage        = {
8269 +                               .init   = 3300,
8270 +                               .max    = 3300,
8271 +                       },
8272 +               }
8273 +       },
8274 +};
8275 +
8276 +static void cfg_pmu_vrail(struct pmu_voltage_rail *vrail, char *name,
8277 +                         unsigned int flags, unsigned int init,
8278 +                         unsigned int max)
8279 +{
8280 +       vrail->name = name;
8281 +       vrail->flags = flags;
8282 +       vrail->voltage.init = init;
8283 +       vrail->voltage.max = max;
8284 +}
8285 +
8286 +static void mangle_pmu_pdata_by_system_rev(void)
8287 +{
8288 +       switch (system_rev) {
8289 +       case GTA01Bv4_SYSTEM_REV:
8290 +               gta01_pcf_pdata.used_features |= PCF50606_FEAT_ACD;
8291 +               break;
8292 +       case GTA01Bv3_SYSTEM_REV:
8293 +       case GTA01Bv2_SYSTEM_REV:
8294 +               gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG]
8295 +                                       .name = "user1";
8296 +               gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG]
8297 +                                       .flags &= ~PMU_VRAIL_F_SUSPEND_ON;
8298 +               gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG]
8299 +                                       .flags = PMU_VRAIL_F_UNUSED;
8300 +               break;
8301 +       case GTA01v4_SYSTEM_REV:
8302 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCUD],
8303 +                             "core_1v8", PMU_VRAIL_F_SUSPEND_ON, 1800, 1800);
8304 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D1REG],
8305 +                             "vrf_3v", 0, 3000, 3000);
8306 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG],
8307 +                             "vtcxo_2v8", 0, 2800, 2800);
8308 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCD],
8309 +                             "gl_3v5", 0, 3500, 3500);
8310 +               break;
8311 +       case GTA01v3_SYSTEM_REV:
8312 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D1REG],
8313 +                             "vrf_3v", 0, 3000, 3000);
8314 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D2REG],
8315 +                             "sd_3v3", 0, 3300, 3300);
8316 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG],
8317 +                             "codec_3v3", 0, 3300, 3300);
8318 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCD],
8319 +                             "gpsio_3v3", 0, 3300, 3300);
8320 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCUD],
8321 +                             "core_1v8", PMU_VRAIL_F_SUSPEND_ON, 1800, 1800);
8322 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_IOREG],
8323 +                             "vtcxo_2v8", 0, 2800, 2800);
8324 +               break;
8325 +       }
8326 +}
8327 +
8328 +static struct resource gta01_pmu_resources[] = {
8329 +       [0] = {
8330 +               .flags  = IORESOURCE_IRQ,
8331 +               .start  = GTA01_IRQ_PCF50606,
8332 +               .end    = GTA01_IRQ_PCF50606,
8333 +       },
8334 +};
8335 +
8336 +struct platform_device gta01_pmu_dev = {
8337 +       .name           = "pcf50606",
8338 +       .num_resources  = ARRAY_SIZE(gta01_pmu_resources),
8339 +       .resource       = gta01_pmu_resources,
8340 +       .dev            = {
8341 +               .platform_data = &gta01_pcf_pdata,
8342 +       },
8343 +};
8344 +
8345 +/* LCD driver info */
8346 +
8347 +/* Configuration for 480x640 toppoly TD028TTEC1.
8348 + * Do not mark this as __initdata or it will break! */
8349 +static struct s3c2410fb_display gta01_displays[] =  {
8350 +       {
8351 +               .type           = S3C2410_LCDCON1_TFT,
8352 +               .width          = 43,
8353 +               .height         = 58,
8354 +               .xres           = 480,
8355 +               .yres           = 640,
8356 +               .bpp            = 16,
8357 +
8358 +               .pixclock       = 40000,        /* HCLK/4 */
8359 +               .left_margin    = 104,
8360 +               .right_margin   = 8,
8361 +               .hsync_len      = 8,
8362 +               .upper_margin   = 2,
8363 +               .lower_margin   = 16,
8364 +               .vsync_len      = 2,
8365 +               .lcdcon5        = S3C2410_LCDCON5_FRM565 |
8366 +                                 S3C2410_LCDCON5_INVVCLK |
8367 +                                 S3C2410_LCDCON5_INVVLINE |
8368 +                                 S3C2410_LCDCON5_INVVFRAME |
8369 +                                 S3C2410_LCDCON5_PWREN |
8370 +                                 S3C2410_LCDCON5_HWSWP,
8371 +       },
8372 +       {
8373 +               .type           = S3C2410_LCDCON1_TFT,
8374 +               .width          = 43,
8375 +               .height         = 58,
8376 +               .xres           = 480,
8377 +               .yres           = 640,
8378 +               .bpp            = 32,
8379 +
8380 +               .pixclock       = 40000,        /* HCLK/4 */
8381 +               .left_margin    = 104,
8382 +               .right_margin   = 8,
8383 +               .hsync_len      = 8,
8384 +               .upper_margin   = 2,
8385 +               .lower_margin   = 16,
8386 +               .vsync_len      = 2,
8387 +               .lcdcon5        = S3C2410_LCDCON5_FRM565 |
8388 +                                 S3C2410_LCDCON5_INVVCLK |
8389 +                                 S3C2410_LCDCON5_INVVLINE |
8390 +                                 S3C2410_LCDCON5_INVVFRAME |
8391 +                                 S3C2410_LCDCON5_PWREN |
8392 +                                 S3C2410_LCDCON5_HWSWP,
8393 +       },
8394 +       {
8395 +               .type           = S3C2410_LCDCON1_TFT,
8396 +               .width          = 43,
8397 +               .height         = 58,
8398 +               .xres           = 240,
8399 +               .yres           = 320,
8400 +               .bpp            = 16,
8401 +
8402 +               .pixclock       = 40000,        /* HCLK/4 */
8403 +               .left_margin    = 104,
8404 +               .right_margin   = 8,
8405 +               .hsync_len      = 8,
8406 +               .upper_margin   = 2,
8407 +               .lower_margin   = 16,
8408 +               .vsync_len      = 2,
8409 +               .lcdcon5        = S3C2410_LCDCON5_FRM565 |
8410 +                                 S3C2410_LCDCON5_INVVCLK |
8411 +                                 S3C2410_LCDCON5_INVVLINE |
8412 +                                 S3C2410_LCDCON5_INVVFRAME |
8413 +                                 S3C2410_LCDCON5_PWREN |
8414 +                                 S3C2410_LCDCON5_HWSWP,
8415 +       },
8416 +};
8417 +
8418 +static struct s3c2410fb_mach_info gta01_lcd_cfg __initdata = {
8419 +       .displays       = gta01_displays,
8420 +       .num_displays   = ARRAY_SIZE(gta01_displays),
8421 +       .default_display = 0,
8422 +
8423 +       .lpcsel         = ((0xCE6) & ~7) | 1<<4,
8424 +};
8425 +
8426 +static struct platform_device *gta01_devices[] __initdata = {
8427 +       &s3c_device_usb,
8428 +       &s3c_device_lcd,
8429 +       &s3c_device_wdt,
8430 +       &s3c_device_i2c0,
8431 +       &s3c_device_iis,
8432 +       &s3c_device_sdi,
8433 +       &s3c_device_usbgadget,
8434 +       &s3c_device_nand,
8435 +       &s3c_device_ts,
8436 +};
8437 +
8438 +static struct s3c2410_nand_set gta01_nand_sets[] = {
8439 +       [0] = {
8440 +               .name           = "neo1973-nand",
8441 +               .nr_chips       = 1,
8442 +               .flags          = S3C2410_NAND_BBT,
8443 +       },
8444 +};
8445 +
8446 +static struct s3c2410_platform_nand gta01_nand_info = {
8447 +       .tacls          = 20,
8448 +       .twrph0         = 60,
8449 +       .twrph1         = 20,
8450 +       .nr_sets        = ARRAY_SIZE(gta01_nand_sets),
8451 +       .sets           = gta01_nand_sets,
8452 +};
8453 +
8454 +static void gta01_mmc_set_power(unsigned char power_mode, unsigned short vdd)
8455 +{
8456 +       int bit;
8457 +       int mv = 1700; /* 1.7V for MMC_VDD_165_195 */
8458 +
8459 +       printk(KERN_DEBUG "mmc_set_power(power_mode=%u, vdd=%u)\n",
8460 +              power_mode, vdd);
8461 +
8462 +       switch (system_rev) {
8463 +       case GTA01v3_SYSTEM_REV:
8464 +               switch (power_mode) {
8465 +               case MMC_POWER_OFF:
8466 +                       pcf50606_onoff_set(pcf50606_global,
8467 +                                          PCF50606_REGULATOR_D2REG, 0);
8468 +                       break;
8469 +               case MMC_POWER_ON:
8470 +                       /* translate MMC_VDD_* VDD bit to mv */
8471 +                       for (bit = 8; bit != 24; bit++)
8472 +                               if (vdd == (1 << bit))
8473 +                                       mv += 100 * (bit - 4);
8474 +                       pcf50606_voltage_set(pcf50606_global,
8475 +                                            PCF50606_REGULATOR_D2REG, mv);
8476 +                       pcf50606_onoff_set(pcf50606_global,
8477 +                                          PCF50606_REGULATOR_D2REG, 1);
8478 +                       break;
8479 +               }
8480 +               break;
8481 +       case GTA01v4_SYSTEM_REV:
8482 +       case GTA01Bv2_SYSTEM_REV:
8483 +       case GTA01Bv3_SYSTEM_REV:
8484 +       case GTA01Bv4_SYSTEM_REV:
8485 +               switch (power_mode) {
8486 +               case MMC_POWER_OFF:
8487 +                       neo1973_gpb_setpin(GTA01_GPIO_SDMMC_ON, 1);
8488 +                       break;
8489 +               case MMC_POWER_ON:
8490 +                       neo1973_gpb_setpin(GTA01_GPIO_SDMMC_ON, 0);
8491 +                       break;
8492 +               }
8493 +               break;
8494 +       }
8495 +}
8496 +
8497 +static struct s3c24xx_mci_pdata gta01_mmc_cfg = {
8498 +       .gpio_detect    = GTA01_GPIO_nSD_DETECT,
8499 +       .set_power      = &gta01_mmc_set_power,
8500 +       .ocr_avail      = MMC_VDD_165_195|MMC_VDD_20_21|
8501 +                         MMC_VDD_21_22|MMC_VDD_22_23|MMC_VDD_23_24|
8502 +                         MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27|
8503 +                         MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
8504 +                         MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33,
8505 +};
8506 +
8507 +static void gta01_udc_command(enum s3c2410_udc_cmd_e cmd)
8508 +{
8509 +       printk(KERN_DEBUG "%s(%d)\n", __func__, cmd);
8510 +
8511 +       switch (cmd) {
8512 +       case S3C2410_UDC_P_ENABLE:
8513 +               neo1973_gpb_setpin(GTA01_GPIO_USB_PULLUP, 1);
8514 +               break;
8515 +       case S3C2410_UDC_P_DISABLE:
8516 +               neo1973_gpb_setpin(GTA01_GPIO_USB_PULLUP, 0);
8517 +               break;
8518 +       default:
8519 +               break;
8520 +       }
8521 +}
8522 +
8523 +/* use a work queue, since I2C API inherently schedules
8524 + * and we get called in hardirq context from UDC driver */
8525 +
8526 +struct vbus_draw {
8527 +       struct work_struct work;
8528 +       int ma;
8529 +};
8530 +static struct vbus_draw gta01_udc_vbus_drawer;
8531 +
8532 +static void __gta01_udc_vbus_draw(struct work_struct *work)
8533 +{
8534 +       /* this is a fix to work around boot-time ordering problems if the
8535 +        * s3c2410_udc is initialized before the pcf50606 driver has defined
8536 +        * pcf50606_global */
8537 +       if (!pcf50606_global)
8538 +               return;
8539 +
8540 +       if (gta01_udc_vbus_drawer.ma >= 500) {
8541 +               /* enable fast charge */
8542 +               printk(KERN_DEBUG "udc: enabling fast charge\n");
8543 +               pcf50606_charge_fast(pcf50606_global, 1);
8544 +       } else {
8545 +               /* disable fast charge */
8546 +               printk(KERN_DEBUG "udc: disabling fast charge\n");
8547 +               pcf50606_charge_fast(pcf50606_global, 0);
8548 +       }
8549 +}
8550 +
8551 +static void gta01_udc_vbus_draw(unsigned int ma)
8552 +{
8553 +       gta01_udc_vbus_drawer.ma = ma;
8554 +       schedule_work(&gta01_udc_vbus_drawer.work);
8555 +}
8556 +
8557 +static struct s3c2410_udc_mach_info gta01_udc_cfg = {
8558 +       .vbus_draw      = gta01_udc_vbus_draw,
8559 +};
8560 +
8561 +
8562 +/* touchscreen configuration */
8563 +
8564 +static struct ts_filter_median_configuration gta01_ts_median_config = {
8565 +       .extent = 31,
8566 +       .decimation_below = 24,
8567 +       .decimation_threshold = 8 * 3,
8568 +       .decimation_above = 12,
8569 +};
8570 +
8571 +static struct ts_filter_mean_configuration gta01_ts_mean_config = {
8572 +       .bits_filter_length = 5,
8573 +       .averaging_threshold = 12
8574 +};
8575 +
8576 +static struct s3c2410_ts_mach_info gta01_ts_cfg = {
8577 +       .delay = 10000,
8578 +       .presc = 0xff, /* slow as we can go */
8579 +       .filter_sequence = {
8580 +               [0] = &ts_filter_median_api,
8581 +               [1] = &ts_filter_mean_api,
8582 +       },
8583 +       .filter_config = {
8584 +               [0] = &gta01_ts_median_config,
8585 +               [1] = &gta01_ts_mean_config,
8586 +       },
8587 +};
8588 +
8589 +
8590 +/* SPI */
8591 +
8592 +static void gta01_jbt6k74_reset(int devidx, int level)
8593 +{
8594 +       /* empty place holder; gta01 does not yet use this */
8595 +       printk(KERN_DEBUG "gta01_jbt6k74_reset\n");
8596 +}
8597 +
8598 +static void gta01_jbt6k74_resuming(int devidx)
8599 +{
8600 +       gta01bl_deferred_resume();
8601 +}
8602 +
8603 +const struct jbt6k74_platform_data gta01_jbt6k74_pdata = {
8604 +       .reset          = gta01_jbt6k74_reset,
8605 +       .resuming       = gta01_jbt6k74_resuming,
8606 +};
8607 +
8608 +static struct spi_board_info gta01_spi_board_info[] = {
8609 +       {
8610 +               .modalias       = "jbt6k74",
8611 +               .platform_data  = &gta01_jbt6k74_pdata,
8612 +               /* controller_data */
8613 +               /* irq */
8614 +               .max_speed_hz   = 10 * 1000 * 1000,
8615 +               .bus_num        = 1,
8616 +               /* chip_select */
8617 +       },
8618 +};
8619 +
8620 +static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int csidx, int cs)
8621 +{
8622 +       switch (cs) {
8623 +       case BITBANG_CS_ACTIVE:
8624 +               s3c2410_gpio_setpin(S3C2410_GPG3, 0);
8625 +               break;
8626 +       case BITBANG_CS_INACTIVE:
8627 +               s3c2410_gpio_setpin(S3C2410_GPG3, 1);
8628 +               break;
8629 +       }
8630 +}
8631 +
8632 +static struct s3c2410_spigpio_info spi_gpio_cfg = {
8633 +       .pin_clk        = S3C2410_GPG7,
8634 +       .pin_mosi       = S3C2410_GPG6,
8635 +       .pin_miso       = S3C2410_GPG5,
8636 +       .board_size     = ARRAY_SIZE(gta01_spi_board_info),
8637 +       .board_info     = gta01_spi_board_info,
8638 +       .chip_select    = &spi_gpio_cs,
8639 +       .num_chipselect = 2,   /*** Should be 1 or 2 for gta01? ***/
8640 +};
8641 +
8642 +static struct resource s3c_spi_lcm_resource[] = {
8643 +       [0] = {
8644 +               .start = S3C2410_GPG3,
8645 +               .end   = S3C2410_GPG3,
8646 +       },
8647 +       [1] = {
8648 +               .start = S3C2410_GPG5,
8649 +               .end   = S3C2410_GPG5,
8650 +       },
8651 +       [2] = {
8652 +               .start = S3C2410_GPG6,
8653 +               .end   = S3C2410_GPG6,
8654 +       },
8655 +       [3] = {
8656 +               .start = S3C2410_GPG7,
8657 +               .end   = S3C2410_GPG7,
8658 +       },
8659 +};
8660 +
8661 +struct platform_device s3c_device_spi_lcm = {
8662 +       .name             = "spi_s3c24xx_gpio",
8663 +       .id               = 1,
8664 +       .num_resources    = ARRAY_SIZE(s3c_spi_lcm_resource),
8665 +       .resource         = s3c_spi_lcm_resource,
8666 +       .dev = {
8667 +               .platform_data = &spi_gpio_cfg,
8668 +       },
8669 +};
8670 +
8671 +static struct gta01bl_machinfo backlight_machinfo = {
8672 +       .default_intensity      = 1,
8673 +       .max_intensity          = 1,
8674 +       .limit_mask             = 1,
8675 +       .defer_resume_backlight = 1,
8676 +};
8677 +
8678 +static struct resource gta01_bl_resources[] = {
8679 +       [0] = {
8680 +               .start  = GTA01_GPIO_BACKLIGHT,
8681 +               .end    = GTA01_GPIO_BACKLIGHT,
8682 +       },
8683 +};
8684 +
8685 +struct platform_device gta01_bl_dev = {
8686 +       .name           = "gta01-bl",
8687 +       .num_resources  = ARRAY_SIZE(gta01_bl_resources),
8688 +       .resource       = gta01_bl_resources,
8689 +       .dev            = {
8690 +               .platform_data = &backlight_machinfo,
8691 +       },
8692 +};
8693 +
8694 +static struct resource gta01_led_resources[] = {
8695 +       [0] = {
8696 +               .start  = GTA01_GPIO_VIBRATOR_ON,
8697 +               .end    = GTA01_GPIO_VIBRATOR_ON,
8698 +       },
8699 +};
8700 +
8701 +struct platform_device gta01_led_dev = {
8702 +       .name           = "neo1973-vibrator",
8703 +       .num_resources  = ARRAY_SIZE(gta01_led_resources),
8704 +       .resource       = gta01_led_resources,
8705 +};
8706 +
8707 +static struct resource gta01_button_resources[] = {
8708 +       [0] = {
8709 +               .start = GTA01_GPIO_AUX_KEY,
8710 +               .end   = GTA01_GPIO_AUX_KEY,
8711 +       },
8712 +       [1] = {
8713 +               .start = GTA01_GPIO_HOLD_KEY,
8714 +               .end   = GTA01_GPIO_HOLD_KEY,
8715 +       },
8716 +       [2] = {
8717 +               .start = GTA01_GPIO_JACK_INSERT,
8718 +               .end   = GTA01_GPIO_JACK_INSERT,
8719 +       },
8720 +       [3] = {
8721 +               .start = 0,
8722 +               .end   = 0,
8723 +       },
8724 +       [4] = {
8725 +               .start = 0,
8726 +               .end   = 0,
8727 +       },
8728 +};
8729 +
8730 +struct platform_device gta01_button_dev = {
8731 +       .name           = "neo1973-button",
8732 +       .num_resources  = ARRAY_SIZE(gta01_button_resources),
8733 +       .resource       = gta01_button_resources,
8734 +};
8735 +
8736 +static struct platform_device gta01_pm_gsm_dev = {
8737 +       .name           = "neo1973-pm-gsm",
8738 +};
8739 +
8740 +/* USB */
8741 +static struct s3c2410_hcd_info gta01_usb_info = {
8742 +       .port[0]        = {
8743 +               .flags  = S3C_HCDFLG_USED,
8744 +       },
8745 +       .port[1]        = {
8746 +               .flags  = 0,
8747 +       },
8748 +};
8749 +
8750 +static void __init gta01_map_io(void)
8751 +{
8752 +       s3c24xx_init_io(gta01_iodesc, ARRAY_SIZE(gta01_iodesc));
8753 +       s3c24xx_init_clocks(12*1000*1000);
8754 +       s3c24xx_init_uarts(gta01_uartcfgs, ARRAY_SIZE(gta01_uartcfgs));
8755 +}
8756 +
8757 +static irqreturn_t gta01_modem_irq(int irq, void *param)
8758 +{
8759 +       printk(KERN_DEBUG "GSM wakeup interrupt (IRQ %d)\n", irq);
8760 +       gta_gsm_interrupts++;
8761 +       return IRQ_HANDLED;
8762 +}
8763 +
8764 +static void __init gta01_machine_init(void)
8765 +{
8766 +       int rc;
8767 +
8768 +       if (system_rev == GTA01v4_SYSTEM_REV ||
8769 +           system_rev == GTA01Bv2_SYSTEM_REV ||
8770 +           system_rev == GTA01Bv3_SYSTEM_REV ||
8771 +           system_rev == GTA01Bv4_SYSTEM_REV) {
8772 +               gta01_udc_cfg.udc_command = gta01_udc_command;
8773 +               gta01_mmc_cfg.ocr_avail = MMC_VDD_32_33;
8774 +       }
8775 +
8776 +       s3c_device_usb.dev.platform_data = &gta01_usb_info;
8777 +       s3c_device_nand.dev.platform_data = &gta01_nand_info;
8778 +       s3c_device_sdi.dev.platform_data = &gta01_mmc_cfg;
8779 +
8780 +       s3c24xx_fb_set_platdata(&gta01_lcd_cfg);
8781 +
8782 +       INIT_WORK(&gta01_udc_vbus_drawer.work, __gta01_udc_vbus_draw);
8783 +       s3c24xx_udc_set_platdata(&gta01_udc_cfg);
8784 +       s3c_i2c0_set_platdata(NULL);
8785 +       set_s3c2410ts_info(&gta01_ts_cfg);
8786 +
8787 +       /* Set LCD_RESET / XRES to high */
8788 +       s3c2410_gpio_cfgpin(S3C2410_GPC6, S3C2410_GPIO_OUTPUT);
8789 +       s3c2410_gpio_setpin(S3C2410_GPC6, 1);
8790 +
8791 +       /* SPI chip select is gpio output */
8792 +       s3c2410_gpio_cfgpin(S3C2410_GPG3, S3C2410_GPIO_OUTPUT);
8793 +       s3c2410_gpio_setpin(S3C2410_GPG3, 1);
8794 +       platform_device_register(&s3c_device_spi_lcm);
8795 +
8796 +       platform_device_register(&gta01_bl_dev);
8797 +       platform_device_register(&gta01_button_dev);
8798 +       platform_device_register(&gta01_pm_gsm_dev);
8799 +
8800 +       switch (system_rev) {
8801 +       case GTA01v3_SYSTEM_REV:
8802 +       case GTA01v4_SYSTEM_REV:
8803 +               /* just use the default (GTA01_IRQ_PCF50606) */
8804 +               break;
8805 +       case GTA01Bv2_SYSTEM_REV:
8806 +       case GTA01Bv3_SYSTEM_REV:
8807 +               /* just use the default (GTA01_IRQ_PCF50606) */
8808 +               gta01_led_resources[0].start =
8809 +                       gta01_led_resources[0].end = GTA01Bv2_GPIO_VIBRATOR_ON;
8810 +               break;
8811 +       case GTA01Bv4_SYSTEM_REV:
8812 +               gta01_pmu_resources[0].start =
8813 +                       gta01_pmu_resources[0].end = GTA01Bv4_IRQ_PCF50606;
8814 +               gta01_led_resources[0].start =
8815 +                       gta01_led_resources[0].end = GTA01Bv4_GPIO_VIBRATOR_ON;
8816 +               break;
8817 +       }
8818 +       mangle_pmu_pdata_by_system_rev();
8819 +       platform_device_register(&gta01_pmu_dev);
8820 +       platform_device_register(&gta01_led_dev);
8821 +
8822 +       platform_add_devices(gta01_devices, ARRAY_SIZE(gta01_devices));
8823 +
8824 +       s3c2410_pm_init();
8825 +
8826 +       set_irq_type(GTA01_IRQ_MODEM, IRQ_TYPE_EDGE_RISING);
8827 +       rc = request_irq(GTA01_IRQ_MODEM, gta01_modem_irq, IRQF_DISABLED,
8828 +                        "modem", NULL);
8829 +       enable_irq_wake(GTA01_IRQ_MODEM);
8830 +       printk(KERN_DEBUG  "Enabled GSM wakeup IRQ %d (rc=%d)\n",
8831 +              GTA01_IRQ_MODEM, rc);
8832 +}
8833 +
8834 +MACHINE_START(NEO1973_GTA01, "GTA01")
8835 +       .phys_io        = S3C2410_PA_UART,
8836 +       .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
8837 +       .boot_params    = S3C2410_SDRAM_PA + 0x100,
8838 +       .map_io         = gta01_map_io,
8839 +       .init_irq       = s3c24xx_init_irq,
8840 +       .init_machine   = gta01_machine_init,
8841 +       .timer          = &s3c24xx_timer,
8842 +MACHINE_END
8843 --- a/arch/arm/mach-s3c2410/mach-h1940.c
8844 +++ b/arch/arm/mach-s3c2410/mach-h1940.c
8845 @@ -38,11 +38,13 @@
8846  #include <mach/h1940.h>
8847  #include <mach/h1940-latch.h>
8848  #include <mach/fb.h>
8849 -#include <asm/plat-s3c24xx/udc.h>
8850 +#include <plat/udc.h>
8851 +#include <plat/iic.h>
8852
8853  #include <plat/clock.h>
8854  #include <plat/devs.h>
8855  #include <plat/cpu.h>
8856 +#include <plat/pll.h>
8857  #include <plat/pm.h>
8858
8859  static struct map_desc h1940_iodesc[] __initdata = {
8860 @@ -129,6 +131,11 @@ static struct s3c2410_udc_mach_info h194
8861         .vbus_pin_inverted      = 1,
8862  };
8863
8864 +static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = {
8865 +               .delay = 10000,
8866 +               .presc = 49,
8867 +               .oversampling_shift = 2,
8868 +};
8869
8870  /**
8871   * Set lcd on or off
8872 @@ -183,9 +190,10 @@ static struct platform_device *h1940_dev
8873         &s3c_device_usb,
8874         &s3c_device_lcd,
8875         &s3c_device_wdt,
8876 -       &s3c_device_i2c,
8877 +       &s3c_device_i2c0,
8878         &s3c_device_iis,
8879         &s3c_device_usbgadget,
8880 +       &s3c_device_ts,
8881         &s3c_device_leds,
8882         &s3c_device_bluetooth,
8883  };
8884 @@ -201,7 +209,7 @@ static void __init h1940_map_io(void)
8885  #ifdef CONFIG_PM_H1940
8886         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
8887  #endif
8888 -       s3c2410_pm_init();
8889 +       s3c_pm_init();
8890  }
8891
8892  static void __init h1940_init_irq(void)
8893 @@ -214,7 +222,9 @@ static void __init h1940_init(void)
8894         u32 tmp;
8895
8896         s3c24xx_fb_set_platdata(&h1940_fb_info);
8897 +       set_s3c2410ts_info(&h1940_ts_cfg);
8898         s3c24xx_udc_set_platdata(&h1940_udc_cfg);
8899 +       s3c_i2c0_set_platdata(NULL);
8900
8901         /* Turn off suspend on both USB ports, and switch the
8902          * selectable USB port to USB device mode. */
8903 @@ -223,10 +233,9 @@ static void __init h1940_init(void)
8904                               S3C2410_MISCCR_USBSUSPND0 |
8905                               S3C2410_MISCCR_USBSUSPND1, 0x0);
8906
8907 -       tmp = (
8908 -                0x78 << S3C2410_PLLCON_MDIVSHIFT)
8909 -             | (0x02 << S3C2410_PLLCON_PDIVSHIFT)
8910 -             | (0x03 << S3C2410_PLLCON_SDIVSHIFT);
8911 +       tmp =   (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
8912 +             | (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
8913 +             | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
8914         writel(tmp, S3C2410_UPLLCON);
8915
8916         platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
8917 --- a/arch/arm/mach-s3c2410/mach-n30.c
8918 +++ b/arch/arm/mach-s3c2410/mach-n30.c
8919 @@ -40,14 +40,14 @@
8920  #include <asm/mach/irq.h>
8921  #include <asm/mach/map.h>
8922
8923 -#include <asm/plat-s3c/iic.h>
8924 +#include <plat/iic.h>
8925  #include <plat/regs-serial.h>
8926
8927  #include <plat/clock.h>
8928  #include <plat/cpu.h>
8929  #include <plat/devs.h>
8930  #include <plat/s3c2410.h>
8931 -#include <asm/plat-s3c24xx/udc.h>
8932 +#include <plat/udc.h>
8933
8934  static struct map_desc n30_iodesc[] __initdata = {
8935         /* nothing here yet */
8936 @@ -320,7 +320,7 @@ static struct s3c2410fb_mach_info n30_fb
8937  static struct platform_device *n30_devices[] __initdata = {
8938         &s3c_device_lcd,
8939         &s3c_device_wdt,
8940 -       &s3c_device_i2c,
8941 +       &s3c_device_i2c0,
8942         &s3c_device_iis,
8943         &s3c_device_usb,
8944         &s3c_device_usbgadget,
8945 @@ -332,7 +332,7 @@ static struct platform_device *n30_devic
8946  static struct platform_device *n35_devices[] __initdata = {
8947         &s3c_device_lcd,
8948         &s3c_device_wdt,
8949 -       &s3c_device_i2c,
8950 +       &s3c_device_i2c0,
8951         &s3c_device_iis,
8952         &s3c_device_usbgadget,
8953         &n35_button_device,
8954 @@ -501,7 +501,7 @@ static void __init n30_init_irq(void)
8955  static void __init n30_init(void)
8956  {
8957         s3c24xx_fb_set_platdata(&n30_fb_info);
8958 -       s3c_device_i2c.dev.platform_data = &n30_i2ccfg;
8959 +       s3c_device_i2c0.dev.platform_data = &n30_i2ccfg;
8960         s3c24xx_udc_set_platdata(&n30_udc_cfg);
8961
8962         /* Turn off suspend on both USB ports, and switch the
8963 --- a/arch/arm/mach-s3c2410/mach-otom.c
8964 +++ b/arch/arm/mach-s3c2410/mach-otom.c
8965 @@ -35,6 +35,7 @@
8966  #include <plat/s3c2410.h>
8967  #include <plat/clock.h>
8968  #include <plat/devs.h>
8969 +#include <plat/iic.h>
8970  #include <plat/cpu.h>
8971
8972  static struct map_desc otom11_iodesc[] __initdata = {
8973 @@ -94,7 +95,7 @@ static struct platform_device *otom11_de
8974         &s3c_device_usb,
8975         &s3c_device_lcd,
8976         &s3c_device_wdt,
8977 -       &s3c_device_i2c,
8978 +       &s3c_device_i2c0,
8979         &s3c_device_iis,
8980         &s3c_device_rtc,
8981         &otom_device_nor,
8982 @@ -109,6 +110,7 @@ static void __init otom11_map_io(void)
8983
8984  static void __init otom11_init(void)
8985  {
8986 +       s3c_i2c0_set_platdata(NULL);
8987         platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
8988  }
8989
8990 --- a/arch/arm/mach-s3c2410/mach-qt2410.c
8991 +++ b/arch/arm/mach-s3c2410/mach-qt2410.c
8992 @@ -1,6 +1,6 @@
8993  /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
8994   *
8995 - * Copyright (C) 2006 by OpenMoko, Inc.
8996 + * Copyright (C) 2006 by Openmoko, Inc.
8997   * Author: Harald Welte <laforge@openmoko.org>
8998   * All rights reserved.
8999   *
9000 @@ -50,10 +50,11 @@
9001  #include <mach/leds-gpio.h>
9002  #include <plat/regs-serial.h>
9003  #include <mach/fb.h>
9004 -#include <asm/plat-s3c/nand.h>
9005 -#include <asm/plat-s3c24xx/udc.h>
9006 +#include <plat/nand.h>
9007 +#include <plat/udc.h>
9008  #include <mach/spi.h>
9009  #include <mach/spi-gpio.h>
9010 +#include <plat/iic.h>
9011
9012  #include <plat/common-smdk.h>
9013  #include <plat/devs.h>
9014 @@ -213,7 +214,7 @@ static struct platform_device qt2410_led
9015
9016  /* SPI */
9017
9018 -static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
9019 +static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int csidx, int cs)
9020  {
9021         switch (cs) {
9022         case BITBANG_CS_ACTIVE:
9023 @@ -247,7 +248,7 @@ static struct platform_device *qt2410_de
9024         &s3c_device_usb,
9025         &s3c_device_lcd,
9026         &s3c_device_wdt,
9027 -       &s3c_device_i2c,
9028 +       &s3c_device_i2c0,
9029         &s3c_device_iis,
9030         &s3c_device_sdi,
9031         &s3c_device_usbgadget,
9032 @@ -320,6 +321,24 @@ static int __init qt2410_tft_setup(char
9033
9034  __setup("tft=", qt2410_tft_setup);
9035
9036 +static struct resource qt2410_button_resources[] = {
9037 +       [0] = {
9038 +               .start = S3C2410_GPF0,
9039 +               .end   = S3C2410_GPF0,
9040 +       },
9041 +       [1] = {
9042 +               .start = S3C2410_GPF2,
9043 +               .end   = S3C2410_GPF2,
9044 +       },
9045 +};
9046 +
9047 +struct platform_device qt2410_button_dev = {
9048 +       .name           ="qt2410-button",
9049 +       .num_resources  = ARRAY_SIZE(qt2410_button_resources),
9050 +       .resource       = qt2410_button_resources,
9051 +};
9052 +
9053 +
9054  static void __init qt2410_map_io(void)
9055  {
9056         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
9057 @@ -349,11 +368,12 @@ static void __init qt2410_machine_init(v
9058         s3c2410_gpio_setpin(S3C2410_GPB0, 1);
9059
9060         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
9061 +       s3c_i2c0_set_platdata(NULL);
9062
9063         s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
9064
9065         platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
9066 -       s3c2410_pm_init();
9067 +       s3c_pm_init();
9068  }
9069
9070  MACHINE_START(QT2410, "QT2410")
9071 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c
9072 +++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
9073 @@ -47,6 +47,7 @@
9074  #include <asm/mach-types.h>
9075
9076  #include <plat/regs-serial.h>
9077 +#include <plat/iic.h>
9078
9079  #include <plat/devs.h>
9080  #include <plat/cpu.h>
9081 @@ -89,7 +90,7 @@ static struct platform_device *smdk2410_
9082         &s3c_device_usb,
9083         &s3c_device_lcd,
9084         &s3c_device_wdt,
9085 -       &s3c_device_i2c,
9086 +       &s3c_device_i2c0,
9087         &s3c_device_iis,
9088  };
9089
9090 @@ -102,6 +103,7 @@ static void __init smdk2410_map_io(void)
9091
9092  static void __init smdk2410_init(void)
9093  {
9094 +       s3c_i2c0_set_platdata(NULL);
9095         platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices));
9096         smdk_machine_init();
9097  }
9098 --- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
9099 +++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
9100 @@ -45,6 +45,7 @@
9101  #include <asm/mach-types.h>
9102
9103  #include <plat/regs-serial.h>
9104 +#include <plat/iic.h>
9105  #include <plat/devs.h>
9106  #include <plat/cpu.h>
9107
9108 @@ -127,7 +128,7 @@ static struct s3c2410_uartcfg tct_hammer
9109  static struct platform_device *tct_hammer_devices[] __initdata = {
9110         &s3c_device_adc,
9111         &s3c_device_wdt,
9112 -       &s3c_device_i2c,
9113 +       &s3c_device_i2c0,
9114         &s3c_device_usb,
9115         &s3c_device_rtc,
9116         &s3c_device_usbgadget,
9117 @@ -146,6 +147,7 @@ static void __init tct_hammer_map_io(voi
9118
9119  static void __init tct_hammer_init(void)
9120  {
9121 +       s3c_i2c0_set_platdata(NULL);
9122         platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
9123  }
9124
9125 --- a/arch/arm/mach-s3c2410/mach-vr1000.c
9126 +++ b/arch/arm/mach-s3c2410/mach-vr1000.c
9127 @@ -47,6 +47,7 @@
9128  #include <plat/clock.h>
9129  #include <plat/devs.h>
9130  #include <plat/cpu.h>
9131 +#include <plat/iic.h>
9132
9133  #include "usb-simtec.h"
9134  #include "nor-simtec.h"
9135 @@ -334,7 +335,7 @@ static struct platform_device *vr1000_de
9136         &s3c_device_usb,
9137         &s3c_device_lcd,
9138         &s3c_device_wdt,
9139 -       &s3c_device_i2c,
9140 +       &s3c_device_i2c0,
9141         &s3c_device_adc,
9142         &serial_device,
9143         &vr1000_dm9k0,
9144 @@ -384,6 +385,7 @@ static void __init vr1000_map_io(void)
9145
9146  static void __init vr1000_init(void)
9147  {
9148 +       s3c_i2c0_set_platdata(NULL);
9149         platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
9150
9151         i2c_register_board_info(0, vr1000_i2c_devs,
9152 --- a/arch/arm/mach-s3c2410/Makefile
9153 +++ b/arch/arm/mach-s3c2410/Makefile
9154 @@ -15,7 +15,8 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
9155  obj-$(CONFIG_CPU_S3C2410_DMA)  += dma.o
9156  obj-$(CONFIG_S3C2410_PM)       += pm.o sleep.o
9157  obj-$(CONFIG_S3C2410_GPIO)     += gpio.o
9158 -obj-$(CONFIG_S3C2410_CLOCK)    += clock.o
9159 +#obj-$(CONFIG_S3C2410_CLOCK)   += clock.o
9160 +obj-$(CONFIG_S3C2410_PWM)      += pwm.o
9161
9162  # Machine support
9163
9164 @@ -38,3 +39,5 @@ obj-$(CONFIG_SIMTEC_NOR)      += nor-simtec.o
9165  # machine additions
9166
9167  obj-$(CONFIG_MACH_BAST_IDE)    += bast-ide.o
9168 +obj-$(CONFIG_MACH_NEO1973_GTA01)+= mach-gta01.o
9169 +
9170 --- a/arch/arm/mach-s3c2410/pm.c
9171 +++ b/arch/arm/mach-s3c2410/pm.c
9172 @@ -37,21 +37,14 @@
9173  #include <plat/cpu.h>
9174  #include <plat/pm.h>
9175
9176 -#ifdef CONFIG_S3C2410_PM_DEBUG
9177 -extern void pm_dbg(const char *fmt, ...);
9178 -#define DBG(fmt...) pm_dbg(fmt)
9179 -#else
9180 -#define DBG(fmt...) printk(KERN_DEBUG fmt)
9181 -#endif
9182 -
9183  static void s3c2410_pm_prepare(void)
9184  {
9185         /* ensure at least GSTATUS3 has the resume address */
9186
9187 -       __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
9188 +       __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
9189
9190 -       DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
9191 -       DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
9192 +       S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
9193 +       S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
9194
9195         if (machine_is_h1940()) {
9196                 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
9197 --- /dev/null
9198 +++ b/arch/arm/mach-s3c2410/pwm.c
9199 @@ -0,0 +1,288 @@
9200 +/*
9201 + * arch/arm/mach-s3c2410/3c2410-pwm.c
9202 + *
9203 + * Copyright (c) by Javi Roman <javiroman@kernel-labs.org>
9204 + *              for the Openmoko Project.
9205 + *
9206 + *     S3C2410A SoC PWM support
9207 + *
9208 + * This program is free software; you can redistribute it and/or modify
9209 + * it under the terms of the GNU General Public License as published by
9210 + * the Free Software Foundation; either version 2 of the License, or
9211 + * (at your option) any later version.
9212 + *
9213 + * You should have received a copy of the GNU General Public License
9214 + * along with this program; if not, write to the Free Software
9215 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
9216 + *
9217 + */
9218 +
9219 +#include <linux/kernel.h>
9220 +#include <linux/init.h>
9221 +#include <linux/clk.h>
9222 +#include <linux/device.h>
9223 +#include <mach/hardware.h>
9224 +#include <plat/regs-timer.h>
9225 +#include <mach/pwm.h>
9226 +#include <asm/io.h>
9227 +
9228 +#ifdef CONFIG_PM
9229 +       static unsigned long standby_reg_tcon;
9230 +       static unsigned long standby_reg_tcfg0;
9231 +       static unsigned long standby_reg_tcfg1;
9232 +#endif
9233 +
9234 +int s3c2410_pwm_disable(struct s3c2410_pwm *pwm)
9235 +{
9236 +       unsigned long tcon;
9237 +
9238 +       /* stop timer */
9239 +       tcon = __raw_readl(S3C2410_TCON);
9240 +       tcon &= 0xffffff00;
9241 +       __raw_writel(tcon, S3C2410_TCON);
9242 +
9243 +       clk_disable(pwm->pclk);
9244 +       clk_put(pwm->pclk);
9245 +
9246 +       return 0;
9247 +}
9248 +EXPORT_SYMBOL_GPL(s3c2410_pwm_disable);
9249 +
9250 +int s3c2410_pwm_init(struct s3c2410_pwm *pwm)
9251 +{
9252 +       pwm->pclk = clk_get(NULL, "timers");
9253 +       if (IS_ERR(pwm->pclk))
9254 +               return PTR_ERR(pwm->pclk);
9255 +
9256 +       clk_enable(pwm->pclk);
9257 +       pwm->pclk_rate = clk_get_rate(pwm->pclk);
9258 +       return 0;
9259 +}
9260 +EXPORT_SYMBOL_GPL(s3c2410_pwm_init);
9261 +
9262 +int s3c2410_pwm_enable(struct s3c2410_pwm *pwm)
9263 +{
9264 +       unsigned long tcfg0, tcfg1, tcnt, tcmp;
9265 +
9266 +       /* control registers bits */
9267 +       tcfg1 = __raw_readl(S3C2410_TCFG1);
9268 +       tcfg0 = __raw_readl(S3C2410_TCFG0);
9269 +
9270 +       /* divider & scaler slection */
9271 +       switch (pwm->timerid) {
9272 +       case PWM0:
9273 +               tcfg1 &= ~S3C2410_TCFG1_MUX0_MASK;
9274 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
9275 +               break;
9276 +       case PWM1:
9277 +               tcfg1 &= ~S3C2410_TCFG1_MUX1_MASK;
9278 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
9279 +               break;
9280 +       case PWM2:
9281 +               tcfg1 &= ~S3C2410_TCFG1_MUX2_MASK;
9282 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
9283 +               break;
9284 +       case PWM3:
9285 +               tcfg1 &= ~S3C2410_TCFG1_MUX3_MASK;
9286 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
9287 +               break;
9288 +       case PWM4:
9289 +               /* timer four is not capable of doing PWM */
9290 +               break;
9291 +       default:
9292 +               clk_disable(pwm->pclk);
9293 +               clk_put(pwm->pclk);
9294 +               return -1;
9295 +       }
9296 +
9297 +       /* divider & scaler values */
9298 +       tcfg1 |= pwm->divider;
9299 +       __raw_writel(tcfg1, S3C2410_TCFG1);
9300 +
9301 +       switch (pwm->timerid) {
9302 +       case PWM0:
9303 +       case PWM1:
9304 +               tcfg0 |= pwm->prescaler;
9305 +               __raw_writel(tcfg0, S3C2410_TCFG0);
9306 +               break;
9307 +       default:
9308 +               if ((tcfg0 | pwm->prescaler) != tcfg0) {
9309 +                       printk(KERN_WARNING "not changing prescaler of PWM %u,"
9310 +                              " since it's shared with timer4 (clock tick)\n",
9311 +                              pwm->timerid);
9312 +               }
9313 +               break;
9314 +       }
9315 +
9316 +       /* timer count and compare buffer initial values */
9317 +       tcnt = pwm->counter;
9318 +       tcmp = pwm->comparer;
9319 +
9320 +       __raw_writel(tcnt, S3C2410_TCNTB(pwm->timerid));
9321 +       __raw_writel(tcmp, S3C2410_TCMPB(pwm->timerid));
9322 +
9323 +       /* ensure timer is stopped */
9324 +       s3c2410_pwm_stop(pwm);
9325 +
9326 +       return 0;
9327 +}
9328 +EXPORT_SYMBOL_GPL(s3c2410_pwm_enable);
9329 +
9330 +int s3c2410_pwm_start(struct s3c2410_pwm *pwm)
9331 +{
9332 +       unsigned long tcon;
9333 +
9334 +       tcon = __raw_readl(S3C2410_TCON);
9335 +
9336 +       switch (pwm->timerid) {
9337 +       case PWM0:
9338 +               tcon |= S3C2410_TCON_T0START;
9339 +               tcon &= ~S3C2410_TCON_T0MANUALUPD;
9340 +               break;
9341 +       case PWM1:
9342 +               tcon |= S3C2410_TCON_T1START;
9343 +               tcon &= ~S3C2410_TCON_T1MANUALUPD;
9344 +               break;
9345 +       case PWM2:
9346 +               tcon |= S3C2410_TCON_T2START;
9347 +               tcon &= ~S3C2410_TCON_T2MANUALUPD;
9348 +               break;
9349 +       case PWM3:
9350 +               tcon |= S3C2410_TCON_T3START;
9351 +               tcon &= ~S3C2410_TCON_T3MANUALUPD;
9352 +               break;
9353 +       case PWM4:
9354 +               /* timer four is not capable of doing PWM */
9355 +       default:
9356 +               return -ENODEV;
9357 +       }
9358 +
9359 +       __raw_writel(tcon, S3C2410_TCON);
9360 +
9361 +       return 0;
9362 +}
9363 +EXPORT_SYMBOL_GPL(s3c2410_pwm_start);
9364 +
9365 +int s3c2410_pwm_stop(struct s3c2410_pwm *pwm)
9366 +{
9367 +       unsigned long tcon;
9368 +
9369 +       tcon = __raw_readl(S3C2410_TCON);
9370 +
9371 +       switch (pwm->timerid) {
9372 +       case PWM0:
9373 +               tcon &= ~0x00000000;
9374 +               tcon |= S3C2410_TCON_T0RELOAD;
9375 +               tcon |= S3C2410_TCON_T0MANUALUPD;
9376 +               break;
9377 +       case PWM1:
9378 +               tcon &= ~0x00000080;
9379 +               tcon |= S3C2410_TCON_T1RELOAD;
9380 +               tcon |= S3C2410_TCON_T1MANUALUPD;
9381 +               break;
9382 +       case PWM2:
9383 +               tcon &= ~0x00000800;
9384 +               tcon |= S3C2410_TCON_T2RELOAD;
9385 +               tcon |= S3C2410_TCON_T2MANUALUPD;
9386 +               break;
9387 +       case PWM3:
9388 +               tcon &= ~0x00008000;
9389 +               tcon |= S3C2410_TCON_T3RELOAD;
9390 +               tcon |= S3C2410_TCON_T3MANUALUPD;
9391 +               break;
9392 +       case PWM4:
9393 +               /* timer four is not capable of doing PWM */
9394 +       default:
9395 +               return -ENODEV;
9396 +       }
9397 +
9398 +       __raw_writel(tcon, S3C2410_TCON);
9399 +
9400 +       return 0;
9401 +}
9402 +EXPORT_SYMBOL_GPL(s3c2410_pwm_stop);
9403 +
9404 +int s3c2410_pwm_duty_cycle(int reg_value, struct s3c2410_pwm *pwm)
9405 +{
9406 +       __raw_writel(reg_value, S3C2410_TCMPB(pwm->timerid));
9407 +
9408 +       return 0;
9409 +}
9410 +EXPORT_SYMBOL_GPL(s3c2410_pwm_duty_cycle);
9411 +
9412 +int s3c2410_pwm_dumpregs(void)
9413 +{
9414 +       printk(KERN_INFO "TCON: %08lx, TCFG0: %08lx, TCFG1: %08lx\n",
9415 +                       (unsigned long) __raw_readl(S3C2410_TCON),
9416 +                       (unsigned long) __raw_readl(S3C2410_TCFG0),
9417 +                       (unsigned long) __raw_readl(S3C2410_TCFG1));
9418 +
9419 +       return 0;
9420 +}
9421 +EXPORT_SYMBOL_GPL(s3c2410_pwm_dumpregs);
9422 +
9423 +static int __init s3c24xx_pwm_probe(struct platform_device *pdev)
9424 +{
9425 +       struct s3c24xx_pwm_platform_data *pdata = pdev->dev.platform_data;
9426 +
9427 +       dev_info(&pdev->dev, "s3c24xx_pwm is registered \n");
9428 +
9429 +       /* if platform was interested, give him a chance to register
9430 +        * platform devices that switch power with us as the parent
9431 +        * at registration time -- ensures suspend / resume ordering
9432 +        */
9433 +       if (pdata)
9434 +               if (pdata->attach_child_devices)
9435 +                       (pdata->attach_child_devices)(&pdev->dev);
9436 +
9437 +       return 0;
9438 +}
9439 +
9440 +#ifdef CONFIG_PM
9441 +static int s3c24xx_pwm_suspend(struct platform_device *pdev, pm_message_t state)
9442 +{
9443 +       /* PWM config should be kept in suspending */
9444 +       standby_reg_tcon = __raw_readl(S3C2410_TCON);
9445 +       standby_reg_tcfg0 = __raw_readl(S3C2410_TCFG0);
9446 +       standby_reg_tcfg1 = __raw_readl(S3C2410_TCFG1);
9447 +
9448 +       return 0;
9449 +}
9450 +
9451 +static int s3c24xx_pwm_resume(struct platform_device *pdev)
9452 +{
9453 +       __raw_writel(standby_reg_tcon, S3C2410_TCON);
9454 +       __raw_writel(standby_reg_tcfg0, S3C2410_TCFG0);
9455 +       __raw_writel(standby_reg_tcfg1, S3C2410_TCFG1);
9456 +
9457 +       return 0;
9458 +}
9459 +#else
9460 +#define sc32440_pwm_suspend    NULL
9461 +#define sc32440_pwm_resume     NULL
9462 +#endif
9463 +
9464 +static struct platform_driver s3c24xx_pwm_driver = {
9465 +       .driver = {
9466 +               .name   = "s3c24xx_pwm",
9467 +               .owner  = THIS_MODULE,
9468 +       },
9469 +       .probe   = s3c24xx_pwm_probe,
9470 +       .suspend = s3c24xx_pwm_suspend,
9471 +       .resume  = s3c24xx_pwm_resume,
9472 +};
9473 +
9474 +static int __init s3c24xx_pwm_init(void)
9475 +{
9476 +       return platform_driver_register(&s3c24xx_pwm_driver);
9477 +}
9478 +
9479 +static void __exit s3c24xx_pwm_exit(void)
9480 +{
9481 +}
9482 +
9483 +MODULE_AUTHOR("Javi Roman <javiroman@kernel-labs.org>");
9484 +MODULE_LICENSE("GPL");
9485 +
9486 +module_init(s3c24xx_pwm_init);
9487 +module_exit(s3c24xx_pwm_exit);
9488 --- a/arch/arm/mach-s3c2410/s3c2410.c
9489 +++ b/arch/arm/mach-s3c2410/s3c2410.c
9490 @@ -16,6 +16,7 @@
9491  #include <linux/list.h>
9492  #include <linux/timer.h>
9493  #include <linux/init.h>
9494 +#include <linux/clk.h>
9495  #include <linux/sysdev.h>
9496  #include <linux/serial_core.h>
9497  #include <linux/platform_device.h>
9498 @@ -28,6 +29,8 @@
9499  #include <mach/hardware.h>
9500  #include <asm/irq.h>
9501
9502 +#include <plat/cpu-freq.h>
9503 +
9504  #include <mach/regs-clock.h>
9505  #include <plat/regs-serial.h>
9506
9507 @@ -35,6 +38,7 @@
9508  #include <plat/cpu.h>
9509  #include <plat/devs.h>
9510  #include <plat/clock.h>
9511 +#include <plat/pll.h>
9512
9513  /* Initial IO mappings */
9514
9515 @@ -59,25 +63,28 @@ void __init s3c2410_init_uarts(struct s3
9516   * machine specific initialisation.
9517  */
9518
9519 -void __init s3c2410_map_io(struct map_desc *mach_desc, int mach_size)
9520 +void __init s3c2410_map_io(void)
9521  {
9522 -       /* register our io-tables */
9523 -
9524         iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
9525 -       iotable_init(mach_desc, mach_size);
9526  }
9527
9528 -void __init s3c2410_init_clocks(int xtal)
9529 +void __init_or_cpufreq s3c2410_setup_clocks(void)
9530  {
9531 +       struct clk *xtal_clk;
9532         unsigned long tmp;
9533 +       unsigned long xtal;
9534         unsigned long fclk;
9535         unsigned long hclk;
9536         unsigned long pclk;
9537
9538 +       xtal_clk = clk_get(NULL, "xtal");
9539 +       xtal = clk_get_rate(xtal_clk);
9540 +       clk_put(xtal_clk);
9541 +
9542         /* now we've got our machine bits initialised, work out what
9543          * clocks we've got */
9544
9545 -       fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
9546 +       fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
9547
9548         tmp = __raw_readl(S3C2410_CLKDIVN);
9549
9550 @@ -95,7 +102,13 @@ void __init s3c2410_init_clocks(int xtal
9551          * console to use them
9552          */
9553
9554 -       s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
9555 +       s3c24xx_setup_clocks(fclk, hclk, pclk);
9556 +}
9557 +
9558 +void __init s3c2410_init_clocks(int xtal)
9559 +{
9560 +       s3c24xx_register_baseclocks(xtal);
9561 +       s3c2410_setup_clocks();
9562         s3c2410_baseclk_add();
9563  }
9564
9565 --- a/arch/arm/mach-s3c2412/clock.c
9566 +++ b/arch/arm/mach-s3c2412/clock.c
9567 @@ -93,12 +93,6 @@ static int s3c2412_upll_enable(struct cl
9568
9569  /* clock selections */
9570
9571 -/* CPU EXTCLK input */
9572 -static struct clk clk_ext = {
9573 -       .name           = "extclk",
9574 -       .id             = -1,
9575 -};
9576 -
9577  static struct clk clk_erefclk = {
9578         .name           = "erefclk",
9579         .id             = -1,
9580 @@ -773,5 +767,6 @@ int __init s3c2412_baseclk_add(void)
9581                 s3c2412_clkcon_enable(clkp, 0);
9582         }
9583
9584 +       s3c_pwmclk_init();
9585         return 0;
9586  }
9587 --- a/arch/arm/mach-s3c2412/dma.c
9588 +++ b/arch/arm/mach-s3c2412/dma.c
9589 @@ -26,13 +26,13 @@
9590
9591  #include <plat/regs-serial.h>
9592  #include <mach/regs-gpio.h>
9593 -#include <asm/plat-s3c/regs-ac97.h>
9594 +#include <plat/regs-ac97.h>
9595  #include <mach/regs-mem.h>
9596  #include <mach/regs-lcd.h>
9597  #include <mach/regs-sdi.h>
9598  #include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
9599  #include <asm/plat-s3c24xx/regs-iis.h>
9600 -#include <asm/plat-s3c24xx/regs-spi.h>
9601 +#include <plat/regs-spi.h>
9602
9603  #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
9604
9605 --- a/arch/arm/mach-s3c2412/mach-jive.c
9606 +++ b/arch/arm/mach-s3c2412/mach-jive.c
9607 @@ -31,8 +31,8 @@
9608  #include <asm/mach/irq.h>
9609
9610  #include <plat/regs-serial.h>
9611 -#include <asm/plat-s3c/nand.h>
9612 -#include <asm/plat-s3c/iic.h>
9613 +#include <plat/nand.h>
9614 +#include <plat/iic.h>
9615
9616  #include <mach/regs-power.h>
9617  #include <mach/regs-gpio.h>
9618 @@ -52,7 +52,8 @@
9619  #include <plat/devs.h>
9620  #include <plat/cpu.h>
9621  #include <plat/pm.h>
9622 -#include <asm/plat-s3c24xx/udc.h>
9623 +#include <plat/udc.h>
9624 +#include <plat/iic.h>
9625
9626  static struct map_desc jive_iodesc[] __initdata = {
9627  };
9628 @@ -450,14 +451,14 @@ static struct spi_board_info __initdata
9629
9630  /* I2C bus and device configuration. */
9631
9632 -static struct s3c2410_platform_i2c jive_i2c_cfg = {
9633 +static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
9634         .max_freq       = 80 * 1000,
9635         .bus_freq       = 50 * 1000,
9636         .flags          = S3C_IICFLG_FILTER,
9637         .sda_delay      = 2,
9638  };
9639
9640 -static struct i2c_board_info jive_i2c_devs[] = {
9641 +static struct i2c_board_info jive_i2c_devs[] __initdata = {
9642         [0] = {
9643                 I2C_BOARD_INFO("lis302dl", 0x1c),
9644                 .irq    = IRQ_EINT14,
9645 @@ -470,7 +471,7 @@ static struct platform_device *jive_devi
9646         &s3c_device_usb,
9647         &s3c_device_rtc,
9648         &s3c_device_wdt,
9649 -       &s3c_device_i2c,
9650 +       &s3c_device_i2c0,
9651         &s3c_device_lcd,
9652         &jive_device_lcdspi,
9653         &jive_device_wm8750,
9654 @@ -492,7 +493,7 @@ static int jive_pm_suspend(struct sys_de
9655          * correct address to resume from. */
9656
9657         __raw_writel(0x2BED, S3C2412_INFORM0);
9658 -       __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
9659 +       __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
9660
9661         return 0;
9662  }
9663 @@ -628,7 +629,7 @@ static void __init jive_machine_init(voi
9664
9665         /* initialise the power management now we've setup everything. */
9666
9667 -       s3c2410_pm_init();
9668 +       s3c_pm_init();
9669
9670         s3c_device_nand.dev.platform_data = &jive_nand_info;
9671
9672 @@ -663,7 +664,7 @@ static void __init jive_machine_init(voi
9673
9674         spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
9675
9676 -       s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
9677 +       s3c_i2c0_set_platdata(&jive_i2c_cfg);
9678         i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
9679
9680         pm_power_off = jive_power_off;
9681 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c
9682 +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
9683 @@ -37,7 +37,8 @@
9684  #include <mach/regs-lcd.h>
9685
9686  #include <mach/idle.h>
9687 -#include <asm/plat-s3c24xx/udc.h>
9688 +#include <plat/udc.h>
9689 +#include <plat/iic.h>
9690  #include <mach/fb.h>
9691
9692  #include <plat/s3c2410.h>
9693 @@ -105,7 +106,7 @@ static struct platform_device *smdk2413_
9694         &s3c_device_usb,
9695         //&s3c_device_lcd,
9696         &s3c_device_wdt,
9697 -       &s3c_device_i2c,
9698 +       &s3c_device_i2c0,
9699         &s3c_device_iis,
9700         &s3c_device_usbgadget,
9701  };
9702 @@ -142,6 +143,7 @@ static void __init smdk2413_machine_init
9703
9704
9705         s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
9706 +       s3c_i2c0_set_platdata(NULL);
9707
9708         platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
9709         smdk_machine_init();
9710 --- a/arch/arm/mach-s3c2412/mach-vstms.c
9711 +++ b/arch/arm/mach-s3c2412/mach-vstms.c
9712 @@ -39,7 +39,8 @@
9713  #include <mach/idle.h>
9714  #include <mach/fb.h>
9715
9716 -#include <asm/plat-s3c/nand.h>
9717 +#include <plat/iic.h>
9718 +#include <plat/nand.h>
9719
9720  #include <plat/s3c2410.h>
9721  #include <plat/s3c2412.h>
9722 @@ -122,7 +123,7 @@ static struct s3c2410_platform_nand vstm
9723  static struct platform_device *vstms_devices[] __initdata = {
9724         &s3c_device_usb,
9725         &s3c_device_wdt,
9726 -       &s3c_device_i2c,
9727 +       &s3c_device_i2c0,
9728         &s3c_device_iis,
9729         &s3c_device_rtc,
9730         &s3c_device_nand,
9731 @@ -151,6 +152,7 @@ static void __init vstms_map_io(void)
9732
9733  static void __init vstms_init(void)
9734  {
9735 +       s3c_i2c0_set_platdata(NULL);
9736         platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
9737  }
9738
9739 --- a/arch/arm/mach-s3c2412/pm.c
9740 +++ b/arch/arm/mach-s3c2412/pm.c
9741 @@ -85,7 +85,7 @@ static struct sleep_save s3c2412_sleep[]
9742
9743  static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state)
9744  {
9745 -       s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
9746 +       s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
9747         return 0;
9748  }
9749
9750 @@ -98,7 +98,7 @@ static int s3c2412_pm_resume(struct sys_
9751         tmp |=  S3C2412_PWRCFG_STANDBYWFI_IDLE;
9752         __raw_writel(tmp, S3C2412_PWRCFG);
9753
9754 -       s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
9755 +       s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
9756         return 0;
9757  }
9758
9759 --- a/arch/arm/mach-s3c2412/s3c2412.c
9760 +++ b/arch/arm/mach-s3c2412/s3c2412.c
9761 @@ -16,6 +16,7 @@
9762  #include <linux/list.h>
9763  #include <linux/timer.h>
9764  #include <linux/init.h>
9765 +#include <linux/clk.h>
9766  #include <linux/delay.h>
9767  #include <linux/sysdev.h>
9768  #include <linux/serial_core.h>
9769 @@ -33,13 +34,15 @@
9770  #include <mach/reset.h>
9771  #include <mach/idle.h>
9772
9773 +#include <plat/cpu-freq.h>
9774 +
9775  #include <mach/regs-clock.h>
9776  #include <plat/regs-serial.h>
9777  #include <mach/regs-power.h>
9778  #include <mach/regs-gpio.h>
9779  #include <mach/regs-gpioj.h>
9780  #include <mach/regs-dsc.h>
9781 -#include <asm/plat-s3c24xx/regs-spi.h>
9782 +#include <plat/regs-spi.h>
9783  #include <mach/regs-s3c2412.h>
9784
9785  #include <plat/s3c2412.h>
9786 @@ -47,6 +50,7 @@
9787  #include <plat/devs.h>
9788  #include <plat/clock.h>
9789  #include <plat/pm.h>
9790 +#include <plat/pll.h>
9791
9792  #ifndef CONFIG_CPU_S3C2412_ONLY
9793  void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
9794 @@ -136,7 +140,7 @@ static void s3c2412_hard_reset(void)
9795   * machine specific initialisation.
9796  */
9797
9798 -void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
9799 +void __init s3c2412_map_io(void)
9800  {
9801         /* move base of IO */
9802
9803 @@ -153,20 +157,25 @@ void __init s3c2412_map_io(struct map_de
9804         /* register our io-tables */
9805
9806         iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
9807 -       iotable_init(mach_desc, mach_size);
9808  }
9809
9810 -void __init s3c2412_init_clocks(int xtal)
9811 +void __init_or_cpufreq s3c2412_setup_clocks(void)
9812  {
9813 +       struct clk *xtal_clk;
9814         unsigned long tmp;
9815 +       unsigned long xtal;
9816         unsigned long fclk;
9817         unsigned long hclk;
9818         unsigned long pclk;
9819
9820 +       xtal_clk = clk_get(NULL, "xtal");
9821 +       xtal = clk_get_rate(xtal_clk);
9822 +       clk_put(xtal_clk);
9823 +
9824         /* now we've got our machine bits initialised, work out what
9825          * clocks we've got */
9826
9827 -       fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
9828 +       fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
9829
9830         clk_mpll.rate = fclk;
9831
9832 @@ -183,11 +192,17 @@ void __init s3c2412_init_clocks(int xtal
9833         printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
9834                print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
9835
9836 +       s3c24xx_setup_clocks(fclk, hclk, pclk);
9837 +}
9838 +
9839 +void __init s3c2412_init_clocks(int xtal)
9840 +{
9841         /* initialise the clocks here, to allow other things like the
9842          * console to use them
9843          */
9844
9845 -       s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
9846 +       s3c24xx_register_baseclocks(xtal);
9847 +       s3c2412_setup_clocks();
9848         s3c2412_baseclk_add();
9849  }
9850
9851 @@ -216,5 +231,8 @@ int __init s3c2412_init(void)
9852  {
9853         printk("S3C2412: Initialising architecture\n");
9854
9855 +       /* make sure SD/MMC driver can distinguish 2412 from 2410 */
9856 +       s3c_device_sdi.name = "s3c2412-sdi";
9857 +
9858         return sysdev_register(&s3c2412_sysdev);
9859  }
9860 --- /dev/null
9861 +++ b/arch/arm/mach-s3c2440/camera/bits.h
9862 @@ -0,0 +1,48 @@
9863 +/*
9864 + *  Copyright (C) Samsung Electroincs  2003
9865 + *  Author: SW.LEE <hitchcar@samsung.com>
9866 + *
9867 + * This program is free software; you can redistribute it and/or modify
9868 + * it under the terms of the GNU General Public License as published by
9869 + * the Free Software Foundation; either version 2 of the License, or
9870 + * (at your option) any later version.
9871 + *
9872 + */
9873 +
9874 +#ifndef __SW_BITS_H
9875 +#define __SW_BITS_H
9876 +
9877 +#define BIT0                            0x00000001
9878 +#define BIT1                            0x00000002
9879 +#define BIT2                            0x00000004
9880 +#define BIT3                            0x00000008
9881 +#define BIT4                            0x00000010
9882 +#define BIT5                            0x00000020
9883 +#define BIT6                            0x00000040
9884 +#define BIT7                            0x00000080
9885 +#define BIT8                            0x00000100
9886 +#define BIT9                            0x00000200
9887 +#define BIT10                           0x00000400
9888 +#define BIT11                           0x00000800
9889 +#define BIT12                           0x00001000
9890 +#define BIT13                           0x00002000
9891 +#define BIT14                           0x00004000
9892 +#define BIT15                           0x00008000
9893 +#define BIT16                           0x00010000
9894 +#define BIT17                           0x00020000
9895 +#define BIT18                           0x00040000
9896 +#define BIT19                           0x00080000
9897 +#define BIT20                           0x00100000
9898 +#define BIT21                           0x00200000
9899 +#define BIT22                           0x00400000
9900 +#define BIT23                           0x00800000
9901 +#define BIT24                           0x01000000
9902 +#define BIT25                           0x02000000
9903 +#define BIT26                           0x04000000
9904 +#define BIT27                           0x08000000
9905 +#define BIT28                           0x10000000
9906 +#define BIT29                           0x20000000
9907 +#define BIT30                           0x40000000
9908 +#define BIT31                           0x80000000
9909 +
9910 +#endif
9911 --- /dev/null
9912 +++ b/arch/arm/mach-s3c2440/camera/camif.c
9913 @@ -0,0 +1,1047 @@
9914 +/*
9915 + *   Copyright (C) 2004 Samsung Electronics
9916 + *       SW.LEE <hitchcar@samsung.com>
9917 + *
9918 + * This file is subject to the terms and conditions of the GNU General Public
9919 + * License 2. See the file COPYING in the main directory of this archive
9920 + * for more details.
9921 + */
9922 +
9923 +#include <linux/module.h>
9924 +#include <linux/kernel.h>
9925 +#include <linux/init.h>
9926 +#include <linux/sched.h>
9927 +#include <linux/irq.h>
9928 +#include <linux/completion.h>
9929 +#include <linux/delay.h>
9930 +#include <linux/slab.h>
9931 +#include <linux/vmalloc.h>
9932 +#include <linux/miscdevice.h>
9933 +#include <linux/wait.h>
9934 +#include <linux/miscdevice.h>
9935 +#include <asm/io.h>
9936 +#include <asm/semaphore.h>
9937 +#include <asm/hardware.h>
9938 +#include <asm/uaccess.h>
9939 +#include <linux/device.h>
9940 +#include <linux/dma-mapping.h>
9941 +#include <linux/clk.h>
9942 +
9943 +#ifdef CONFIG_ARCH_S3C24A0A
9944 +#include <asm/arch/S3C24A0.h>
9945 +#include <asm/arch/clocks.h>
9946 +#else
9947 +#include <asm/arch/regs-gpio.h>
9948 +#include <asm/arch/regs-gpioj.h>
9949 +#include <asm/arch/regs-irq.h>
9950 +#endif
9951 +
9952 +#include "cam_reg.h"
9953 +//#define SW_DEBUG
9954 +#define CONFIG_VIDEO_V4L1_COMPAT
9955 +#include <linux/videodev.h>
9956 +#include "camif.h"
9957 +#include "miscdevice.h"
9958 +
9959 +static int camif_dma_burst(camif_cfg_t *);
9960 +static int camif_scaler(camif_cfg_t *);
9961 +
9962 +/* For SXGA Image */
9963 +#define RESERVE_MEM  15*1024*1024
9964 +#define YUV_MEM      10*1024*1024
9965 +#define RGB_MEM      (RESERVE_MEM - YUV_MEM)
9966 +
9967 +static int camif_malloc(camif_cfg_t *cfg)
9968 +{
9969 +       unsigned int t_size;
9970 +       unsigned int daon = cfg->target_x *cfg->target_y;
9971 +
9972 +       if(cfg->dma_type & CAMIF_CODEC) {
9973 +               if (cfg->fmt & CAMIF_OUT_YCBCR420) {
9974 +                       t_size = daon * 3 / 2 ;
9975 +               }
9976 +               else  { t_size = daon * 2; /* CAMIF_OUT_YCBCR422 */ }
9977 +               t_size = t_size *cfg->pp_num;
9978 +
9979 +#ifndef SAMSUNG_SXGA_CAM
9980 +               cfg->pp_virt_buf = dma_alloc_coherent(cfg->v->dev,
9981 +                                                     t_size, &cfg->pp_phys_buf,
9982 +                                                     GFP_KERNEL);
9983 +#else
9984 +               printk(KERN_INFO "Reserving High RAM Addresses \n");
9985 +               cfg->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVE_MEM);
9986 +               cfg->pp_virt_buf = ioremap_nocache(cfg->pp_phys_buf, YUV_MEM);
9987 +#endif
9988 +
9989 +               if ( !cfg->pp_virt_buf ) {
9990 +                       printk(KERN_ERR"CAMERA:Failed to request YCBCR MEM\n");
9991 +                       return -ENOMEM;
9992 +               }
9993 +               memset(cfg->pp_virt_buf, 0, t_size);
9994 +               cfg->pp_totalsize = t_size;
9995 +               return 0;
9996 +       }
9997 +       if ( cfg->dma_type & CAMIF_PREVIEW ) {
9998 +               if (cfg->fmt & CAMIF_RGB16)
9999 +                       t_size = daon * 2; /*  4byte per two pixel*/
10000 +               else {
10001 +                       assert(cfg->fmt & CAMIF_RGB24);
10002 +                       t_size = daon * 4; /* 4byte per one pixel */
10003 +               }
10004 +               t_size = t_size * cfg->pp_num;
10005 +#ifndef SAMSUNG_SXGA_CAM
10006 +               cfg->pp_virt_buf = dma_alloc_coherent(cfg->v->dev,
10007 +                                                     t_size, &cfg->pp_phys_buf,
10008 +                                                     GFP_KERNEL);
10009 +#else
10010 +               printk(KERN_INFO "Reserving High RAM Addresses \n");
10011 +               cfg->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVE_MEM ) + YUV_MEM;
10012 +               cfg->pp_virt_buf = ioremap_nocache(cfg->pp_phys_buf,RGB_MEM);
10013 +#endif
10014 +               if ( !cfg->pp_virt_buf ) {
10015 +                       printk(KERN_ERR"CAMERA:Failed to request RGB MEM\n");
10016 +                       return -ENOMEM;
10017 +               }
10018 +               memset(cfg->pp_virt_buf, 0, t_size);
10019 +               cfg->pp_totalsize = t_size;
10020 +               return 0;
10021 +       }
10022 +
10023 +       return 0;               /* Never come. */
10024 +}
10025 +
10026 +static int camif_demalloc(camif_cfg_t *cfg)
10027 +{
10028 +#ifndef SAMSUNG_SXGA_CAM
10029 +       if ( cfg->pp_virt_buf ) {
10030 +               dma_free_coherent(cfg->v->dev, cfg->pp_totalsize,
10031 +                                 cfg->pp_virt_buf, cfg->pp_phys_buf);
10032 +               cfg->pp_virt_buf = 0;
10033 +       }
10034 +#else
10035 +       iounmap(cfg->pp_virt_buf);
10036 +       cfg->pp_virt_buf = 0;
10037 +#endif
10038 +       return 0;
10039 +}
10040 +
10041 +/*
10042 + * advise a person to use this func in ISR
10043 + * index value indicates the next frame count to be used
10044 + */
10045 +int camif_g_frame_num(camif_cfg_t *cfg)
10046 +{
10047 +       int index = 0;
10048 +
10049 +       if (cfg->dma_type & CAMIF_CODEC ) {
10050 +               index = FRAME_CNT(readl(camregs + S3C2440_CAM_REG_CICOSTATUS));
10051 +               DPRINTK("CAMIF_CODEC frame %d \n", index);
10052 +       }
10053 +       else {
10054 +               assert(cfg->dma_type & CAMIF_PREVIEW );
10055 +               index = FRAME_CNT(readl(camregs + S3C2440_CAM_REG_CIPRSTATUS));
10056 +               DPRINTK("CAMIF_PREVIEW frame %d  0x%08X \n", index,
10057 +                       readl(camregs + S3C2440_CAM_REG_CIPRSTATUS));
10058 +       }
10059 +       cfg->now_frame_num = (index + 2) % 4; /* When 4 PingPong */
10060 +       return index; /* meaningless */
10061 +}
10062 +
10063 +static int camif_pp_codec(camif_cfg_t *cfg)
10064 +{
10065 +       u32 i, c_size; /* Cb,Cr size */
10066 +       u32 one_p_size;
10067 +       u32 daon = cfg->target_x * cfg->target_y;
10068 +       if (cfg->fmt & CAMIF_OUT_YCBCR420)
10069 +               c_size = daon / 4;
10070 +       else {
10071 +               assert(cfg->fmt & CAMIF_OUT_YCBCR422);
10072 +               c_size = daon / 2;
10073 +       }
10074 +       switch ( cfg->pp_num ) {
10075 +       case 1 :
10076 +               for (i =0 ; i < 4; i++) {
10077 +                       cfg->img_buf[i].virt_y = cfg->pp_virt_buf;
10078 +                       cfg->img_buf[i].phys_y = cfg->pp_phys_buf;
10079 +                       cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon;
10080 +                       cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon;
10081 +                       cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size;
10082 +                       cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size;
10083 +                       writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
10084 +                       writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
10085 +                       writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10086 +               }
10087 +               break;
10088 +       case 2:
10089 +#define  TRY   (( i%2 ) ? 1 :0)
10090 +               one_p_size = daon + 2*c_size;
10091 +               for (i = 0; i < 4  ; i++) {
10092 +                       cfg->img_buf[i].virt_y = cfg->pp_virt_buf + TRY * one_p_size;
10093 +                       cfg->img_buf[i].phys_y = cfg->pp_phys_buf + TRY * one_p_size;
10094 +                       cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + TRY * one_p_size;
10095 +                       cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + TRY * one_p_size;
10096 +                       cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + TRY * one_p_size;
10097 +                       cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + TRY * one_p_size;
10098 +                       writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
10099 +                       writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
10100 +                       writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10101 +               }
10102 +               break;
10103 +       case 4:
10104 +               one_p_size = daon + 2*c_size;
10105 +               for (i = 0; i < 4 ; i++) {
10106 +                       cfg->img_buf[i].virt_y = cfg->pp_virt_buf + i * one_p_size;
10107 +                       cfg->img_buf[i].phys_y = cfg->pp_phys_buf + i * one_p_size;
10108 +                       cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + i * one_p_size;
10109 +                       cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + i * one_p_size;
10110 +                       cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + i * one_p_size;
10111 +                       cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + i * one_p_size;
10112 +                       writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
10113 +                       writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
10114 +                       writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10115 +               }
10116 +               break;
10117 +       default:
10118 +               printk("Invalid PingPong Number %d \n",cfg->pp_num);
10119 +               panic("halt\n");
10120 +}
10121 +       return 0;
10122 +}
10123 +
10124 +/* RGB Buffer Allocation */
10125 +static int camif_pp_preview(camif_cfg_t *cfg)
10126 +{
10127 +       int i;
10128 +       u32 daon = cfg->target_x * cfg->target_y;
10129 +
10130 +       if(cfg->fmt & CAMIF_RGB24)
10131 +               daon = daon * 4 ;
10132 +       else {
10133 +               assert (cfg->fmt & CAMIF_RGB16);
10134 +               daon = daon *2;
10135 +       }
10136 +       switch ( cfg->pp_num ) {
10137 +               case 1:
10138 +                       for ( i = 0; i < 4 ; i++ ) {
10139 +                               cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf ;
10140 +                               cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf ;
10141 +                               writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10142 +                       }
10143 +                       break;
10144 +               case 2:
10145 +                       for ( i = 0; i < 4 ; i++) {
10146 +                               cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + TRY * daon;
10147 +                               cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + TRY * daon;
10148 +                               writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10149 +                       }
10150 +                       break;
10151 +               case 4:
10152 +                       for ( i = 0; i < 4 ; i++) {
10153 +                               cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + i * daon;
10154 +                               cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + i * daon;
10155 +                               writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10156 +                       }
10157 +                       break;
10158 +               default:
10159 +                       printk("Invalid PingPong Number %d \n",cfg->pp_num);
10160 +                       panic("halt\n");
10161 +       }
10162 +       return 0;
10163 +}
10164 +
10165 +static int camif_pingpong(camif_cfg_t *cfg)
10166 +{
10167 +       if (cfg->dma_type & CAMIF_CODEC ) {
10168 +               camif_pp_codec(cfg);
10169 +       }
10170 +
10171 +       if ( cfg->dma_type & CAMIF_PREVIEW) {
10172 +               camif_pp_preview(cfg);
10173 +       }
10174 +       return 0;
10175 +}
10176 +
10177 +
10178 +/***********       Image Convert *******************************/
10179 +/*  Return Format
10180 + *  Supported by Hardware
10181 + *  V4L2_PIX_FMT_YUV420,
10182 + *  V4L2_PIX_FMT_YUV422P,
10183 + *  V4L2_PIX_FMT_BGR32 (BGR4)
10184 + * -----------------------------------
10185 + *  V4L2_PIX_FMT_RGB565(X)
10186 + *  Currenly 2byte --> BGR656 Format
10187 + *  S3C2440A,S3C24A0 supports vairants with reversed FMT_RGB565
10188 +    i.e  blue toward the least, red towards the most significant bit
10189 +    --  by SW.LEE
10190 + */
10191 +
10192 +
10193 +/*
10194 + * After calling camif_g_frame_num,
10195 + * this func must be called
10196 + */
10197 +u8 * camif_g_frame(camif_cfg_t *cfg)
10198 +{
10199 +       u8 * ret = NULL;
10200 +       int cnt = cfg->now_frame_num;
10201 +
10202 +       if(cfg->dma_type & CAMIF_PREVIEW) {
10203 +               ret = cfg->img_buf[cnt].virt_rgb;
10204 +       }
10205 +       if (cfg->dma_type & CAMIF_CODEC) {
10206 +               ret = cfg->img_buf[cnt].virt_y;
10207 +       }
10208 +       return ret;
10209 +}
10210 +
10211 +/* This function must be called in module initial time */
10212 +static int camif_source_fmt(camif_gc_t *gc)
10213 +{
10214 +       u32 cmd = 0;
10215 +
10216 +       /* Configure CISRCFMT --Source Format */
10217 +       if (gc->itu_fmt & CAMIF_ITU601) {
10218 +               cmd = CAMIF_ITU601;
10219 +       }
10220 +       else {
10221 +               assert ( gc->itu_fmt & CAMIF_ITU656);
10222 +               cmd = CAMIF_ITU656;
10223 +       }
10224 +       cmd  |= SOURCE_HSIZE(gc->source_x)| SOURCE_VSIZE(gc->source_y);
10225 +       /* Order422 */
10226 +       cmd |=  gc->order422;
10227 +       writel(cmd, camregs + S3C2440_CAM_REG_CISRCFMT);
10228 +
10229 +       return 0 ;
10230 +}
10231 +
10232 +
10233 +/*
10234 + * Codec Input YCBCR422 will be Fixed
10235 + */
10236 +static int camif_target_fmt(camif_cfg_t *cfg)
10237 +{
10238 +       u32 cmd = 0;
10239 +
10240 +       if (cfg->dma_type & CAMIF_CODEC) {
10241 +               /* YCBCR setting */
10242 +               cmd = TARGET_HSIZE(cfg->target_x)| TARGET_VSIZE(cfg->target_y);
10243 +               if ( cfg->fmt & CAMIF_OUT_YCBCR420 ) {
10244 +                       cmd |= OUT_YCBCR420|IN_YCBCR422;
10245 +               }
10246 +               else {
10247 +                       assert(cfg->fmt & CAMIF_OUT_YCBCR422);
10248 +                       cmd |= OUT_YCBCR422|IN_YCBCR422;
10249 +               }
10250 +               writel(cmd | cfg->flip, camregs + S3C2440_CAM_REG_CICOTRGFMT);
10251 +
10252 +       } else {
10253 +               assert(cfg->dma_type & CAMIF_PREVIEW);
10254 +               writel(TARGET_HSIZE(cfg->target_x)|TARGET_VSIZE(cfg->target_y)|cfg->flip,
10255 +                       camregs + S3C2440_CAM_REG_CIPRTRGFMT);
10256 +       }
10257 +       return 0;
10258 +}
10259 +
10260 +void camif_change_flip(camif_cfg_t *cfg)
10261 +{
10262 +       u32 cmd = readl(camregs + S3C2440_CAM_REG_CICOTRGFMT);
10263 +
10264 +       cmd &= ~(BIT14|BIT15);
10265 +       cmd |= cfg->flip;
10266 +
10267 +       writel(cmd, camregs + S3C2440_CAM_REG_CICOTRGFMT);
10268 +}
10269 +
10270 +
10271 +
10272 +/* Must:
10273 + * Before calling this function,
10274 + * you must use "camif_dynamic_open"
10275 + * If you want to enable both CODEC and preview
10276 + *  you must do it at the same time.
10277 + */
10278 +int camif_capture_start(camif_cfg_t *cfg)
10279 +{
10280 +       u32 n_cmd = 0;          /* Next Command */
10281 +
10282 +       switch(cfg->exec) {
10283 +       case CAMIF_BOTH_DMA_ON:
10284 +               camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
10285 +               writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) |
10286 +                            SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
10287 +               writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) |
10288 +                            SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
10289 +               n_cmd = CAMIF_CAP_PREVIEW_ON | CAMIF_CAP_CODEC_ON;
10290 +               break;
10291 +       case CAMIF_DMA_ON:
10292 +               camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
10293 +               if (cfg->dma_type&CAMIF_CODEC) {
10294 +                       writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) |
10295 +                            SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
10296 +                       n_cmd = CAMIF_CAP_CODEC_ON;
10297 +               } else {
10298 +                       writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) |
10299 +                            SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
10300 +                       n_cmd = CAMIF_CAP_PREVIEW_ON;
10301 +               }
10302 +
10303 +               /* wait until Sync Time expires */
10304 +               /* First settting, to wait VSYNC fall  */
10305 +               /* By VESA spec,in 640x480 @60Hz
10306 +                       MAX Delay Time is around 64us which "while" has.*/
10307 +               while(VSYNC & readl(camregs + S3C2440_CAM_REG_CICOSTATUS));
10308 +               break;
10309 +       default:
10310 +               break;
10311 +}
10312 +       writel(n_cmd | CAMIF_CAP_ON, camregs + S3C2440_CAM_REG_CIIMGCPT);
10313 +       return 0;
10314 +}
10315 +
10316 +
10317 +int camif_capture_stop(camif_cfg_t *cfg)
10318 +{
10319 +       u32 n_cmd = readl(camregs + S3C2440_CAM_REG_CIIMGCPT);  /* Next Command */
10320 +
10321 +       switch(cfg->exec) {
10322 +       case CAMIF_BOTH_DMA_OFF:
10323 +               writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) &
10324 +                       ~SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
10325 +               writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) &
10326 +                       ~SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
10327 +               n_cmd = 0;
10328 +               break;
10329 +       case CAMIF_DMA_OFF_L_IRQ: /* fall thru */
10330 +       case CAMIF_DMA_OFF:
10331 +               if (cfg->dma_type&CAMIF_CODEC) {
10332 +                       writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) &
10333 +                           ~SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
10334 +                       n_cmd &= ~CAMIF_CAP_CODEC_ON;
10335 +                       if (!(n_cmd & CAMIF_CAP_PREVIEW_ON))
10336 +                               n_cmd = 0;
10337 +               } else {
10338 +                       writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) &
10339 +                           ~SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
10340 +                       n_cmd &= ~CAMIF_CAP_PREVIEW_ON;
10341 +                       if (!(n_cmd & CAMIF_CAP_CODEC_ON))
10342 +                               n_cmd = 0;
10343 +               }
10344 +               break;
10345 +       default:
10346 +               panic("Unexpected \n");
10347 +       }
10348 +       writel(n_cmd, camregs + S3C2440_CAM_REG_CIIMGCPT);
10349 +
10350 +       if (cfg->exec == CAMIF_DMA_OFF_L_IRQ) { /* Last IRQ  */
10351 +               if (cfg->dma_type & CAMIF_CODEC)
10352 +                       writel(readl(camregs + S3C2440_CAM_REG_CICOCTRL) |
10353 +                            LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CICOCTRL);
10354 +               else
10355 +                       writel(readl(camregs + S3C2440_CAM_REG_CIPRCTRL) |
10356 +                            LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CIPRCTRL);
10357 +       }
10358 +#if 0
10359 +       else {                          /* to make internal state machine of CAMERA stop */
10360 +               camif_reset(CAMIF_RESET, 0);
10361 +       }
10362 +#endif
10363 +       return 0;
10364 +}
10365 +
10366 +
10367 +/* LastIRQEn is autoclear */
10368 +void camif_last_irq_en(camif_cfg_t *cfg)
10369 +{
10370 +       if ((cfg->exec == CAMIF_BOTH_DMA_ON) || (cfg->dma_type & CAMIF_CODEC))
10371 +               writel(readl(camregs + S3C2440_CAM_REG_CICOCTRL) |
10372 +                       LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CICOCTRL);
10373 +
10374 +       if ((cfg->exec == CAMIF_BOTH_DMA_ON) || !(cfg->dma_type & CAMIF_CODEC))
10375 +               writel(readl(camregs + S3C2440_CAM_REG_CIPRCTRL) |
10376 +                       LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CIPRCTRL);
10377 +}
10378 +
10379 +static int
10380 +camif_scaler_internal(u32 srcWidth, u32 dstWidth, u32 *ratio, u32 *shift)
10381 +{
10382 +       if(srcWidth>=64*dstWidth){
10383 +               printk(KERN_ERR"CAMERA:out of prescaler range: srcWidth /dstWidth = %d(< 64)\n",
10384 +                        srcWidth/dstWidth);
10385 +               return 1;
10386 +       }
10387 +       else if(srcWidth>=32*dstWidth){
10388 +               *ratio=32;
10389 +               *shift=5;
10390 +       }
10391 +       else if(srcWidth>=16*dstWidth){
10392 +               *ratio=16;
10393 +               *shift=4;
10394 +       }
10395 +       else if(srcWidth>=8*dstWidth){
10396 +               *ratio=8;
10397 +               *shift=3;
10398 +       }
10399 +       else if(srcWidth>=4*dstWidth){
10400 +               *ratio=4;
10401 +               *shift=2;
10402 +       }
10403 +       else if(srcWidth>=2*dstWidth){
10404 +               *ratio=2;
10405 +               *shift=1;
10406 +       }
10407 +       else {
10408 +               *ratio=1;
10409 +               *shift=0;
10410 +       }
10411 +       return 0;
10412 +}
10413 +
10414 +
10415 +int camif_g_fifo_status(camif_cfg_t *cfg)
10416 +{
10417 +       u32 reg;
10418 +
10419 +       if (cfg->dma_type & CAMIF_CODEC) {
10420 +               u32 flag = CO_OVERFLOW_Y | CO_OVERFLOW_CB | CO_OVERFLOW_CR;
10421 +               reg = readl(camregs + S3C2440_CAM_REG_CICOSTATUS);
10422 +               if (reg & flag) {
10423 +                       printk("CODEC: FIFO error(0x%08x) and corrected\n",reg);
10424 +                       /* FIFO Error Count ++  */
10425 +                       writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) |
10426 +                               CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR,
10427 +                               camregs + S3C2440_CAM_REG_CIWDOFST);
10428 +
10429 +                       writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) &
10430 +                               ~(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR),
10431 +                               camregs + S3C2440_CAM_REG_CIWDOFST);
10432 +                       return 1; /* Error */
10433 +               }
10434 +       }
10435 +       if (cfg->dma_type & CAMIF_PREVIEW) {
10436 +               u32 flag = PR_OVERFLOW_CB | PR_OVERFLOW_CR;
10437 +               reg = readl(camregs + S3C2440_CAM_REG_CIPRSTATUS);
10438 +               if (reg & flag) {
10439 +                       printk("PREVIEW:FIFO error(0x%08x) and corrected\n",reg);
10440 +                       writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) |
10441 +                               CO_FIFO_CB | CO_FIFO_CR,
10442 +                               camregs + S3C2440_CAM_REG_CIWDOFST);
10443 +
10444 +                       writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) &
10445 +                               ~(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR),
10446 +                               camregs + S3C2440_CAM_REG_CIWDOFST);
10447 +                       /* FIFO Error Count ++  */
10448 +                       return 1; /* Error */
10449 +               }
10450 +       }
10451 +       return 0;               /* No Error */
10452 +}
10453 +
10454 +
10455 +/* Policy:
10456 + * if codec or preview define the win offset,
10457 + *    other must follow that value.
10458 + */
10459 +int camif_win_offset(camif_gc_t *gc )
10460 +{
10461 +       u32 h = gc->win_hor_ofst;
10462 +       u32 v = gc->win_ver_ofst;
10463 +
10464 +       /*Clear Overflow */
10465 +       writel(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR | PR_FIFO_CB | PR_FIFO_CB,
10466 +               camregs + S3C2440_CAM_REG_CIWDOFST);
10467 +       writel(0, camregs + S3C2440_CAM_REG_CIWDOFST);
10468 +
10469 +       if (!h && !v)   {
10470 +               writel(0, camregs + S3C2440_CAM_REG_CIWDOFST);
10471 +               return 0;
10472 +       }
10473 +
10474 +       writel(WINOFEN | WINHOROFST(h) | WINVEROFST(v), camregs + S3C2440_CAM_REG_CIWDOFST);
10475 +       return 0;
10476 +}
10477 +
10478 +/*
10479 + * when you change the resolution in a specific camera,
10480 + * sometimes, it is necessary to change the polarity
10481 + *                                       -- SW.LEE
10482 + */
10483 +static void camif_polarity(camif_gc_t *gc)
10484 +{
10485 +       u32 cmd = readl(camregs + S3C2440_CAM_REG_CIGCTRL);;
10486 +
10487 +       cmd = cmd & ~(BIT26|BIT25|BIT24); /* clear polarity */
10488 +       if (gc->polarity_pclk)
10489 +               cmd |= GC_INVPOLPCLK;
10490 +       if (gc->polarity_vsync)
10491 +               cmd |= GC_INVPOLVSYNC;
10492 +       if (gc->polarity_href)
10493 +               cmd |= GC_INVPOLHREF;
10494 +       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
10495 +              cmd, camregs + S3C2440_CAM_REG_CIGCTRL);
10496 +}
10497 +
10498 +
10499 +int camif_dynamic_open(camif_cfg_t *cfg)
10500 +{
10501 +       camif_win_offset(cfg->gc);
10502 +       camif_polarity(cfg->gc);
10503 +
10504 +       if(camif_scaler(cfg)) {
10505 +               printk(KERN_ERR "CAMERA:Preview Scaler, Change WinHorOfset or Target Size\n");
10506 +               return 1;
10507 +       }
10508 +       camif_target_fmt(cfg);
10509 +       if (camif_dma_burst(cfg)) {
10510 +               printk(KERN_ERR "CAMERA:DMA Busrt Length Error \n");
10511 +               return 1;
10512 +       }
10513 +       if(camif_malloc(cfg) ) {
10514 +               printk(KERN_ERR "    Instead of using consistent_alloc()\n"
10515 +                               "    lease use dedicated memory allocation for DMA memory\n");
10516 +               return -1;
10517 +       }
10518 +       camif_pingpong(cfg);
10519 +       return 0;
10520 +}
10521 +
10522 +int camif_dynamic_close(camif_cfg_t *cfg)
10523 +{
10524 +       camif_demalloc(cfg);
10525 +       return 0;
10526 +}
10527 +
10528 +static int camif_target_area(camif_cfg_t *cfg)
10529 +{
10530 +       u32 rect = cfg->target_x * cfg->target_y;
10531 +
10532 +       if (cfg->dma_type & CAMIF_CODEC)
10533 +               writel(rect, camregs + S3C2440_CAM_REG_CICOTAREA);
10534 +
10535 +       if (cfg->dma_type & CAMIF_PREVIEW)
10536 +               writel(rect, camregs + S3C2440_CAM_REG_CIPRTAREA);
10537 +
10538 +       return 0;
10539 +}
10540 +
10541 +static int inline camif_hw_reg(camif_cfg_t *cfg)
10542 +{
10543 +       u32 cmd = 0;
10544 +
10545 +       if (cfg->dma_type & CAMIF_CODEC) {
10546 +               writel(PRE_SHIFT(cfg->sc.shfactor) |
10547 +                      PRE_HRATIO(cfg->sc.prehratio) |
10548 +                      PRE_VRATIO(cfg->sc.prevratio),
10549 +                      camregs + S3C2440_CAM_REG_CICOSCPRERATIO);
10550 +               writel(PRE_DST_WIDTH(cfg->sc.predst_x) |
10551 +                      PRE_DST_HEIGHT(cfg->sc.predst_y),
10552 +                      camregs + S3C2440_CAM_REG_CICOSCPREDST);
10553 +
10554 +               /* Differ from Preview */
10555 +               if (cfg->sc.scalerbypass)
10556 +                       cmd |= SCALERBYPASS;
10557 +               if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
10558 +                       cmd |= BIT30|BIT29;
10559 +               writel(cmd | MAIN_HRATIO(cfg->sc.mainhratio) |
10560 +                      MAIN_VRATIO(cfg->sc.mainvratio),
10561 +                      camregs + S3C2440_CAM_REG_CICOSCCTRL);
10562 +               return 0;
10563 +       }
10564 +       if (cfg->dma_type & CAMIF_PREVIEW) {
10565 +               writel(PRE_SHIFT(cfg->sc.shfactor) |
10566 +                      PRE_HRATIO(cfg->sc.prehratio) |
10567 +                      PRE_VRATIO(cfg->sc.prevratio),
10568 +                      camregs + S3C2440_CAM_REG_CIPRSCPRERATIO);
10569 +               writel(PRE_DST_WIDTH(cfg->sc.predst_x) |
10570 +                      PRE_DST_HEIGHT(cfg->sc.predst_y),
10571 +                      camregs + S3C2440_CAM_REG_CIPRSCPREDST);
10572 +               /* Differ from Codec */
10573 +               if (cfg->fmt & CAMIF_RGB24)
10574 +                       cmd |= RGB_FMT24;
10575 +               if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
10576 +                       cmd |= BIT29 | BIT28;
10577 +               writel(cmd | MAIN_HRATIO(cfg->sc.mainhratio) | S_METHOD |
10578 +                      MAIN_VRATIO(cfg->sc.mainvratio),
10579 +                      camregs + S3C2440_CAM_REG_CIPRSCCTRL);
10580 +               return 0;
10581 +       }
10582 +
10583 +       panic("CAMERA:DMA_TYPE Wrong \n");
10584 +       return 0;
10585 +}
10586 +
10587 +
10588 +/* Configure Pre-scaler control  & main scaler control register */
10589 +static int camif_scaler(camif_cfg_t *cfg)
10590 +{
10591 +       int tx = cfg->target_x, ty = cfg->target_y;
10592 +       int sx, sy;
10593 +
10594 +       if (tx <= 0 || ty <= 0)
10595 +               panic("CAMERA: Invalid target size \n");
10596 +
10597 +       sx = cfg->gc->source_x - 2 * cfg->gc->win_hor_ofst;
10598 +       sy = cfg->gc->source_y - 2 * cfg->gc->win_ver_ofst;
10599 +       if (sx <= 0 || sy <= 0)
10600 +               panic("CAMERA: Invalid source size \n");
10601 +
10602 +       cfg->sc.modified_src_x = sx;
10603 +       cfg->sc.modified_src_y = sy;
10604 +
10605 +       /* Pre-scaler control register 1 */
10606 +       camif_scaler_internal(sx, tx, &cfg->sc.prehratio, &cfg->sc.hfactor);
10607 +       camif_scaler_internal(sy, ty, &cfg->sc.prevratio, &cfg->sc.vfactor);
10608 +
10609 +       if (cfg->dma_type & CAMIF_PREVIEW)
10610 +               if ((sx / cfg->sc.prehratio) > 640) {
10611 +                       printk(KERN_INFO "CAMERA: Internal Preview line "
10612 +                                        "buffer is 640 pixels\n");
10613 +                       return 1; /* Error */
10614 +               }
10615 +
10616 +       cfg->sc.shfactor = 10 - (cfg->sc.hfactor + cfg->sc.vfactor);
10617 +       /* Pre-scaler control register 2 */
10618 +       cfg->sc.predst_x = sx / cfg->sc.prehratio;
10619 +       cfg->sc.predst_y = sy / cfg->sc.prevratio;
10620 +
10621 +       /* Main-scaler control register */
10622 +       cfg->sc.mainhratio = (sx << 8) / (tx << cfg->sc.hfactor);
10623 +       cfg->sc.mainvratio = (sy << 8) / (ty << cfg->sc.vfactor);
10624 +       DPRINTK(" sx %d, sy %d tx %d ty %d  \n", sx, sy, tx, ty);
10625 +       DPRINTK(" hfactor %d  vfactor %d \n",cfg->sc.hfactor, cfg->sc.vfactor);
10626 +
10627 +       cfg->sc.scaleup_h  = (sx <= tx) ? 1: 0;
10628 +       cfg->sc.scaleup_v  = (sy <= ty) ? 1: 0;
10629 +       if (cfg->sc.scaleup_h != cfg->sc.scaleup_v)
10630 +               printk(KERN_ERR "scaleup_h must be same to scaleup_v \n");
10631 +
10632 +       camif_hw_reg(cfg);
10633 +       camif_target_area(cfg);
10634 +
10635 +       return 0;
10636 +}
10637 +
10638 +/******************************************************
10639 + CalculateBurstSize - Calculate the busrt lengths
10640 + Description:
10641 + - dstHSize: the number of the byte of H Size.
10642 +********************************************************/
10643 +static void camif_g_bsize(u32 hsize, u32 *mburst, u32 *rburst)
10644 +{
10645 +       u32 tmp;
10646 +
10647 +       tmp = (hsize / 4) % 16;
10648 +       switch(tmp) {
10649 +       case 0:
10650 +               *mburst=16;
10651 +               *rburst=16;
10652 +               break;
10653 +       case 4:
10654 +               *mburst=16;
10655 +               *rburst=4;
10656 +               break;
10657 +       case 8:
10658 +               *mburst=16;
10659 +               *rburst=8;
10660 +               break;
10661 +       default:
10662 +               tmp=(hsize / 4) % 8;
10663 +               switch(tmp) {
10664 +               case 0:
10665 +                       *mburst = 8;
10666 +                       *rburst = 8;
10667 +                       break;
10668 +               case 4:
10669 +                       *mburst = 8;
10670 +                       *rburst = 4;
10671 +               default:
10672 +                       *mburst = 4;
10673 +                       tmp = (hsize / 4) % 4;
10674 +                       *rburst= (tmp) ? tmp: 4;
10675 +                       break;
10676 +       }
10677 +               break;
10678 +       }
10679 +}
10680 +
10681 +/* SXGA 1028x1024*/
10682 +/* XGA 1024x768 */
10683 +/* SVGA 800x600 */
10684 +/* VGA 640x480 */
10685 +/* CIF 352x288 */
10686 +/* QVGA 320x240 */
10687 +/* QCIF 176x144 */
10688 +/* ret val
10689 +        1 : DMA Size Error
10690 +*/
10691 +#define BURST_ERR 1
10692 +static int camif_dma_burst(camif_cfg_t *cfg)
10693 +{
10694 +       int width = cfg->target_x;
10695 +
10696 +       if (cfg->dma_type & CAMIF_CODEC ) {
10697 +               u32 yburst_m, yburst_r;
10698 +               u32 cburst_m, cburst_r;
10699 +               /* CODEC DMA WIDHT is multiple of 16 */
10700 +               if (width % 16)
10701 +                       return BURST_ERR;   /* DMA Burst Length Error */
10702 +               camif_g_bsize(width, &yburst_m, &yburst_r);
10703 +               camif_g_bsize(width / 2, &cburst_m, &cburst_r);
10704 +
10705 +               writel(YBURST_M(yburst_m) | CBURST_M(cburst_m) |
10706 +                      YBURST_R(yburst_r) | CBURST_R(cburst_r),
10707 +                      camregs + S3C2440_CAM_REG_CICOCTRL);
10708 +       }
10709 +
10710 +       if (cfg->dma_type & CAMIF_PREVIEW) {
10711 +               u32 rgburst_m, rgburst_r;
10712 +               if(cfg->fmt == CAMIF_RGB24) {
10713 +                       if (width % 2)
10714 +                               return BURST_ERR;   /* DMA Burst Length Error */
10715 +                       camif_g_bsize(width*4,&rgburst_m,&rgburst_r);
10716 +               } else {                /* CAMIF_RGB16 */
10717 +                       if ((width / 2) %2)
10718 +                               return BURST_ERR; /* DMA Burst Length Error */
10719 +                       camif_g_bsize(width*2,&rgburst_m,&rgburst_r);
10720 +               }
10721 +
10722 +               writel(RGBURST_M(rgburst_m) | RGBURST_R(rgburst_r),
10723 +                      camregs + S3C2440_CAM_REG_CIPRCTRL);
10724 +       }
10725 +       return 0;
10726 +}
10727 +
10728 +static int camif_gpio_init(void)
10729 +{
10730 +#ifdef CONFIG_ARCH_S3C24A0A
10731 +       /* S3C24A0A has the dedicated signal pins for Camera */
10732 +#else
10733 +       s3c2410_gpio_cfgpin(S3C2440_GPJ0, S3C2440_GPJ0_CAMDATA0);
10734 +       s3c2410_gpio_cfgpin(S3C2440_GPJ1, S3C2440_GPJ1_CAMDATA1);
10735 +       s3c2410_gpio_cfgpin(S3C2440_GPJ2, S3C2440_GPJ2_CAMDATA2);
10736 +       s3c2410_gpio_cfgpin(S3C2440_GPJ3, S3C2440_GPJ3_CAMDATA3);
10737 +       s3c2410_gpio_cfgpin(S3C2440_GPJ4, S3C2440_GPJ4_CAMDATA4);
10738 +       s3c2410_gpio_cfgpin(S3C2440_GPJ5, S3C2440_GPJ5_CAMDATA5);
10739 +       s3c2410_gpio_cfgpin(S3C2440_GPJ6, S3C2440_GPJ6_CAMDATA6);
10740 +       s3c2410_gpio_cfgpin(S3C2440_GPJ7, S3C2440_GPJ7_CAMDATA7);
10741 +
10742 +       s3c2410_gpio_cfgpin(S3C2440_GPJ8, S3C2440_GPJ8_CAMPCLK);
10743 +       s3c2410_gpio_cfgpin(S3C2440_GPJ9, S3C2440_GPJ9_CAMVSYNC);
10744 +       s3c2410_gpio_cfgpin(S3C2440_GPJ10, S3C2440_GPJ10_CAMHREF);
10745 +       s3c2410_gpio_cfgpin(S3C2440_GPJ11, S3C2440_GPJ11_CAMCLKOUT);
10746 +       s3c2410_gpio_cfgpin(S3C2440_GPJ12, S3C2440_GPJ12_CAMRESET);
10747 +#endif
10748 +        return 0;
10749 +}
10750 +
10751 +
10752 +#define ROUND_ADD 0x100000
10753 +
10754 +#ifdef CONFIG_ARCH_S3C24A0A
10755 +int camif_clock_init(camif_gc_t *gc)
10756 +{
10757 +       unsigned int upll, camclk_div, camclk;
10758 +
10759 +       if (!gc) camclk = 24000000;
10760 +       else  {
10761 +               camclk = gc->camclk;
10762 +               if (camclk > 48000000)
10763 +                       printk(KERN_ERR "Wrong Camera Clock\n");
10764 +       }
10765 +
10766 +       CLKCON |= CLKCON_CAM_UPLL | CLKCON_CAM_HCLK;
10767 +       upll = get_bus_clk(GET_UPLL);
10768 +       printk(KERN_INFO "CAMERA:Default UPLL %08d and Assing 96Mhz to UPLL\n",upll);
10769 +       UPLLCON = FInsrt(56, fPLL_MDIV) | FInsrt(2, fPLL_PDIV)| FInsrt(1, fPLL_SDIV);
10770 +       upll = get_bus_clk(GET_UPLL);
10771 +
10772 +       camclk_div = (upll+ROUND_ADD) / camclk - 1;
10773 +       CLKDIVN = (CLKDIVN & 0xFF) | CLKDIVN_CAM(camclk_div);
10774 +       printk(KERN_INFO"CAMERA:upll %d MACRO 0x%08X CLKDIVN 0x%08X \n",
10775 +                               upll, CLKDIVN_CAM(camclk_div), CLKDIVN);
10776 +       writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);  /* Dummy ? */
10777 +
10778 +       return 0;
10779 +}
10780 +#else
10781 +int camif_clock_init(camif_gc_t *gc)
10782 +{
10783 +       unsigned int camclk;
10784 +       struct clk *clk_camif = clk_get(NULL, "camif");
10785 +       struct clk *clk_camif_upll = clk_get(NULL, "camif-upll");
10786 +
10787 +       if (!gc)
10788 +               camclk = 24000000;
10789 +       else {
10790 +               camclk = gc->camclk;
10791 +               if (camclk > 48000000)
10792 +                       printk(KERN_ERR "Wrong Camera Clock\n");
10793 +       }
10794 +
10795 +       clk_set_rate(clk_camif, camclk);
10796 +
10797 +       clk_enable(clk_camif);
10798 +       clk_enable(clk_camif_upll);
10799 +
10800 +
10801 +#if 0
10802 +       CLKCON |= CLKCON_CAMIF;
10803 +       upll = elfin_get_bus_clk(GET_UPLL);
10804 +       printk(KERN_INFO "CAMERA:Default UPLL %08d and Assing 96Mhz to UPLL\n",upll);
10805 +       {
10806 +               UPLLCON = FInsrt(60, fPLL_MDIV) | FInsrt(4, fPLL_PDIV)| FInsrt(1, fPLL_SDIV);
10807 +               CLKDIVN |= DIVN_UPLL;   /* For USB */
10808 +               upll = elfin_get_bus_clk(GET_UPLL);
10809 +       }
10810 +
10811 +       camclk_div = (upll+ROUND_ADD) /(camclk * 2) -1;
10812 +       CAMDIVN = CAMCLK_SET_DIV|(camclk_div&0xf);
10813 +       printk(KERN_INFO "CAMERA:upll %08d  cam_clk %08d CAMDIVN 0x%08x \n",upll,camclk, CAMDIVN);
10814 +#endif
10815 +       writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);  /* Dummy ? */
10816 +
10817 +       return 0;
10818 +}
10819 +#endif
10820 +
10821 +/*
10822 +   Reset Camera IP in CPU
10823 +   Reset External Sensor
10824 + */
10825 +void camif_reset(int is, int delay)
10826 +{
10827 +       switch (is) {
10828 +               case CAMIF_RESET:
10829 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
10830 +                              GC_SWRST,
10831 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10832 +                       mdelay(1);
10833 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
10834 +                              ~GC_SWRST,
10835 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10836 +                       break;
10837 +               case CAMIF_EX_RESET_AH: /*Active High */
10838 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
10839 +                              ~GC_CAMRST,
10840 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10841 +                       udelay(200);
10842 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
10843 +                              GC_CAMRST,
10844 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10845 +                       udelay(delay);
10846 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
10847 +                              ~GC_CAMRST,
10848 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10849 +                       break;
10850 +               case CAMIF_EX_RESET_AL: /*Active Low */
10851 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
10852 +                              GC_CAMRST,
10853 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10854 +                       udelay(200);
10855 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
10856 +                              ~GC_CAMRST,
10857 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10858 +                       udelay(delay);
10859 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
10860 +                              GC_CAMRST,
10861 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10862 +                       break;
10863 +               default:
10864 +                       break;
10865 +       }
10866 +}
10867 +
10868 +/* For Camera Operation,
10869 + * we can give the high priority to REQ2 of ARBITER1
10870 + */
10871 +
10872 +/* Please move me into proper place
10873 + *  camif_gc_t is not because "rmmod imgsenor" will delete the instance of camif_gc_t
10874 + */
10875 +static u32 old_priority;
10876 +
10877 +static void camif_bus_priority(int flag)
10878 +{
10879 +       if (flag) {
10880 +#ifdef CONFIG_ARCH_S3C24A0A
10881 +               old_priority = PRIORITY0;
10882 +               PRIORITY0 = PRIORITY_I_FIX;
10883 +               PRIORITY1 = PRIORITY_I_FIX;
10884 +
10885 +#else
10886 +               old_priority = readl(S3C2410_PRIORITY);
10887 +               writel(readl(S3C2410_PRIORITY) & ~(3<<7), S3C2410_PRIORITY);
10888 +               writel(readl(S3C2410_PRIORITY) |  (1<<7), S3C2410_PRIORITY); /* Arbiter 1, REQ2 first */
10889 +               writel(readl(S3C2410_PRIORITY) & ~(1<<1), S3C2410_PRIORITY); /* Disable Priority Rotate */
10890 +#endif
10891 +       }
10892 +       else {
10893 +#ifdef CONFIG_ARCH_S3C24A0A
10894 +               PRIORITY0 = old_priority;
10895 +               PRIORITY1 = old_priority;
10896 +#else
10897 +               writel(old_priority, S3C2410_PRIORITY);
10898 +#endif
10899 +       }
10900 +}
10901 +
10902 +static void inline camif_clock_off(void)
10903 +{
10904 +#if defined (CONFIG_ARCH_S3C24A0A)
10905 +       writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);
10906 +
10907 +       CLKCON &= ~CLKCON_CAM_UPLL;
10908 +       CLKCON &= ~CLKCON_CAM_HCLK;
10909 +#else
10910 +       struct clk *clk_camif = clk_get(NULL, "camif");
10911 +       struct clk *clk_camif_upll = clk_get(NULL, "camif-upll");
10912 +
10913 +       writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);
10914 +
10915 +       clk_disable(clk_camif);
10916 +       clk_disable(clk_camif_upll);
10917 +#endif
10918 +}
10919 +
10920 +
10921 +/* Init external image sensor
10922 + *  Before make some value into image senor,
10923 + *  you must set up the pixel clock.
10924 + */
10925 +void camif_setup_sensor(void)
10926 +{
10927 +       camif_reset(CAMIF_RESET, 0);
10928 +       camif_gpio_init();
10929 +       camif_clock_init(NULL);
10930 +/* Sometimes ,Before loading I2C module, we need the reset signal */
10931 +#ifdef CONFIG_ARCH_S3C24A0A
10932 +       camif_reset(CAMIF_EX_RESET_AL,1000);
10933 +#else
10934 +       camif_reset(CAMIF_EX_RESET_AH,1000);
10935 +#endif
10936 +}
10937 +
10938 +void camif_hw_close(camif_cfg_t *cfg)
10939 +{
10940 +       camif_bus_priority(0);
10941 +       camif_clock_off();
10942 +}
10943 +
10944 +void camif_hw_open(camif_gc_t *gc)
10945 +{
10946 +       camif_source_fmt(gc);
10947 +       camif_win_offset(gc);
10948 +       camif_bus_priority(1);
10949 +}
10950 +
10951 +
10952 +
10953 +/*
10954 + * Local variables:
10955 + * tab-width: 8
10956 + *  c-indent-level: 8
10957 + *  c-basic-offset: 8
10958 + *  c-set-style: "K&R"
10959 + * End:
10960 + */
10961 --- /dev/null
10962 +++ b/arch/arm/mach-s3c2440/camera/camif_fsm.c
10963 @@ -0,0 +1,432 @@
10964 +/*
10965 +    Copyright (C) 2004 Samsung Electronics
10966 +                     SW.LEE <hitchcar@sec.samsung.com>
10967 +
10968 +    This program is free software; you can redistribute it and/or modify
10969 +    it under the terms of the GNU General Public License as published by
10970 +    the Free Software Foundation; either version 2 of the License, or
10971 +    (at your option) any later version.
10972 +*/
10973 +
10974 +#include <linux/version.h>
10975 +#include <linux/module.h>
10976 +#include <linux/delay.h>
10977 +#include <linux/errno.h>
10978 +#include <linux/fs.h>
10979 +#include <linux/kernel.h>
10980 +#include <linux/major.h>
10981 +#include <linux/slab.h>
10982 +#include <linux/poll.h>
10983 +#include <linux/signal.h>
10984 +#include <linux/ioport.h>
10985 +#include <linux/sched.h>
10986 +#include <linux/types.h>
10987 +#include <linux/interrupt.h>
10988 +#include <linux/kmod.h>
10989 +#include <linux/vmalloc.h>
10990 +#include <linux/init.h>
10991 +#include <linux/pagemap.h>
10992 +#include <asm/io.h>
10993 +#include <asm/irq.h>
10994 +#include <asm/semaphore.h>
10995 +#include <linux/miscdevice.h>
10996 +
10997 +#define CONFIG_VIDEO_V4L1_COMPAT
10998 +#include <linux/videodev.h>
10999 +#include "camif.h"
11000 +
11001 +//#define SW_DEBUG
11002 +static void camif_start_p_with_c(camif_cfg_t *cfg);
11003 +
11004 +#include "camif.h"
11005 +const char *fsm_version =
11006 +        "$Id: camif_fsm.c,v 1.3 2004/04/27 10:26:28 swlee Exp $";
11007 +
11008 +
11009 +/*
11010 + * FSM function is the place where Synchronization in not necessary
11011 + * because IRS calls this functions.
11012 + */
11013 +
11014 +ssize_t camif_p_1fsm_start(camif_cfg_t *cfg)
11015 +{
11016 +       //camif_reset(CAMIF_RESET,0);
11017 +       cfg->exec = CAMIF_DMA_ON;
11018 +       camif_capture_start(cfg);
11019 +       camif_last_irq_en(cfg);
11020 +       cfg->status = CAMIF_STARTED;
11021 +       cfg->fsm = CAMIF_1nd_INT;
11022 +       return 0;
11023 +}
11024 +
11025 +
11026 +ssize_t camif_p_2fsm_start(camif_cfg_t *cfg)
11027 +{
11028 +       camif_reset(CAMIF_RESET,0);/* FIFO Count goes to zero */
11029 +       cfg->exec = CAMIF_DMA_ON;
11030 +       camif_capture_start(cfg);
11031 +       cfg->status = CAMIF_STARTED;
11032 +       cfg->fsm = CAMIF_1nd_INT;
11033 +       return 0;
11034 +}
11035 +
11036 +
11037 +ssize_t camif_4fsm_start(camif_cfg_t *cfg)
11038 +{
11039 +       camif_reset(CAMIF_RESET,0); /* FIFO Count goes to zero */
11040 +       cfg->exec = CAMIF_DMA_ON;
11041 +       camif_capture_start(cfg);
11042 +       cfg->status = CAMIF_STARTED;
11043 +       cfg->fsm = CAMIF_1nd_INT;
11044 +       cfg->perf.frames = 0;
11045 +       return 0;
11046 +}
11047 +
11048 +
11049 +/* Policy:
11050 +     cfg->perf.frames  set in camif_fsm.c
11051 +     cfg->status set in video-driver.c
11052 + */
11053 +
11054 +/*
11055 + * Don't insert camif_reset(CAM_RESET, 0 ) into this func
11056 + */
11057 +ssize_t camif_p_stop(camif_cfg_t *cfg)
11058 +{
11059 +       cfg->exec = CAMIF_DMA_OFF;
11060 +//     cfg->status = CAMIF_STOPPED;
11061 +       camif_capture_stop(cfg);
11062 +       cfg->perf.frames = 0;   /* Dupplicated ? */
11063 +       return 0;
11064 +}
11065 +
11066 +/* When C working, P asks C to play togehter */
11067 +/* Only P must call this function */
11068 +void camif_start_c_with_p (camif_cfg_t *cfg, camif_cfg_t *other)
11069 +{
11070 +//     cfg->gc->other = get_camif(CODEC_MINOR);
11071 +       cfg->gc->other = other;
11072 +       camif_start_p_with_c(cfg);
11073 +}
11074 +
11075 +static void camif_start_p_with_c(camif_cfg_t *cfg)
11076 +{
11077 +       camif_cfg_t *other = (camif_cfg_t *)cfg->gc->other;
11078 +       /* Preview Stop */
11079 +       cfg->exec = CAMIF_DMA_OFF;
11080 +       camif_capture_stop(cfg);
11081 +       /* Start P and C */
11082 +       camif_reset(CAMIF_RESET, 0);
11083 +       cfg->exec =CAMIF_BOTH_DMA_ON;
11084 +       camif_capture_start(cfg);
11085 +       cfg->fsm = CAMIF_1nd_INT; /* For Preview */
11086 +       if(!other) panic("Unexpected Error \n");
11087 +       other->fsm = CAMIF_1nd_INT; /* For Preview */
11088 +}
11089 +
11090 +static void camif_auto_restart(camif_cfg_t *cfg)
11091 +{
11092 +//     if (cfg->dma_type & CAMIF_CODEC) return;
11093 +       if (cfg->auto_restart)
11094 +               camif_start_p_with_c(cfg);
11095 +}
11096 +
11097 +
11098 +/* Supposed that PREVIEW already running
11099 + * request PREVIEW to start with Codec
11100 + */
11101 +static int camif_check_global(camif_cfg_t *cfg)
11102 +{
11103 +       int ret = 0;
11104 +
11105 +        if (down_interruptible(&cfg->gc->lock))
11106 +                       return -ERESTARTSYS;
11107 +        if ( cfg->gc->status & CWANT2START ) {
11108 +               cfg->gc->status &= ~CWANT2START;
11109 +               cfg->auto_restart = 1;
11110 +               ret = 1;
11111 +       }
11112 +       else {
11113 +               ret = 0; /* There is no codec */
11114 +               cfg->auto_restart = 0; /* Duplicated ..Dummy */
11115 +       }
11116 +
11117 +       up(&cfg->gc->lock);
11118 +
11119 +        return ret;
11120 +}
11121 +
11122 +/*
11123 + *    1nd INT : Start Interrupt
11124 + *    Xnd INT : enable Last IRQ : pingpong get the valid data
11125 + *    Ynd INT : Stop Codec or Preview : pingpong get the valid data
11126 + *    Znd INT : Last IRQ : valid data
11127 + */
11128 +#define CHECK_FREQ 5
11129 +int camif_enter_p_4fsm(camif_cfg_t *cfg)
11130 +{
11131 +       int ret = 0;
11132 +
11133 +       cfg->perf.frames++;
11134 +       if (cfg->fsm == CAMIF_NORMAL_INT)
11135 +       if (cfg->perf.frames % CHECK_FREQ == 0)
11136 +               ret = camif_check_global(cfg);
11137 +       if (ret > 0) cfg->fsm = CAMIF_Xnd_INT; /* Codec wait for Preview */
11138 +
11139 +       switch (cfg->fsm) {
11140 +               case CAMIF_1nd_INT:           /* Start IRQ */
11141 +                       cfg->fsm = CAMIF_NORMAL_INT;
11142 +                       ret = INSTANT_SKIP;
11143 +                       DPRINTK(KERN_INFO "1nd INT \n");
11144 +                       break;
11145 +               case CAMIF_NORMAL_INT:
11146 +                       cfg->status = CAMIF_INT_HAPPEN;
11147 +                       cfg->fsm = CAMIF_NORMAL_INT;
11148 +                       ret = INSTANT_GO;
11149 +                       DPRINTK(KERN_INFO "NORMAL INT \n");
11150 +                       break;
11151 +               case CAMIF_Xnd_INT:
11152 +                       camif_last_irq_en(cfg);/* IRQ for Enabling LAST IRQ */
11153 +                       cfg->status = CAMIF_INT_HAPPEN;
11154 +                       cfg->fsm = CAMIF_Ynd_INT;
11155 +                       ret = INSTANT_GO;
11156 +                       DPRINTK(KERN_INFO "Xnd INT \n");
11157 +                       break;
11158 +               case CAMIF_Ynd_INT:        /* Capture Stop */
11159 +                       cfg->exec = CAMIF_DMA_OFF;
11160 +                       cfg->status = CAMIF_INT_HAPPEN;
11161 +                       camif_capture_stop(cfg);
11162 +                       cfg->fsm = CAMIF_Znd_INT;
11163 +                       ret = INSTANT_GO;
11164 +                       DPRINTK(KERN_INFO "Ynd INT \n");
11165 +                       break;
11166 +               case CAMIF_Znd_INT:             /*  LAST IRQ (Dummy IRQ */
11167 +                       cfg->fsm = CAMIF_DUMMY_INT;
11168 +                       cfg->status = CAMIF_INT_HAPPEN;
11169 +                       ret = INSTANT_GO;
11170 +                       camif_auto_restart(cfg);  /* Automatically Restart Camera */
11171 +                       DPRINTK(KERN_INFO "Znd INT \n");
11172 +                       break;
11173 +               case CAMIF_DUMMY_INT:
11174 +                       cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
11175 +                       ret = INSTANT_SKIP;
11176 +//                     DPRINTK(KERN_INFO "Dummy INT \n");
11177 +                       break;
11178 +               default:
11179 +                       printk(KERN_INFO "Unexpect INT %d \n",cfg->fsm);
11180 +                       ret = INSTANT_SKIP;
11181 +                       break;
11182 +       }
11183 +       return ret;
11184 +}
11185 +
11186 +
11187 +/*
11188 + * NO autorestart included in this function
11189 + */
11190 +int camif_enter_c_4fsm(camif_cfg_t *cfg)
11191 +{
11192 +       int ret;
11193 +
11194 +       cfg->perf.frames++;
11195 +#if 0
11196 +       if (   (cfg->fsm==CAMIF_NORMAL_INT)
11197 +           && (cfg->perf.frames>cfg->restart_limit-1)
11198 +          )
11199 +               cfg->fsm = CAMIF_Xnd_INT;
11200 +#endif
11201 +       switch (cfg->fsm) {
11202 +               case CAMIF_1nd_INT:           /* Start IRQ */
11203 +                       cfg->fsm = CAMIF_NORMAL_INT;
11204 +//                     cfg->status = CAMIF_STARTED; /* need this to meet auto-restart */
11205 +                       ret = INSTANT_SKIP;
11206 +                       DPRINTK(KERN_INFO "1nd INT \n");
11207 +                       break;
11208 +               case CAMIF_NORMAL_INT:
11209 +                       cfg->status = CAMIF_INT_HAPPEN;
11210 +                       cfg->fsm = CAMIF_NORMAL_INT;
11211 +                       ret = INSTANT_GO;
11212 +                       DPRINTK(KERN_INFO "NORMALd INT \n");
11213 +                       break;
11214 +               case CAMIF_Xnd_INT:
11215 +                       camif_last_irq_en(cfg);/* IRQ for Enabling LAST IRQ */
11216 +                       cfg->status = CAMIF_INT_HAPPEN;
11217 +                       cfg->fsm = CAMIF_Ynd_INT;
11218 +                       ret = INSTANT_GO;
11219 +                       DPRINTK(KERN_INFO "Xnd INT \n");
11220 +                       break;
11221 +               case CAMIF_Ynd_INT:        /* Capture Stop */
11222 +                       cfg->exec = CAMIF_DMA_OFF;
11223 +                       cfg->status = CAMIF_INT_HAPPEN;
11224 +                       camif_capture_stop(cfg);
11225 +                       cfg->fsm = CAMIF_Znd_INT;
11226 +                       ret = INSTANT_GO;
11227 +                       DPRINTK(KERN_INFO "Ynd INT \n");
11228 +                       break;
11229 +               case CAMIF_Znd_INT:             /*  LAST IRQ (Dummy IRQ */
11230 +                       cfg->fsm = CAMIF_DUMMY_INT;
11231 +                       cfg->status = CAMIF_INT_HAPPEN;
11232 +                       ret = INSTANT_GO;
11233 +                       DPRINTK(KERN_INFO "Znd INT \n");
11234 +                       break;
11235 +               case CAMIF_DUMMY_INT:
11236 +                       cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
11237 +                       ret = INSTANT_SKIP;
11238 +                       break;
11239 +               default:
11240 +                       printk(KERN_INFO "Unexpect INT %d \n",cfg->fsm);
11241 +                       ret = INSTANT_SKIP;
11242 +                       break;
11243 +       }
11244 +       return ret;
11245 +}
11246 +
11247 +/* 4 Interrups State Machine is for two pingpong
11248 + *    1nd INT : Start Interrupt
11249 + *    Xnd INT : enable Last IRQ : pingpong get the valid data
11250 + *    Ynd INT : Stop Codec or Preview : pingpong get the valid data
11251 + *    Znd INT : Last IRQ : valid data
11252 + *
11253 + * Note:
11254 + *    Before calling this func, you must call camif_reset
11255 + */
11256 +
11257 +int camif_enter_2fsm(camif_cfg_t *cfg) /* Codec FSM */
11258 +{
11259 +       int ret;
11260 +
11261 +       cfg->perf.frames++;
11262 +       switch (cfg->fsm) {
11263 +               case CAMIF_1nd_INT:           /* Start IRQ */
11264 +                       cfg->fsm = CAMIF_Xnd_INT;
11265 +                       ret = INSTANT_SKIP;
11266 +//                     printk(KERN_INFO "1nd INT \n");
11267 +                       break;
11268 +               case CAMIF_Xnd_INT:
11269 +                       camif_last_irq_en(cfg);/* IRQ for Enabling LAST IRQ */
11270 +                       cfg->now_frame_num = 0;
11271 +                       cfg->status = CAMIF_INT_HAPPEN;
11272 +                       cfg->fsm = CAMIF_Ynd_INT;
11273 +                       ret = INSTANT_GO;
11274 +//                     printk(KERN_INFO "2nd INT \n");
11275 +                       break;
11276 +               case CAMIF_Ynd_INT:        /* Capture Stop */
11277 +                       cfg->exec = CAMIF_DMA_OFF;
11278 +                       cfg->now_frame_num = 1;
11279 +                       cfg->status = CAMIF_INT_HAPPEN;
11280 +                       camif_capture_stop(cfg);
11281 +                       cfg->fsm = CAMIF_Znd_INT;
11282 +                       ret = INSTANT_GO;
11283 +//                     printk(KERN_INFO "Ynd INT \n");
11284 +                       break;
11285 +               case CAMIF_Znd_INT:             /*  LAST IRQ (Dummy IRQ */
11286 +                       cfg->now_frame_num = 0;
11287 +//                     cfg->fsm = CAMIF_DUMMY_INT;
11288 +                       cfg->status = CAMIF_INT_HAPPEN;
11289 +                       ret = INSTANT_GO;
11290 +//                     printk(KERN_INFO "Znd INT \n");
11291 +                       break;
11292 +               case CAMIF_DUMMY_INT:
11293 +                       cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
11294 +                       ret = INSTANT_SKIP;
11295 +                       printk(KERN_INFO "Dummy INT \n");
11296 +                       break;
11297 +               default:  /* CAMIF_PENDING_INT */
11298 +                       printk(KERN_INFO "Unexpect INT \n");
11299 +                       ret = INSTANT_SKIP;
11300 +                       break;
11301 +       }
11302 +       return ret;
11303 +}
11304 +
11305 +
11306 +/* 2 Interrups State Machine is for one pingpong
11307 + *    1nd INT : Stop Codec or Preview : pingpong get the valid data
11308 + *    2nd INT : Last IRQ : dummy data
11309 + */
11310 +int camif_enter_1fsm(camif_cfg_t *cfg) /* Codec FSM */
11311 +{
11312 +       int ret;
11313 +
11314 +       cfg->perf.frames++;
11315 +       switch (cfg->fsm) {
11316 +               case CAMIF_Ynd_INT:             /* IRQ for Enabling LAST IRQ */
11317 +                       cfg->exec = CAMIF_DMA_OFF;
11318 +                       camif_capture_stop(cfg);
11319 +                       cfg->fsm = CAMIF_Znd_INT;
11320 +                       ret = INSTANT_SKIP;
11321 +       //              printk(KERN_INFO "Ynd INT \n");
11322 +                       break;
11323 +               case CAMIF_Znd_INT:             /*  LAST IRQ (Dummy IRQ */
11324 +                       cfg->fsm = CAMIF_DUMMY_INT;
11325 +                       cfg->status = CAMIF_INT_HAPPEN;
11326 +                       ret = INSTANT_GO;
11327 +       //              printk(KERN_INFO "Znd INT \n");
11328 +                       break;
11329 +               case CAMIF_DUMMY_INT:
11330 +                       cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
11331 +                       ret = INSTANT_SKIP;
11332 +                       printk(KERN_INFO "Dummy INT \n");
11333 +                       break;
11334 +               default:
11335 +                       printk(KERN_INFO "Unexpect INT \n");
11336 +                       ret = INSTANT_SKIP;
11337 +                       break;
11338 +       }
11339 +       return ret;
11340 +}
11341 +
11342 +
11343 +/*
11344 + *  GLOBAL STATUS CONTROL FUNCTION
11345 + *
11346 + */
11347 +
11348 +
11349 +/* Supposed that PREVIEW already running
11350 + * request PREVIEW to start with Codec
11351 + */
11352 +int camif_callback_start(camif_cfg_t *cfg)
11353 +{
11354 +        int  doit = 1;
11355 +        while (doit) {
11356 +                if (down_interruptible(&cfg->gc->lock)) {
11357 +                        return -ERESTARTSYS;
11358 +                }
11359 +                cfg->gc->status = CWANT2START;
11360 +                cfg->gc->other = cfg;
11361 +                up(&cfg->gc->lock);
11362 +                doit = 0;
11363 +        }
11364 +        return 0;
11365 +}
11366 +
11367 +/*
11368 + * Return status of Preview Machine
11369 +  ret value :
11370 +      0: Preview is not working
11371 +      X: Codec must follow PREVIEW start
11372 +*/
11373 +int camif_check_preview(camif_cfg_t *cfg)
11374 +{
11375 +        int ret = 0;
11376 +
11377 +        if (down_interruptible(&cfg->gc->lock)) {
11378 +                        ret = -ERESTARTSYS;
11379 +                        return ret;
11380 +        }
11381 +        if (cfg->gc->user == 1) ret = 0;
11382 +     //   else if (cfg->gc->status & PNOTWORKING) ret = 0;
11383 +        else ret = 1;
11384 +        up(&cfg->gc->lock);
11385 +        return ret;
11386 +}
11387 +
11388 +
11389 +
11390 +
11391 +/*
11392 + * Local variables:
11393 + * c-basic-offset: 8
11394 + * End:
11395 + */
11396 --- /dev/null
11397 +++ b/arch/arm/mach-s3c2440/camera/camif.h
11398 @@ -0,0 +1,304 @@
11399 +/*
11400 +    FIMC2.0  Camera Header File
11401 +
11402 +    Copyright (C) 2003 Samsung Electronics (SW.LEE: hitchcar@samsung.com)
11403 +
11404 +       Author : SW.LEE <hitchcar@samsung.com>
11405 +
11406 +    This program is free software; you can redistribute it and/or modify
11407 +    it under the terms of the GNU General Public License as published by
11408 +    the Free Software Foundation; either version 2 of the License, or
11409 +    (at your option) any later version.
11410 +*
11411 +*/
11412 +
11413 +
11414 +#ifndef __FIMC20_CAMIF_H_
11415 +#define __FIMC20_CAMIF_H_
11416 +
11417 +#ifdef __KERNEL__
11418 +
11419 +#include "bits.h"
11420 +#include "videodev.h"
11421 +#include <asm/types.h>
11422 +#include <linux/i2c.h>
11423 +
11424 +#endif  /* __KERNEL__ */
11425 +
11426 +#ifndef O_NONCAP
11427 +#define O_NONCAP O_TRUNC
11428 +#endif
11429 +
11430 +/* Codec or Preview Status */
11431 +#define CAMIF_STARTED         BIT1
11432 +#define CAMIF_STOPPED         BIT2
11433 +#define CAMIF_INT_HAPPEN      BIT3
11434 +
11435 +/* Codec or Preview  : Interrupt FSM */
11436 +#define CAMIF_1nd_INT         BIT7
11437 +#define CAMIF_Xnd_INT         BIT8
11438 +#define CAMIF_Ynd_INT         BIT9
11439 +#define CAMIF_Znd_INT         BIT10
11440 +#define CAMIF_NORMAL_INT      BIT11
11441 +#define CAMIF_DUMMY_INT       BIT12
11442 +#define CAMIF_PENDING_INT     0
11443 +
11444 +
11445 +/* CAMIF RESET Definition */
11446 +#define CAMIF_RESET           BIT0
11447 +#define CAMIF_EX_RESET_AL     BIT1     /* Active Low */
11448 +#define CAMIF_EX_RESET_AH     BIT2     /* Active High */
11449 +
11450 +
11451 +enum camif_itu_fmt {
11452 +       CAMIF_ITU601 = BIT31,
11453 +       CAMIF_ITU656 = 0
11454 +};
11455 +
11456 +/* It is possbie to use two device simultaneously */
11457 +enum camif_dma_type {
11458 +       CAMIF_PREVIEW = BIT0,
11459 +       CAMIF_CODEC   = BIT1,
11460 +};
11461 +
11462 +enum camif_order422 {
11463 +       CAMIF_YCBYCR = 0,
11464 +       CAMIF_YCRYCB = BIT14,
11465 +       CAMIF_CBYCRY = BIT15,
11466 +       CAMIF_CRYCBY = BIT14 | BIT15
11467 +};
11468 +
11469 +enum flip_mode {
11470 +        CAMIF_FLIP   = 0,
11471 +        CAMIF_FLIP_X = BIT14,
11472 +        CAMIF_FLIP_Y = BIT15,
11473 +        CAMIF_FLIP_MIRROR = BIT14 |BIT15,
11474 +};
11475 +
11476 +enum camif_codec_fmt {
11477 +       /* Codec part */
11478 +        CAMIF_IN_YCBCR420  = BIT0, /* Currently IN_YCBCR format fixed */
11479 +        CAMIF_IN_YCBCR422  = BIT1,
11480 +        CAMIF_OUT_YCBCR420 = BIT4,
11481 +        CAMIF_OUT_YCBCR422 = BIT5,
11482 +       /* Preview Part */
11483 +       CAMIF_RGB16        = BIT2,
11484 +       CAMIF_RGB24        = BIT3,
11485 +};
11486 +
11487 +enum camif_capturing {
11488 +        CAMIF_BOTH_DMA_ON  = BIT4,
11489 +       CAMIF_DMA_ON       = BIT3,
11490 +       CAMIF_BOTH_DMA_OFF = BIT1,
11491 +       CAMIF_DMA_OFF      = BIT0,
11492 +       /*------------------------*/
11493 +       CAMIF_DMA_OFF_L_IRQ= BIT5,
11494 +};
11495 +
11496 +typedef struct camif_performance
11497 +{
11498 +       int     frames;
11499 +       int     framesdropped;
11500 +       __u64   bytesin;
11501 +       __u64   bytesout;
11502 +       __u32   reserved[4];
11503 +} camif_perf_t;
11504 +
11505 +
11506 +typedef struct {
11507 +        dma_addr_t  phys_y;
11508 +        dma_addr_t  phys_cb;
11509 +        dma_addr_t  phys_cr;
11510 +        u8          *virt_y;
11511 +        u8          *virt_cb;
11512 +        u8          *virt_cr;
11513 +        dma_addr_t  phys_rgb;
11514 +        u8          *virt_rgb;
11515 +}img_buf_t;
11516 +
11517 +
11518 +/* this structure convers the CIWDOFFST, prescaler, mainscaler */
11519 +typedef struct {
11520 +       u32 modified_src_x;     /* After windows applyed to source_x */
11521 +       u32 modified_src_y;
11522 +       u32 hfactor;
11523 +       u32 vfactor;
11524 +       u32 shfactor;           /* SHfactor = 10 - ( hfactor + vfactor ) */
11525 +       u32 prehratio;
11526 +       u32 prevratio;
11527 +       u32 predst_x;
11528 +       u32 predst_y;
11529 +       u32 scaleup_h;
11530 +       u32 scaleup_v;
11531 +       u32 mainhratio;
11532 +       u32 mainvratio;
11533 +       u32 scalerbypass;       /* only codec */
11534 +} scaler_t;
11535 +
11536 +
11537 +enum v4l2_status {
11538 +        CAMIF_V4L2_INIT    = BIT0,
11539 +        CAMIF_v4L2_DIRTY   = BIT1,
11540 +};
11541 +
11542 +
11543 +/* Global Status Definition */
11544 +#define PWANT2START   BIT0
11545 +#define CWANT2START   BIT1
11546 +#define BOTH_STARTED  (PWANT2START|CWANT2START)
11547 +#define PNOTWORKING   BIT4
11548 +#define C_WORKING     BIT5
11549 +
11550 +typedef struct {
11551 +       struct semaphore         lock;
11552 +        enum camif_itu_fmt       itu_fmt;
11553 +        enum camif_order422      order422;
11554 +       u32                      win_hor_ofst;
11555 +       u32                      win_ver_ofst;
11556 +        u32                      camclk;  /* External Image Sensor Camera Clock */
11557 +        u32                      source_x;
11558 +        u32                      source_y;
11559 +       u32                      polarity_pclk;
11560 +       u32                      polarity_vsync;
11561 +       u32                      polarity_href;
11562 +       struct i2c_client        *sensor;
11563 +       u32                      user; /* MAX 2 (codec, preview) */
11564 +       u32                      old_priority; /* BUS PRIORITY register */
11565 +       u32                      status;
11566 +       u32                      init_sensor;/* initializing sensor */
11567 +       void                     *other;    /* Codec camif_cfg_t */
11568 +       u32                      reset_type;    /* External Sensor Reset  Type */
11569 +       u32                      reset_udelay;
11570 +} camif_gc_t;                  /* gobal control register */
11571 +
11572 +
11573 +/* when  App want to change v4l2 parameter,
11574 + * we instantly store it into v4l2_t v2
11575 + * and then reflect it to hardware
11576 + */
11577 +typedef struct v4l2 {
11578 +       struct v4l2_fmtdesc     *fmtdesc;
11579 +       struct v4l2_pix_format   fmt; /* current pixel format */
11580 +       struct v4l2_input        input;
11581 +        struct video_picture     picture;
11582 +       enum v4l2_status         status;
11583 +       int     used_fmt ;      /* used format index  */
11584 +} v4l2_t;
11585 +
11586 +
11587 +typedef struct camif_c_t {
11588 +        struct video_device      *v;
11589 +       /* V4L2 param only for v4l2 driver */
11590 +       v4l2_t                    v2;
11591 +       camif_gc_t               *gc; /* Common between Codec and Preview */
11592 +       /* logical parameter */
11593 +       wait_queue_head_t        waitq;
11594 +       u32                      status; /* Start/Stop */
11595 +       u32                      fsm; /* Start/Stop */
11596 +       u32                      open_count; /* duplicated */
11597 +       int                      irq;
11598 +       char                     shortname[16];
11599 +        u32                      target_x;
11600 +        u32                      target_y;
11601 +       scaler_t                 sc;
11602 +       enum flip_mode           flip;
11603 +        enum camif_dma_type      dma_type;
11604 +       /* 4 pingpong Frame memory */
11605 +        u8                       *pp_virt_buf;
11606 +        dma_addr_t               pp_phys_buf;
11607 +        u32                      pp_totalsize;
11608 +       u32                      pp_num; /* used pingpong memory number */
11609 +        img_buf_t                img_buf[4];
11610 +        enum camif_codec_fmt     fmt;
11611 +        enum camif_capturing     exec;
11612 +       camif_perf_t             perf;
11613 +       u32                      now_frame_num;
11614 +       u32                      auto_restart; /* Only For Preview */
11615 +} camif_cfg_t;
11616 +
11617 +#ifdef SW_DEBUG
11618 +#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
11619 +#else
11620 +#define DPRINTK(fmt, args...)
11621 +#endif
11622 +
11623 +
11624 +#ifdef SW_DEBUG
11625 +#define assert(expr) \
11626 +        if(!(expr)) {                                   \
11627 +        printk( "Assertion failed! %s,%s,%s,line=%d\n", \
11628 +        #expr,__FILE__,__FUNCTION__,__LINE__);          \
11629 +        }
11630 +#else
11631 +#define assert(expr)
11632 +#endif
11633 +
11634 +
11635 +
11636 +extern int camif_capture_start(camif_cfg_t *);
11637 +extern int camif_capture_stop(camif_cfg_t *);
11638 +extern int camif_g_frame_num(camif_cfg_t *);
11639 +extern u8 * camif_g_frame(camif_cfg_t *);
11640 +extern int  camif_win_offset(camif_gc_t *);
11641 +extern void camif_hw_open(camif_gc_t *);
11642 +extern void camif_hw_close(camif_cfg_t *);
11643 +extern int camif_dynamic_open(camif_cfg_t *);
11644 +extern int camif_dynamic_close(camif_cfg_t *);
11645 +extern void camif_reset(int,int);
11646 +extern void camif_setup_sensor(void);
11647 +extern int camif_g_fifo_status(camif_cfg_t *);
11648 +extern void camif_last_irq_en(camif_cfg_t *);
11649 +extern void camif_change_flip(camif_cfg_t *);
11650 +
11651 +
11652 +/* Todo
11653 + *  API Interface function to both Character and V4L2 Drivers
11654 + */
11655 +extern int camif_do_write(struct file *,const char *, size_t, loff_t *);
11656 +extern int camif_do_ioctl(struct inode *, struct file *,unsigned int, void *);
11657 +
11658 +
11659 +/*
11660 + * API for Decoder (S5x532, OV7620..)
11661 + */
11662 +void camif_register_decoder(struct i2c_client *);
11663 +void camif_unregister_decoder(struct i2c_client*);
11664 +
11665 +
11666 +
11667 +/* API for FSM */
11668 +#define INSTANT_SKIP 0
11669 +#define INSTANT_GO   1
11670 +
11671 +extern ssize_t camif_p_1fsm_start(camif_cfg_t *);
11672 +extern ssize_t camif_p_2fsm_start(camif_cfg_t *);
11673 +extern ssize_t camif_4fsm_start(camif_cfg_t *);
11674 +extern ssize_t camif_p_stop(camif_cfg_t *);
11675 +extern int camif_enter_p_4fsm(camif_cfg_t *);
11676 +extern int camif_enter_c_4fsm(camif_cfg_t *);
11677 +extern int camif_enter_2fsm(camif_cfg_t *);
11678 +extern int camif_enter_1fsm(camif_cfg_t *);
11679 +extern int camif_check_preview(camif_cfg_t *);
11680 +extern int camif_callback_start(camif_cfg_t *);
11681 +extern int camif_clock_init(camif_gc_t *);
11682 +
11683 +/*
11684 + *  V4L2 Part
11685 + */
11686 +#define VID_HARDWARE_SAMSUNG_FIMC20   236
11687 +
11688 +
11689 +
11690 +
11691 +
11692 +#endif
11693 +
11694 +
11695 +/*
11696 + * Local variables:
11697 + * tab-width: 8
11698 + *  c-indent-level: 8
11699 + *  c-basic-offset: 8
11700 + *  c-set-style: "K&R"
11701 + * End:
11702 + */
11703 --- /dev/null
11704 +++ b/arch/arm/mach-s3c2440/camera/cam_reg.h
11705 @@ -0,0 +1,234 @@
11706 + /*----------------------------------------------------------
11707 +  *   (C) 2004 Samsung Electronics
11708 +  *   SW.LEE < hitchcar@samsung.com>
11709 +  *
11710 +  ----------------------------------------------------------- */
11711 +
11712 +#ifndef __FIMC20_CAMERA_H__
11713 +#define __FIMC20_CAMERA_H__
11714 +
11715 +extern u32 * camregs;
11716 +
11717 +#ifdef CONFIG_ARCH_S3C24A0
11718 +#define CAM_BASE_ADD             0x48000000
11719 +#else /* S3C2440A */
11720 +#define CAM_BASE_ADD             0x4F000000
11721 +#endif
11722 +
11723 +#if ! defined(FExtr)
11724 +#define UData(Data)     ((unsigned long) (Data))
11725 +#define FExtr(Data, Field) \
11726 +                        ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
11727 +#define FInsrt(Value, Field) \
11728 +                        (UData (Value) << FShft (Field))
11729 +#define FSize(Field)    ((Field) >> 16)
11730 +#define FShft(Field)    ((Field) & 0x0000FFFF)
11731 +#define FMsk(Field)     (((UData (1) << FSize (Field)) - 1) << FShft (Field))
11732 +#define FAlnMsk(Field)  ((UData (1) << FSize (Field)) - 1)
11733 +#define F1stBit(Field)  (UData (1) << FShft (Field))
11734 +#define Fld(Size, Shft) (((Size) << 16) + (Shft))
11735 +#endif
11736 +
11737 +/*
11738 + * CAMERA IP
11739 + * P-port is used as RGB Capturing device which including scale and crop
11740 + *  those who want to see(preview ) the image on display needs RGB image.
11741 + *
11742 + * C-port is used as YCbCr(4:2:0, 4:2:2) Capturing device which including the scale and crop
11743 + *   the prefix of C-port have the meaning of "Codec" ex. mpeg4, h263.. which requries the
11744 +     YCBCB format not RGB
11745 + */
11746 +
11747 +#define S3C2440_CAM_REG_CISRCFMT            (0x00) // RW Input Source Format
11748 +#define S3C2440_CAM_REG_CIWDOFST            (0x04) // Window offset register
11749 +#define S3C2440_CAM_REG_CIGCTRL             (0x08) // Global control register
11750 +#define S3C2440_CAM_REG_CICOYSA0            (0x18) // Y 1 st frame start ads
11751 +#define S3C2440_CAM_REG_CICOYSA1            (0x1C) // Y 2 nd frame start ads
11752 +#define S3C2440_CAM_REG_CICOYSA2            (0x20) // Y 3 rd frame start ads
11753 +#define S3C2440_CAM_REG_CICOYSA3            (0x24) // Y 4 th frame start ads
11754 +#define S3C2440_CAM_REG_CICOCBSA0           (0x28) // Cb 1 st frame start ads
11755 +#define S3C2440_CAM_REG_CICOCBSA1           (0x2C) // Cb 2 nd frame start ads
11756 +#define S3C2440_CAM_REG_CICOCBSA2           (0x30) // Cb 3 rd frame start ads
11757 +#define S3C2440_CAM_REG_CICOCBSA3           (0x34) // Cb 4 th frame start ads
11758 +#define S3C2440_CAM_REG_CICOCRSA0           (0x38) // Cr 1 st frame start ads
11759 +#define S3C2440_CAM_REG_CICOCRSA1           (0x3C) // Cr 2 nd frame start ads
11760 +#define S3C2440_CAM_REG_CICOCRSA2           (0x40) // Cr 3 rd frame start ads
11761 +#define S3C2440_CAM_REG_CICOCRSA3           (0x44) // Cr 4 th frame start ads
11762 +#define S3C2440_CAM_REG_CICOTRGFMT          (0x48) // Target img format of codec
11763 +#define S3C2440_CAM_REG_CICOCTRL            (0x4C) // Codec DMA control related
11764 +#define S3C2440_CAM_REG_CICOSCPRERATIO      (0x50) // Codec pre-scaler ratio
11765 +#define S3C2440_CAM_REG_CICOSCPREDST        (0x54) // Codec pre-scaler dest
11766 +#define S3C2440_CAM_REG_CICOSCCTRL          (0x58) // Codec main-scaler control
11767 +#define S3C2440_CAM_REG_CICOTAREA           (0x5C) // Codec pre-scaler dest
11768 +#define S3C2440_CAM_REG_CICOSTATUS          (0x64) // Codec path status
11769 +#define S3C2440_CAM_REG_CIPRCLRSA0          (0x6C) // RGB 1 st frame start ads
11770 +#define S3C2440_CAM_REG_CIPRCLRSA1          (0x70) // RGB 2 nd frame start ads
11771 +#define S3C2440_CAM_REG_CIPRCLRSA2          (0x74) // RGB 3 rd frame start ads
11772 +#define S3C2440_CAM_REG_CIPRCLRSA3          (0x78) // RGB 4 th frame start ads
11773 +#define S3C2440_CAM_REG_CIPRTRGFMT          (0x7C) // Target img fmt of preview
11774 +#define S3C2440_CAM_REG_CIPRCTRL            (0x80) // Preview DMA ctl related
11775 +#define S3C2440_CAM_REG_CIPRSCPRERATIO      (0x84) // Preview pre-scaler ratio
11776 +#define S3C2440_CAM_REG_CIPRSCPREDST        (0x88) // Preview pre-scaler dest
11777 +#define S3C2440_CAM_REG_CIPRSCCTRL          (0x8C) // Preview main-scaler ctl
11778 +#define S3C2440_CAM_REG_CIPRTAREA           (0x90) // Preview pre-scaler dest
11779 +#define S3C2440_CAM_REG_CIPRSTATUS          (0x98) // Preview path status
11780 +#define S3C2440_CAM_REG_CIIMGCPT            (0xA0) // Image capture enable cmd
11781 +
11782 +#define S3C2440_CAM_REG_CICOYSA(__x)        (0x18 + (__x)*4 )
11783 +#define S3C2440_CAM_REG_CICOCBSA(__x)       (0x28 + (__x)*4 )
11784 +#define S3C2440_CAM_REG_CICOCRSA(__x)       (0x38 + (__x)*4 )
11785 +#define S3C2440_CAM_REG_CIPRCLRSA(__x)      (0x6C + (__x)*4 )
11786 +
11787 +/* CISRCFMT BitField */
11788 +#define SRCFMT_ITU601       BIT31
11789 +#define SRCFMT_ITU656       0
11790 +#define SRCFMT_UVOFFSET_128 BIT30
11791 +#define fCAM_SIZE_H         Fld(13, 16)
11792 +#define fCAM_SIZE_V         Fld(13, 0)
11793 +#define SOURCE_HSIZE(x)     FInsrt((x), fCAM_SIZE_H)
11794 +#define SOURCE_VSIZE(x)     FInsrt((x), fCAM_SIZE_V)
11795 +
11796 +
11797 +/* Window Option Register */
11798 +#define WINOFEN             BIT31
11799 +#define CO_FIFO_Y           BIT30
11800 +#define CO_FIFO_CB          BIT15
11801 +#define CO_FIFO_CR          BIT14
11802 +#define PR_FIFO_CB          BIT13
11803 +#define PR_FIFO_CR          BIT12
11804 +#define fWINHOR             Fld(11, 16)
11805 +#define fWINVER             Fld(11, 0)
11806 +#define WINHOROFST(x)       FInsrt((x), fWINHOR)
11807 +#define WINVEROFST(x)       FInsrt((x), fWINVER)
11808 +
11809 +/* Global Control Register */
11810 +#define GC_SWRST            BIT31
11811 +#define GC_CAMRST           BIT30
11812 +#define GC_INVPOLPCLK       BIT26
11813 +#define GC_INVPOLVSYNC      BIT25
11814 +#define GC_INVPOLHREF       BIT24
11815 +
11816 +/*--------------------------------------------------
11817 +                REGISTER BIT FIELD DEFINITION TO
11818 +                          YCBCR and RGB
11819 +----------------------------------------------------*/
11820 +/* Codec Target Format Register */
11821 +#define IN_YCBCR420         0
11822 +#define IN_YCBCR422         BIT31
11823 +#define OUT_YCBCR420        0
11824 +#define OUT_YCBCR422        BIT30
11825 +
11826 +#if 0
11827 +#define FLIP_NORMAL        0
11828 +#define FLIP_X              (BIT14)
11829 +#define FLIP_Y              (BIT15)
11830 +#define FLIP_MIRROR         (BIT14|BIT15)
11831 +#endif
11832 +
11833 +/**  BEGIN    ************************************/
11834 +/* Cotents: Common in both P and C port          */
11835 +#define fTARGET_HSIZE       Fld(13,16)
11836 +#define TARGET_HSIZE(x)     FInsrt((x), fTARGET_HSIZE)
11837 +#define fTARGET_VSIZE       Fld(13,0)
11838 +#define TARGET_VSIZE(x)     FInsrt((x), fTARGET_VSIZE)
11839 +#define FLIP_X_MIRROR       BIT14
11840 +#define FLIP_Y_MIRROR       BIT15
11841 +#define FLIP_180_MIRROR     (BIT14 | BIT15)
11842 +/**  END     *************************************/
11843 +
11844 +/* Codec DMA Control Register */
11845 +#define fYBURST_M           Fld(5,19)
11846 +#define fYBURST_R           Fld(5,14)
11847 +#define fCBURST_M           Fld(5,9)
11848 +#define fCBURST_R           Fld(5,4)
11849 +#define YBURST_M(x)         FInsrt((x), fYBURST_M)
11850 +#define CBURST_M(x)         FInsrt((x), fCBURST_M)
11851 +#define YBURST_R(x)         FInsrt((x), fYBURST_R)
11852 +#define CBURST_R(x)         FInsrt((x), fCBURST_R)
11853 +#define LAST_IRQ_EN         BIT2              /* Common in both P and C port */
11854 +/*
11855 + *  Check the done signal of capturing image for JPEG
11856 + *  !!! AutoClear Bit
11857 + */
11858 +
11859 +
11860 +/* (Codec, Preview ) Pre-Scaler Control Register 1 */
11861 +#define fSHIFT              Fld(4,28)
11862 +#define PRE_SHIFT(x)        FInsrt((x), fSHIFT)
11863 +#define fRATIO_H            Fld(7,16)
11864 +#define PRE_HRATIO(x)       FInsrt((x), fRATIO_H)
11865 +#define fRATIO_V            Fld(7,0)
11866 +#define PRE_VRATIO(x)       FInsrt((x), fRATIO_V)
11867 +
11868 +/* (Codec, Preview ) Pre-Scaler Control Register 2*/
11869 +#define fDST_WIDTH          Fld(12,16)
11870 +#define fDST_HEIGHT         Fld(12,0)
11871 +#define PRE_DST_WIDTH(x)    FInsrt((x), fDST_WIDTH)
11872 +#define PRE_DST_HEIGHT(x)   FInsrt((x), fDST_HEIGHT)
11873 +
11874 +
11875 +/* (Codec, Preview) Main-scaler control Register */
11876 +#define S_METHOD            BIT31  /* Sampling method only for P-port */
11877 +#define SCALERSTART         BIT15
11878 +/* Codec scaler bypass for upper 2048x2048
11879 +   where ImgCptEn_CoSC and ImgCptEn_PrSC should be 0
11880 +*/
11881 +
11882 +#define SCALERBYPASS        BIT31
11883 +#define RGB_FMT24           BIT30
11884 +#define RGB_FMT16           0
11885 +
11886 +/*
11887 +#define SCALE_UP_H          BIT29
11888 +#define SCALE_UP_V          BIT28
11889 +*/
11890 +
11891 +#define fMAIN_HRATIO        Fld(9, 16)
11892 +#define MAIN_HRATIO(x)      FInsrt((x), fMAIN_HRATIO)
11893 +
11894 +#define SCALER_START        BIT15
11895 +
11896 +#define fMAIN_VRATIO        Fld(9, 0)
11897 +#define MAIN_VRATIO(x)      FInsrt((x), fMAIN_VRATIO)
11898 +
11899 +/* (Codec, Preview ) DMA Target AREA Register */
11900 +#define fCICOTAREA          Fld(26,0)
11901 +#define TARGET_DMA_AREA(x)  FInsrt((x), fCICOTAREA)
11902 +
11903 +/* Preview DMA Control Register */
11904 +#define fRGBURST_M          Fld(5,19)
11905 +#define fRGBURST_R          Fld(5,14)
11906 +#define RGBURST_M(x)        FInsrt((x), fRGBURST_M)
11907 +#define RGBURST_R(x)        FInsrt((x), fRGBURST_R)
11908 +
11909 +
11910 +/* (Codec, Preview) Status Register */
11911 +#define CO_OVERFLOW_Y       BIT31
11912 +#define CO_OVERFLOW_CB      BIT30
11913 +#define CO_OVERFLOW_CR      BIT29
11914 +#define PR_OVERFLOW_CB      BIT31
11915 +#define PR_OVERFLOW_CR      BIT30
11916 +
11917 +#define VSYNC               BIT28
11918 +
11919 +#define fFRAME_CNT          Fld(2,26)
11920 +#define FRAME_CNT(x)        FExtr((x),fFRAME_CNT)
11921 +
11922 +#define WIN_OFF_EN          BIT25
11923 +#define fFLIP_MODE          Fld(2,23)
11924 +#define FLIP_MODE(x)        EExtr((x), fFLIP_MODE)
11925 +#define CAP_STATUS_CAMIF    BIT22
11926 +#define CAP_STATUS_CODEC    BIT21
11927 +#define CAP_STATUS_PREVIEW  BIT21
11928 +#define VSYNC_A             BIT20
11929 +#define VSYNC_B             BIT19
11930 +
11931 +/* Image Capture Enable Regiser */
11932 +#define        CAMIF_CAP_ON         BIT31
11933 +#define CAMIF_CAP_CODEC_ON   BIT30
11934 +#define CAMIF_CAP_PREVIEW_ON BIT29
11935 +
11936 +
11937 +
11938 +
11939 +#endif /* S3C2440_CAMER_H */
11940 --- /dev/null
11941 +++ b/arch/arm/mach-s3c2440/camera/imgsensor.c
11942 @@ -0,0 +1,250 @@
11943 +/*
11944 + *  Copyright (C) 2004 Samsung Electronics
11945 + *             SW.LEE <hitchcar@samsung.com>
11946 + *
11947 + *  Copyright (C) 2000 Russell King : pcf8583.c
11948 + *
11949 + * This program is free software; you can redistribute it and/or modify
11950 + * it under the terms of the GNU General Public License version 2 as
11951 + * published by the Free Software Foundation.
11952 + *
11953 + *  Driver for FIMC20 Camera Decoder
11954 + */
11955 +
11956 +
11957 +#include <linux/module.h>
11958 +#include <linux/kernel.h>
11959 +#include <linux/init.h>
11960 +#include <linux/i2c.h>
11961 +#include <linux/slab.h>
11962 +#include <linux/string.h>
11963 +#include <linux/init.h>
11964 +#include <linux/delay.h>
11965 +
11966 +
11967 +#ifdef CONFIG_ARCH_S3C24A0A
11968 +#else
11969 +//#include <asm/arch/S3C2440.h>
11970 +#endif
11971 +
11972 +#define SW_DEBUG
11973 +#define CONFIG_VIDEO_V4L1_COMPAT
11974 +#include <linux/videodev.h>
11975 +#include "camif.h"
11976 +#include "sensor.h"
11977 +
11978 +#ifndef SAMSUNG_SXGA_CAM
11979 +#include "s5x532_rev36.h"
11980 +#else
11981 +#include "sxga.h"
11982 +#endif
11983 +
11984 +static struct i2c_driver s5x532_driver;
11985 +static camif_gc_t data = {
11986 +       itu_fmt:      CAMIF_ITU601,
11987 +       order422:     CAMIF_YCBYCR,
11988 +       camclk:       24000000,
11989 +#ifndef SAMSUNG_SXGA_CAM
11990 +       source_x:     640,
11991 +       source_y:     480,
11992 +       win_hor_ofst: 112,
11993 +       win_ver_ofst: 20,
11994 +#else
11995 +       source_x:     1280,
11996 +       source_y:     1024,
11997 +       win_hor_ofst: 0,
11998 +       win_ver_ofst: 0,
11999 +#endif
12000 +       polarity_pclk:1,
12001 +       polarity_href:0,
12002 +#ifdef CONFIG_ARCH_S3C24A0A
12003 +       reset_type:CAMIF_EX_RESET_AL, /* Active Low */
12004 +#else
12005 +       reset_type:CAMIF_EX_RESET_AH, /* Ref board has inverted signal */
12006 +#endif
12007 +       reset_udelay:2000,
12008 +};
12009 +
12010 +#define CAM_ID 0x5a
12011 +
12012 +static unsigned short ignore = I2C_CLIENT_END;
12013 +static unsigned short normal_addr[] = { (CAM_ID>>1), I2C_CLIENT_END };
12014 +static struct i2c_client_address_data addr_data = {
12015 +       normal_i2c:             normal_addr,
12016 +       probe:                  &ignore,
12017 +       ignore:                 &ignore,
12018 +};
12019 +
12020 +s5x532_t s5x532_regs_mirror[S5X532_REGS];
12021 +
12022 +unsigned char
12023 +s5x532_read(struct i2c_client *client, unsigned char subaddr)
12024 +{
12025 +       int ret;
12026 +       unsigned char buf[1];
12027 +       struct i2c_msg msg ={ client->addr, 0, 1, buf};
12028 +       buf[0] = subaddr;
12029 +
12030 +       ret = i2c_transfer(client->adapter,&msg, 1) == 1 ? 0 : -EIO;
12031 +       if (ret == -EIO) {
12032 +         printk(" I2C write Error \n");
12033 +         return -EIO;
12034 +       }
12035 +
12036 +       msg.flags = I2C_M_RD;
12037 +       ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
12038 +
12039 +       return buf[0];
12040 +}
12041 +
12042 +
12043 +static int
12044 +s5x532_write(struct i2c_client *client,
12045 +                 unsigned char subaddr, unsigned char val)
12046 +{
12047 +       unsigned char buf[2];
12048 +       struct i2c_msg msg = { client->addr, 0, 2, buf};
12049 +
12050 +       buf[0]= subaddr;
12051 +       buf[1]= val;
12052 +
12053 +       return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
12054 +}
12055 +
12056 +void inline s5x532_init(struct i2c_client *sam_client)
12057 +{
12058 +       int i;
12059 +
12060 +       printk(KERN_ERR "s5x532_init  \n");
12061 +       for (i = 0; i < S5X532_INIT_REGS; i++) {
12062 +               s5x532_write(sam_client,
12063 +                             s5x532_reg[i].subaddr, s5x532_reg[i].value );
12064 +       }
12065 +
12066 +#ifdef YOU_WANT_TO_CHECK_IMG_SENSOR
12067 +       for (i = 0; i < S5X532_INIT_REGS;i++) {
12068 +               if ( s5x532_reg[i].subaddr == PAGE_ADDRESS ) {
12069 +                       s5x532_write(sam_client,
12070 +                             s5x532_reg[i].subaddr, s5x532_reg[i].value);
12071 +
12072 +                       printk(KERN_ERR "Page: Subaddr %02x = 0x%02x\n",
12073 +                              s5x532_reg[i].subaddr, s5x532_regs_mirror[i].value);
12074 +
12075 +
12076 +               } else
12077 +               {
12078 +                       s5x532_regs_mirror[i].subaddr = s5x532_reg[i].subaddr;
12079 +                       s5x532_regs_mirror[i].value =
12080 +                       s5x532_read(sam_client,s5x532_reg[i].subaddr);
12081 +                       printk(KERN_ERR "Subaddr %02x = 0x%02x\n",
12082 +                              s5x532_reg[i].subaddr, s5x532_regs_mirror[i].value);
12083 +               }
12084 +       }
12085 +#endif
12086 +
12087 +}
12088 +
12089 +static int
12090 +s5x532_attach(struct i2c_adapter *adap, int addr, int kind)
12091 +{
12092 +       struct i2c_client *c;
12093 +
12094 +       c = kmalloc(sizeof(*c), GFP_KERNEL);
12095 +       if (!c) return -ENOMEM;
12096 +
12097 +       strcpy(c->name, "S5X532");
12098 +//     c->id           = s5x532_driver.id;
12099 +       c->flags        = 0 /* I2C_CLIENT_ALLOW_USE */;
12100 +       c->addr         = addr;
12101 +       c->adapter      = adap;
12102 +       c->driver       = &s5x532_driver;
12103 +       data.sensor     = c;
12104 +       i2c_set_clientdata(c, &data);
12105 +
12106 +       camif_register_decoder(c);
12107 +       return i2c_attach_client(c);
12108 +}
12109 +
12110 +static int s5x532_probe(struct i2c_adapter *adap)
12111 +{
12112 +       return i2c_probe(adap, &addr_data, s5x532_attach);
12113 +}
12114 +
12115 +static int s5x532_detach(struct i2c_client *client)
12116 +{
12117 +       i2c_detach_client(client);
12118 +       camif_unregister_decoder(client);
12119 +       return 0;
12120 +}
12121 +
12122 +static int
12123 +s5x532_command(struct i2c_client *client, unsigned int cmd, void *arg)
12124 +{
12125 +        switch (cmd) {
12126 +        case SENSOR_INIT:
12127 +                 s5x532_init(client);
12128 +                printk(KERN_INFO "CAMERA: S5X532 Sensor initialized\n");
12129 +                break;
12130 +       case USER_ADD:
12131 +               /* MOD_INC_USE_COUNT; uh.. 2.6 deals with this, old-timer */
12132 +               break;
12133 +       case USER_EXIT:
12134 +               /* MOD_DEC_USE_COUNT; */
12135 +               break;
12136 +/* Todo
12137 +       case SENSOR_BRIGHTNESS:
12138 +               change_sensor();
12139 +               break;
12140 +*/
12141 +       default:
12142 +               panic("Unexpect Sensor Command \n");
12143 +               break;
12144 +        }
12145 +       return 0;
12146 +}
12147 +
12148 +static struct i2c_driver s5x532_driver = {
12149 +       driver:         { name:         "S5X532" },
12150 +       id:             0, /* optional in i2c-id.h I2C_ALGO_S3C, */
12151 +       attach_adapter: s5x532_probe,
12152 +       detach_client:  s5x532_detach,
12153 +       command:        s5x532_command
12154 +};
12155 +
12156 +static void iic_gpio_port(void)
12157 +{
12158 +/*    FIXME: no gpio config for i2c !!!
12159 +#ifdef CONFIG_ARCH_S3C24A0A
12160 +#else
12161 +       GPECON &=  ~(0xf <<28);
12162 +       GPECON |=    0xa <<28;
12163 +#endif
12164 +*/
12165 +}
12166 +
12167 +static __init int camif_sensor_init(void)
12168 +{
12169 +        iic_gpio_port();
12170 +       return i2c_add_driver(&s5x532_driver);
12171 +}
12172 +
12173 +
12174 +static __init void camif_sensor_exit(void)
12175 +{
12176 +       i2c_del_driver(&s5x532_driver);
12177 +}
12178 +
12179 +module_init(camif_sensor_init)
12180 +module_exit(camif_sensor_exit)
12181 +
12182 +MODULE_AUTHOR("SW.LEE <hitchcar@sec.samsung.com>");
12183 +MODULE_DESCRIPTION("I2C Client Driver For Fimc2.0 MISC Driver");
12184 +MODULE_LICENSE("GPL");
12185 +
12186 +
12187 +
12188 +/*
12189 + * Local variables:
12190 + * c-basic-offset: 8
12191 + * End:
12192 + */
12193 --- /dev/null
12194 +++ b/arch/arm/mach-s3c2440/camera/Kconfig
12195 @@ -0,0 +1,7 @@
12196 +
12197 +config S3C2440_CAMERA
12198 +       bool "S3C24xx Camera interface"
12199 +       depends on ARCH_S3C2410
12200 +       help
12201 +         Camera driver for S3C2440 camera unit
12202 +
12203 --- /dev/null
12204 +++ b/arch/arm/mach-s3c2440/camera/Makefile
12205 @@ -0,0 +1,8 @@
12206 +obj-$(CONFIG_S3C2440_CAMERA) += \
12207 +       videodev.o \
12208 +       imgsensor.o \
12209 +       video-driver.o \
12210 +       camif.o \
12211 +       camif_fsm.o \
12212 +       qt-driver.o
12213 +
12214 --- /dev/null
12215 +++ b/arch/arm/mach-s3c2440/camera/miscdevice.h
12216 @@ -0,0 +1,18 @@
12217 +
12218 + /*----------------------------------------------------------
12219 +  *   (C) 2004 Samsung Electronics
12220 +  *   SW.LEE < hitchcar@samsung.com>
12221 +  *
12222 +  ----------------------------------------------------------- */
12223 +
12224 +#ifndef _LINUX_S3C_MISCDEVICE_H
12225 +#define _LINUX_S3C_MISCDEVICE_H
12226 +
12227 +#define CODEC_MINOR 212
12228 +#define PREVIEW_MINOR 213
12229 +
12230 +
12231 +
12232 +
12233 +
12234 +#endif
12235 --- /dev/null
12236 +++ b/arch/arm/mach-s3c2440/camera/qt-driver.c
12237 @@ -0,0 +1,172 @@
12238 +/*
12239 + * SW.LEE <hitchcar@samsung.com>
12240 + *
12241 + * This file is subject to the terms and conditions of the GNU General Public
12242 + * License 2. See the file COPYING in the main directory of this archive
12243 + * for more details.
12244 + */
12245 +
12246 +#include <linux/version.h>
12247 +#include <linux/module.h>
12248 +#include <linux/delay.h>
12249 +#include <linux/errno.h>
12250 +#include <linux/fs.h>
12251 +#include <linux/kernel.h>
12252 +#include <linux/major.h>
12253 +#include <linux/slab.h>
12254 +#include <linux/poll.h>
12255 +#include <linux/signal.h>
12256 +#include <linux/ioport.h>
12257 +#include <linux/sched.h>
12258 +#include <linux/types.h>
12259 +#include <linux/interrupt.h>
12260 +#include <linux/kmod.h>
12261 +#include <linux/vmalloc.h>
12262 +#include <linux/init.h>
12263 +#include <asm/io.h>
12264 +#include <asm/page.h>
12265 +#include <asm/irq.h>
12266 +#include <asm/semaphore.h>
12267 +#include <linux/miscdevice.h>
12268 +
12269 +//#define SW_DEBUG
12270 +
12271 +#define CONFIG_VIDEO_V4L1_COMPAT
12272 +#include <linux/videodev.h>
12273 +#include "camif.h"
12274 +#include "miscdevice.h"
12275 +#include "cam_reg.h"
12276 +#include "sensor.h"
12277 +#include "userapp.h"
12278 +
12279 +extern camif_cfg_t * get_camif(int nr);
12280 +
12281 +
12282 +/************************* Sharp Zarus API **************************
12283 +* refering to Camera Driver API for SL-5000D/SL-5600 revision 1.00
12284 +*                              April 11, 2002.
12285 +  SW.LEE <hitchcar@sec.samsung.com>
12286 +               I want to use Sharp Camera Application.
12287 +*
12288 +*/
12289 +
12290 +#define READ_MODE_STATUS       0x1
12291 +#define READ_MODE_IMAGE                0x0
12292 +#define CAPTURE_SPEED
12293 +#define        H_FLIP
12294 +#define V_FLIP
12295 +typedef enum sharp_readmode
12296 +{
12297 +        IMAGE = 0, STATUS = 1,
12298 +        FASTER = 0, BETTER = 2,
12299 +        XNOFLIP = 0, XFLIP = 4,
12300 +        YNOFLIP = 0, YFLIP = 8,
12301 +        AUTOMATICFLIP = -1
12302 +} ReadMode_t;
12303 +
12304 +
12305 +static struct sharp_param_t {
12306 +       ReadMode_t readMode;
12307 +       char CameraStatus[4];
12308 +} sharp_param = { STATUS, {'s','m','c','A'}};
12309 +
12310 +
12311 +camif_param_t qt_parm = { 640,480,240,320,16,0};
12312 +
12313 +static void setReadMode(const char *b,size_t count)
12314 +{
12315 +       int i =   *(b+2) - 48 ;
12316 +       if ( 4 == count ) {
12317 +               i = (*(b+3) - 48)  + i * 10;
12318 +       }
12319 +
12320 +       //      DPRINTK(" setReadMode %s conversion value %d \n",b , i);
12321 +       if ( i & STATUS ) {
12322 +       //      DPRINTK(" STATUS MODE \n");
12323 +               sharp_param.readMode = i;
12324 +       }
12325 +       else  {
12326 +       //      DPRINTK(" IMAGE MODE \n");
12327 +               sharp_param.readMode = i;
12328 +       }
12329 +}
12330 +
12331 +
12332 +
12333 +
12334 +extern ssize_t camif_p_read(struct file *, char *, size_t , loff_t *);
12335 +
12336 +ssize_t z_read(struct file *f, char *buf, size_t count, loff_t *pos)
12337 +{
12338 +       size_t end;
12339 +
12340 +       if (sharp_param.readMode & STATUS ) {
12341 +               buf[0] = sharp_param.CameraStatus[0];
12342 +               buf[1] = sharp_param.CameraStatus[1];
12343 +               buf[2] = sharp_param.CameraStatus[2];
12344 +               buf[3] = sharp_param.CameraStatus[3];
12345 +               end = 4;
12346 +               return end;
12347 +       }
12348 +       else {  /* Image ReadMode */
12349 +               /*
12350 +               if (( sharp_param.readMode & (BETTER|X  FLIP|YFLIP)))
12351 +                       DPRINTK("  Not Supporting BETTER|XFLIP|YFLIP\n");
12352 +               */
12353 +               return camif_p_read(f,buf,count,pos);
12354 +       }
12355 +}
12356 +
12357 +static void z_config(camif_cfg_t *cfg,int x, int y)
12358 +{
12359 +       cfg->target_x = x;
12360 +       cfg->target_y = y;
12361 +       cfg->fmt = CAMIF_RGB16;
12362 +       if (camif_dynamic_open(cfg)) {
12363 +               panic(" Eror Happens \n");
12364 +       }
12365 +}
12366 +
12367 +
12368 +ssize_t z_write(struct file *f, const char *b, size_t c, loff_t *pos)
12369 +{
12370 +       int array[5];
12371 +       int zoom = 1;
12372 +       camif_cfg_t *cfg;
12373 +
12374 +       cfg = get_camif(MINOR(f->f_dentry->d_inode->i_rdev));
12375 +//     DPRINTK(" param %s count %d \n",b, c );
12376 +
12377 +       switch(*b) {
12378 +       case 'M':
12379 +               setReadMode(b, c);
12380 +               break;
12381 +       case 'B':       /* Clear the latch flag of shutter button */
12382 +               DPRINTK("  clear latch flag of camera's shutter button\n");
12383 +               sharp_param.CameraStatus[0]='s';
12384 +               break;
12385 +       case 'Y':       /* I don't know how to set Shutter pressed */
12386 +               DPRINTK("  set latch flag n");
12387 +               sharp_param.CameraStatus[0]='S';
12388 +               break;
12389 +       case 'S':       /* Camera Image Resolution */
12390 +       case 'R':       /* Donot support Rotation */
12391 +       DPRINTK(" param %s count %d \n",b, c );
12392 +               get_options((char *)(b+2), 5, array);
12393 +               if ( array[3] == 512 ) zoom = 2;
12394 +               z_config(cfg, array[1] * zoom , array[2] * zoom );
12395 +               camif_4fsm_start(cfg);
12396 +               break;
12397 +       case 'C':
12398 +       DPRINTK(" param %s count %d \n",b, c );
12399 +               DPRINTK("  Start the camera to capture \n");
12400 +               sharp_param.CameraStatus[2]='C';
12401 +               camif_4fsm_start(cfg);
12402 +               break;
12403 +       default:
12404 +               printk("Unexpected  param %s count %d \n",b, c );
12405 +       }
12406 +
12407 +       return c;
12408 +}
12409 +
12410 --- /dev/null
12411 +++ b/arch/arm/mach-s3c2440/camera/qt.h
12412 @@ -0,0 +1,18 @@
12413 +/*
12414 + * SW.LEE <hitchcar@samsung.com>
12415 + *
12416 + * This file is subject to the terms and conditions of the GNU General Public
12417 + * License 2. See the file COPYING in the main directory of this archive
12418 + * for more details.
12419 + */
12420 +
12421 +#ifndef __Z_API_H_
12422 +#define __Z_API_H_
12423 +
12424 +extern ssize_t z_read(struct file *f, char *buf, size_t count, loff_t *pos);
12425 +extern ssize_t z_write(struct file *f, const char *b, size_t c, loff_t *pos);
12426 +
12427 +
12428 +
12429 +#endif
12430 +
12431 --- /dev/null
12432 +++ b/arch/arm/mach-s3c2440/camera/s5x532.h
12433 @@ -0,0 +1,143 @@
12434 +/*
12435 + * 2004 (C) Samsung Electronics
12436 + *  SW.LEE <hitchcar@sec.samsung.com>
12437 + * This file is subject to the terms and conditions of the GNU General Public
12438 + * License 2. See the file COPYING in the main directory of this archive
12439 + * for more details.
12440 + */
12441 +
12442 +
12443 +#ifndef _SMDK2440_S5X532_H_
12444 +#define _SMDK2440_S5X532_H_
12445 +
12446 +
12447 +#define CHIP_DELAY 0xFF
12448 +
12449 +typedef struct samsung_t{
12450 +       unsigned char subaddr;
12451 +       unsigned char value;
12452 +       unsigned char page;
12453 +} s5x532_t;
12454 +
12455 +s5x532_t s5x532_reg[] = {
12456 +       // page 5
12457 +       {0xec,0x05},
12458 +       {0x08,0x55,0x5},
12459 +       {0x0a,0x75,0x5},
12460 +       {0x0c,0x90,0x5},
12461 +       {0x0e,0x18,0x5},
12462 +       {0x12,0x09,0x5},
12463 +       {0x14,0x9d,0x5},
12464 +       {0x16,0x90,0x5},
12465 +       {0x1a,0x18,0x5},
12466 +       {0x1c,0x0c,0x5},
12467 +       {0x1e,0x09,0x5},
12468 +       {0x20,0x06,0x5},
12469 +       {0x22,0x20,0x5},
12470 +       {0x2a,0x00,0x5},
12471 +       {0x2d,0x04,0x5},
12472 +       {0x12,0x24,0x5},
12473 +       // page 3
12474 +       {0xec,0x03,0x3},
12475 +       {0x0c,0x09,0x3},
12476 +       {0x6c,0x09,0x3},
12477 +       {0x2b,0x10,0x3}, // momo clock inversion
12478 +       // page 2
12479 +       {0xec,0x02,0x2},
12480 +       {0x03,0x09,0x2},
12481 +       {0x05,0x08,0x2},
12482 +       {0x06,0x01,0x2},
12483 +       {0x07,0xf8,0x2},
12484 +       {0x15,0x25,0x2},
12485 +       {0x30,0x29,0x2},
12486 +       {0x36,0x12,0x2},
12487 +       {0x38,0x04,0x2},
12488 +       {0x1b,0x77,0x2}, // 24MHz : 0x77, 12MHz : 0x22
12489 +       {0x1c,0x77,0x2}, // 24MHz : 0x77, 12MHz : 0x22
12490 +       // page 1
12491 +       {0xec,0x01,0x1},
12492 +       {0x00,0x03,0x1}, //
12493 +       {0x0a,0x08,0x1}, // 0x0-QQVGA, 0x06-CIF, 0x02-QCIF, 0x08-VGA, 0x04-QVGA, 0x0a-SXGA
12494 +       {0x0c,0x00,0x1}, // Pattern selectio. 0-CIS, 1-Color bar, 2-Ramp, 3-Blue screen
12495 +       {0x10,0x27,0x1},
12496 +       // 0x21-ITU-R656(CrYCbY), 0x25-ITU-R601(CrYCbY), 0x26-ITU-R601(YCbYCr)
12497 +       {0x50,0x21,0x1},                // Hblank
12498 +       {0x51,0x00,0x1},                // Hblank
12499 +       {0x52,0xA1,0x1},                // Hblank
12500 +       {0x53,0x02,0x1},                // Hblank
12501 +       {0x54,0x01,0x1},                // Vblank
12502 +       {0x55,0x00,0x1},                // Vblank
12503 +       {0x56,0xE1,0x1},                // Vblank
12504 +       {0x57,0x01,0x1},                // Vblank
12505 +       {0x58,0x21,0x1},                // Hsync
12506 +       {0x59,0x00,0x1},                // Hsync
12507 +       {0x5a,0xA1,0x1},                // Hsync
12508 +       {0x5b,0x02,0x1},                // Hsync
12509 +       {0x5c,0x03,0x1},                // Vref
12510 +       {0x5d,0x00,0x1},                // Vref
12511 +       {0x5e,0x05,0x1},                // Vref
12512 +       {0x5f,0x00,0x1},                // Vref
12513 +       {0x70,0x0E,0x1},
12514 +       {0x71,0xD6,0x1},
12515 +       {0x72,0x30,0x1},
12516 +       {0x73,0xDB,0x1},
12517 +       {0x74,0x0E,0x1},
12518 +       {0x75,0xD6,0x1},
12519 +       {0x76,0x18,0x1},
12520 +       {0x77,0xF5,0x1},
12521 +       {0x78,0x0E,0x1},
12522 +       {0x79,0xD6,0x1},
12523 +       {0x7a,0x28,0x1},
12524 +       {0x7b,0xE6,0x1},
12525 +       {0x50,0x00,0x1},
12526 +       {0x5c,0x00,0x1},
12527 +
12528 +       // page 0
12529 +       {0xec,0x00,0x0},
12530 +       {0x79,0x01,0x0},
12531 +       {0x58,0x90,0x0},
12532 +       {0x59,0xA0,0x0},
12533 +       {0x5a,0x50,0x0},
12534 +       {0x5b,0x70,0x0},
12535 +       {0x5c,0xD0,0x0},
12536 +       {0x5d,0xC0,0x0},
12537 +       {0x5e,0x28,0x0},
12538 +       {0x5f,0x08,0x0},
12539 +       {0x50,0x90,0x0},
12540 +       {0x51,0xA0,0x0},
12541 +       {0x52,0x50,0x0},
12542 +       {0x53,0x70,0x0},
12543 +       {0x54,0xD0,0x0},
12544 +       {0x55,0xC0,0x0},
12545 +       {0x56,0x28,0x0},
12546 +       {0x57,0x00,0x0},
12547 +       {0x48,0x90,0x0},
12548 +       {0x49,0xA0,0x0},
12549 +       {0x4a,0x50,0x0},
12550 +       {0x4b,0x70,0x0},
12551 +       {0x4c,0xD0,0x0},
12552 +       {0x4d,0xC0,0x0},
12553 +       {0x4e,0x28,0x0},
12554 +       {0x4f,0x08,0x0},
12555 +       {0x72,0x82,0x0}, // main clock = 24MHz:0xd2, 16M:0x82, 12M:0x54
12556 +       {0x75,0x05,0x0} // absolute vertical mirror.  junon
12557 +
12558 +};
12559 +
12560 +
12561 +#define S5X532_INIT_REGS (sizeof(s5x532_reg)/sizeof(s5x532_reg[0]))
12562 +#define S5X532_RISC_REGS 0xEB
12563 +#define S5X532_ISP_REGS 0xFB /* S5C7323X */
12564 +#define S5X532_CIS_REGS 0x2F /* S5K437LA03 */
12565 +
12566 +
12567 +#define PAGE_ADDRESS      0xEC
12568 +
12569 +//#define S5X532_REGS (S5X532_RISC_REGS+S5X532_ISP_REGS+S5X532_CIS_REGS)
12570 +#define S5X532_REGS (0x1000)
12571 +
12572 +
12573 +
12574 +#endif
12575 +
12576 +
12577 --- /dev/null
12578 +++ b/arch/arm/mach-s3c2440/camera/s5x532_rev36.h
12579 @@ -0,0 +1,208 @@
12580 +/*
12581 + * 2004 (C) Samsung Electronics
12582 + *  SW.LEE <hitchcar@sec.samsung.com>
12583 + * This file is subject to the terms and conditions of the GNU General Public
12584 + * License 2. See the file COPYING in the main directory of this archive
12585 + * for more details.
12586 + */
12587 +
12588 +
12589 +#ifndef _SMDK2440_S5X532_H_
12590 +#define _SMDK2440_S5X532_H_
12591 +
12592 +
12593 +#define CHIP_DELAY 0xFF
12594 +
12595 +typedef struct samsung_t{
12596 +       unsigned char subaddr;
12597 +       unsigned char value;
12598 +       unsigned char page;
12599 +} s5x532_t;
12600 +
12601 +s5x532_t s5x532_reg[] = {
12602 +
12603 +       //=============== page0 ===============//
12604 +       {0xec,0x00,0x00},
12605 +       {0x02,0x00,0x00},
12606 +       {0x14,0x60,0x00},
12607 +       {0x15,0x60,0x00},
12608 +       {0x16,0x60,0x00},
12609 +       {0x1b,0x20,0x00},
12610 +       {0x1c,0x20,0x00},
12611 +       {0x1d,0x20,0x00},
12612 +       {0x1e,0x20,0x00},
12613 +       {0x72,0xdc,0x00},
12614 +       {0x73,0x11,0x00},
12615 +       {0x76,0x82,0x00},
12616 +       {0x77,0x90,0x00},
12617 +       {0x78,0x6c,0x00},
12618 +       {0x0a,0x02,0x00},
12619 +       {0x34,0x0d,0x00},
12620 +       {0x35,0x0a,0x00},
12621 +       {0x36,0x05,0x00},
12622 +       {0x37,0x05,0x00},
12623 +       {0x38,0x06,0x00},
12624 +       {0x39,0x08,0x00},
12625 +       {0x3A,0x0d,0x00},
12626 +       {0x3B,0x0d,0x00},
12627 +       {0x3C,0x18,0x00},
12628 +       {0x3D,0xE0,0x00},
12629 +       {0x3E,0x20,0x00},
12630 +       {0x66,0x02,0x00},
12631 +       {0x6c,0x40,0x00},
12632 +       {0x7c,0x01,0x00},
12633 +       {0x0D,0x24,0x00},
12634 +       {0x40,0x1B,0x00},
12635 +       {0x41,0x4F,0x00},
12636 +       {0x42,0x24,0x00},
12637 +       {0x43,0x3E,0x00},
12638 +       {0x44,0x32,0x00},
12639 +       {0x45,0x30,0x00},
12640 +       {0x48,0xa0,0x00},
12641 +       {0x49,0xd0,0x00},
12642 +       {0x4A,0x28,0x00},
12643 +       {0x4B,0x7d,0x00},
12644 +       {0x4C,0xd0,0x00},
12645 +       {0x4D,0xe0,0x00},
12646 +       {0x4E,0x1a,0x00},
12647 +       {0x4F,0xa0,0x00},
12648 +       {0x50,0xc0,0x00},
12649 +       {0x51,0xc0,0x00},
12650 +       {0x52,0x42,0x00},
12651 +       {0x53,0x7e,0x00},
12652 +       {0x54,0xc0,0x00},
12653 +       {0x55,0xf0,0x00},
12654 +       {0x56,0x1e,0x00},
12655 +       {0x57,0xe0,0x00},
12656 +       {0x58,0xc0,0x00},
12657 +       {0x59,0xa0,0x00},
12658 +       {0x5A,0x4a,0x00},
12659 +       {0x5B,0x7e,0x00},
12660 +       {0x5C,0xc0,0x00},
12661 +       {0x5D,0xf0,0x00},
12662 +       {0x5E,0x2a,0x00},
12663 +       {0x5F,0x10,0x00},
12664 +       {0x79,0x00,0x00},
12665 +       {0x7a,0x00,0x00},
12666 +       {0xe0,0x0f,0x00},
12667 +       {0xe3,0x14,0x00},
12668 +       {0xe5,0x48,0x00},
12669 +       {0xe7,0x58,0x00},
12670 +
12671 +       //=============== page1 ===============//
12672 +       {0xec,0x01,0x01},
12673 +       {0x10,0x05,0x01},
12674 +       {0x20,0xde,0x01},
12675 +       {0x0b,0x06,0x01},
12676 +       {0x30,0x00,0x01},
12677 +       {0x31,0x00,0x01},
12678 +       {0x32,0x00,0x01},
12679 +       {0x24,0x28,0x01},
12680 +       {0x25,0x3F,0x01},
12681 +       {0x26,0x65,0x01},
12682 +       {0x27,0xA1,0x01},
12683 +       {0x28,0xFF,0x01},
12684 +       {0x29,0x96,0x01},
12685 +       {0x2A,0x85,0x01},
12686 +       {0x2B,0xFF,0x01},
12687 +       {0x2C,0x00,0x01},
12688 +       {0x2D,0x1B,0x01},
12689 +       {0xB0,0x28,0x01},
12690 +       {0xB1,0x3F,0x01},
12691 +       {0xB2,0x65,0x01},
12692 +       {0xB3,0xA1,0x01},
12693 +       {0xB4,0xFF,0x01},
12694 +       {0xB5,0x96,0x01},
12695 +       {0xB6,0x85,0x01},
12696 +       {0xB7,0xFF,0x01},
12697 +       {0xB8,0x00,0x01},
12698 +       {0xB9,0x1B,0x01},
12699 +       {0x15,0x15,0x01},
12700 +       {0x18,0x85,0x01},
12701 +       {0x1f,0x05,0x01},
12702 +       {0x87,0x40,0x01},
12703 +       {0x37,0x60,0x01},
12704 +       {0x38,0xd5,0x01},
12705 +       {0x48,0xa0,0x01},
12706 +       {0x61,0x54,0x01},
12707 +       {0x62,0x54,0x01},
12708 +       {0x63,0x14,0x01},
12709 +       {0x64,0x14,0x01},
12710 +       {0x6d,0x12,0x01},
12711 +       {0x78,0x09,0x01},
12712 +       {0x79,0xD7,0x01},
12713 +       {0x7A,0x14,0x01},
12714 +       {0x7B,0xEE,0x01},
12715 +
12716 +       //=============== page2 ===============//
12717 +       {0xec,0x02,0x02},
12718 +       {0x2c,0x76,0x02},
12719 +       {0x25,0x25,0x02},
12720 +       {0x27,0x27,0x02},
12721 +       {0x30,0x29,0x02},
12722 +       {0x36,0x08,0x02},
12723 +       {0x38,0x04,0x02},
12724 +
12725 +       //=============== page3 ===============//
12726 +       {0xec,0x03,0x03},
12727 +       {0x08,0x00,0x03},
12728 +       {0x09,0x33,0x03},
12729 +
12730 +       //=============== page4 ===============//
12731 +       {0xec,0x04,0x04},
12732 +       {0x00,0x21,0x04},
12733 +       {0x01,0x00,0x04},
12734 +       {0x02,0x9d,0x04},
12735 +       {0x03,0x02,0x04},
12736 +       {0x04,0x04,0x04},
12737 +       {0x05,0x00,0x04},
12738 +       {0x06,0x1f,0x04},
12739 +       {0x07,0x02,0x04},
12740 +       {0x08,0x21,0x04},
12741 +       {0x09,0x00,0x04},
12742 +       {0x0a,0x9d,0x04},
12743 +       {0x0b,0x02,0x04},
12744 +       {0x0c,0x04,0x04},
12745 +       {0x0d,0x00,0x04},
12746 +       {0x0e,0x20,0x04},
12747 +       {0x0f,0x02,0x04},
12748 +       {0x1b,0x3c,0x04},
12749 +       {0x1c,0x3c,0x04},
12750 +
12751 +       //=============== page5 ===============//
12752 +       {0xec,0x05,0x05},
12753 +       {0x1f,0x00,0x05},
12754 +       {0x08,0x59,0x05},
12755 +       {0x0a,0x71,0x05},
12756 +       {0x1e,0x23,0x05},
12757 +       {0x0e,0x3c,0x05},
12758 +
12759 +       //=============== page7 ===============//
12760 +       {0xec,0x07,0x07},
12761 +       {0x11,0xfe,0x07},
12762 +
12763 +       // added by junon
12764 +       {0xec,0x01,0x07},
12765 +       {0x10,0x26,0x07},
12766 +       // 0x21-ITU-R656(CbYCrY), 0x25-ITU-R601(CbYCrY), 0x26-ITU-R601(YCrYCb)
12767 +
12768 +
12769 +};
12770 +
12771 +
12772 +#define S5X532_INIT_REGS (sizeof(s5x532_reg)/sizeof(s5x532_reg[0]))
12773 +#define S5X532_RISC_REGS 0xEB
12774 +#define S5X532_ISP_REGS 0xFB /* S5C7323X */
12775 +#define S5X532_CIS_REGS 0x2F /* S5K437LA03 */
12776 +
12777 +
12778 +#define PAGE_ADDRESS      0xEC
12779 +
12780 +//#define S5X532_REGS (S5X532_RISC_REGS+S5X532_ISP_REGS+S5X532_CIS_REGS)
12781 +#define S5X532_REGS (0x1000)
12782 +
12783 +
12784 +
12785 +#endif
12786 +
12787 +
12788 --- /dev/null
12789 +++ b/arch/arm/mach-s3c2440/camera/sensor.h
12790 @@ -0,0 +1,20 @@
12791 +/*
12792 + *
12793 + *  Copyright (C) 2004 Samsung Electronics
12794 + *            SW.LEE <hitchcar@sec.samsung.com>
12795 + *
12796 + * This program is free software; you can redistribute it and/or modify
12797 + * it under the terms of the GNU General Public License version 2 as
12798 + * published by the Free Software Foundation.
12799 + */
12800 +
12801 +#ifndef __SENSOR_CMD_H_
12802 +#define __SENSOR_CMD_H_
12803 +
12804 +#include "bits.h"
12805 +
12806 +#define SENSOR_INIT    BIT0
12807 +#define USER_ADD        BIT1
12808 +#define USER_EXIT       BIT2
12809 +
12810 +#endif
12811 --- /dev/null
12812 +++ b/arch/arm/mach-s3c2440/camera/sxga.h
12813 @@ -0,0 +1,504 @@
12814 +/*
12815 + * 2004 (C) Samsung Electronics
12816 + *  SW.LEE <hitchcar@sec.samsung.com>
12817 + * This file is subject to the terms and conditions of the GNU General Public
12818 + * License 2. See the file COPYING in the main directory of this archive
12819 + * for more details.
12820 + */
12821 +
12822 +
12823 +#ifndef _SAMSUNG_SXGA_H_
12824 +#define _SAMSUNG_SXGA_H_
12825 +
12826 +
12827 +#define CHIP_DELAY 0xFF
12828 +
12829 +typedef struct samsung_t{
12830 +       unsigned char subaddr;
12831 +       unsigned char value;
12832 +       unsigned char page;
12833 +} s5x532_t;
12834 +
12835 +s5x532_t s5x532_reg[] = {
12836 +       // page 0
12837 +       {0xec,0x00,0x0},
12838 +       {0x0c,0x38,0x0},
12839 +       {0x0d,0x24,0x0},
12840 +       {0x13,0x10,0x0},
12841 +       {0x14,0x10,0x0},
12842 +       {0x15,0x10,0x0},
12843 +       {0x16,0x10,0x0},
12844 +       {0x17,0x20,0x0},
12845 +       {0x18,0x30,0x0},
12846 +       {0x19,0x30,0x0},
12847 +       {0x1a,0x10,0x0},
12848 +       {0x1b,0x10,0x0},
12849 +
12850 +       {0x2d,0x40,0x0},
12851 +       {0x3e,0x10,0x0},
12852 +       {0x34,0x0a,0x0},
12853 +       {0x39,0x04,0x0},
12854 +       {0x3a,0x02,0x0},
12855 +       {0x31,0x05,0x0},
12856 +
12857 +       {0x40,0x1d,0x0},
12858 +       {0x41,0x50,0x0},
12859 +       {0x42,0x24,0x0},
12860 +       {0x43,0x3f,0x0},
12861 +       {0x44,0x30,0x0},
12862 +       {0x45,0x31,0x0},
12863 +
12864 +       {0x48,0xa0,0x0},
12865 +       {0x49,0xc0,0x0},
12866 +       {0x4a,0x58,0x0},
12867 +       {0x4b,0x50,0x0},
12868 +       {0x4c,0xb0,0x0},
12869 +       {0x4d,0xc0,0x0},
12870 +       {0x4e,0x30,0x0},
12871 +       {0x4f,0x20,0x0},
12872 +
12873 +       {0x50,0xa0,0x0},
12874 +       {0x51,0xc0,0x0},
12875 +       {0x52,0x50,0x0},
12876 +       {0x53,0x60,0x0},
12877 +       {0x54,0xb0,0x0},
12878 +       {0x55,0xc0,0x0},
12879 +       {0x56,0x20,0x0},
12880 +       {0x57,0x08,0x0},
12881 +//     {0x72,0x50,0x0}, // Clock 16
12882 +       {0x72,0x78,0x0}, // Clock 24Mhz
12883 +//     {0x72,0xf0,0x0}, // Clock 48Mhz
12884 +       // page 1
12885 +       {0xec,0x01,0x1},
12886 +       {0x10,0x17,0x1}, // ITU-R601
12887 +                        /*
12888 +                          [3:2] : out_sel
12889 +                            00 : 656
12890 +                            01 : 601
12891 +                            10 : RGB
12892 +                            11 : CIS
12893 +                          [1] : YC_SEL
12894 +                          [0] : CBCR_SEL
12895 +                        */
12896 +
12897 +       {0x0b,0x06,0x1}, // 6
12898 +       {0x20,0xa8,0x1}, //b0); // Highlight C Supp 040215
12899 +       {0x22,0x26,0x1}, //2f); 040225
12900 +
12901 +       {0x24,0x08,0x1}, //00); //1F); 040226
12902 +       {0x25,0x10,0x1}, //10); //34);
12903 +       {0x26,0x40,0x1}, //56);
12904 +       {0x27,0x80,0x1}, //8D);
12905 +       {0x28,0x2c,0x1}, //E7);
12906 +       {0x29,0xd6,0x1}, //7C);
12907 +       {0x2A,0x0c,0x1}, //70);
12908 +       {0x2B,0xFF,0x1}, //FF);
12909 +       {0x2C,0x00,0x1}, //00);
12910 +       {0x2D,0x5f,0x1}, //1B);
12911 +       //
12912 +       {0xB0,0x08,0x1}, //00); //1F); 040226
12913 +       {0xB1,0x10,0x1}, //10); //34);50
12914 +       {0xB2,0x40,0x1}, //36);
12915 +       {0xB3,0x80,0x1}, //6D);
12916 +       {0xB4,0x2c,0x1}, //b7);
12917 +       {0xB5,0xd6,0x1}, //7C);
12918 +       {0xB6,0x0c,0x1}, //70);
12919 +       {0xB7,0xFF,0x1}, //FF);
12920 +       {0xB8,0x00,0x1}, //00);
12921 +       {0xB9,0x5f,0x1}, //1B);
12922 +
12923 +
12924 +       {0xc2,0x01,0x1}, // shading On
12925 +       {0xc3,0x80,0x1},
12926 +       {0xc4,0x02,0x1},
12927 +       {0xc5,0x00,0x1},
12928 +       {0xc6,0x01,0x1},
12929 +       {0xc7,0x00,0x1},
12930 +       {0xc8,0x05,0x1},
12931 +       {0xc9,0x00,0x1},
12932 +       {0xca,0x04,0x1},
12933 +
12934 +       // shading 5
12935 +       {0xd0,0xb5,0x1},
12936 +       {0xd1,0x9c,0x1},
12937 +       {0xd2,0x8d,0x1},
12938 +       {0xd3,0x84,0x1},
12939 +       {0xd4,0x84,0x1},
12940 +       {0xd5,0x91,0x1},
12941 +       {0xd6,0xa0,0x1},
12942 +       {0xd7,0xb5,0x1},
12943 +
12944 +       {0xd8,0xc0,0x1},
12945 +       {0xd9,0xa6,0x1},
12946 +       {0xda,0x93,0x1},
12947 +       {0xdb,0x85,0x1},
12948 +       {0xdc,0x85,0x1},
12949 +       {0xdd,0x90,0x1},
12950 +       {0xde,0xa0,0x1},
12951 +       {0xdf,0xb8,0x1},
12952 +
12953 +       // Page 2
12954 +       {0xec,0x02,0x02},
12955 +
12956 +       {0x2d,0x02,0x02},
12957 +       {0x20,0x13,0x02},
12958 +       {0x21,0x13,0x2},
12959 +       {0x22,0x13,0x2},
12960 +       {0x23,0x13,0x2},
12961 +       {0x2e,0x85,0x2},
12962 +       {0x2f,0x34,0x2},
12963 +       {0x30,0x00,0x2},
12964 +       {0x28,0x94,0x2},
12965 +
12966 +
12967 +       // page 3
12968 +       {0xec,0x03,0x03},
12969 +       {0x10,0x00,0x3},
12970 +       {0x20,0x00,0x3},
12971 +       {0x21,0x20,0x3},
12972 +       {0x22,0x00,0x3},
12973 +       {0x23,0x00,0x3},
12974 +       {0x40,0x20,0x3},
12975 +       {0x41,0x20,0x3},
12976 +       {0x42,0x20,0x3},
12977 +       {0x43,0x20,0x3},
12978 +       {0x60,0x00,0x3},
12979 +       {0x61,0x00,0x3},
12980 +       {0x62,0x00,0x3},
12981 +       {0x63,0x00,0x3},
12982 +       {0x64,0x04,0x3},
12983 +       {0x65,0x1C,0x3},
12984 +       {0x66,0x05,0x3},
12985 +       {0x67,0x1C,0x3},
12986 +       {0x68,0x00,0x3},
12987 +       {0x69,0x2D,0x3},
12988 +       {0x6a,0x00,0x3},
12989 +       {0x6b,0x72,0x3},
12990 +       {0x6c,0x00,0x3},
12991 +       {0x6d,0x00,0x3},
12992 +       {0x6e,0x16,0x3}, // 2.38
12993 +       {0x6f,0x16,0x3}, // 2.38
12994 +       {0x70,0x00,0x3},
12995 +       {0x71,0x00,0x3},
12996 +       {0x72,0x45,0x3},
12997 +       {0x73,0x00,0x3},
12998 +       {0x74,0x1C,0x3},
12999 +       {0x75,0x05,0x3},
13000 +
13001 +       {0x80,0x00,0x3},  //for 0.02 _ 44
13002 +       {0x81,0x00,0x3},
13003 +       {0x82,0x00,0x3},
13004 +       {0x83,0x00,0x3},
13005 +       {0x84,0x04,0x3},
13006 +       {0x85,0x1c,0x3},
13007 +       {0x86,0x05,0x3},
13008 +       {0x87,0x1c,0x3},
13009 +       {0x88,0x00,0x3},
13010 +       {0x89,0x2d,0x3},
13011 +       {0x8a,0x00,0x3},
13012 +       {0x8b,0xcc,0x3},
13013 +       {0x8c,0x00,0x3},
13014 +       {0x8d,0x00,0x3},
13015 +       {0x8e,0x08,0x3},
13016 +       {0x8f,0x08,0x3},
13017 +       {0x90,0x01,0x3},
13018 +       {0x91,0x00,0x3},
13019 +       {0x92,0x91,0x3},
13020 +       {0x93,0x00,0x3},
13021 +       {0x94,0x88,0x3},
13022 +       {0x95,0x02,0x3},
13023 +
13024 +
13025 +
13026 +       // page 4
13027 +       {0xec,0x04,0x04},
13028 +       {0x3f,0x09,0x04}, // VGA : old board :0x08 , new board ; 0X09
13029 +       {0x18,0x00,0x04},  // sxga
13030 +       {0x1c,0x41,0x04},
13031 +       {0x20,0x41,0x04}, // vga center 040215
13032 +       {0x22,0xc1,0x04},// a1);
13033 +       {0x23,0x02,0x04},
13034 +       {0x28,0x41,0x04},
13035 +       {0x2a,0xc1,0x04},// a1);
13036 +       {0x2b,0x02,0x04},
13037 +
13038 +       {0x3c,0x0b,0x04}, //f);  // vga
13039 +       {0x58,0x11,0x04},
13040 +       {0x5c,0x14,0x04},
13041 +       {0x60,0x21,0x04},
13042 +       {0x61,0x00,0x04},
13043 +       {0x62,0xB1,0x04},
13044 +       {0x63,0x02,0x04},
13045 +       {0x64,0x01,0x04},
13046 +       {0x65,0x00,0x04},
13047 +       {0x66,0x01,0x04},
13048 +       {0x67,0x02,0x04},
13049 +       {0x68,0x21,0x04},
13050 +       {0x69,0x00,0x04},
13051 +       {0x6a,0xB1,0x04},
13052 +       {0x6b,0x02,0x04},
13053 +       {0x6c,0x01,0x04},
13054 +       {0x6d,0x00,0x04},
13055 +       {0x6e,0x01,0x04},
13056 +       {0x6f,0x02,0x04},
13057 +       {0x70,0x2D,0x04},
13058 +       {0x71,0x00,0x04},
13059 +       {0x72,0xd3,0x04}, // 14
13060 +       {0x73,0x05,0x04}, // 15
13061 +       {0x74,0x1C,0x04},
13062 +       {0x75,0x05,0x04},
13063 +       {0x76,0x1b,0x04}, // HendL
13064 +       {0x77,0x0b,0x04}, // HendH
13065 +       {0x78,0x01,0x04}, // 5.00
13066 +       {0x79,0x80,0x04}, // 5.2a
13067 +       {0x7a,0x33,0x04},
13068 +       {0x7b,0x00,0x04},
13069 +       {0x7c,0x38,0x04}, // 5.0e
13070 +       {0x7d,0x03,0x04},
13071 +       {0x7e,0x00,0x04},
13072 +       {0x7f,0x0A,0x04},
13073 +
13074 +       {0x80,0x2e,0x04},
13075 +       {0x81,0x00,0x04},
13076 +       {0x82,0xae,0x04},
13077 +       {0x83,0x02,0x04},
13078 +       {0x84,0x00,0x04},
13079 +       {0x85,0x00,0x04},
13080 +       {0x86,0x01,0x04},
13081 +       {0x87,0x02,0x04},
13082 +       {0x88,0x2e,0x04},
13083 +       {0x89,0x00,0x04},
13084 +       {0x8a,0xae,0x04},
13085 +       {0x8b,0x02,0x04},
13086 +       {0x8c,0x1c,0x04},
13087 +       {0x8d,0x00,0x04},
13088 +       {0x8e,0x04,0x04},
13089 +       {0x8f,0x02,0x04},
13090 +       {0x90,0x2d,0x04},
13091 +       {0x91,0x00,0x04},
13092 +       {0x92,0xa5,0x04},
13093 +       {0x93,0x00,0x04},
13094 +       {0x94,0x88,0x04},
13095 +       {0x95,0x02,0x04},
13096 +       {0x96,0xb3,0x04},
13097 +       {0x97,0x06,0x04},
13098 +       {0x98,0x01,0x04},
13099 +       {0x99,0x00,0x04},
13100 +       {0x9a,0x33,0x04},
13101 +       {0x9b,0x30,0x04},
13102 +       {0x9c,0x50,0x04},
13103 +       {0x9d,0x30,0x04},
13104 +       {0x9e,0x01,0x04},
13105 +       {0x9f,0x08,0x04},
13106 +
13107 +       // page 5
13108 +       {0xec,0x05,0x05},
13109 +       {0x5a,0x22,0x05},
13110 +
13111 +       // page 6
13112 +       {0xec,0x06,0x06},
13113 +       {0x14,0x1e,0x06},
13114 +       {0x15,0xb4,0x04},
13115 +       {0x16,0x25,0x04},
13116 +       {0x17,0x74,0x04},
13117 +
13118 +       {0x10,0x48,0x04},
13119 +       {0x11,0xa0,0x04},
13120 +       {0x12,0x40,0x04},  // 040216  AE1 window ÁÙÀÓ
13121 +       {0x13,0x70,0x04},
13122 +
13123 +       {0x1a,0x29,0x04},  // 040217  AWB window ÁÙÀÓ
13124 +       {0x30,0x40,0x04},
13125 +       {0x31,0xa2,0x04},
13126 +       {0x32,0x50,0x04},
13127 +       {0x33,0xbc,0x04},
13128 +       {0x34,0x10,0x04},
13129 +       {0x35,0xd2,0x04},
13130 +       {0x36,0x18,0x04},
13131 +       {0x37,0xf5,0x04},
13132 +       {0x38,0x10,0x04},
13133 +       {0x39,0xd3,0x04},
13134 +       {0x3a,0x1a,0x04},
13135 +       {0x3b,0xf0,0x04},
13136 +
13137 +       // page 7
13138 +       {0xec,0x07,0x07},
13139 +       {0x08,0xff,0x7},
13140 +       {0x38,0x01,0x7}, //07); 040315
13141 +       {0x39,0x01,0x7}, //02); //4);  040223   040315
13142 +       {0x11,0xfe,0x7},  //fe);   // green -2  040303
13143 +       {0x2a,0x20,0x7},
13144 +       {0x2b,0x20,0x7},
13145 +       {0x2c,0x10,0x7},
13146 +       {0x2d,0x00,0x7},
13147 +       {0x2e,0xf0,0x7},
13148 +       {0x2f,0xd0,0x7},
13149 +       {0x3a,0xf0,0x7},
13150 +       {0x23,0x07,0x7},  //  for ESD
13151 +
13152 +       // page 0
13153 +       {0xec,0x00,0x00},
13154 +       {0x8a,0x04,0x00},
13155 +
13156 +       // page 1
13157 +       {0xec,0x01,0x01},
13158 +       {0xe5,0xb0,0x01},
13159 +       {0xe5,0xb0,0x01},
13160 +       {0xc2,0x01,0x01},
13161 +
13162 +       {0x61,0x7b,0x01},
13163 +       {0x62,0x7b,0x01},
13164 +       {0x63,0x1b,0x01},
13165 +       {0x64,0x1b,0x01},
13166 +
13167 +       // page 0
13168 +       {0xec,0x00,0x00},
13169 +       {0x7e,0x04,0x00},
13170 +
13171 +       // page 4
13172 +       {0xec,0x04,0x04},
13173 +       {0x04,0x02,0x04},
13174 +       {0x06,0x02,0x04},
13175 +
13176 +       // page 1
13177 +       {0xec,0x01,0x01},
13178 +       {0x10,0x05,0x01},
13179 +       {0x54,0x02,0x01},
13180 +       {0x56,0x02,0x01},
13181 +
13182 +       // page 3
13183 +       {0xec,0x03,0x03},
13184 +       {0x0e,0x08,0x03},
13185 +       {0x0f,0x08,0x03},
13186 +
13187 +       // page 4
13188 +       {0xec,0x04,0x04},
13189 +       {0x00,0x30,0x04},
13190 +       {0x0a,0x30,0x04},
13191 +
13192 +       // page 5
13193 +       {0xec,0x05,0x05},
13194 +       {0x08,0x33,0x05},
13195 +
13196 +       // page 0
13197 +       {0xec,0x00,0x00},
13198 +       {0x02,0x00,0x00},
13199 +
13200 +       // page 4
13201 +//scale out
13202 +       {0xec,0x04,0x04},
13203 +       {0x02,0x20,0x04},
13204 +       {0x1c,0x4f,0x04},
13205 +
13206 +       // page 1
13207 +       {0xec,0x01,0x01},
13208 +       {0x52,0x20,0x01},
13209 +
13210 +       // page 5
13211 +       {0xec,0x05,0x05},
13212 +       {0x0e,0x4f,0x05},
13213 +
13214 +//ae speed
13215 +       // page 0
13216 +       {0xec,0x00,0x00},
13217 +       {0x92,0x80,0x00},
13218 +       {0x93,0x02,0x00},
13219 +       {0x94,0x04,0x00},
13220 +       {0x95,0x04,0x00},
13221 +       {0x96,0x04,0x00},
13222 +       {0x97,0x04,0x00},
13223 +       {0x9b,0x47,0x00},
13224 +
13225 +       {0xec,0x00,0x00},
13226 +       {0x40,0x17,0x00},
13227 +       {0x41,0x4c,0x00},
13228 +       {0x42,0x1d,0x00},
13229 +       {0x43,0x3e,0x00},
13230 +       {0x44,0x2a,0x00},
13231 +       {0x45,0x2d,0x00},
13232 +
13233 +       {0xec,0x01,0x01},
13234 +       {0x20,0xd0,0x01},   //high light color reference
13235 +
13236 +       {0xec,0x00,0x00},
13237 +       {0x7e,0x00,0x00},
13238 +       {0x73,0x11,0x00}, // 41
13239 +       {0x78,0x78,0x00},
13240 +
13241 +       {0xec,0x07,0x07},
13242 +       {0x1b,0x3e,0x07},
13243 +
13244 +       {0xec,0x00,0x00},
13245 +       {0x48,0xA0,0x00}, //s48C0
13246 +       {0x49,0xB0,0x00}, //s49B0
13247 +       {0x4a,0x30,0x00}, //s4a20
13248 +       {0x4b,0x70,0x00}, //s4b70
13249 +       {0x4c,0xD0,0x00}, //s4cA0
13250 +       {0x4d,0xB0,0x00}, //s4dB0
13251 +       {0x4e,0x30,0x00}, //s4e30
13252 +       {0x4f,0xF0,0x00}, //s4fF0
13253 +       {0x50,0xA0,0x00}, //s50D0
13254 +       {0x51,0xB0,0x00}, //s51B0
13255 +       {0x52,0x25,0x00}, //s5210
13256 +       {0x53,0x70,0x00}, //s5370
13257 +       {0x54,0xD0,0x00}, //s5490
13258 +       {0x55,0xD0,0x00}, //s55B0
13259 +       {0x56,0x3A,0x00}, //s5640
13260 +       {0x57,0xD0,0x00}, //s57D0
13261 +       {0x58,0xA0,0x00}, //s58D0
13262 +       {0x59,0xA0,0x00}, //s59B0
13263 +       {0x5a,0x32,0x00}, //s5a0A
13264 +       {0x5b,0x7A,0x00}, //s5b7A
13265 +       {0x5c,0xB0,0x00}, //s5c90
13266 +       {0x5d,0xC0,0x00}, //s5dC0
13267 +       {0x5e,0x3E,0x00}, //s5e4A
13268 +       {0x5f,0xfa,0x00}, //s5fD0
13269 +
13270 +       // gamma
13271 +       {0xec,0x01,0x01},
13272 +       {0x24,0x31,0x01},
13273 +       {0x25,0x4C,0x01},
13274 +       {0x26,0x75,0x01},
13275 +       {0x27,0xB5,0x01},
13276 +       {0x28,0x17,0x01},
13277 +       {0x29,0xAE,0x01},
13278 +       {0x2A,0x97,0x01},
13279 +       {0x2B,0xFF,0x01},
13280 +       {0x2C,0x00,0x01},
13281 +       {0x2D,0x5B,0x01},
13282 +
13283 +       {0xB0,0x31,0x01},
13284 +       {0xB1,0x4C,0x01},
13285 +       {0xB2,0x75,0x01},
13286 +       {0xB3,0xB5,0x01},
13287 +       {0xB4,0x17,0x01},
13288 +       {0xB5,0xAE,0x01},
13289 +       {0xB6,0x97,0x01},
13290 +       {0xB7,0xFF,0x01},
13291 +       {0xB8,0x00,0x01},
13292 +       {0xB9,0x5B,0x01},
13293 +
13294 +       {0xec,0x00,0x00},
13295 +       {0x77,0xb0,0x00},
13296 +       {0x39,0x06,0x00},
13297 +       {0x3a,0x08,0x00},
13298 +
13299 +};
13300 +
13301 +
13302 +#define S5X532_INIT_REGS (sizeof(s5x532_reg)/sizeof(s5x532_reg[0]))
13303 +#define S5X532_RISC_REGS 0xEB
13304 +#define S5X532_ISP_REGS 0xFB /* S5C7323X */
13305 +#define S5X532_CIS_REGS 0x2F /* S5K437LA03 */
13306 +
13307 +
13308 +#define PAGE_ADDRESS      0xEC
13309 +
13310 +//#define S5X532_REGS (S5X532_RISC_REGS+S5X532_ISP_REGS+S5X532_CIS_REGS)
13311 +#define S5X532_REGS (0x1000)
13312 +
13313 +
13314 +
13315 +#endif
13316 +
13317 +
13318 --- /dev/null
13319 +++ b/arch/arm/mach-s3c2440/camera/userapp.h
13320 @@ -0,0 +1,44 @@
13321 +/*
13322 +    Character Driver API Interface
13323 +
13324 +    Copyright (C) 2003 Samsung Electronics (SW.LEE: hitchcar@samsung.com)
13325 +
13326 +    This program is free software; you can redistribute it and/or modify
13327 +    it under the terms of the GNU General Public License as published by
13328 +    the Free Software Foundation; either version 2 of the License, or
13329 +    (at your option) any later version.
13330 +
13331 +*/
13332 +
13333 +#ifndef __FIMC20_CAMIF_USR_APP_H_
13334 +#define __FIMC20_CAMIF_USR_APP_H_
13335 +
13336 +
13337 +/*
13338 + * IOCTL Command for Character Driver
13339 + */
13340 +
13341 +#define CMD_CAMERA_INIT   0x23
13342 +/*  Test Application Usage */
13343 +typedef struct {
13344 +        int src_x;
13345 +        int src_y;
13346 +        int dst_x;
13347 +        int dst_y;
13348 +        int bpp;
13349 +        int flip;
13350 +} camif_param_t;
13351 +
13352 +
13353 +
13354 +#endif
13355 +
13356 +
13357 +/*
13358 + * Local variables:
13359 + * tab-width: 8
13360 + *  c-indent-level: 8
13361 + *  c-basic-offset: 8
13362 + *  c-set-style: "K&R"
13363 + * End:
13364 + */
13365 --- /dev/null
13366 +++ b/arch/arm/mach-s3c2440/camera/v4l2_api.c
13367 @@ -0,0 +1,311 @@
13368 +/*
13369 + * . 2004-01-03: SW.LEE <hitchcar@sec.samsung.com>
13370 + *
13371 + * This file is subject to the terms and conditions of the GNU General Public
13372 + * License 2. See the file COPYING in the main directory of this archive
13373 + * for more details.
13374 + */
13375 +
13376 +#include <linux/config.h>
13377 +#include <linux/module.h>
13378 +#include <linux/kernel.h>
13379 +#include <linux/init.h>
13380 +#include <linux/sched.h>
13381 +#include <linux/irq.h>
13382 +#include <linux/tqueue.h>
13383 +#include <linux/locks.h>
13384 +#include <linux/completion.h>
13385 +#include <linux/delay.h>
13386 +#include <linux/slab.h>
13387 +#include <linux/vmalloc.h>
13388 +#include <linux/miscdevice.h>
13389 +#include <linux/wait.h>
13390 +
13391 +#include <asm/io.h>
13392 +#include <asm/semaphore.h>
13393 +#include <asm/hardware.h>
13394 +#include <asm/uaccess.h>
13395 +
13396 +#include <asm/arch/cpu_s3c2440.h>
13397 +#include <asm/arch/S3C2440.h>
13398 +
13399 +#include "camif.h"
13400 +#include "videodev.h"
13401 +
13402 +/*
13403 +  Codec_formats/Preview_format[0] must be same to initial value of
13404 +  preview_init_param/codec_init_param
13405 +*/
13406 +
13407 +const struct v4l2_fmtdesc codec_formats[] = {
13408 +       {
13409 +               .index     = 0,
13410 +               .type      = V4L2_BUF_TYPE_VIDEO_CAPTURE,
13411 +//             .flags     = FORMAT_FLAGS_PLANAR,
13412 +               .description = "4:2:2, planar, Y-Cb-Cr",
13413 +               .pixelformat = V4L2_PIX_FMT_YUV422P,
13414 +
13415 +       },{
13416 +               .index    = 1,
13417 +               .type     = V4L2_BUF_TYPE_VIDEO_CAPTURE,
13418 +//             .flags    = FORMAT_FLAGS_PLANAR,
13419 +               .name     = "4:2:0, planar, Y-Cb-Cr",
13420 +               .fourcc   = V4L2_PIX_FMT_YUV420,
13421 +       }
13422 +};
13423 +
13424 +
13425 +/* Todo
13426 +   FIMC V4L2_PIX_FMT_RGB565 is not same to that of V4L2spec
13427 +   and so we need image convert to FIMC V4l2_PIX_FMT_RGB565.
13428 +*/
13429 +const struct v4l2_fmtdesc preview_formats[] = {
13430 +       {
13431 +               .index    = 1,
13432 +               .type     = V4L2_BUF_TYPE_VIDEO_CAPTURE,
13433 +               .description = "16 bpp RGB, le",
13434 +               .fourcc   = V4L2_PIX_FMT_RGB565,
13435 +//             .flags    = FORMAT_FLAGS_PACKED,
13436 +       },
13437 +       {
13438 +               .index    = 0,
13439 +               .type     = V4L2_BUF_TYPE_VIDEO_CAPTURE,
13440 +//             .flags    = FORMAT_FLAGS_PACKED,
13441 +               .description = "32 bpp RGB, le",
13442 +               .fourcc   = V4L2_PIX_FMT_BGR32,
13443 +       }
13444 +}
13445 +
13446 +#define NUM_F       ARRARY_SIZE(preview_formats)
13447 +
13448 +
13449 +/*
13450 + * This function and v4l2 structure made for V4L2 API functions
13451 + *     App <--> v4l2 <--> logical param <--> hardware
13452 + */
13453 +static int camif_get_v4l2(camif_cfg_t *cfg)
13454 +{
13455 +       return 0;
13456 +}
13457 +
13458 +
13459 +/*
13460 +** Gives the depth of a video4linux2 fourcc aka pixel format in bits.
13461 +*/
13462 +static int pixfmt2depth(int pixfmt,int *fmtptr)
13463 +{
13464 +       int fmt, depth;
13465 +
13466 +       switch (pixfmt) {
13467 +       case V4L2_PIX_FMT_RGB565:
13468 +       case V4L2_PIX_FMT_RGB565X:
13469 +               fmt = CAMIF_RGB_16;
13470 +               depth = 16;
13471 +               break;
13472 +       case V4L2_PIX_FMT_BGR24: /* Not tested */
13473 +       case V4L2_PIX_FMT_RGB24:
13474 +               fmt = CAMIF_RGB_24;
13475 +               depth = 24;
13476 +               break;
13477 +       case V4L2_PIX_FMT_BGR32:
13478 +       case V4L2_PIX_FMT_RGB32:
13479 +               fmt = CAMIF_RGB_24;
13480 +               depth 32;
13481 +               break;
13482 +       case V4L2_PIX_FMT_GREY: /* Not tested  */
13483 +               fmt = CAMIF_OUT_YCBCR420;
13484 +               depth = 8;
13485 +               break;
13486 +       case V4L2_PIX_FMT_YUYV:
13487 +       case V4L2_PIX_FMT_UYVY:
13488 +       case V4L2_PIX_FMT_YUV422P:
13489 +               fmt = CAMIF_OUT_YCBCR422;
13490 +               depth = 16;
13491 +               break;
13492 +       case V4L2_PIX_FMT_YUV420:
13493 +               fmt = CAMIF_OUT_YCBCR420;
13494 +               depth = 12;
13495 +               break;
13496 +       }
13497 +       if (fmtptr) *fmtptr = fmt;
13498 +       return depth;
13499 +}
13500 +
13501 +
13502 +
13503 +static int camif_s_v4l2(camif_cfg_t *cfg)
13504 +{
13505 +       int num = cfg->v2.used_fmt;
13506 +
13507 +       if ( !(cfg->v2.status&CAMIF_V4L2_INIT)) {
13508 +               int depth;
13509 +               int fourcc = v2.fmtdesc[num].pixelformat;
13510 +
13511 +               /* To define v4l2_fmtsdesc */
13512 +               if (cfg->dma_type == CAMIF_CODEC)
13513 +                       cfg->v2->fmtdesc = codec_formats;
13514 +               else
13515 +                       cfg->v2->fmtdesc = preview_formats;
13516 +
13517 +               /* To define v4l2_format used currently */
13518 +               cfg->v2.fmt.width    = cfg->target_x;
13519 +               cfg->v2.fmt.height   = cfg->target_y;
13520 +               cfg->v2.fmt.field    = V4L2_FIELD_NONE;
13521 +               cfg->v2.fmt.pixelformat = fourcc;
13522 +               depth       = pixfmt2depth(fourcc,NULL);
13523 +               cfg->v2.fmt.bytesperline= cfg->v2.fmt.width*depth >> 3;
13524 +               cfg->v2.fmt.sizeimage =
13525 +                       cfg->v2.fmt.height * cfg->v2.fmt.bytesperline;
13526 +
13527 +               /* To define v4l2_input */
13528 +               cfg->v2.input.index  = 0;
13529 +               if (cfg->dma_type == CAMIF_CODEC)
13530 +                       snprintf(cfg->v2.input.name, 31, "CAMIF CODEC");
13531 +               else
13532 +                       snprintf(cfg->v2.input.name, 31, "CAMIF PREVIEW");
13533 +               cfg->v2.input.type = V4L2_INPUT_TYPE_CAMERA;
13534 +
13535 +               /* Write the Status of v4l2 machine */
13536 +               cfg->v2.status |= CAMIF_V4L2_INIT;
13537 +        }
13538 +       return 0;
13539 +}
13540 +
13541 +
13542 +static int camif_g_fmt(camif_cfg_t *cfg, struct v4l2_format *f)
13543 +{
13544 +       int size = sizeof(struct v4l2_pix_format);
13545 +
13546 +       switch (f->type) {
13547 +       case V4L2_BUF_TYPE_VIDEO_CAPTURE:
13548 +               memset(&f->fmt.pix,0,size);
13549 +               memcpy(&f->fmt.pix,&cfg->v2.fmt,size);
13550 +               return 0;
13551 +       default:
13552 +               return -EINVAL;
13553 +       }
13554 +}
13555 +
13556 +
13557 +/* Copy v4l2 parameter into other element of camif_cfg_t */
13558 +static int camif_s_try(camif_cfg_t *cfg, int f)
13559 +{
13560 +       int fmt;
13561 +       cfg->target_x = cfg->v2.fmt.width;
13562 +       cfg->target_y = cfg->v2.fmt.height;
13563 +       pixfmt2depth(cfg->v2.fmt.pixelformat,&fmt);
13564 +       cfg->fmt = fmt;
13565 +       camif_dynamic_conf(cfg);
13566 +}
13567 +
13568 +
13569 +static int camif_s_fmt(camif_cfg_t *cfg, struct v4l2_format *f)
13570 +{
13571 +       int retval;
13572 +
13573 +       switch (f->type) {
13574 +       case V4L2_BUF_TYPE_VIDEO_CAPTURE:
13575 +       {
13576 +               /* update our state informations */
13577 +//             down(&fh->cap.lock);
13578 +               cfg->v2.fmt          = f->pix;
13579 +               cfg->v2.status       |= CAMIF_v4L2_DIRTY;
13580 +               camif_dynamic_conf(cfg);
13581 +               cfg->v2.status      &= ~CAMIF_v4L2_DIRTY; /* dummy ? */
13582 +//             up(&fh->cap.lock);
13583 +
13584 +               return 0;
13585 +       }
13586 +       default:
13587 +               return -EINVAL;
13588 +       }
13589 +
13590 +}
13591 +
13592 +/* Refer ioctl of  videodeX.c  and bttv-driver.c */
13593 +int camif_do_ioctl
13594 +(struct inode *inode, struct file *file,unsigned int cmd, void * arg)
13595 +{
13596 +       camif_cfg_t *cfg = file->private_data;
13597 +       int ret = 0;
13598 +
13599 +       switch (cmd) {
13600 +        case VIDIOC_QUERYCAP:
13601 +               {
13602 +                       struct v4l2_capability *cap = arg;
13603 +
13604 +                       strcpy(cap->driver,"Fimc Camera");
13605 +                       strlcpy(cap->card,cfg->v->name,sizeof(cap->card));
13606 +                       sprintf(cap->bus_info,"FIMC 2.0 AHB Bus");
13607 +                       cap->version = 0;
13608 +                       cap->capabilities =
13609 +                               V4L2_CAP_VIDEO_CAPTURE |V4L2_CAP_READWRITE;
13610 +                       return 0;
13611 +               }
13612 +       case VIDIOC_G_FMT:
13613 +               {
13614 +                       struct v4l2_format *f = arg;
13615 +                       return camif_g_fmt(cfg,f);
13616 +               }
13617 +       case VIDIOC_S_FMT:
13618 +               {
13619 +                       struct v4l2_format *f = arg;
13620 +                       return camif_s_fmt(cfg,f);
13621 +               }
13622 +
13623 +       case VIDIOC_ENUM_FMT:
13624 +               {
13625 +                       struct v4l2_fmtdesc *f = arg;
13626 +                       enum v4l2_buf_type type = f->type;
13627 +                       int index = f->index;
13628 +
13629 +                       if (index >= NUM_F)
13630 +                               return -EINVAL;
13631 +                       switch (f->type) {
13632 +                       case V4L2_BUF_TYPE_VIDEO_CAPTURE:
13633 +                               break;
13634 +                       case V4L2_BUF_TYPE_VIDEO_OVERLAY:
13635 +                       case V4L2_BUF_TYPE_VBI_CAPTURE:
13636 +                                       default:
13637 +                       return -EINVAL;
13638 +                       }
13639 +                       memset(f,0,sizeof(*f));
13640 +                       memcpy(f,cfg->v2.fmtdesc+index,sizeof(*f));
13641 +                       return 0;
13642 +               }
13643 +       case VIDIOC_G_INPUT:
13644 +               {
13645 +                       u32 *i = arg;
13646 +                       *i = cfg->v2.input;
13647 +                       return 0;
13648 +               }
13649 +       case VIDIOC_S_INPUT:
13650 +               {
13651 +                       int index = *((int *)arg);
13652 +                       if (index != 0)
13653 +                               return -EINVAL;
13654 +                       cfg->v2.input.index = index;
13655 +                       return 0;
13656 +               }
13657 +
13658 +       default:
13659 +               return -ENOIOCTLCMD; /* errno.h */
13660 +       } /* End of Switch  */
13661 +
13662 +
13663 +}
13664 +
13665 +
13666 +
13667 +
13668 +
13669 +
13670 +
13671 +/*
13672 + * Local variables:
13673 + * tab-width: 8
13674 + *  c-indent-level: 8
13675 + *  c-basic-offset: 8
13676 + *  c-set-style: "K&R"
13677 + * End:
13678 + */
13679 --- /dev/null
13680 +++ b/arch/arm/mach-s3c2440/camera/videodev2.h
13681 @@ -0,0 +1,938 @@
13682 +#ifndef __LINUX_VIDEODEV2_H
13683 +#define __LINUX_VIDEODEV2_H
13684 +/*
13685 + *     Video for Linux Two
13686 + *
13687 + *     Header file for v4l or V4L2 drivers and applications, for
13688 + *     Linux kernels 2.2.x or 2.4.x.
13689 + *
13690 + *     See http://bytesex.org/v4l/ for API specs and other
13691 + *     v4l2 documentation.
13692 + *
13693 + *     Author: Bill Dirks <bdirks@pacbell.net>
13694 + *             Justin Schoeman
13695 + *             et al.
13696 + */
13697 +#ifdef __KERNEL__
13698 +#include <linux/time.h> /* need struct timeval */
13699 +#endif
13700 +
13701 +/*
13702 + *     M I S C E L L A N E O U S
13703 + */
13704 +
13705 +/*  Four-character-code (FOURCC) */
13706 +#define v4l2_fourcc(a,b,c,d)\
13707 +        (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
13708 +
13709 +/*
13710 + *     E N U M S
13711 + */
13712 +enum v4l2_field {
13713 +       V4L2_FIELD_ANY        = 0, /* driver can choose from none,
13714 +                                     top, bottom, interlaced
13715 +                                     depending on whatever it thinks
13716 +                                     is approximate ... */
13717 +       V4L2_FIELD_NONE       = 1, /* this device has no fields ... */
13718 +       V4L2_FIELD_TOP        = 2, /* top field only */
13719 +       V4L2_FIELD_BOTTOM     = 3, /* bottom field only */
13720 +       V4L2_FIELD_INTERLACED = 4, /* both fields interlaced */
13721 +       V4L2_FIELD_SEQ_TB     = 5, /* both fields sequential into one
13722 +                                     buffer, top-bottom order */
13723 +       V4L2_FIELD_SEQ_BT     = 6, /* same as above + bottom-top order */
13724 +       V4L2_FIELD_ALTERNATE  = 7, /* both fields alternating into
13725 +                                     separate buffers */
13726 +};
13727 +#define V4L2_FIELD_HAS_TOP(field)      \
13728 +       ((field) == V4L2_FIELD_TOP      ||\
13729 +        (field) == V4L2_FIELD_INTERLACED ||\
13730 +        (field) == V4L2_FIELD_SEQ_TB   ||\
13731 +        (field) == V4L2_FIELD_SEQ_BT)
13732 +#define V4L2_FIELD_HAS_BOTTOM(field)   \
13733 +       ((field) == V4L2_FIELD_BOTTOM   ||\
13734 +        (field) == V4L2_FIELD_INTERLACED ||\
13735 +        (field) == V4L2_FIELD_SEQ_TB   ||\
13736 +        (field) == V4L2_FIELD_SEQ_BT)
13737 +#define V4L2_FIELD_HAS_BOTH(field)     \
13738 +       ((field) == V4L2_FIELD_INTERLACED ||\
13739 +        (field) == V4L2_FIELD_SEQ_TB   ||\
13740 +        (field) == V4L2_FIELD_SEQ_BT)
13741 +
13742 +enum v4l2_buf_type {
13743 +       V4L2_BUF_TYPE_VIDEO_CAPTURE  = 1,
13744 +       V4L2_BUF_TYPE_VIDEO_OUTPUT   = 2,
13745 +       V4L2_BUF_TYPE_VIDEO_OVERLAY  = 3,
13746 +       V4L2_BUF_TYPE_VBI_CAPTURE    = 4,
13747 +       V4L2_BUF_TYPE_VBI_OUTPUT     = 5,
13748 +       V4L2_BUF_TYPE_PRIVATE        = 0x80,
13749 +};
13750 +
13751 +enum v4l2_ctrl_type {
13752 +       V4L2_CTRL_TYPE_INTEGER       = 1,
13753 +       V4L2_CTRL_TYPE_BOOLEAN       = 2,
13754 +       V4L2_CTRL_TYPE_MENU          = 3,
13755 +       V4L2_CTRL_TYPE_BUTTON        = 4,
13756 +};
13757 +
13758 +enum v4l2_tuner_type {
13759 +       V4L2_TUNER_RADIO             = 1,
13760 +       V4L2_TUNER_ANALOG_TV         = 2,
13761 +};
13762 +
13763 +enum v4l2_memory {
13764 +       V4L2_MEMORY_MMAP             = 1,
13765 +       V4L2_MEMORY_USERPTR          = 2,
13766 +       V4L2_MEMORY_OVERLAY          = 3,
13767 +};
13768 +
13769 +/* see also http://vektor.theorem.ca/graphics/ycbcr/ */
13770 +enum v4l2_colorspace {
13771 +       /* ITU-R 601 -- broadcast NTSC/PAL */
13772 +       V4L2_COLORSPACE_SMPTE170M     = 1,
13773 +
13774 +       /* 1125-Line (US) HDTV */
13775 +       V4L2_COLORSPACE_SMPTE240M     = 2,
13776 +
13777 +       /* HD and modern captures. */
13778 +       V4L2_COLORSPACE_REC709        = 3,
13779 +
13780 +       /* broken BT878 extents (601, luma range 16-253 instead of 16-235) */
13781 +       V4L2_COLORSPACE_BT878         = 4,
13782 +
13783 +       /* These should be useful.  Assume 601 extents. */
13784 +       V4L2_COLORSPACE_470_SYSTEM_M  = 5,
13785 +       V4L2_COLORSPACE_470_SYSTEM_BG = 6,
13786 +
13787 +       /* I know there will be cameras that send this.  So, this is
13788 +        * unspecified chromaticities and full 0-255 on each of the
13789 +        * Y'CbCr components
13790 +        */
13791 +       V4L2_COLORSPACE_JPEG          = 7,
13792 +
13793 +       /* For RGB colourspaces, this is probably a good start. */
13794 +       V4L2_COLORSPACE_SRGB          = 8,
13795 +};
13796 +
13797 +enum v4l2_priority {
13798 +       V4L2_PRIORITY_UNSET       = 0,  /* not initialized */
13799 +       V4L2_PRIORITY_BACKGROUND  = 1,
13800 +       V4L2_PRIORITY_INTERACTIVE = 2,
13801 +       V4L2_PRIORITY_RECORD      = 3,
13802 +       V4L2_PRIORITY_DEFAULT     = V4L2_PRIORITY_INTERACTIVE,
13803 +};
13804 +
13805 +struct v4l2_rect {
13806 +       __s32   left;
13807 +       __s32   top;
13808 +       __s32   width;
13809 +       __s32   height;
13810 +};
13811 +
13812 +struct v4l2_fract {
13813 +       __u32   numerator;
13814 +       __u32   denominator;
13815 +};
13816 +
13817 +/*
13818 + *     D R I V E R   C A P A B I L I T I E S
13819 + */
13820 +struct v4l2_capability
13821 +{
13822 +       __u8    driver[16];     /* i.e. "bttv" */
13823 +       __u8    card[32];       /* i.e. "Hauppauge WinTV" */
13824 +       __u8    bus_info[32];   /* "PCI:" + pci_name(pci_dev) */
13825 +       __u32   version;        /* should use KERNEL_VERSION() */
13826 +       __u32   capabilities;   /* Device capabilities */
13827 +       __u32   reserved[4];
13828 +};
13829 +
13830 +/* Values for 'capabilities' field */
13831 +#define V4L2_CAP_VIDEO_CAPTURE 0x00000001  /* Is a video capture device */
13832 +#define V4L2_CAP_VIDEO_OUTPUT  0x00000002  /* Is a video output device */
13833 +#define V4L2_CAP_VIDEO_OVERLAY 0x00000004  /* Can do video overlay */
13834 +#define V4L2_CAP_VBI_CAPTURE   0x00000010  /* Is a VBI capture device */
13835 +#define V4L2_CAP_VBI_OUTPUT    0x00000020  /* Is a VBI output device */
13836 +#define V4L2_CAP_RDS_CAPTURE   0x00000100  /* RDS data capture */
13837 +
13838 +#define V4L2_CAP_TUNER         0x00010000  /* has a tuner */
13839 +#define V4L2_CAP_AUDIO         0x00020000  /* has audio support */
13840 +#define V4L2_CAP_RADIO         0x00040000  /* is a radio device */
13841 +
13842 +#define V4L2_CAP_READWRITE      0x01000000  /* read/write systemcalls */
13843 +#define V4L2_CAP_ASYNCIO        0x02000000  /* async I/O */
13844 +#define V4L2_CAP_STREAMING      0x04000000  /* streaming I/O ioctls */
13845 +
13846 +/*
13847 + *     V I D E O   I M A G E   F O R M A T
13848 + */
13849 +
13850 +struct v4l2_pix_format
13851 +{
13852 +       __u32                   width;
13853 +       __u32                   height;
13854 +       __u32                   pixelformat;
13855 +       enum v4l2_field         field;
13856 +       __u32                   bytesperline;   /* for padding, zero if unused */
13857 +       __u32                   sizeimage;
13858 +        enum v4l2_colorspace   colorspace;
13859 +       __u32                   priv;           /* private data, depends on pixelformat */
13860 +};
13861 +
13862 +/*           Pixel format    FOURCC                  depth  Description   */
13863 +#define V4L2_PIX_FMT_RGB332  v4l2_fourcc('R','G','B','1') /*  8  RGB-3-3-2     */
13864 +#define V4L2_PIX_FMT_RGB555  v4l2_fourcc('R','G','B','O') /* 16  RGB-5-5-5     */
13865 +#define V4L2_PIX_FMT_RGB565  v4l2_fourcc('R','G','B','P') /* 16  RGB-5-6-5     */
13866 +#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R','G','B','Q') /* 16  RGB-5-5-5 BE  */
13867 +#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R','G','B','R') /* 16  RGB-5-6-5 BE  */
13868 +#define V4L2_PIX_FMT_BGR24   v4l2_fourcc('B','G','R','3') /* 24  BGR-8-8-8     */
13869 +#define V4L2_PIX_FMT_RGB24   v4l2_fourcc('R','G','B','3') /* 24  RGB-8-8-8     */
13870 +#define V4L2_PIX_FMT_BGR32   v4l2_fourcc('B','G','R','4') /* 32  BGR-8-8-8-8   */
13871 +#define V4L2_PIX_FMT_RGB32   v4l2_fourcc('R','G','B','4') /* 32  RGB-8-8-8-8   */
13872 +#define V4L2_PIX_FMT_GREY    v4l2_fourcc('G','R','E','Y') /*  8  Greyscale     */
13873 +#define V4L2_PIX_FMT_YVU410  v4l2_fourcc('Y','V','U','9') /*  9  YVU 4:1:0     */
13874 +#define V4L2_PIX_FMT_YVU420  v4l2_fourcc('Y','V','1','2') /* 12  YVU 4:2:0     */
13875 +#define V4L2_PIX_FMT_YUYV    v4l2_fourcc('Y','U','Y','V') /* 16  YUV 4:2:2     */
13876 +#define V4L2_PIX_FMT_UYVY    v4l2_fourcc('U','Y','V','Y') /* 16  YUV 4:2:2     */
13877 +#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4','2','2','P') /* 16  YVU422 planar */
13878 +#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4','1','1','P') /* 16  YVU411 planar */
13879 +#define V4L2_PIX_FMT_Y41P    v4l2_fourcc('Y','4','1','P') /* 12  YUV 4:1:1     */
13880 +
13881 +/* two planes -- one Y, one Cr + Cb interleaved  */
13882 +#define V4L2_PIX_FMT_NV12    v4l2_fourcc('N','V','1','2') /* 12  Y/CbCr 4:2:0  */
13883 +#define V4L2_PIX_FMT_NV21    v4l2_fourcc('N','V','2','1') /* 12  Y/CrCb 4:2:0  */
13884 +
13885 +/*  The following formats are not defined in the V4L2 specification */
13886 +#define V4L2_PIX_FMT_YUV410  v4l2_fourcc('Y','U','V','9') /*  9  YUV 4:1:0     */
13887 +#define V4L2_PIX_FMT_YUV420  v4l2_fourcc('Y','U','1','2') /* 12  YUV 4:2:0     */
13888 +#define V4L2_PIX_FMT_YYUV    v4l2_fourcc('Y','Y','U','V') /* 16  YUV 4:2:2     */
13889 +#define V4L2_PIX_FMT_HI240   v4l2_fourcc('H','I','2','4') /*  8  8-bit color   */
13890 +
13891 +/* compressed formats */
13892 +#define V4L2_PIX_FMT_MJPEG    v4l2_fourcc('M','J','P','G') /* Motion-JPEG   */
13893 +#define V4L2_PIX_FMT_JPEG     v4l2_fourcc('J','P','E','G') /* JFIF JPEG     */
13894 +#define V4L2_PIX_FMT_DV       v4l2_fourcc('d','v','s','d') /* 1394          */
13895 +#define V4L2_PIX_FMT_MPEG     v4l2_fourcc('M','P','E','G') /* MPEG          */
13896 +
13897 +/*  Vendor-specific formats   */
13898 +#define V4L2_PIX_FMT_WNVA     v4l2_fourcc('W','N','V','A') /* Winnov hw compress */
13899 +
13900 +/*
13901 + *     F O R M A T   E N U M E R A T I O N
13902 + */
13903 +struct v4l2_fmtdesc
13904 +{
13905 +       __u32               index;             /* Format number      */
13906 +       enum v4l2_buf_type  type;              /* buffer type        */
13907 +       __u32               flags;
13908 +       __u8                description[32];   /* Description string */
13909 +       __u32               pixelformat;       /* Format fourcc      */
13910 +       __u32               reserved[4];
13911 +};
13912 +
13913 +#define V4L2_FMT_FLAG_COMPRESSED 0x0001
13914 +
13915 +
13916 +/*
13917 + *     T I M E C O D E
13918 + */
13919 +struct v4l2_timecode
13920 +{
13921 +       __u32   type;
13922 +       __u32   flags;
13923 +       __u8    frames;
13924 +       __u8    seconds;
13925 +       __u8    minutes;
13926 +       __u8    hours;
13927 +       __u8    userbits[4];
13928 +};
13929 +
13930 +/*  Type  */
13931 +#define V4L2_TC_TYPE_24FPS             1
13932 +#define V4L2_TC_TYPE_25FPS             2
13933 +#define V4L2_TC_TYPE_30FPS             3
13934 +#define V4L2_TC_TYPE_50FPS             4
13935 +#define V4L2_TC_TYPE_60FPS             5
13936 +
13937 +/*  Flags  */
13938 +#define V4L2_TC_FLAG_DROPFRAME         0x0001 /* "drop-frame" mode */
13939 +#define V4L2_TC_FLAG_COLORFRAME                0x0002
13940 +#define V4L2_TC_USERBITS_field         0x000C
13941 +#define V4L2_TC_USERBITS_USERDEFINED   0x0000
13942 +#define V4L2_TC_USERBITS_8BITCHARS     0x0008
13943 +/* The above is based on SMPTE timecodes */
13944 +
13945 +
13946 +/*
13947 + *     C O M P R E S S I O N   P A R A M E T E R S
13948 + */
13949 +#if 0
13950 +/* ### generic compression settings don't work, there is too much
13951 + * ### codec-specific stuff.  Maybe reuse that for MPEG codec settings
13952 + * ### later ... */
13953 +struct v4l2_compression
13954 +{
13955 +       __u32   quality;
13956 +       __u32   keyframerate;
13957 +       __u32   pframerate;
13958 +       __u32   reserved[5];
13959 +
13960 +/*  what we'll need for MPEG, extracted from some postings on
13961 +    the v4l list (Gert Vervoort, PlasmaJohn).
13962 +
13963 +system stream:
13964 +  - type: elementary stream(ES), packatised elementary stream(s) (PES)
13965 +    program stream(PS), transport stream(TS)
13966 +  - system bitrate
13967 +  - PS packet size (DVD: 2048 bytes, VCD: 2324 bytes)
13968 +  - TS video PID
13969 +  - TS audio PID
13970 +  - TS PCR PID
13971 +  - TS system information tables (PAT, PMT, CAT, NIT and SIT)
13972 +  - (MPEG-1 systems stream vs. MPEG-2 program stream (TS not supported
13973 +    by MPEG-1 systems)
13974 +
13975 +audio:
13976 +  - type: MPEG (+Layer I,II,III), AC-3, LPCM
13977 +  - bitrate
13978 +  - sampling frequency (DVD: 48 Khz, VCD: 44.1 KHz, 32 kHz)
13979 +  - Trick Modes? (ff, rew)
13980 +  - Copyright
13981 +  - Inverse Telecine
13982 +
13983 +video:
13984 +  - picturesize (SIF, 1/2 D1, 2/3 D1, D1) and PAL/NTSC norm can be set
13985 +    through excisting V4L2 controls
13986 +  - noise reduction, parameters encoder specific?
13987 +  - MPEG video version: MPEG-1, MPEG-2
13988 +  - GOP (Group Of Pictures) definition:
13989 +    - N: number of frames per GOP
13990 +    - M: distance between reference (I,P) frames
13991 +    - open/closed GOP
13992 +  - quantiser matrix: inter Q matrix (64 bytes) and intra Q matrix (64 bytes)
13993 +  - quantiser scale: linear or logarithmic
13994 +  - scanning: alternate or zigzag
13995 +  - bitrate mode: CBR (constant bitrate) or VBR (variable bitrate).
13996 +  - target video bitrate for CBR
13997 +  - target video bitrate for VBR
13998 +  - maximum video bitrate for VBR - min. quantiser value for VBR
13999 +  - max. quantiser value for VBR
14000 +  - adaptive quantisation value
14001 +  - return the number of bytes per GOP or bitrate for bitrate monitoring
14002 +
14003 +*/
14004 +};
14005 +#endif
14006 +
14007 +struct v4l2_jpegcompression
14008 +{
14009 +       int quality;
14010 +
14011 +       int  APPn;              /* Number of APP segment to be written,
14012 +                                * must be 0..15 */
14013 +       int  APP_len;           /* Length of data in JPEG APPn segment */
14014 +       char APP_data[60];      /* Data in the JPEG APPn segment. */
14015 +
14016 +       int  COM_len;           /* Length of data in JPEG COM segment */
14017 +       char COM_data[60];      /* Data in JPEG COM segment */
14018 +
14019 +       __u32 jpeg_markers;     /* Which markers should go into the JPEG
14020 +                                * output. Unless you exactly know what
14021 +                                * you do, leave them untouched.
14022 +                                * Inluding less markers will make the
14023 +                                * resulting code smaller, but there will
14024 +                                * be fewer aplications which can read it.
14025 +                                * The presence of the APP and COM marker
14026 +                                * is influenced by APP_len and COM_len
14027 +                                * ONLY, not by this property! */
14028 +
14029 +#define V4L2_JPEG_MARKER_DHT (1<<3)    /* Define Huffman Tables */
14030 +#define V4L2_JPEG_MARKER_DQT (1<<4)    /* Define Quantization Tables */
14031 +#define V4L2_JPEG_MARKER_DRI (1<<5)    /* Define Restart Interval */
14032 +#define V4L2_JPEG_MARKER_COM (1<<6)    /* Comment segment */
14033 +#define V4L2_JPEG_MARKER_APP (1<<7)    /* App segment, driver will
14034 +                                        * allways use APP0 */
14035 +};
14036 +
14037 +
14038 +/*
14039 + *     M E M O R Y - M A P P I N G   B U F F E R S
14040 + */
14041 +struct v4l2_requestbuffers
14042 +{
14043 +       __u32                   count;
14044 +       enum v4l2_buf_type      type;
14045 +       enum v4l2_memory        memory;
14046 +       __u32                   reserved[2];
14047 +};
14048 +
14049 +struct v4l2_buffer
14050 +{
14051 +       __u32                   index;
14052 +       enum v4l2_buf_type      type;
14053 +       __u32                   bytesused;
14054 +       __u32                   flags;
14055 +       enum v4l2_field         field;
14056 +       struct timeval          timestamp;
14057 +       struct v4l2_timecode    timecode;
14058 +       __u32                   sequence;
14059 +
14060 +       /* memory location */
14061 +       enum v4l2_memory        memory;
14062 +       union {
14063 +               __u32           offset;
14064 +               unsigned long   userptr;
14065 +       } m;
14066 +       __u32                   length;
14067 +
14068 +       __u32                   reserved[2];
14069 +};
14070 +
14071 +/*  Flags for 'flags' field */
14072 +#define V4L2_BUF_FLAG_MAPPED   0x0001  /* Buffer is mapped (flag) */
14073 +#define V4L2_BUF_FLAG_QUEUED   0x0002  /* Buffer is queued for processing */
14074 +#define V4L2_BUF_FLAG_DONE     0x0004  /* Buffer is ready */
14075 +#define V4L2_BUF_FLAG_KEYFRAME 0x0008  /* Image is a keyframe (I-frame) */
14076 +#define V4L2_BUF_FLAG_PFRAME   0x0010  /* Image is a P-frame */
14077 +#define V4L2_BUF_FLAG_BFRAME   0x0020  /* Image is a B-frame */
14078 +#define V4L2_BUF_FLAG_TIMECODE 0x0100  /* timecode field is valid */
14079 +
14080 +/*
14081 + *     O V E R L A Y   P R E V I E W
14082 + */
14083 +struct v4l2_framebuffer
14084 +{
14085 +       __u32                   capability;
14086 +       __u32                   flags;
14087 +/* FIXME: in theory we should pass something like PCI device + memory
14088 + * region + offset instead of some physical address */
14089 +       void*                   base;
14090 +       struct v4l2_pix_format  fmt;
14091 +};
14092 +/*  Flags for the 'capability' field. Read only */
14093 +#define V4L2_FBUF_CAP_EXTERNOVERLAY    0x0001
14094 +#define V4L2_FBUF_CAP_CHROMAKEY                0x0002
14095 +#define V4L2_FBUF_CAP_LIST_CLIPPING     0x0004
14096 +#define V4L2_FBUF_CAP_BITMAP_CLIPPING  0x0008
14097 +/*  Flags for the 'flags' field. */
14098 +#define V4L2_FBUF_FLAG_PRIMARY         0x0001
14099 +#define V4L2_FBUF_FLAG_OVERLAY         0x0002
14100 +#define V4L2_FBUF_FLAG_CHROMAKEY       0x0004
14101 +
14102 +struct v4l2_clip
14103 +{
14104 +       struct v4l2_rect        c;
14105 +       struct v4l2_clip        *next;
14106 +};
14107 +
14108 +struct v4l2_window
14109 +{
14110 +       struct v4l2_rect        w;
14111 +       enum v4l2_field         field;
14112 +       __u32                   chromakey;
14113 +       struct v4l2_clip        *clips;
14114 +       __u32                   clipcount;
14115 +       void                    *bitmap;
14116 +};
14117 +
14118 +
14119 +/*
14120 + *     C A P T U R E   P A R A M E T E R S
14121 + */
14122 +struct v4l2_captureparm
14123 +{
14124 +       __u32              capability;    /*  Supported modes */
14125 +       __u32              capturemode;   /*  Current mode */
14126 +       struct v4l2_fract  timeperframe;  /*  Time per frame in .1us units */
14127 +       __u32              extendedmode;  /*  Driver-specific extensions */
14128 +       __u32              readbuffers;   /*  # of buffers for read */
14129 +       __u32              reserved[4];
14130 +};
14131 +/*  Flags for 'capability' and 'capturemode' fields */
14132 +#define V4L2_MODE_HIGHQUALITY  0x0001  /*  High quality imaging mode */
14133 +#define V4L2_CAP_TIMEPERFRAME  0x1000  /*  timeperframe field is supported */
14134 +
14135 +struct v4l2_outputparm
14136 +{
14137 +       __u32              capability;   /*  Supported modes */
14138 +       __u32              outputmode;   /*  Current mode */
14139 +       struct v4l2_fract  timeperframe; /*  Time per frame in seconds */
14140 +       __u32              extendedmode; /*  Driver-specific extensions */
14141 +       __u32              writebuffers; /*  # of buffers for write */
14142 +       __u32              reserved[4];
14143 +};
14144 +
14145 +/*
14146 + *     I N P U T   I M A G E   C R O P P I N G
14147 + */
14148 +
14149 +struct v4l2_cropcap {
14150 +       enum v4l2_buf_type      type;
14151 +        struct v4l2_rect        bounds;
14152 +        struct v4l2_rect        defrect;
14153 +        struct v4l2_fract       pixelaspect;
14154 +};
14155 +
14156 +struct v4l2_crop {
14157 +       enum v4l2_buf_type      type;
14158 +       struct v4l2_rect        c;
14159 +};
14160 +
14161 +/*
14162 + *      A N A L O G   V I D E O   S T A N D A R D
14163 + */
14164 +
14165 +typedef __u64 v4l2_std_id;
14166 +
14167 +/* one bit for each */
14168 +#define V4L2_STD_PAL_B          ((v4l2_std_id)0x00000001)
14169 +#define V4L2_STD_PAL_B1         ((v4l2_std_id)0x00000002)
14170 +#define V4L2_STD_PAL_G          ((v4l2_std_id)0x00000004)
14171 +#define V4L2_STD_PAL_H          ((v4l2_std_id)0x00000008)
14172 +#define V4L2_STD_PAL_I          ((v4l2_std_id)0x00000010)
14173 +#define V4L2_STD_PAL_D          ((v4l2_std_id)0x00000020)
14174 +#define V4L2_STD_PAL_D1         ((v4l2_std_id)0x00000040)
14175 +#define V4L2_STD_PAL_K          ((v4l2_std_id)0x00000080)
14176 +
14177 +#define V4L2_STD_PAL_M          ((v4l2_std_id)0x00000100)
14178 +#define V4L2_STD_PAL_N          ((v4l2_std_id)0x00000200)
14179 +#define V4L2_STD_PAL_Nc         ((v4l2_std_id)0x00000400)
14180 +#define V4L2_STD_PAL_60         ((v4l2_std_id)0x00000800)
14181 +
14182 +#define V4L2_STD_NTSC_M         ((v4l2_std_id)0x00001000)
14183 +#define V4L2_STD_NTSC_M_JP      ((v4l2_std_id)0x00002000)
14184 +
14185 +#define V4L2_STD_SECAM_B        ((v4l2_std_id)0x00010000)
14186 +#define V4L2_STD_SECAM_D        ((v4l2_std_id)0x00020000)
14187 +#define V4L2_STD_SECAM_G        ((v4l2_std_id)0x00040000)
14188 +#define V4L2_STD_SECAM_H        ((v4l2_std_id)0x00080000)
14189 +#define V4L2_STD_SECAM_K        ((v4l2_std_id)0x00100000)
14190 +#define V4L2_STD_SECAM_K1       ((v4l2_std_id)0x00200000)
14191 +#define V4L2_STD_SECAM_L        ((v4l2_std_id)0x00400000)
14192 +
14193 +/* ATSC/HDTV */
14194 +#define V4L2_STD_ATSC_8_VSB     ((v4l2_std_id)0x01000000)
14195 +#define V4L2_STD_ATSC_16_VSB    ((v4l2_std_id)0x02000000)
14196 +
14197 +/* some common needed stuff */
14198 +#define V4L2_STD_PAL_BG                (V4L2_STD_PAL_B         |\
14199 +                                V4L2_STD_PAL_B1        |\
14200 +                                V4L2_STD_PAL_G)
14201 +#define V4L2_STD_PAL_DK                (V4L2_STD_PAL_D         |\
14202 +                                V4L2_STD_PAL_D1        |\
14203 +                                V4L2_STD_PAL_K)
14204 +#define V4L2_STD_PAL           (V4L2_STD_PAL_BG        |\
14205 +                                V4L2_STD_PAL_DK        |\
14206 +                                V4L2_STD_PAL_H         |\
14207 +                                V4L2_STD_PAL_I)
14208 +#define V4L2_STD_NTSC           (V4L2_STD_NTSC_M       |\
14209 +                                V4L2_STD_NTSC_M_JP)
14210 +#define V4L2_STD_SECAM         (V4L2_STD_SECAM_B       |\
14211 +                                V4L2_STD_SECAM_D       |\
14212 +                                V4L2_STD_SECAM_G       |\
14213 +                                V4L2_STD_SECAM_H       |\
14214 +                                V4L2_STD_SECAM_K       |\
14215 +                                V4L2_STD_SECAM_K1      |\
14216 +                                V4L2_STD_SECAM_L)
14217 +
14218 +#define V4L2_STD_525_60                (V4L2_STD_PAL_M         |\
14219 +                                V4L2_STD_PAL_60        |\
14220 +                                V4L2_STD_NTSC)
14221 +#define V4L2_STD_625_50                (V4L2_STD_PAL           |\
14222 +                                V4L2_STD_PAL_N         |\
14223 +                                V4L2_STD_PAL_Nc        |\
14224 +                                V4L2_STD_SECAM)
14225 +
14226 +#define V4L2_STD_UNKNOWN        0
14227 +#define V4L2_STD_ALL            (V4L2_STD_525_60       |\
14228 +                                V4L2_STD_625_50)
14229 +
14230 +struct v4l2_standard
14231 +{
14232 +       __u32                index;
14233 +       v4l2_std_id          id;
14234 +       __u8                 name[24];
14235 +       struct v4l2_fract    frameperiod; /* Frames, not fields */
14236 +       __u32                framelines;
14237 +       __u32                reserved[4];
14238 +};
14239 +
14240 +
14241 +/*
14242 + *     V I D E O   I N P U T S
14243 + */
14244 +struct v4l2_input
14245 +{
14246 +       __u32        index;             /*  Which input */
14247 +       __u8         name[32];          /*  Label */
14248 +       __u32        type;              /*  Type of input */
14249 +       __u32        audioset;          /*  Associated audios (bitfield) */
14250 +       __u32        tuner;             /*  Associated tuner */
14251 +       v4l2_std_id  std;
14252 +       __u32        status;
14253 +       __u32        reserved[4];
14254 +};
14255 +/*  Values for the 'type' field */
14256 +#define V4L2_INPUT_TYPE_TUNER          1
14257 +#define V4L2_INPUT_TYPE_CAMERA         2
14258 +
14259 +/* field 'status' - general */
14260 +#define V4L2_IN_ST_NO_POWER    0x00000001  /* Attached device is off */
14261 +#define V4L2_IN_ST_NO_SIGNAL   0x00000002
14262 +#define V4L2_IN_ST_NO_COLOR    0x00000004
14263 +
14264 +/* field 'status' - analog */
14265 +#define V4L2_IN_ST_NO_H_LOCK   0x00000100  /* No horizontal sync lock */
14266 +#define V4L2_IN_ST_COLOR_KILL  0x00000200  /* Color killer is active */
14267 +
14268 +/* field 'status' - digital */
14269 +#define V4L2_IN_ST_NO_SYNC     0x00010000  /* No synchronization lock */
14270 +#define V4L2_IN_ST_NO_EQU      0x00020000  /* No equalizer lock */
14271 +#define V4L2_IN_ST_NO_CARRIER  0x00040000  /* Carrier recovery failed */
14272 +
14273 +/* field 'status' - VCR and set-top box */
14274 +#define V4L2_IN_ST_MACROVISION 0x01000000  /* Macrovision detected */
14275 +#define V4L2_IN_ST_NO_ACCESS   0x02000000  /* Conditional access denied */
14276 +#define V4L2_IN_ST_VTR         0x04000000  /* VTR time constant */
14277 +
14278 +/*
14279 + *     V I D E O   O U T P U T S
14280 + */
14281 +struct v4l2_output
14282 +{
14283 +       __u32        index;             /*  Which output */
14284 +       __u8         name[32];          /*  Label */
14285 +       __u32        type;              /*  Type of output */
14286 +       __u32        audioset;          /*  Associated audios (bitfield) */
14287 +       __u32        modulator;         /*  Associated modulator */
14288 +       v4l2_std_id  std;
14289 +       __u32        reserved[4];
14290 +};
14291 +/*  Values for the 'type' field */
14292 +#define V4L2_OUTPUT_TYPE_MODULATOR             1
14293 +#define V4L2_OUTPUT_TYPE_ANALOG                        2
14294 +#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY      3
14295 +
14296 +/*
14297 + *     C O N T R O L S
14298 + */
14299 +struct v4l2_control
14300 +{
14301 +       __u32                id;
14302 +       __s32                value;
14303 +};
14304 +
14305 +/*  Used in the VIDIOC_QUERYCTRL ioctl for querying controls */
14306 +struct v4l2_queryctrl
14307 +{
14308 +       __u32                id;
14309 +       enum v4l2_ctrl_type  type;
14310 +       __u8                 name[32];  /* Whatever */
14311 +       __s32                minimum;   /* Note signedness */
14312 +       __s32                maximum;
14313 +       __s32                step;
14314 +       __s32                default_value;
14315 +       __u32                flags;
14316 +       __u32                reserved[2];
14317 +};
14318 +
14319 +/*  Used in the VIDIOC_QUERYMENU ioctl for querying menu items */
14320 +struct v4l2_querymenu
14321 +{
14322 +       __u32           id;
14323 +       __u32           index;
14324 +       __u8            name[32];       /* Whatever */
14325 +       __u32           reserved;
14326 +};
14327 +
14328 +/*  Control flags  */
14329 +#define V4L2_CTRL_FLAG_DISABLED                0x0001
14330 +#define V4L2_CTRL_FLAG_GRABBED         0x0002
14331 +
14332 +/*  Control IDs defined by V4L2 */
14333 +#define V4L2_CID_BASE                  0x00980900
14334 +/*  IDs reserved for driver specific controls */
14335 +#define V4L2_CID_PRIVATE_BASE          0x08000000
14336 +
14337 +#define V4L2_CID_BRIGHTNESS            (V4L2_CID_BASE+0)
14338 +#define V4L2_CID_CONTRAST              (V4L2_CID_BASE+1)
14339 +#define V4L2_CID_SATURATION            (V4L2_CID_BASE+2)
14340 +#define V4L2_CID_HUE                   (V4L2_CID_BASE+3)
14341 +#define V4L2_CID_AUDIO_VOLUME          (V4L2_CID_BASE+5)
14342 +#define V4L2_CID_AUDIO_BALANCE         (V4L2_CID_BASE+6)
14343 +#define V4L2_CID_AUDIO_BASS            (V4L2_CID_BASE+7)
14344 +#define V4L2_CID_AUDIO_TREBLE          (V4L2_CID_BASE+8)
14345 +#define V4L2_CID_AUDIO_MUTE            (V4L2_CID_BASE+9)
14346 +#define V4L2_CID_AUDIO_LOUDNESS                (V4L2_CID_BASE+10)
14347 +#define V4L2_CID_BLACK_LEVEL           (V4L2_CID_BASE+11)
14348 +#define V4L2_CID_AUTO_WHITE_BALANCE    (V4L2_CID_BASE+12)
14349 +#define V4L2_CID_DO_WHITE_BALANCE      (V4L2_CID_BASE+13)
14350 +#define V4L2_CID_RED_BALANCE           (V4L2_CID_BASE+14)
14351 +#define V4L2_CID_BLUE_BALANCE          (V4L2_CID_BASE+15)
14352 +#define V4L2_CID_GAMMA                 (V4L2_CID_BASE+16)
14353 +#define V4L2_CID_WHITENESS             (V4L2_CID_GAMMA) /* ? Not sure */
14354 +#define V4L2_CID_EXPOSURE              (V4L2_CID_BASE+17)
14355 +#define V4L2_CID_AUTOGAIN              (V4L2_CID_BASE+18)
14356 +#define V4L2_CID_GAIN                  (V4L2_CID_BASE+19)
14357 +#define V4L2_CID_HFLIP                 (V4L2_CID_BASE+20)
14358 +#define V4L2_CID_VFLIP                 (V4L2_CID_BASE+21)
14359 +#define V4L2_CID_HCENTER               (V4L2_CID_BASE+22)
14360 +#define V4L2_CID_VCENTER               (V4L2_CID_BASE+23)
14361 +#define V4L2_CID_LASTP1                        (V4L2_CID_BASE+24) /* last CID + 1 */
14362 +
14363 +/*
14364 + *     T U N I N G
14365 + */
14366 +struct v4l2_tuner
14367 +{
14368 +       __u32                   index;
14369 +       __u8                    name[32];
14370 +       enum v4l2_tuner_type    type;
14371 +       __u32                   capability;
14372 +       __u32                   rangelow;
14373 +       __u32                   rangehigh;
14374 +       __u32                   rxsubchans;
14375 +       __u32                   audmode;
14376 +       __s32                   signal;
14377 +       __s32                   afc;
14378 +       __u32                   reserved[4];
14379 +};
14380 +
14381 +struct v4l2_modulator
14382 +{
14383 +       __u32                   index;
14384 +       __u8                    name[32];
14385 +       __u32                   capability;
14386 +       __u32                   rangelow;
14387 +       __u32                   rangehigh;
14388 +       __u32                   txsubchans;
14389 +       __u32                   reserved[4];
14390 +};
14391 +
14392 +/*  Flags for the 'capability' field */
14393 +#define V4L2_TUNER_CAP_LOW             0x0001
14394 +#define V4L2_TUNER_CAP_NORM            0x0002
14395 +#define V4L2_TUNER_CAP_STEREO          0x0010
14396 +#define V4L2_TUNER_CAP_LANG2           0x0020
14397 +#define V4L2_TUNER_CAP_SAP             0x0020
14398 +#define V4L2_TUNER_CAP_LANG1           0x0040
14399 +
14400 +/*  Flags for the 'rxsubchans' field */
14401 +#define V4L2_TUNER_SUB_MONO            0x0001
14402 +#define V4L2_TUNER_SUB_STEREO          0x0002
14403 +#define V4L2_TUNER_SUB_LANG2           0x0004
14404 +#define V4L2_TUNER_SUB_SAP             0x0004
14405 +#define V4L2_TUNER_SUB_LANG1           0x0008
14406 +
14407 +/*  Values for the 'audmode' field */
14408 +#define V4L2_TUNER_MODE_MONO           0x0000
14409 +#define V4L2_TUNER_MODE_STEREO         0x0001
14410 +#define V4L2_TUNER_MODE_LANG2          0x0002
14411 +#define V4L2_TUNER_MODE_SAP            0x0002
14412 +#define V4L2_TUNER_MODE_LANG1          0x0003
14413 +
14414 +struct v4l2_frequency
14415 +{
14416 +       __u32                 tuner;
14417 +       enum v4l2_tuner_type  type;
14418 +        __u32                frequency;
14419 +       __u32                 reserved[8];
14420 +};
14421 +
14422 +/*
14423 + *     A U D I O
14424 + */
14425 +struct v4l2_audio
14426 +{
14427 +       __u32   index;
14428 +       __u8    name[32];
14429 +       __u32   capability;
14430 +       __u32   mode;
14431 +       __u32   reserved[2];
14432 +};
14433 +/*  Flags for the 'capability' field */
14434 +#define V4L2_AUDCAP_STEREO             0x00001
14435 +#define V4L2_AUDCAP_AVL                        0x00002
14436 +
14437 +/*  Flags for the 'mode' field */
14438 +#define V4L2_AUDMODE_AVL               0x00001
14439 +
14440 +struct v4l2_audioout
14441 +{
14442 +       __u32   index;
14443 +       __u8    name[32];
14444 +       __u32   capability;
14445 +       __u32   mode;
14446 +       __u32   reserved[2];
14447 +};
14448 +
14449 +/*
14450 + *     D A T A   S E R V I C E S   ( V B I )
14451 + *
14452 + *     Data services API by Michael Schimek
14453 + */
14454 +
14455 +struct v4l2_vbi_format
14456 +{
14457 +       __u32   sampling_rate;          /* in 1 Hz */
14458 +       __u32   offset;
14459 +       __u32   samples_per_line;
14460 +       __u32   sample_format;          /* V4L2_PIX_FMT_* */
14461 +       __s32   start[2];
14462 +       __u32   count[2];
14463 +       __u32   flags;                  /* V4L2_VBI_* */
14464 +       __u32   reserved[2];            /* must be zero */
14465 +};
14466 +
14467 +/*  VBI flags  */
14468 +#define V4L2_VBI_UNSYNC                (1<< 0)
14469 +#define V4L2_VBI_INTERLACED    (1<< 1)
14470 +
14471 +
14472 +/*
14473 + *     A G G R E G A T E   S T R U C T U R E S
14474 + */
14475 +
14476 +/*     Stream data format
14477 + */
14478 +struct v4l2_format
14479 +{
14480 +       enum v4l2_buf_type type;
14481 +       union
14482 +       {
14483 +               struct v4l2_pix_format  pix;  // V4L2_BUF_TYPE_VIDEO_CAPTURE
14484 +               struct v4l2_window      win;  // V4L2_BUF_TYPE_VIDEO_OVERLAY
14485 +               struct v4l2_vbi_format  vbi;  // V4L2_BUF_TYPE_VBI_CAPTURE
14486 +               __u8    raw_data[200];        // user-defined
14487 +       } fmt;
14488 +};
14489 +
14490 +
14491 +/*     Stream type-dependent parameters
14492 + */
14493 +struct v4l2_streamparm
14494 +{
14495 +       enum v4l2_buf_type type;
14496 +       union
14497 +       {
14498 +               struct v4l2_captureparm capture;
14499 +               struct v4l2_outputparm  output;
14500 +               __u8    raw_data[200];  /* user-defined */
14501 +       } parm;
14502 +};
14503 +
14504 +
14505 +
14506 +/*
14507 + *     I O C T L   C O D E S   F O R   V I D E O   D E V I C E S
14508 + *
14509 + */
14510 +#define VIDIOC_QUERYCAP                _IOR  ('V',  0, struct v4l2_capability)
14511 +#define VIDIOC_RESERVED                _IO   ('V',  1)
14512 +#define VIDIOC_ENUM_FMT         _IOWR ('V',  2, struct v4l2_fmtdesc)
14513 +#define VIDIOC_G_FMT           _IOWR ('V',  4, struct v4l2_format)
14514 +#define VIDIOC_S_FMT           _IOWR ('V',  5, struct v4l2_format)
14515 +#if 0
14516 +#define VIDIOC_G_COMP          _IOR  ('V',  6, struct v4l2_compression)
14517 +#define VIDIOC_S_COMP          _IOW  ('V',  7, struct v4l2_compression)
14518 +#endif
14519 +#define VIDIOC_REQBUFS         _IOWR ('V',  8, struct v4l2_requestbuffers)
14520 +#define VIDIOC_QUERYBUF                _IOWR ('V',  9, struct v4l2_buffer)
14521 +#define VIDIOC_G_FBUF          _IOR  ('V', 10, struct v4l2_framebuffer)
14522 +#define VIDIOC_S_FBUF          _IOW  ('V', 11, struct v4l2_framebuffer)
14523 +#define VIDIOC_OVERLAY         _IOW  ('V', 14, int)
14524 +#define VIDIOC_QBUF            _IOWR ('V', 15, struct v4l2_buffer)
14525 +#define VIDIOC_DQBUF           _IOWR ('V', 17, struct v4l2_buffer)
14526 +#define VIDIOC_STREAMON                _IOW  ('V', 18, int)
14527 +#define VIDIOC_STREAMOFF       _IOW  ('V', 19, int)
14528 +#define VIDIOC_G_PARM          _IOWR ('V', 21, struct v4l2_streamparm)
14529 +#define VIDIOC_S_PARM          _IOWR ('V', 22, struct v4l2_streamparm)
14530 +#define VIDIOC_G_STD           _IOR  ('V', 23, v4l2_std_id)
14531 +#define VIDIOC_S_STD           _IOW  ('V', 24, v4l2_std_id)
14532 +#define VIDIOC_ENUMSTD         _IOWR ('V', 25, struct v4l2_standard)
14533 +#define VIDIOC_ENUMINPUT       _IOWR ('V', 26, struct v4l2_input)
14534 +#define VIDIOC_G_CTRL          _IOWR ('V', 27, struct v4l2_control)
14535 +#define VIDIOC_S_CTRL          _IOWR ('V', 28, struct v4l2_control)
14536 +#define VIDIOC_G_TUNER         _IOWR ('V', 29, struct v4l2_tuner)
14537 +#define VIDIOC_S_TUNER         _IOW  ('V', 30, struct v4l2_tuner)
14538 +#define VIDIOC_G_AUDIO         _IOR  ('V', 33, struct v4l2_audio)
14539 +#define VIDIOC_S_AUDIO         _IOW  ('V', 34, struct v4l2_audio)
14540 +#define VIDIOC_QUERYCTRL       _IOWR ('V', 36, struct v4l2_queryctrl)
14541 +#define VIDIOC_QUERYMENU       _IOWR ('V', 37, struct v4l2_querymenu)
14542 +#define VIDIOC_G_INPUT         _IOR  ('V', 38, int)
14543 +#define VIDIOC_S_INPUT         _IOWR ('V', 39, int)
14544 +#define VIDIOC_G_OUTPUT                _IOR  ('V', 46, int)
14545 +#define VIDIOC_S_OUTPUT                _IOWR ('V', 47, int)
14546 +#define VIDIOC_ENUMOUTPUT      _IOWR ('V', 48, struct v4l2_output)
14547 +#define VIDIOC_G_AUDOUT                _IOR  ('V', 49, struct v4l2_audioout)
14548 +#define VIDIOC_S_AUDOUT                _IOW  ('V', 50, struct v4l2_audioout)
14549 +#define VIDIOC_G_MODULATOR     _IOWR ('V', 54, struct v4l2_modulator)
14550 +#define VIDIOC_S_MODULATOR     _IOW  ('V', 55, struct v4l2_modulator)
14551 +#define VIDIOC_G_FREQUENCY     _IOWR ('V', 56, struct v4l2_frequency)
14552 +#define VIDIOC_S_FREQUENCY     _IOW  ('V', 57, struct v4l2_frequency)
14553 +#define VIDIOC_CROPCAP         _IOR  ('V', 58, struct v4l2_cropcap)
14554 +#define VIDIOC_G_CROP          _IOWR ('V', 59, struct v4l2_crop)
14555 +#define VIDIOC_S_CROP          _IOW  ('V', 60, struct v4l2_crop)
14556 +#define VIDIOC_G_JPEGCOMP      _IOR  ('V', 61, struct v4l2_jpegcompression)
14557 +#define VIDIOC_S_JPEGCOMP      _IOW  ('V', 62, struct v4l2_jpegcompression)
14558 +#define VIDIOC_QUERYSTD        _IOR  ('V', 63, v4l2_std_id)
14559 +#define VIDIOC_TRY_FMT         _IOWR ('V', 64, struct v4l2_format)
14560 +#define VIDIOC_ENUMAUDIO       _IOWR ('V', 65, struct v4l2_audio)
14561 +#define VIDIOC_ENUMAUDOUT      _IOWR ('V', 66, struct v4l2_audioout)
14562 +#define VIDIOC_G_PRIORITY       _IOR  ('V', 67, enum v4l2_priority)
14563 +#define VIDIOC_S_PRIORITY       _IOW  ('V', 68, enum v4l2_priority)
14564 +
14565 +/* for compatibility, will go away some day */
14566 +#define VIDIOC_OVERLAY_OLD             _IOWR ('V', 14, int)
14567 +#define VIDIOC_S_PARM_OLD              _IOW  ('V', 22, struct v4l2_streamparm)
14568 +#define VIDIOC_S_CTRL_OLD              _IOW  ('V', 28, struct v4l2_control)
14569 +#define VIDIOC_G_AUDIO_OLD             _IOWR ('V', 33, struct v4l2_audio)
14570 +#define VIDIOC_G_AUDOUT_OLD            _IOWR ('V', 49, struct v4l2_audioout)
14571 +
14572 +#define BASE_VIDIOC_PRIVATE    192             /* 192-255 are private */
14573 +
14574 +
14575 +#ifdef __KERNEL__
14576 +/*
14577 + *
14578 + *     V 4 L 2   D R I V E R   H E L P E R   A P I
14579 + *
14580 + *     Some commonly needed functions for drivers (v4l2-common.o module)
14581 + */
14582 +#include <linux/fs.h>
14583 +
14584 +/*  Video standard functions  */
14585 +extern unsigned int v4l2_video_std_fps(struct v4l2_standard *vs);
14586 +extern int v4l2_video_std_construct(struct v4l2_standard *vs,
14587 +                                   int id, char *name);
14588 +
14589 +/* prority handling */
14590 +struct v4l2_prio_state {
14591 +       atomic_t prios[4];
14592 +};
14593 +int v4l2_prio_init(struct v4l2_prio_state *global);
14594 +int v4l2_prio_change(struct v4l2_prio_state *global, enum v4l2_priority *local,
14595 +                    enum v4l2_priority new);
14596 +int v4l2_prio_open(struct v4l2_prio_state *global, enum v4l2_priority *local);
14597 +int v4l2_prio_close(struct v4l2_prio_state *global, enum v4l2_priority *local);
14598 +enum v4l2_priority v4l2_prio_max(struct v4l2_prio_state *global);
14599 +int v4l2_prio_check(struct v4l2_prio_state *global, enum v4l2_priority *local);
14600 +
14601 +/* names for fancy debug output */
14602 +extern char *v4l2_field_names[];
14603 +extern char *v4l2_type_names[];
14604 +extern char *v4l2_ioctl_names[];
14605 +
14606 +/*  Compatibility layer interface  --  v4l1-compat module */
14607 +typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file,
14608 +                          unsigned int cmd, void *arg);
14609 +int v4l_compat_translate_ioctl(struct inode *inode, struct file *file,
14610 +                              int cmd, void *arg, v4l2_kioctl driver_ioctl);
14611 +
14612 +#endif /* __KERNEL__ */
14613 +#endif /* __LINUX_VIDEODEV2_H */
14614 +
14615 +/*
14616 + * Local variables:
14617 + * c-basic-offset: 8
14618 + * End:
14619 + */
14620 --- /dev/null
14621 +++ b/arch/arm/mach-s3c2440/camera/videodev.c
14622 @@ -0,0 +1,332 @@
14623 +/*
14624 + * Video capture interface for Linux Character Device Driver.
14625 + *              based on
14626 + *              Alan Cox, <alan@redhat.com> video4linux
14627 + *
14628 + * Author:      SW.LEE <hitchcar@samsung.com>
14629 + *              2004 (C) Samsung Electronics
14630 + *              Modified for S3C2440/S3C24A0 Interface
14631 + *
14632 + * This file is released under the GPLv2
14633 + */
14634 +
14635 +
14636 +#include <linux/module.h>
14637 +#include <linux/types.h>
14638 +#include <linux/kernel.h>
14639 +#include <linux/sched.h>
14640 +#include <linux/smp_lock.h>
14641 +#include <linux/mm.h>
14642 +#include <linux/string.h>
14643 +#include <linux/errno.h>
14644 +#include <linux/init.h>
14645 +#include <linux/kmod.h>
14646 +#include <linux/slab.h>
14647 +/* #include <linux/devfs_fs_kernel.h> */
14648 +#include <linux/miscdevice.h>
14649 +#include <asm/uaccess.h>
14650 +#include <asm/system.h>
14651 +#include <asm/semaphore.h>
14652 +
14653 +
14654 +
14655 +#define CONFIG_VIDEO_V4L1_COMPAT
14656 +#include <linux/videodev.h>
14657 +#include "camif.h"
14658 +#include "miscdevice.h"
14659 +
14660 +
14661 +static DECLARE_MUTEX(videodev_lock);
14662 +
14663 +const char *fimc_version = "$Id: videodev.c,v 1.1.1.1 2004/04/27 03:52:50 swlee Exp $";
14664 +
14665 +#define VIDEO_NAME              "video4linux"
14666 +
14667 +
14668 +#define VIDEO_NUM_DEVICES      2
14669 +static struct video_device *video_device[VIDEO_NUM_DEVICES];
14670 +
14671 +static inline struct video_device * get_vd(int nr)
14672 +{
14673 +       if ( nr == CODEC_MINOR)
14674 +               return video_device[0];
14675 +       else {
14676 +               assert ( nr & PREVIEW_MINOR);
14677 +               return video_device[1];
14678 +       }
14679 +}
14680 +
14681 +static inline void set_vd ( struct video_device * vd, int nr)
14682 +{
14683 +       if ( nr == CODEC_MINOR)
14684 +               video_device[0] = vd;
14685 +       else {
14686 +               assert ( nr & PREVIEW_MINOR);
14687 +               video_device[1] = vd;
14688 +       }
14689 +}
14690 +
14691 +static inline int video_release(struct inode *inode, struct file *f)
14692 +{
14693 +       int minor = MINOR(inode->i_rdev);
14694 +       struct video_device *vfd;
14695 +
14696 +       vfd = get_vd(minor);
14697 +#if 1 /* needed until all drivers are fixed */
14698 +       if (!vfd->release)
14699 +               return 0;
14700 +#endif
14701 +       vfd->release(vfd);
14702 +       return 0;
14703 +}
14704 +
14705 +struct video_device* video_devdata(struct file *file)
14706 +{
14707 +       return video_device[iminor(file->f_dentry->d_inode)];
14708 +}
14709 +
14710 +
14711 +/*
14712 + *     Open a video device.
14713 + */
14714 +static int video_open(struct inode *inode, struct file *file)
14715 +{
14716 +       int minor = MINOR(inode->i_rdev);
14717 +       int err = 0;
14718 +       struct video_device *vfl;
14719 +       struct file_operations const *old_fops;
14720 +
14721 +       down(&videodev_lock);
14722 +
14723 +       vfl = get_vd(minor);
14724 +
14725 +       old_fops = file->f_op;
14726 +       file->f_op = fops_get(vfl->fops);
14727 +       if(file->f_op->open)
14728 +               err = file->f_op->open(inode,file);
14729 +       if (err) {
14730 +               fops_put(file->f_op);
14731 +               file->f_op = fops_get(old_fops);
14732 +       }
14733 +       fops_put(old_fops);
14734 +       up(&videodev_lock);
14735 +       return err;
14736 +}
14737 +
14738 +/*
14739 + * open/release helper functions -- handle exclusive opens
14740 + */
14741 +extern int video_exclusive_open(struct inode *inode, struct file *file)
14742 +{
14743 +       struct  video_device *vfl = get_vd(MINOR(inode->i_rdev));
14744 +       int retval = 0;
14745 +
14746 +       mutex_lock(&vfl->lock);
14747 +       if (vfl->users) {
14748 +               retval = -EBUSY;
14749 +       } else {
14750 +               vfl->users++;
14751 +       }
14752 +       mutex_unlock(&vfl->lock);
14753 +       return retval;
14754 +}
14755 +
14756 +extern int video_exclusive_release(struct inode *inode, struct file *file)
14757 +{
14758 +       struct  video_device *vfl = get_vd(MINOR(inode->i_rdev));
14759 +       vfl->users--;
14760 +       return 0;
14761 +}
14762 +
14763 +int
14764 +video_usercopy(struct inode *inode, struct file *file,
14765 +              unsigned int cmd, unsigned long arg,
14766 +              int (*func)(struct inode *inode, struct file *file,
14767 +                          unsigned int cmd, void *arg))
14768 +{
14769 +       char    sbuf[128];
14770 +       void    *mbuf = NULL;
14771 +       void    *parg = NULL;
14772 +       int     err  = -EINVAL;
14773 +
14774 +       //      cmd = video_fix_command(cmd);
14775 +
14776 +       /*  Copy arguments into temp kernel buffer  */
14777 +       switch (_IOC_DIR(cmd)) {
14778 +       case _IOC_NONE:
14779 +               parg = (void *)arg;
14780 +               break;
14781 +       case _IOC_READ:
14782 +       case _IOC_WRITE:
14783 +       case (_IOC_WRITE | _IOC_READ):
14784 +               if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
14785 +                       parg = sbuf;
14786 +               } else {
14787 +                       /* too big to allocate from stack */
14788 +                       mbuf = kmalloc(_IOC_SIZE(cmd),GFP_KERNEL);
14789 +                       if (NULL == mbuf)
14790 +                               return -ENOMEM;
14791 +                       parg = mbuf;
14792 +               }
14793 +
14794 +               err = -EFAULT;
14795 +               if (_IOC_DIR(cmd) & _IOC_WRITE)
14796 +                       if (copy_from_user(parg, (void *)arg, _IOC_SIZE(cmd)))
14797 +                               goto out;
14798 +               break;
14799 +       }
14800 +
14801 +       /* call driver */
14802 +       err = func(inode, file, cmd, parg);
14803 +       if (err == -ENOIOCTLCMD)
14804 +               err = -EINVAL;
14805 +       if (err < 0)
14806 +               goto out;
14807 +
14808 +       /*  Copy results into user buffer  */
14809 +       switch (_IOC_DIR(cmd))
14810 +       {
14811 +       case _IOC_READ:
14812 +       case (_IOC_WRITE | _IOC_READ):
14813 +               if (copy_to_user((void *)arg, parg, _IOC_SIZE(cmd)))
14814 +                       err = -EFAULT;
14815 +               break;
14816 +       }
14817 +
14818 +out:
14819 +       if (mbuf)
14820 +               kfree(mbuf);
14821 +       return err;
14822 +}
14823 +
14824 +
14825 +static struct file_operations video_fops=
14826 +{
14827 +       .owner          = THIS_MODULE,
14828 +       .llseek         = no_llseek,
14829 +       .open           = video_open,
14830 +       .release        = video_release,
14831 +};
14832 +
14833 +static struct miscdevice codec_dev = {
14834 +       minor: CODEC_MINOR,
14835 +       name : "codec",
14836 +       fops : &video_fops
14837 +};
14838 +
14839 +static struct miscdevice preview_dev = {
14840 +       minor: PREVIEW_MINOR,
14841 +       name : "preview",
14842 +       fops : &video_fops
14843 +};
14844 +
14845 +
14846 +/**
14847 + *     video_register_device - register video4linux devices
14848 + *     @vfd:  video device structure we want to register
14849 + *     @type: type of device to register
14850 + *     @nr:   minor number
14851 + *
14852 + *     Zero is returned on success.
14853 + *      type : ignored.
14854 + *      nr :
14855 + *           0 Codec index
14856 + *           1 Preview index
14857 + */
14858 +int video_register_device(struct video_device *vfd, int type, int nr)
14859 +{
14860 +       int ret=0;
14861 +
14862 +       /* pick a minor number */
14863 +       down(&videodev_lock);
14864 +       set_vd (vfd, nr);
14865 +       vfd->minor=nr;
14866 +       up(&videodev_lock);
14867 +
14868 +       switch (vfd->minor) {
14869 +               case CODEC_MINOR:
14870 +                       ret = misc_register(&codec_dev);
14871 +                       if (ret) {
14872 +                               printk(KERN_ERR
14873 +                                               "can't misc_register : codec on minor=%d\n", CODEC_MINOR);
14874 +                               panic(" Give me misc codec \n");
14875 +                       }
14876 +                       break;
14877 +               case PREVIEW_MINOR:
14878 +                       ret = misc_register(&preview_dev);
14879 +                       if (ret) {
14880 +                               printk(KERN_ERR
14881 +                                               "can't misc_register (preview) on minor=%d\n", PREVIEW_MINOR);
14882 +                               panic(" Give me misc codec \n");
14883 +                       }
14884 +                       break;
14885 +       }
14886 +
14887 +#if 0 /* needed until all drivers are fixed */
14888 +       if (!vfd->release)
14889 +               printk(KERN_WARNING "videodev: \"%s\" has no release callback. "
14890 +                               "Please fix your driver for proper sysfs support, see "
14891 +                               "http://lwn.net/Articles/36850/\n", vfd->name);
14892 +#endif
14893 +       return 0;
14894 +}
14895 +
14896 +/**
14897 + *     video_unregister_device - unregister a video4linux device
14898 + *     @vfd: the device to unregister
14899 + *
14900 + *     This unregisters the passed device and deassigns the minor
14901 + *     number. Future open calls will be met with errors.
14902 + */
14903 +
14904 +void video_unregister_device(struct video_device *vfd)
14905 +{
14906 +       down(&videodev_lock);
14907 +
14908 +       if(get_vd(vfd->minor)!=vfd)
14909 +               panic("videodev: bad unregister");
14910 +
14911 +       if (vfd->minor== CODEC_MINOR)
14912 +               misc_deregister(&codec_dev);
14913 +       else
14914 +               misc_deregister(&preview_dev);
14915 +       set_vd (NULL, vfd->minor);
14916 +       up(&videodev_lock);
14917 +}
14918 +
14919 +
14920 +/*
14921 + *     Initialise video for linux
14922 + */
14923 +
14924 +static int __init videodev_init(void)
14925 +{
14926 +//     printk(KERN_INFO "FIMC2.0 Built:"__DATE__" "__TIME__"\n%s\n",fimc_version);
14927 +       return 0;
14928 +}
14929 +
14930 +static void __exit videodev_exit(void)
14931 +{
14932 +}
14933 +
14934 +module_init(videodev_init)
14935 +module_exit(videodev_exit)
14936 +
14937 +EXPORT_SYMBOL(video_register_device);
14938 +EXPORT_SYMBOL(fimc_version);
14939 +EXPORT_SYMBOL(video_unregister_device);
14940 +EXPORT_SYMBOL(video_usercopy);
14941 +EXPORT_SYMBOL(video_exclusive_open);
14942 +EXPORT_SYMBOL(video_exclusive_release);
14943 +
14944 +
14945 +MODULE_AUTHOR("SW.LEE <hitchcar@sec.samsung.com>");
14946 +MODULE_DESCRIPTION("VideoDev For FIMC2.0 MISC Drivers");
14947 +MODULE_LICENSE("GPL");
14948 +
14949 +
14950 +/*
14951 + * Local variables:
14952 + * c-basic-offset: 8
14953 + * End:
14954 + */
14955 --- /dev/null
14956 +++ b/arch/arm/mach-s3c2440/camera/videodev.h
14957 @@ -0,0 +1,108 @@
14958 +//#ifndef __LINUX_S3C_VIDEODEV_H
14959 +//#define __LINUX_S3C_VIDEODEV_H
14960 +
14961 +#include <linux/types.h>
14962 +#include <linux/version.h>
14963 +#include <media/v4l2-dev.h>
14964 +
14965 +#if 0
14966 +struct video_device
14967 +{
14968 +       /* device info */
14969 +       //      struct device *dev;
14970 +       char name[32];
14971 +       int type;       /* v4l1 */
14972 +       int type2;      /* v4l2 */
14973 +       int hardware;
14974 +       int minor;
14975 +
14976 +       /* device ops + callbacks */
14977 +       struct file_operations *fops;
14978 +       void (*release)(struct video_device *vfd);
14979 +
14980 +
14981 +#if 1 /* to be removed in 2.7.x */
14982 +       /* obsolete -- fops->owner is used instead */
14983 +       struct module *owner;
14984 +       /* dev->driver_data will be used instead some day.
14985 +        * Use the video_{get|set}_drvdata() helper functions,
14986 +        * so the switch over will be transparent for you.
14987 +        * Or use {pci|usb}_{get|set}_drvdata() directly. */
14988 +       void *priv;
14989 +#endif
14990 +
14991 +       /* for videodev.c intenal usage -- please don't touch */
14992 +       int users;                     /* video_exclusive_{open|close} ... */
14993 +       struct semaphore lock;         /* ... helper function uses these   */
14994 +       char devfs_name[64];           /* devfs */
14995 +       //      struct class_device class_dev; /* sysfs */
14996 +};
14997 +
14998 +#define VIDEO_MAJOR    81
14999 +
15000 +#define VFL_TYPE_GRABBER       0
15001 +
15002 +
15003 +extern int video_register_device(struct video_device *, int type, int nr);
15004 +extern void video_unregister_device(struct video_device *);
15005 +extern struct video_device* video_devdata(struct file*);
15006 +
15007 +
15008 +
15009 +struct video_picture
15010 +{
15011 +        __u16   brightness;
15012 +        __u16   hue;
15013 +        __u16   colour;
15014 +        __u16   contrast;
15015 +        __u16   whiteness;      /* Black and white only */
15016 +        __u16   depth;          /* Capture depth */
15017 +        __u16   palette;        /* Palette in use */
15018 +#define VIDEO_PALETTE_GREY      1       /* Linear greyscale */
15019 +#define VIDEO_PALETTE_HI240     2       /* High 240 cube (BT848) */
15020 +#define VIDEO_PALETTE_RGB565    3       /* 565 16 bit RGB */
15021 +#define VIDEO_PALETTE_RGB24     4       /* 24bit RGB */
15022 +#define VIDEO_PALETTE_RGB32     5       /* 32bit RGB */
15023 +#define VIDEO_PALETTE_RGB555    6       /* 555 15bit RGB */
15024 +#define VIDEO_PALETTE_YUV422    7       /* YUV422 capture */
15025 +#define VIDEO_PALETTE_YUYV      8
15026 +#define VIDEO_PALETTE_UYVY      9       /* The great thing about standards is ... */
15027 +#define VIDEO_PALETTE_YUV420    10
15028 +#define VIDEO_PALETTE_YUV411    11      /* YUV411 capture */
15029 +#define VIDEO_PALETTE_RAW       12      /* RAW capture (BT848) */
15030 +#define VIDEO_PALETTE_YUV422P   13      /* YUV 4:2:2 Planar */
15031 +#define VIDEO_PALETTE_YUV411P   14      /* YUV 4:1:1 Planar */
15032 +#define VIDEO_PALETTE_YUV420P   15      /* YUV 4:2:0 Planar */
15033 +#define VIDEO_PALETTE_YUV410P   16      /* YUV 4:1:0 Planar */
15034 +#define VIDEO_PALETTE_PLANAR    13      /* start of planar entries */
15035 +#define VIDEO_PALETTE_COMPONENT 7       /* start of component entries */
15036 +};
15037 +
15038 +extern int video_exclusive_open(struct inode *inode, struct file *file);
15039 +extern int video_exclusive_release(struct inode *inode, struct file *file);
15040 +extern int video_usercopy(struct inode *inode, struct file *file,
15041 +                          unsigned int cmd, unsigned long arg,
15042 +                          int (*func)(struct inode *inode, struct file *file,
15043 +                                      unsigned int cmd, void *arg));
15044 +
15045 +
15046 +
15047 +
15048 +#define VID_TYPE_CAPTURE        1       /* Can capture */
15049 +#define VID_TYPE_CLIPPING       32      /* Can clip */
15050 +#define VID_TYPE_FRAMERAM       64      /* Uses the frame buffer memory */
15051 +#define VID_TYPE_SCALES         128     /* Scalable */
15052 +#define VID_TYPE_SUBCAPTURE     512     /* Can capture subareas of the image */
15053 +
15054 +
15055 +
15056 +#endif
15057 +//#endif
15058 +
15059 +#define VID_HARDWARE_SAMSUNG_FIMC  255
15060 +
15061 +/*
15062 + * Local variables:
15063 + * c-basic-offset: 8
15064 + * End:
15065 + */
15066 --- /dev/null
15067 +++ b/arch/arm/mach-s3c2440/camera/video-driver.c
15068 @@ -0,0 +1,624 @@
15069 +/*
15070 +    Copyright (C) 2004 Samsung Electronics
15071 +                     SW.LEE <hitchcar@sec.samsung.com>
15072 +    This program is free software; you can redistribute it and/or modify
15073 +    it under the terms of the GNU General Public License as published by
15074 +    the Free Software Foundation; either version 2 of the License, or
15075 +    (at your option) any later version.
15076 +*/
15077 +
15078 +#include <linux/version.h>
15079 +#include <linux/module.h>
15080 +#include <linux/delay.h>
15081 +#include <linux/errno.h>
15082 +#include <linux/fs.h>
15083 +#include <linux/kernel.h>
15084 +#include <linux/major.h>
15085 +#include <linux/slab.h>
15086 +#include <linux/poll.h>
15087 +#include <linux/signal.h>
15088 +#include <linux/ioport.h>
15089 +#include <linux/sched.h>
15090 +#include <linux/types.h>
15091 +#include <linux/interrupt.h>
15092 +#include <linux/kmod.h>
15093 +#include <linux/vmalloc.h>
15094 +#include <linux/init.h>
15095 +#include <asm/io.h>
15096 +#include <asm/page.h>
15097 +#include <asm/irq.h>
15098 +#include <asm/semaphore.h>
15099 +#include <linux/miscdevice.h>
15100 +#include <asm/arch/irqs.h>
15101 +
15102 +//#define SW_DEBUG
15103 +#define CONFIG_VIDEO_V4L1_COMPAT
15104 +#include <linux/videodev.h>
15105 +#include "camif.h"
15106 +#include "miscdevice.h"
15107 +#include "cam_reg.h"
15108 +#include "sensor.h"
15109 +#include "userapp.h"
15110 +
15111 +#ifdef Z_API
15112 +#include "qt.h"
15113 +#endif
15114 +
15115 +/* Codec and Preview */
15116 +#define CAMIF_NUM  2
15117 +static camif_cfg_t  fimc[CAMIF_NUM];
15118 +u32 *camregs;
15119 +
15120 +static const char *driver_version =
15121 +       "$Id: video-driver.c,v 1.9 2004/06/02 03:10:36 swlee Exp $";
15122 +extern const char *fimc_version;
15123 +extern const char *fsm_version;
15124 +
15125 +extern void camif_start_c_with_p (camif_cfg_t *cfg, camif_cfg_t *other);
15126 +
15127 +camif_cfg_t * get_camif(int nr)
15128 +{
15129 +       camif_cfg_t *ret = NULL;
15130 +       switch(nr) {
15131 +       case CODEC_MINOR:
15132 +               ret = &fimc[0];
15133 +               break;
15134 +       case PREVIEW_MINOR:
15135 +               ret = &fimc[1];
15136 +               break;
15137 +       default:
15138 +               panic("Unknow Minor Number \n");
15139 +       }
15140 +       return ret;
15141 +}
15142 +
15143 +
15144 +static int camif_codec_start(camif_cfg_t *cfg)
15145 +{
15146 +       int  ret = 0;
15147 +       ret =camif_check_preview(cfg);
15148 +       switch(ret) {
15149 +       case 0:                 /* Play alone */
15150 +               DPRINTK("Start Alone \n");
15151 +               camif_4fsm_start(cfg);
15152 +               cfg->gc->status |= C_WORKING;
15153 +               break;
15154 +       case -ERESTARTSYS:       /* Busy , retry */
15155 +               //DPRINTK("Error \n");
15156 +               printk("Error \n");
15157 +               break;
15158 +       case 1:
15159 +               DPRINTK("need callback \n");
15160 +               ret = camif_callback_start(cfg);
15161 +               if(ret < 0 ) {
15162 +                       printk(KERN_INFO "Busy RESTART \n");
15163 +                       return ret; /* Busy, retry */
15164 +               }
15165 +               break;
15166 +       }
15167 +       return ret;
15168 +}
15169 +
15170 +
15171 +ssize_t camif_write (struct file *f, const char *b, size_t c,loff_t *offset)
15172 +{
15173 +       camif_cfg_t *cfg;
15174 +
15175 +       c = 0;                  /* return value */
15176 +       DPRINTK("\n");
15177 +       cfg = get_camif(MINOR(f->f_dentry->d_inode->i_rdev));
15178 +       switch (*b) {
15179 +               case 'O':
15180 +                       if (cfg->dma_type & CAMIF_PREVIEW) {
15181 +                               if (cfg->gc->status & C_WORKING) {
15182 +                                       camif_start_c_with_p(cfg,get_camif(CODEC_MINOR));
15183 +                               }
15184 +                               else  {
15185 +                                       camif_4fsm_start(cfg);
15186 +                               }
15187 +                       }
15188 +                       else{
15189 +                               c = camif_codec_start(cfg);
15190 +                               if(c < 0) c = 1; /* Error and neet to retry */
15191 +                       }
15192 +
15193 +                       break;
15194 +               case 'X':
15195 +                       camif_p_stop(cfg);
15196 +                       break;
15197 +               default:
15198 +                       panic("CAMERA:camif_write: Unexpected Param\n");
15199 +       }
15200 +       DPRINTK("end\n");
15201 +
15202 +       return c;
15203 +}
15204 +
15205 +
15206 +ssize_t camif_p_read(struct file *file, char *buf, size_t count, loff_t *pos)
15207 +{
15208 +       camif_cfg_t *cfg = NULL;
15209 +       size_t end;
15210 +
15211 +       cfg = get_camif(MINOR(file->f_dentry->d_inode->i_rdev));
15212 +       cfg->status = CAMIF_STARTED;
15213 +
15214 +       if (wait_event_interruptible(cfg->waitq,cfg->status == CAMIF_INT_HAPPEN))
15215 +               return -ERESTARTSYS;
15216 +
15217 +       cfg->status = CAMIF_STOPPED;
15218 +       end = min_t(size_t, cfg->pp_totalsize /cfg->pp_num, count);
15219 +       if (copy_to_user(buf, camif_g_frame(cfg), end))
15220 +               return -EFAULT;
15221 +
15222 +       return end;
15223 +}
15224 +
15225 +
15226 +static ssize_t
15227 +camif_c_read(struct file *file, char *buf, size_t count, loff_t *pos)
15228 +{
15229 +       camif_cfg_t *cfg = NULL;
15230 +       size_t end;
15231 +
15232 +       /* cfg = file->private_data; */
15233 +       cfg = get_camif(MINOR(file->f_dentry->d_inode->i_rdev));
15234 +#if 0
15235 +       if(file->f_flags & O_NONBLOCK) {
15236 +               printk(KERN_ERR"Don't Support NON_BLOCK \n");
15237 +       }
15238 +#endif
15239 +
15240 +      /* Change the below wait_event_interruptible func */
15241 +       if (wait_event_interruptible(cfg->waitq,cfg->status == CAMIF_INT_HAPPEN))
15242 +              return -ERESTARTSYS;
15243 +       cfg->status = CAMIF_STOPPED;
15244 +       end = min_t(size_t, cfg->pp_totalsize /cfg->pp_num, count);
15245 +       if (copy_to_user(buf, camif_g_frame(cfg), end))
15246 +              return -EFAULT;
15247 +       return end;
15248 +}
15249 +
15250 +
15251 +static irqreturn_t camif_c_irq(int irq, void *dev_id)
15252 +{
15253 +        camif_cfg_t *cfg = (camif_cfg_t *)dev_id;
15254 +
15255 +       DPRINTK("\n");
15256 +       camif_g_fifo_status(cfg);
15257 +       camif_g_frame_num(cfg);
15258 +       if(camif_enter_c_4fsm(cfg) != INSTANT_SKIP)
15259 +               wake_up_interruptible(&cfg->waitq);
15260 +
15261 +       return IRQ_HANDLED;
15262 +}
15263 +
15264 +static irqreturn_t camif_p_irq(int irq, void *dev_id)
15265 +{
15266 +        camif_cfg_t *cfg = (camif_cfg_t *)dev_id;
15267 +
15268 +       DPRINTK("\n");
15269 +       camif_g_fifo_status(cfg);
15270 +       camif_g_frame_num(cfg);
15271 +       if(camif_enter_p_4fsm(cfg) != INSTANT_SKIP)
15272 +               wake_up_interruptible(&cfg->waitq);
15273 +#if 0
15274 +       if( (cfg->perf.frames % 5) == 0)
15275 +               DPRINTK("5\n");
15276 +#endif
15277 +
15278 +       return IRQ_HANDLED;
15279 +}
15280 +
15281 +static void camif_release_irq(camif_cfg_t *cfg)
15282 +{
15283 +       disable_irq(cfg->irq);
15284 +       free_irq(cfg->irq, cfg);
15285 +}
15286 +
15287 +static int camif_irq_request(camif_cfg_t *cfg)
15288 +{
15289 +       int ret = 0;
15290 +
15291 +       if (cfg->dma_type & CAMIF_CODEC) {
15292 +               if ((ret = request_irq(cfg->irq, camif_c_irq,
15293 +                              0, cfg->shortname, cfg))) {
15294 +                       printk("request_irq(CAM_C) failed.\n");
15295 +               }
15296 +       }
15297 +       if (cfg->dma_type & CAMIF_PREVIEW) {
15298 +               if ((ret = request_irq(cfg->irq, camif_p_irq,
15299 +                              0, cfg->shortname, cfg))) {
15300 +                       printk("request_irq(CAM_P) failed.\n");
15301 +               }
15302 +       }
15303 +       return 0;
15304 +}
15305 +
15306 +static void camif_init_sensor(camif_cfg_t *cfg)
15307 +{
15308 +       camif_gc_t *gc =  cfg->gc;
15309 +       if (!gc->sensor)
15310 +               panic("CAMERA:I2C Client(Img Sensor)Not registered\n");
15311 +       if(!gc->init_sensor) {
15312 +               camif_reset(gc->reset_type, gc->reset_udelay);
15313 +               gc->sensor->driver->command(gc->sensor,SENSOR_INIT,NULL);
15314 +               gc->init_sensor = 1; /*sensor init done */
15315 +       }
15316 +       gc->sensor->driver->command(gc->sensor, USER_ADD, NULL);
15317 +}
15318 +
15319 +static int camif_open(struct inode *inode, struct file *file)
15320 +{
15321 +       int err;
15322 +       camif_cfg_t * cfg = get_camif(MINOR(inode->i_rdev));
15323 +
15324 +       if(cfg->dma_type & CAMIF_PREVIEW) {
15325 +               if(down_interruptible(&cfg->gc->lock))
15326 +                       return -ERESTARTSYS;
15327 +               if (cfg->dma_type & CAMIF_PREVIEW) {
15328 +                       cfg->gc->status &= ~PNOTWORKING;
15329 +               }
15330 +               up(&cfg->gc->lock);
15331 +       }
15332 +       err = video_exclusive_open(inode,file);
15333 +       cfg->gc->user++;
15334 +       cfg->status = CAMIF_STOPPED;
15335 +       if (err < 0)  return err;
15336 +       if (file->f_flags & O_NONCAP ) {
15337 +               printk("Don't Support Non-capturing open \n");
15338 +               return 0;
15339 +       }
15340 +       file->private_data = cfg;
15341 +       camif_irq_request(cfg);
15342 +       camif_init_sensor(cfg);
15343 +       return 0;
15344 +}
15345 +
15346 +#if 0
15347 +static void print_pregs(void)
15348 +{
15349 +       printk(" CISRCFMT 0x%08X  \n", CISRCFMT);
15350 +       printk(" CIWDOFST 0x%08X  \n", CIWDOFST);
15351 +       printk(" CIGCTRL  0x%08X  \n", CIGCTRL);
15352 +       printk(" CIPRTRGFMT 0x%08X  \n", CIPRTRGFMT);
15353 +       printk(" CIPRCTRL 0x%08X  \n", CIPRCTRL);
15354 +       printk(" CIPRSCPRERATIO 0x%08X  \n", CIPRSCPRERATIO);
15355 +       printk(" CIPRSCPREDST 0x%08X  \n", CIPRSCPREDST);
15356 +       printk(" CIPRSCCTRL 0x%08X  \n", CIPRSCCTRL);
15357 +       printk(" CIPRTAREA 0x%08X  \n", CIPRTAREA);
15358 +       printk(" CIPRSTATUS 0x%08X  \n", CIPRSTATUS);
15359 +       printk(" CIIMGCPT 0x%08X  \n", CIIMGCPT);
15360 +}
15361 +
15362 +static void print_cregs(void)
15363 +{
15364 +       printk(" CISRCFMT 0x%08X  \n", CISRCFMT);
15365 +       printk(" CIWDOFST 0x%08X  \n", CIWDOFST);
15366 +       printk(" CIGCTRL  0x%08X  \n", CIGCTRL);
15367 +       printk(" CICOCTRL 0x%8X   \n", CICOCTRL);
15368 +       printk(" CICOSCPRERATIO 0x%08X  \n", CICOSCPRERATIO);
15369 +       printk(" CICOSCPREDST 0x%08X  \n", CICOSCPREDST);
15370 +       printk(" CICOSCCTRL 0x%08X  \n", CICOSCCTRL);
15371 +       printk(" CICOTAREA 0x%08X  \n", CICOTAREA);
15372 +       printk(" CICOSTATUS 0x%8X \n", CICOSTATUS);
15373 +       printk(" CIIMGCPT 0x%08X  \n", CIIMGCPT);
15374 +}
15375 +#endif
15376 +
15377 +
15378 +static int camif_release(struct inode *inode, struct file *file)
15379 +{
15380 +       camif_cfg_t * cfg = get_camif(MINOR(inode->i_rdev));
15381 +
15382 +       //DPRINTK(" cfg->status 0x%0X cfg->gc->status 0x%0X \n", cfg->status,cfg->gc->status );
15383 +       if (cfg->dma_type & CAMIF_PREVIEW) {
15384 +               if(down_interruptible(&cfg->gc->lock))
15385 +                       return -ERESTARTSYS;
15386 +               cfg->gc->status &= ~PWANT2START;
15387 +               cfg->gc->status |= PNOTWORKING;
15388 +               up(&cfg->gc->lock);
15389 +       }
15390 +       else {
15391 +               cfg->gc->status &= ~CWANT2START; /* No need semaphore */
15392 +       }
15393 +       camif_dynamic_close(cfg);
15394 +       camif_release_irq(cfg);
15395 +       video_exclusive_release(inode,file);
15396 +       camif_p_stop(cfg);
15397 +       cfg->gc->sensor->driver->command(cfg->gc->sensor, USER_EXIT, NULL);
15398 +       cfg->gc->user--;
15399 +       cfg->status = CAMIF_STOPPED;
15400 +       return 0;
15401 +}
15402 +
15403 +static void fimc_config(camif_cfg_t *cfg,u32 x, u32 y, int bpp)
15404 +{
15405 +       cfg->target_x = x;
15406 +       cfg->target_y = y;
15407 +
15408 +       switch (bpp) {
15409 +       case 16:
15410 +               cfg->fmt = CAMIF_RGB16;
15411 +               break;
15412 +       case 24:
15413 +               cfg->fmt = CAMIF_RGB24;
15414 +               break;
15415 +       case 420:
15416 +               cfg->fmt = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR420;
15417 +               break;
15418 +       case 422:
15419 +               cfg->fmt = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR422;
15420 +               break;
15421 +       default:
15422 +               panic("Wrong BPP \n");
15423 +       }
15424 +}
15425 +
15426 +
15427 +static int
15428 +camif_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
15429 +{
15430 +       int ret = 0;
15431 +       camif_cfg_t *cfg  = file->private_data;
15432 +       camif_param_t par;
15433 +
15434 +       switch (cmd) {
15435 +               case CMD_CAMERA_INIT:
15436 +                       if (copy_from_user(&par,(camif_param_t *)arg,
15437 +                                               sizeof(camif_param_t)))
15438 +                               return -EFAULT;
15439 +                       fimc_config(cfg,par.dst_x, par.dst_y, par.bpp);
15440 +                       if (camif_dynamic_open(cfg)) {
15441 +                               printk(" Eror Happens \n");
15442 +                               ret = -1;
15443 +                       }
15444 +
15445 +                       switch (par.flip) {
15446 +                       case 3 :
15447 +                               cfg->flip = CAMIF_FLIP_MIRROR;
15448 +                               break;
15449 +                       case 1 :
15450 +                               cfg->flip = CAMIF_FLIP_X;
15451 +                               break;
15452 +                       case 2 :
15453 +                               cfg->flip = CAMIF_FLIP_Y;
15454 +                               break;
15455 +                       case 0 :
15456 +                       default:
15457 +                               cfg->flip = CAMIF_FLIP;
15458 +                       }
15459 +                       break;
15460 +       /* Todo
15461 +               case CMD_SENSOR_BRIGHTNESS:
15462 +                       cfg->gc->sensor->driver->command(cfg->gc->sensor, SENSOR_BRIGHTNESS, NULL);
15463 +                       break;
15464 +       */
15465 +               default:
15466 +                       ret = -EINVAL;
15467 +                       break;
15468 +       }
15469 +
15470 +       return ret;
15471 +}
15472 +
15473 +
15474 +#if 0
15475 +static int camif_ioctl(struct inode *inode, struct file *file,
15476 +                     unsigned int cmd, unsigned long arg)
15477 +{
15478 +//     camif_cfg_t *cfg  = file->private_data;
15479 +
15480 +
15481 +       switch (cmd) {
15482 +/*     case Some_other_action */
15483 +       default:
15484 +               return video_usercopy(inode, file, cmd, arg, camif_do_ioctl);
15485 +       }
15486 +}
15487 +#endif
15488 +
15489 +static struct file_operations camif_c_fops =
15490 +{
15491 +       .owner    = THIS_MODULE,
15492 +       .open     = camif_open,
15493 +       .release  = camif_release,
15494 +       .ioctl    = camif_ioctl,
15495 +       .read     = camif_c_read,
15496 +       .write    = camif_write,
15497 +};
15498 +
15499 +static struct file_operations camif_p_fops =
15500 +{
15501 +       .owner    = THIS_MODULE,
15502 +       .open     = camif_open,
15503 +       .release  = camif_release,
15504 +       .ioctl    = camif_ioctl,
15505 +#ifdef Z_API
15506 +       .read     = z_read,
15507 +       .write    = z_write,
15508 +#else
15509 +       .read     = camif_p_read,
15510 +       .write    = camif_write,
15511 +#endif
15512 +};
15513 +
15514 +static struct video_device codec_template =
15515 +{
15516 +       .name     = "CODEC_IF",
15517 +       .type     = VID_TYPE_CAPTURE|VID_TYPE_CLIPPING|VID_TYPE_SCALES,
15518 +/*     .hardware = VID_HARDWARE_SAMSUNG_FIMC20, */
15519 +       .fops     = &camif_c_fops,
15520 +//     .release  = camif_release
15521 +       .minor    = -1,
15522 +};
15523 +
15524 +static struct video_device preview_template =
15525 +{
15526 +       .name     = "PREVIEW_IF",
15527 +       .type     = VID_TYPE_CAPTURE|VID_TYPE_CLIPPING|VID_TYPE_SCALES,
15528 +/*     .hardware = VID_HARDWARE_SAMSUNG_FIMC20, */
15529 +       .fops     = &camif_p_fops,
15530 +       .minor    = -1,
15531 +};
15532 +
15533 +static int preview_init(camif_cfg_t *cfg)
15534 +{
15535 +       char name[16]="CAM_PREVIEW";
15536 +
15537 +       memset(cfg, 0, sizeof(camif_cfg_t));
15538 +       cfg->target_x = 640;
15539 +       cfg->target_y = 480;
15540 +       cfg->pp_num   = 4;
15541 +       cfg->dma_type = CAMIF_PREVIEW;
15542 +       cfg->fmt      = CAMIF_RGB16;
15543 +       cfg->flip     = CAMIF_FLIP_Y;
15544 +       cfg->v        = &preview_template;
15545 +       mutex_init(&cfg->v->lock);
15546 +       cfg->irq       = IRQ_S3C2440_CAM_P;
15547 +
15548 +       strcpy(cfg->shortname,name);
15549 +        init_waitqueue_head(&cfg->waitq);
15550 +       cfg->status = CAMIF_STOPPED;
15551 +       return cfg->status;
15552 +}
15553 +
15554 +static int codec_init(camif_cfg_t *cfg)
15555 +{
15556 +       char name[16]="CAM_CODEC";
15557 +
15558 +       memset(cfg, 0, sizeof(camif_cfg_t));
15559 +       cfg->target_x = 176;
15560 +       cfg->target_y = 144;
15561 +       cfg->pp_num   = 4;
15562 +       cfg->dma_type = CAMIF_CODEC;
15563 +       cfg->fmt      = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR420;
15564 +       cfg->flip     = CAMIF_FLIP_X;
15565 +       cfg->v         = &codec_template;
15566 +       mutex_init(&cfg->v->lock);
15567 +       cfg->irq       = IRQ_S3C2440_CAM_C;
15568 +       strcpy(cfg->shortname,name);
15569 +       init_waitqueue_head(&cfg->waitq);
15570 +       cfg->status = CAMIF_STOPPED;
15571 +       return cfg->status;
15572 +}
15573 +
15574 +static void camif_init(void)
15575 +{
15576 +       camif_setup_sensor();
15577 +}
15578 +
15579 +
15580 +
15581 +static void print_version(void)
15582 +{
15583 +       printk(KERN_INFO"FIMC built:"__DATE__ " "__TIME__"\n%s\n%s\n%s\n",
15584 +                                       fimc_version, driver_version,fsm_version);
15585 +}
15586 +
15587 +
15588 +static int camif_m_in(void)
15589 +{
15590 +       int ret = -EINVAL;
15591 +       camif_cfg_t * cfg;
15592 +
15593 +       printk(KERN_INFO"Starting S3C2440 Camera Driver\n");
15594 +
15595 +       camregs = ioremap(CAM_BASE_ADD, 0x100);
15596 +       if (!camregs) {
15597 +               printk(KERN_ERR"Unable to map camera regs\n");
15598 +               ret = -ENOMEM;
15599 +               goto bail1;
15600 +       }
15601 +
15602 +       camif_init();
15603 +       cfg = get_camif(CODEC_MINOR);
15604 +       codec_init(cfg);
15605 +
15606 +       ret = video_register_device(cfg->v,0,CODEC_MINOR);
15607 +       if (ret) {
15608 +                       printk(KERN_ERR"Couldn't register codec driver.\n");
15609 +                       goto bail2;
15610 +       }
15611 +       cfg = get_camif(PREVIEW_MINOR);
15612 +       preview_init(cfg);
15613 +       ret = video_register_device(cfg->v,0,PREVIEW_MINOR);
15614 +       if (ret) {
15615 +                       printk(KERN_ERR"Couldn't register preview driver.\n");
15616 +                       goto bail3; /* hm seems it us unregistered the once */
15617 +       }
15618 +
15619 +       print_version();
15620 +       return 0;
15621 +
15622 +bail3:
15623 +       video_unregister_device(cfg->v);
15624 +bail2:
15625 +       iounmap(camregs);
15626 +       camregs = NULL;
15627 +bail1:
15628 +       return ret;
15629 +}
15630 +
15631 +static void unconfig_device(camif_cfg_t *cfg)
15632 +{
15633 +       video_unregister_device(cfg->v);
15634 +       camif_hw_close(cfg);
15635 +       iounmap(camregs);
15636 +       //memset(cfg, 0, sizeof(camif_cfg_t));
15637 +       camregs = NULL;
15638 +}
15639 +
15640 +static void camif_m_out(void)  /* module out */
15641 +{
15642 +       camif_cfg_t *cfg;
15643 +
15644 +       cfg = get_camif(CODEC_MINOR);
15645 +       unconfig_device(cfg);
15646 +       cfg = get_camif(PREVIEW_MINOR);
15647 +       unconfig_device(cfg);
15648 +
15649 +       return;
15650 +}
15651 +
15652 +void camif_register_decoder(struct i2c_client *ptr)
15653 +{
15654 +       camif_cfg_t *cfg;
15655 +       void * data = i2c_get_clientdata(ptr);
15656 +
15657 +       cfg =get_camif(CODEC_MINOR);
15658 +       cfg->gc = (camif_gc_t *)(data);
15659 +
15660 +       cfg =get_camif(PREVIEW_MINOR);
15661 +       cfg->gc = (camif_gc_t *)(data);
15662 +
15663 +       sema_init(&cfg->gc->lock, 1); /* global lock for both Codec and Preview */
15664 +       cfg->gc->status |= PNOTWORKING; /* Default Value */
15665 +       camif_hw_open(cfg->gc);
15666 +}
15667 +
15668 +void camif_unregister_decoder(struct i2c_client *ptr)
15669 +{
15670 +       camif_gc_t *gc;
15671 +       void * data = i2c_get_clientdata(ptr);
15672 +
15673 +       gc = (camif_gc_t *)(data);
15674 +       gc->init_sensor = 0; /* need to modify */
15675 +}
15676 +
15677 +module_init(camif_m_in);
15678 +module_exit(camif_m_out);
15679 +
15680 +EXPORT_SYMBOL(camif_register_decoder);
15681 +EXPORT_SYMBOL(camif_unregister_decoder);
15682 +
15683 +MODULE_AUTHOR("SW.LEE <hitchcar@sec.samsung.com>");
15684 +MODULE_DESCRIPTION("Video-Driver For Fimc2.0 MISC Drivers");
15685 +MODULE_LICENSE("GPL");
15686 +
15687 +
15688 +/*
15689 + * Local variables:
15690 + * c-basic-offset: 8
15691 + * End:
15692 + */
15693 --- a/arch/arm/mach-s3c2440/dma.c
15694 +++ b/arch/arm/mach-s3c2440/dma.c
15695 @@ -25,12 +25,12 @@
15696
15697  #include <plat/regs-serial.h>
15698  #include <mach/regs-gpio.h>
15699 -#include <asm/plat-s3c/regs-ac97.h>
15700 +#include <plat/regs-ac97.h>
15701  #include <mach/regs-mem.h>
15702  #include <mach/regs-lcd.h>
15703  #include <mach/regs-sdi.h>
15704  #include <asm/plat-s3c24xx/regs-iis.h>
15705 -#include <asm/plat-s3c24xx/regs-spi.h>
15706 +#include <plat/regs-spi.h>
15707
15708  static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
15709         [DMACH_XD0] = {
15710 --- /dev/null
15711 +++ b/arch/arm/mach-s3c2440/fiq_c_isr.c
15712 @@ -0,0 +1,321 @@
15713 +/*
15714 + * Copyright 2007  Andy Green <andy@warmcat.com>
15715 + * S3C modfifications
15716 + * Copyright 2008 Andy Green <andy@openmoko.com>
15717 + */
15718 +
15719 +#include <linux/module.h>
15720 +#include <linux/kernel.h>
15721 +#include <mach/hardware.h>
15722 +#include <asm/fiq.h>
15723 +#include "fiq_c_isr.h"
15724 +#include <linux/sysfs.h>
15725 +#include <linux/device.h>
15726 +#include <linux/delay.h>
15727 +#include <linux/platform_device.h>
15728 +
15729 +#include <asm/io.h>
15730 +
15731 +#include <plat/cpu.h>
15732 +#include <plat/irq.h>
15733 +
15734 +#include <mach/pwm.h>
15735 +#include <plat/regs-timer.h>
15736 +
15737 +/*
15738 + * Major Caveats for using FIQ
15739 + * ---------------------------
15740 + *
15741 + * 1) it CANNOT touch any vmalloc()'d memory, only memory
15742 + *    that was kmalloc()'d.  Static allocations in the monolithic kernel
15743 + *    are kmalloc()'d so they are okay.  You can touch memory-mapped IO, but
15744 + *    the pointer for it has to have been stored in kmalloc'd memory.  The
15745 + *    reason for this is simple: every now and then Linux turns off interrupts
15746 + *    and reorders the paging tables.  If a FIQ happens during this time, the
15747 + *    virtual memory space can be partly or entirely disordered or missing.
15748 + *
15749 + * 2) Because vmalloc() is used when a module is inserted, THIS FIQ
15750 + *    ISR HAS TO BE IN THE MONOLITHIC KERNEL, not a module.  But the way
15751 + *    it is set up, you can all to enable and disable it from your module
15752 + *    and intercommunicate with it through struct fiq_ipc
15753 + *    fiq_ipc which you can define in
15754 + *    asm/archfiq_ipc_type.h.  The reason is the same as above, a
15755 + *    FIQ could happen while even the ISR is not present in virtual memory
15756 + *    space due to pagetables being changed at the time.
15757 + *
15758 + * 3) You can't call any Linux API code except simple macros
15759 + *    - understand that FIQ can come in at any time, no matter what
15760 + *      state of undress the kernel may privately be in, thinking it
15761 + *      locked the door by turning off interrupts... FIQ is an
15762 + *      unstoppable monster force (which is its value)
15763 + *    - they are not vmalloc()'d memory safe
15764 + *    - they might do crazy stuff like sleep: FIQ pisses fire and
15765 + *      is not interested in 'sleep' that the weak seem to need
15766 + *    - calling APIs from FIQ can re-enter un-renterable things
15767 + *    - summary: you cannot interoperate with linux APIs directly in the FIQ ISR
15768 + *
15769 + * If you follow these rules, it is fantastic, an extremely powerful, solid,
15770 + * genuine hard realtime feature.
15771 + *
15772 + */
15773 +
15774 +/* more than enough to cover our jump instruction to the isr */
15775 +#define SIZEOF_FIQ_JUMP 4
15776 +
15777 +#define FIQ_VECTOR 0xffff001c
15778 +
15779 +/* we put the stack at the area after the FIQ vector */
15780 +#define FIQ_STACK_SIZE 256
15781 +
15782 +/* only one FIQ ISR possible, okay to do these here */
15783 +u32 _fiq_ack_mask; /* used by isr exit define */
15784 +unsigned long _fiq_count_fiqs; /* used by isr exit define */
15785 +static int _fiq_irq; /* private ; irq index we were started with, or 0 */
15786 +struct s3c2410_pwm pwm_timer_fiq;
15787 +int _fiq_timer_index;
15788 +u16 _fiq_timer_divisor;
15789 +u8 fiq_ready;
15790 +
15791 +/* this function must live in the monolithic kernel somewhere!  A module is
15792 + * NOT good enough!
15793 + */
15794 +extern void __attribute__ ((naked)) s3c2440_fiq_isr(void);
15795 +
15796 +static void fiq_set_vector_and_regs(void);
15797 +
15798 +
15799 +/* this is copied into the hard FIQ vector during init */
15800 +
15801 +static void __attribute__ ((naked)) s3c2440_FIQ_Branch(void)
15802 +{
15803 +       asm __volatile__ (
15804 +               "mov pc, r8 ; "
15805 +       );
15806 +}
15807 +
15808 +/* sysfs */
15809 +
15810 +static ssize_t show_count(struct device *dev, struct device_attribute *attr,
15811 +                        char *buf)
15812 +{
15813 +       return sprintf(buf, "%ld\n", _fiq_count_fiqs);
15814 +}
15815 +
15816 +static DEVICE_ATTR(count, 0444, show_count, NULL);
15817 +
15818 +static struct attribute *s3c2440_fiq_sysfs_entries[] = {
15819 +       &dev_attr_count.attr,
15820 +       NULL
15821 +};
15822 +
15823 +static struct attribute_group s3c2440_fiq_attr_group = {
15824 +       .name   = "fiq",
15825 +       .attrs  = s3c2440_fiq_sysfs_entries,
15826 +};
15827 +
15828 +/*
15829 + * call this from your kernel module to set up the FIQ ISR to service FIQs,
15830 + * You need to have configured your FIQ input pin before anything will happen
15831 + *
15832 + * call it with, eg, IRQ_TIMER3 from asm-arm/arch-s3c2410/irqs.h
15833 + *
15834 + * you still need to clear the source interrupt in S3C2410_INTMSK to get
15835 + * anything good happening
15836 + */
15837 +static int fiq_init_irq_source(int irq_index_fiq)
15838 +{
15839 +       int rc = 0;
15840 +
15841 +       if (!irq_index_fiq) /* no interrupt */
15842 +               goto bail;
15843 +
15844 +       local_fiq_disable();
15845 +
15846 +       _fiq_irq = irq_index_fiq;
15847 +       _fiq_ack_mask = 1 << (irq_index_fiq - S3C2410_CPUIRQ_OFFSET);
15848 +       _fiq_timer_index = (irq_index_fiq - IRQ_TIMER0);
15849 +
15850 +       /* set up the timer to operate as a pwm device */
15851 +
15852 +       rc = s3c2410_pwm_init(&pwm_timer_fiq);
15853 +       if (rc)
15854 +               goto bail;
15855 +
15856 +       pwm_timer_fiq.timerid = PWM0 + _fiq_timer_index;
15857 +       pwm_timer_fiq.prescaler = (6 - 1) / 2;
15858 +       pwm_timer_fiq.divider = S3C2410_TCFG1_MUX3_DIV2;
15859 +       /* default rate == ~32us */
15860 +       pwm_timer_fiq.counter = pwm_timer_fiq.comparer = 3000;
15861 +
15862 +       rc = s3c2410_pwm_enable(&pwm_timer_fiq);
15863 +       if (rc)
15864 +               goto bail;
15865 +
15866 +       s3c2410_pwm_start(&pwm_timer_fiq);
15867 +
15868 +       _fiq_timer_divisor = 0xffff; /* so kick will work initially */
15869 +
15870 +       /* let our selected interrupt be a magic FIQ interrupt */
15871 +       __raw_writel(_fiq_ack_mask, S3C2410_INTMOD);
15872 +
15873 +       /* it's ready to go as soon as we unmask the source in S3C2410_INTMSK */
15874 +       local_fiq_enable();
15875 +bail:
15876 +       return rc;
15877 +}
15878 +
15879 +
15880 +/* call this from your kernel module to disable generation of FIQ actions */
15881 +static void fiq_disable_irq_source(void)
15882 +{
15883 +       /* nothing makes FIQ any more */
15884 +       __raw_writel(0, S3C2410_INTMOD);
15885 +       local_fiq_disable();
15886 +       _fiq_irq = 0; /* no active source interrupt now either */
15887 +}
15888 +
15889 +/*
15890 + * fiq_kick() forces a FIQ event to happen shortly after leaving the routine
15891 + */
15892 +void fiq_kick(void)
15893 +{
15894 +       unsigned long flags;
15895 +       u32 tcon;
15896 +
15897 +       if (!fiq_ready) {
15898 +               printk(KERN_ERR "fiq_kick called before fiq probed\n");
15899 +               return;
15900 +       }
15901 +
15902 +       /* we have to take care about FIQ because this modification is
15903 +        * non-atomic, FIQ could come in after the read and before the
15904 +        * writeback and its changes to the register would be lost
15905 +        * (platform INTMSK mod code is taken care of already)
15906 +        */
15907 +       local_save_flags(flags);
15908 +       local_fiq_disable();
15909 +       /* allow FIQs to resume */
15910 +       __raw_writel(__raw_readl(S3C2410_INTMSK) &
15911 +                    ~(1 << (_fiq_irq - S3C2410_CPUIRQ_OFFSET)),
15912 +                    S3C2410_INTMSK);
15913 +       tcon = __raw_readl(S3C2410_TCON) & ~S3C2410_TCON_T3START;
15914 +       /* fake the timer to a count of 1 */
15915 +       __raw_writel(1, S3C2410_TCNTB(_fiq_timer_index));
15916 +       __raw_writel(tcon | S3C2410_TCON_T3MANUALUPD, S3C2410_TCON);
15917 +       __raw_writel(tcon | S3C2410_TCON_T3MANUALUPD | S3C2410_TCON_T3START,
15918 +                    S3C2410_TCON);
15919 +       __raw_writel(tcon | S3C2410_TCON_T3START, S3C2410_TCON);
15920 +       local_irq_restore(flags);
15921 +}
15922 +EXPORT_SYMBOL_GPL(fiq_kick);
15923 +
15924 +
15925 +
15926 +
15927 +static int __init sc32440_fiq_probe(struct platform_device *pdev)
15928 +{
15929 +       struct resource *r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
15930 +       struct sc32440_fiq_platform_data *pdata = pdev->dev.platform_data;
15931 +       int ret;
15932 +
15933 +       if (!r)
15934 +               return -EIO;
15935 +
15936 +       /* configure for the interrupt we are meant to use */
15937 +       printk(KERN_INFO "Enabling FIQ using irq %d\n", r->start);
15938 +
15939 +       fiq_set_vector_and_regs();
15940 +       fiq_init_irq_source(r->start);
15941 +
15942 +       ret = sysfs_create_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group);
15943 +       if (ret)
15944 +               return ret;
15945 +
15946 +       fiq_ready = 1;
15947 +
15948 +       /*
15949 +        * if wanted, users can defer registration of devices
15950 +        * that depend on FIQ until after we register, and can use our
15951 +        * device as parent so suspend-resume ordering is correct
15952 +        */
15953 +       if (pdata->attach_child_devices)
15954 +               (pdata->attach_child_devices)(&pdev->dev);
15955 +
15956 +       return 0;
15957 +}
15958 +
15959 +static int sc32440_fiq_remove(struct platform_device *pdev)
15960 +{
15961 +       fiq_disable_irq_source();
15962 +       sysfs_remove_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group);
15963 +
15964 +       return 0;
15965 +}
15966 +
15967 +static void fiq_set_vector_and_regs(void)
15968 +{
15969 +       struct pt_regs regs;
15970 +
15971 +       /* prep the special FIQ mode regs */
15972 +       memset(&regs, 0, sizeof(regs));
15973 +       regs.ARM_r8 = (unsigned long)s3c2440_fiq_isr;
15974 +       regs.ARM_r10 = FIQ_VECTOR + SIZEOF_FIQ_JUMP;
15975 +       regs.ARM_sp = FIQ_VECTOR + SIZEOF_FIQ_JUMP + FIQ_STACK_SIZE - 4;
15976 +
15977 +       /* copy our jump to the real ISR into the hard vector address */
15978 +       set_fiq_handler(s3c2440_FIQ_Branch, SIZEOF_FIQ_JUMP);
15979 +
15980 +       /* set up the special FIQ-mode-only registers from our regs */
15981 +       set_fiq_regs(&regs);
15982 +}
15983 +
15984 +#ifdef CONFIG_PM
15985 +static int sc32440_fiq_suspend(struct platform_device *pdev, pm_message_t state)
15986 +{
15987 +       /* nothing makes FIQ any more */
15988 +       __raw_writel(0, S3C2410_INTMOD);
15989 +       local_fiq_disable();
15990 +
15991 +       return 0;
15992 +}
15993 +
15994 +static int sc32440_fiq_resume(struct platform_device *pdev)
15995 +{
15996 +       fiq_set_vector_and_regs();
15997 +       fiq_init_irq_source(_fiq_irq);
15998 +       return 0;
15999 +}
16000 +#else
16001 +#define sc32440_fiq_suspend    NULL
16002 +#define sc32440_fiq_resume     NULL
16003 +#endif
16004 +
16005 +static struct platform_driver sc32440_fiq_driver = {
16006 +       .driver = {
16007 +               .name   = "sc32440_fiq",
16008 +               .owner  = THIS_MODULE,
16009 +       },
16010 +
16011 +       .probe   = sc32440_fiq_probe,
16012 +       .remove  = __devexit_p(sc32440_fiq_remove),
16013 +       .suspend = sc32440_fiq_suspend,
16014 +       .resume  = sc32440_fiq_resume,
16015 +};
16016 +
16017 +static int __init sc32440_fiq_init(void)
16018 +{
16019 +       fiq_set_vector_and_regs();
16020 +
16021 +       return platform_driver_register(&sc32440_fiq_driver);
16022 +}
16023 +
16024 +static void __exit sc32440_fiq_exit(void)
16025 +{
16026 +       fiq_disable_irq_source();
16027 +}
16028 +
16029 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
16030 +MODULE_LICENSE("GPL");
16031 +
16032 +module_init(sc32440_fiq_init);
16033 +module_exit(sc32440_fiq_exit);
16034 --- /dev/null
16035 +++ b/arch/arm/mach-s3c2440/fiq_c_isr.h
16036 @@ -0,0 +1,76 @@
16037 +#ifndef _LINUX_FIQ_C_ISR_H
16038 +#define _LINUX_FIQ_C_ISR_H
16039 +
16040 +#include <mach/regs-irq.h>
16041 +#include <linux/platform_device.h>
16042 +
16043 +extern unsigned long _fiq_count_fiqs;
16044 +extern u32 _fiq_ack_mask;
16045 +extern int _fiq_timer_index;
16046 +extern u16 _fiq_timer_divisor;
16047 +
16048 +/* platform data */
16049 +
16050 +struct sc32440_fiq_platform_data {
16051 +       /*
16052 +        * give an opportunity to use us as parent for
16053 +        * devices that depend on us
16054 +        */
16055 +       void (*attach_child_devices)(struct device *parent_device);
16056 +};
16057 +
16058 +/* This CANNOT be implemented in a module -- it has to be used in code
16059 + * included in the monolithic kernel
16060 + */
16061 +
16062 +#define FIQ_HANDLER_START() \
16063 +void __attribute__ ((naked)) s3c2440_fiq_isr(void) \
16064 +{\
16065 +       /*\
16066 +        * you can declare local vars here, take care to set the frame size\
16067 +        *  below accordingly if there are more than a few dozen bytes of them\
16068 +        */\
16069 +
16070 +/* stick your locals here :-)
16071 + * Do NOT initialize them here!  define them and initialize them after
16072 + * FIQ_HANDLER_ENTRY() is done.
16073 + */
16074 +
16075 +#define FIQ_HANDLER_ENTRY(LOCALS, FRAME) \
16076 +       const int _FIQ_FRAME_SIZE = FRAME; \
16077 +       /* entry takes care to store registers we will be treading on here */\
16078 +       asm __volatile__ (\
16079 +               /* stash FIQ and r0-r8 normal regs */\
16080 +               "stmdb  sp!, {r0-r12, lr};"\
16081 +               /* allow SP to get some space */\
16082 +               "sub     sp, sp, %1 ;"\
16083 +               /* !! THIS SETS THE FRAME, adjust to > sizeof locals */\
16084 +               "sub     fp, sp, %0 ;"\
16085 +               :\
16086 +               : "rI" (LOCALS), "rI" (FRAME)\
16087 +               :"r9"\
16088 +       );
16089 +
16090 +/* stick your ISR code here and then end with... */
16091 +
16092 +#define FIQ_HANDLER_END() \
16093 +       _fiq_count_fiqs++;\
16094 +       __raw_writel(_fiq_ack_mask, S3C2410_SRCPND);\
16095 +\
16096 +       /* exit back to normal mode restoring everything */\
16097 +       asm __volatile__ (\
16098 +               /* pop our allocation */\
16099 +               "add     sp, sp, %0 ;"\
16100 +               /* return FIQ regs back to pristine state\
16101 +                * and get normal regs back\
16102 +                */\
16103 +               "ldmia  sp!, {r0-r12, lr};"\
16104 +\
16105 +               /* return */\
16106 +               "subs   pc, lr, #4;"\
16107 +               : \
16108 +               : "rI" (_FIQ_FRAME_SIZE) \
16109 +       );\
16110 +}
16111 +
16112 +#endif /* _LINUX_FIQ_C_ISR_H */
16113 --- a/arch/arm/mach-s3c2440/Kconfig
16114 +++ b/arch/arm/mach-s3c2440/Kconfig
16115 @@ -22,12 +22,20 @@ config S3C2440_DMA
16116         help
16117           Support for S3C2440 specific DMA code5A
16118
16119 +config S3C2440_C_FIQ
16120 +       bool "FIQ ISR support in C"
16121 +       depends on ARCH_S3C2410
16122 +       select FIQ
16123 +       help
16124 +         Support for S3C2440 FIQ support in C -- see
16125 +         ./arch/arm/mach-s3c2440/fiq_c_isr.c
16126
16127  menu "S3C2440 Machines"
16128
16129  config MACH_ANUBIS
16130         bool "Simtec Electronics ANUBIS"
16131         select CPU_S3C2440
16132 +       select S3C24XX_DCLK
16133         select PM_SIMTEC if PM
16134         select HAVE_PATA_PLATFORM
16135         help
16136 @@ -37,6 +45,7 @@ config MACH_ANUBIS
16137  config MACH_OSIRIS
16138         bool "Simtec IM2440D20 (OSIRIS) module"
16139         select CPU_S3C2440
16140 +       select S3C24XX_DCLK
16141         select PM_SIMTEC if PM
16142         help
16143           Say Y here if you are using the Simtec IM2440D20 module, also
16144 @@ -74,5 +83,30 @@ config MACH_AT2440EVB
16145         help
16146           Say Y here if you are using the AT2440EVB development board
16147
16148 +config MACH_NEO1973_GTA02
16149 +       bool "FIC Neo1973 GSM Phone (GTA02 Hardware)"
16150 +       select CPU_S3C2442
16151 +       select MFD_PCF50633
16152 +       select INPUT_PCF50633_PMU
16153 +       select PCF50633_ADC
16154 +       select PCF50633_GPIO
16155 +       select RTC_DRV_PCF50633
16156 +       select REGULATOR_PCF50633
16157 +       select CHARGER_PCF50633
16158 +       select POWER_SUPPLY
16159 +       select GTA02_HDQ
16160 +       select MACH_NEO1973
16161 +       help
16162 +          Say Y here if you are using the FIC Neo1973 GSM Phone
16163 +
16164 +config NEO1973_GTA02_2440
16165 +       bool "Old FIC Neo1973 GTA02 hardware using S3C2440 CPU"
16166 +       depends on MACH_NEO1973_GTA02
16167 +       select CPU_S3C2440
16168 +       help
16169 +          Say Y here if you are using an early hardware revision
16170 +          of the FIC/Openmoko Neo1973 GTA02 GSM Phone.
16171 +
16172  endmenu
16173
16174 +#source "arch/arm/mach-s3c2440/camera/Kconfig"
16175 --- a/arch/arm/mach-s3c2440/mach-anubis.c
16176 +++ b/arch/arm/mach-s3c2440/mach-anubis.c
16177 @@ -39,7 +39,8 @@
16178  #include <mach/regs-gpio.h>
16179  #include <mach/regs-mem.h>
16180  #include <mach/regs-lcd.h>
16181 -#include <asm/plat-s3c/nand.h>
16182 +#include <plat/nand.h>
16183 +#include <plat/iic.h>
16184
16185  #include <linux/mtd/mtd.h>
16186  #include <linux/mtd/nand.h>
16187 @@ -404,7 +405,7 @@ static struct platform_device *anubis_de
16188         &s3c_device_usb,
16189         &s3c_device_wdt,
16190         &s3c_device_adc,
16191 -       &s3c_device_i2c,
16192 +       &s3c_device_i2c0,
16193         &s3c_device_rtc,
16194         &s3c_device_nand,
16195         &anubis_device_ide0,
16196 @@ -468,6 +469,7 @@ static void __init anubis_map_io(void)
16197
16198  static void __init anubis_init(void)
16199  {
16200 +       s3c_i2c0_set_platdata(NULL);
16201         platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
16202
16203         i2c_register_board_info(0, anubis_i2c_devs,
16204 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c
16205 +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
16206 @@ -35,7 +35,8 @@
16207  #include <mach/regs-gpio.h>
16208  #include <mach/regs-mem.h>
16209  #include <mach/regs-lcd.h>
16210 -#include <asm/plat-s3c/nand.h>
16211 +#include <plat/nand.h>
16212 +#include <plat/iic.h>
16213
16214  #include <linux/mtd/mtd.h>
16215  #include <linux/mtd/nand.h>
16216 @@ -166,7 +167,7 @@ static struct platform_device *at2440evb
16217         &s3c_device_usb,
16218         &s3c_device_wdt,
16219         &s3c_device_adc,
16220 -       &s3c_device_i2c,
16221 +       &s3c_device_i2c0,
16222         &s3c_device_rtc,
16223         &s3c_device_nand,
16224         &at2440evb_device_eth,
16225 @@ -183,6 +184,7 @@ static void __init at2440evb_map_io(void
16226
16227  static void __init at2440evb_init(void)
16228  {
16229 +       s3c_i2c0_set_platdata(NULL);
16230         platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
16231  }
16232
16233 --- /dev/null
16234 +++ b/arch/arm/mach-s3c2440/mach-gta02.c
16235 @@ -0,0 +1,1778 @@
16236 +/*
16237 + * linux/arch/arm/mach-s3c2440/mach-gta02.c
16238 + *
16239 + * S3C2440 Machine Support for the FIC GTA02 (Neo1973)
16240 + *
16241 + * Copyright (C) 2006-2007 by Openmoko, Inc.
16242 + * Author: Harald Welte <laforge@openmoko.org>
16243 + * All rights reserved.
16244 + *
16245 + * This program is free software; you can redistribute it and/or
16246 + * modify it under the terms of the GNU General Public License as
16247 + * published by the Free Software Foundation; either version 2 of
16248 + * the License, or (at your option) any later version.
16249 + *
16250 + * This program is distributed in the hope that it will be useful,
16251 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
16252 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16253 + * GNU General Public License for more details.
16254 + *
16255 + * You should have received a copy of the GNU General Public License
16256 + * along with this program; if not, write to the Free Software
16257 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
16258 + * MA 02111-1307 USA
16259 + *
16260 + */
16261 +
16262 +#include <linux/kernel.h>
16263 +#include <linux/types.h>
16264 +#include <linux/interrupt.h>
16265 +#include <linux/list.h>
16266 +#include <linux/delay.h>
16267 +#include <linux/timer.h>
16268 +#include <linux/init.h>
16269 +#include <linux/workqueue.h>
16270 +#include <linux/platform_device.h>
16271 +#include <linux/serial_core.h>
16272 +#include <linux/spi/spi.h>
16273 +#include <linux/spi/glamo.h>
16274 +#include <linux/spi/spi_bitbang.h>
16275 +#include <linux/mmc/host.h>
16276 +
16277 +#include <linux/mtd/mtd.h>
16278 +#include <linux/mtd/nand.h>
16279 +#include <linux/mtd/nand_ecc.h>
16280 +#include <linux/mtd/partitions.h>
16281 +#include <linux/mtd/physmap.h>
16282 +
16283 +#include <linux/i2c.h>
16284 +#include <linux/backlight.h>
16285 +#include <linux/regulator/machine.h>
16286 +
16287 +#include <linux/mfd/pcf50633/core.h>
16288 +#include <linux/mfd/pcf50633/mbc.h>
16289 +#include <linux/mfd/pcf50633/adc.h>
16290 +#include <linux/mfd/pcf50633/gpio.h>
16291 +#include <linux/mfd/pcf50633/led.h>
16292 +
16293 +#include <linux/lis302dl.h>
16294 +
16295 +#include <asm/mach/arch.h>
16296 +#include <asm/mach/map.h>
16297 +#include <asm/mach/irq.h>
16298 +
16299 +#include <mach/hardware.h>
16300 +#include <mach/io.h>
16301 +#include <asm/irq.h>
16302 +#include <asm/mach-types.h>
16303 +
16304 +#include <mach/regs-irq.h>
16305 +#include <mach/regs-gpio.h>
16306 +#include <mach/regs-gpioj.h>
16307 +#include <mach/fb.h>
16308 +#include <mach/mci.h>
16309 +#include <mach/ts.h>
16310 +#include <mach/spi.h>
16311 +#include <mach/spi-gpio.h>
16312 +#include <mach/usb-control.h>
16313 +#include <mach/regs-mem.h>
16314 +
16315 +#include <mach/gta02.h>
16316 +
16317 +#include <plat/regs-serial.h>
16318 +#include <plat/nand.h>
16319 +#include <plat/devs.h>
16320 +#include <plat/cpu.h>
16321 +#include <plat/pm.h>
16322 +#include <plat/udc.h>
16323 +#include <plat/iic.h>
16324 +#include <asm/plat-s3c24xx/neo1973.h>
16325 +#include <mach/neo1973-pm-gsm.h>
16326 +#include <mach/gta02-pm-wlan.h>
16327 +
16328 +#include <linux/jbt6k74.h>
16329 +
16330 +#include <linux/glamofb.h>
16331 +
16332 +#include <mach/fiq_ipc_gta02.h>
16333 +#include "fiq_c_isr.h"
16334 +#include <linux/gta02_hdq.h>
16335 +#include <linux/bq27000_battery.h>
16336 +
16337 +#include <linux/i2c.h>
16338 +
16339 +#include "../plat-s3c24xx/neo1973_pm_gps.h"
16340 +
16341 +#include <linux/ts_filter_linear.h>
16342 +#include <linux/ts_filter_mean.h>
16343 +#include <linux/ts_filter_median.h>
16344 +#include <linux/ts_filter_group.h>
16345 +
16346 +/* arbitrates which sensor IRQ owns the shared SPI bus */
16347 +static spinlock_t motion_irq_lock;
16348 +
16349 +/* define FIQ IPC struct */
16350 +/*
16351 + * contains stuff FIQ ISR modifies and normal kernel code can see and use
16352 + * this is defined in <arch/arm/mach-s3c2410/include/mach/fiq_ipc_gta02.h>, you should customize
16353 + * the definition in there and include the same definition in your kernel
16354 + * module that wants to interoperate with your FIQ code.
16355 + */
16356 +struct fiq_ipc fiq_ipc;
16357 +EXPORT_SYMBOL(fiq_ipc);
16358 +
16359 +#define DIVISOR_FROM_US(x) ((x) << 3)
16360 +
16361 +#define FIQ_DIVISOR_VIBRATOR DIVISOR_FROM_US(100)
16362 +
16363 +#ifdef CONFIG_GTA02_HDQ
16364 +/* HDQ specific */
16365 +#define HDQ_SAMPLE_PERIOD_US 20
16366 +/* private HDQ FSM state -- all other info interesting for caller in fiq_ipc */
16367 +static enum hdq_bitbang_states hdq_state;
16368 +static u8 hdq_ctr;
16369 +static u8 hdq_ctr2;
16370 +static u8 hdq_bit;
16371 +static u8 hdq_shifter;
16372 +static u8 hdq_tx_data_done;
16373 +
16374 +#define FIQ_DIVISOR_HDQ DIVISOR_FROM_US(HDQ_SAMPLE_PERIOD_US)
16375 +#endif
16376 +/* define FIQ ISR */
16377 +
16378 +FIQ_HANDLER_START()
16379 +/* define your locals here -- no initializers though */
16380 +       u16 divisor;
16381 +FIQ_HANDLER_ENTRY(64, 64)
16382 +/* Your ISR here :-) */
16383 +       divisor = 0xffff;
16384 +
16385 +       /* Vibrator servicing */
16386 +
16387 +       if (fiq_ipc.vib_pwm_latched || fiq_ipc.vib_pwm) { /* not idle */
16388 +               if (((u8)_fiq_count_fiqs) == fiq_ipc.vib_pwm_latched)
16389 +                       neo1973_gpb_setpin(fiq_ipc.vib_gpio_pin, 0);
16390 +               if (((u8)_fiq_count_fiqs) == 0) {
16391 +                       fiq_ipc.vib_pwm_latched = fiq_ipc.vib_pwm;
16392 +                       if (fiq_ipc.vib_pwm_latched)
16393 +                               neo1973_gpb_setpin(fiq_ipc.vib_gpio_pin, 1);
16394 +               }
16395 +               divisor = FIQ_DIVISOR_VIBRATOR;
16396 +       }
16397 +
16398 +#ifdef CONFIG_GTA02_HDQ
16399 +       /* HDQ servicing */
16400 +
16401 +       switch (hdq_state) {
16402 +       case HDQB_IDLE:
16403 +               if (fiq_ipc.hdq_request_ctr == fiq_ipc.hdq_transaction_ctr)
16404 +                       break;
16405 +               hdq_ctr = 210 / HDQ_SAMPLE_PERIOD_US;
16406 +               s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0);
16407 +               s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
16408 +               hdq_tx_data_done = 0;
16409 +               hdq_state = HDQB_TX_BREAK;
16410 +               break;
16411 +
16412 +       case HDQB_TX_BREAK: /* issue low for > 190us */
16413 +               if (--hdq_ctr == 0) {
16414 +                       hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
16415 +                       hdq_state = HDQB_TX_BREAK_RECOVERY;
16416 +                       s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
16417 +               }
16418 +               break;
16419 +
16420 +       case HDQB_TX_BREAK_RECOVERY: /* issue low for > 40us */
16421 +               if (--hdq_ctr)
16422 +                       break;
16423 +               hdq_shifter = fiq_ipc.hdq_ads;
16424 +               hdq_bit = 8; /* 8 bits of ads / rw */
16425 +               hdq_tx_data_done = 0; /* doing ads */
16426 +               /* fallthru on last one */
16427 +       case HDQB_ADS_CALC:
16428 +               if (hdq_shifter & 1)
16429 +                       hdq_ctr = 50 / HDQ_SAMPLE_PERIOD_US;
16430 +               else
16431 +                       hdq_ctr = 120 / HDQ_SAMPLE_PERIOD_US;
16432 +               /* carefully precompute the other phase length */
16433 +               hdq_ctr2 = (210 - (hdq_ctr * HDQ_SAMPLE_PERIOD_US)) /
16434 +                               HDQ_SAMPLE_PERIOD_US;
16435 +               hdq_state = HDQB_ADS_LOW;
16436 +               hdq_shifter >>= 1;
16437 +               hdq_bit--;
16438 +               s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0);
16439 +               break;
16440 +
16441 +       case HDQB_ADS_LOW:
16442 +               if (--hdq_ctr)
16443 +                       break;
16444 +               s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
16445 +               hdq_state = HDQB_ADS_HIGH;
16446 +               break;
16447 +
16448 +       case HDQB_ADS_HIGH:
16449 +               if (--hdq_ctr2 > 1) /* account for HDQB_ADS_CALC */
16450 +                       break;
16451 +               if (hdq_bit) { /* more bits to do */
16452 +                       hdq_state = HDQB_ADS_CALC;
16453 +                       break;
16454 +               }
16455 +               /* no more bits, wait it out until hdq_ctr2 exhausted */
16456 +               if (hdq_ctr2)
16457 +                       break;
16458 +               /* ok no more bits and very last state */
16459 +               hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
16460 +               /* FIXME 0 = read */
16461 +               if (fiq_ipc.hdq_ads & 0x80) { /* write the byte out */
16462 +                        /* set delay before payload */
16463 +                       hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US;
16464 +                       /* already high, no need to write */
16465 +                       hdq_state = HDQB_WAIT_TX;
16466 +                       break;
16467 +               }
16468 +               /* read the next byte */
16469 +               hdq_bit = 8; /* 8 bits of data */
16470 +               hdq_ctr = 3000 / HDQ_SAMPLE_PERIOD_US;
16471 +               hdq_state = HDQB_WAIT_RX;
16472 +               s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_INPUT);
16473 +               break;
16474 +
16475 +       case HDQB_WAIT_TX: /* issue low for > 40us */
16476 +               if (--hdq_ctr)
16477 +                       break;
16478 +               if (!hdq_tx_data_done) { /* was that the data sent? */
16479 +                       hdq_tx_data_done++;
16480 +                       hdq_shifter = fiq_ipc.hdq_tx_data;
16481 +                       hdq_bit = 8; /* 8 bits of data */
16482 +                       hdq_state = HDQB_ADS_CALC; /* start sending */
16483 +                       break;
16484 +               }
16485 +               fiq_ipc.hdq_error = 0;
16486 +               fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
16487 +               hdq_state = HDQB_IDLE; /* all tx is done */
16488 +               /* idle in input mode, it's pulled up by 10K */
16489 +               s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_INPUT);
16490 +               break;
16491 +
16492 +       case HDQB_WAIT_RX: /* wait for battery to talk to us */
16493 +               if (s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin) == 0) {
16494 +                       /* it talks to us! */
16495 +                       hdq_ctr2 = 1;
16496 +                       hdq_bit = 8; /* 8 bits of data */
16497 +                       /* timeout */
16498 +                       hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US;
16499 +                       hdq_state = HDQB_DATA_RX_LOW;
16500 +                       break;
16501 +               }
16502 +               if (--hdq_ctr == 0) { /* timed out, error */
16503 +                       fiq_ipc.hdq_error = 1;
16504 +                       fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
16505 +                       hdq_state = HDQB_IDLE; /* abort */
16506 +               }
16507 +               break;
16508 +
16509 +       /*
16510 +        * HDQ basically works by measuring the low time of the bit cell
16511 +        * 32-50us --> '1', 80 - 145us --> '0'
16512 +        */
16513 +
16514 +       case HDQB_DATA_RX_LOW:
16515 +               if (s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin)) {
16516 +                       fiq_ipc.hdq_rx_data >>= 1;
16517 +                       if (hdq_ctr2 <= (65 / HDQ_SAMPLE_PERIOD_US))
16518 +                               fiq_ipc.hdq_rx_data |= 0x80;
16519 +
16520 +                       if (--hdq_bit == 0) {
16521 +                               fiq_ipc.hdq_error = 0;
16522 +                               fiq_ipc.hdq_transaction_ctr =
16523 +                                                       fiq_ipc.hdq_request_ctr;
16524 +
16525 +                               hdq_state = HDQB_IDLE;
16526 +                       } else
16527 +                               hdq_state = HDQB_DATA_RX_HIGH;
16528 +                       /* timeout */
16529 +                       hdq_ctr = 1000 / HDQ_SAMPLE_PERIOD_US;
16530 +                       hdq_ctr2 = 1;
16531 +                       break;
16532 +               }
16533 +               hdq_ctr2++;
16534 +               if (--hdq_ctr)
16535 +                       break;
16536 +                /* timed out, error */
16537 +               fiq_ipc.hdq_error = 2;
16538 +               fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
16539 +               hdq_state = HDQB_IDLE; /* abort */
16540 +               break;
16541 +
16542 +       case HDQB_DATA_RX_HIGH:
16543 +               if (!s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin)) {
16544 +                       /* it talks to us! */
16545 +                       hdq_ctr2 = 1;
16546 +                       /* timeout */
16547 +                       hdq_ctr = 400 / HDQ_SAMPLE_PERIOD_US;
16548 +                       hdq_state = HDQB_DATA_RX_LOW;
16549 +                       break;
16550 +               }
16551 +               if (--hdq_ctr)
16552 +                       break;
16553 +               /* timed out, error */
16554 +               fiq_ipc.hdq_error = 3;
16555 +               fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
16556 +
16557 +               /* we're in input mode already */
16558 +               hdq_state = HDQB_IDLE; /* abort */
16559 +               break;
16560 +       }
16561 +
16562 +       if (hdq_state != HDQB_IDLE) /* ie, not idle */
16563 +               if (divisor > FIQ_DIVISOR_HDQ)
16564 +                       divisor = FIQ_DIVISOR_HDQ; /* keep us going */
16565 +#endif
16566 +
16567 +       /* disable further timer interrupts if nobody has any work
16568 +        * or adjust rate according to who still has work
16569 +        *
16570 +        * CAUTION: it means forground code must disable FIQ around
16571 +        * its own non-atomic S3C2410_INTMSK changes... not common
16572 +        * thankfully and taken care of by the fiq-basis patch
16573 +        */
16574 +       if (divisor == 0xffff) /* mask the fiq irq source */
16575 +               __raw_writel(__raw_readl(S3C2410_INTMSK) | _fiq_ack_mask,
16576 +                            S3C2410_INTMSK);
16577 +       else /* still working, maybe at a different rate */
16578 +               __raw_writel(divisor, S3C2410_TCNTB(_fiq_timer_index));
16579 +       _fiq_timer_divisor = divisor;
16580 +
16581 +FIQ_HANDLER_END()
16582 +
16583 +
16584 +/*
16585 + * this gets called every 1ms when we paniced.
16586 + */
16587 +
16588 +static long gta02_panic_blink(long count)
16589 +{
16590 +       long delay = 0;
16591 +       static long last_blink;
16592 +       static char led;
16593 +
16594 +       if (count - last_blink < 100) /* 200ms period, fast blink */
16595 +               return 0;
16596 +
16597 +       led ^= 1;
16598 +       s3c2410_gpio_cfgpin(GTA02_GPIO_AUX_LED, S3C2410_GPIO_OUTPUT);
16599 +       neo1973_gpb_setpin(GTA02_GPIO_AUX_LED, led);
16600 +
16601 +       last_blink = count;
16602 +       return delay;
16603 +}
16604 +
16605 +
16606 +/**
16607 + * returns PCB revision information in b9,b8 and b2,b1,b0
16608 + * Pre-GTA02 A6 returns 0x000
16609 + *     GTA02 A6 returns 0x101
16610 + *     ...
16611 + */
16612 +
16613 +int gta02_get_pcb_revision(void)
16614 +{
16615 +       int n;
16616 +       int u = 0;
16617 +       static unsigned long pinlist[] = {
16618 +               GTA02_PCB_ID1_0,
16619 +               GTA02_PCB_ID1_1,
16620 +               GTA02_PCB_ID1_2,
16621 +               GTA02_PCB_ID2_0,
16622 +               GTA02_PCB_ID2_1,
16623 +       };
16624 +       static int pin_offset[] = {
16625 +               0, 1, 2, 8, 9
16626 +       };
16627 +
16628 +       for (n = 0 ; n < ARRAY_SIZE(pinlist); n++) {
16629 +               /*
16630 +                * set the PCB version GPIO to be pulled-down input
16631 +                * force low briefly first
16632 +                */
16633 +               s3c2410_gpio_cfgpin(pinlist[n], S3C2410_GPIO_OUTPUT);
16634 +               s3c2410_gpio_setpin(pinlist[n], 0);
16635 +               /* misnomer: it is a pullDOWN in 2442 */
16636 +               s3c2410_gpio_pullup(pinlist[n], 1);
16637 +               s3c2410_gpio_cfgpin(pinlist[n], S3C2410_GPIO_INPUT);
16638 +
16639 +               udelay(10);
16640 +
16641 +               if (s3c2410_gpio_getpin(pinlist[n]))
16642 +                       u |= 1 << pin_offset[n];
16643 +
16644 +               /*
16645 +               * when not being interrogated, all of the revision GPIO
16646 +               * are set to output HIGH without pulldown so no current flows
16647 +               * if they are NC or pulled up.
16648 +               */
16649 +               s3c2410_gpio_setpin(pinlist[n], 1);
16650 +               s3c2410_gpio_cfgpin(pinlist[n], S3C2410_GPIO_OUTPUT);
16651 +               /* misnomer: it is a pullDOWN in 2442 */
16652 +               s3c2410_gpio_pullup(pinlist[n], 0);
16653 +       }
16654 +
16655 +       return u;
16656 +}
16657 +
16658 +struct platform_device gta02_version_device = {
16659 +       .name           = "neo1973-version",
16660 +       .num_resources  = 0,
16661 +};
16662 +
16663 +struct platform_device gta02_resume_reason_device = {
16664 +       .name           = "neo1973-resume",
16665 +       .num_resources  = 0,
16666 +};
16667 +
16668 +struct platform_device gta02_memconfig_device = {
16669 +       .name           = "neo1973-memconfig",
16670 +       .num_resources  = 0,
16671 +};
16672 +
16673 +static struct map_desc gta02_iodesc[] __initdata = {
16674 +       {
16675 +               .virtual        = 0xe0000000,
16676 +               .pfn            = __phys_to_pfn(S3C2410_CS3+0x01000000),
16677 +               .length         = SZ_1M,
16678 +               .type           = MT_DEVICE
16679 +       },
16680 +};
16681 +
16682 +#define UCON S3C2410_UCON_DEFAULT
16683 +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
16684 +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
16685 +
16686 +static struct s3c2410_uartcfg gta02_uartcfgs[] = {
16687 +       [0] = {
16688 +               .hwport      = 0,
16689 +               .flags       = 0,
16690 +               .ucon        = UCON,
16691 +               .ulcon       = ULCON,
16692 +               .ufcon       = UFCON,
16693 +       },
16694 +       [1] = {
16695 +               .hwport      = 1,
16696 +               .flags       = 0,
16697 +               .ucon        = UCON,
16698 +               .ulcon       = ULCON,
16699 +               .ufcon       = UFCON,
16700 +       },
16701 +       [2] = {
16702 +               .hwport      = 2,
16703 +               .flags       = 0,
16704 +               .ucon        = UCON,
16705 +               .ulcon       = ULCON,
16706 +               .ufcon       = UFCON,
16707 +       },
16708 +
16709 +};
16710 +
16711 +/* BQ27000 Battery */
16712 +
16713 +static int gta02_get_charger_online_status(void)
16714 +{
16715 +       struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
16716 +
16717 +       return pcf->mbc.usb_online;
16718 +}
16719 +
16720 +static int gta02_get_charger_active_status(void)
16721 +{
16722 +       struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
16723 +
16724 +       return pcf->mbc.usb_active;
16725 +}
16726 +
16727 +
16728 +struct bq27000_platform_data bq27000_pdata = {
16729 +       .name = "battery",
16730 +       .rsense_mohms = 20,
16731 +       .hdq_read = gta02hdq_read,
16732 +       .hdq_write = gta02hdq_write,
16733 +       .hdq_initialized = gta02hdq_initialized,
16734 +       .get_charger_online_status = gta02_get_charger_online_status,
16735 +       .get_charger_active_status = gta02_get_charger_active_status
16736 +};
16737 +
16738 +struct platform_device bq27000_battery_device = {
16739 +       .name           = "bq27000-battery",
16740 +       .dev = {
16741 +               .platform_data = &bq27000_pdata,
16742 +       },
16743 +};
16744 +
16745 +#define ADC_NOM_CHG_DETECT_1A 6
16746 +#define ADC_NOM_CHG_DETECT_USB 43
16747 +
16748 +static void
16749 +gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res)
16750 +{
16751 +       int  ma;
16752 +
16753 +       /* Interpret charger type */
16754 +       if (res < ((ADC_NOM_CHG_DETECT_USB + ADC_NOM_CHG_DETECT_1A) / 2)) {
16755 +
16756 +               /* Stop GPO driving out now that we have a IA charger */
16757 +               pcf50633_gpio_set(pcf, PCF50633_GPO, 0);
16758 +
16759 +               ma = 1000;
16760 +       } else
16761 +               ma = 100;
16762 +
16763 +       pcf50633_mbc_usb_curlim_set(pcf, ma);
16764 +}
16765 +
16766 +static struct delayed_work gta02_charger_work;
16767 +static int gta02_usb_vbus_draw;
16768 +
16769 +static void gta02_charger_worker(struct work_struct *work)
16770 +{
16771 +       struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
16772 +
16773 +       if (gta02_usb_vbus_draw) {
16774 +               pcf50633_mbc_usb_curlim_set(pcf, gta02_usb_vbus_draw);
16775 +               return;
16776 +       } else {
16777 +               pcf50633_adc_async_read(pcf,
16778 +                       PCF50633_ADCC1_MUX_ADCIN1,
16779 +                       PCF50633_ADCC1_AVERAGE_16,
16780 +                       gta02_configure_pmu_for_charger, NULL);
16781 +               return;
16782 +       }
16783 +}
16784 +
16785 +#define GTA02_CHARGER_CONFIGURE_TIMEOUT ((3000 * HZ) / 1000)
16786 +static void gta02_pmu_event_callback(struct pcf50633 *pcf, int irq)
16787 +{
16788 +       if (irq == PCF50633_IRQ_USBINS) {
16789 +               schedule_delayed_work(&gta02_charger_work,
16790 +                               GTA02_CHARGER_CONFIGURE_TIMEOUT);
16791 +               return;
16792 +       } else if (irq == PCF50633_IRQ_USBREM) {
16793 +               cancel_delayed_work_sync(&gta02_charger_work);
16794 +               gta02_usb_vbus_draw = 0;
16795 +       }
16796 +}
16797 +
16798 +static struct platform_device gta01_pm_gps_dev = {
16799 +       .name           = "neo1973-pm-gps",
16800 +};
16801 +
16802 +static struct platform_device gta01_pm_bt_dev = {
16803 +       .name           = "neo1973-pm-bt",
16804 +};
16805 +
16806 +static struct platform_device gta02_pm_gsm_dev = {
16807 +       .name           = "neo1973-pm-gsm",
16808 +};
16809 +
16810 +/* this is called when pc50633 is probed, unfortunately quite late in the
16811 + * day since it is an I2C bus device.  Here we can belatedly define some
16812 + * platform devices with the advantage that we can mark the pcf50633 as the
16813 + * parent.  This makes them get suspended and resumed with their parent
16814 + * the pcf50633 still around.
16815 + */
16816 +
16817 +static struct platform_device gta02_glamo_dev;
16818 +static void mangle_glamo_res_by_system_rev(void);
16819 +
16820 +static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf);
16821 +static void gta02_pmu_regulator_registered(struct pcf50633 *pcf, int id);
16822 +
16823 +static struct platform_device gta02_pm_wlan_dev = {
16824 +       .name           = "gta02-pm-wlan",
16825 +};
16826 +
16827 +static struct regulator_consumer_supply ldo4_consumers[] = {
16828 +       {
16829 +               .dev = &gta01_pm_bt_dev.dev,
16830 +               .supply = "BT_3V2",
16831 +       },
16832 +};
16833 +
16834 +static struct regulator_consumer_supply ldo5_consumers[] = {
16835 +       {
16836 +               .dev = &gta01_pm_gps_dev.dev,
16837 +               .supply = "RF_3V",
16838 +       },
16839 +};
16840 +
16841 +/*
16842 + * We need this dummy thing to fill the regulator consumers
16843 + */
16844 +static struct platform_device gta02_mmc_dev = {
16845 +       /* details filled in by glamo core */
16846 +};
16847 +
16848 +static struct regulator_consumer_supply hcldo_consumers[] = {
16849 +       {
16850 +               .dev = &gta02_mmc_dev.dev,
16851 +               .supply = "SD_3V3",
16852 +       },
16853 +};
16854 +
16855 +static char *gta02_batteries[] = {
16856 +       "battery",
16857 +};
16858 +
16859 +struct pcf50633_platform_data gta02_pcf_pdata = {
16860 +       .resumers = {
16861 +               [0] =   PCF50633_INT1_USBINS |
16862 +                       PCF50633_INT1_USBREM |
16863 +                       PCF50633_INT1_ALARM,
16864 +               [1] =   PCF50633_INT2_ONKEYF,
16865 +               [2] =   PCF50633_INT3_ONKEY1S,
16866 +               [3] =   PCF50633_INT4_LOWSYS |
16867 +                       PCF50633_INT4_LOWBAT |
16868 +                       PCF50633_INT4_HIGHTMP,
16869 +       },
16870 +
16871 +       .batteries = gta02_batteries,
16872 +       .num_batteries = ARRAY_SIZE(gta02_batteries),
16873 +
16874 +       .reg_init_data = {
16875 +               [PCF50633_REGULATOR_AUTO] = {
16876 +                       .constraints = {
16877 +                               .min_uV = 3300000,
16878 +                               .max_uV = 3300000,
16879 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16880 +                               .boot_on = 1,
16881 +                               .apply_uV = 1,
16882 +                               .state_mem = {
16883 +                                       .enabled = 1,
16884 +                               },
16885 +                       },
16886 +                       .num_consumer_supplies = 0,
16887 +               },
16888 +               [PCF50633_REGULATOR_DOWN1] = {
16889 +                       .constraints = {
16890 +                               .min_uV = 1300000,
16891 +                               .max_uV = 1600000,
16892 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16893 +                               .boot_on = 1,
16894 +                               .apply_uV = 1,
16895 +                       },
16896 +                       .num_consumer_supplies = 0,
16897 +               },
16898 +               [PCF50633_REGULATOR_DOWN2] = {
16899 +                       .constraints = {
16900 +                               .min_uV = 1800000,
16901 +                               .max_uV = 1800000,
16902 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16903 +                               .apply_uV = 1,
16904 +                               .boot_on = 1,
16905 +                               .state_mem = {
16906 +                                       .enabled = 1,
16907 +                               },
16908 +                       },
16909 +                       .num_consumer_supplies = 0,
16910 +               },
16911 +               [PCF50633_REGULATOR_HCLDO] = {
16912 +                       .constraints = {
16913 +                               .min_uV = 2000000,
16914 +                               .max_uV = 3300000,
16915 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16916 +                               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
16917 +                               .boot_on = 1,
16918 +                       },
16919 +                       .num_consumer_supplies = 1,
16920 +                       .consumer_supplies = hcldo_consumers,
16921 +               },
16922 +               [PCF50633_REGULATOR_LDO1] = {
16923 +                       .constraints = {
16924 +                               .min_uV = 1300000,
16925 +                               .max_uV = 1300000,
16926 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16927 +                               .apply_uV = 1,
16928 +                       },
16929 +                       .num_consumer_supplies = 0,
16930 +               },
16931 +               [PCF50633_REGULATOR_LDO2] = {
16932 +                       .constraints = {
16933 +                               .min_uV = 3300000,
16934 +                               .max_uV = 3300000,
16935 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16936 +                               .apply_uV = 1,
16937 +                       },
16938 +                       .num_consumer_supplies = 0,
16939 +               },
16940 +               [PCF50633_REGULATOR_LDO3] = {
16941 +                       .constraints = {
16942 +                               .min_uV = 3000000,
16943 +                               .max_uV = 3000000,
16944 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16945 +                               .apply_uV = 1,
16946 +                       },
16947 +                       .num_consumer_supplies = 0,
16948 +               },
16949 +               [PCF50633_REGULATOR_LDO4] = {
16950 +                       .constraints = {
16951 +                               .min_uV = 3200000,
16952 +                               .max_uV = 3200000,
16953 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16954 +                               .apply_uV = 1,
16955 +                       },
16956 +                       .num_consumer_supplies = 1,
16957 +                       .consumer_supplies = ldo4_consumers,
16958 +               },
16959 +               [PCF50633_REGULATOR_LDO5] = {
16960 +                       .constraints = {
16961 +                               .min_uV = 1500000,
16962 +                               .max_uV = 1500000,
16963 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16964 +                               .apply_uV = 1,
16965 +                       },
16966 +                       .num_consumer_supplies = 1,
16967 +                       .consumer_supplies = ldo5_consumers,
16968 +               },
16969 +               [PCF50633_REGULATOR_LDO6] = {
16970 +                       .constraints = {
16971 +                               .min_uV = 0,
16972 +                               .max_uV = 3300000,
16973 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16974 +                       },
16975 +                       .num_consumer_supplies = 0,
16976 +               },
16977 +               [PCF50633_REGULATOR_MEMLDO] = {
16978 +                       .constraints = {
16979 +                               .min_uV = 1800000,
16980 +                               .max_uV = 1800000,
16981 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
16982 +                               .state_mem = {
16983 +                                       .enabled = 1,
16984 +                               },
16985 +                       },
16986 +                       .num_consumer_supplies = 0,
16987 +               },
16988 +
16989 +       },
16990 +       .probe_done = gta02_pmu_attach_child_devices,
16991 +       .regulator_registered = gta02_pmu_regulator_registered,
16992 +       .mbc_event_callback = gta02_pmu_event_callback,
16993 +};
16994 +
16995 +static void mangle_pmu_pdata_by_system_rev(void)
16996 +{
16997 +       struct regulator_init_data *reg_init_data;
16998 +
16999 +       reg_init_data = gta02_pcf_pdata.reg_init_data;
17000 +
17001 +       switch (system_rev) {
17002 +       case GTA02v1_SYSTEM_REV:
17003 +               /* FIXME: this is only in v1 due to wrong PMU variant */
17004 +               reg_init_data[PCF50633_REGULATOR_DOWN2]
17005 +                                       .constraints.state_mem.enabled = 1;
17006 +               break;
17007 +       case GTA02v2_SYSTEM_REV:
17008 +       case GTA02v3_SYSTEM_REV:
17009 +       case GTA02v4_SYSTEM_REV:
17010 +       case GTA02v5_SYSTEM_REV:
17011 +       case GTA02v6_SYSTEM_REV:
17012 +               reg_init_data[PCF50633_REGULATOR_LDO1]
17013 +                                       .constraints.min_uV = 3300000;
17014 +               reg_init_data[PCF50633_REGULATOR_LDO1]
17015 +                                       .constraints.min_uV = 3300000;
17016 +               reg_init_data[PCF50633_REGULATOR_LDO1]
17017 +                                       .constraints.state_mem.enabled = 0;
17018 +
17019 +               reg_init_data[PCF50633_REGULATOR_LDO5]
17020 +                                       .constraints.min_uV = 3000000;
17021 +               reg_init_data[PCF50633_REGULATOR_LDO5]
17022 +                                       .constraints.max_uV = 3000000;
17023 +
17024 +               reg_init_data[PCF50633_REGULATOR_LDO6]
17025 +                                       .constraints.min_uV = 3000000;
17026 +               reg_init_data[PCF50633_REGULATOR_LDO6]
17027 +                                       .constraints.max_uV = 3000000;
17028 +               reg_init_data[PCF50633_REGULATOR_LDO6]
17029 +                                       .constraints.apply_uV = 1;
17030 +               break;
17031 +       default:
17032 +               break;
17033 +       }
17034 +}
17035 +
17036 +#ifdef CONFIG_GTA02_HDQ
17037 +/* HDQ */
17038 +
17039 +static void gta02_hdq_attach_child_devices(struct device *parent_device)
17040 +{
17041 +       switch (system_rev) {
17042 +       case GTA02v5_SYSTEM_REV:
17043 +       case GTA02v6_SYSTEM_REV:
17044 +               bq27000_battery_device.dev.parent = parent_device;
17045 +               platform_device_register(&bq27000_battery_device);
17046 +               break;
17047 +       default:
17048 +               break;
17049 +       }
17050 +}
17051 +
17052 +static struct resource gta02_hdq_resources[] = {
17053 +       [0] = {
17054 +               .start  = GTA02v5_GPIO_HDQ,
17055 +               .end    = GTA02v5_GPIO_HDQ,
17056 +       },
17057 +};
17058 +
17059 +struct gta02_hdq_platform_data gta02_hdq_platform_data = {
17060 +       .attach_child_devices = gta02_hdq_attach_child_devices
17061 +};
17062 +
17063 +struct platform_device gta02_hdq_device = {
17064 +       .name           = "gta02-hdq",
17065 +       .num_resources  = 1,
17066 +       .resource       = gta02_hdq_resources,
17067 +       .dev            = {
17068 +               .platform_data = &gta02_hdq_platform_data,
17069 +       },
17070 +};
17071 +#endif
17072 +
17073 +/* vibrator (child of FIQ) */
17074 +
17075 +static struct resource gta02_vibrator_resources[] = {
17076 +       [0] = {
17077 +               .start  = GTA02_GPIO_VIBRATOR_ON,
17078 +               .end    = GTA02_GPIO_VIBRATOR_ON,
17079 +       },
17080 +};
17081 +
17082 +static struct platform_device gta02_vibrator_dev = {
17083 +       .name           = "neo1973-vibrator",
17084 +       .num_resources  = ARRAY_SIZE(gta02_vibrator_resources),
17085 +       .resource       = gta02_vibrator_resources,
17086 +};
17087 +
17088 +/* FIQ, used PWM regs, so not child of PWM */
17089 +
17090 +static void gta02_fiq_attach_child_devices(struct device *parent_device)
17091 +{
17092 +#ifdef CONFIG_GTA02_HDQ
17093 +       switch (system_rev) {
17094 +       case GTA02v5_SYSTEM_REV:
17095 +       case GTA02v6_SYSTEM_REV:
17096 +               gta02_hdq_device.dev.parent = parent_device;
17097 +               platform_device_register(&gta02_hdq_device);
17098 +               gta02_vibrator_dev.dev.parent = parent_device;
17099 +               platform_device_register(&gta02_vibrator_dev);
17100 +               break;
17101 +       default:
17102 +               break;
17103 +       }
17104 +#endif
17105 +}
17106 +
17107 +
17108 +static struct resource sc32440_fiq_resources[] = {
17109 +       [0] = {
17110 +               .flags  = IORESOURCE_IRQ,
17111 +               .start  = IRQ_TIMER3,
17112 +               .end    = IRQ_TIMER3,
17113 +       },
17114 +};
17115 +
17116 +struct sc32440_fiq_platform_data gta02_sc32440_fiq_platform_data = {
17117 +       .attach_child_devices = gta02_fiq_attach_child_devices
17118 +};
17119 +
17120 +struct platform_device sc32440_fiq_device = {
17121 +       .name           = "sc32440_fiq",
17122 +       .num_resources  = 1,
17123 +       .resource       = sc32440_fiq_resources,
17124 +       .dev            = {
17125 +               .platform_data = &gta02_sc32440_fiq_platform_data,
17126 +       },
17127 +};
17128 +
17129 +/* NOR Flash */
17130 +
17131 +#define GTA02_FLASH_BASE       0x18000000 /* GCS3 */
17132 +#define GTA02_FLASH_SIZE       0x200000 /* 2MBytes */
17133 +
17134 +static struct physmap_flash_data gta02_nor_flash_data = {
17135 +       .width          = 2,
17136 +};
17137 +
17138 +static struct resource gta02_nor_flash_resource = {
17139 +       .start          = GTA02_FLASH_BASE,
17140 +       .end            = GTA02_FLASH_BASE + GTA02_FLASH_SIZE - 1,
17141 +       .flags          = IORESOURCE_MEM,
17142 +};
17143 +
17144 +static struct platform_device gta02_nor_flash = {
17145 +       .name           = "physmap-flash",
17146 +       .id             = 0,
17147 +       .dev            = {
17148 +                               .platform_data  = &gta02_nor_flash_data,
17149 +                       },
17150 +       .resource       = &gta02_nor_flash_resource,
17151 +       .num_resources  = 1,
17152 +};
17153 +
17154 +
17155 +struct platform_device s3c24xx_pwm_device = {
17156 +       .name           = "s3c24xx_pwm",
17157 +       .num_resources  = 0,
17158 +};
17159 +
17160 +static struct i2c_board_info gta02_i2c_devs[] __initdata = {
17161 +       {
17162 +               I2C_BOARD_INFO("pcf50633", 0x73),
17163 +               .irq = GTA02_IRQ_PCF50633,
17164 +               .platform_data = &gta02_pcf_pdata,
17165 +       },
17166 +};
17167 +
17168 +static struct s3c2410_nand_set gta02_nand_sets[] = {
17169 +       [0] = {
17170 +               .name           = "neo1973-nand",
17171 +               .nr_chips       = 1,
17172 +               .flags          = S3C2410_NAND_BBT,
17173 +       },
17174 +};
17175 +
17176 +/* choose a set of timings derived from S3C@2442B MCP54
17177 + * data sheet (K5D2G13ACM-D075 MCP Memory)
17178 + */
17179 +
17180 +static struct s3c2410_platform_nand gta02_nand_info = {
17181 +       .tacls          = 0,
17182 +       .twrph0         = 25,
17183 +       .twrph1         = 15,
17184 +       .nr_sets        = ARRAY_SIZE(gta02_nand_sets),
17185 +       .sets           = gta02_nand_sets,
17186 +       .software_ecc   = 1,
17187 +};
17188 +
17189 +
17190 +static void gta02_s3c_mmc_set_power(unsigned char power_mode,
17191 +    unsigned short vdd)
17192 +{
17193 +       gta02_wlan_power(
17194 +           power_mode == MMC_POWER_ON ||
17195 +           power_mode == MMC_POWER_UP);
17196 +}
17197 +
17198 +
17199 +static struct s3c24xx_mci_pdata gta02_s3c_mmc_cfg = {
17200 +       .set_power      = gta02_s3c_mmc_set_power,
17201 +};
17202 +
17203 +static void gta02_udc_command(enum s3c2410_udc_cmd_e cmd)
17204 +{
17205 +       switch (cmd) {
17206 +       case S3C2410_UDC_P_ENABLE:
17207 +               printk(KERN_DEBUG "%s S3C2410_UDC_P_ENABLE\n", __func__);
17208 +               neo1973_gpb_setpin(GTA02_GPIO_USB_PULLUP, 1);
17209 +               break;
17210 +       case S3C2410_UDC_P_DISABLE:
17211 +               printk(KERN_DEBUG "%s S3C2410_UDC_P_DISABLE\n", __func__);
17212 +               neo1973_gpb_setpin(GTA02_GPIO_USB_PULLUP, 0);
17213 +               break;
17214 +       case S3C2410_UDC_P_RESET:
17215 +               printk(KERN_DEBUG "%s S3C2410_UDC_P_RESET\n", __func__);
17216 +               /* FIXME! */
17217 +               break;
17218 +       default:
17219 +               break;
17220 +       }
17221 +}
17222 +
17223 +/* get PMU to set USB current limit accordingly */
17224 +
17225 +static void gta02_udc_vbus_draw(unsigned int ma)
17226 +{
17227 +        if (!gta02_pcf_pdata.pcf) {
17228 +               printk(KERN_ERR "********** NULL gta02_pcf_pdata.pcf *****\n");
17229 +               return;
17230 +       }
17231 +
17232 +       gta02_usb_vbus_draw = ma;
17233 +
17234 +       schedule_delayed_work(&gta02_charger_work,
17235 +                               GTA02_CHARGER_CONFIGURE_TIMEOUT);
17236 +}
17237 +
17238 +static struct s3c2410_udc_mach_info gta02_udc_cfg = {
17239 +       .vbus_draw      = gta02_udc_vbus_draw,
17240 +       .udc_command    = gta02_udc_command,
17241 +
17242 +};
17243 +
17244 +
17245 +/* touchscreen configuration */
17246 +
17247 +static struct ts_filter_linear_configuration gta02_ts_linear_config = {
17248 +       .constants = {1, 0, 0, 0, 1, 0, 1},     /* don't modify coords */
17249 +       .coord0 = 0,
17250 +       .coord1 = 1,
17251 +};
17252 +
17253 +static struct ts_filter_group_configuration gta02_ts_group_config = {
17254 +       .extent = 12,
17255 +       .close_enough = 10,
17256 +       .threshold = 6,         /* at least half of the points in a group */
17257 +       .attempts = 10,
17258 +};
17259 +
17260 +static struct ts_filter_median_configuration gta02_ts_median_config = {
17261 +       .extent = 20,
17262 +       .decimation_below = 3,
17263 +       .decimation_threshold = 8 * 3,
17264 +       .decimation_above = 4,
17265 +};
17266 +
17267 +static struct ts_filter_mean_configuration gta02_ts_mean_config = {
17268 +       .bits_filter_length = 2, /* 4 points */
17269 +};
17270 +
17271 +static struct s3c2410_ts_mach_info gta02_ts_cfg = {
17272 +       .delay = 10000,
17273 +       .presc = 0xff, /* slow as we can go */
17274 +       .filter_sequence = {
17275 +               [0] = &ts_filter_group_api,
17276 +               [1] = &ts_filter_median_api,
17277 +               [2] = &ts_filter_mean_api,
17278 +               [3] = &ts_filter_linear_api,
17279 +       },
17280 +       .filter_config = {
17281 +               [0] = &gta02_ts_group_config,
17282 +               [1] = &gta02_ts_median_config,
17283 +               [2] = &gta02_ts_mean_config,
17284 +               [3] = &gta02_ts_linear_config,
17285 +       },
17286 +};
17287 +
17288 +
17289 +static void gta02_bl_set_intensity(int intensity)
17290 +{
17291 +       struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
17292 +       int old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT);
17293 +       int ret;
17294 +
17295 +       intensity >>= 2;
17296 +
17297 +       if (intensity == old_intensity)
17298 +               return;
17299 +
17300 +       /* We can't do this anywhere else */
17301 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 5);
17302 +
17303 +       if (!(pcf50633_reg_read(pcf, PCF50633_REG_LEDENA) & 3))
17304 +               old_intensity = 0;
17305 +
17306 +       /*
17307 +        * The PCF50633 cannot handle LEDOUT = 0 (datasheet p60)
17308 +        * if seen, you have to re-enable the LED unit
17309 +        */
17310 +       if (!intensity || !old_intensity)
17311 +               pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0);
17312 +
17313 +       if (!intensity) /* illegal to set LEDOUT to 0 */
17314 +               ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f,
17315 +                                                                            2);
17316 +       else
17317 +               ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f,
17318 +                              intensity);
17319 +
17320 +       if (intensity)
17321 +               pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 2);
17322 +
17323 +}
17324 +
17325 +static struct generic_bl_info gta02_bl_info = {
17326 +       .name                   = "gta02-bl",
17327 +       .max_intensity          = 0xff,
17328 +       .default_intensity      = 0xff,
17329 +       .set_bl_intensity       = gta02_bl_set_intensity,
17330 +};
17331 +
17332 +static struct platform_device gta02_bl_dev = {
17333 +       .name             = "generic-bl",
17334 +       .id               = 1,
17335 +       .dev = {
17336 +               .platform_data = &gta02_bl_info,
17337 +       },
17338 +};
17339 +
17340 +/* SPI: LCM control interface attached to Glamo3362 */
17341 +
17342 +static void gta02_jbt6k74_reset(int devidx, int level)
17343 +{
17344 +       glamo_lcm_reset(level);
17345 +}
17346 +
17347 +static void gta02_jbt6k74_probe_completed(struct device *dev)
17348 +{
17349 +       struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
17350 +
17351 +       /* Switch on backlight. Qi does not do it for us */
17352 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDOUT, 0x01);
17353 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x00);
17354 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 0x01);
17355 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x01);
17356 +
17357 +       gta02_bl_dev.dev.parent = dev;
17358 +       platform_device_register(&gta02_bl_dev);
17359 +}
17360 +
17361 +const struct jbt6k74_platform_data jbt6k74_pdata = {
17362 +       .reset          = gta02_jbt6k74_reset,
17363 +       .probe_completed = gta02_jbt6k74_probe_completed,
17364 +};
17365 +
17366 +static struct spi_board_info gta02_spi_board_info[] = {
17367 +       {
17368 +               .modalias       = "jbt6k74",
17369 +               /* platform_data */
17370 +               .platform_data  = &jbt6k74_pdata,
17371 +               /* controller_data */
17372 +               /* irq */
17373 +               .max_speed_hz   = 100 * 1000,
17374 +               .bus_num        = 2,
17375 +               /* chip_select */
17376 +       },
17377 +};
17378 +
17379 +#if 0 /* currently this is not used and we use gpio spi */
17380 +static struct glamo_spi_info glamo_spi_cfg = {
17381 +       .board_size     = ARRAY_SIZE(gta02_spi_board_info),
17382 +       .board_info     = gta02_spi_board_info,
17383 +};
17384 +#endif /* 0 */
17385 +
17386 +static struct glamo_spigpio_info glamo_spigpio_cfg = {
17387 +       .pin_clk        = GLAMO_GPIO10_OUTPUT,
17388 +       .pin_mosi       = GLAMO_GPIO11_OUTPUT,
17389 +       .pin_cs         = GLAMO_GPIO12_OUTPUT,
17390 +       .pin_miso       = 0,
17391 +       .board_size     = ARRAY_SIZE(gta02_spi_board_info),
17392 +       .board_info     = gta02_spi_board_info,
17393 +};
17394 +
17395 +/* SPI: Accelerometers attached to SPI of s3c244x */
17396 +
17397 +/*
17398 + * Situation is that Linux SPI can't work in an interrupt context, so we
17399 + * implement our own bitbang here.  Arbitration is needed because not only
17400 + * can this interrupt happen at any time even if foreground wants to use
17401 + * the bitbang API from Linux, but multiple motion sensors can be on the
17402 + * same SPI bus, and multiple interrupts can happen.
17403 + *
17404 + * Foreground / interrupt arbitration is okay because the interrupts are
17405 + * disabled around all the foreground SPI code.
17406 + *
17407 + * Interrupt / Interrupt arbitration is evidently needed, otherwise we
17408 + * lose edge-triggered service after a while due to the two sensors sharing
17409 + * the SPI bus having irqs at the same time eventually.
17410 + *
17411 + * Servicing is typ 75 - 100us at 400MHz.
17412 + */
17413 +
17414 +/* #define DEBUG_SPEW_MS */
17415 +#define MG_PER_SAMPLE 18
17416 +
17417 +struct lis302dl_platform_data lis302_pdata_top;
17418 +struct lis302dl_platform_data lis302_pdata_bottom;
17419 +
17420 +/*
17421 + * generic SPI RX and TX bitbang
17422 + * only call with interrupts off!
17423 + */
17424 +
17425 +static void __gta02_lis302dl_bitbang(struct lis302dl_info *lis, u8 *tx,
17426 +                                            int tx_bytes, u8 *rx, int rx_bytes)
17427 +{
17428 +       struct lis302dl_platform_data *pdata = lis->pdata;
17429 +       int n;
17430 +       u8 shifter = 0;
17431 +       unsigned long other_cs;
17432 +
17433 +       /*
17434 +        * Huh... "quirk"... CS on this device is not really "CS" like you can
17435 +        * expect.
17436 +        *
17437 +        * When it is 0 it selects SPI interface mode.
17438 +        * When it is 1 it selects I2C interface mode.
17439 +        *
17440 +        * Because we have 2 devices on one interface we have to make sure
17441 +        * that the "disabled" device (actually in I2C mode) don't think we're
17442 +        * talking to it.
17443 +        *
17444 +        * When we talk to the "enabled" device, the "disabled" device sees
17445 +        * the clocks as I2C clocks, creating havoc.
17446 +        *
17447 +        * I2C sees MOSI going LOW while CLK HIGH as a START action, thus we
17448 +        * must ensure this is never issued.
17449 +        */
17450 +
17451 +       if (&lis302_pdata_top == pdata)
17452 +               other_cs = lis302_pdata_bottom.pin_chip_select;
17453 +       else
17454 +               other_cs = lis302_pdata_top.pin_chip_select;
17455 +
17456 +       s3c2410_gpio_setpin(other_cs, 1);
17457 +       s3c2410_gpio_setpin(pdata->pin_chip_select, 1);
17458 +       s3c2410_gpio_setpin(pdata->pin_clk, 1);
17459 +       s3c2410_gpio_setpin(pdata->pin_chip_select, 0);
17460 +
17461 +       /* send the register index, r/w and autoinc bits */
17462 +       for (n = 0; n < (tx_bytes << 3); n++) {
17463 +               if (!(n & 7))
17464 +                       shifter = ~tx[n >> 3];
17465 +               s3c2410_gpio_setpin(pdata->pin_clk, 0);
17466 +               s3c2410_gpio_setpin(pdata->pin_mosi, !(shifter & 0x80));
17467 +               s3c2410_gpio_setpin(pdata->pin_clk, 1);
17468 +               shifter <<= 1;
17469 +       }
17470 +
17471 +       for (n = 0; n < (rx_bytes << 3); n++) { /* 8 bits each */
17472 +               s3c2410_gpio_setpin(pdata->pin_clk, 0);
17473 +               shifter <<= 1;
17474 +               if (s3c2410_gpio_getpin(pdata->pin_miso))
17475 +                       shifter |= 1;
17476 +               if ((n & 7) == 7)
17477 +                       rx[n >> 3] = shifter;
17478 +               s3c2410_gpio_setpin(pdata->pin_clk, 1);
17479 +       }
17480 +       s3c2410_gpio_setpin(pdata->pin_chip_select, 1);
17481 +       s3c2410_gpio_setpin(other_cs, 1);
17482 +}
17483 +
17484 +
17485 +static int gta02_lis302dl_bitbang_read_reg(struct lis302dl_info *lis, u8 reg)
17486 +{
17487 +       u8 data = 0xc0 | reg; /* read, autoincrement */
17488 +       unsigned long flags;
17489 +
17490 +       local_irq_save(flags);
17491 +
17492 +       __gta02_lis302dl_bitbang(lis, &data, 1, &data, 1);
17493 +
17494 +       local_irq_restore(flags);
17495 +
17496 +       return data;
17497 +}
17498 +
17499 +static void gta02_lis302dl_bitbang_write_reg(struct lis302dl_info *lis, u8 reg,
17500 +                                                                        u8 val)
17501 +{
17502 +       u8 data[2] = { 0x00 | reg, val }; /* write, no autoincrement */
17503 +       unsigned long flags;
17504 +
17505 +       local_irq_save(flags);
17506 +
17507 +       __gta02_lis302dl_bitbang(lis, &data[0], 2, NULL, 0);
17508 +
17509 +       local_irq_restore(flags);
17510 +
17511 +}
17512 +
17513 +
17514 +void gta02_lis302dl_suspend_io(struct lis302dl_info *lis, int resume)
17515 +{
17516 +       struct lis302dl_platform_data *pdata = lis->pdata;
17517 +
17518 +       if (!resume) {
17519 +                /*
17520 +                * we don't want to power them with a high level
17521 +                * because GSENSOR_3V3 is not up during suspend
17522 +                */
17523 +               s3c2410_gpio_setpin(pdata->pin_chip_select, 0);
17524 +               s3c2410_gpio_setpin(pdata->pin_clk, 0);
17525 +               s3c2410_gpio_setpin(pdata->pin_mosi, 0);
17526 +               /* misnomer: it is a pullDOWN in 2442 */
17527 +               s3c2410_gpio_pullup(pdata->pin_miso, 1);
17528 +               return;
17529 +       }
17530 +
17531 +       /* back to normal */
17532 +       s3c2410_gpio_setpin(pdata->pin_chip_select, 1);
17533 +       s3c2410_gpio_setpin(pdata->pin_clk, 1);
17534 +       /* misnomer: it is a pullDOWN in 2442 */
17535 +       s3c2410_gpio_pullup(pdata->pin_miso, 0);
17536 +
17537 +       s3c2410_gpio_cfgpin(pdata->pin_chip_select, S3C2410_GPIO_OUTPUT);
17538 +       s3c2410_gpio_cfgpin(pdata->pin_clk, S3C2410_GPIO_OUTPUT);
17539 +       s3c2410_gpio_cfgpin(pdata->pin_mosi, S3C2410_GPIO_OUTPUT);
17540 +       s3c2410_gpio_cfgpin(pdata->pin_miso, S3C2410_GPIO_INPUT);
17541 +
17542 +}
17543 +
17544 +
17545 +
17546 +struct lis302dl_platform_data lis302_pdata_top = {
17547 +               .name           = "lis302-1 (top)",
17548 +               .pin_chip_select= S3C2410_GPD12,
17549 +               .pin_clk        = S3C2410_GPG7,
17550 +               .pin_mosi       = S3C2410_GPG6,
17551 +               .pin_miso       = S3C2410_GPG5,
17552 +               .interrupt      = GTA02_IRQ_GSENSOR_1,
17553 +               .open_drain     = 1, /* altered at runtime by PCB rev */
17554 +               .lis302dl_bitbang = __gta02_lis302dl_bitbang,
17555 +               .lis302dl_bitbang_reg_read = gta02_lis302dl_bitbang_read_reg,
17556 +               .lis302dl_bitbang_reg_write = gta02_lis302dl_bitbang_write_reg,
17557 +               .lis302dl_suspend_io = gta02_lis302dl_suspend_io,
17558 +};
17559 +
17560 +struct lis302dl_platform_data lis302_pdata_bottom = {
17561 +               .name           = "lis302-2 (bottom)",
17562 +               .pin_chip_select= S3C2410_GPD13,
17563 +               .pin_clk        = S3C2410_GPG7,
17564 +               .pin_mosi       = S3C2410_GPG6,
17565 +               .pin_miso       = S3C2410_GPG5,
17566 +               .interrupt      = GTA02_IRQ_GSENSOR_2,
17567 +               .open_drain     = 1, /* altered at runtime by PCB rev */
17568 +               .lis302dl_bitbang = __gta02_lis302dl_bitbang,
17569 +               .lis302dl_bitbang_reg_read = gta02_lis302dl_bitbang_read_reg,
17570 +               .lis302dl_bitbang_reg_write = gta02_lis302dl_bitbang_write_reg,
17571 +               .lis302dl_suspend_io = gta02_lis302dl_suspend_io,
17572 +};
17573 +
17574 +
17575 +static struct platform_device s3c_device_spi_acc1 = {
17576 +       .name             = "lis302dl",
17577 +       .id               = 1,
17578 +       .dev = {
17579 +               .platform_data = &lis302_pdata_top,
17580 +       },
17581 +};
17582 +
17583 +static struct platform_device s3c_device_spi_acc2 = {
17584 +       .name             = "lis302dl",
17585 +       .id               = 2,
17586 +       .dev = {
17587 +               .platform_data = &lis302_pdata_bottom,
17588 +       },
17589 +};
17590 +
17591 +static struct resource gta02_led_resources[] = {
17592 +       {
17593 +               .name   = "gta02-power:orange",
17594 +               .start  = GTA02_GPIO_PWR_LED1,
17595 +               .end    = GTA02_GPIO_PWR_LED1,
17596 +       }, {
17597 +               .name   = "gta02-power:blue",
17598 +               .start  = GTA02_GPIO_PWR_LED2,
17599 +               .end    = GTA02_GPIO_PWR_LED2,
17600 +       }, {
17601 +               .name   = "gta02-aux:red",
17602 +               .start  = GTA02_GPIO_AUX_LED,
17603 +               .end    = GTA02_GPIO_AUX_LED,
17604 +       },
17605 +};
17606 +
17607 +struct platform_device gta02_led_dev = {
17608 +       .name           = "gta02-led",
17609 +       .num_resources  = ARRAY_SIZE(gta02_led_resources),
17610 +       .resource       = gta02_led_resources,
17611 +};
17612 +
17613 +static struct resource gta02_button_resources[] = {
17614 +       [0] = {
17615 +               .start = GTA02_GPIO_AUX_KEY,
17616 +               .end   = GTA02_GPIO_AUX_KEY,
17617 +       },
17618 +       [1] = {
17619 +               .start = GTA02_GPIO_HOLD_KEY,
17620 +               .end   = GTA02_GPIO_HOLD_KEY,
17621 +       },
17622 +       [2] = {
17623 +               .start = GTA02_GPIO_JACK_INSERT,
17624 +               .end   = GTA02_GPIO_JACK_INSERT,
17625 +       },
17626 +       [3] = {
17627 +               .start = 0,
17628 +               .end   = 0,
17629 +       },
17630 +       [4] = {
17631 +               .start = 0,
17632 +               .end   = 0,
17633 +       },
17634 +};
17635 +
17636 +static struct platform_device gta02_button_dev = {
17637 +       .name           = "neo1973-button",
17638 +       .num_resources  = ARRAY_SIZE(gta02_button_resources),
17639 +       .resource       = gta02_button_resources,
17640 +};
17641 +
17642 +
17643 +static struct platform_device gta02_pm_usbhost_dev = {
17644 +       .name           = "neo1973-pm-host",
17645 +};
17646 +
17647 +
17648 +/* USB */
17649 +static struct s3c2410_hcd_info gta02_usb_info = {
17650 +       .port[0]        = {
17651 +               .flags  = S3C_HCDFLG_USED,
17652 +       },
17653 +       .port[1]        = {
17654 +               .flags  = 0,
17655 +       },
17656 +};
17657 +
17658 +static int glamo_irq_is_wired(void)
17659 +{
17660 +       int rc;
17661 +       int count = 0;
17662 +
17663 +       /*
17664 +       * GTA02 S-Media IRQs prior to A5 are broken due to a lack of
17665 +       * a pullup on the INT# line.  Check for the bad behaviour.
17666 +       */
17667 +       s3c2410_gpio_setpin(S3C2410_GPG4, 0);
17668 +       s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_OUTP);
17669 +       s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_INP);
17670 +       /*
17671 +       * we force it low ourselves for a moment and resume being input.
17672 +       * If there is a pullup, it won't stay low for long.  But if the
17673 +       * level converter is there as on < A5 revision, the weak keeper
17674 +       * on the input of the LC will hold the line low indefinitiely
17675 +       */
17676 +       do
17677 +               rc = s3c2410_gpio_getpin(S3C2410_GPG4);
17678 +       while ((!rc) && ((count++) < 10));
17679 +       if (rc) { /* it got pulled back up, it's good */
17680 +               printk(KERN_INFO "Detected S-Media IRQ# pullup, "
17681 +               "enabling interrupt\n");
17682 +               return 0;
17683 +       } else  /* Gah we can't work with this level converter */
17684 +               printk(KERN_WARNING "** Detected bad IRQ# circuit found"
17685 +               " on pre-A5 GTA02: S-Media interrupt disabled **\n");
17686 +       return -ENODEV;
17687 +}
17688 +
17689 +static int gta02_glamo_can_set_mmc_power(void)
17690 +{
17691 +       switch (system_rev) {
17692 +               case GTA02v3_SYSTEM_REV:
17693 +               case GTA02v4_SYSTEM_REV:
17694 +               case GTA02v5_SYSTEM_REV:
17695 +               case GTA02v6_SYSTEM_REV:
17696 +                       return 1;
17697 +       }
17698 +
17699 +       return 0;
17700 +}
17701 +
17702 +/* Smedia Glamo 3362 */
17703 +
17704 +/*
17705 + * we crank down SD Card clock dynamically when GPS is powered
17706 + */
17707 +
17708 +static int gta02_glamo_mci_use_slow(void)
17709 +{
17710 +       return neo1973_pm_gps_is_on();
17711 +}
17712 +
17713 +static void gta02_glamo_external_reset(int level)
17714 +{
17715 +       s3c2410_gpio_setpin(GTA02_GPIO_3D_RESET, level);
17716 +       s3c2410_gpio_cfgpin(GTA02_GPIO_3D_RESET, S3C2410_GPIO_OUTPUT);
17717 +}
17718 +
17719 +static struct glamofb_platform_data gta02_glamo_pdata = {
17720 +       .width          = 43,
17721 +       .height         = 58,
17722 +        /* 24.5MHz --> 40.816ns */
17723 +       .pixclock       = 40816,
17724 +       .left_margin    = 8,
17725 +       .right_margin   = 16,
17726 +       .upper_margin   = 2,
17727 +       .lower_margin   = 16,
17728 +       .hsync_len      = 8,
17729 +       .vsync_len      = 2,
17730 +       .fb_mem_size    = 0x400000, /* glamo has 8 megs of SRAM. we use 4 */
17731 +       .xres           = {
17732 +               .min    = 240,
17733 +               .max    = 640,
17734 +               .defval = 480,
17735 +       },
17736 +       .yres           = {
17737 +               .min    = 320,
17738 +               .max    = 640,
17739 +               .defval = 640,
17740 +       },
17741 +       .bpp            = {
17742 +               .min    = 16,
17743 +               .max    = 16,
17744 +               .defval = 16,
17745 +       },
17746 +       //.spi_info     = &glamo_spi_cfg,
17747 +       .spigpio_info   = &glamo_spigpio_cfg,
17748 +
17749 +       /* glamo MMC function platform data */
17750 +       .mmc_dev = &gta02_mmc_dev,
17751 +       .glamo_can_set_mci_power = gta02_glamo_can_set_mmc_power,
17752 +       .glamo_mci_use_slow = gta02_glamo_mci_use_slow,
17753 +       .glamo_irq_is_wired = glamo_irq_is_wired,
17754 +       .glamo_external_reset = gta02_glamo_external_reset
17755 +};
17756 +
17757 +static struct resource gta02_glamo_resources[] = {
17758 +       [0] = {
17759 +               .start  = S3C2410_CS1,
17760 +               .end    = S3C2410_CS1 + 0x1000000 - 1,
17761 +               .flags  = IORESOURCE_MEM,
17762 +       },
17763 +       [1] = {
17764 +               .start  = GTA02_IRQ_3D,
17765 +               .end    = GTA02_IRQ_3D,
17766 +               .flags  = IORESOURCE_IRQ,
17767 +       },
17768 +       [2] = {
17769 +               .start = GTA02v1_GPIO_3D_RESET,
17770 +               .end   = GTA02v1_GPIO_3D_RESET,
17771 +       },
17772 +};
17773 +
17774 +static struct platform_device gta02_glamo_dev = {
17775 +       .name           = "glamo3362",
17776 +       .num_resources  = ARRAY_SIZE(gta02_glamo_resources),
17777 +       .resource       = gta02_glamo_resources,
17778 +       .dev            = {
17779 +               .platform_data  = &gta02_glamo_pdata,
17780 +       },
17781 +};
17782 +
17783 +static void mangle_glamo_res_by_system_rev(void)
17784 +{
17785 +       switch (system_rev) {
17786 +       case GTA02v1_SYSTEM_REV:
17787 +               break;
17788 +       default:
17789 +               gta02_glamo_resources[2].start = GTA02_GPIO_3D_RESET;
17790 +               gta02_glamo_resources[2].end = GTA02_GPIO_3D_RESET;
17791 +               break;
17792 +       }
17793 +
17794 +       switch (system_rev) {
17795 +       case GTA02v1_SYSTEM_REV:
17796 +       case GTA02v2_SYSTEM_REV:
17797 +       case GTA02v3_SYSTEM_REV:
17798 +       /* case GTA02v4_SYSTEM_REV: - FIXME: handle this later */
17799 +               /* The hardware is missing a pull-up resistor and thus can't
17800 +                * support the Smedia Glamo IRQ */
17801 +               gta02_glamo_resources[1].start = 0;
17802 +               gta02_glamo_resources[1].end = 0;
17803 +               break;
17804 +       }
17805 +}
17806 +
17807 +static void __init gta02_map_io(void)
17808 +{
17809 +       s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
17810 +       s3c24xx_init_clocks(12000000);
17811 +       s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
17812 +}
17813 +
17814 +static irqreturn_t gta02_modem_irq(int irq, void *param)
17815 +{
17816 +       printk(KERN_DEBUG "modem wakeup interrupt\n");
17817 +       gta_gsm_interrupts++;
17818 +       return IRQ_HANDLED;
17819 +}
17820 +
17821 +static irqreturn_t ar6000_wow_irq(int irq, void *param)
17822 +{
17823 +       printk(KERN_DEBUG "ar6000_wow interrupt\n");
17824 +       return IRQ_HANDLED;
17825 +}
17826 +
17827 +/*
17828 + * hardware_ecc=1|0
17829 + */
17830 +static char hardware_ecc_str[4] __initdata = "";
17831 +
17832 +static int __init hardware_ecc_setup(char *str)
17833 +{
17834 +       if (str)
17835 +               strlcpy(hardware_ecc_str, str, sizeof(hardware_ecc_str));
17836 +       return 1;
17837 +}
17838 +
17839 +__setup("hardware_ecc=", hardware_ecc_setup);
17840 +
17841 +/* these are the guys that don't need to be children of PMU */
17842 +
17843 +static struct platform_device *gta02_devices[] __initdata = {
17844 +       &gta02_version_device,
17845 +       &s3c_device_usb,
17846 +       &s3c_device_wdt,
17847 +       &gta02_memconfig_device,
17848 +       &s3c_device_sdi,
17849 +       &s3c_device_usbgadget,
17850 +       &s3c_device_nand,
17851 +       &gta02_nor_flash,
17852 +
17853 +       &sc32440_fiq_device,
17854 +       &s3c24xx_pwm_device,
17855 +       &gta02_led_dev,
17856 +       &gta02_pm_wlan_dev, /* not dependent on PMU */
17857 +
17858 +       &s3c_device_iis,
17859 +       &s3c_device_i2c0,
17860 +};
17861 +
17862 +/* these guys DO need to be children of PMU */
17863 +
17864 +static struct platform_device *gta02_devices_pmu_children[] = {
17865 +       &s3c_device_ts, /* input 1 */
17866 +       &gta02_pm_gsm_dev,
17867 +       &gta02_pm_usbhost_dev,
17868 +       &s3c_device_spi_acc1, /* input 2 */
17869 +       &s3c_device_spi_acc2, /* input 3 */
17870 +       &gta02_button_dev, /* input 4 */
17871 +       &gta02_resume_reason_device,
17872 +};
17873 +
17874 +static void gta02_pmu_regulator_registered(struct pcf50633 *pcf, int id)
17875 +{
17876 +       struct platform_device *regulator, *pdev;
17877 +
17878 +       regulator = pcf->pmic.pdev[id];
17879 +
17880 +       switch(id) {
17881 +               case PCF50633_REGULATOR_LDO4:
17882 +                       pdev = &gta01_pm_bt_dev;
17883 +                       break;
17884 +               case PCF50633_REGULATOR_LDO5:
17885 +                       pdev = &gta01_pm_gps_dev;
17886 +                       break;
17887 +               case PCF50633_REGULATOR_HCLDO:
17888 +                       pdev = &gta02_glamo_dev;
17889 +                       break;
17890 +               default:
17891 +                       return;
17892 +       }
17893 +
17894 +       pdev->dev.parent = &regulator->dev;
17895 +       platform_device_register(pdev);
17896 +}
17897 +
17898 +/* this is called when pc50633 is probed, unfortunately quite late in the
17899 + * day since it is an I2C bus device.  Here we can belatedly define some
17900 + * platform devices with the advantage that we can mark the pcf50633 as the
17901 + * parent.  This makes them get suspended and resumed with their parent
17902 + * the pcf50633 still around.
17903 + */
17904 +
17905 +static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf)
17906 +{
17907 +       int n;
17908 +
17909 +       for (n = 0; n < ARRAY_SIZE(gta02_devices_pmu_children); n++)
17910 +               gta02_devices_pmu_children[n]->dev.parent = pcf->dev;
17911 +
17912 +       mangle_glamo_res_by_system_rev();
17913 +       platform_add_devices(gta02_devices_pmu_children,
17914 +                                       ARRAY_SIZE(gta02_devices_pmu_children));
17915 +}
17916 +
17917 +
17918 +static void __init gta02_machine_init(void)
17919 +{
17920 +       int rc;
17921 +
17922 +       /* set the panic callback to make AUX blink fast */
17923 +       panic_blink = gta02_panic_blink;
17924 +
17925 +       switch (system_rev) {
17926 +       case GTA02v6_SYSTEM_REV:
17927 +               /* we need push-pull interrupt from motion sensors */
17928 +               lis302_pdata_top.open_drain = 0;
17929 +               lis302_pdata_bottom.open_drain = 0;
17930 +               break;
17931 +       default:
17932 +               break;
17933 +       }
17934 +
17935 +       spin_lock_init(&motion_irq_lock);
17936 +       INIT_DELAYED_WORK(&gta02_charger_work, gta02_charger_worker);
17937 +
17938 +       /* Glamo chip select optimization */
17939 +/*      *((u32 *)(S3C2410_MEMREG(((1 + 1) << 2)))) = 0x1280; */
17940 +
17941 +       /* do not force soft ecc if we are asked to use hardware_ecc */
17942 +       if (hardware_ecc_str[0] == '1')
17943 +               gta02_nand_info.software_ecc = 0;
17944 +
17945 +       s3c_device_usb.dev.platform_data = &gta02_usb_info;
17946 +       s3c_device_nand.dev.platform_data = &gta02_nand_info;
17947 +       s3c_device_sdi.dev.platform_data = &gta02_s3c_mmc_cfg;
17948 +
17949 +       /* acc sensor chip selects */
17950 +       s3c2410_gpio_setpin(S3C2410_GPD12, 1);
17951 +       s3c2410_gpio_cfgpin(S3C2410_GPD12, S3C2410_GPIO_OUTPUT);
17952 +       s3c2410_gpio_setpin(S3C2410_GPD13, 1);
17953 +       s3c2410_gpio_cfgpin(S3C2410_GPD13, S3C2410_GPIO_OUTPUT);
17954 +
17955 +       s3c24xx_udc_set_platdata(&gta02_udc_cfg);
17956 +       s3c_i2c0_set_platdata(NULL);
17957 +       set_s3c2410ts_info(&gta02_ts_cfg);
17958 +
17959 +       mangle_glamo_res_by_system_rev();
17960 +
17961 +       i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs));
17962 +
17963 +       mangle_pmu_pdata_by_system_rev();
17964 +
17965 +       platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices));
17966 +
17967 +       s3c_pm_init();
17968 +
17969 +       /* Make sure the modem can wake us up */
17970 +       set_irq_type(GTA02_IRQ_MODEM, IRQ_TYPE_EDGE_RISING);
17971 +       rc = request_irq(GTA02_IRQ_MODEM, gta02_modem_irq, IRQF_DISABLED,
17972 +                        "modem", NULL);
17973 +       if (rc < 0)
17974 +               printk(KERN_ERR "GTA02: can't request GSM modem wakeup IRQ\n");
17975 +       enable_irq_wake(GTA02_IRQ_MODEM);
17976 +
17977 +       /* Make sure the wifi module can wake us up*/
17978 +       set_irq_type(GTA02_IRQ_WLAN_GPIO1, IRQ_TYPE_EDGE_RISING);
17979 +       rc = request_irq(GTA02_IRQ_WLAN_GPIO1, ar6000_wow_irq, IRQF_DISABLED,
17980 +                       "ar6000", NULL);
17981 +
17982 +       if (rc < 0)
17983 +               printk(KERN_ERR "GTA02: can't request ar6k wakeup IRQ\n");
17984 +       enable_irq_wake(GTA02_IRQ_WLAN_GPIO1);
17985 +}
17986 +
17987 +void DEBUG_LED(int n)
17988 +{
17989 +//     int *p = NULL;
17990 +       switch (n) {
17991 +       case 0:
17992 +               neo1973_gpb_setpin(GTA02_GPIO_PWR_LED1, 1);
17993 +               break;
17994 +       case 1:
17995 +               neo1973_gpb_setpin(GTA02_GPIO_PWR_LED2, 1);
17996 +               break;
17997 +       default:
17998 +               neo1973_gpb_setpin(GTA02_GPIO_AUX_LED, 1);
17999 +               break;
18000 +       }
18001 +//     printk(KERN_ERR"die %d\n", *p);
18002 +}
18003 +EXPORT_SYMBOL_GPL(DEBUG_LED);
18004 +
18005 +MACHINE_START(NEO1973_GTA02, "GTA02")
18006 +       .phys_io        = S3C2410_PA_UART,
18007 +       .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
18008 +       .boot_params    = S3C2410_SDRAM_PA + 0x100,
18009 +       .map_io         = gta02_map_io,
18010 +       .init_irq       = s3c24xx_init_irq,
18011 +       .init_machine   = gta02_machine_init,
18012 +       .timer          = &s3c24xx_timer,
18013 +MACHINE_END
18014 --- a/arch/arm/mach-s3c2440/mach-nexcoder.c
18015 +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
18016 @@ -37,6 +37,7 @@
18017  //#include <asm/debug-ll.h>
18018  #include <mach/regs-gpio.h>
18019  #include <plat/regs-serial.h>
18020 +#include <plat/iic.h>
18021
18022  #include <plat/s3c2410.h>
18023  #include <plat/s3c2440.h>
18024 @@ -107,7 +108,7 @@ static struct platform_device *nexcoder_
18025         &s3c_device_usb,
18026         &s3c_device_lcd,
18027         &s3c_device_wdt,
18028 -       &s3c_device_i2c,
18029 +       &s3c_device_i2c0,
18030         &s3c_device_iis,
18031         &s3c_device_rtc,
18032         &s3c_device_camif,
18033 @@ -142,6 +143,7 @@ static void __init nexcoder_map_io(void)
18034
18035  static void __init nexcoder_init(void)
18036  {
18037 +       s3c_i2c0_set_platdata(NULL);
18038         platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
18039  };
18040
18041 --- a/arch/arm/mach-s3c2440/mach-osiris.c
18042 +++ b/arch/arm/mach-s3c2440/mach-osiris.c
18043 @@ -37,7 +37,8 @@
18044  #include <mach/regs-gpio.h>
18045  #include <mach/regs-mem.h>
18046  #include <mach/regs-lcd.h>
18047 -#include <asm/plat-s3c/nand.h>
18048 +#include <plat/nand.h>
18049 +#include <plat/iic.h>
18050
18051  #include <linux/mtd/mtd.h>
18052  #include <linux/mtd/nand.h>
18053 @@ -335,7 +336,7 @@ static struct i2c_board_info osiris_i2c_
18054  /* Standard Osiris devices */
18055
18056  static struct platform_device *osiris_devices[] __initdata = {
18057 -       &s3c_device_i2c,
18058 +       &s3c_device_i2c0,
18059         &s3c_device_wdt,
18060         &s3c_device_nand,
18061         &osiris_pcmcia,
18062 @@ -398,6 +399,8 @@ static void __init osiris_init(void)
18063         sysdev_class_register(&osiris_pm_sysclass);
18064         sysdev_register(&osiris_pm_sysdev);
18065
18066 +       s3c_i2c0_set_platdata(NULL);
18067 +
18068         i2c_register_board_info(0, osiris_i2c_devs,
18069                                 ARRAY_SIZE(osiris_i2c_devs));
18070
18071 --- a/arch/arm/mach-s3c2440/mach-rx3715.c
18072 +++ b/arch/arm/mach-s3c2440/mach-rx3715.c
18073 @@ -42,7 +42,7 @@
18074  #include <mach/regs-lcd.h>
18075
18076  #include <mach/h1940.h>
18077 -#include <asm/plat-s3c/nand.h>
18078 +#include <plat/nand.h>
18079  #include <mach/fb.h>
18080
18081  #include <plat/clock.h>
18082 @@ -179,7 +179,7 @@ static struct platform_device *rx3715_de
18083         &s3c_device_usb,
18084         &s3c_device_lcd,
18085         &s3c_device_wdt,
18086 -       &s3c_device_i2c,
18087 +       &s3c_device_i2c0,
18088         &s3c_device_iis,
18089         &s3c_device_nand,
18090  };
18091 @@ -203,7 +203,7 @@ static void __init rx3715_init_machine(v
18092  #ifdef CONFIG_PM_H1940
18093         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
18094  #endif
18095 -       s3c2410_pm_init();
18096 +       s3c_pm_init();
18097
18098         s3c24xx_fb_set_platdata(&rx3715_fb_info);
18099         platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
18100 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c
18101 +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
18102 @@ -37,6 +37,7 @@
18103
18104  #include <mach/idle.h>
18105  #include <mach/fb.h>
18106 +#include <plat/iic.h>
18107
18108  #include <plat/s3c2410.h>
18109  #include <plat/s3c2440.h>
18110 @@ -152,7 +153,7 @@ static struct platform_device *smdk2440_
18111         &s3c_device_usb,
18112         &s3c_device_lcd,
18113         &s3c_device_wdt,
18114 -       &s3c_device_i2c,
18115 +       &s3c_device_i2c0,
18116         &s3c_device_iis,
18117  };
18118
18119 @@ -166,6 +167,7 @@ static void __init smdk2440_map_io(void)
18120  static void __init smdk2440_machine_init(void)
18121  {
18122         s3c24xx_fb_set_platdata(&smdk2440_fb_info);
18123 +       s3c_i2c0_set_platdata(NULL);
18124
18125         platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices));
18126         smdk_machine_init();
18127 --- a/arch/arm/mach-s3c2440/Makefile
18128 +++ b/arch/arm/mach-s3c2440/Makefile
18129 @@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_S3C2440)     += s3c2440.o d
18130  obj-$(CONFIG_CPU_S3C2440)      += irq.o
18131  obj-$(CONFIG_CPU_S3C2440)      += clock.o
18132  obj-$(CONFIG_S3C2440_DMA)      += dma.o
18133 +obj-$(CONFIG_S3C2440_C_FIQ)    += fiq_c_isr.o
18134
18135  # Machine support
18136
18137 @@ -22,3 +23,6 @@ obj-$(CONFIG_MACH_RX3715)     += mach-rx3715
18138  obj-$(CONFIG_ARCH_S3C2440)     += mach-smdk2440.o
18139  obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
18140  obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
18141 +obj-$(CONFIG_MACH_HXD8)                += mach-hxd8.o
18142 +obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
18143 +
18144 --- a/arch/arm/mach-s3c2440/s3c2440.c
18145 +++ b/arch/arm/mach-s3c2440/s3c2440.c
18146 @@ -46,6 +46,9 @@ int __init s3c2440_init(void)
18147         s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
18148         s3c_device_wdt.resource[1].end   = IRQ_S3C2440_WDT;
18149
18150 +       /* make sure SD/MMC driver can distinguish 2440 from 2410 */
18151 +       s3c_device_sdi.name = "s3c2440-sdi";
18152 +
18153         /* register our system device for everything else */
18154
18155         return sysdev_register(&s3c2440_sysdev);
18156 --- a/arch/arm/mach-s3c2442/Kconfig
18157 +++ b/arch/arm/mach-s3c2442/Kconfig
18158 @@ -6,10 +6,11 @@
18159
18160  config CPU_S3C2442
18161         bool
18162 -       depends on ARCH_S3C2410
18163 +       depends on CPU_S3C2440
18164         select S3C2410_CLOCK
18165         select S3C2410_GPIO
18166         select S3C2410_PM if PM
18167 +       select S3C2440_DMA if S3C2410_DMA
18168         select CPU_S3C244X
18169         select CPU_LLSERIAL_S3C2440
18170         help
18171 --- a/arch/arm/mach-s3c2442/s3c2442.c
18172 +++ b/arch/arm/mach-s3c2442/s3c2442.c
18173 @@ -21,6 +21,7 @@
18174
18175  #include <plat/s3c2442.h>
18176  #include <plat/cpu.h>
18177 +#include <plat/devs.h>
18178
18179  static struct sys_device s3c2442_sysdev = {
18180         .cls            = &s3c2442_sysclass,
18181 @@ -30,5 +31,8 @@ int __init s3c2442_init(void)
18182  {
18183         printk("S3C2442: Initialising architecture\n");
18184
18185 +       /* make sure SD/MMC driver can distinguish 2440 from 2410 */
18186 +       s3c_device_sdi.name = "s3c2440-sdi";
18187 +
18188         return sysdev_register(&s3c2442_sysdev);
18189  }
18190 --- a/arch/arm/mach-s3c2443/clock.c
18191 +++ b/arch/arm/mach-s3c2443/clock.c
18192 @@ -39,6 +39,8 @@
18193
18194  #include <mach/regs-s3c2443-clock.h>
18195
18196 +#include <plat/cpu-freq.h>
18197 +
18198  #include <plat/s3c2443.h>
18199  #include <plat/clock.h>
18200  #include <plat/cpu.h>
18201 @@ -145,12 +147,6 @@ static unsigned long s3c2443_roundrate_c
18202
18203  /* clock selections */
18204
18205 -/* CPU EXTCLK input */
18206 -static struct clk clk_ext = {
18207 -       .name           = "ext",
18208 -       .id             = -1,
18209 -};
18210 -
18211  static struct clk clk_mpllref = {
18212         .name           = "mpllref",
18213         .parent         = &clk_xtal,
18214 @@ -165,14 +161,6 @@ static struct clk clk_mpll = {
18215  };
18216  #endif
18217
18218 -static struct clk clk_epllref;
18219 -
18220 -static struct clk clk_epll = {
18221 -       .name           = "epll",
18222 -       .parent         = &clk_epllref,
18223 -       .id             = -1,
18224 -};
18225 -
18226  static struct clk clk_i2s_ext = {
18227         .name           = "i2s-ext",
18228         .id             = -1,
18229 @@ -1011,22 +999,20 @@ static struct clk *clks[] __initdata = {
18230         &clk_prediv,
18231  };
18232
18233 -void __init s3c2443_init_clocks(int xtal)
18234 +void __init_or_cpufreq s3c2443_setup_clocks(void)
18235  {
18236 -       unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
18237         unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
18238         unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
18239 +       struct clk *xtal_clk;
18240 +       unsigned long xtal;
18241         unsigned long pll;
18242         unsigned long fclk;
18243         unsigned long hclk;
18244         unsigned long pclk;
18245 -       struct clk *clkp;
18246 -       int ret;
18247 -       int ptr;
18248
18249 -       /* s3c2443 parents h and p clocks from prediv */
18250 -       clk_h.parent = &clk_prediv;
18251 -       clk_p.parent = &clk_prediv;
18252 +       xtal_clk = clk_get(NULL, "xtal");
18253 +       xtal = clk_get_rate(xtal_clk);
18254 +       clk_put(xtal_clk);
18255
18256         pll = s3c2443_get_mpll(mpllcon, xtal);
18257         clk_msysclk.rate = pll;
18258 @@ -1036,13 +1022,29 @@ void __init s3c2443_init_clocks(int xtal
18259         hclk /= s3c2443_get_hdiv(clkdiv0);
18260         pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
18261
18262 -       s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
18263 +       s3c24xx_setup_clocks(fclk, hclk, pclk);
18264
18265         printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
18266                (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
18267                print_mhz(pll), print_mhz(fclk),
18268                print_mhz(hclk), print_mhz(pclk));
18269
18270 +       s3c24xx_setup_clocks(fclk, hclk, pclk);
18271 +}
18272 +
18273 +void __init s3c2443_init_clocks(int xtal)
18274 +{
18275 +       struct clk *clkp;
18276 +       unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
18277 +       int ret;
18278 +       int ptr;
18279 +
18280 +       /* s3c2443 parents h and p clocks from prediv */
18281 +       clk_h.parent = &clk_prediv;
18282 +       clk_p.parent = &clk_prediv;
18283 +
18284 +       s3c24xx_register_baseclocks(xtal);
18285 +       s3c2443_setup_clocks();
18286         s3c2443_clk_initparents();
18287
18288         for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
18289 @@ -1056,7 +1058,7 @@ void __init s3c2443_init_clocks(int xtal
18290         }
18291
18292         clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
18293 -
18294 +       clk_epll.parent = &clk_epllref;
18295         clk_usb_bus.parent = &clk_usb_bus_host;
18296
18297         /* ensure usb bus clock is within correct rate of 48MHz */
18298 @@ -1105,4 +1107,6 @@ void __init s3c2443_init_clocks(int xtal
18299
18300                 (clkp->enable)(clkp, 0);
18301         }
18302 +
18303 +       s3c_pwmclk_init();
18304  }
18305 --- a/arch/arm/mach-s3c2443/dma.c
18306 +++ b/arch/arm/mach-s3c2443/dma.c
18307 @@ -26,12 +26,12 @@
18308
18309  #include <plat/regs-serial.h>
18310  #include <mach/regs-gpio.h>
18311 -#include <asm/plat-s3c/regs-ac97.h>
18312 +#include <plat/regs-ac97.h>
18313  #include <mach/regs-mem.h>
18314  #include <mach/regs-lcd.h>
18315  #include <mach/regs-sdi.h>
18316  #include <asm/plat-s3c24xx/regs-iis.h>
18317 -#include <asm/plat-s3c24xx/regs-spi.h>
18318 +#include <plat/regs-spi.h>
18319
18320  #define MAP(x) { \
18321                 [0]     = (x) | DMA_CH_VALID,   \
18322 --- a/arch/arm/mach-s3c2443/Kconfig
18323 +++ b/arch/arm/mach-s3c2443/Kconfig
18324 @@ -24,6 +24,7 @@ config MACH_SMDK2443
18325         bool "SMDK2443"
18326         select CPU_S3C2443
18327         select MACH_SMDK
18328 +       select S3C_DEV_HSMMC
18329         help
18330           Say Y here if you are using an SMDK2443
18331
18332 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c
18333 +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
18334 @@ -37,6 +37,7 @@
18335
18336  #include <mach/idle.h>
18337  #include <mach/fb.h>
18338 +#include <plat/iic.h>
18339
18340  #include <plat/s3c2410.h>
18341  #include <plat/s3c2440.h>
18342 @@ -103,8 +104,8 @@ static struct s3c2410_uartcfg smdk2443_u
18343
18344  static struct platform_device *smdk2443_devices[] __initdata = {
18345         &s3c_device_wdt,
18346 -       &s3c_device_i2c,
18347 -       &s3c_device_hsmmc,
18348 +       &s3c_device_i2c0,
18349 +       &s3c_device_hsmmc0,
18350  };
18351
18352  static void __init smdk2443_map_io(void)
18353 @@ -116,6 +117,7 @@ static void __init smdk2443_map_io(void)
18354
18355  static void __init smdk2443_machine_init(void)
18356  {
18357 +       s3c_i2c0_set_platdata(NULL);
18358         platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
18359         smdk_machine_init();
18360  }
18361 --- a/arch/arm/mach-s3c2443/s3c2443.c
18362 +++ b/arch/arm/mach-s3c2443/s3c2443.c
18363 @@ -81,10 +81,9 @@ void __init s3c2443_init_uarts(struct s3
18364   * machine specific initialisation.
18365   */
18366
18367 -void __init s3c2443_map_io(struct map_desc *mach_desc, int mach_size)
18368 +void __init s3c2443_map_io(void)
18369  {
18370         iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
18371 -       iotable_init(mach_desc, mach_size);
18372  }
18373
18374  /* need to register class before we actually register the device, and
18375 --- /dev/null
18376 +++ b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
18377 @@ -0,0 +1,28 @@
18378 +/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
18379 + *
18380 + * This program is free software; you can redistribute it and/or modify
18381 + * it under the terms of the GNU General Public License version 2 as
18382 + * published by the Free Software Foundation.
18383 +*/
18384 +
18385 +/* pull in the relevant register and map files. */
18386 +
18387 +#include <mach/map.h>
18388 +#include <plat/regs-serial.h>
18389 +
18390 +       .macro addruart, rx
18391 +               mrc     p15, 0, \rx, c1, c0
18392 +               tst     \rx, #1
18393 +               ldreq   \rx, = S3C24XX_PA_UART
18394 +               ldrne   \rx, = S3C24XX_VA_UART
18395 +#if CONFIG_DEBUG_S3C_UART != 0
18396 +               add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
18397 +#endif
18398 +       .endm
18399 +
18400 +/* include the reset of the code which will do the work, we're only
18401 + * compiling for a single cpu processor type so the default of s3c2440
18402 + * will be fine with us.
18403 + */
18404 +
18405 +#include <plat/debug-macro.S>
18406 --- /dev/null
18407 +++ b/arch/arm/mach-s3c24a0/include/mach/io.h
18408 @@ -0,0 +1,16 @@
18409 +/* arch/arm/mach-s3c24a0/include/mach/io.h
18410 + *
18411 + * Copyright 2008 Simtec Electronics
18412 + *     Ben Dooks <ben-linux@fluff.org>
18413 + *
18414 + * IO access and mapping routines for the S3C24A0
18415 + */
18416 +
18417 +#ifndef __ASM_ARM_ARCH_IO_H
18418 +#define __ASM_ARM_ARCH_IO_H
18419 +
18420 +/* No current ISA/PCI bus support. */
18421 +#define __io(a)                ((void __iomem *)(a))
18422 +#define __mem_pci(a)   (a)
18423 +
18424 +#endif
18425 --- /dev/null
18426 +++ b/arch/arm/mach-s3c24a0/include/mach/irqs.h
18427 @@ -0,0 +1,117 @@
18428 +/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h
18429 + *
18430 + * Copyright (c) 2003-2005 Simtec Electronics
18431 + *   Ben Dooks <ben@simtec.co.uk>
18432 + *
18433 + * This program is free software; you can redistribute it and/or modify
18434 + * it under the terms of the GNU General Public License version 2 as
18435 + * published by the Free Software Foundation.
18436 +*/
18437 +
18438 +
18439 +#ifndef __ASM_ARCH_24A0_IRQS_H
18440 +#define __ASM_ARCH_24A0_IRQS_H __FILE__
18441 +
18442 +#define IRQ_EINT0t2    S3C2410_IRQ(0)  /* 16 */
18443 +/* for generic entry-macro.S */
18444 +#define IRQ_EINT0      IRQ_EINT0t2
18445 +
18446 +#define IRQ_EINT3t6    S3C2410_IRQ(1)
18447 +#define IRQ_EINT7t10   S3C2410_IRQ(2)
18448 +#define IRQ_EINT11t14  S3C2410_IRQ(3)
18449 +#define IRQ_EINT15t18  S3C2410_IRQ(4)  /* 20 */
18450 +#define IRQ_TICK       S3C2410_IRQ(5)
18451 +#define IRQ_DCTQ       S3C2410_IRQ(6)
18452 +#define IRQ_MC         S3C2410_IRQ(7)
18453 +#define IRQ_ME         S3C2410_IRQ(8)  /* 24 */
18454 +#define IRQ_KEYPAD     S3C2410_IRQ(9)
18455 +#define IRQ_TIMER0     S3C2410_IRQ(10)
18456 +#define IRQ_TIMER1     S3C2410_IRQ(11)
18457 +#define IRQ_TIMER2     S3C2410_IRQ(12)
18458 +#define IRQ_TIMER3_4   S3C2410_IRQ(13)
18459 +#define IRQ_OS_TIMER   IRQ_TIMER3_4
18460 +#define IRQ_LCD                S3C2410_IRQ(14)
18461 +#define IRQ_CAM_C      S3C2410_IRQ(15)
18462 +#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */
18463 +#define IRQ_UART0      S3C2410_IRQ(17)
18464 +#define IRQ_CAM_P      S3C2410_IRQ(18)
18465 +#define IRQ_MODEM      S3C2410_IRQ(19)
18466 +#define IRQ_DMA                S3C2410_IRQ(20)
18467 +#define IRQ_SDI                S3C2410_IRQ(21)
18468 +#define IRQ_SPI0       S3C2410_IRQ(22)
18469 +#define IRQ_UART1      S3C2410_IRQ(23)
18470 +#define IRQ_AC97_NFLASH        S3C2410_IRQ(24) /* 40 */
18471 +#define IRQ_USBD       S3C2410_IRQ(25)
18472 +#define IRQ_USBH       S3C2410_IRQ(26)
18473 +#define IRQ_IIC                S3C2410_IRQ(27)
18474 +#define IRQ_IRDA_MSTICK        S3C2410_IRQ(28) /* 44 */
18475 +#define IRQ_VLX_SPI1   S3C2410_IRQ(29)
18476 +#define IRQ_RTC                S3C2410_IRQ(30) /* 46 */
18477 +#define IRQ_ADC_PEN     S3C2410_IRQ(31)
18478 +
18479 +/* interrupts generated from the external interrupts sources */
18480 +#define IRQ_EINT00     S3C2410_IRQ(32) /* 48 */
18481 +#define IRQ_EINT1      S3C2410_IRQ(33)
18482 +#define IRQ_EINT2      S3C2410_IRQ(34)
18483 +#define IRQ_EINT3      S3C2410_IRQ(35)
18484 +#define IRQ_EINT4      S3C2410_IRQ(36)
18485 +#define IRQ_EINT5      S3C2410_IRQ(37)
18486 +#define IRQ_EINT6      S3C2410_IRQ(38)
18487 +#define IRQ_EINT7      S3C2410_IRQ(39)
18488 +#define IRQ_EINT8      S3C2410_IRQ(40)
18489 +#define IRQ_EINT9      S3C2410_IRQ(41)
18490 +#define IRQ_EINT10     S3C2410_IRQ(42)
18491 +#define IRQ_EINT11     S3C2410_IRQ(43)
18492 +#define IRQ_EINT12     S3C2410_IRQ(44)
18493 +#define IRQ_EINT13     S3C2410_IRQ(45)
18494 +#define IRQ_EINT14     S3C2410_IRQ(46)
18495 +#define IRQ_EINT15     S3C2410_IRQ(47)
18496 +#define IRQ_EINT16     S3C2410_IRQ(48)
18497 +#define IRQ_EINT17     S3C2410_IRQ(49)
18498 +#define IRQ_EINT18     S3C2410_IRQ(50)
18499 +
18500 +#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00)
18501 +
18502 +/* SUB IRQS */
18503 +#define IRQ_S3CUART_RX0                S3C2410_IRQ(51) /* 67 */
18504 +#define IRQ_S3CUART_TX0                S3C2410_IRQ(52)
18505 +#define IRQ_S3CUART_ERR0       S3C2410_IRQ(53)
18506 +
18507 +#define IRQ_S3CUART_RX1                S3C2410_IRQ(54)
18508 +#define IRQ_S3CUART_TX1                S3C2410_IRQ(55)
18509 +#define IRQ_S3CUART_ERR1       S3C2410_IRQ(56)
18510 +
18511 +#define IRQ_S3CUART_RX2                (0x0)
18512 +#define IRQ_S3CUART_TX2                (0x0)
18513 +#define IRQ_S3CUART_ERR2       (0x0)
18514 +
18515 +
18516 +#define IRQ_IRDA       S3C2410_IRQ(57)
18517 +#define IRQ_MSTICK     S3C2410_IRQ(58)
18518 +#define IRQ_RESERVED0  S3C2410_IRQ(59)
18519 +#define IRQ_RESERVED1  S3C2410_IRQ(60)
18520 +#define IRQ_RESERVED2  S3C2410_IRQ(61)
18521 +#define IRQ_TIMER3     S3C2410_IRQ(62)
18522 +#define IRQ_TIMER4     S3C2410_IRQ(63)
18523 +#define IRQ_WDT                S3C2410_IRQ(64)
18524 +#define IRQ_BATFLT     S3C2410_IRQ(65)
18525 +#define IRQ_POST       S3C2410_IRQ(66)
18526 +#define IRQ_DISP_FIFO  S3C2410_IRQ(67)
18527 +#define IRQ_PENUP      S3C2410_IRQ(68)
18528 +#define IRQ_PENDN      S3C2410_IRQ(69)
18529 +#define IRQ_ADC                S3C2410_IRQ(70)
18530 +#define IRQ_DISP_FRAME S3C2410_IRQ(71)
18531 +#define IRQ_NFLASH     S3C2410_IRQ(72)
18532 +#define IRQ_AC97       S3C2410_IRQ(73)
18533 +#define IRQ_SPI1       S3C2410_IRQ(74)
18534 +#define IRQ_VLX                S3C2410_IRQ(75)
18535 +#define IRQ_DMA0       S3C2410_IRQ(76)
18536 +#define IRQ_DMA1       S3C2410_IRQ(77)
18537 +#define IRQ_DMA2       S3C2410_IRQ(78)
18538 +#define IRQ_DMA3       S3C2410_IRQ(79)
18539 +
18540 +#define IRQ_TC         (0x0)
18541 +
18542 +#define NR_IRQS                (IRQ_DMA3+1)
18543 +
18544 +#endif /* __ASM_ARCH_24A0_IRQS_H */
18545 --- /dev/null
18546 +++ b/arch/arm/mach-s3c24a0/include/mach/map.h
18547 @@ -0,0 +1,85 @@
18548 +/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
18549 + *
18550 + * Copyright 2003,2007  Simtec Electronics
18551 + *     http://armlinux.simtec.co.uk/
18552 + *     Ben Dooks <ben@simtec.co.uk>
18553 + *
18554 + * S3C24A0 - Memory map definitions
18555 + *
18556 + * This program is free software; you can redistribute it and/or modify
18557 + * it under the terms of the GNU General Public License version 2 as
18558 + * published by the Free Software Foundation.
18559 +*/
18560 +
18561 +#ifndef __ASM_ARCH_24A0_MAP_H
18562 +#define __ASM_ARCH_24A0_MAP_H __FILE__
18563 +
18564 +#include <plat/map-base.h>
18565 +#include <plat/map.h>
18566 +
18567 +#define S3C24A0_PA_IO_BASE     (0x40000000)
18568 +#define S3C24A0_PA_CLKPWR      (0x40000000)
18569 +#define S3C24A0_PA_IRQ         (0x40200000)
18570 +#define S3C24A0_PA_DMA         (0x40400000)
18571 +#define S3C24A0_PA_MEMCTRL     (0x40C00000)
18572 +#define S3C24A0_PA_NAND                (0x40C00000)
18573 +#define S3C24A0_PA_SROM                (0x40C20000)
18574 +#define S3C24A0_PA_SDRAM       (0x40C40000)
18575 +#define S3C24A0_PA_BUSM                (0x40CE0000)
18576 +#define S3C24A0_PA_USBHOST     (0x41000000)
18577 +#define S3C24A0_PA_MODEMIF     (0x41180000)
18578 +#define S3C24A0_PA_IRDA                (0x41800000)
18579 +#define S3C24A0_PA_TIMER       (0x44000000)
18580 +#define S3C24A0_PA_WATCHDOG    (0x44100000)
18581 +#define S3C24A0_PA_RTC         (0x44200000)
18582 +#define S3C24A0_PA_UART                (0x44400000)
18583 +#define S3C24A0_PA_UART0       (S3C24A0_PA_UART)
18584 +#define S3C24A0_PA_UART1       (S3C24A0_PA_UART + 0x4000)
18585 +#define S3C24A0_PA_SPI         (0x44500000)
18586 +#define S3C24A0_PA_IIC         (0x44600000)
18587 +#define S3C24A0_PA_IIS         (0x44700000)
18588 +#define S3C24A0_PA_GPIO                (0x44800000)
18589 +#define S3C24A0_PA_KEYIF       (0x44900000)
18590 +#define S3C24A0_PA_USBDEV      (0x44A00000)
18591 +#define S3C24A0_PA_AC97                (0x45000000)
18592 +#define S3C24A0_PA_ADC         (0x45800000)
18593 +#define S3C24A0_PA_SDI         (0x46000000)
18594 +#define S3C24A0_PA_MS          (0x46100000)
18595 +#define S3C24A0_PA_LCD         (0x4A000000)
18596 +#define S3C24A0_PA_VPOST       (0x4A100000)
18597 +
18598 +/* physical addresses of all the chip-select areas */
18599 +
18600 +#define S3C24A0_CS0    (0x00000000)
18601 +#define S3C24A0_CS1    (0x04000000)
18602 +#define S3C24A0_CS2    (0x08000000)
18603 +#define S3C24A0_CS3    (0x0C000000)
18604 +#define S3C24A0_CS4    (0x10000000)
18605 +#define S3C24A0_CS5    (0x40000000)
18606 +
18607 +#define S3C24A0_SDRAM_PA       (S3C24A0_CS4)
18608 +
18609 +/* Use a single interface for common resources between S3C24XX cpus */
18610 +
18611 +#define S3C24XX_PA_IRQ         S3C24A0_PA_IRQ
18612 +#define S3C24XX_PA_MEMCTRL     S3C24A0_PA_MEMCTRL
18613 +#define S3C24XX_PA_USBHOST     S3C24A0_PA_USBHOST
18614 +#define S3C24XX_PA_DMA         S3C24A0_PA_DMA
18615 +#define S3C24XX_PA_CLKPWR      S3C24A0_PA_CLKPWR
18616 +#define S3C24XX_PA_LCD         S3C24A0_PA_LCD
18617 +#define S3C24XX_PA_UART                S3C24A0_PA_UART
18618 +#define S3C24XX_PA_TIMER       S3C24A0_PA_TIMER
18619 +#define S3C24XX_PA_USBDEV      S3C24A0_PA_USBDEV
18620 +#define S3C24XX_PA_WATCHDOG    S3C24A0_PA_WATCHDOG
18621 +#define S3C24XX_PA_IIS         S3C24A0_PA_IIS
18622 +#define S3C24XX_PA_GPIO                S3C24A0_PA_GPIO
18623 +#define S3C24XX_PA_RTC         S3C24A0_PA_RTC
18624 +#define S3C24XX_PA_ADC         S3C24A0_PA_ADC
18625 +#define S3C24XX_PA_SPI         S3C24A0_PA_SPI
18626 +#define S3C24XX_PA_SDI         S3C24A0_PA_SDI
18627 +#define S3C24XX_PA_NAND                S3C24A0_PA_NAND
18628 +
18629 +#define S3C_PA_UART            S3C24A0_PA_UART
18630 +#define S3C_PA_IIC             S3C24A0_PA_IIC
18631 +
18632 +#endif /* __ASM_ARCH_24A0_MAP_H */
18633 --- /dev/null
18634 +++ b/arch/arm/mach-s3c24a0/include/mach/memory.h
18635 @@ -0,0 +1,19 @@
18636 +/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h
18637 + *  from linux/include/asm-arm/arch-rpc/memory.h
18638 + *
18639 + *  Copyright (C) 1996,1997,1998 Russell King.
18640 + *
18641 + * This program is free software; you can redistribute it and/or modify
18642 + * it under the terms of the GNU General Public License version 2 as
18643 + * published by the Free Software Foundation.
18644 +*/
18645 +
18646 +#ifndef __ASM_ARCH_24A0_MEMORY_H
18647 +#define __ASM_ARCH_24A0_MEMORY_H __FILE__
18648 +
18649 +#define PHYS_OFFSET UL(0x10000000)
18650 +
18651 +#define __virt_to_bus(x) __virt_to_phys(x)
18652 +#define __bus_to_virt(x) __phys_to_virt(x)
18653 +
18654 +#endif
18655 --- /dev/null
18656 +++ b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
18657 @@ -0,0 +1,88 @@
18658 +/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
18659 + *
18660 + * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
18661 + *                   http://armlinux.simtec.co.uk/
18662 + *
18663 + * This program is free software; you can redistribute it and/or modify
18664 + * it under the terms of the GNU General Public License version 2 as
18665 + * published by the Free Software Foundation.
18666 + *
18667 + * S3C24A0 clock register definitions
18668 +*/
18669 +
18670 +#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
18671 +#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
18672 +
18673 +#define S3C24A0_MPLLCON                S3C2410_CLKREG(0x10)
18674 +#define S3C24A0_UPLLCON                S3C2410_CLKREG(0x14)
18675 +#define S3C24A0_CLKCON         S3C2410_CLKREG(0x20)
18676 +#define S3C24A0_CLKSRC         S3C2410_CLKREG(0x24)
18677 +#define S3C24A0_CLKDIVN                S3C2410_CLKREG(0x28)
18678 +
18679 +/* CLKCON register bits */
18680 +
18681 +#define S3C24A0_CLKCON_VLX     (1<<29)
18682 +#define S3C24A0_CLKCON_VPOST   (1<<28)
18683 +#define S3C24A0_CLKCON_WDT     (1<<27) /* reserved */
18684 +#define S3C24A0_CLKCON_MPEGDCTQ        (1<<26)
18685 +#define S3C24A0_CLKCON_VPOSTIF (1<<25)
18686 +#define S3C24A0_CLKCON_MPEG4IF (1<<24)
18687 +#define S3C24A0_CLKCON_CAM_UPLL        (1<<23)
18688 +#define S3C24A0_CLKCON_LCDC    (1<<22)
18689 +#define S3C24A0_CLKCON_CAM_HCLK        (1<<21)
18690 +#define S3C24A0_CLKCON_MPEG4   (1<<20)
18691 +#define S3C24A0_CLKCON_KEYPAD  (1<<19)
18692 +#define S3C24A0_CLKCON_ADC     (1<<18)
18693 +#define S3C24A0_CLKCON_SDI     (1<<17)
18694 +#define S3C24A0_CLKCON_MS      (1<<16) /* memory stick */
18695 +#define S3C24A0_CLKCON_USBD    (1<<15)
18696 +#define S3C24A0_CLKCON_GPIO    (1<<14)
18697 +#define S3C24A0_CLKCON_IIS     (1<<13)
18698 +#define S3C24A0_CLKCON_IIC     (1<<12)
18699 +#define S3C24A0_CLKCON_SPI     (1<<11)
18700 +#define S3C24A0_CLKCON_UART1   (1<<10)
18701 +#define S3C24A0_CLKCON_UART0   (1<<9)
18702 +#define S3C24A0_CLKCON_PWMT    (1<<8)
18703 +#define S3C24A0_CLKCON_USBH    (1<<7)
18704 +#define S3C24A0_CLKCON_AC97    (1<<6)
18705 +#define S3C24A0_CLKCON_IrDA    (1<<4)
18706 +#define S3C24A0_CLKCON_IDLE    (1<<2)
18707 +#define S3C24A0_CLKCON_MON     (1<<1)
18708 +#define S3C24A0_CLKCON_STOP    (1<<0)
18709 +
18710 +/* CLKSRC register bits */
18711 +
18712 +#define S3C24A0_CLKSRC_OSC     (1<<8)  /* CLKSRC */
18713 +#define S3C24A0_CLKSRC_UPLL    (1<<7)
18714 +#define S3C24A0_CLKSRC_MPLL    (1<<5)
18715 +#define S3C24A0_CLKSRC_EXT     (1<<4)
18716 +
18717 +/* Use a single interface with the common code, for s3c24xx */
18718 +
18719 +#define S3C2410_MPLLCON                S3C24A0_MPLLCON
18720 +#define S3C2410_UPLLCON                S3C24A0_UPLLCON
18721 +#define S3C2410_CLKCON         S3C24A0_CLKCON
18722 +#define S3C2410_CLKSLOW                S3C24A0_CLKSRC
18723 +#define S3C2410_CLKDIVN                S3C24A0_CLKDIVN
18724 +
18725 +#define S3C2410_CLKCON_IDLE    S3C24A0_CLKCON_IDLE
18726 +#define S3C2410_CLKCON_POWER   S3C24A0_CLKCON_STOP
18727 +#define S3C2410_CLKCON_LCDC    S3C24A0_CLKCON_LCDC
18728 +#define S3C2410_CLKCON_USBH    S3C24A0_CLKCON_USBH
18729 +#define S3C2410_CLKCON_USBD    S3C24A0_CLKCON_USBD
18730 +#define S3C2410_CLKCON_PWMT    S3C24A0_CLKCON_PWMT
18731 +#define S3C2410_CLKCON_SDI     S3C24A0_CLKCON_SDI
18732 +#define S3C2410_CLKCON_UART0   S3C24A0_CLKCON_UART0
18733 +#define S3C2410_CLKCON_UART1   S3C24A0_CLKCON_UART1
18734 +#define S3C2410_CLKCON_GPIO    S3C24A0_CLKCON_GPIO
18735 +#define S3C2410_CLKCON_ADC     S3C24A0_CLKCON_ADC
18736 +#define S3C2410_CLKCON_IIC     S3C24A0_CLKCON_IIC
18737 +#define S3C2410_CLKCON_IIS     S3C24A0_CLKCON_IIS
18738 +#define S3C2410_CLKCON_SPI     S3C24A0_CLKCON_SPI
18739 +
18740 +#define S3C2410_CLKSLOW_UCLK_OFF       S3C24A0_CLKSRC_UPLL
18741 +#define S3C2410_CLKSLOW_MPLL_OFF       S3C24A0_CLKSRC_MPLL
18742 +#define S3C2410_CLKSLOW_SLOW           (0xFF)
18743 +#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
18744 +
18745 +#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */
18746 --- /dev/null
18747 +++ b/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
18748 @@ -0,0 +1,25 @@
18749 +/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
18750 + *
18751 + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
18752 + *                   http://www.simtec.co.uk/products/SWLINUX/
18753 + *
18754 + * This program is free software; you can redistribute it and/or modify
18755 + * it under the terms of the GNU General Public License version 2 as
18756 + * published by the Free Software Foundation.
18757 +*/
18758 +
18759 +
18760 +#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H
18761 +#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__
18762 +
18763 +
18764 +#define S3C2410_EINTMASK       S3C2410_EINTREG(0x034)
18765 +#define S3C2410_EINTPEND       S3C2410_EINTREG(0X038)
18766 +
18767 +#define S3C24XX_EINTMASK       S3C24XX_EINTREG(0x034)
18768 +#define S3C24XX_EINTPEND       S3C24XX_EINTREG(0X038)
18769 +
18770 +#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */
18771 +
18772 +
18773 +
18774 --- /dev/null
18775 +++ b/arch/arm/mach-s3c24a0/include/mach/system.h
18776 @@ -0,0 +1,25 @@
18777 +/* linux/arch/arm/mach-s3c24a0/include/mach/system.h
18778 + *
18779 + * Copyright 2008 Simtec Electronics
18780 + *     Ben Dooks <ben@simtec.co.uk>
18781 + *
18782 + * S3C24A0 - System function defines and includes
18783 + *
18784 + * This program is free software; you can redistribute it and/or modify
18785 + * it under the terms of the GNU General Public License version 2 as
18786 + * published by the Free Software Foundation.
18787 +*/
18788 +
18789 +#include <mach/hardware.h>
18790 +#include <asm/io.h>
18791 +
18792 +#include <mach/map.h>
18793 +
18794 +static void arch_idle(void)
18795 +{
18796 +       /* currently no specific idle support. */
18797 +}
18798 +
18799 +void (*s3c24xx_reset_hook)(void);
18800 +
18801 +#include <asm/plat-s3c24xx/system-reset.h>
18802 --- /dev/null
18803 +++ b/arch/arm/mach-s3c24a0/include/mach/tick.h
18804 @@ -0,0 +1,15 @@
18805 +/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h
18806 + *
18807 + * Copyright 2008 Simtec Electronics
18808 + *      Ben Dooks <ben@simtec.co.uk>
18809 + *      http://armlinux.simtec.co.uk/
18810 + *
18811 + * S3C24A0 - timer tick support
18812 + */
18813 +
18814 +#define SUBSRC_TIMER4  (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0))
18815 +
18816 +static inline int s3c24xx_ostimer_pending(void)
18817 +{
18818 +       return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4;
18819 +}
18820 --- /dev/null
18821 +++ b/arch/arm/mach-s3c24a0/include/mach/timex.h
18822 @@ -0,0 +1,18 @@
18823 +/* linux/arch/arm/mach-s3c24a0/include/mach/timex.h
18824 + *
18825 + * Copyright (c) 2008 Simtec Electronics
18826 + *     Ben Dooks <ben@simtec.co.uk>
18827 + *
18828 + * S3C2410 - time parameters
18829 + *
18830 + * This program is free software; you can redistribute it and/or modify
18831 + * it under the terms of the GNU General Public License version 2 as
18832 + * published by the Free Software Foundation.
18833 +*/
18834 +
18835 +#ifndef __ASM_ARCH_TIMEX_H
18836 +#define __ASM_ARCH_TIMEX_H
18837 +
18838 +#define CLOCK_TICK_RATE 12000000
18839 +
18840 +#endif /* __ASM_ARCH_TIMEX_H */
18841 --- /dev/null
18842 +++ b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
18843 @@ -0,0 +1,17 @@
18844 +/* linux/include/asm-arm/arch-s3c24ao/vmalloc.h
18845 + *
18846 + * Copyright 2008 Simtec Electronics <linux@simtec.co.uk>
18847 +
18848 + * This program is free software; you can redistribute it and/or modify
18849 + * it under the terms of the GNU General Public License version 2 as
18850 + * published by the Free Software Foundation.
18851 + *
18852 + * S3C24A0 vmalloc definition
18853 +*/
18854 +
18855 +#ifndef __ASM_ARCH_VMALLOC_H
18856 +#define __ASM_ARCH_VMALLOC_H
18857 +
18858 +#define VMALLOC_END      (0xE0000000)
18859 +
18860 +#endif /* __ASM_ARCH_VMALLOC_H */
18861 --- /dev/null
18862 +++ b/arch/arm/mach-s3c6400/include/mach/debug-macro.S
18863 @@ -0,0 +1,39 @@
18864 +/* arch/arm/mach-s3c6400/include/mach/debug-macro.S
18865 + *
18866 + * Copyright 2008 Openmoko, Inc.
18867 + * Copyright 2008 Simtec Electronics
18868 + *     http://armlinux.simtec.co.uk/
18869 + *     Ben Dooks <ben@simtec.co.uk>
18870 + *
18871 + * This program is free software; you can redistribute it and/or modify
18872 + * it under the terms of the GNU General Public License version 2 as
18873 + * published by the Free Software Foundation.
18874 +*/
18875 +
18876 +/* pull in the relevant register and map files. */
18877 +
18878 +#include <mach/map.h>
18879 +#include <plat/regs-serial.h>
18880 +
18881 +       /* note, for the boot process to work we have to keep the UART
18882 +        * virtual address aligned to an 1MiB boundary for the L1
18883 +        * mapping the head code makes. We keep the UART virtual address
18884 +        * aligned and add in the offset when we load the value here.
18885 +        */
18886 +
18887 +       .macro addruart, rx
18888 +               mrc     p15, 0, \rx, c1, c0
18889 +               tst     \rx, #1
18890 +               ldreq   \rx, = S3C_PA_UART
18891 +               ldrne   \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
18892 +#if CONFIG_DEBUG_S3C_UART != 0
18893 +               add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
18894 +#endif
18895 +       .endm
18896 +
18897 +/* include the reset of the code which will do the work, we're only
18898 + * compiling for a single cpu processor type so the default of s3c2440
18899 + * will be fine with us.
18900 + */
18901 +
18902 +#include <plat/debug-macro.S>
18903 --- /dev/null
18904 +++ b/arch/arm/mach-s3c6400/include/mach/dma.h
18905 @@ -0,0 +1,16 @@
18906 +/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
18907 + *
18908 + * Copyright 2008 Openmoko, Inc.
18909 + * Copyright 2008 Simtec Electronics
18910 + *      Ben Dooks <ben@simtec.co.uk>
18911 + *      http://armlinux.simtec.co.uk/
18912 + *
18913 + * S3C6400 - DMA support
18914 + */
18915 +
18916 +#ifndef __ASM_ARCH_DMA_H
18917 +#define __ASM_ARCH_DMA_H __FILE__
18918 +
18919 +/* currently nothing here, placeholder */
18920 +
18921 +#endif /* __ASM_ARCH_IRQ_H */
18922 --- /dev/null
18923 +++ b/arch/arm/mach-s3c6400/include/mach/entry-macro.S
18924 @@ -0,0 +1,44 @@
18925 +/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
18926 + *
18927 + * Copyright 2008 Openmoko, Inc.
18928 + * Copyright 2008 Simtec Electronics
18929 + *     http://armlinux.simtec.co.uk/
18930 + *     Ben Dooks <ben@simtec.co.uk>
18931 + *
18932 + * Low-level IRQ helper macros for the Samsung S3C64XX series
18933 + *
18934 + * This file is licensed under  the terms of the GNU General Public
18935 + * License version 2. This program is licensed "as is" without any
18936 + * warranty of any kind, whether express or implied.
18937 +*/
18938 +
18939 +#include <asm/hardware/vic.h>
18940 +#include <mach/map.h>
18941 +#include <plat/irqs.h>
18942 +
18943 +       .macro  disable_fiq
18944 +       .endm
18945 +
18946 +       .macro  get_irqnr_preamble, base, tmp
18947 +       ldr     \base, =S3C_VA_VIC0
18948 +       .endm
18949 +
18950 +       .macro  arch_ret_to_user, tmp1, tmp2
18951 +       .endm
18952 +
18953 +       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
18954 +
18955 +       @ check the vic0
18956 +       mov     \irqnr, # S3C_IRQ_OFFSET + 31
18957 +       ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
18958 +       teq     \irqstat, #0
18959 +
18960 +       @ otherwise try vic1
18961 +       addeq   \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
18962 +       addeq   \irqnr, \irqnr, #32
18963 +       ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
18964 +       teqeq   \irqstat, #0
18965 +
18966 +       clzne   \irqstat, \irqstat
18967 +       subne   \irqnr, \irqnr, \irqstat
18968 +       .endm
18969 --- /dev/null
18970 +++ b/arch/arm/mach-s3c6400/include/mach/gpio-core.h
18971 @@ -0,0 +1,21 @@
18972 +/* arch/arm/mach-s3c6400/include/mach/gpio-core.h
18973 + *
18974 + * Copyright 2008 Openmoko, Inc.
18975 + * Copyright 2008 Simtec Electronics
18976 + *      Ben Dooks <ben@simtec.co.uk>
18977 + *      http://armlinux.simtec.co.uk/
18978 + *
18979 + * S3C64XX - GPIO core support
18980 + *
18981 + * This program is free software; you can redistribute it and/or modify
18982 + * it under the terms of the GNU General Public License version 2 as
18983 + * published by the Free Software Foundation.
18984 +*/
18985 +
18986 +#ifndef __ASM_ARCH_GPIO_CORE_H
18987 +#define __ASM_ARCH_GPIO_CORE_H __FILE__
18988 +
18989 +/* currently we just include the platform support */
18990 +#include <plat/gpio-core.h>
18991 +
18992 +#endif /* __ASM_ARCH_GPIO_CORE_H */
18993 --- /dev/null
18994 +++ b/arch/arm/mach-s3c6400/include/mach/gpio.h
18995 @@ -0,0 +1,96 @@
18996 +/* arch/arm/mach-s3c6400/include/mach/gpio.h
18997 + *
18998 + * Copyright 2008 Openmoko, Inc.
18999 + * Copyright 2008 Simtec Electronics
19000 + *     http://armlinux.simtec.co.uk/
19001 + *     Ben Dooks <ben@simtec.co.uk>
19002 + *
19003 + * S3C6400 - GPIO lib support
19004 + *
19005 + * This program is free software; you can redistribute it and/or modify
19006 + * it under the terms of the GNU General Public License version 2 as
19007 + * published by the Free Software Foundation.
19008 +*/
19009 +
19010 +#define gpio_get_value __gpio_get_value
19011 +#define gpio_set_value __gpio_set_value
19012 +#define gpio_cansleep  __gpio_cansleep
19013 +#define gpio_to_irq    __gpio_to_irq
19014 +
19015 +/* GPIO bank sizes */
19016 +#define S3C64XX_GPIO_A_NR      (8)
19017 +#define S3C64XX_GPIO_B_NR      (7)
19018 +#define S3C64XX_GPIO_C_NR      (8)
19019 +#define S3C64XX_GPIO_D_NR      (5)
19020 +#define S3C64XX_GPIO_E_NR      (5)
19021 +#define S3C64XX_GPIO_F_NR      (16)
19022 +#define S3C64XX_GPIO_G_NR      (7)
19023 +#define S3C64XX_GPIO_H_NR      (10)
19024 +#define S3C64XX_GPIO_I_NR      (16)
19025 +#define S3C64XX_GPIO_J_NR      (12)
19026 +#define S3C64XX_GPIO_K_NR      (16)
19027 +#define S3C64XX_GPIO_L_NR      (15)
19028 +#define S3C64XX_GPIO_M_NR      (6)
19029 +#define S3C64XX_GPIO_N_NR      (16)
19030 +#define S3C64XX_GPIO_O_NR      (16)
19031 +#define S3C64XX_GPIO_P_NR      (15)
19032 +#define S3C64XX_GPIO_Q_NR      (9)
19033 +
19034 +/* GPIO bank numbes */
19035 +
19036 +/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
19037 + * space for debugging purposes so that any accidental
19038 + * change from one gpio bank to another can be caught.
19039 +*/
19040 +
19041 +#define S3C64XX_GPIO_NEXT(__gpio) \
19042 +       ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
19043 +
19044 +enum s3c_gpio_number {
19045 +       S3C64XX_GPIO_A_START = 0,
19046 +       S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
19047 +       S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
19048 +       S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
19049 +       S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
19050 +       S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
19051 +       S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
19052 +       S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
19053 +       S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
19054 +       S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
19055 +       S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
19056 +       S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
19057 +       S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
19058 +       S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
19059 +       S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
19060 +       S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
19061 +       S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
19062 +};
19063 +
19064 +/* S3C64XX GPIO number definitions. */
19065 +
19066 +#define S3C64XX_GPA(_nr)       (S3C64XX_GPIO_A_START + (_nr))
19067 +#define S3C64XX_GPB(_nr)       (S3C64XX_GPIO_B_START + (_nr))
19068 +#define S3C64XX_GPC(_nr)       (S3C64XX_GPIO_C_START + (_nr))
19069 +#define S3C64XX_GPD(_nr)       (S3C64XX_GPIO_D_START + (_nr))
19070 +#define S3C64XX_GPE(_nr)       (S3C64XX_GPIO_E_START + (_nr))
19071 +#define S3C64XX_GPF(_nr)       (S3C64XX_GPIO_F_START + (_nr))
19072 +#define S3C64XX_GPG(_nr)       (S3C64XX_GPIO_G_START + (_nr))
19073 +#define S3C64XX_GPH(_nr)       (S3C64XX_GPIO_H_START + (_nr))
19074 +#define S3C64XX_GPI(_nr)       (S3C64XX_GPIO_I_START + (_nr))
19075 +#define S3C64XX_GPJ(_nr)       (S3C64XX_GPIO_J_START + (_nr))
19076 +#define S3C64XX_GPK(_nr)       (S3C64XX_GPIO_K_START + (_nr))
19077 +#define S3C64XX_GPL(_nr)       (S3C64XX_GPIO_L_START + (_nr))
19078 +#define S3C64XX_GPM(_nr)       (S3C64XX_GPIO_M_START + (_nr))
19079 +#define S3C64XX_GPN(_nr)       (S3C64XX_GPIO_N_START + (_nr))
19080 +#define S3C64XX_GPO(_nr)       (S3C64XX_GPIO_O_START + (_nr))
19081 +#define S3C64XX_GPP(_nr)       (S3C64XX_GPIO_P_START + (_nr))
19082 +#define S3C64XX_GPQ(_nr)       (S3C64XX_GPIO_Q_START + (_nr))
19083 +
19084 +/* the end of the S3C64XX specific gpios */
19085 +#define S3C64XX_GPIO_END       (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
19086 +#define S3C_GPIO_END           S3C64XX_GPIO_END
19087 +
19088 +/* define the number of gpios we need to the one after the GPQ() range */
19089 +#define ARCH_NR_GPIOS  (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
19090 +
19091 +#include <asm-generic/gpio.h>
19092 --- /dev/null
19093 +++ b/arch/arm/mach-s3c6400/include/mach/hardware.h
19094 @@ -0,0 +1,16 @@
19095 +/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h
19096 + *
19097 + * Copyright 2008 Openmoko, Inc.
19098 + * Copyright 2008 Simtec Electronics
19099 + *      Ben Dooks <ben@simtec.co.uk>
19100 + *      http://armlinux.simtec.co.uk/
19101 + *
19102 + * S3C6400 - Hardware support
19103 + */
19104 +
19105 +#ifndef __ASM_ARCH_HARDWARE_H
19106 +#define __ASM_ARCH_HARDWARE_H __FILE__
19107 +
19108 +/* currently nothing here, placeholder */
19109 +
19110 +#endif /* __ASM_ARCH_IRQ_H */
19111 --- /dev/null
19112 +++ b/arch/arm/mach-s3c6400/include/mach/irqs.h
19113 @@ -0,0 +1,20 @@
19114 +/* linux/arch/arm/mach-s3c6400/include/mach/irqs.h
19115 + *
19116 + * Copyright 2008 Openmoko, Inc.
19117 + * Copyright 2008 Simtec Electronics
19118 + *      Ben Dooks <ben@simtec.co.uk>
19119 + *      http://armlinux.simtec.co.uk/
19120 + *
19121 + * S3C6400 - IRQ definitions
19122 + */
19123 +
19124 +#ifndef __ASM_ARCH_IRQS_H
19125 +#define __ASM_ARCH_IRQS_H __FILE__
19126 +
19127 +#ifndef __ASM_ARM_IRQ_H
19128 +#error "Do not include this directly, instead #include <asm/irq.h>"
19129 +#endif
19130 +
19131 +#include <plat/irqs.h>
19132 +
19133 +#endif /* __ASM_ARCH_IRQ_H */
19134 --- /dev/null
19135 +++ b/arch/arm/mach-s3c6400/include/mach/map.h
19136 @@ -0,0 +1,71 @@
19137 +/* linux/arch/arm/mach-s3c6400/include/mach/map.h
19138 + *
19139 + * Copyright 2008 Openmoko, Inc.
19140 + * Copyright 2008 Simtec Electronics
19141 + *     http://armlinux.simtec.co.uk/
19142 + *     Ben Dooks <ben@simtec.co.uk>
19143 + *
19144 + * S3C64XX - Memory map definitions
19145 + *
19146 + * This program is free software; you can redistribute it and/or modify
19147 + * it under the terms of the GNU General Public License version 2 as
19148 + * published by the Free Software Foundation.
19149 +*/
19150 +
19151 +#ifndef __ASM_ARCH_MAP_H
19152 +#define __ASM_ARCH_MAP_H __FILE__
19153 +
19154 +#include <plat/map-base.h>
19155 +
19156 +/* HSMMC units */
19157 +#define S3C64XX_PA_HSMMC(x)    (0x7C200000 + ((x) * 0x100000))
19158 +#define S3C64XX_PA_HSMMC0      S3C64XX_PA_HSMMC(0)
19159 +#define S3C64XX_PA_HSMMC1      S3C64XX_PA_HSMMC(1)
19160 +#define S3C64XX_PA_HSMMC2      S3C64XX_PA_HSMMC(2)
19161 +
19162 +#define S3C_PA_UART            (0x7F005000)
19163 +#define S3C_PA_UART0           (S3C_PA_UART + 0x00)
19164 +#define S3C_PA_UART1           (S3C_PA_UART + 0x400)
19165 +#define S3C_PA_UART2           (S3C_PA_UART + 0x800)
19166 +#define S3C_PA_UART3           (S3C_PA_UART + 0xC00)
19167 +#define S3C_UART_OFFSET                (0x400)
19168 +
19169 +/* See notes on UART VA mapping in debug-macro.S */
19170 +#define S3C_VA_UARTx(x)        (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
19171 +
19172 +#define S3C_VA_UART0           S3C_VA_UARTx(0)
19173 +#define S3C_VA_UART1           S3C_VA_UARTx(1)
19174 +#define S3C_VA_UART2           S3C_VA_UARTx(2)
19175 +#define S3C_VA_UART3           S3C_VA_UARTx(3)
19176 +
19177 +#define S3C64XX_PA_FB          (0x77100000)
19178 +#define S3C64XX_PA_SYSCON      (0x7E00F000)
19179 +#define S3C64XX_PA_TIMER       (0x7F006000)
19180 +#define S3C64XX_PA_IIC0                (0x7F004000)
19181 +#define S3C64XX_PA_IIC1                (0x7F00F000)
19182 +
19183 +#define S3C64XX_PA_GPIO                (0x7F008000)
19184 +#define S3C64XX_VA_GPIO                S3C_ADDR(0x00500000)
19185 +#define S3C64XX_SZ_GPIO                SZ_4K
19186 +
19187 +#define S3C64XX_PA_SDRAM       (0x50000000)
19188 +#define S3C64XX_PA_VIC0                (0x71200000)
19189 +#define S3C64XX_PA_VIC1                (0x71300000)
19190 +
19191 +#define S3C64XX_PA_MODEM       (0x74108000)
19192 +#define S3C64XX_VA_MODEM       S3C_ADDR(0x00600000)
19193 +
19194 +/* place VICs close together */
19195 +#define S3C_VA_VIC0            (S3C_VA_IRQ + 0x00)
19196 +#define S3C_VA_VIC1            (S3C_VA_IRQ + 0x10000)
19197 +
19198 +/* compatibiltiy defines. */
19199 +#define S3C_PA_TIMER           S3C64XX_PA_TIMER
19200 +#define S3C_PA_HSMMC0          S3C64XX_PA_HSMMC0
19201 +#define S3C_PA_HSMMC1          S3C64XX_PA_HSMMC1
19202 +#define S3C_PA_HSMMC2          S3C64XX_PA_HSMMC2
19203 +#define S3C_PA_IIC             S3C64XX_PA_IIC0
19204 +#define S3C_PA_IIC1            S3C64XX_PA_IIC1
19205 +#define S3C_PA_FB              S3C64XX_PA_FB
19206 +
19207 +#endif /* __ASM_ARCH_6400_MAP_H */
19208 --- /dev/null
19209 +++ b/arch/arm/mach-s3c6400/include/mach/memory.h
19210 @@ -0,0 +1,21 @@
19211 +/* arch/arm/mach-s3c6400/include/mach/memory.h
19212 + *
19213 + * Copyright 2008 Openmoko, Inc.
19214 + * Copyright 2008 Simtec Electronics
19215 + *      Ben Dooks <ben@simtec.co.uk>
19216 + *      http://armlinux.simtec.co.uk/
19217 + *
19218 + * This program is free software; you can redistribute it and/or modify
19219 + * it under the terms of the GNU General Public License version 2 as
19220 + * published by the Free Software Foundation.
19221 +*/
19222 +
19223 +#ifndef __ASM_ARCH_MEMORY_H
19224 +#define __ASM_ARCH_MEMORY_H
19225 +
19226 +#define PHYS_OFFSET     UL(0x50000000)
19227 +
19228 +#define __virt_to_bus(x) __virt_to_phys(x)
19229 +#define __bus_to_virt(x) __phys_to_virt(x)
19230 +
19231 +#endif
19232 --- /dev/null
19233 +++ b/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
19234 @@ -0,0 +1,56 @@
19235 +/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
19236 + *
19237 + * Copyright 2008 Openmoko, Inc.
19238 + * Copyright 2008 Simtec Electronics
19239 + *      Ben Dooks <ben@simtec.co.uk>
19240 + *      http://armlinux.simtec.co.uk/
19241 + *
19242 + * S3C64xx - pwm clock and timer support
19243 + */
19244 +
19245 +/**
19246 + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
19247 + * @tcfg: The timer TCFG1 register bits shifted down to 0.
19248 + *
19249 + * Return true if the given configuration from TCFG1 is a TCLK instead
19250 + * any of the TDIV clocks.
19251 + */
19252 +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
19253 +{
19254 +       return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
19255 +}
19256 +
19257 +/**
19258 + * tcfg_to_divisor() - convert tcfg1 setting to a divisor
19259 + * @tcfg1: The tcfg1 setting, shifted down.
19260 + *
19261 + * Get the divisor value for the given tcfg1 setting. We assume the
19262 + * caller has already checked to see if this is not a TCLK source.
19263 + */
19264 +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
19265 +{
19266 +       return 1 << tcfg1;
19267 +}
19268 +
19269 +/**
19270 + * pwm_tdiv_has_div1() - does the tdiv setting have a /1
19271 + *
19272 + * Return true if we have a /1 in the tdiv setting.
19273 + */
19274 +static inline unsigned int pwm_tdiv_has_div1(void)
19275 +{
19276 +       return 1;
19277 +}
19278 +
19279 +/**
19280 + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
19281 + * @div: The divisor to calculate the bit information for.
19282 + *
19283 + * Turn a divisor into the necessary bit field for TCFG1.
19284 + */
19285 +static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
19286 +{
19287 +       return ilog2(div);
19288 +}
19289 +
19290 +#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
19291 --- /dev/null
19292 +++ b/arch/arm/mach-s3c6400/include/mach/regs-clock.h
19293 @@ -0,0 +1,16 @@
19294 +/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
19295 + *
19296 + * Copyright 2008 Openmoko, Inc.
19297 + * Copyright 2008 Simtec Electronics
19298 + *     http://armlinux.simtec.co.uk/
19299 + *     Ben Dooks <ben@simtec.co.uk>
19300 + *
19301 + * S3C64XX - clock register compatibility with s3c24xx
19302 + *
19303 + * This program is free software; you can redistribute it and/or modify
19304 + * it under the terms of the GNU General Public License version 2 as
19305 + * published by the Free Software Foundation.
19306 +*/
19307 +
19308 +#include <plat/regs-clock.h>
19309 +
19310 --- /dev/null
19311 +++ b/arch/arm/mach-s3c6400/include/mach/regs-fb.h
19312 @@ -0,0 +1,259 @@
19313 +/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
19314 + *
19315 + * Copyright 2008 Openmoko, Inc.
19316 + * Copyright 2008 Simtec Electronics
19317 + *      http://armlinux.simtec.co.uk/
19318 + *      Ben Dooks <ben@simtec.co.uk>
19319 + *
19320 + * S3C64XX - new-style framebuffer register definitions
19321 + *
19322 + * This is the register set for the new style framebuffer interface
19323 + * found from the S3C2443 onwards and specifically the S3C64XX series
19324 + * S3C6400 and S3C6410.
19325 + *
19326 + * The file contains the cpu specific items which change between whichever
19327 + * architecture is selected. See <plat/regs-fb.h> for the core definitions
19328 + * that are the same.
19329 + *
19330 + * This program is free software; you can redistribute it and/or modify
19331 + * it under the terms of the GNU General Public License version 2 as
19332 + * published by the Free Software Foundation.
19333 +*/
19334 +
19335 +/* include the core definitions here, in case we really do need to
19336 + * override them at a later date.
19337 +*/
19338 +
19339 +#include <plat/regs-fb.h>
19340 +
19341 +#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
19342 +#define VIDCON1_FSTATUS_EVEN   (1 << 15)
19343 +
19344 +/* Video timing controls */
19345 +#define VIDTCON0                               (0x10)
19346 +#define VIDTCON1                               (0x14)
19347 +#define VIDTCON2                               (0x18)
19348 +
19349 +/* Window position controls */
19350 +
19351 +#define WINCON(_win)                           (0x20 + ((_win) * 4))
19352 +
19353 +/* OSD1 and OSD4 do not have register D */
19354 +
19355 +#define VIDOSD_A(_win)                         (0x40 + ((_win) * 16))
19356 +#define VIDOSD_B(_win)                         (0x44 + ((_win) * 16))
19357 +#define VIDOSD_C(_win)                         (0x48 + ((_win) * 16))
19358 +#define VIDOSD_D(_win)                         (0x4C + ((_win) * 16))
19359 +
19360 +/* Video buffer addresses */
19361 +
19362 +#define VIDW_BUF_START(_buff)                  (0xA0 + ((_buff) * 8))
19363 +#define VIDW_BUF_START1(_buff)                 (0xA4 + ((_buff) * 8))
19364 +#define VIDW_BUF_END(_buff)                    (0xD0 + ((_buff) * 8))
19365 +#define VIDW_BUF_END1(_buff)                   (0xD4 + ((_buff) * 8))
19366 +#define VIDW_BUF_SIZE(_buff)                   (0x100 + ((_buff) * 4))
19367 +
19368 +#define VIDINTCON0                             (0x130)
19369 +
19370 +#define WxKEYCONy(_win, _con)                  ((0x140 + ((_win) * 8)) + ((_con) * 4))
19371 +
19372 +/* WINCONx */
19373 +
19374 +#define WINCONx_CSCWIDTH_MASK                  (0x3 << 26)
19375 +#define WINCONx_CSCWIDTH_SHIFT                 (26)
19376 +#define WINCONx_CSCWIDTH_WIDE                  (0x0 << 26)
19377 +#define WINCONx_CSCWIDTH_NARROW                        (0x3 << 26)
19378 +
19379 +#define WINCONx_ENLOCAL                                (1 << 22)
19380 +#define WINCONx_BUFSTATUS                      (1 << 21)
19381 +#define WINCONx_BUFSEL                         (1 << 20)
19382 +#define WINCONx_BUFAUTOEN                      (1 << 19)
19383 +#define WINCONx_YCbCr                          (1 << 13)
19384 +
19385 +#define WINCON1_LOCALSEL_CAMIF                 (1 << 23)
19386 +
19387 +#define WINCON2_LOCALSEL_CAMIF                 (1 << 23)
19388 +#define WINCON2_BLD_PIX                                (1 << 6)
19389 +
19390 +#define WINCON2_ALPHA_SEL                      (1 << 1)
19391 +#define WINCON2_BPPMODE_MASK                   (0xf << 2)
19392 +#define WINCON2_BPPMODE_SHIFT                  (2)
19393 +#define WINCON2_BPPMODE_1BPP                   (0x0 << 2)
19394 +#define WINCON2_BPPMODE_2BPP                   (0x1 << 2)
19395 +#define WINCON2_BPPMODE_4BPP                   (0x2 << 2)
19396 +#define WINCON2_BPPMODE_8BPP_1232              (0x4 << 2)
19397 +#define WINCON2_BPPMODE_16BPP_565              (0x5 << 2)
19398 +#define WINCON2_BPPMODE_16BPP_A1555            (0x6 << 2)
19399 +#define WINCON2_BPPMODE_16BPP_I1555            (0x7 << 2)
19400 +#define WINCON2_BPPMODE_18BPP_666              (0x8 << 2)
19401 +#define WINCON2_BPPMODE_18BPP_A1665            (0x9 << 2)
19402 +#define WINCON2_BPPMODE_19BPP_A1666            (0xa << 2)
19403 +#define WINCON2_BPPMODE_24BPP_888              (0xb << 2)
19404 +#define WINCON2_BPPMODE_24BPP_A1887            (0xc << 2)
19405 +#define WINCON2_BPPMODE_25BPP_A1888            (0xd << 2)
19406 +#define WINCON2_BPPMODE_28BPP_A4888            (0xd << 2)
19407 +
19408 +#define WINCON3_BLD_PIX                                (1 << 6)
19409 +
19410 +#define WINCON3_ALPHA_SEL                      (1 << 1)
19411 +#define WINCON3_BPPMODE_MASK                   (0xf << 2)
19412 +#define WINCON3_BPPMODE_SHIFT                  (2)
19413 +#define WINCON3_BPPMODE_1BPP                   (0x0 << 2)
19414 +#define WINCON3_BPPMODE_2BPP                   (0x1 << 2)
19415 +#define WINCON3_BPPMODE_4BPP                   (0x2 << 2)
19416 +#define WINCON3_BPPMODE_16BPP_565              (0x5 << 2)
19417 +#define WINCON3_BPPMODE_16BPP_A1555            (0x6 << 2)
19418 +#define WINCON3_BPPMODE_16BPP_I1555            (0x7 << 2)
19419 +#define WINCON3_BPPMODE_18BPP_666              (0x8 << 2)
19420 +#define WINCON3_BPPMODE_18BPP_A1665            (0x9 << 2)
19421 +#define WINCON3_BPPMODE_19BPP_A1666            (0xa << 2)
19422 +#define WINCON3_BPPMODE_24BPP_888              (0xb << 2)
19423 +#define WINCON3_BPPMODE_24BPP_A1887            (0xc << 2)
19424 +#define WINCON3_BPPMODE_25BPP_A1888            (0xd << 2)
19425 +#define WINCON3_BPPMODE_28BPP_A4888            (0xd << 2)
19426 +
19427 +#define VIDINTCON0_FIFIOSEL_WINDOW2            (0x10 << 5)
19428 +#define VIDINTCON0_FIFIOSEL_WINDOW3            (0x20 << 5)
19429 +#define VIDINTCON0_FIFIOSEL_WINDOW4            (0x40 << 5)
19430 +
19431 +#define DITHMODE                               (0x170)
19432 +#define WINxMAP(_win)                          (0x180 + ((_win) * 4))
19433 +
19434 +
19435 +#define DITHMODE_R_POS_MASK                    (0x3 << 5)
19436 +#define DITHMODE_R_POS_SHIFT                   (5)
19437 +#define DITHMODE_R_POS_8BIT                    (0x0 << 5)
19438 +#define DITHMODE_R_POS_6BIT                    (0x1 << 5)
19439 +#define DITHMODE_R_POS_5BIT                    (0x2 << 5)
19440 +
19441 +#define DITHMODE_G_POS_MASK                    (0x3 << 3)
19442 +#define DITHMODE_G_POS_SHIFT                   (3)
19443 +#define DITHMODE_G_POS_8BIT                    (0x0 << 3)
19444 +#define DITHMODE_G_POS_6BIT                    (0x1 << 3)
19445 +#define DITHMODE_G_POS_5BIT                    (0x2 << 3)
19446 +
19447 +#define DITHMODE_B_POS_MASK                    (0x3 << 1)
19448 +#define DITHMODE_B_POS_SHIFT                   (1)
19449 +#define DITHMODE_B_POS_8BIT                    (0x0 << 1)
19450 +#define DITHMODE_B_POS_6BIT                    (0x1 << 1)
19451 +#define DITHMODE_B_POS_5BIT                    (0x2 << 1)
19452 +
19453 +#define DITHMODE_DITH_EN                       (1 << 0)
19454 +
19455 +#define WPALCON                                        (0x1A0)
19456 +
19457 +#define WPALCON_W4PAL_16BPP_A555               (1 << 8)
19458 +#define WPALCON_W3PAL_16BPP_A555               (1 << 7)
19459 +#define WPALCON_W2PAL_16BPP_A555               (1 << 6)
19460 +
19461 +/* Palette registers */
19462 +
19463 +#define WIN2_PAL(_entry)                       (0x300 + ((_entry) * 2))
19464 +#define WIN3_PAL(_entry)                       (0x320 + ((_entry) * 2))
19465 +#define WIN4_PAL(_entry)                       (0x340 + ((_entry) * 2))
19466 +#define WIN0_PAL(_entry)                       (0x400 + ((_entry) * 4))
19467 +#define WIN1_PAL(_entry)                       (0x800 + ((_entry) * 4))
19468 +
19469 +/* system specific implementation code for palette sizes, and other
19470 + * information that changes depending on which architecture is being
19471 + * compiled.
19472 +*/
19473 +
19474 +/* return true if window _win has OSD register D */
19475 +#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
19476 +
19477 +static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
19478 +{
19479 +       if (win < 2)
19480 +               return 256;
19481 +       if (win < 4)
19482 +               return 16;
19483 +       if (win == 4)
19484 +               return 4;
19485 +
19486 +       BUG();  /* shouldn't get here */
19487 +}
19488 +
19489 +static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
19490 +{
19491 +       /* all windows can do 1/2 bpp */
19492 +
19493 +       if ((bpp == 25 || bpp == 19) && win == 0)
19494 +               return 0;       /* win 0 does not have 19 or 25bpp modes */
19495 +
19496 +       if (bpp == 4 && win == 4)
19497 +               return 0;
19498 +
19499 +       if (bpp == 8 && (win >= 3))
19500 +               return 0;       /* win 3/4 cannot do 8bpp in any mode */
19501 +
19502 +       return 1;
19503 +}
19504 +
19505 +static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
19506 +{
19507 +       switch (window) {
19508 +       case 0: return WIN0_PAL(reg);
19509 +       case 1: return WIN1_PAL(reg);
19510 +       case 2: return WIN2_PAL(reg);
19511 +       case 3: return WIN3_PAL(reg);
19512 +       case 4: return WIN4_PAL(reg);
19513 +       }
19514 +
19515 +       BUG();
19516 +}
19517 +
19518 +static inline int s3c_fb_pal_is16(unsigned int window)
19519 +{
19520 +       return window > 1;
19521 +}
19522 +
19523 +struct s3c_fb_palette {
19524 +       struct fb_bitfield      r;
19525 +       struct fb_bitfield      g;
19526 +       struct fb_bitfield      b;
19527 +       struct fb_bitfield      a;
19528 +};
19529 +
19530 +static inline void s3c_fb_init_palette(unsigned int window,
19531 +                                      struct s3c_fb_palette *palette)
19532 +{
19533 +       if (window < 2) {
19534 +               /* Windows 0/1 are 8/8/8 or A/8/8/8 */
19535 +               palette->r.offset = 16;
19536 +               palette->r.length = 8;
19537 +               palette->g.offset = 8;
19538 +               palette->g.length = 8;
19539 +               palette->b.offset = 0;
19540 +               palette->b.length = 8;
19541 +       } else {
19542 +               /* currently we assume RGB 5/6/5 */
19543 +               palette->r.offset = 11;
19544 +               palette->r.length = 5;
19545 +               palette->g.offset = 5;
19546 +               palette->g.length = 6;
19547 +               palette->b.offset = 0;
19548 +               palette->b.length = 5;
19549 +       }
19550 +}
19551 +
19552 +/* Notes on per-window bpp settings
19553 + *
19554 + * Value       Win0     Win1     Win2     Win3     Win 4
19555 + * 0000                1(P)     1(P)     1(P)     1(P)     1(P)
19556 + * 0001                2(P)     2(P)     2(P)     2(P)     2(P)
19557 + * 0010                4(P)     4(P)     4(P)     4(P)     -none-
19558 + * 0011                8(P)     8(P)     -none-   -none-   -none-
19559 + * 0100                -none-   8(A232)  8(A232)  -none-   -none-
19560 + * 0101                16(565)  16(565)  16(565)  16(565)   16(565)
19561 + * 0110                -none-   16(A555) 16(A555) 16(A555)  16(A555)
19562 + * 0111                16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
19563 + * 1000                18(666)  18(666)  18(666)  18(666)   18(666)
19564 + * 1001                -none-   18(A665) 18(A665) 18(A665)  16(A665)
19565 + * 1010                -none-   19(A666) 19(A666) 19(A666)  19(A666)
19566 + * 1011                24(888)  24(888)  24(888)  24(888)   24(888)
19567 + * 1100                -none-   24(A887) 24(A887) 24(A887)  24(A887)
19568 + * 1101                -none-   25(A888) 25(A888) 25(A888)  25(A888)
19569 + * 1110                -none-   -none-   -none-   -none-    -none-
19570 + * 1111                -none-   -none-   -none-   -none-    -none-
19571 +*/
19572 --- /dev/null
19573 +++ b/arch/arm/mach-s3c6400/include/mach/regs-irq.h
19574 @@ -0,0 +1,20 @@
19575 +/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h
19576 + *
19577 + * Copyright 2008 Openmoko, Inc.
19578 + * Copyright 2008 Simtec Electronics
19579 + *     http://armlinux.simtec.co.uk/
19580 + *     Ben Dooks <ben@simtec.co.uk>
19581 + *
19582 + * S3C64XX - IRQ register definitions
19583 + *
19584 + * This program is free software; you can redistribute it and/or modify
19585 + * it under the terms of the GNU General Public License version 2 as
19586 + * published by the Free Software Foundation.
19587 +*/
19588 +
19589 +#ifndef __ASM_ARCH_REGS_IRQ_H
19590 +#define __ASM_ARCH_REGS_IRQ_H __FILE__
19591 +
19592 +#include <asm/hardware/vic.h>
19593 +
19594 +#endif /* __ASM_ARCH_6400_REGS_IRQ_H */
19595 --- /dev/null
19596 +++ b/arch/arm/mach-s3c6400/include/mach/system.h
19597 @@ -0,0 +1,44 @@
19598 +/* linux/arch/arm/mach-s3c6400/include/mach/system.h
19599 + *
19600 + * Copyright 2008 Openmoko, Inc.
19601 + * Copyright 2008 Simtec Electronics
19602 + *      Ben Dooks <ben@simtec.co.uk>
19603 + *      http://armlinux.simtec.co.uk/
19604 + *
19605 + * S3C6400 - system implementation
19606 + */
19607 +
19608 +#ifndef __ASM_ARCH_SYSTEM_H
19609 +#define __ASM_ARCH_SYSTEM_H __FILE__
19610 +
19611 +#include <linux/io.h>
19612 +#include <mach/map.h>
19613 +
19614 +#include <plat/regs-sys.h>
19615 +#include <plat/regs-syscon-power.h>
19616 +
19617 +static void arch_idle(void)
19618 +{
19619 +       unsigned long flags;
19620 +       u32 mode;
19621 +
19622 +       /* ensure that if we execute the cpu idle sequence that we
19623 +        * go into idle mode instead of powering off. */
19624 +
19625 +       local_irq_save(flags);
19626 +       mode = __raw_readl(S3C64XX_PWR_CFG);
19627 +       mode &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
19628 +       mode |= S3C64XX_PWRCFG_CFG_WFI_IDLE;
19629 +       __raw_writel(mode, S3C64XX_PWR_CFG);
19630 +
19631 +       local_irq_restore(flags);
19632 +
19633 +       cpu_do_idle();
19634 +}
19635 +
19636 +static void arch_reset(char mode)
19637 +{
19638 +       /* nothing here yet */
19639 +}
19640 +
19641 +#endif /* __ASM_ARCH_IRQ_H */
19642 --- /dev/null
19643 +++ b/arch/arm/mach-s3c6400/include/mach/tick.h
19644 @@ -0,0 +1,29 @@
19645 +/* linux/arch/arm/mach-s3c6400/include/mach/tick.h
19646 + *
19647 + * Copyright 2008 Openmoko, Inc.
19648 + * Copyright 2008 Simtec Electronics
19649 + *     http://armlinux.simtec.co.uk/
19650 + *     Ben Dooks <ben@simtec.co.uk>
19651 + *
19652 + * S3C64XX - Timer tick support definitions
19653 + *
19654 + * This program is free software; you can redistribute it and/or modify
19655 + * it under the terms of the GNU General Public License version 2 as
19656 + * published by the Free Software Foundation.
19657 +*/
19658 +
19659 +#ifndef __ASM_ARCH_TICK_H
19660 +#define __ASM_ARCH_TICK_H __FILE__
19661 +
19662 +/* note, the timer interrutps turn up in 2 places, the vic and then
19663 + * the timer block. We take the VIC as the base at the moment.
19664 + */
19665 +static inline u32 s3c24xx_ostimer_pending(void)
19666 +{
19667 +       u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
19668 +       return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0));
19669 +}
19670 +
19671 +#define TICK_MAX       (0xffffffff)
19672 +
19673 +#endif /* __ASM_ARCH_6400_TICK_H */
19674 --- /dev/null
19675 +++ b/arch/arm/mach-s3c6400/include/mach/uncompress.h
19676 @@ -0,0 +1,28 @@
19677 +/* arch/arm/mach-s3c6400/include/mach/uncompress.h
19678 + *
19679 + * Copyright 2008 Openmoko, Inc.
19680 + * Copyright 2008 Simtec Electronics
19681 + *     http://armlinux.simtec.co.uk/
19682 + *     Ben Dooks <ben@simtec.co.uk>
19683 + *
19684 + * S3C6400 - uncompress code
19685 + *
19686 + * This program is free software; you can redistribute it and/or modify
19687 + * it under the terms of the GNU General Public License version 2 as
19688 + * published by the Free Software Foundation.
19689 +*/
19690 +
19691 +#ifndef __ASM_ARCH_UNCOMPRESS_H
19692 +#define __ASM_ARCH_UNCOMPRESS_H
19693 +
19694 +#include <mach/map.h>
19695 +#include <plat/uncompress.h>
19696 +
19697 +static void arch_detect_cpu(void)
19698 +{
19699 +       /* we do not need to do any cpu detection here at the moment. */
19700 +       fifo_mask = S3C2440_UFSTAT_TXMASK;
19701 +       fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
19702 +}
19703 +
19704 +#endif /* __ASM_ARCH_UNCOMPRESS_H */
19705 --- /dev/null
19706 +++ b/arch/arm/mach-s3c6400/Kconfig
19707 @@ -0,0 +1,8 @@
19708 +# arch/arm/mach-s3c6400/Kconfig
19709 +#
19710 +# Copyright 2008 Openmoko, Inc.
19711 +#      Simtec Electronics, Ben Dooks <ben@simtec.co.uk>
19712 +#
19713 +# Licensed under GPLv2
19714 +
19715 +# Currently nothing here, this will be added later
19716 --- /dev/null
19717 +++ b/arch/arm/mach-s3c6400/Makefile
19718 @@ -0,0 +1,15 @@
19719 +# arch/arm/mach-s3c6400/Makefile
19720 +#
19721 +# Copyright 2008 Openmoko, Inc.
19722 +# Copyright 2008 Simtec Electronics
19723 +#
19724 +# Licensed under GPLv2
19725 +
19726 +obj-y                          :=
19727 +obj-m                          :=
19728 +obj-n                          :=
19729 +obj-                           :=
19730 +
19731 +# Core support for S3C6400 system
19732 +
19733 +obj-n                          += blank.o
19734 --- /dev/null
19735 +++ b/arch/arm/mach-s3c6400/Makefile.boot
19736 @@ -0,0 +1,2 @@
19737 +   zreladdr-y  := 0x50008000
19738 +params_phys-y  := 0x50000100
19739 --- /dev/null
19740 +++ b/arch/arm/mach-s3c6410/cpu.c
19741 @@ -0,0 +1,101 @@
19742 +/* linux/arch/arm/mach-s3c6410/cpu.c
19743 + *
19744 + * Copyright 2008 Simtec Electronics
19745 + * Copyright 2008 Simtec Electronics
19746 + *     Ben Dooks <ben@simtec.co.uk>
19747 + *     http://armlinux.simtec.co.uk/
19748 + *
19749 + * This program is free software; you can redistribute it and/or modify
19750 + * it under the terms of the GNU General Public License version 2 as
19751 + * published by the Free Software Foundation.
19752 +*/
19753 +
19754 +#include <linux/kernel.h>
19755 +#include <linux/types.h>
19756 +#include <linux/interrupt.h>
19757 +#include <linux/list.h>
19758 +#include <linux/timer.h>
19759 +#include <linux/init.h>
19760 +#include <linux/clk.h>
19761 +#include <linux/io.h>
19762 +#include <linux/sysdev.h>
19763 +#include <linux/serial_core.h>
19764 +#include <linux/platform_device.h>
19765 +
19766 +#include <asm/mach/arch.h>
19767 +#include <asm/mach/map.h>
19768 +#include <asm/mach/irq.h>
19769 +
19770 +#include <mach/hardware.h>
19771 +#include <asm/irq.h>
19772 +
19773 +#include <plat/cpu-freq.h>
19774 +#include <plat/regs-serial.h>
19775 +
19776 +#include <plat/cpu.h>
19777 +#include <plat/devs.h>
19778 +#include <plat/clock.h>
19779 +#include <plat/sdhci.h>
19780 +#include <plat/iic-core.h>
19781 +#include <plat/s3c6400.h>
19782 +#include <plat/s3c6410.h>
19783 +
19784 +/* Initial IO mappings */
19785 +
19786 +static struct map_desc s3c6410_iodesc[] __initdata = {
19787 +};
19788 +
19789 +/* s3c6410_map_io
19790 + *
19791 + * register the standard cpu IO areas
19792 +*/
19793 +
19794 +void __init s3c6410_map_io(void)
19795 +{
19796 +       iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
19797 +
19798 +       /* initialise device information early */
19799 +       s3c6410_default_sdhci0();
19800 +       s3c6410_default_sdhci1();
19801 +
19802 +       /* the i2c devices are directly compatible with s3c2440 */
19803 +       s3c_i2c0_setname("s3c2440-i2c");
19804 +       s3c_i2c1_setname("s3c2440-i2c");
19805 +}
19806 +
19807 +void __init s3c6410_init_clocks(int xtal)
19808 +{
19809 +       printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
19810 +       s3c24xx_register_baseclocks(xtal);
19811 +       s3c64xx_register_clocks();
19812 +       s3c6400_register_clocks();
19813 +       s3c6400_setup_clocks();
19814 +}
19815 +
19816 +void __init s3c6410_init_irq(void)
19817 +{
19818 +       /* VIC0 is missing IRQ7, VIC1 is fully populated. */
19819 +       s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
19820 +}
19821 +
19822 +struct sysdev_class s3c6410_sysclass = {
19823 +       .name   = "s3c6410-core",
19824 +};
19825 +
19826 +static struct sys_device s3c6410_sysdev = {
19827 +       .cls    = &s3c6410_sysclass,
19828 +};
19829 +
19830 +static int __init s3c6410_core_init(void)
19831 +{
19832 +       return sysdev_class_register(&s3c6410_sysclass);
19833 +}
19834 +
19835 +core_initcall(s3c6410_core_init);
19836 +
19837 +int __init s3c6410_init(void)
19838 +{
19839 +       printk("S3C6410: Initialising architecture\n");
19840 +
19841 +       return sysdev_register(&s3c6410_sysdev);
19842 +}
19843 --- /dev/null
19844 +++ b/arch/arm/mach-s3c6410/include/mach/om-gta03.h
19845 @@ -0,0 +1,91 @@
19846 +/*
19847 + * GTA03 GPIO Mappings
19848 + *
19849 + * (C) 2008 by Openmoko Inc.
19850 + * Author: Andy Green <andy@openmoko.com>
19851 + * All rights reserved.
19852 + *
19853 + * This program is free software; you can redistribute it and/or modify
19854 + * it under the terms of the GNU General Public License version 2 as
19855 + * published by the Free Software Foundation
19856 + *
19857 + */
19858 +
19859 +#ifndef _OM_GTA03_H
19860 +#define _OM_GTA03_H
19861 +
19862 +#include <mach/gpio.h>
19863 +#include <mach/irqs.h>
19864 +#include <linux/mfd/pcf50633/core.h>
19865 +
19866 +extern struct pcf50633_platform_data om_gta03_pcf_pdata;
19867 +
19868 +/* ATAG_REVISION from bootloader */
19869 +#define GTA03v1_SYSTEM_REV     0x00000001
19870 +
19871 +#define GTA03_GPIO_VIBRATOR_ON         S3C64XX_GPF(13)
19872 +#define GTA03_GPIO_CLKOUT              S3C64XX_GPF(14)
19873 +
19874 +#define GTA03_GPIO_ACCEL_MISO          S3C64XX_GPC(0)
19875 +#define GTA03_GPIO_ACCEL_CLK           S3C64XX_GPC(1)
19876 +#define GTA03_GPIO_ACCEL_MOSI          S3C64XX_GPC(2)
19877 +
19878 +#define GTA03_GPIO_LCM_MISO            S3C64XX_GPC(4)
19879 +#define GTA03_GPIO_LCM_CLK             S3C64XX_GPC(5)
19880 +#define GTA03_GPIO_LCM_MOSI            S3C64XX_GPC(6)
19881 +#define GTA03_GPIO_LCM_CS              S3C64XX_GPC(7)
19882 +
19883 +#define GTA03_GPIO_BTPCM_SHARED_SCLK   S3C64XX_GPE(0)
19884 +#define GTA03_GPIO_BTPCM_SHARED_EXTCLK S3C64XX_GPE(1)
19885 +#define GTA03_GPIO_BTPCM_SHARED_FSYNC  S3C64XX_GPE(2)
19886 +#define GTA03_GPIO_BTPCM_SHARED_SIN    S3C64XX_GPE(3)
19887 +#define GTA03_GPIO_BTPCM_SHARED_SOUT   S3C64XX_GPE(4)
19888 +
19889 +#define GTA03_GPIO_WLAN_RESET          S3C64XX_GPH(6)
19890 +#define GTA03_GPIO_HDQ                 S3C64XX_GPH(7)
19891 +#define GTA03_GPIO_WLAN_PWRDN          S3C64XX_GPH(8)
19892 +
19893 +#define GTA03_GPIO_VERSION2            S3C64XX_GPI(0)
19894 +#define GTA03_GPIO_VERSION1            S3C64XX_GPI(1)
19895 +#define GTA03_GPIO_VERSION0            S3C64XX_GPI(8)
19896 +
19897 +#define GTA03_GPIO_NWLAN_POWER         S3C64XX_GPK(0)
19898 +#define GTA03_GPIO_MODEN_ON            S3C64XX_GPK(2)
19899 +
19900 +#define GTA03_GPIO_TP_RESET            S3C64XX_GPM(0)
19901 +#define GTA03_GPIO_GPS_LNA_EN          S3C64XX_GPM(2)
19902 +
19903 +#define GTA03_GPIO_USB_FLT             S3C64XX_GPM(4)
19904 +#define GTA03_GPIO_USB_OC              S3C64XX_GPM(5)
19905 +
19906 +#define GTA03_GPIO_ACCEL_INT1          S3C64XX_GPN(0)
19907 +#define GTA03_GPIO_KEY_MINUS           S3C64XX_GPN(1)
19908 +#define GTA03_GPIO_KEY_PLUS            S3C64XX_GPN(2)
19909 +#define GTA03_GPIO_PWR_IND             S3C64XX_GPN(3)
19910 +#define GTA03_GPIO_PWR_IRQ             S3C64XX_GPN(4)
19911 +#define GTA03_GPIO_TOUCH               S3C64XX_GPN(5)
19912 +#define GTA03_GPIO_JACK_INSERT         S3C64XX_GPN(6)
19913 +#define GTA03_GPIO_GPS_INT             S3C64XX_GPN(7)
19914 +#define GTA03_GPIO_HOLD                        S3C64XX_GPN(8)
19915 +#define GTA03_GPIO_WLAN_WAKEUP         S3C64XX_GPN(9)
19916 +#define GTA03_GPIO_ACCEL_INT2          S3C64XX_GPN(10)
19917 +#define GTA03_GPIO_IO1                 S3C64XX_GPN(11)
19918 +#define GTA03_GPIO_NONKEYWAKE          S3C64XX_GPN(12)
19919 +
19920 +#define GTA03_GPIO_N_MODEM_RESET       S3C64XX_GPO(1)
19921 +
19922 +#define GTA03_IRQ_GSENSOR_1    S3C_EINT(0)
19923 +#define GTA03_IRQ_KEY_MINUS    S3C_EINT(1)
19924 +#define GTA03_IRQ_KEY_PLUS     S3C_EINT(2)
19925 +#define GTA03_IRQ_PWR_IND      S3C_EINT(3)
19926 +#define GTA03_IRQ_PMU          S3C_EINT(4)
19927 +#define GTA03_IRQ_TOUCH                S3C_EINT(5)
19928 +#define GTA03_IRQ_JACK_INSERT  S3C_EINT(6)
19929 +#define GTA03_IRQ_GPS_INT      S3C_EINT(7)
19930 +#define GTA03_IRQ_NHOLD                S3C_EINT(8)
19931 +#define GTA03_IRQ_WLAN_WAKEUP  S3C_EINT(9)
19932 +#define GTA03_IRQ_GSENSOR_2    S3C_EINT(10)
19933 +#define GTA03_IRQ_IO1          S3C_EINT(11)
19934 +#define GTA03_IRQ_NONKEYWAKE   S3C_EINT(12)
19935 +
19936 +#endif /* _OM_GTA03_H */
19937 --- /dev/null
19938 +++ b/arch/arm/mach-s3c6410/Kconfig
19939 @@ -0,0 +1,80 @@
19940 +# arch/arm/mach-s3c6410/Kconfig
19941 +#
19942 +# Copyright 2008 Openmoko, Inc.
19943 +# Copyright 2008 Simtec Electronics
19944 +#
19945 +# Licensed under GPLv2
19946 +
19947 +# Configuration options for the S3C6410 CPU
19948 +
19949 +config CPU_S3C6410
19950 +       bool
19951 +       select CPU_S3C6400_INIT
19952 +       select CPU_S3C6400_CLOCK
19953 +       help
19954 +         Enable S3C6410 CPU support
19955 +
19956 +config S3C6410_SETUP_SDHCI
19957 +       bool
19958 +       help
19959 +         Internal helper functions for S3C6410 based SDHCI systems
19960 +
19961 +config MACH_SMDK6410
19962 +       bool "SMDK6410"
19963 +       select CPU_S3C6410
19964 +       select S3C_DEV_HSMMC
19965 +       select S3C_DEV_HSMMC1
19966 +       select S3C_DEV_I2C1
19967 +       select S3C_DEV_FB
19968 +       select S3C6410_SETUP_SDHCI
19969 +       select S3C64XX_SETUP_I2C1
19970 +       select S3C64XX_SETUP_FB_24BPP
19971 +       help
19972 +         Machine support for the Samsung SMDK6410
19973 +
19974 +# At least some of the SMDK6410s were shipped with the card detect
19975 +# for the MMC/SD slots connected to the same input. This means that
19976 +# either the boards need to be altered to have channel0 to an alternate
19977 +# configuration or that only one slot can be used.
19978 +
19979 +choice
19980 +       prompt "SMDK6410 MMC/SD slot setup"
19981 +       depends on MACH_SMDK6410
19982 +
19983 +config SMDK6410_SD_CH0
19984 +       bool "Use channel 0 only"
19985 +       depends on MACH_SMDK6410
19986 +       help
19987 +          Select CON7 (channel 0) as the MMC/SD slot, as
19988 +         at least some SMDK6410 boards come with the
19989 +         resistors fitted so that the card detects for
19990 +         channels 0 and 1 are the same.
19991 +
19992 +config SMDK6410_SD_CH1
19993 +       bool "Use channel 1 only"
19994 +       depends on MACH_SMDK6410
19995 +       help
19996 +          Select CON6 (channel 1) as the MMC/SD slot, as
19997 +         at least some SMDK6410 boards come with the
19998 +         resistors fitted so that the card detects for
19999 +         channels 0 and 1 are the same.
20000 +
20001 +endchoice
20002 +
20003 +config MACH_OPENMOKO_GTA03
20004 +        bool "Openmoko GTA03 Phone"
20005 +       select CPU_S3C6410
20006 +       select S3C_DEV_HSMMC
20007 +       select S3C_DEV_HSMMC1
20008 +       select S3C_DEV_I2C1
20009 +       select S3C6410_SETUP_SDHCI
20010 +       select S3C64XX_SETUP_I2C1
20011 +       select S3C_DEV_FB
20012 +       select S3C64XX_SETUP_FB_24BPP
20013 +#      select SENSORS_PCF50633
20014 +       select POWER_SUPPLY
20015 +#      select GTA02_HDQ
20016 +       select MACH_NEO1973
20017 +       help
20018 +          Machine support for the Openmoko GTA03 Phone
20019 +
20020 --- /dev/null
20021 +++ b/arch/arm/mach-s3c6410/mach-om-gta03.c
20022 @@ -0,0 +1,654 @@
20023 +/* linux/arch/arm/mach-s3c6410/mach-om_gta03.c
20024 + *
20025 + * Copyright 2008 Openmoko, Inc.
20026 + * Andy Green <andy@openmoko.org>
20027 + *
20028 + * based on mach_om_gta03.c which is
20029 + *
20030 + * Copyright 2008 Openmoko, Inc.
20031 + * Copyright 2008 Simtec Electronics
20032 + *     Ben Dooks <ben@simtec.co.uk>
20033 + *     http://armlinux.simtec.co.uk/
20034 + *
20035 + * This program is free software; you can redistribute it and/or modify
20036 + * it under the terms of the GNU General Public License version 2 as
20037 + * published by the Free Software Foundation.
20038 + *
20039 +*/
20040 +
20041 +#include <linux/kernel.h>
20042 +#include <linux/types.h>
20043 +#include <linux/interrupt.h>
20044 +#include <linux/list.h>
20045 +#include <linux/timer.h>
20046 +#include <linux/init.h>
20047 +#include <linux/serial_core.h>
20048 +#include <linux/platform_device.h>
20049 +#include <linux/io.h>
20050 +#include <linux/i2c.h>
20051 +#include <linux/fb.h>
20052 +#include <linux/delay.h>
20053 +#include <linux/lis302dl.h>
20054 +
20055 +#include <video/platform_lcd.h>
20056 +
20057 +#include <asm/mach/arch.h>
20058 +#include <asm/mach/map.h>
20059 +#include <asm/mach/irq.h>
20060 +
20061 +#include <mach/hardware.h>
20062 +#include <mach/map.h>
20063 +#include <mach/regs-fb.h>
20064 +
20065 +#include <asm/irq.h>
20066 +#include <asm/mach-types.h>
20067 +
20068 +#include <plat/regs-serial.h>
20069 +#include <plat/iic.h>
20070 +#include <plat/fb.h>
20071 +#include <plat/gpio-cfg.h>
20072 +#include <plat/pm.h>
20073 +
20074 +#include <plat/s3c6410.h>
20075 +#include <plat/clock.h>
20076 +#include <plat/devs.h>
20077 +#include <plat/cpu.h>
20078 +
20079 +/* #include <plat/udc.h> */
20080 +#include <linux/i2c.h>
20081 +#include <linux/backlight.h>
20082 +#include <linux/regulator/machine.h>
20083 +
20084 +#include <mach/om-gta03.h>
20085 +
20086 +#include <linux/mfd/pcf50633/core.h>
20087 +#include <linux/mfd/pcf50633/mbc.h>
20088 +#include <linux/mfd/pcf50633/adc.h>
20089 +#include <linux/mfd/pcf50633/gpio.h>
20090 +#include <linux/mfd/pcf50633/led.h>
20091 +
20092 +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
20093 +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
20094 +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
20095 +
20096 +static struct s3c2410_uartcfg om_gta03_uartcfgs[] __initdata = {
20097 +       [0] = {
20098 +               .hwport      = 0,
20099 +               .flags       = 0,
20100 +               .ucon        = 0x3c5,
20101 +               .ulcon       = 0x03,
20102 +               .ufcon       = 0x51,
20103 +       },
20104 +       [1] = {
20105 +               .hwport      = 1,
20106 +               .flags       = 0,
20107 +               .ucon        = 0x3c5,
20108 +               .ulcon       = 0x03,
20109 +               .ufcon       = 0x51,
20110 +       },
20111 +       [2] = {
20112 +               .hwport      = 2,
20113 +               .flags       = 0,
20114 +               .ucon        = 0x3c5,
20115 +               .ulcon       = 0x03,
20116 +               .ufcon       = 0x51,
20117 +       },
20118 +       [3] = {
20119 +               .hwport      = 3,
20120 +               .flags       = 0,
20121 +               .ucon        = 0x3c5,
20122 +               .ulcon       = 0x03,
20123 +               .ufcon       = 0x51,
20124 +       },
20125 +};
20126 +
20127 +
20128 +/*
20129 + * Situation is that Linux SPI can't work in an interrupt context, so we
20130 + * implement our own bitbang here.  Arbitration is needed because not only
20131 + * can this interrupt happen at any time even if foreground wants to use
20132 + * the bitbang API from Linux, but multiple motion sensors can be on the
20133 + * same SPI bus, and multiple interrupts can happen.
20134 + *
20135 + * Foreground / interrupt arbitration is okay because the interrupts are
20136 + * disabled around all the foreground SPI code.
20137 + *
20138 + * Interrupt / Interrupt arbitration is evidently needed, otherwise we
20139 + * lose edge-triggered service after a while due to the two sensors sharing
20140 + * the SPI bus having irqs at the same time eventually.
20141 + *
20142 + * Servicing is typ 75 - 100us at 400MHz.
20143 + */
20144 +
20145 +/* #define DEBUG_SPEW_MS */
20146 +#define MG_PER_SAMPLE 18
20147 +
20148 +struct lis302dl_platform_data lis302_pdata;
20149 +
20150 +/*
20151 + * generic SPI RX and TX bitbang
20152 + * only call with interrupts off!
20153 + */
20154 +
20155 +static void __gta03_lis302dl_bitbang(struct lis302dl_info *lis, u8 *tx,
20156 +                                            int tx_bytes, u8 *rx, int rx_bytes)
20157 +{
20158 +       struct lis302dl_platform_data *pdata = lis->pdata;
20159 +       int n;
20160 +       u8 shifter = 0;
20161 +
20162 +       gpio_direction_output(pdata->pin_chip_select, 1);
20163 +       gpio_direction_output(pdata->pin_clk, 1);
20164 +       gpio_direction_output(pdata->pin_chip_select, 0);
20165 +
20166 +       /* send the register index, r/w and autoinc bits */
20167 +       for (n = 0; n < (tx_bytes << 3); n++) {
20168 +               if (!(n & 7))
20169 +                       shifter = ~tx[n >> 3];
20170 +               gpio_direction_output(pdata->pin_clk, 0);
20171 +               gpio_direction_output(pdata->pin_mosi, !(shifter & 0x80));
20172 +               gpio_direction_output(pdata->pin_clk, 1);
20173 +               shifter <<= 1;
20174 +       }
20175 +
20176 +       for (n = 0; n < (rx_bytes << 3); n++) { /* 8 bits each */
20177 +               gpio_direction_output(pdata->pin_clk, 0);
20178 +               shifter <<= 1;
20179 +               if (gpio_direction_input(pdata->pin_miso))
20180 +                       shifter |= 1;
20181 +               if ((n & 7) == 7)
20182 +                       rx[n >> 3] = shifter;
20183 +               gpio_direction_output(pdata->pin_clk, 1);
20184 +       }
20185 +       gpio_direction_output(pdata->pin_chip_select, 1);
20186 +}
20187 +
20188 +
20189 +static int gta03_lis302dl_bitbang_read_reg(struct lis302dl_info *lis, u8 reg)
20190 +{
20191 +       u8 data = 0xc0 | reg; /* read, autoincrement */
20192 +       unsigned long flags;
20193 +
20194 +       local_irq_save(flags);
20195 +
20196 +       __gta03_lis302dl_bitbang(lis, &data, 1, &data, 1);
20197 +
20198 +       local_irq_restore(flags);
20199 +
20200 +       return data;
20201 +}
20202 +
20203 +static void gta03_lis302dl_bitbang_write_reg(struct lis302dl_info *lis, u8 reg,
20204 +                                                                        u8 val)
20205 +{
20206 +       u8 data[2] = { 0x00 | reg, val }; /* write, no autoincrement */
20207 +       unsigned long flags;
20208 +
20209 +       local_irq_save(flags);
20210 +
20211 +       __gta03_lis302dl_bitbang(lis, &data[0], 2, NULL, 0);
20212 +
20213 +       local_irq_restore(flags);
20214 +
20215 +}
20216 +
20217 +
20218 +void gta03_lis302dl_suspend_io(struct lis302dl_info *lis, int resume)
20219 +{
20220 +       struct lis302dl_platform_data *pdata = lis->pdata;
20221 +
20222 +       if (!resume) {
20223 +                /*
20224 +                * we don't want to power them with a high level
20225 +                * because GSENSOR_3V3 is not up during suspend
20226 +                */
20227 +               gpio_direction_output(pdata->pin_chip_select, 0);
20228 +               gpio_direction_output(pdata->pin_clk, 0);
20229 +               gpio_direction_output(pdata->pin_mosi, 0);
20230 +               s3c_gpio_setpull(pdata->pin_miso, S3C_GPIO_PULL_DOWN);
20231 +
20232 +               return;
20233 +       }
20234 +
20235 +       /* back to normal */
20236 +       gpio_direction_output(pdata->pin_chip_select, 1);
20237 +       gpio_direction_output(pdata->pin_clk, 1);
20238 +       s3c_gpio_setpull(pdata->pin_miso, S3C_GPIO_PULL_NONE);
20239 +
20240 +       s3c_gpio_cfgpin(pdata->pin_chip_select, S3C_GPIO_SFN(1));
20241 +       s3c_gpio_cfgpin(pdata->pin_clk, S3C_GPIO_SFN(1));
20242 +       s3c_gpio_cfgpin(pdata->pin_mosi, S3C_GPIO_SFN(1));
20243 +       s3c_gpio_cfgpin(pdata->pin_miso, S3C_GPIO_SFN(0));
20244 +
20245 +}
20246 +
20247 +struct lis302dl_platform_data lis302_pdata = {
20248 +               .name           = "lis302",
20249 +               .pin_chip_select= S3C64XX_GPC(3), /* NC */
20250 +               .pin_clk        = GTA03_GPIO_ACCEL_CLK,
20251 +               .pin_mosi       = GTA03_GPIO_ACCEL_MOSI,
20252 +               .pin_miso       = GTA03_GPIO_ACCEL_MISO,
20253 +               .interrupt      = GTA03_IRQ_GSENSOR_1,
20254 +               .open_drain     = 0,
20255 +               .lis302dl_bitbang = __gta03_lis302dl_bitbang,
20256 +               .lis302dl_bitbang_reg_read = gta03_lis302dl_bitbang_read_reg,
20257 +               .lis302dl_bitbang_reg_write = gta03_lis302dl_bitbang_write_reg,
20258 +               .lis302dl_suspend_io = gta03_lis302dl_suspend_io,
20259 +};
20260 +
20261 +static struct platform_device s3c_device_spi_acc1 = {
20262 +       .name             = "lis302dl",
20263 +       .id               = 1,
20264 +       .dev = {
20265 +               .platform_data = &lis302_pdata,
20266 +       },
20267 +};
20268 +
20269 +
20270 +
20271 +/* framebuffer and LCD setup. */
20272 +
20273 +/* GPF15 = LCD backlight control
20274 + * GPF13 => Panel power
20275 + * GPN5 = LCD nRESET signal
20276 + * PWM_TOUT1 => backlight brightness
20277 + */
20278 +
20279 +static void om_gta03_lcd_power_set(struct plat_lcd_data *pd,
20280 +                                  unsigned int power)
20281 +{
20282 +
20283 +}
20284 +
20285 +static struct plat_lcd_data om_gta03_lcd_power_data = {
20286 +       .set_power      = om_gta03_lcd_power_set,
20287 +};
20288 +
20289 +static struct platform_device om_gta03_lcd_powerdev = {
20290 +       .name                   = "platform-lcd",
20291 +       .dev.parent             = &s3c_device_fb.dev,
20292 +       .dev.platform_data      = &om_gta03_lcd_power_data,
20293 +};
20294 +
20295 +static struct s3c_fb_pd_win om_gta03_fb_win0 = {
20296 +       /* this is to ensure we use win0 */
20297 +       .win_mode       = {
20298 +               .pixclock       = 40816,
20299 +               .left_margin    = 8,
20300 +               .right_margin   = 16,
20301 +               .upper_margin   = 2,
20302 +               .lower_margin   = 16,
20303 +               .hsync_len      = 8,
20304 +               .vsync_len      = 2,
20305 +               .xres           = 640,
20306 +               .yres           = 480,
20307 +       },
20308 +       .max_bpp        = 32,
20309 +       .default_bpp    = 16,
20310 +};
20311 +
20312 +static struct s3c_fb_platdata om_gta03_lcd_pdata __initdata = {
20313 +       .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
20314 +       .win[0]         = &om_gta03_fb_win0,
20315 +       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
20316 +       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
20317 +};
20318 +
20319 +
20320 +struct map_desc om_gta03_6410_iodesc[] = {};
20321 +
20322 +static struct resource om_gta03_button_resources[] = {
20323 +       [0] = {
20324 +               .start = 0,
20325 +               .end   = 0,
20326 +       },
20327 +       [1] = {
20328 +               .start = GTA03_GPIO_HOLD,
20329 +               .end   = GTA03_GPIO_HOLD,
20330 +       },
20331 +       [2] = {
20332 +               .start = GTA03_GPIO_JACK_INSERT,
20333 +               .end   = GTA03_GPIO_JACK_INSERT,
20334 +       },
20335 +       [3] = {
20336 +               .start = GTA03_GPIO_KEY_PLUS,
20337 +               .end   = GTA03_GPIO_KEY_PLUS,
20338 +       },
20339 +       [4] = {
20340 +               .start = GTA03_GPIO_KEY_MINUS,
20341 +               .end   = GTA03_GPIO_KEY_MINUS,
20342 +       },
20343 +};
20344 +
20345 +static struct platform_device om_gta03_button_dev = {
20346 +       .name           = "neo1973-button",
20347 +       .num_resources  = ARRAY_SIZE(om_gta03_button_resources),
20348 +       .resource       = om_gta03_button_resources,
20349 +};
20350 +
20351 +
20352 +/********************** PMU ***************************/
20353 +/*
20354 + * GTA03 PMU Mapping info
20355 + *
20356 + *  name  maxcurr  default    Nom   consumers
20357 + *
20358 + *  AUTO   1100mA  ON  3.3V   3.3V  Main 3.3V rail
20359 + *  DOWN1   500mA  ON  1.2V   1.2V  CPU VddARM, VddINT, VddMPLL, VddOTGI
20360 + *  DOWN2   500mA  ON  1.8V   1.8V  CPU VddAlive via LDO, Memories, WLAN
20361 + *  LED      25mA  OFF        18V   Backlight
20362 + *  HCLDO   200mA  OFF        2.8V  Camera 2V8
20363 + *  LDO1     50mA  ON  3.3V   3.3V  Accel
20364 + *  LDO2     50mA  OFF        1.5V  Camera 1V5
20365 + *  LDO3     50mA  OFF        3.3V  CODEC 3.3V
20366 + *  LDO4    150mA  ON  2.8V   2.7V  uSD power
20367 + *  LDO5    150mA  OFF        3.0V  GPS 3V
20368 + *  LDO6     50mA  ON  3.0V   3.0V  LCM 3V
20369 + *
20370 + */
20371 +
20372 +
20373 +/* PMU driver info */
20374 +
20375 +
20376 +static struct regulator_consumer_supply ldo4_consumers[] = {
20377 +       {
20378 +               .dev = &s3c_device_hsmmc0.dev,
20379 +               .supply = "SD_3V",
20380 +       },
20381 +};
20382 +
20383 +static struct platform_device om_gta03_features_dev = {
20384 +       .name           = "om-gta03",
20385 +};
20386 +
20387 +static struct regulator_consumer_supply ldo5_consumers[] = {
20388 +       {
20389 +               .dev = &om_gta03_features_dev.dev,
20390 +               .supply = "RF_3V",
20391 +       },
20392 +};
20393 +
20394 +
20395 +static void om_gta03_pmu_event_callback(struct pcf50633 *pcf, int irq)
20396 +{
20397 +#if 0
20398 +       if (irq == PCF50633_IRQ_USBINS) {
20399 +               schedule_delayed_work(&gta02_charger_work,
20400 +                               GTA02_CHARGER_CONFIGURE_TIMEOUT);
20401 +               return;
20402 +       } else if (irq == PCF50633_IRQ_USBREM) {
20403 +               cancel_delayed_work_sync(&gta02_charger_work);
20404 +               pcf50633_mbc_usb_curlim_set(pcf, 0);
20405 +               gta02_usb_vbus_draw = 0;
20406 +       }
20407 +
20408 +       bq27000_charging_state_change(&bq27000_battery_device);
20409 +#endif
20410 +}
20411 +
20412 +
20413 +static void om_gta03_pcf50633_attach_child_devices(struct pcf50633 *pcf);
20414 +static void om_gta03_pmu_regulator_registered(struct pcf50633 *pcf, int id);
20415 +
20416 +struct pcf50633_platform_data om_gta03_pcf_pdata = {
20417 +
20418 +       .resumers = {
20419 +               [0] = PCF50633_INT1_USBINS |
20420 +                     PCF50633_INT1_USBREM |
20421 +                     PCF50633_INT1_ALARM,
20422 +               [1] = PCF50633_INT2_ONKEYF,
20423 +               [2] = PCF50633_INT3_ONKEY1S
20424 +       },
20425 +
20426 +       .reg_init_data = {
20427 +               /* GTA03: Main 3.3V rail */
20428 +               [PCF50633_REGULATOR_AUTO] = {
20429 +                       .constraints = {
20430 +                               .min_uV = 3300000,
20431 +                               .max_uV = 3300000,
20432 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20433 +                               .apply_uV = 1,
20434 +                               .state_mem = {
20435 +                                       .enabled = 1,
20436 +                               },
20437 +                       },
20438 +                       .num_consumer_supplies = 0,
20439 +               },
20440 +               /* GTA03: CPU core power */
20441 +               [PCF50633_REGULATOR_DOWN1] = {
20442 +                       .constraints = {
20443 +                               .min_uV = 900000,
20444 +                               .max_uV = 1200000,
20445 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20446 +                               .apply_uV = 1,
20447 +                       },
20448 +                       .num_consumer_supplies = 0,
20449 +               },
20450 +               /* GTA03: Memories */
20451 +               [PCF50633_REGULATOR_DOWN2] = {
20452 +                       .constraints = {
20453 +                               .min_uV = 1800000,
20454 +                               .max_uV = 1800000,
20455 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20456 +                               .apply_uV = 1,
20457 +                               .state_mem = {
20458 +                                       .enabled = 1,
20459 +                               },
20460 +                       },
20461 +                       .num_consumer_supplies = 0,
20462 +               },
20463 +               /* GTA03: Camera 2V8 */
20464 +               [PCF50633_REGULATOR_HCLDO] = {
20465 +                       .constraints = {
20466 +                               .min_uV = 2800000,
20467 +                               .max_uV = 2800000,
20468 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20469 +                       },
20470 +                       .num_consumer_supplies = 0,
20471 +/*                     .consumer_supplies = hcldo_consumers, */
20472 +               },
20473 +
20474 +               /* GTA03: Accel 3V3 */
20475 +               [PCF50633_REGULATOR_LDO1] = {
20476 +                       .constraints = {
20477 +                               .min_uV = 3300000,
20478 +                               .max_uV = 3300000,
20479 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20480 +                               .apply_uV = 1,
20481 +                       },
20482 +                       .num_consumer_supplies = 0,
20483 +               },
20484 +               /* GTA03: Camera 1V5 */
20485 +               [PCF50633_REGULATOR_LDO2] = {
20486 +                       .constraints = {
20487 +                               .min_uV = 1500000,
20488 +                               .max_uV = 1500000,
20489 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20490 +                               .apply_uV = 1,
20491 +                       },
20492 +                       .num_consumer_supplies = 0,
20493 +               },
20494 +               /* GTA03: Codec 3.3V */
20495 +               [PCF50633_REGULATOR_LDO3] = {
20496 +                       .constraints = {
20497 +                               .min_uV = 3300000,
20498 +                               .max_uV = 3300000,
20499 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20500 +                               .apply_uV = 1,
20501 +                       },
20502 +                       .num_consumer_supplies = 0,
20503 +               },
20504 +               /* GTA03: uSD Power */
20505 +               [PCF50633_REGULATOR_LDO4] = {
20506 +                       .constraints = {
20507 +                               .min_uV = 3000000,
20508 +                               .max_uV = 3000000,
20509 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20510 +                               .apply_uV = 1,
20511 +                       },
20512 +                       .num_consumer_supplies = 1,
20513 +                       .consumer_supplies = ldo4_consumers,
20514 +               },
20515 +               /* GTA03: GPS 3V */
20516 +               [PCF50633_REGULATOR_LDO5] = {
20517 +                       .constraints = {
20518 +                               .min_uV = 3000000,
20519 +                               .max_uV = 3000000,
20520 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20521 +                               .apply_uV = 1,
20522 +                       },
20523 +                       .num_consumer_supplies = 1,
20524 +                       .consumer_supplies = ldo5_consumers,
20525 +               },
20526 +               /* GTA03: LCM 3V */
20527 +               [PCF50633_REGULATOR_LDO6] = {
20528 +                       .constraints = {
20529 +                               .min_uV = 3000000,
20530 +                               .max_uV = 3000000,
20531 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20532 +                               .state_mem = {
20533 +                                       .enabled = 1,
20534 +                               },
20535 +                       },
20536 +                       .num_consumer_supplies = 0,
20537 +               },
20538 +               /* power for memories in suspend */
20539 +               [PCF50633_REGULATOR_MEMLDO] = {
20540 +                       .constraints = {
20541 +                               .min_uV = 1800000,
20542 +                               .max_uV = 1800000,
20543 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20544 +                               .state_mem = {
20545 +                                       .enabled = 1,
20546 +                               },
20547 +                       },
20548 +                       .num_consumer_supplies = 0,
20549 +               },
20550 +
20551 +       },
20552 +       .probe_done = om_gta03_pcf50633_attach_child_devices,
20553 +       .regulator_registered = om_gta03_pmu_regulator_registered,
20554 +       .mbc_event_callback = om_gta03_pmu_event_callback,
20555 +};
20556 +
20557 +
20558 +static struct i2c_board_info om_gta03_i2c_devs[] __initdata = {
20559 +       {
20560 +               I2C_BOARD_INFO("pcf50633", 0x73),
20561 +               .irq = GTA03_IRQ_PMU,
20562 +               .platform_data = &om_gta03_pcf_pdata,
20563 +       },
20564 +       {
20565 +               I2C_BOARD_INFO("pcap7200", 0x0a),
20566 +               .irq = GTA03_IRQ_TOUCH,
20567 +       },
20568 +
20569 +};
20570 +
20571 +
20572 +static struct platform_device *om_gta03_devices[] __initdata = {
20573 +       &s3c_device_fb,
20574 +       &s3c_device_i2c0,
20575 +       &s3c_device_hsmmc1, /* SDIO to WLAN */
20576 +};
20577 +
20578 +
20579 +static void om_gta03_pmu_regulator_registered(struct pcf50633 *pcf, int id)
20580 +{
20581 +       struct platform_device *regulator, *pdev;
20582 +
20583 +       regulator = pcf->pmic.pdev[id];
20584 +
20585 +       switch(id) {
20586 +               case PCF50633_REGULATOR_LDO4:
20587 +                       pdev = &s3c_device_hsmmc0;
20588 +                       break;
20589 +               case PCF50633_REGULATOR_LDO5: /* GPS regulator */
20590 +                       pdev = &om_gta03_features_dev;
20591 +                       break;
20592 +               case PCF50633_REGULATOR_LDO6:
20593 +                       pdev = &om_gta03_lcd_powerdev;
20594 +                       break;
20595 +               default:
20596 +                       return;
20597 +       }
20598 +
20599 +       pdev->dev.parent = &regulator->dev;
20600 +       platform_device_register(pdev);
20601 +}
20602 +
20603 +static struct platform_device *om_gta03_devices_pmu_children[] = {
20604 +       &om_gta03_button_dev,
20605 +       &s3c_device_spi_acc1, /* relies on PMU reg for power */
20606 +};
20607 +
20608 +/* this is called when pc50633 is probed, unfortunately quite late in the
20609 + * day since it is an I2C bus device.  Here we can belatedly define some
20610 + * platform devices with the advantage that we can mark the pcf50633 as the
20611 + * parent.  This makes them get suspended and resumed with their parent
20612 + * the pcf50633 still around.
20613 + */
20614 +
20615 +static void om_gta03_pcf50633_attach_child_devices(struct pcf50633 *pcf)
20616 +{
20617 +       int n;
20618 +
20619 +       for (n = 0; n < ARRAY_SIZE(om_gta03_devices_pmu_children); n++)
20620 +               om_gta03_devices_pmu_children[n]->dev.parent = pcf->dev;
20621 +
20622 +       platform_add_devices(om_gta03_devices_pmu_children,
20623 +                                    ARRAY_SIZE(om_gta03_devices_pmu_children));
20624 +
20625 +       /* Switch on backlight. Qi does not do it for us */
20626 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x00);
20627 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 0x01);
20628 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x01);
20629 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDOUT, 0x3f);
20630 +
20631 +}
20632 +
20633 +
20634 +
20635 +extern void s3c64xx_init_io(struct map_desc *, int);
20636 +
20637 +static void __init om_gta03_map_io(void)
20638 +{
20639 +       s3c64xx_init_io(om_gta03_6410_iodesc, ARRAY_SIZE(om_gta03_6410_iodesc));
20640 +       s3c24xx_init_clocks(12000000);
20641 +       s3c24xx_init_uarts(om_gta03_uartcfgs, ARRAY_SIZE(om_gta03_uartcfgs));
20642 +}
20643 +
20644 +static void __init om_gta03_machine_init(void)
20645 +{
20646 +       s3c_pm_init();
20647 +
20648 +       s3c_i2c0_set_platdata(NULL);
20649 +       s3c_fb_set_platdata(&om_gta03_lcd_pdata);
20650 +
20651 +       s3c_gpio_setpull(S3C64XX_GPH(0), S3C_GPIO_PULL_UP);
20652 +       s3c_gpio_setpull(S3C64XX_GPH(1), S3C_GPIO_PULL_UP);
20653 +       s3c_gpio_setpull(S3C64XX_GPH(2), S3C_GPIO_PULL_UP);
20654 +       s3c_gpio_setpull(S3C64XX_GPH(3), S3C_GPIO_PULL_UP);
20655 +       s3c_gpio_setpull(S3C64XX_GPH(4), S3C_GPIO_PULL_UP);
20656 +       s3c_gpio_setpull(S3C64XX_GPH(5), S3C_GPIO_PULL_UP);
20657 +
20658 +
20659 +       i2c_register_board_info(0, om_gta03_i2c_devs,
20660 +                                                ARRAY_SIZE(om_gta03_i2c_devs));
20661 +
20662 +       platform_add_devices(om_gta03_devices, ARRAY_SIZE(om_gta03_devices));
20663 +}
20664 +
20665 +MACHINE_START(OPENMOKO_GTA03, "OM-GTA03")
20666 +       /* Maintainer: Andy Green <andy@openmoko.com> */
20667 +       .phys_io        = S3C_PA_UART & 0xfff00000,
20668 +       .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
20669 +       .boot_params    = S3C64XX_PA_SDRAM + 0x100,
20670 +
20671 +       .init_irq       = s3c6410_init_irq,
20672 +       .map_io         = om_gta03_map_io,
20673 +       .init_machine   = om_gta03_machine_init,
20674 +       .timer          = &s3c24xx_timer,
20675 +MACHINE_END
20676 +
20677 --- /dev/null
20678 +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
20679 @@ -0,0 +1,205 @@
20680 +/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
20681 + *
20682 + * Copyright 2008 Openmoko, Inc.
20683 + * Copyright 2008 Simtec Electronics
20684 + *     Ben Dooks <ben@simtec.co.uk>
20685 + *     http://armlinux.simtec.co.uk/
20686 + *
20687 + * This program is free software; you can redistribute it and/or modify
20688 + * it under the terms of the GNU General Public License version 2 as
20689 + * published by the Free Software Foundation.
20690 + *
20691 +*/
20692 +
20693 +#include <linux/kernel.h>
20694 +#include <linux/types.h>
20695 +#include <linux/interrupt.h>
20696 +#include <linux/list.h>
20697 +#include <linux/timer.h>
20698 +#include <linux/init.h>
20699 +#include <linux/serial_core.h>
20700 +#include <linux/platform_device.h>
20701 +#include <linux/io.h>
20702 +#include <linux/i2c.h>
20703 +#include <linux/fb.h>
20704 +#include <linux/gpio.h>
20705 +#include <linux/delay.h>
20706 +
20707 +#include <video/platform_lcd.h>
20708 +
20709 +#include <asm/mach/arch.h>
20710 +#include <asm/mach/map.h>
20711 +#include <asm/mach/irq.h>
20712 +
20713 +#include <mach/hardware.h>
20714 +#include <mach/regs-fb.h>
20715 +#include <mach/map.h>
20716 +
20717 +#include <asm/irq.h>
20718 +#include <asm/mach-types.h>
20719 +
20720 +#include <plat/regs-serial.h>
20721 +#include <plat/regs-modem.h>
20722 +#include <plat/regs-gpio.h>
20723 +#include <plat/regs-sys.h>
20724 +#include <plat/iic.h>
20725 +#include <plat/fb.h>
20726 +#include <plat/pm.h>
20727 +
20728 +#include <plat/s3c6410.h>
20729 +#include <plat/clock.h>
20730 +#include <plat/devs.h>
20731 +#include <plat/cpu.h>
20732 +
20733 +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
20734 +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
20735 +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
20736 +
20737 +static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
20738 +       [0] = {
20739 +               .hwport      = 0,
20740 +               .flags       = 0,
20741 +               .ucon        = 0x3c5,
20742 +               .ulcon       = 0x03,
20743 +               .ufcon       = 0x51,
20744 +       },
20745 +       [1] = {
20746 +               .hwport      = 1,
20747 +               .flags       = 0,
20748 +               .ucon        = 0x3c5,
20749 +               .ulcon       = 0x03,
20750 +               .ufcon       = 0x51,
20751 +       },
20752 +};
20753 +
20754 +/* framebuffer and LCD setup. */
20755 +
20756 +/* GPF15 = LCD backlight control
20757 + * GPF13 => Panel power
20758 + * GPN5 = LCD nRESET signal
20759 + * PWM_TOUT1 => backlight brightness
20760 + */
20761 +
20762 +static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
20763 +                                  unsigned int power)
20764 +{
20765 +       if (power) {
20766 +               gpio_direction_output(S3C64XX_GPF(13), 1);
20767 +               gpio_direction_output(S3C64XX_GPF(15), 1);
20768 +
20769 +               /* fire nRESET on power up */
20770 +               gpio_direction_output(S3C64XX_GPN(5), 0);
20771 +               msleep(10);
20772 +               gpio_direction_output(S3C64XX_GPN(5), 1);
20773 +               msleep(1);
20774 +       } else {
20775 +               gpio_direction_output(S3C64XX_GPF(15), 0);
20776 +               gpio_direction_output(S3C64XX_GPF(13), 0);
20777 +       }
20778 +}
20779 +
20780 +static struct plat_lcd_data smdk6410_lcd_power_data = {
20781 +       .set_power      = smdk6410_lcd_power_set,
20782 +};
20783 +
20784 +static struct platform_device smdk6410_lcd_powerdev = {
20785 +       .name                   = "platform-lcd",
20786 +       .dev.parent             = &s3c_device_fb.dev,
20787 +       .dev.platform_data      = &smdk6410_lcd_power_data,
20788 +};
20789 +
20790 +static struct s3c_fb_pd_win smdk6410_fb_win0 = {
20791 +       /* this is to ensure we use win0 */
20792 +       .win_mode       = {
20793 +               .pixclock       = 41094,
20794 +               .left_margin    = 8,
20795 +               .right_margin   = 13,
20796 +               .upper_margin   = 7,
20797 +               .lower_margin   = 5,
20798 +               .hsync_len      = 3,
20799 +               .vsync_len      = 1,
20800 +               .xres           = 800,
20801 +               .yres           = 480,
20802 +       },
20803 +       .max_bpp        = 32,
20804 +       .default_bpp    = 16,
20805 +};
20806 +
20807 +/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
20808 +static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
20809 +       .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
20810 +       .win[0]         = &smdk6410_fb_win0,
20811 +       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
20812 +       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
20813 +};
20814 +
20815 +struct map_desc smdk6410_iodesc[] = {};
20816 +
20817 +static struct platform_device *smdk6410_devices[] __initdata = {
20818 +#ifdef CONFIG_SMDK6410_SD_CH0
20819 +       &s3c_device_hsmmc0,
20820 +#endif
20821 +#ifdef CONFIG_SMDK6410_SD_CH1
20822 +       &s3c_device_hsmmc1,
20823 +#endif
20824 +       &s3c_device_i2c0,
20825 +       &s3c_device_i2c1,
20826 +       &s3c_device_fb,
20827 +       &smdk6410_lcd_powerdev,
20828 +};
20829 +
20830 +static struct i2c_board_info i2c_devs0[] __initdata = {
20831 +       { I2C_BOARD_INFO("24c08", 0x50), },
20832 +       { I2C_BOARD_INFO("WM8580", 0X1b), },
20833 +};
20834 +
20835 +static struct i2c_board_info i2c_devs1[] __initdata = {
20836 +       { I2C_BOARD_INFO("24c128", 0x57), },    /* Samsung S524AD0XD1 */
20837 +};
20838 +
20839 +static void __init smdk6410_map_io(void)
20840 +{
20841 +       u32 tmp;
20842 +
20843 +       s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
20844 +       s3c24xx_init_clocks(12000000);
20845 +       s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
20846 +
20847 +       /* set the LCD type */
20848 +
20849 +       tmp = __raw_readl(S3C64XX_SPCON);
20850 +       tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
20851 +       tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
20852 +       __raw_writel(tmp, S3C64XX_SPCON);
20853 +
20854 +       /* remove the lcd bypass */
20855 +       tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
20856 +       tmp &= ~MIFPCON_LCD_BYPASS;
20857 +       __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
20858 +}
20859 +
20860 +static void __init smdk6410_machine_init(void)
20861 +{
20862 +       s3c_pm_init();
20863 +
20864 +       s3c_i2c0_set_platdata(NULL);
20865 +       s3c_i2c1_set_platdata(NULL);
20866 +       s3c_fb_set_platdata(&smdk6410_lcd_pdata);
20867 +
20868 +       i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
20869 +       i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
20870 +
20871 +       platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
20872 +}
20873 +
20874 +MACHINE_START(SMDK6410, "SMDK6410")
20875 +       /* Maintainer: Ben Dooks <ben@fluff.org> */
20876 +       .phys_io        = S3C_PA_UART & 0xfff00000,
20877 +       .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
20878 +       .boot_params    = S3C64XX_PA_SDRAM + 0x100,
20879 +
20880 +       .init_irq       = s3c6410_init_irq,
20881 +       .map_io         = smdk6410_map_io,
20882 +       .init_machine   = smdk6410_machine_init,
20883 +       .timer          = &s3c24xx_timer,
20884 +MACHINE_END
20885 --- /dev/null
20886 +++ b/arch/arm/mach-s3c6410/Makefile
20887 @@ -0,0 +1,26 @@
20888 +# arch/arm/plat-s3c6410/Makefile
20889 +#
20890 +# Copyright 2008 Openmoko, Inc.
20891 +# Copyright 2008 Simtec Electronics
20892 +#
20893 +# Licensed under GPLv2
20894 +
20895 +obj-y                          :=
20896 +obj-m                          :=
20897 +obj-n                          :=
20898 +obj-                           :=
20899 +
20900 +# Core support for S3C6410 system
20901 +
20902 +obj-$(CONFIG_CPU_S3C6410)      += cpu.o
20903 +
20904 +# Helper and device support
20905 +
20906 +obj-$(CONFIG_S3C6410_SETUP_SDHCI)      += setup-sdhci.o
20907 +
20908 +# machine support
20909 +
20910 +obj-$(CONFIG_MACH_SMDK6410)    += mach-smdk6410.o
20911 +obj-$(CONFIG_MACH_OPENMOKO_GTA03)      += mach-om-gta03.o \
20912 +                                          om-gta03-features.o
20913 +
20914 --- /dev/null
20915 +++ b/arch/arm/mach-s3c6410/om-gta03-features.c
20916 @@ -0,0 +1,344 @@
20917 +/*
20918 + * Support for features of Openmoko GTA03
20919 + *
20920 + * (C) 2008 by Openmoko Inc.
20921 + * Author: Andy Green <andy@openmoko.com>
20922 + * All rights reserved.
20923 + *
20924 + * Somewhat based on the GTA01 / 02 neo1973_pm_ stuff mainly by Harald Welte
20925 + *
20926 + * This program is free software; you can redistribute it and/or modify
20927 + * it under the terms of the GNU General Public License version 2 as
20928 + * published by the Free Software Foundation
20929 + *
20930 + */
20931 +
20932 +#include <linux/module.h>
20933 +#include <linux/init.h>
20934 +#include <linux/kernel.h>
20935 +#include <linux/delay.h>
20936 +#include <linux/platform_device.h>
20937 +
20938 +#include <mach/hardware.h>
20939 +#include <mach/om-gta03.h>
20940 +#include <asm/mach-types.h>
20941 +
20942 +#include <linux/regulator/consumer.h>
20943 +#include <linux/mfd/pcf50633/core.h>
20944 +#include <linux/mfd/pcf50633/gpio.h>
20945 +#include <linux/mmc/host.h>
20946 +
20947 +#include <plat/sdhci.h>
20948 +#include <plat/devs.h>
20949 +
20950 +#include <plat/gpio-cfg.h>
20951 +
20952 +enum feature {
20953 +       OM_GTA03_GPS,           /* power to GPS section and LNA */
20954 +       OM_GTA03_WLAN_BT,       /* WLAN and BT Module */
20955 +       OM_GTA03_GSM,           /* GSM module */
20956 +       OM_GTA03_USBHOST,       /* USB Host power generation */
20957 +       OM_GTA03_VIB,           /* Vibrator */
20958 +
20959 +       OM_GTA03_FEATURE_COUNT  /* always last */
20960 +};
20961 +
20962 +
20963 +struct om_gta03_feature_info {
20964 +       const char * name;
20965 +       int depower_on_suspend;
20966 +       int on;
20967 +};
20968 +
20969 +static struct om_gta03_feature_info feature_info[OM_GTA03_FEATURE_COUNT] = {
20970 +       [OM_GTA03_GPS] =        { "gps_power",          1, 0 },
20971 +       [OM_GTA03_WLAN_BT] =    { "wlan_bt_power",      1, 0 },
20972 +       [OM_GTA03_GSM] =        { "gsm_power",          0, 0 },
20973 +       [OM_GTA03_USBHOST] =    { "usbhost_power",      1, 0 },
20974 +       [OM_GTA03_VIB] =        { "vibrator_power",     1, 0 },
20975 +};
20976 +
20977 +static struct regulator *gps_regulator;
20978 +
20979 +
20980 +
20981 +static void om_gta03_features_pwron_set_on(enum feature feature)
20982 +{
20983 +       int gpio;
20984 +
20985 +       switch (feature) {
20986 +       case OM_GTA03_GPS:
20987 +               regulator_enable(gps_regulator);
20988 +               /* enable LNA */
20989 +               gpio_direction_output(GTA03_GPIO_GPS_LNA_EN, 1);
20990 +               break;
20991 +       case OM_GTA03_WLAN_BT:
20992 +
20993 +               for (gpio = S3C64XX_GPH(0); gpio < S3C64XX_GPH(6); gpio++) {
20994 +                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); /* sdio */
20995 +                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
20996 +               }
20997 +               /* assert reset */
20998 +               s3c_gpio_setpull(GTA03_GPIO_WLAN_RESET, S3C_GPIO_PULL_NONE);
20999 +               s3c_gpio_cfgpin(GTA03_GPIO_WLAN_RESET, S3C_GPIO_SFN(1));
21000 +               gpio_direction_output(GTA03_GPIO_WLAN_RESET, 0);
21001 +
21002 +               /* "full power down (active low)" -- deassert it*/
21003 +               gpio_direction_output(GTA03_GPIO_WLAN_PWRDN, 1);
21004 +               s3c_gpio_setpull(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_PULL_NONE);
21005 +               s3c_gpio_cfgpin(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_SFN(1));
21006 +
21007 +               /* enable P-Channel mosfet switch for power */
21008 +               gpio_direction_output(GTA03_GPIO_NWLAN_POWER, 0);
21009 +               s3c_gpio_setpull(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_PULL_NONE);
21010 +               s3c_gpio_cfgpin(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_SFN(1));
21011 +               msleep(50);
21012 +               /* deassert reset */
21013 +               gpio_direction_output(GTA03_GPIO_WLAN_RESET, 1);
21014 +               msleep(1500);
21015 +               sdhci_s3c_force_presence_change(&s3c_device_hsmmc1);
21016 +               break;
21017 +       case OM_GTA03_GSM:
21018 +               /* give power to GSM module */
21019 +               s3c_gpio_setpull(GTA03_GPIO_N_MODEM_RESET, S3C_GPIO_PULL_NONE);
21020 +               s3c_gpio_cfgpin(GTA03_GPIO_N_MODEM_RESET, S3C_GPIO_SFN(1));
21021 +               gpio_direction_output(GTA03_GPIO_N_MODEM_RESET, 0);
21022 +
21023 +               gpio_direction_output(GTA03_GPIO_MODEN_ON, 0);
21024 +               s3c_gpio_setpull(GTA03_GPIO_MODEN_ON, S3C_GPIO_PULL_NONE);
21025 +               s3c_gpio_cfgpin(GTA03_GPIO_MODEN_ON, S3C_GPIO_SFN(1));
21026 +               msleep(1);
21027 +               gpio_direction_output(GTA03_GPIO_N_MODEM_RESET, 1);
21028 +               break;
21029 +       case OM_GTA03_USBHOST:
21030 +               pcf50633_gpio_set(om_gta03_pcf_pdata.pcf, PCF50633_GPO, 1);
21031 +               break;
21032 +       case OM_GTA03_VIB:
21033 +               gpio_direction_output(GTA03_GPIO_VIBRATOR_ON, 1);
21034 +               break;
21035 +       default:
21036 +               break;
21037 +       }
21038 +}
21039 +
21040 +static void om_gta03_features_pwron_set_off(enum feature feature)
21041 +{
21042 +       int gpio;
21043 +
21044 +       switch (feature) {
21045 +       case OM_GTA03_GPS:
21046 +               /* disable LNA */
21047 +               gpio_direction_output(GTA03_GPIO_GPS_LNA_EN, 0);
21048 +               regulator_disable(gps_regulator);
21049 +               break;
21050 +       case OM_GTA03_WLAN_BT:
21051 +               gpio_direction_output(GTA03_GPIO_WLAN_RESET, 0);
21052 +               s3c_gpio_setpull(GTA03_GPIO_WLAN_RESET, S3C_GPIO_PULL_NONE);
21053 +               s3c_gpio_cfgpin(GTA03_GPIO_WLAN_RESET, S3C_GPIO_SFN(1));
21054 +
21055 +               gpio_direction_output(GTA03_GPIO_WLAN_PWRDN, 0);
21056 +               s3c_gpio_setpull(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_PULL_NONE);
21057 +               s3c_gpio_cfgpin(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_SFN(1));
21058 +               msleep(500);
21059 +               /* remove power from WLAN / BT module */
21060 +               gpio_direction_output(GTA03_GPIO_NWLAN_POWER, 1);
21061 +               s3c_gpio_setpull(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_PULL_NONE);
21062 +               s3c_gpio_cfgpin(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_SFN(1));
21063 +
21064 +               sdhci_s3c_force_presence_change(&s3c_device_hsmmc1);
21065 +               for (gpio = S3C64XX_GPH(0); gpio < S3C64XX_GPH(6); gpio++) {
21066 +                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0)); /* input */
21067 +                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_DOWN);
21068 +               }
21069 +               break;
21070 +       case OM_GTA03_GSM:
21071 +               /* remove power from WLAN / BT module */
21072 +               gpio_direction_output(GTA03_GPIO_MODEN_ON, 1);
21073 +               s3c_gpio_setpull(GTA03_GPIO_MODEN_ON, S3C_GPIO_PULL_NONE);
21074 +               s3c_gpio_cfgpin(GTA03_GPIO_MODEN_ON, S3C_GPIO_SFN(1));
21075 +               break;
21076 +       case OM_GTA03_USBHOST:
21077 +               pcf50633_gpio_set(om_gta03_pcf_pdata.pcf, PCF50633_GPO, 0);
21078 +               break;
21079 +       case OM_GTA03_VIB:
21080 +               gpio_direction_output(GTA03_GPIO_VIBRATOR_ON, 0);
21081 +               break;
21082 +       default:
21083 +               break;
21084 +       }
21085 +}
21086 +
21087 +static void om_gta03_features_pwron_set(enum feature feature, int on)
21088 +{
21089 +       if ((on) && (!feature_info[feature].on))
21090 +               om_gta03_features_pwron_set_on(feature);
21091 +       else
21092 +               if ((!on) && (feature_info[feature].on))
21093 +                       om_gta03_features_pwron_set_off(feature);
21094 +}
21095 +
21096 +static ssize_t om_gta03_feature_read(struct device *dev,
21097 +                                      struct device_attribute *attr, char *buf)
21098 +{
21099 +       int on;
21100 +       int feature = 0;
21101 +       int hit = 0;
21102 +
21103 +       while (!hit && feature < OM_GTA03_FEATURE_COUNT) {
21104 +               if (!strcmp(attr->attr.name, feature_info[feature].name))
21105 +                       hit = 1;
21106 +               else
21107 +                       feature++;
21108 +       }
21109 +
21110 +       if (!hit)
21111 +               return -EINVAL;
21112 +
21113 +       switch (feature) {
21114 +       case OM_GTA03_GPS:
21115 +               on = regulator_is_enabled(gps_regulator);
21116 +               break;
21117 +       case OM_GTA03_USBHOST:
21118 +               on = pcf50633_gpio_get(om_gta03_pcf_pdata.pcf, PCF50633_GPO);
21119 +               break;
21120 +       default:
21121 +               on = feature_info[feature].on;
21122 +       }
21123 +
21124 +       *buf++ = '0' + on;
21125 +       *buf++='\n';
21126 +       *buf = '\0';
21127 +
21128 +       return 3;
21129 +}
21130 +
21131 +static ssize_t om_gta03_feature_write(struct device *dev,
21132 +                                       struct device_attribute *attr,
21133 +                                       const char *buf, size_t count)
21134 +{
21135 +       int on = !!simple_strtoul(buf, NULL, 10);
21136 +       int feature = 0;
21137 +       int hit = 0;
21138 +
21139 +       while (!hit && feature < OM_GTA03_FEATURE_COUNT) {
21140 +               if (!strcmp(attr->attr.name, feature_info[feature].name))
21141 +                       hit = 1;
21142 +               else
21143 +                       feature++;
21144 +       }
21145 +
21146 +       if (!hit)
21147 +               return -EINVAL;
21148 +
21149 +       om_gta03_features_pwron_set(feature, on);
21150 +       feature_info[feature].on = on;
21151 +
21152 +       return count;
21153 +}
21154 +
21155 +
21156 +static DEVICE_ATTR(gps_power, 0644, om_gta03_feature_read,
21157 +                                                       om_gta03_feature_write);
21158 +
21159 +static DEVICE_ATTR(wlan_bt_power, 0644, om_gta03_feature_read,
21160 +                                                       om_gta03_feature_write);
21161 +
21162 +static DEVICE_ATTR(gsm_power, 0644, om_gta03_feature_read,
21163 +                                                       om_gta03_feature_write);
21164 +
21165 +static DEVICE_ATTR(usbhost_power, 0644, om_gta03_feature_read,
21166 +                                                       om_gta03_feature_write);
21167 +
21168 +static DEVICE_ATTR(vibrator_power, 0644, om_gta03_feature_read,
21169 +                                                       om_gta03_feature_write);
21170 +
21171 +
21172 +static struct attribute *om_gta03_features_sysfs_entries[] = {
21173 +       &dev_attr_gps_power.attr,
21174 +       &dev_attr_wlan_bt_power.attr,
21175 +       &dev_attr_gsm_power.attr,
21176 +       &dev_attr_usbhost_power.attr,
21177 +       &dev_attr_vibrator_power.attr,
21178 +       NULL
21179 +};
21180 +
21181 +
21182 +static struct attribute_group om_gta03_features_attr_group = {
21183 +       .name   = NULL,
21184 +       .attrs  = om_gta03_features_sysfs_entries,
21185 +};
21186 +
21187 +static int __init om_gta03_features_probe(struct platform_device *pdev)
21188 +{
21189 +       gps_regulator = regulator_get(&pdev->dev, "RF_3V");
21190 +       dev_info(&pdev->dev, "starting\n");
21191 +
21192 +       return sysfs_create_group(&pdev->dev.kobj,
21193 +                                                &om_gta03_features_attr_group);
21194 +}
21195 +
21196 +static int om_gta03_features_remove(struct platform_device *pdev)
21197 +{
21198 +
21199 +       regulator_put(gps_regulator);
21200 +       sysfs_remove_group(&pdev->dev.kobj, &om_gta03_features_attr_group);
21201 +
21202 +       return 0;
21203 +}
21204 +
21205 +
21206 +#ifdef CONFIG_PM
21207 +static int om_gta03_features_suspend(struct platform_device *pdev,
21208 +                                    pm_message_t state)
21209 +{
21210 +       int feature;
21211 +
21212 +       for (feature = 0; feature < OM_GTA03_FEATURE_COUNT; feature++)
21213 +               if (feature_info[feature].depower_on_suspend)
21214 +                       om_gta03_features_pwron_set_off(feature);
21215 +
21216 +       return 0;
21217 +}
21218 +
21219 +static int om_gta03_features_resume(struct platform_device *pdev)
21220 +{
21221 +       int feature;
21222 +
21223 +       for (feature = 0; feature < OM_GTA03_FEATURE_COUNT; feature++)
21224 +               if (feature_info[feature].depower_on_suspend)
21225 +                       if (feature_info[feature].on)
21226 +                               om_gta03_features_pwron_set_on(feature);
21227 +
21228 +       return 0;
21229 +}
21230 +#else
21231 +#define om_gta03_features_suspend      NULL
21232 +#define om_gta03_features_resume       NULL
21233 +#endif
21234 +
21235 +static struct platform_driver om_gta03_features_driver = {
21236 +       .probe          = om_gta03_features_probe,
21237 +       .remove         = om_gta03_features_remove,
21238 +       .suspend        = om_gta03_features_suspend,
21239 +       .resume         = om_gta03_features_resume,
21240 +       .driver         = {
21241 +               .name           = "om-gta03",
21242 +       },
21243 +};
21244 +
21245 +static int __devinit om_gta03_features_init(void)
21246 +{
21247 +       return platform_driver_register(&om_gta03_features_driver);
21248 +}
21249 +
21250 +static void om_gta03_features_exit(void)
21251 +{
21252 +       platform_driver_unregister(&om_gta03_features_driver);
21253 +}
21254 +
21255 +module_init(om_gta03_features_init);
21256 +module_exit(om_gta03_features_exit);
21257 +
21258 +MODULE_LICENSE("GPL");
21259 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
21260 +MODULE_DESCRIPTION("Openmoko GTA03 Feature Driver");
21261 --- /dev/null
21262 +++ b/arch/arm/mach-s3c6410/setup-sdhci.c
21263 @@ -0,0 +1,103 @@
21264 +/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
21265 + *
21266 + * Copyright 2008 Simtec Electronics
21267 + * Copyright 2008 Simtec Electronics
21268 + *     Ben Dooks <ben@simtec.co.uk>
21269 + *     http://armlinux.simtec.co.uk/
21270 + *
21271 + * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
21272 + *
21273 + * This program is free software; you can redistribute it and/or modify
21274 + * it under the terms of the GNU General Public License version 2 as
21275 + * published by the Free Software Foundation.
21276 +*/
21277 +
21278 +#include <linux/kernel.h>
21279 +#include <linux/types.h>
21280 +#include <linux/interrupt.h>
21281 +#include <linux/platform_device.h>
21282 +#include <linux/io.h>
21283 +
21284 +#include <linux/mmc/card.h>
21285 +#include <linux/mmc/host.h>
21286 +
21287 +#include <mach/gpio.h>
21288 +#include <plat/gpio-cfg.h>
21289 +#include <plat/regs-sdhci.h>
21290 +#include <plat/sdhci.h>
21291 +
21292 +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
21293 +
21294 +char *s3c6410_hsmmc_clksrcs[4] = {
21295 +       [0] = "hsmmc",
21296 +       [1] = "hsmmc",
21297 +       [2] = "mmc_bus",
21298 +       /* [3] = "48m", - note not succesfully used yet */
21299 +};
21300 +
21301 +void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
21302 +{
21303 +       unsigned int gpio;
21304 +       unsigned int end;
21305 +
21306 +       end = S3C64XX_GPG(2 + width);
21307 +
21308 +       /* Set all the necessary GPG pins to special-function 0 */
21309 +       for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
21310 +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
21311 +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
21312 +       }
21313 +
21314 +       /* FIXME this needs defining in machine as to if we even have CD */
21315 +       s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
21316 +       s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
21317 +}
21318 +
21319 +void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
21320 +                                   void __iomem *r,
21321 +                                   struct mmc_ios *ios,
21322 +                                   struct mmc_card *card)
21323 +{
21324 +       u32 ctrl2, ctrl3;
21325 +
21326 +       /* don't need to alter anything acording to card-type */
21327 +
21328 +       writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
21329 +
21330 +       ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
21331 +       ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
21332 +       ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
21333 +                 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
21334 +                 S3C_SDHCI_CTRL2_ENFBCLKRX |
21335 +                 S3C_SDHCI_CTRL2_DFCNT_NONE |
21336 +                 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
21337 +
21338 +       if (ios->clock < 25 * 1000000)
21339 +               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
21340 +                        S3C_SDHCI_CTRL3_FCSEL2 |
21341 +                        S3C_SDHCI_CTRL3_FCSEL1 |
21342 +                        S3C_SDHCI_CTRL3_FCSEL0);
21343 +       else
21344 +               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
21345 +
21346 +       printk(KERN_INFO "%s: %p CTRL 2=%08x, 3=%08x\n", __func__, r, ctrl2, ctrl3);
21347 +       writel(ctrl2, r + S3C_SDHCI_CONTROL2);
21348 +       writel(ctrl3, r + S3C_SDHCI_CONTROL3);
21349 +}
21350 +
21351 +void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
21352 +{
21353 +       unsigned int gpio;
21354 +       unsigned int end;
21355 +
21356 +       end = S3C64XX_GPH(2 + width);
21357 +
21358 +       /* Set all the necessary GPG pins to special-function 0 */
21359 +       for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
21360 +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
21361 +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
21362 +       }
21363 +
21364 +//     s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
21365 +//     s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
21366 +}
21367 --- a/arch/arm/Makefile
21368 +++ b/arch/arm/Makefile
21369 @@ -121,7 +121,10 @@ endif
21370   machine-$(CONFIG_ARCH_OMAP3)     := omap2
21371      plat-$(CONFIG_ARCH_OMAP)      := omap
21372   machine-$(CONFIG_ARCH_S3C2410)           := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
21373 + machine-$(CONFIG_ARCH_S3C24A0)           := s3c24a0
21374      plat-$(CONFIG_PLAT_S3C24XX)           := s3c24xx s3c
21375 + machine-$(CONFIG_ARCH_S3C64XX)           := s3c6400 s3c6410
21376 +    plat-$(CONFIG_PLAT_S3C64XX)           := s3c64xx s3c
21377   machine-$(CONFIG_ARCH_LH7A40X)           := lh7a40x
21378   machine-$(CONFIG_ARCH_VERSATILE)  := versatile
21379   machine-$(CONFIG_ARCH_IMX)       := imx
21380 --- a/arch/arm/mm/Kconfig
21381 +++ b/arch/arm/mm/Kconfig
21382 @@ -183,14 +183,14 @@ config CPU_ARM926T
21383         depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \
21384                 MACH_VERSATILE_AB || ARCH_OMAP730 || \
21385                 ARCH_OMAP16XX || MACH_REALVIEW_EB || \
21386 -               ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
21387 +               ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_S3C24A0 || \
21388                 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
21389                 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
21390                 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
21391                 ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
21392         default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \
21393                 ARCH_OMAP730 || ARCH_OMAP16XX || \
21394 -               ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
21395 +               ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_S3C24A0 || \
21396                 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
21397                 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
21398                 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
21399 @@ -400,9 +400,10 @@ config CPU_FEROCEON_OLD_ID
21400  # ARMv6
21401  config CPU_V6
21402         bool "Support ARM V6 processor"
21403 -       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
21404 +       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || ARCH_S3C64XX
21405         default y if ARCH_MX3
21406         default y if ARCH_MSM
21407 +       default y if ARCH_S3C64XX
21408         select CPU_32v6
21409         select CPU_ABRT_EV6
21410         select CPU_PABRT_NOIFAR
21411 --- /dev/null
21412 +++ b/arch/arm/plat-s3c/clock.c
21413 @@ -0,0 +1,369 @@
21414 +/* linux/arch/arm/plat-s3c24xx/clock.c
21415 + *
21416 + * Copyright (c) 2004-2005 Simtec Electronics
21417 + *     Ben Dooks <ben@simtec.co.uk>
21418 + *
21419 + * S3C24XX Core clock control support
21420 + *
21421 + * Based on, and code from linux/arch/arm/mach-versatile/clock.c
21422 + **
21423 + **  Copyright (C) 2004 ARM Limited.
21424 + **  Written by Deep Blue Solutions Limited.
21425 + *
21426 + *
21427 + * This program is free software; you can redistribute it and/or modify
21428 + * it under the terms of the GNU General Public License as published by
21429 + * the Free Software Foundation; either version 2 of the License, or
21430 + * (at your option) any later version.
21431 + *
21432 + * This program is distributed in the hope that it will be useful,
21433 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
21434 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21435 + * GNU General Public License for more details.
21436 + *
21437 + * You should have received a copy of the GNU General Public License
21438 + * along with this program; if not, write to the Free Software
21439 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21440 +*/
21441 +
21442 +#include <linux/init.h>
21443 +#include <linux/module.h>
21444 +#include <linux/kernel.h>
21445 +#include <linux/list.h>
21446 +#include <linux/errno.h>
21447 +#include <linux/err.h>
21448 +#include <linux/platform_device.h>
21449 +#include <linux/sysdev.h>
21450 +#include <linux/interrupt.h>
21451 +#include <linux/ioport.h>
21452 +#include <linux/clk.h>
21453 +#include <linux/spinlock.h>
21454 +#include <linux/delay.h>
21455 +#include <linux/io.h>
21456 +
21457 +#include <mach/hardware.h>
21458 +#include <asm/irq.h>
21459 +
21460 +#include <plat/cpu-freq.h>
21461 +
21462 +#include <plat/clock.h>
21463 +#include <plat/cpu.h>
21464 +
21465 +/* clock information */
21466 +
21467 +static LIST_HEAD(clocks);
21468 +
21469 +/* We originally used an mutex here, but some contexts (see resume)
21470 + * are calling functions such as clk_set_parent() with IRQs disabled
21471 + * causing an BUG to be triggered.
21472 + */
21473 +DEFINE_SPINLOCK(clocks_lock);
21474 +
21475 +/* enable and disable calls for use with the clk struct */
21476 +
21477 +static int clk_null_enable(struct clk *clk, int enable)
21478 +{
21479 +       return 0;
21480 +}
21481 +
21482 +/* Clock API calls */
21483 +
21484 +struct clk *clk_get(struct device *dev, const char *id)
21485 +{
21486 +       struct clk *p;
21487 +       struct clk *clk = ERR_PTR(-ENOENT);
21488 +       int idno;
21489 +
21490 +       if (dev == NULL || dev->bus != &platform_bus_type)
21491 +               idno = -1;
21492 +       else
21493 +               idno = to_platform_device(dev)->id;
21494 +
21495 +       spin_lock(&clocks_lock);
21496 +
21497 +       list_for_each_entry(p, &clocks, list) {
21498 +               if (p->id == idno &&
21499 +                   strcmp(id, p->name) == 0 &&
21500 +                   try_module_get(p->owner)) {
21501 +                       clk = p;
21502 +                       break;
21503 +               }
21504 +       }
21505 +
21506 +       /* check for the case where a device was supplied, but the
21507 +        * clock that was being searched for is not device specific */
21508 +
21509 +       if (IS_ERR(clk)) {
21510 +               list_for_each_entry(p, &clocks, list) {
21511 +                       if (p->id == -1 && strcmp(id, p->name) == 0 &&
21512 +                           try_module_get(p->owner)) {
21513 +                               clk = p;
21514 +                               break;
21515 +                       }
21516 +               }
21517 +       }
21518 +
21519 +       spin_unlock(&clocks_lock);
21520 +       return clk;
21521 +}
21522 +
21523 +void clk_put(struct clk *clk)
21524 +{
21525 +       module_put(clk->owner);
21526 +}
21527 +
21528 +int clk_enable(struct clk *clk)
21529 +{
21530 +       if (IS_ERR(clk) || clk == NULL)
21531 +               return -EINVAL;
21532 +
21533 +       clk_enable(clk->parent);
21534 +
21535 +       spin_lock(&clocks_lock);
21536 +
21537 +       if ((clk->usage++) == 0)
21538 +               (clk->enable)(clk, 1);
21539 +
21540 +       spin_unlock(&clocks_lock);
21541 +       return 0;
21542 +}
21543 +
21544 +void clk_disable(struct clk *clk)
21545 +{
21546 +       if (IS_ERR(clk) || clk == NULL)
21547 +               return;
21548 +
21549 +       spin_lock(&clocks_lock);
21550 +
21551 +       if ((--clk->usage) == 0)
21552 +               (clk->enable)(clk, 0);
21553 +
21554 +       spin_unlock(&clocks_lock);
21555 +       clk_disable(clk->parent);
21556 +}
21557 +
21558 +
21559 +unsigned long clk_get_rate(struct clk *clk)
21560 +{
21561 +       if (IS_ERR(clk))
21562 +               return 0;
21563 +
21564 +       if (clk->rate != 0)
21565 +               return clk->rate;
21566 +
21567 +       if (clk->get_rate != NULL)
21568 +               return (clk->get_rate)(clk);
21569 +
21570 +       if (clk->parent != NULL)
21571 +               return clk_get_rate(clk->parent);
21572 +
21573 +       return clk->rate;
21574 +}
21575 +
21576 +long clk_round_rate(struct clk *clk, unsigned long rate)
21577 +{
21578 +       if (!IS_ERR(clk) && clk->round_rate)
21579 +               return (clk->round_rate)(clk, rate);
21580 +
21581 +       return rate;
21582 +}
21583 +
21584 +int clk_set_rate(struct clk *clk, unsigned long rate)
21585 +{
21586 +       int ret;
21587 +
21588 +       if (IS_ERR(clk))
21589 +               return -EINVAL;
21590 +
21591 +       /* We do not default just do a clk->rate = rate as
21592 +        * the clock may have been made this way by choice.
21593 +        */
21594 +
21595 +       WARN_ON(clk->set_rate == NULL);
21596 +
21597 +       if (clk->set_rate == NULL)
21598 +               return -EINVAL;
21599 +
21600 +       spin_lock(&clocks_lock);
21601 +       ret = (clk->set_rate)(clk, rate);
21602 +       spin_unlock(&clocks_lock);
21603 +
21604 +       return ret;
21605 +}
21606 +
21607 +struct clk *clk_get_parent(struct clk *clk)
21608 +{
21609 +       return clk->parent;
21610 +}
21611 +
21612 +int clk_set_parent(struct clk *clk, struct clk *parent)
21613 +{
21614 +       int ret = 0;
21615 +
21616 +       if (IS_ERR(clk))
21617 +               return -EINVAL;
21618 +
21619 +       spin_lock(&clocks_lock);
21620 +
21621 +       if (clk->set_parent)
21622 +               ret = (clk->set_parent)(clk, parent);
21623 +
21624 +       spin_unlock(&clocks_lock);
21625 +
21626 +       return ret;
21627 +}
21628 +
21629 +EXPORT_SYMBOL(clk_get);
21630 +EXPORT_SYMBOL(clk_put);
21631 +EXPORT_SYMBOL(clk_enable);
21632 +EXPORT_SYMBOL(clk_disable);
21633 +EXPORT_SYMBOL(clk_get_rate);
21634 +EXPORT_SYMBOL(clk_round_rate);
21635 +EXPORT_SYMBOL(clk_set_rate);
21636 +EXPORT_SYMBOL(clk_get_parent);
21637 +EXPORT_SYMBOL(clk_set_parent);
21638 +
21639 +/* base clocks */
21640 +
21641 +static int clk_default_setrate(struct clk *clk, unsigned long rate)
21642 +{
21643 +       clk->rate = rate;
21644 +       return 0;
21645 +}
21646 +
21647 +struct clk clk_xtal = {
21648 +       .name           = "xtal",
21649 +       .id             = -1,
21650 +       .rate           = 0,
21651 +       .parent         = NULL,
21652 +       .ctrlbit        = 0,
21653 +};
21654 +
21655 +struct clk clk_ext = {
21656 +       .name           = "ext",
21657 +       .id             = -1,
21658 +};
21659 +
21660 +struct clk clk_epll = {
21661 +       .name           = "epll",
21662 +       .id             = -1,
21663 +};
21664 +
21665 +struct clk clk_mpll = {
21666 +       .name           = "mpll",
21667 +       .id             = -1,
21668 +       .set_rate       = clk_default_setrate,
21669 +};
21670 +
21671 +struct clk clk_upll = {
21672 +       .name           = "upll",
21673 +       .id             = -1,
21674 +       .parent         = NULL,
21675 +       .ctrlbit        = 0,
21676 +};
21677 +
21678 +struct clk clk_f = {
21679 +       .name           = "fclk",
21680 +       .id             = -1,
21681 +       .rate           = 0,
21682 +       .parent         = &clk_mpll,
21683 +       .ctrlbit        = 0,
21684 +       .set_rate       = clk_default_setrate,
21685 +};
21686 +
21687 +struct clk clk_h = {
21688 +       .name           = "hclk",
21689 +       .id             = -1,
21690 +       .rate           = 0,
21691 +       .parent         = NULL,
21692 +       .ctrlbit        = 0,
21693 +       .set_rate       = clk_default_setrate,
21694 +};
21695 +
21696 +struct clk clk_p = {
21697 +       .name           = "pclk",
21698 +       .id             = -1,
21699 +       .rate           = 0,
21700 +       .parent         = NULL,
21701 +       .ctrlbit        = 0,
21702 +       .set_rate       = clk_default_setrate,
21703 +};
21704 +
21705 +struct clk clk_usb_bus = {
21706 +       .name           = "usb-bus",
21707 +       .id             = -1,
21708 +       .rate           = 0,
21709 +       .parent         = &clk_upll,
21710 +};
21711 +
21712 +
21713 +
21714 +struct clk s3c24xx_uclk = {
21715 +       .name           = "uclk",
21716 +       .id             = -1,
21717 +};
21718 +
21719 +/* initialise the clock system */
21720 +
21721 +int s3c24xx_register_clock(struct clk *clk)
21722 +{
21723 +       clk->owner = THIS_MODULE;
21724 +
21725 +       if (clk->enable == NULL)
21726 +               clk->enable = clk_null_enable;
21727 +
21728 +       /* add to the list of available clocks */
21729 +
21730 +       /* Quick check to see if this clock has already been registered. */
21731 +       BUG_ON(clk->list.prev != clk->list.next);
21732 +
21733 +       spin_lock(&clocks_lock);
21734 +       list_add(&clk->list, &clocks);
21735 +       spin_unlock(&clocks_lock);
21736 +
21737 +       return 0;
21738 +}
21739 +
21740 +int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
21741 +{
21742 +       int fails = 0;
21743 +
21744 +       for (; nr_clks > 0; nr_clks--, clks++) {
21745 +               if (s3c24xx_register_clock(*clks) < 0)
21746 +                       fails++;
21747 +       }
21748 +
21749 +       return fails;
21750 +}
21751 +
21752 +/* initalise all the clocks */
21753 +
21754 +int __init s3c24xx_register_baseclocks(unsigned long xtal)
21755 +{
21756 +       printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
21757 +
21758 +       clk_xtal.rate = xtal;
21759 +
21760 +       /* register our clocks */
21761 +
21762 +       if (s3c24xx_register_clock(&clk_xtal) < 0)
21763 +               printk(KERN_ERR "failed to register master xtal\n");
21764 +
21765 +       if (s3c24xx_register_clock(&clk_mpll) < 0)
21766 +               printk(KERN_ERR "failed to register mpll clock\n");
21767 +
21768 +       if (s3c24xx_register_clock(&clk_upll) < 0)
21769 +               printk(KERN_ERR "failed to register upll clock\n");
21770 +
21771 +       if (s3c24xx_register_clock(&clk_f) < 0)
21772 +               printk(KERN_ERR "failed to register cpu fclk\n");
21773 +
21774 +       if (s3c24xx_register_clock(&clk_h) < 0)
21775 +               printk(KERN_ERR "failed to register cpu hclk\n");
21776 +
21777 +       if (s3c24xx_register_clock(&clk_p) < 0)
21778 +               printk(KERN_ERR "failed to register cpu pclk\n");
21779 +
21780 +       return 0;
21781 +}
21782 +
21783 --- /dev/null
21784 +++ b/arch/arm/plat-s3c/dev-fb.c
21785 @@ -0,0 +1,72 @@
21786 +/* linux/arch/arm/plat-s3c/dev-fb.c
21787 + *
21788 + * Copyright 2008 Simtec Electronics
21789 + *     Ben Dooks <ben@simtec.co.uk>
21790 + *     http://armlinux.simtec.co.uk/
21791 + *
21792 + * S3C series device definition for framebuffer device
21793 + *
21794 + * This program is free software; you can redistribute it and/or modify
21795 + * it under the terms of the GNU General Public License version 2 as
21796 + * published by the Free Software Foundation.
21797 +*/
21798 +
21799 +#include <linux/kernel.h>
21800 +#include <linux/string.h>
21801 +#include <linux/platform_device.h>
21802 +#include <linux/fb.h>
21803 +
21804 +#include <mach/map.h>
21805 +#include <mach/regs-fb.h>
21806 +
21807 +#include <plat/fb.h>
21808 +#include <plat/devs.h>
21809 +#include <plat/cpu.h>
21810 +
21811 +static struct resource s3c_fb_resource[] = {
21812 +       [0] = {
21813 +               .start = S3C_PA_FB,
21814 +               .end   = S3C_PA_FB + SZ_16K - 1,
21815 +               .flags = IORESOURCE_MEM,
21816 +       },
21817 +       [1] = {
21818 +               .start = IRQ_LCD_VSYNC,
21819 +               .end   = IRQ_LCD_VSYNC,
21820 +               .flags = IORESOURCE_IRQ,
21821 +       },
21822 +       [2] = {
21823 +               .start = IRQ_LCD_FIFO,
21824 +               .end   = IRQ_LCD_FIFO,
21825 +               .flags = IORESOURCE_IRQ,
21826 +       },
21827 +       [3] = {
21828 +               .start = IRQ_LCD_SYSTEM,
21829 +               .end   = IRQ_LCD_SYSTEM,
21830 +               .flags = IORESOURCE_IRQ,
21831 +       },
21832 +};
21833 +
21834 +struct platform_device s3c_device_fb = {
21835 +       .name             = "s3c-fb",
21836 +       .id               = -1,
21837 +       .num_resources    = ARRAY_SIZE(s3c_fb_resource),
21838 +       .resource         = s3c_fb_resource,
21839 +       .dev.dma_mask     = &s3c_device_fb.dev.coherent_dma_mask,
21840 +       .dev.coherent_dma_mask = 0xffffffffUL,
21841 +};
21842 +
21843 +void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
21844 +{
21845 +       struct s3c_fb_platdata *npd;
21846 +
21847 +       if (!pd) {
21848 +               printk(KERN_ERR "%s: no platform data\n", __func__);
21849 +               return;
21850 +       }
21851 +
21852 +       npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL);
21853 +       if (!npd)
21854 +               printk(KERN_ERR "%s: no memory for platform data\n", __func__);
21855 +
21856 +       s3c_device_fb.dev.platform_data = npd;
21857 +}
21858 --- /dev/null
21859 +++ b/arch/arm/plat-s3c/dev-hsmmc1.c
21860 @@ -0,0 +1,68 @@
21861 +/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
21862 + *
21863 + * Copyright (c) 2008 Simtec Electronics
21864 + *     Ben Dooks <ben@simtec.co.uk>
21865 + *     http://armlinux.simtec.co.uk/
21866 + *
21867 + * S3C series device definition for hsmmc device 1
21868 + *
21869 + * This program is free software; you can redistribute it and/or modify
21870 + * it under the terms of the GNU General Public License version 2 as
21871 + * published by the Free Software Foundation.
21872 +*/
21873 +
21874 +#include <linux/kernel.h>
21875 +#include <linux/platform_device.h>
21876 +#include <linux/mmc/host.h>
21877 +
21878 +#include <mach/map.h>
21879 +#include <plat/sdhci.h>
21880 +#include <plat/devs.h>
21881 +#include <plat/cpu.h>
21882 +
21883 +#define S3C_SZ_HSMMC   (0x1000)
21884 +
21885 +static struct resource s3c_hsmmc1_resource[] = {
21886 +       [0] = {
21887 +               .start = S3C_PA_HSMMC1,
21888 +               .end   = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
21889 +               .flags = IORESOURCE_MEM,
21890 +       },
21891 +       [1] = {
21892 +               .start = IRQ_HSMMC1,
21893 +               .end   = IRQ_HSMMC1,
21894 +               .flags = IORESOURCE_IRQ,
21895 +       }
21896 +};
21897 +
21898 +static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
21899 +
21900 +struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
21901 +       .max_width      = 4,
21902 +       .host_caps      = (MMC_CAP_4_BIT_DATA |
21903 +                          MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
21904 +};
21905 +
21906 +struct platform_device s3c_device_hsmmc1 = {
21907 +       .name           = "s3c-sdhci",
21908 +       .id             = 1,
21909 +       .num_resources  = ARRAY_SIZE(s3c_hsmmc1_resource),
21910 +       .resource       = s3c_hsmmc1_resource,
21911 +       .dev            = {
21912 +               .dma_mask               = &s3c_device_hsmmc1_dmamask,
21913 +               .coherent_dma_mask      = 0xffffffffUL,
21914 +               .platform_data          = &s3c_hsmmc1_def_platdata,
21915 +       },
21916 +};
21917 +
21918 +void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
21919 +{
21920 +       struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
21921 +
21922 +       set->max_width = pd->max_width;
21923 +
21924 +       if (pd->cfg_gpio)
21925 +               set->cfg_gpio = pd->cfg_gpio;
21926 +       if (pd->cfg_card)
21927 +               set->cfg_card = pd->cfg_card;
21928 +}
21929 --- /dev/null
21930 +++ b/arch/arm/plat-s3c/dev-hsmmc.c
21931 @@ -0,0 +1,68 @@
21932 +/* linux/arch/arm/plat-s3c/dev-hsmmc.c
21933 + *
21934 + * Copyright (c) 2008 Simtec Electronics
21935 + *     Ben Dooks <ben@simtec.co.uk>
21936 + *     http://armlinux.simtec.co.uk/
21937 + *
21938 + * S3C series device definition for hsmmc devices
21939 + *
21940 + * This program is free software; you can redistribute it and/or modify
21941 + * it under the terms of the GNU General Public License version 2 as
21942 + * published by the Free Software Foundation.
21943 +*/
21944 +
21945 +#include <linux/kernel.h>
21946 +#include <linux/platform_device.h>
21947 +#include <linux/mmc/host.h>
21948 +
21949 +#include <mach/map.h>
21950 +#include <plat/sdhci.h>
21951 +#include <plat/devs.h>
21952 +#include <plat/cpu.h>
21953 +
21954 +#define S3C_SZ_HSMMC   (0x1000)
21955 +
21956 +static struct resource s3c_hsmmc_resource[] = {
21957 +       [0] = {
21958 +               .start = S3C_PA_HSMMC0,
21959 +               .end   = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
21960 +               .flags = IORESOURCE_MEM,
21961 +       },
21962 +       [1] = {
21963 +               .start = IRQ_HSMMC0,
21964 +               .end   = IRQ_HSMMC0,
21965 +               .flags = IORESOURCE_IRQ,
21966 +       }
21967 +};
21968 +
21969 +static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
21970 +
21971 +struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
21972 +       .max_width      = 4,
21973 +       .host_caps      = (MMC_CAP_4_BIT_DATA |
21974 +                          MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
21975 +};
21976 +
21977 +struct platform_device s3c_device_hsmmc0 = {
21978 +       .name           = "s3c-sdhci",
21979 +       .id             = 0,
21980 +       .num_resources  = ARRAY_SIZE(s3c_hsmmc_resource),
21981 +       .resource       = s3c_hsmmc_resource,
21982 +       .dev            = {
21983 +               .dma_mask               = &s3c_device_hsmmc_dmamask,
21984 +               .coherent_dma_mask      = 0xffffffffUL,
21985 +               .platform_data          = &s3c_hsmmc0_def_platdata,
21986 +       },
21987 +};
21988 +
21989 +void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
21990 +{
21991 +       struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
21992 +
21993 +       set->max_width = pd->max_width;
21994 +
21995 +       if (pd->cfg_gpio)
21996 +               set->cfg_gpio = pd->cfg_gpio;
21997 +       if (pd->cfg_card)
21998 +               set->cfg_card = pd->cfg_card;
21999 +}
22000 --- /dev/null
22001 +++ b/arch/arm/plat-s3c/dev-i2c0.c
22002 @@ -0,0 +1,71 @@
22003 +/* linux/arch/arm/plat-s3c/dev-i2c0.c
22004 + *
22005 + * Copyright 2008 Simtec Electronics
22006 + *     Ben Dooks <ben@simtec.co.uk>
22007 + *     http://armlinux.simtec.co.uk/
22008 + *
22009 + * S3C series device definition for i2c device 0
22010 + *
22011 + * This program is free software; you can redistribute it and/or modify
22012 + * it under the terms of the GNU General Public License version 2 as
22013 + * published by the Free Software Foundation.
22014 +*/
22015 +
22016 +#include <linux/kernel.h>
22017 +#include <linux/string.h>
22018 +#include <linux/platform_device.h>
22019 +
22020 +#include <mach/map.h>
22021 +
22022 +#include <plat/regs-iic.h>
22023 +#include <plat/iic.h>
22024 +#include <plat/devs.h>
22025 +#include <plat/cpu.h>
22026 +
22027 +static struct resource s3c_i2c_resource[] = {
22028 +       [0] = {
22029 +               .start = S3C_PA_IIC,
22030 +               .end   = S3C_PA_IIC + SZ_4K - 1,
22031 +               .flags = IORESOURCE_MEM,
22032 +       },
22033 +       [1] = {
22034 +               .start = IRQ_IIC,
22035 +               .end   = IRQ_IIC,
22036 +               .flags = IORESOURCE_IRQ,
22037 +       },
22038 +};
22039 +
22040 +struct platform_device s3c_device_i2c0 = {
22041 +       .name             = "s3c2410-i2c",
22042 +#ifdef CONFIG_S3C_DEV_I2C1
22043 +       .id               = 0,
22044 +#else
22045 +       .id               = -1,
22046 +#endif
22047 +       .num_resources    = ARRAY_SIZE(s3c_i2c_resource),
22048 +       .resource         = s3c_i2c_resource,
22049 +};
22050 +
22051 +static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
22052 +       .flags          = 0,
22053 +       .slave_addr     = 0x10,
22054 +       .bus_freq       = 100*1000,
22055 +       .max_freq       = 400*1000,
22056 +       .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
22057 +};
22058 +
22059 +void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
22060 +{
22061 +       struct s3c2410_platform_i2c *npd;
22062 +
22063 +       if (!pd)
22064 +               pd = &default_i2c_data0;
22065 +
22066 +       npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
22067 +       if (!npd)
22068 +               printk(KERN_ERR "%s: no memory for platform data\n", __func__);
22069 +       else if (!npd->cfg_gpio)
22070 +               npd->cfg_gpio = s3c_i2c0_cfg_gpio;
22071 +
22072 +       s3c_device_i2c0.dev.platform_data = npd;
22073 +}
22074 --- /dev/null
22075 +++ b/arch/arm/plat-s3c/dev-i2c1.c
22076 @@ -0,0 +1,68 @@
22077 +/* linux/arch/arm/plat-s3c/dev-i2c1.c
22078 + *
22079 + * Copyright 2008 Simtec Electronics
22080 + *     Ben Dooks <ben@simtec.co.uk>
22081 + *     http://armlinux.simtec.co.uk/
22082 + *
22083 + * S3C series device definition for i2c device 1
22084 + *
22085 + * This program is free software; you can redistribute it and/or modify
22086 + * it under the terms of the GNU General Public License version 2 as
22087 + * published by the Free Software Foundation.
22088 +*/
22089 +
22090 +#include <linux/kernel.h>
22091 +#include <linux/string.h>
22092 +#include <linux/platform_device.h>
22093 +
22094 +#include <mach/map.h>
22095 +
22096 +#include <plat/regs-iic.h>
22097 +#include <plat/iic.h>
22098 +#include <plat/devs.h>
22099 +#include <plat/cpu.h>
22100 +
22101 +static struct resource s3c_i2c_resource[] = {
22102 +       [0] = {
22103 +               .start = S3C_PA_IIC1,
22104 +               .end   = S3C_PA_IIC1 + SZ_4K - 1,
22105 +               .flags = IORESOURCE_MEM,
22106 +       },
22107 +       [1] = {
22108 +               .start = IRQ_IIC1,
22109 +               .end   = IRQ_IIC1,
22110 +               .flags = IORESOURCE_IRQ,
22111 +       },
22112 +};
22113 +
22114 +struct platform_device s3c_device_i2c1 = {
22115 +       .name             = "s3c2410-i2c",
22116 +       .id               = 1,
22117 +       .num_resources    = ARRAY_SIZE(s3c_i2c_resource),
22118 +       .resource         = s3c_i2c_resource,
22119 +};
22120 +
22121 +static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
22122 +       .flags          = 0,
22123 +       .bus_num        = 1,
22124 +       .slave_addr     = 0x10,
22125 +       .bus_freq       = 100*1000,
22126 +       .max_freq       = 400*1000,
22127 +       .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
22128 +};
22129 +
22130 +void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
22131 +{
22132 +       struct s3c2410_platform_i2c *npd;
22133 +
22134 +       if (!pd)
22135 +               pd = &default_i2c_data1;
22136 +
22137 +       npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
22138 +       if (!npd)
22139 +               printk(KERN_ERR "%s: no memory for platform data\n", __func__);
22140 +       else if (!npd->cfg_gpio)
22141 +               npd->cfg_gpio = s3c_i2c1_cfg_gpio;
22142 +
22143 +       s3c_device_i2c1.dev.platform_data = npd;
22144 +}
22145 --- /dev/null
22146 +++ b/arch/arm/plat-s3c/gpio.c
22147 @@ -0,0 +1,156 @@
22148 +/* linux/arch/arm/plat-s3c/gpio.c
22149 + *
22150 + * Copyright 2008 Simtec Electronics
22151 + *     Ben Dooks <ben@simtec.co.uk>
22152 + *     http://armlinux.simtec.co.uk/
22153 + *
22154 + * S3C series GPIO core
22155 + *
22156 + * This program is free software; you can redistribute it and/or modify
22157 + * it under the terms of the GNU General Public License version 2 as
22158 + * published by the Free Software Foundation.
22159 +*/
22160 +
22161 +#include <linux/kernel.h>
22162 +#include <linux/init.h>
22163 +#include <linux/io.h>
22164 +#include <linux/gpio.h>
22165 +
22166 +#include <mach/gpio-core.h>
22167 +
22168 +#ifdef CONFIG_S3C_GPIO_TRACK
22169 +struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
22170 +
22171 +static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
22172 +{
22173 +       unsigned int gpn;
22174 +       int i;
22175 +
22176 +       gpn = chip->chip.base;
22177 +       for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
22178 +               BUG_ON(gpn > ARRAY_SIZE(s3c_gpios));
22179 +               s3c_gpios[gpn] = chip;
22180 +       }
22181 +}
22182 +#endif /* CONFIG_S3C_GPIO_TRACK */
22183 +
22184 +/* Default routines for controlling GPIO, based on the original S3C24XX
22185 + * GPIO functions which deal with the case where each gpio bank of the
22186 + * chip is as following:
22187 + *
22188 + * base + 0x00: Control register, 2 bits per gpio
22189 + *             gpio n: 2 bits starting at (2*n)
22190 + *             00 = input, 01 = output, others mean special-function
22191 + * base + 0x04: Data register, 1 bit per gpio
22192 + *             bit n: data bit n
22193 +*/
22194 +
22195 +static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
22196 +{
22197 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
22198 +       void __iomem *base = ourchip->base;
22199 +       unsigned long flags;
22200 +       unsigned long con;
22201 +
22202 +       local_irq_save(flags);
22203 +
22204 +       con = __raw_readl(base + 0x00);
22205 +       con &= ~(3 << (offset * 2));
22206 +
22207 +       __raw_writel(con, base + 0x00);
22208 +
22209 +       local_irq_restore(flags);
22210 +       return 0;
22211 +}
22212 +
22213 +static int s3c_gpiolib_output(struct gpio_chip *chip,
22214 +                             unsigned offset, int value)
22215 +{
22216 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
22217 +       void __iomem *base = ourchip->base;
22218 +       unsigned long flags;
22219 +       unsigned long dat;
22220 +       unsigned long con;
22221 +
22222 +       local_irq_save(flags);
22223 +
22224 +       dat = __raw_readl(base + 0x04);
22225 +       dat &= ~(1 << offset);
22226 +       if (value)
22227 +               dat |= 1 << offset;
22228 +       __raw_writel(dat, base + 0x04);
22229 +
22230 +       con = __raw_readl(base + 0x00);
22231 +       con &= ~(3 << (offset * 2));
22232 +       con |= 1 << (offset * 2);
22233 +
22234 +       __raw_writel(con, base + 0x00);
22235 +       __raw_writel(dat, base + 0x04);
22236 +
22237 +       local_irq_restore(flags);
22238 +       return 0;
22239 +}
22240 +
22241 +static void s3c_gpiolib_set(struct gpio_chip *chip,
22242 +                           unsigned offset, int value)
22243 +{
22244 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
22245 +       void __iomem *base = ourchip->base;
22246 +       unsigned long flags;
22247 +       unsigned long dat;
22248 +
22249 +       local_irq_save(flags);
22250 +
22251 +       dat = __raw_readl(base + 0x04);
22252 +       dat &= ~(1 << offset);
22253 +       if (value)
22254 +               dat |= 1 << offset;
22255 +       __raw_writel(dat, base + 0x04);
22256 +
22257 +       local_irq_restore(flags);
22258 +}
22259 +
22260 +static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
22261 +{
22262 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
22263 +       unsigned long val;
22264 +
22265 +       val = __raw_readl(ourchip->base + 0x04);
22266 +       val >>= offset;
22267 +       val &= 1;
22268 +
22269 +       return val;
22270 +}
22271 +
22272 +__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
22273 +{
22274 +       struct gpio_chip *gc = &chip->chip;
22275 +       int ret;
22276 +
22277 +       BUG_ON(!chip->base);
22278 +       BUG_ON(!gc->label);
22279 +       BUG_ON(!gc->ngpio);
22280 +
22281 +       if (!gc->direction_input)
22282 +               gc->direction_input = s3c_gpiolib_input;
22283 +       if (!gc->direction_output)
22284 +               gc->direction_output = s3c_gpiolib_output;
22285 +       if (!gc->set)
22286 +               gc->set = s3c_gpiolib_set;
22287 +       if (!gc->get)
22288 +               gc->get = s3c_gpiolib_get;
22289 +
22290 +#ifdef CONFIG_PM
22291 +       if (chip->pm != NULL) {
22292 +               if (!chip->pm->save || !chip->pm->resume)
22293 +                       printk(KERN_ERR "gpio: %s has missing PM functions\n",
22294 +                              gc->label);
22295 +       } else
22296 +               printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
22297 +#endif
22298 +
22299 +       /* gpiochip_add() prints own failure message on error. */
22300 +       ret = gpiochip_add(gc);
22301 +       if (ret >= 0)
22302 +               s3c_gpiolib_track(chip);
22303 +}
22304 --- /dev/null
22305 +++ b/arch/arm/plat-s3c/gpio-config.c
22306 @@ -0,0 +1,163 @@
22307 +/* linux/arch/arm/plat-s3c/gpio-config.c
22308 + *
22309 + * Copyright 2008 Openmoko, Inc.
22310 + * Copyright 2008 Simtec Electronics
22311 + *     Ben Dooks <ben@simtec.co.uk>
22312 + *     http://armlinux.simtec.co.uk/
22313 + *
22314 + * S3C series GPIO configuration core
22315 + *
22316 + * This program is free software; you can redistribute it and/or modify
22317 + * it under the terms of the GNU General Public License version 2 as
22318 + * published by the Free Software Foundation.
22319 +*/
22320 +
22321 +#include <linux/kernel.h>
22322 +#include <linux/gpio.h>
22323 +#include <linux/io.h>
22324 +
22325 +#include <mach/gpio-core.h>
22326 +#include <plat/gpio-cfg.h>
22327 +#include <plat/gpio-cfg-helpers.h>
22328 +
22329 +int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
22330 +{
22331 +       struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
22332 +       unsigned long flags;
22333 +       int offset;
22334 +       int ret;
22335 +
22336 +       if (!chip)
22337 +               return -EINVAL;
22338 +
22339 +       offset = pin - chip->chip.base;
22340 +
22341 +       local_irq_save(flags);
22342 +       ret = s3c_gpio_do_setcfg(chip, offset, config);
22343 +       local_irq_restore(flags);
22344 +
22345 +       return ret;
22346 +}
22347 +
22348 +int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
22349 +{
22350 +       struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
22351 +       unsigned long flags;
22352 +       int offset, ret;
22353 +
22354 +       if (!chip)
22355 +               return -EINVAL;
22356 +
22357 +       offset = pin - chip->chip.base;
22358 +
22359 +       local_irq_save(flags);
22360 +       ret = s3c_gpio_do_setpull(chip, offset, pull);
22361 +       local_irq_restore(flags);
22362 +
22363 +       return ret;
22364 +}
22365 +
22366 +#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
22367 +int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
22368 +                                 unsigned int off, unsigned int cfg)
22369 +{
22370 +       void __iomem *reg = chip->base;
22371 +       unsigned int shift = off;
22372 +       u32 con;
22373 +
22374 +       if (s3c_gpio_is_cfg_special(cfg)) {
22375 +               cfg &= 0xf;
22376 +
22377 +               /* Map output to 0, and SFN2 to 1 */
22378 +               cfg -= 1;
22379 +               if (cfg > 1)
22380 +                       return -EINVAL;
22381 +
22382 +               cfg <<= shift;
22383 +       }
22384 +
22385 +       con = __raw_readl(reg);
22386 +       con &= ~(0x1 << shift);
22387 +       con |= cfg;
22388 +       __raw_writel(con, reg);
22389 +
22390 +       return 0;
22391 +}
22392 +
22393 +int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
22394 +                           unsigned int off, unsigned int cfg)
22395 +{
22396 +       void __iomem *reg = chip->base;
22397 +       unsigned int shift = off * 2;
22398 +       u32 con;
22399 +
22400 +       if (s3c_gpio_is_cfg_special(cfg)) {
22401 +               cfg &= 0xf;
22402 +               if (cfg > 3)
22403 +                       return -EINVAL;
22404 +
22405 +               cfg <<= shift;
22406 +       }
22407 +
22408 +       con = __raw_readl(reg);
22409 +       con &= ~(0x3 << shift);
22410 +       con |= cfg;
22411 +       __raw_writel(con, reg);
22412 +
22413 +       return 0;
22414 +}
22415 +#endif
22416 +
22417 +#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
22418 +int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
22419 +                                unsigned int off, unsigned int cfg)
22420 +{
22421 +       void __iomem *reg = chip->base;
22422 +       unsigned int shift = (off & 7) * 4;
22423 +       u32 con;
22424 +
22425 +       if (off < 8 && chip->chip.ngpio >= 8)
22426 +               reg -= 4;
22427 +
22428 +       if (s3c_gpio_is_cfg_special(cfg)) {
22429 +               cfg &= 0xf;
22430 +               cfg <<= shift;
22431 +       }
22432 +
22433 +       con = __raw_readl(reg);
22434 +       con &= ~(0xf << shift);
22435 +       con |= cfg;
22436 +       __raw_writel(con, reg);
22437 +
22438 +       return 0;
22439 +}
22440 +#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
22441 +
22442 +#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
22443 +int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
22444 +                           unsigned int off, s3c_gpio_pull_t pull)
22445 +{
22446 +       void __iomem *reg = chip->base + 0x08;
22447 +       int shift = off * 2;
22448 +       u32 pup;
22449 +
22450 +       pup = __raw_readl(reg);
22451 +       pup &= ~(3 << shift);
22452 +       pup |= pull << shift;
22453 +       __raw_writel(pup, reg);
22454 +
22455 +       return 0;
22456 +}
22457 +
22458 +s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
22459 +                                       unsigned int off)
22460 +{
22461 +       void __iomem *reg = chip->base + 0x08;
22462 +       int shift = off * 2;
22463 +       u32 pup = __raw_readl(reg);
22464 +
22465 +       pup >>= shift;
22466 +       pup &= 0x3;
22467 +       return (__force s3c_gpio_pull_t)pup;
22468 +}
22469 +#endif
22470 --- /dev/null
22471 +++ b/arch/arm/plat-s3c/include/mach/io.h
22472 @@ -0,0 +1,18 @@
22473 +/* arch/arm/plat-s3c/include/mach/io.h
22474 + *
22475 + * Copyright 2008 Simtec Electronics
22476 + *     Ben Dooks <ben-linux@fluff.org>
22477 + *
22478 + * Default IO routines for plat-s3c based systems, such as S3C24A0
22479 + */
22480 +
22481 +#ifndef __ASM_ARM_ARCH_IO_H
22482 +#define __ASM_ARM_ARCH_IO_H
22483 +
22484 +/* No current ISA/PCI bus support. */
22485 +#define __io(a)                ((void __iomem *)(a))
22486 +#define __mem_pci(a)   (a)
22487 +
22488 +#define IO_SPACE_LIMIT (0xFFFFFFFF)
22489 +
22490 +#endif
22491 --- /dev/null
22492 +++ b/arch/arm/plat-s3c/include/mach/timex.h
22493 @@ -0,0 +1,26 @@
22494 +/* arch/arm/mach-s3c2410/include/mach/timex.h
22495 + *
22496 + * Copyright (c) 2003-2005 Simtec Electronics
22497 + *     Ben Dooks <ben@simtec.co.uk>
22498 + *
22499 + * S3C2410 - time parameters
22500 + *
22501 + * This program is free software; you can redistribute it and/or modify
22502 + * it under the terms of the GNU General Public License version 2 as
22503 + * published by the Free Software Foundation.
22504 +*/
22505 +
22506 +#ifndef __ASM_ARCH_TIMEX_H
22507 +#define __ASM_ARCH_TIMEX_H
22508 +
22509 +/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
22510 + * a variable is useless. It seems as long as we make our timers an
22511 + * exact multiple of HZ, any value that makes a 1->1 correspondence
22512 + * for the time conversion functions to/from jiffies is acceptable.
22513 +*/
22514 +
22515 +
22516 +#define CLOCK_TICK_RATE 12000000
22517 +
22518 +
22519 +#endif /* __ASM_ARCH_TIMEX_H */
22520 --- /dev/null
22521 +++ b/arch/arm/plat-s3c/include/mach/vmalloc.h
22522 @@ -0,0 +1,20 @@
22523 +/* arch/arm/plat-s3c/include/mach/vmalloc.h
22524 + *
22525 + * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
22526 + *
22527 + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
22528 + *                   http://www.simtec.co.uk/products/SWLINUX/
22529 + *
22530 + * This program is free software; you can redistribute it and/or modify
22531 + * it under the terms of the GNU General Public License version 2 as
22532 + * published by the Free Software Foundation.
22533 + *
22534 + * S3C2410 vmalloc definition
22535 +*/
22536 +
22537 +#ifndef __ASM_ARCH_VMALLOC_H
22538 +#define __ASM_ARCH_VMALLOC_H
22539 +
22540 +#define VMALLOC_END      (0xE0000000)
22541 +
22542 +#endif /* __ASM_ARCH_VMALLOC_H */
22543 --- /dev/null
22544 +++ b/arch/arm/plat-s3c/include/plat/clock.h
22545 @@ -0,0 +1,88 @@
22546 +/* linux/arch/arm/plat-s3c/include/plat/clock.h
22547 + *
22548 + * Copyright (c) 2004-2005 Simtec Electronics
22549 + *     http://www.simtec.co.uk/products/SWLINUX/
22550 + *     Written by Ben Dooks, <ben@simtec.co.uk>
22551 + *
22552 + * This program is free software; you can redistribute it and/or modify
22553 + * it under the terms of the GNU General Public License version 2 as
22554 + * published by the Free Software Foundation.
22555 +*/
22556 +
22557 +#include <linux/spinlock.h>
22558 +
22559 +struct clk {
22560 +       struct list_head      list;
22561 +       struct module        *owner;
22562 +       struct clk           *parent;
22563 +       const char           *name;
22564 +       int                   id;
22565 +       int                   usage;
22566 +       unsigned long         rate;
22567 +       unsigned long         ctrlbit;
22568 +
22569 +       int                 (*enable)(struct clk *, int enable);
22570 +       int                 (*set_rate)(struct clk *c, unsigned long rate);
22571 +       unsigned long       (*get_rate)(struct clk *c);
22572 +       unsigned long       (*round_rate)(struct clk *c, unsigned long rate);
22573 +       int                 (*set_parent)(struct clk *c, struct clk *parent);
22574 +};
22575 +
22576 +/* other clocks which may be registered by board support */
22577 +
22578 +extern struct clk s3c24xx_dclk0;
22579 +extern struct clk s3c24xx_dclk1;
22580 +extern struct clk s3c24xx_clkout0;
22581 +extern struct clk s3c24xx_clkout1;
22582 +extern struct clk s3c24xx_uclk;
22583 +
22584 +extern struct clk clk_usb_bus;
22585 +
22586 +/* core clock support */
22587 +
22588 +extern struct clk clk_f;
22589 +extern struct clk clk_h;
22590 +extern struct clk clk_p;
22591 +extern struct clk clk_mpll;
22592 +extern struct clk clk_upll;
22593 +extern struct clk clk_epll;
22594 +extern struct clk clk_xtal;
22595 +extern struct clk clk_ext;
22596 +
22597 +/* S3C64XX specific clocks */
22598 +extern struct clk clk_27m;
22599 +extern struct clk clk_48m;
22600 +
22601 +/* exports for arch/arm/mach-s3c2410
22602 + *
22603 + * Please DO NOT use these outside of arch/arm/mach-s3c2410
22604 +*/
22605 +
22606 +extern spinlock_t clocks_lock;
22607 +
22608 +extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
22609 +
22610 +extern int s3c24xx_register_clock(struct clk *clk);
22611 +extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
22612 +
22613 +extern int s3c24xx_register_baseclocks(unsigned long xtal);
22614 +
22615 +extern void s3c64xx_register_clocks(void);
22616 +
22617 +extern void s3c24xx_setup_clocks(unsigned long fclk,
22618 +                                unsigned long hclk,
22619 +                                unsigned long pclk);
22620 +
22621 +extern void s3c2410_setup_clocks(void);
22622 +extern void s3c2412_setup_clocks(void);
22623 +extern void s3c244x_setup_clocks(void);
22624 +extern void s3c2443_setup_clocks(void);
22625 +
22626 +/* S3C64XX specific functions and clocks */
22627 +
22628 +extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
22629 +
22630 +/* Init for pwm clock code */
22631 +
22632 +extern void s3c_pwmclk_init(void);
22633 +
22634 --- /dev/null
22635 +++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h
22636 @@ -0,0 +1,94 @@
22637 +/* arch/arm/plat-s3c/include/plat/cpu-freq.h
22638 + *
22639 + * Copyright (c) 2006,2007 Simtec Electronics
22640 + *     http://armlinux.simtec.co.uk/
22641 + *     Ben Dooks <ben@simtec.co.uk>
22642 + *
22643 + * S3C CPU frequency scaling support - driver and board
22644 + *
22645 + * This program is free software; you can redistribute it and/or modify
22646 + * it under the terms of the GNU General Public License version 2 as
22647 + * published by the Free Software Foundation.
22648 +*/
22649 +
22650 +#include <linux/cpufreq.h>
22651 +
22652 +struct s3c_cpufreq_info;
22653 +struct s3c_cpufreq_board;
22654 +struct s3c_iotimings;
22655 +
22656 +struct s3c_freq {
22657 +       unsigned long   fclk;
22658 +       unsigned long   armclk;
22659 +       unsigned long   hclk_tns;       /* in 10ths of ns */
22660 +       unsigned long   hclk;
22661 +       unsigned long   pclk;
22662 +};
22663 +
22664 +/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the
22665 + * notification can use this information that is not provided by just
22666 + * having the core frequency alone.
22667 + */
22668 +
22669 +struct s3c_cpufreq_freqs {
22670 +       struct cpufreq_freqs    freqs;
22671 +       struct s3c_freq         old;
22672 +       struct s3c_freq         new;
22673 +};
22674 +
22675 +#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
22676 +
22677 +struct s3c_clkdivs {
22678 +       int             p_divisor;      /* fclk / pclk */
22679 +       int             h_divisor;      /* fclk / hclk */
22680 +       int             arm_divisor;    /* not all cpus have this. */
22681 +       unsigned char   dvs;            /* using dvs mode to arm. */
22682 +};
22683 +
22684 +#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
22685 +
22686 +struct s3c_pllval {
22687 +       unsigned long           freq;
22688 +       unsigned long           pll_reg;
22689 +};
22690 +
22691 +struct s3c_cpufreq_config {
22692 +       struct s3c_freq         freq;
22693 +       struct s3c_pllval       pll;
22694 +       struct s3c_clkdivs      divs;
22695 +       struct s3c_cpufreq_info *info;  /* for core, not drivers */
22696 +       struct s3c_cpufreq_board *board;
22697 +};
22698 +
22699 +/* s3c_cpufreq_board
22700 + *
22701 + * per-board configuraton information, such as memory refresh and
22702 + * how to initialise IO timings.
22703 + */
22704 +struct s3c_cpufreq_board {
22705 +       unsigned int    refresh;        /* refresh period in ns */
22706 +       unsigned int    auto_io:1;      /* automatically init io timings. */
22707 +       unsigned int    need_io:1;      /* set if needs io timing support. */
22708 +
22709 +       /* any non-zero field in here is taken as an upper limit. */
22710 +       struct s3c_freq max;    /* frequency limits */
22711 +};
22712 +
22713 +/* Things depending on frequency scaling. */
22714 +#ifdef CONFIG_CPU_FREQ_S3C
22715 +#define __init_or_cpufreq
22716 +#else
22717 +#define __init_or_cpufreq __init
22718 +#endif
22719 +
22720 +/* Board functions */
22721 +
22722 +#ifdef CONFIG_CPU_FREQ_S3C
22723 +extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
22724 +#else
22725 +
22726 +static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
22727 +{
22728 +       return 0;
22729 +}
22730 +#endif  /* CONFIG_CPU_FREQ_S3C */
22731 --- /dev/null
22732 +++ b/arch/arm/plat-s3c/include/plat/cpu.h
22733 @@ -0,0 +1,74 @@
22734 +/* linux/arch/arm/plat-s3c/include/plat/cpu.h
22735 + *
22736 + * Copyright (c) 2004-2005 Simtec Electronics
22737 + *     Ben Dooks <ben@simtec.co.uk>
22738 + *
22739 + * Header file for S3C24XX CPU support
22740 + *
22741 + * This program is free software; you can redistribute it and/or modify
22742 + * it under the terms of the GNU General Public License version 2 as
22743 + * published by the Free Software Foundation.
22744 +*/
22745 +
22746 +/* todo - fix when rmk changes iodescs to use `void __iomem *` */
22747 +
22748 +#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
22749 +
22750 +#ifndef MHZ
22751 +#define MHZ (1000*1000)
22752 +#endif
22753 +
22754 +#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
22755 +
22756 +/* forward declaration */
22757 +struct s3c24xx_uart_resources;
22758 +struct platform_device;
22759 +struct s3c2410_uartcfg;
22760 +struct map_desc;
22761 +
22762 +/* per-cpu initialisation function table. */
22763 +
22764 +struct cpu_table {
22765 +       unsigned long   idcode;
22766 +       unsigned long   idmask;
22767 +       void            (*map_io)(void);
22768 +       void            (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
22769 +       void            (*init_clocks)(int xtal);
22770 +       int             (*init)(void);
22771 +       const char      *name;
22772 +};
22773 +
22774 +extern void s3c_init_cpu(unsigned long idcode,
22775 +                        struct cpu_table *cpus, unsigned int cputab_size);
22776 +
22777 +/* core initialisation functions */
22778 +
22779 +extern void s3c24xx_init_irq(void);
22780 +extern void s3c64xx_init_irq(u32 vic0, u32 vic1);
22781 +
22782 +extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
22783 +extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
22784 +
22785 +extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
22786 +
22787 +extern void s3c24xx_init_clocks(int xtal);
22788 +
22789 +extern void s3c24xx_init_uartdevs(char *name,
22790 +                                 struct s3c24xx_uart_resources *res,
22791 +                                 struct s3c2410_uartcfg *cfg, int no);
22792 +
22793 +/* timer for 2410/2440 */
22794 +
22795 +struct sys_timer;
22796 +extern struct sys_timer s3c24xx_timer;
22797 +
22798 +/* system device classes */
22799 +
22800 +extern struct sysdev_class s3c2410_sysclass;
22801 +extern struct sysdev_class s3c2412_sysclass;
22802 +extern struct sysdev_class s3c2440_sysclass;
22803 +extern struct sysdev_class s3c2442_sysclass;
22804 +extern struct sysdev_class s3c2443_sysclass;
22805 +extern struct sysdev_class s3c6410_sysclass;
22806 +extern struct sysdev_class s3c64xx_sysclass;
22807 +
22808 --- a/arch/arm/plat-s3c/include/plat/debug-macro.S
22809 +++ b/arch/arm/plat-s3c/include/plat/debug-macro.S
22810 @@ -20,7 +20,7 @@
22811         .endm
22812
22813  #ifndef fifo_level
22814 -#define fifo_level fifo_level_s3c2410
22815 +#define fifo_level fifo_level_s3c2440
22816  #endif
22817
22818         .macro  fifo_full_s3c2440 rd, rx
22819 --- /dev/null
22820 +++ b/arch/arm/plat-s3c/include/plat/devs.h
22821 @@ -0,0 +1,55 @@
22822 +/* linux/include/asm-arm/plat-s3c24xx/devs.h
22823 + *
22824 + * Copyright (c) 2004 Simtec Electronics
22825 + * Ben Dooks <ben@simtec.co.uk>
22826 + *
22827 + * Header file for s3c2410 standard platform devices
22828 + *
22829 + * This program is free software; you can redistribute it and/or modify
22830 + * it under the terms of the GNU General Public License version 2 as
22831 + * published by the Free Software Foundation.
22832 +*/
22833 +#include <linux/platform_device.h>
22834 +
22835 +struct s3c24xx_uart_resources {
22836 +       struct resource         *resources;
22837 +       unsigned long            nr_resources;
22838 +};
22839 +
22840 +extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
22841 +extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
22842 +
22843 +extern struct platform_device *s3c24xx_uart_devs[];
22844 +extern struct platform_device *s3c24xx_uart_src[];
22845 +
22846 +extern struct platform_device s3c_device_timer[];
22847 +
22848 +extern struct platform_device s3c_device_fb;
22849 +extern struct platform_device s3c_device_usb;
22850 +extern struct platform_device s3c_device_lcd;
22851 +extern struct platform_device s3c_device_wdt;
22852 +extern struct platform_device s3c_device_i2c0;
22853 +extern struct platform_device s3c_device_i2c1;
22854 +extern struct platform_device s3c_device_iis;
22855 +extern struct platform_device s3c_device_rtc;
22856 +extern struct platform_device s3c_device_adc;
22857 +extern struct platform_device s3c_device_sdi;
22858 +extern struct platform_device s3c_device_hsmmc0;
22859 +extern struct platform_device s3c_device_hsmmc1;
22860 +extern struct platform_device s3c_device_hsmmc2;
22861 +
22862 +extern struct platform_device s3c_device_spi0;
22863 +extern struct platform_device s3c_device_spi1;
22864 +
22865 +extern struct platform_device s3c_device_nand;
22866 +
22867 +extern struct platform_device s3c_device_usbgadget;
22868 +
22869 +extern struct platform_device s3c_device_ts;
22870 +
22871 +/* s3c2440 specific devices */
22872 +
22873 +#ifdef CONFIG_CPU_S3C2440
22874 +
22875 +extern struct platform_device s3c_device_camif;
22876 +#endif
22877 --- /dev/null
22878 +++ b/arch/arm/plat-s3c/include/plat/fb.h
22879 @@ -0,0 +1,73 @@
22880 +/* linux/arch/arm/plat-s3c/include/plat/fb.h
22881 + *
22882 + * Copyright 2008 Openmoko, Inc.
22883 + * Copyright 2008 Simtec Electronics
22884 + *     http://armlinux.simtec.co.uk/
22885 + *     Ben Dooks <ben@simtec.co.uk>
22886 + *
22887 + * S3C - FB platform data definitions
22888 + *
22889 + * This program is free software; you can redistribute it and/or modify
22890 + * it under the terms of the GNU General Public License version 2 as
22891 + * published by the Free Software Foundation.
22892 +*/
22893 +
22894 +#ifndef __PLAT_S3C_FB_H
22895 +#define __PLAT_S3C_FB_H __FILE__
22896 +
22897 +/**
22898 + * struct s3c_fb_pd_win - per window setup data
22899 + * @win_mode: The display parameters to initialise (not for window 0)
22900 + * @virtual_x: The virtual X size.
22901 + * @virtual_y: The virtual Y size.
22902 + */
22903 +struct s3c_fb_pd_win {
22904 +       struct fb_videomode     win_mode;
22905 +
22906 +       unsigned short          default_bpp;
22907 +       unsigned short          max_bpp;
22908 +       unsigned short          virtual_x;
22909 +       unsigned short          virtual_y;
22910 +};
22911 +
22912 +/**
22913 + * struct s3c_fb_platdata -  S3C driver platform specific information
22914 + * @setup_gpio: Setup the external GPIO pins to the right state to transfer
22915 + *             the data from the display system to the connected display
22916 + *             device.
22917 + * @vidcon0: The base vidcon0 values to control the panel data format.
22918 + * @vidcon1: The base vidcon1 values to control the panel data output.
22919 + * @win: The setup data for each hardware window, or NULL for unused.
22920 + * @display_mode: The LCD output display mode.
22921 + *
22922 + * The platform data supplies the video driver with all the information
22923 + * it requires to work with the display(s) attached to the machine. It
22924 + * controls the initial mode, the number of display windows (0 is always
22925 + * the base framebuffer) that are initialised etc.
22926 + *
22927 + */
22928 +struct s3c_fb_platdata {
22929 +       void    (*setup_gpio)(void);
22930 +
22931 +       struct s3c_fb_pd_win    *win[S3C_FB_MAX_WIN];
22932 +
22933 +       u32                      vidcon0;
22934 +       u32                      vidcon1;
22935 +};
22936 +
22937 +/**
22938 + * s3c_fb_set_platdata() - Setup the FB device with platform data.
22939 + * @pd: The platform data to set. The data is copied from the passed structure
22940 + *      so the machine data can mark the data __initdata so that any unused
22941 + *      machines will end up dumping their data at runtime.
22942 + */
22943 +extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
22944 +
22945 +/**
22946 + * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
22947 + *
22948 + * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
22949 + */
22950 +extern void s3c64xx_fb_gpio_setup_24bpp(void);
22951 +
22952 +#endif /* __PLAT_S3C_FB_H */
22953 --- /dev/null
22954 +++ b/arch/arm/plat-s3c/include/plat/gpio-cfg.h
22955 @@ -0,0 +1,110 @@
22956 +/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h
22957 + *
22958 + * Copyright 2008 Openmoko, Inc.
22959 + * Copyright 2008 Simtec Electronics
22960 + *     http://armlinux.simtec.co.uk/
22961 + *     Ben Dooks <ben@simtec.co.uk>
22962 + *
22963 + * S3C Platform - GPIO pin configuration
22964 + *
22965 + * This program is free software; you can redistribute it and/or modify
22966 + * it under the terms of the GNU General Public License version 2 as
22967 + * published by the Free Software Foundation.
22968 +*/
22969 +
22970 +/* This file contains the necessary definitions to get the basic gpio
22971 + * pin configuration done such as setting a pin to input or output or
22972 + * changing the pull-{up,down} configurations.
22973 + */
22974 +
22975 +/* Note, this interface is being added to the s3c64xx arch first and will
22976 + * be added to the s3c24xx systems later.
22977 + */
22978 +
22979 +#ifndef __PLAT_GPIO_CFG_H
22980 +#define __PLAT_GPIO_CFG_H __FILE__
22981 +
22982 +typedef unsigned int __bitwise__ s3c_gpio_pull_t;
22983 +
22984 +/* forward declaration if gpio-core.h hasn't been included */
22985 +struct s3c_gpio_chip;
22986 +
22987 +/**
22988 + * struct s3c_gpio_cfg GPIO configuration
22989 + * @cfg_eint: Configuration setting when used for external interrupt source
22990 + * @get_pull: Read the current pull configuration for the GPIO
22991 + * @set_pull: Set the current pull configuraiton for the GPIO
22992 + * @set_config: Set the current configuration for the GPIO
22993 + * @get_config: Read the current configuration for the GPIO
22994 + *
22995 + * Each chip can have more than one type of GPIO bank available and some
22996 + * have different capabilites even when they have the same control register
22997 + * layouts. Provide an point to vector control routine and provide any
22998 + * per-bank configuration information that other systems such as the
22999 + * external interrupt code will need.
23000 + */
23001 +struct s3c_gpio_cfg {
23002 +       unsigned int    cfg_eint;
23003 +
23004 +       s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
23005 +       int             (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
23006 +                                   s3c_gpio_pull_t pull);
23007 +
23008 +       unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
23009 +       int      (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
23010 +                              unsigned config);
23011 +};
23012 +
23013 +#define S3C_GPIO_SPECIAL_MARK  (0xfffffff0)
23014 +#define S3C_GPIO_SPECIAL(x)    (S3C_GPIO_SPECIAL_MARK | (x))
23015 +
23016 +/* Defines for generic pin configurations */
23017 +#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0))
23018 +#define S3C_GPIO_OUTPUT        (S3C_GPIO_SPECIAL(1))
23019 +#define S3C_GPIO_SFN(x)        (S3C_GPIO_SPECIAL(x))
23020 +
23021 +#define s3c_gpio_is_cfg_special(_cfg) \
23022 +       (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
23023 +
23024 +/**
23025 + * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
23026 + * @pin pin The pin number to configure.
23027 + * @pin to The configuration for the pin's function.
23028 + *
23029 + * Configure which function is actually connected to the external
23030 + * pin, such as an gpio input, output or some form of special function
23031 + * connected to an internal peripheral block.
23032 + */
23033 +extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
23034 +
23035 +/* Define values for the pull-{up,down} available for each gpio pin.
23036 + *
23037 + * These values control the state of the weak pull-{up,down} resistors
23038 + * available on most pins on the S3C series. Not all chips support both
23039 + * up or down settings, and it may be dependant on the chip that is being
23040 + * used to whether the particular mode is available.
23041 + */
23042 +#define S3C_GPIO_PULL_NONE     ((__force s3c_gpio_pull_t)0x00)
23043 +#define S3C_GPIO_PULL_DOWN     ((__force s3c_gpio_pull_t)0x01)
23044 +#define S3C_GPIO_PULL_UP       ((__force s3c_gpio_pull_t)0x02)
23045 +
23046 +/**
23047 + * s3c_gpio_setpull() - set the state of a gpio pin pull resistor
23048 + * @pin: The pin number to configure the pull resistor.
23049 + * @pull: The configuration for the pull resistor.
23050 + *
23051 + * This function sets the state of the pull-{up,down} resistor for the
23052 + * specified pin. It will return 0 if successfull, or a negative error
23053 + * code if the pin cannot support the requested pull setting.
23054 +*/
23055 +extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
23056 +
23057 +/**
23058 + * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
23059 + * @pin: The pin number to get the settings for
23060 + *
23061 + * Read the pull resistor value for the specified pin.
23062 +*/
23063 +extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
23064 +
23065 +#endif /* __PLAT_GPIO_CFG_H */
23066 --- /dev/null
23067 +++ b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h
23068 @@ -0,0 +1,176 @@
23069 +/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
23070 + *
23071 + * Copyright 2008 Openmoko, Inc.
23072 + * Copyright 2008 Simtec Electronics
23073 + *     http://armlinux.simtec.co.uk/
23074 + *     Ben Dooks <ben@simtec.co.uk>
23075 + *
23076 + * S3C Platform - GPIO pin configuration helper definitions
23077 + *
23078 + * This program is free software; you can redistribute it and/or modify
23079 + * it under the terms of the GNU General Public License version 2 as
23080 + * published by the Free Software Foundation.
23081 +*/
23082 +
23083 +/* This is meant for core cpu support, machine or other driver files
23084 + * should not be including this header.
23085 + */
23086 +
23087 +#ifndef __PLAT_GPIO_CFG_HELPERS_H
23088 +#define __PLAT_GPIO_CFG_HELPERS_H __FILE__
23089 +
23090 +/* As a note, all gpio configuration functions are entered exclusively, either
23091 + * with the relevant lock held or the system prevented from doing anything else
23092 + * by disabling interrupts.
23093 +*/
23094 +
23095 +static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
23096 +                                    unsigned int off, unsigned int config)
23097 +{
23098 +       return (chip->config->set_config)(chip, off, config);
23099 +}
23100 +
23101 +static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
23102 +                                     unsigned int off, s3c_gpio_pull_t pull)
23103 +{
23104 +       return (chip->config->set_pull)(chip, off, pull);
23105 +}
23106 +
23107 +/**
23108 + * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
23109 + * @chip: The gpio chip that is being configured.
23110 + * @off: The offset for the GPIO being configured.
23111 + * @cfg: The configuration value to set.
23112 + *
23113 + * This helper deal with the GPIO cases where the control register
23114 + * has two bits of configuration per gpio, which have the following
23115 + * functions:
23116 + *     00 = input
23117 + *     01 = output
23118 + *     1x = special function
23119 +*/
23120 +extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
23121 +                                  unsigned int off, unsigned int cfg);
23122 +
23123 +/**
23124 + * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
23125 + * @chip: The gpio chip that is being configured.
23126 + * @off: The offset for the GPIO being configured.
23127 + * @cfg: The configuration value to set.
23128 + *
23129 + * This helper deal with the GPIO cases where the control register
23130 + * has one bit of configuration for the gpio, where setting the bit
23131 + * means the pin is in special function mode and unset means output.
23132 +*/
23133 +extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
23134 +                                    unsigned int off, unsigned int cfg);
23135 +
23136 +/**
23137 + * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
23138 + * @chip: The gpio chip that is being configured.
23139 + * @off: The offset for the GPIO being configured.
23140 + * @cfg: The configuration value to set.
23141 + *
23142 + * This helper deal with the GPIO cases where the control register has 4 bits
23143 + * of control per GPIO, generally in the form of:
23144 + *     0000 = Input
23145 + *     0001 = Output
23146 + *     others = Special functions (dependant on bank)
23147 + *
23148 + * Note, since the code to deal with the case where there are two control
23149 + * registers instead of one, we do not have a seperate set of functions for
23150 + * each case.
23151 +*/
23152 +extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
23153 +                                       unsigned int off, unsigned int cfg);
23154 +
23155 +
23156 +/* Pull-{up,down} resistor controls.
23157 + *
23158 + * S3C2410,S3C2440,S3C24A0 = Pull-UP,
23159 + * S3C2412,S3C2413 = Pull-Down
23160 + * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
23161 + * S3C2443 = Pull-Both [not same as S3C6400]
23162 + */
23163 +
23164 +/**
23165 + * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
23166 + * @chip: The gpio chip that is being configured.
23167 + * @off: The offset for the GPIO being configured.
23168 + * @param: pull: The pull mode being requested.
23169 + *
23170 + * This is a helper function for the case where we have GPIOs with one
23171 + * bit configuring the presence of a pull-up resistor.
23172 + */
23173 +extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
23174 +                               unsigned int off, s3c_gpio_pull_t pull);
23175 +
23176 +/**
23177 + * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
23178 + * @chip: The gpio chip that is being configured
23179 + * @off: The offset for the GPIO being configured
23180 + * @param: pull: The pull mode being requested
23181 + *
23182 + * This is a helper function for the case where we have GPIOs with one
23183 + * bit configuring the presence of a pull-down resistor.
23184 + */
23185 +extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
23186 +                                 unsigned int off, s3c_gpio_pull_t pull);
23187 +
23188 +/**
23189 + * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
23190 + * @chip: The gpio chip that is being configured.
23191 + * @off: The offset for the GPIO being configured.
23192 + * @param: pull: The pull mode being requested.
23193 + *
23194 + * This is a helper function for the case where we have GPIOs with two
23195 + * bits configuring the presence of a pull resistor, in the following
23196 + * order:
23197 + *     00 = No pull resistor connected
23198 + *     01 = Pull-up resistor connected
23199 + *     10 = Pull-down resistor connected
23200 + */
23201 +extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
23202 +                                  unsigned int off, s3c_gpio_pull_t pull);
23203 +
23204 +
23205 +/**
23206 + * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
23207 + * @chip: The gpio chip that the GPIO pin belongs to
23208 + * @off: The offset to the pin to get the configuration of.
23209 + *
23210 + * This helper function reads the state of the pull-{up,down} resistor for the
23211 + * given GPIO in the same case as s3c_gpio_setpull_upown.
23212 +*/
23213 +extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
23214 +                                              unsigned int off);
23215 +
23216 +/**
23217 + * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
23218 + * @chip: The gpio chip that is being configured.
23219 + * @off: The offset for the GPIO being configured.
23220 + * @param: pull: The pull mode being requested.
23221 + *
23222 + * This is a helper function for the case where we have GPIOs with two
23223 + * bits configuring the presence of a pull resistor, in the following
23224 + * order:
23225 + *     00 = Pull-up resistor connected
23226 + *     10 = Pull-down resistor connected
23227 + *     x1 = No pull up resistor
23228 + */
23229 +extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
23230 +                                   unsigned int off, s3c_gpio_pull_t pull);
23231 +
23232 +/**
23233 + * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
23234 + * @chip: The gpio chip that the GPIO pin belongs to.
23235 + * @off: The offset to the pin to get the configuration of.
23236 + *
23237 + * This helper function reads the state of the pull-{up,down} resistor for the
23238 + * given GPIO in the same case as s3c_gpio_setpull_upown.
23239 +*/
23240 +extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
23241 +                                               unsigned int off);
23242 +
23243 +#endif /* __PLAT_GPIO_CFG_HELPERS_H */
23244 +
23245 --- /dev/null
23246 +++ b/arch/arm/plat-s3c/include/plat/gpio-core.h
23247 @@ -0,0 +1,107 @@
23248 +/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
23249 + *
23250 + * Copyright 2008 Simtec Electronics
23251 + *     http://armlinux.simtec.co.uk/
23252 + *     Ben Dooks <ben@simtec.co.uk>
23253 + *
23254 + * S3C Platform - GPIO core
23255 + *
23256 + * This program is free software; you can redistribute it and/or modify
23257 + * it under the terms of the GNU General Public License version 2 as
23258 + * published by the Free Software Foundation.
23259 +*/
23260 +
23261 +/* Define the core gpiolib support functions that the s3c platforms may
23262 + * need to extend or change depending on the hardware and the s3c chip
23263 + * selected at build or found at run time.
23264 + *
23265 + * These definitions are not intended for driver inclusion, there is
23266 + * nothing here that should not live outside the platform and core
23267 + * specific code.
23268 +*/
23269 +
23270 +struct s3c_gpio_chip;
23271 +
23272 +/**
23273 + * struct s3c_gpio_pm - power management (suspend/resume) information
23274 + * @save: Routine to save the state of the GPIO block
23275 + * @resume: Routine to resume the GPIO block.
23276 + */
23277 +struct s3c_gpio_pm {
23278 +       void (*save)(struct s3c_gpio_chip *chip);
23279 +       void (*resume)(struct s3c_gpio_chip *chip);
23280 +};
23281 +
23282 +struct s3c_gpio_cfg;
23283 +
23284 +/**
23285 + * struct s3c_gpio_chip - wrapper for specific implementation of gpio
23286 + * @chip: The chip structure to be exported via gpiolib.
23287 + * @base: The base pointer to the gpio configuration registers.
23288 + * @config: special function and pull-resistor control information.
23289 + * @pm_save: Save information for suspend/resume support.
23290 + *
23291 + * This wrapper provides the necessary information for the Samsung
23292 + * specific gpios being registered with gpiolib.
23293 + */
23294 +struct s3c_gpio_chip {
23295 +       struct gpio_chip        chip;
23296 +       struct s3c_gpio_cfg     *config;
23297 +       struct s3c_gpio_pm      *pm;
23298 +       void __iomem            *base;
23299 +#ifdef CONFIG_PM
23300 +       u32                     pm_save[4];
23301 +#endif
23302 +};
23303 +
23304 +static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
23305 +{
23306 +       return container_of(gpc, struct s3c_gpio_chip, chip);
23307 +}
23308 +
23309 +/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
23310 + * @chip: The chip to register
23311 + *
23312 + * This is a wrapper to gpiochip_add() that takes our specific gpio chip
23313 + * information and makes the necessary alterations for the platform and
23314 + * notes the information for use with the configuration systems and any
23315 + * other parts of the system.
23316 + */
23317 +extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
23318 +
23319 +/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
23320 + * for use with the configuration calls, and other parts of the s3c gpiolib
23321 + * support code.
23322 + *
23323 + * Not all s3c support code will need this, as some configurations of cpu
23324 + * may only support one or two different configuration options and have an
23325 + * easy gpio to s3c_gpio_chip mapping function. If this is the case, then
23326 + * the machine support file should provide its own s3c_gpiolib_getchip()
23327 + * and any other necessary functions.
23328 + */
23329 +
23330 +#ifdef CONFIG_S3C_GPIO_TRACK
23331 +extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
23332 +
23333 +static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
23334 +{
23335 +       return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
23336 +}
23337 +#else
23338 +/* machine specific code should provide s3c_gpiolib_getchip */
23339 +
23340 +static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
23341 +#endif
23342 +
23343 +#ifdef CONFIG_PM
23344 +extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
23345 +extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
23346 +extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
23347 +#define __gpio_pm(x) x
23348 +#else
23349 +#define s3c_gpio_pm_1bit NULL
23350 +#define s3c_gpio_pm_2bit NULL
23351 +#define s3c_gpio_pm_4bit NULL
23352 +#define __gpio_pm(x) NULL
23353 +
23354 +#endif /* CONFIG_PM */
23355 --- /dev/null
23356 +++ b/arch/arm/plat-s3c/include/plat/iic-core.h
23357 @@ -0,0 +1,35 @@
23358 +/* arch/arm/mach-s3c2410/include/mach/iic-core.h
23359 + *
23360 + * Copyright 2008 Openmoko, Inc.
23361 + * Copyright 2008 Simtec Electronics
23362 + *     Ben Dooks <ben@simtec.co.uk>
23363 + *
23364 + * S3C - I2C Controller core functions
23365 + *
23366 + * This program is free software; you can redistribute it and/or modify
23367 + * it under the terms of the GNU General Public License version 2 as
23368 + * published by the Free Software Foundation.
23369 +*/
23370 +
23371 +#ifndef __ASM_ARCH_IIC_CORE_H
23372 +#define __ASM_ARCH_IIC_CORE_H __FILE__
23373 +
23374 +/* These functions are only for use with the core support code, such as
23375 + * the cpu specific initialisation code
23376 + */
23377 +
23378 +/* re-define device name depending on support. */
23379 +static inline void s3c_i2c0_setname(char *name)
23380 +{
23381 +       /* currently this device is always compiled in */
23382 +       s3c_device_i2c0.name = name;
23383 +}
23384 +
23385 +static inline void s3c_i2c1_setname(char *name)
23386 +{
23387 +#ifdef CONFIG_S3C_DEV_I2C1
23388 +       s3c_device_i2c1.name = name;
23389 +#endif
23390 +}
23391 +
23392 +#endif /* __ASM_ARCH_IIC_H */
23393 --- /dev/null
23394 +++ b/arch/arm/plat-s3c/include/plat/iic.h
23395 @@ -0,0 +1,57 @@
23396 +/* arch/arm/mach-s3c2410/include/mach/iic.h
23397 + *
23398 + * Copyright (c) 2004 Simtec Electronics
23399 + *     Ben Dooks <ben@simtec.co.uk>
23400 + *
23401 + * S3C2410 - I2C Controller platfrom_device info
23402 + *
23403 + * This program is free software; you can redistribute it and/or modify
23404 + * it under the terms of the GNU General Public License version 2 as
23405 + * published by the Free Software Foundation.
23406 +*/
23407 +
23408 +#ifndef __ASM_ARCH_IIC_H
23409 +#define __ASM_ARCH_IIC_H __FILE__
23410 +
23411 +#define S3C_IICFLG_FILTER      (1<<0)  /* enable s3c2440 filter */
23412 +
23413 +/* Notes:
23414 + *     1) All frequencies are expressed in Hz
23415 + *     2) A value of zero is `do not care`
23416 +*/
23417 +
23418 +struct s3c2410_platform_i2c {
23419 +       int             bus_num;        /* bus number to use */
23420 +       unsigned int    flags;
23421 +       unsigned int    slave_addr;     /* slave address for controller */
23422 +       unsigned long   bus_freq;       /* standard bus frequency */
23423 +       unsigned long   max_freq;       /* max frequency for the bus */
23424 +       unsigned long   min_freq;       /* min frequency for the bus */
23425 +       unsigned int    sda_delay;      /* pclks (s3c2440 only) */
23426 +
23427 +       void    (*cfg_gpio)(struct platform_device *dev);
23428 +};
23429 +
23430 +/**
23431 + * s3c_i2c0_set_platdata - set platform data for i2c0 device
23432 + * @i2c: The platform data to set, or NULL for default data.
23433 + *
23434 + * Register the given platform data for use with the i2c0 device. This
23435 + * call copies the platform data, so the caller can use __initdata for
23436 + * their copy.
23437 + *
23438 + * This call will set cfg_gpio if is null to the default platform
23439 + * implementation.
23440 + *
23441 + * Any user of s3c_device_i2c0 should call this, even if it is with
23442 + * NULL to ensure that the device is given the default platform data
23443 + * as the driver will no longer carry defaults.
23444 + */
23445 +extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
23446 +extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
23447 +
23448 +/* defined by architecture to configure gpio */
23449 +extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
23450 +extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
23451 +
23452 +#endif /* __ASM_ARCH_IIC_H */
23453 --- /dev/null
23454 +++ b/arch/arm/plat-s3c/include/plat/map-base.h
23455 @@ -0,0 +1,40 @@
23456 +/* linux/include/asm-arm/plat-s3c/map.h
23457 + *
23458 + * Copyright 2003, 2007 Simtec Electronics
23459 + *     http://armlinux.simtec.co.uk/
23460 + *     Ben Dooks <ben@simtec.co.uk>
23461 + *
23462 + * S3C - Memory map definitions (virtual addresses)
23463 + *
23464 + * This program is free software; you can redistribute it and/or modify
23465 + * it under the terms of the GNU General Public License version 2 as
23466 + * published by the Free Software Foundation.
23467 +*/
23468 +
23469 +#ifndef __ASM_PLAT_MAP_H
23470 +#define __ASM_PLAT_MAP_H __FILE__
23471 +
23472 +/* Fit all our registers in at 0xF4000000 upwards, trying to use as
23473 + * little of the VA space as possible so vmalloc and friends have a
23474 + * better chance of getting memory.
23475 + *
23476 + * we try to ensure stuff like the IRQ registers are available for
23477 + * an single MOVS instruction (ie, only 8 bits of set data)
23478 + */
23479 +
23480 +#define S3C_ADDR_BASE  (0xF4000000)
23481 +
23482 +#ifndef __ASSEMBLY__
23483 +#define S3C_ADDR(x)    ((void __iomem __force *)S3C_ADDR_BASE + (x))
23484 +#else
23485 +#define S3C_ADDR(x)    (S3C_ADDR_BASE + (x))
23486 +#endif
23487 +
23488 +#define S3C_VA_IRQ     S3C_ADDR(0x00000000)    /* irq controller(s) */
23489 +#define S3C_VA_SYS     S3C_ADDR(0x00100000)    /* system control */
23490 +#define S3C_VA_MEM     S3C_ADDR(0x00200000)    /* system control */
23491 +#define S3C_VA_TIMER   S3C_ADDR(0x00300000)    /* timer block */
23492 +#define S3C_VA_WATCHDOG        S3C_ADDR(0x00400000)    /* watchdog */
23493 +#define S3C_VA_UART    S3C_ADDR(0x01000000)    /* UART */
23494 +
23495 +#endif /* __ASM_PLAT_MAP_H */
23496 --- a/arch/arm/plat-s3c/include/plat/map.h
23497 +++ /dev/null
23498 @@ -1,40 +0,0 @@
23499 -/* linux/include/asm-arm/plat-s3c/map.h
23500 - *
23501 - * Copyright 2003, 2007 Simtec Electronics
23502 - *     http://armlinux.simtec.co.uk/
23503 - *     Ben Dooks <ben@simtec.co.uk>
23504 - *
23505 - * S3C - Memory map definitions (virtual addresses)
23506 - *
23507 - * This program is free software; you can redistribute it and/or modify
23508 - * it under the terms of the GNU General Public License version 2 as
23509 - * published by the Free Software Foundation.
23510 -*/
23511 -
23512 -#ifndef __ASM_PLAT_MAP_H
23513 -#define __ASM_PLAT_MAP_H __FILE__
23514 -
23515 -/* Fit all our registers in at 0xF4000000 upwards, trying to use as
23516 - * little of the VA space as possible so vmalloc and friends have a
23517 - * better chance of getting memory.
23518 - *
23519 - * we try to ensure stuff like the IRQ registers are available for
23520 - * an single MOVS instruction (ie, only 8 bits of set data)
23521 - */
23522 -
23523 -#define S3C_ADDR_BASE  (0xF4000000)
23524 -
23525 -#ifndef __ASSEMBLY__
23526 -#define S3C_ADDR(x)    ((void __iomem __force *)S3C_ADDR_BASE + (x))
23527 -#else
23528 -#define S3C_ADDR(x)    (S3C_ADDR_BASE + (x))
23529 -#endif
23530 -
23531 -#define S3C_VA_IRQ     S3C_ADDR(0x00000000)    /* irq controller(s) */
23532 -#define S3C_VA_SYS     S3C_ADDR(0x00100000)    /* system control */
23533 -#define S3C_VA_MEM     S3C_ADDR(0x00200000)    /* system control */
23534 -#define S3C_VA_TIMER   S3C_ADDR(0x00300000)    /* timer block */
23535 -#define S3C_VA_WATCHDOG        S3C_ADDR(0x00400000)    /* watchdog */
23536 -#define S3C_VA_UART    S3C_ADDR(0x01000000)    /* UART */
23537 -
23538 -#endif /* __ASM_PLAT_MAP_H */
23539 --- /dev/null
23540 +++ b/arch/arm/plat-s3c/include/plat/nand.h
23541 @@ -0,0 +1,56 @@
23542 +/* arch/arm/mach-s3c2410/include/mach/nand.h
23543 + *
23544 + * Copyright (c) 2004 Simtec Electronics
23545 + *     Ben Dooks <ben@simtec.co.uk>
23546 + *
23547 + * S3C2410 - NAND device controller platfrom_device info
23548 + *
23549 + * This program is free software; you can redistribute it and/or modify
23550 + * it under the terms of the GNU General Public License version 2 as
23551 + * published by the Free Software Foundation.
23552 +*/
23553 +
23554 +/* struct s3c2410_nand_set
23555 + *
23556 + * define an set of one or more nand chips registered with an unique mtd
23557 + *
23558 + * nr_chips     = number of chips in this set
23559 + * nr_partitions = number of partitions pointed to be partitoons (or zero)
23560 + * name                 = name of set (optional)
23561 + * nr_map       = map for low-layer logical to physical chip numbers (option)
23562 + * partitions   = mtd partition list
23563 +*/
23564 +
23565 +#define S3C2410_NAND_BBT       0x0001
23566 +
23567 +struct s3c2410_nand_set {
23568 +       unsigned int            disable_ecc : 1;
23569 +
23570 +       int                     nr_chips;
23571 +       int                     nr_partitions;
23572 +       unsigned int            flags;
23573 +       char                    *name;
23574 +       int                     *nr_map;
23575 +       struct mtd_partition    *partitions;
23576 +       struct nand_ecclayout   *ecc_layout;
23577 +};
23578 +
23579 +struct s3c2410_platform_nand {
23580 +       /* timing information for controller, all times in nanoseconds */
23581 +
23582 +       int     tacls;  /* time for active CLE/ALE to nWE/nOE */
23583 +       int     twrph0; /* active time for nWE/nOE */
23584 +       int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
23585 +
23586 +       unsigned int    ignore_unset_ecc : 1;
23587 +
23588 +       int                     nr_sets;
23589 +       struct s3c2410_nand_set *sets;
23590 +
23591 +       /* force software_ecc at runtime */
23592 +       int     software_ecc;
23593 +
23594 +       void                    (*select_chip)(struct s3c2410_nand_set *,
23595 +                                              int chip);
23596 +};
23597 +
23598 --- /dev/null
23599 +++ b/arch/arm/plat-s3c/include/plat/pm.h
23600 @@ -0,0 +1,184 @@
23601 +/* linux/include/asm-arm/plat-s3c24xx/pm.h
23602 + *
23603 + * Copyright (c) 2004 Simtec Electronics
23604 + *     http://armlinux.simtec.co.uk/
23605 + *     Written by Ben Dooks, <ben@simtec.co.uk>
23606 + *
23607 + * This program is free software; you can redistribute it and/or modify
23608 + * it under the terms of the GNU General Public License version 2 as
23609 + * published by the Free Software Foundation.
23610 +*/
23611 +
23612 +#include <linux/sysdev.h>
23613 +
23614 +/* s3c_pm_init
23615 + *
23616 + * called from board at initialisation time to setup the power
23617 + * management
23618 +*/
23619 +
23620 +#ifdef CONFIG_PM
23621 +
23622 +extern __init int s3c_pm_init(void);
23623 +
23624 +#else
23625 +
23626 +static inline int s3c_pm_init(void)
23627 +{
23628 +       return 0;
23629 +}
23630 +#endif
23631 +
23632 +/* configuration for the IRQ mask over sleep */
23633 +extern unsigned long s3c_irqwake_intmask;
23634 +extern unsigned long s3c_irqwake_eintmask;
23635 +
23636 +/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
23637 +extern unsigned long s3c_irqwake_intallow;
23638 +extern unsigned long s3c_irqwake_eintallow;
23639 +
23640 +/* per-cpu sleep functions */
23641 +
23642 +extern void (*pm_cpu_prep)(void);
23643 +extern void (*pm_cpu_sleep)(void);
23644 +
23645 +/* Flags for PM Control */
23646 +
23647 +extern unsigned long s3c_pm_flags;
23648 +
23649 +extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
23650 +
23651 +/* from sleep.S */
23652 +
23653 +extern int  s3c_cpu_save(unsigned long *saveblk);
23654 +extern void s3c_cpu_resume(void);
23655 +
23656 +extern void s3c2410_cpu_suspend(void);
23657 +
23658 +extern unsigned long s3c_sleep_save_phys;
23659 +
23660 +/* sleep save info */
23661 +
23662 +/**
23663 + * struct sleep_save - save information for shared peripherals.
23664 + * @reg: Pointer to the register to save.
23665 + * @val: Holder for the value saved from reg.
23666 + *
23667 + * This describes a list of registers which is used by the pm core and
23668 + * other subsystem to save and restore register values over suspend.
23669 + */
23670 +struct sleep_save {
23671 +       void __iomem    *reg;
23672 +       unsigned long   val;
23673 +};
23674 +
23675 +#define SAVE_ITEM(x) \
23676 +       { .reg = (x) }
23677 +
23678 +/**
23679 + * struct pm_uart_save - save block for core UART
23680 + * @ulcon: Save value for S3C2410_ULCON
23681 + * @ucon: Save value for S3C2410_UCON
23682 + * @ufcon: Save value for S3C2410_UFCON
23683 + * @umcon: Save value for S3C2410_UMCON
23684 + * @ubrdiv: Save value for S3C2410_UBRDIV
23685 + *
23686 + * Save block for UART registers to be held over sleep and restored if they
23687 + * are needed (say by debug).
23688 +*/
23689 +struct pm_uart_save {
23690 +       u32     ulcon;
23691 +       u32     ucon;
23692 +       u32     ufcon;
23693 +       u32     umcon;
23694 +       u32     ubrdiv;
23695 +       u32     udivslot;
23696 +};
23697 +
23698 +/* helper functions to save/restore lists of registers. */
23699 +
23700 +extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
23701 +extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
23702 +extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
23703 +
23704 +#ifdef CONFIG_PM
23705 +extern int s3c_irqext_wake(unsigned int irqno, unsigned int state);
23706 +extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
23707 +extern int s3c24xx_irq_resume(struct sys_device *dev);
23708 +#else
23709 +#define s3c_irqext_wake NULL
23710 +#define s3c24xx_irq_suspend NULL
23711 +#define s3c24xx_irq_resume  NULL
23712 +#endif
23713 +
23714 +/* PM debug functions */
23715 +
23716 +#ifdef CONFIG_S3C2410_PM_DEBUG
23717 +/**
23718 + * s3c_pm_dbg() - low level debug function for use in suspend/resume.
23719 + * @msg: The message to print.
23720 + *
23721 + * This function is used mainly to debug the resume process before the system
23722 + * can rely on printk/console output. It uses the low-level debugging output
23723 + * routine printascii() to do its work.
23724 + */
23725 +extern void s3c_pm_dbg(const char *msg, ...);
23726 +
23727 +#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
23728 +#else
23729 +#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
23730 +#endif
23731 +
23732 +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
23733 +/**
23734 + * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
23735 + * @set: set bits for the state of the LEDs
23736 + * @clear: clear bits for the state of the LEDs.
23737 + */
23738 +extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
23739 +
23740 +#else
23741 +static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
23742 +#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
23743 +
23744 +/* suspend memory checking */
23745 +
23746 +#ifdef CONFIG_S3C2410_PM_CHECK
23747 +extern void s3c_pm_check_prepare(void);
23748 +extern void s3c_pm_check_restore(void);
23749 +extern void s3c_pm_check_cleanup(void);
23750 +extern void s3c_pm_check_store(void);
23751 +#else
23752 +#define s3c_pm_check_prepare() do { } while(0)
23753 +#define s3c_pm_check_restore() do { } while(0)
23754 +#define s3c_pm_check_cleanup() do { } while(0)
23755 +#define s3c_pm_check_store()   do { } while(0)
23756 +#endif
23757 +
23758 +/**
23759 + * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
23760 + *
23761 + * Setup all the necessary GPIO pins for waking the system on external
23762 + * interrupt.
23763 + */
23764 +extern void s3c_pm_configure_extint(void);
23765 +
23766 +/**
23767 + * s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
23768 + *
23769 + * Restore the state of the GPIO pins after sleep, which may involve ensuring
23770 + * that we do not glitch the state of the pins from that the bootloader's
23771 + * resume code has done.
23772 +*/
23773 +extern void s3c_pm_restore_gpios(void);
23774 +
23775 +/**
23776 + * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
23777 + *
23778 + * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios().
23779 + */
23780 +extern void s3c_pm_save_gpios(void);
23781 +
23782 +extern void s3c_pm_save_core(void);
23783 +extern void s3c_pm_restore_core(void);
23784 +
23785 --- /dev/null
23786 +++ b/arch/arm/plat-s3c/include/plat/regs-ac97.h
23787 @@ -0,0 +1,67 @@
23788 +/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
23789 + *
23790 + * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
23791 + *             http://www.simtec.co.uk/products/SWLINUX/
23792 + *
23793 + * This program is free software; you can redistribute it and/or modify
23794 + * it under the terms of the GNU General Public License version 2 as
23795 + * published by the Free Software Foundation.
23796 + *
23797 + * S3C2440 AC97 Controller
23798 +*/
23799 +
23800 +#ifndef __ASM_ARCH_REGS_AC97_H
23801 +#define __ASM_ARCH_REGS_AC97_H __FILE__
23802 +
23803 +#define S3C_AC97_GLBCTRL                               (0x00)
23804 +
23805 +#define S3C_AC97_GLBCTRL_CODECREADYIE                  (1<<22)
23806 +#define S3C_AC97_GLBCTRL_PCMOUTURIE                    (1<<21)
23807 +#define S3C_AC97_GLBCTRL_PCMINORIE                     (1<<20)
23808 +#define S3C_AC97_GLBCTRL_MICINORIE                     (1<<19)
23809 +#define S3C_AC97_GLBCTRL_PCMOUTTIE                     (1<<18)
23810 +#define S3C_AC97_GLBCTRL_PCMINTIE                      (1<<17)
23811 +#define S3C_AC97_GLBCTRL_MICINTIE                      (1<<16)
23812 +#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF                  (0<<12)
23813 +#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO                  (1<<12)
23814 +#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA                  (2<<12)
23815 +#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK                 (3<<12)
23816 +#define S3C_AC97_GLBCTRL_PCMINTM_OFF                   (0<<10)
23817 +#define S3C_AC97_GLBCTRL_PCMINTM_PIO                   (1<<10)
23818 +#define S3C_AC97_GLBCTRL_PCMINTM_DMA                   (2<<10)
23819 +#define S3C_AC97_GLBCTRL_PCMINTM_MASK                  (3<<10)
23820 +#define S3C_AC97_GLBCTRL_MICINTM_OFF                   (0<<8)
23821 +#define S3C_AC97_GLBCTRL_MICINTM_PIO                   (1<<8)
23822 +#define S3C_AC97_GLBCTRL_MICINTM_DMA                   (2<<8)
23823 +#define S3C_AC97_GLBCTRL_MICINTM_MASK                  (3<<8)
23824 +#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE            (1<<3)
23825 +#define S3C_AC97_GLBCTRL_ACLINKON                      (1<<2)
23826 +#define S3C_AC97_GLBCTRL_WARMRESET                     (1<<1)
23827 +#define S3C_AC97_GLBCTRL_COLDRESET                     (1<<0)
23828 +
23829 +#define S3C_AC97_GLBSTAT                               (0x04)
23830 +
23831 +#define S3C_AC97_GLBSTAT_CODECREADY                    (1<<22)
23832 +#define S3C_AC97_GLBSTAT_PCMOUTUR                      (1<<21)
23833 +#define S3C_AC97_GLBSTAT_PCMINORI                      (1<<20)
23834 +#define S3C_AC97_GLBSTAT_MICINORI                      (1<<19)
23835 +#define S3C_AC97_GLBSTAT_PCMOUTTI                      (1<<18)
23836 +#define S3C_AC97_GLBSTAT_PCMINTI                       (1<<17)
23837 +#define S3C_AC97_GLBSTAT_MICINTI                       (1<<16)
23838 +#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE                        (0<<0)
23839 +#define S3C_AC97_GLBSTAT_MAINSTATE_INIT                        (1<<0)
23840 +#define S3C_AC97_GLBSTAT_MAINSTATE_READY               (2<<0)
23841 +#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE              (3<<0)
23842 +#define S3C_AC97_GLBSTAT_MAINSTATE_LP                  (4<<0)
23843 +#define S3C_AC97_GLBSTAT_MAINSTATE_WARM                        (5<<0)
23844 +
23845 +#define S3C_AC97_CODEC_CMD                             (0x08)
23846 +
23847 +#define S3C_AC97_CODEC_CMD_READ                                (1<<23)
23848 +
23849 +#define S3C_AC97_STAT                                  (0x0c)
23850 +#define S3C_AC97_PCM_ADDR                              (0x10)
23851 +#define S3C_AC97_PCM_DATA                              (0x18)
23852 +#define S3C_AC97_MIC_DATA                              (0x1C)
23853 +
23854 +#endif /* __ASM_ARCH_REGS_AC97_H */
23855 --- /dev/null
23856 +++ b/arch/arm/plat-s3c/include/plat/regs-fb.h
23857 @@ -0,0 +1,366 @@
23858 +/* arch/arm/plat-s3c/include/plat/regs-fb.h
23859 + *
23860 + * Copyright 2008 Openmoko, Inc.
23861 + * Copyright 2008 Simtec Electronics
23862 + *      http://armlinux.simtec.co.uk/
23863 + *      Ben Dooks <ben@simtec.co.uk>
23864 + *
23865 + * S3C Platform - new-style framebuffer register definitions
23866 + *
23867 + * This is the register set for the new style framebuffer interface
23868 + * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
23869 + * S3C64XX series such as the S3C6400 and S3C6410.
23870 + *
23871 + * The file does not contain the cpu specific items which are based on
23872 + * whichever architecture is selected, it only contains the core of the
23873 + * register set. See <mach/regs-fb.h> to get the specifics.
23874 + *
23875 + * Note, we changed to using regs-fb.h as it avoids any clashes with
23876 + * the original regs-lcd.h so out of the way of regs-lcd.h as well as
23877 + * indicating the newer block is much more than just an LCD interface.
23878 + *
23879 + * This program is free software; you can redistribute it and/or modify
23880 + * it under the terms of the GNU General Public License version 2 as
23881 + * published by the Free Software Foundation.
23882 +*/
23883 +
23884 +/* Please do not include this file directly, use <mach/regs-fb.h> to
23885 + * ensure all the localised SoC support is included as necessary.
23886 +*/
23887 +
23888 +/* VIDCON0 */
23889 +
23890 +#define VIDCON0                                        (0x00)
23891 +#define VIDCON0_INTERLACE                      (1 << 29)
23892 +#define VIDCON0_VIDOUT_MASK                    (0x3 << 26)
23893 +#define VIDCON0_VIDOUT_SHIFT                   (26)
23894 +#define VIDCON0_VIDOUT_RGB                     (0x0 << 26)
23895 +#define VIDCON0_VIDOUT_TV                      (0x1 << 26)
23896 +#define VIDCON0_VIDOUT_I80_LDI0                        (0x2 << 26)
23897 +#define VIDCON0_VIDOUT_I80_LDI1                        (0x3 << 26)
23898 +
23899 +#define VIDCON0_L1_DATA_MASK                   (0x7 << 23)
23900 +#define VIDCON0_L1_DATA_SHIFT                  (23)
23901 +#define VIDCON0_L1_DATA_16BPP                  (0x0 << 23)
23902 +#define VIDCON0_L1_DATA_18BPP16                        (0x1 << 23)
23903 +#define VIDCON0_L1_DATA_18BPP9                 (0x2 << 23)
23904 +#define VIDCON0_L1_DATA_24BPP                  (0x3 << 23)
23905 +#define VIDCON0_L1_DATA_18BPP                  (0x4 << 23)
23906 +#define VIDCON0_L1_DATA_16BPP8                 (0x5 << 23)
23907 +
23908 +#define VIDCON0_L0_DATA_MASK                   (0x7 << 20)
23909 +#define VIDCON0_L0_DATA_SHIFT                  (20)
23910 +#define VIDCON0_L0_DATA_16BPP                  (0x0 << 20)
23911 +#define VIDCON0_L0_DATA_18BPP16                        (0x1 << 20)
23912 +#define VIDCON0_L0_DATA_18BPP9                 (0x2 << 20)
23913 +#define VIDCON0_L0_DATA_24BPP                  (0x3 << 20)
23914 +#define VIDCON0_L0_DATA_18BPP                  (0x4 << 20)
23915 +#define VIDCON0_L0_DATA_16BPP8                 (0x5 << 20)
23916 +
23917 +#define VIDCON0_PNRMODE_MASK                   (0x3 << 17)
23918 +#define VIDCON0_PNRMODE_SHIFT                  (17)
23919 +#define VIDCON0_PNRMODE_RGB                    (0x0 << 17)
23920 +#define VIDCON0_PNRMODE_BGR                    (0x1 << 17)
23921 +#define VIDCON0_PNRMODE_SERIAL_RGB             (0x2 << 17)
23922 +#define VIDCON0_PNRMODE_SERIAL_BGR             (0x3 << 17)
23923 +
23924 +#define VIDCON0_CLKVALUP                       (1 << 16)
23925 +#define VIDCON0_CLKVAL_F_MASK                  (0xff << 6)
23926 +#define VIDCON0_CLKVAL_F_SHIFT                 (6)
23927 +#define VIDCON0_CLKVAL_F_LIMIT                 (0xff)
23928 +#define VIDCON0_CLKVAL_F(_x)                   ((_x) << 6)
23929 +#define VIDCON0_VLCKFREE                       (1 << 5)
23930 +#define VIDCON0_CLKDIR                         (1 << 4)
23931 +
23932 +#define VIDCON0_CLKSEL_MASK                    (0x3 << 2)
23933 +#define VIDCON0_CLKSEL_SHIFT                   (2)
23934 +#define VIDCON0_CLKSEL_HCLK                    (0x0 << 2)
23935 +#define VIDCON0_CLKSEL_LCD                     (0x1 << 2)
23936 +#define VIDCON0_CLKSEL_27M                     (0x3 << 2)
23937 +
23938 +#define VIDCON0_ENVID                          (1 << 1)
23939 +#define VIDCON0_ENVID_F                                (1 << 0)
23940 +
23941 +#define VIDCON1                                        (0x04)
23942 +#define VIDCON1_LINECNT_MASK                   (0x7ff << 16)
23943 +#define VIDCON1_LINECNT_SHIFT                  (16)
23944 +#define VIDCON1_LINECNT_GET(_v)                        (((_v) >> 16) & 0x7ff)
23945 +#define VIDCON1_VSTATUS_MASK                   (0x3 << 13)
23946 +#define VIDCON1_VSTATUS_SHIFT                  (13)
23947 +#define VIDCON1_VSTATUS_VSYNC                  (0x0 << 13)
23948 +#define VIDCON1_VSTATUS_BACKPORCH              (0x1 << 13)
23949 +#define VIDCON1_VSTATUS_ACTIVE                 (0x2 << 13)
23950 +#define VIDCON1_VSTATUS_FRONTPORCH             (0x0 << 13)
23951 +
23952 +#define VIDCON1_INV_VCLK                       (1 << 7)
23953 +#define VIDCON1_INV_HSYNC                      (1 << 6)
23954 +#define VIDCON1_INV_VSYNC                      (1 << 5)
23955 +#define VIDCON1_INV_VDEN                       (1 << 4)
23956 +
23957 +/* VIDCON2 */
23958 +
23959 +#define VIDCON2                                        (0x08)
23960 +#define VIDCON2_EN601                          (1 << 23)
23961 +#define VIDCON2_TVFMTSEL_SW                    (1 << 14)
23962 +
23963 +#define VIDCON2_TVFMTSEL1_MASK                 (0x3 << 12)
23964 +#define VIDCON2_TVFMTSEL1_SHIFT                        (12)
23965 +#define VIDCON2_TVFMTSEL1_RGB                  (0x0 << 12)
23966 +#define VIDCON2_TVFMTSEL1_YUV422               (0x1 << 12)
23967 +#define VIDCON2_TVFMTSEL1_YUV444               (0x2 << 12)
23968 +
23969 +#define VIDCON2_ORGYCbCr                       (1 << 8)
23970 +#define VIDCON2_YUVORDCrCb                     (1 << 7)
23971 +
23972 +/* VIDTCON0 */
23973 +
23974 +#define VIDTCON0_VBPDE_MASK                    (0xff << 24)
23975 +#define VIDTCON0_VBPDE_SHIFT                   (24)
23976 +#define VIDTCON0_VBPDE_LIMIT                   (0xff)
23977 +#define VIDTCON0_VBPDE(_x)                     ((_x) << 24)
23978 +
23979 +#define VIDTCON0_VBPD_MASK                     (0xff << 16)
23980 +#define VIDTCON0_VBPD_SHIFT                    (16)
23981 +#define VIDTCON0_VBPD_LIMIT                    (0xff)
23982 +#define VIDTCON0_VBPD(_x)                      ((_x) << 16)
23983 +
23984 +#define VIDTCON0_VFPD_MASK                     (0xff << 8)
23985 +#define VIDTCON0_VFPD_SHIFT                    (8)
23986 +#define VIDTCON0_VFPD_LIMIT                    (0xff)
23987 +#define VIDTCON0_VFPD(_x)                      ((_x) << 8)
23988 +
23989 +#define VIDTCON0_VSPW_MASK                     (0xff << 0)
23990 +#define VIDTCON0_VSPW_SHIFT                    (0)
23991 +#define VIDTCON0_VSPW_LIMIT                    (0xff)
23992 +#define VIDTCON0_VSPW(_x)                      ((_x) << 0)
23993 +
23994 +/* VIDTCON1 */
23995 +
23996 +#define VIDTCON1_VFPDE_MASK                    (0xff << 24)
23997 +#define VIDTCON1_VFPDE_SHIFT                   (24)
23998 +#define VIDTCON1_VFPDE_LIMIT                   (0xff)
23999 +#define VIDTCON1_VFPDE(_x)                     ((_x) << 24)
24000 +
24001 +#define VIDTCON1_HBPD_MASK                     (0xff << 16)
24002 +#define VIDTCON1_HBPD_SHIFT                    (16)
24003 +#define VIDTCON1_HBPD_LIMIT                    (0xff)
24004 +#define VIDTCON1_HBPD(_x)                      ((_x) << 16)
24005 +
24006 +#define VIDTCON1_HFPD_MASK                     (0xff << 8)
24007 +#define VIDTCON1_HFPD_SHIFT                    (8)
24008 +#define VIDTCON1_HFPD_LIMIT                    (0xff)
24009 +#define VIDTCON1_HFPD(_x)                      ((_x) << 8)
24010 +
24011 +#define VIDTCON1_HSPW_MASK                     (0xff << 0)
24012 +#define VIDTCON1_HSPW_SHIFT                    (0)
24013 +#define VIDTCON1_HSPW_LIMIT                    (0xff)
24014 +#define VIDTCON1_HSPW(_x)                      ((_x) << 0)
24015 +
24016 +#define VIDTCON2                               (0x18)
24017 +#define VIDTCON2_LINEVAL_MASK                  (0x7ff << 11)
24018 +#define VIDTCON2_LINEVAL_SHIFT                 (11)
24019 +#define VIDTCON2_LINEVAL_LIMIT                 (0x7ff)
24020 +#define VIDTCON2_LINEVAL(_x)                   ((_x) << 11)
24021 +
24022 +#define VIDTCON2_HOZVAL_MASK                   (0x7ff << 0)
24023 +#define VIDTCON2_HOZVAL_SHIFT                  (0)
24024 +#define VIDTCON2_HOZVAL_LIMIT                  (0x7ff)
24025 +#define VIDTCON2_HOZVAL(_x)                    ((_x) << 0)
24026 +
24027 +/* WINCONx */
24028 +
24029 +
24030 +#define WINCONx_BITSWP                         (1 << 18)
24031 +#define WINCONx_BYTSWP                         (1 << 17)
24032 +#define WINCONx_HAWSWP                         (1 << 16)
24033 +#define WINCONx_BURSTLEN_MASK                  (0x3 << 9)
24034 +#define WINCONx_BURSTLEN_SHIFT                 (9)
24035 +#define WINCONx_BURSTLEN_16WORD                        (0x0 << 9)
24036 +#define WINCONx_BURSTLEN_8WORD                 (0x1 << 9)
24037 +#define WINCONx_BURSTLEN_4WORD                 (0x2 << 9)
24038 +
24039 +#define WINCONx_ENWIN                          (1 << 0)
24040 +#define WINCON0_BPPMODE_MASK                   (0xf << 2)
24041 +#define WINCON0_BPPMODE_SHIFT                  (2)
24042 +#define WINCON0_BPPMODE_1BPP                   (0x0 << 2)
24043 +#define WINCON0_BPPMODE_2BPP                   (0x1 << 2)
24044 +#define WINCON0_BPPMODE_4BPP                   (0x2 << 2)
24045 +#define WINCON0_BPPMODE_8BPP_PALETTE           (0x3 << 2)
24046 +#define WINCON0_BPPMODE_16BPP_565              (0x5 << 2)
24047 +#define WINCON0_BPPMODE_16BPP_1555             (0x7 << 2)
24048 +#define WINCON0_BPPMODE_18BPP_666              (0x8 << 2)
24049 +#define WINCON0_BPPMODE_24BPP_888              (0xb << 2)
24050 +
24051 +#define WINCON1_BLD_PIX                                (1 << 6)
24052 +
24053 +#define WINCON1_ALPHA_SEL                      (1 << 1)
24054 +#define WINCON1_BPPMODE_MASK                   (0xf << 2)
24055 +#define WINCON1_BPPMODE_SHIFT                  (2)
24056 +#define WINCON1_BPPMODE_1BPP                   (0x0 << 2)
24057 +#define WINCON1_BPPMODE_2BPP                   (0x1 << 2)
24058 +#define WINCON1_BPPMODE_4BPP                   (0x2 << 2)
24059 +#define WINCON1_BPPMODE_8BPP_PALETTE           (0x3 << 2)
24060 +#define WINCON1_BPPMODE_8BPP_1232              (0x4 << 2)
24061 +#define WINCON1_BPPMODE_16BPP_565              (0x5 << 2)
24062 +#define WINCON1_BPPMODE_16BPP_A1555            (0x6 << 2)
24063 +#define WINCON1_BPPMODE_16BPP_I1555            (0x7 << 2)
24064 +#define WINCON1_BPPMODE_18BPP_666              (0x8 << 2)
24065 +#define WINCON1_BPPMODE_18BPP_A1665            (0x9 << 2)
24066 +#define WINCON1_BPPMODE_19BPP_A1666            (0xa << 2)
24067 +#define WINCON1_BPPMODE_24BPP_888              (0xb << 2)
24068 +#define WINCON1_BPPMODE_24BPP_A1887            (0xc << 2)
24069 +#define WINCON1_BPPMODE_25BPP_A1888            (0xd << 2)
24070 +#define WINCON1_BPPMODE_28BPP_A4888            (0xd << 2)
24071 +
24072 +
24073 +#define VIDOSDxA_TOPLEFT_X_MASK                        (0x7ff << 11)
24074 +#define VIDOSDxA_TOPLEFT_X_SHIFT               (11)
24075 +#define VIDOSDxA_TOPLEFT_X_LIMIT               (0x7ff)
24076 +#define VIDOSDxA_TOPLEFT_X(_x)                 ((_x) << 11)
24077 +
24078 +#define VIDOSDxA_TOPLEFT_Y_MASK                        (0x7ff << 0)
24079 +#define VIDOSDxA_TOPLEFT_Y_SHIFT               (0)
24080 +#define VIDOSDxA_TOPLEFT_Y_LIMIT               (0x7ff)
24081 +#define VIDOSDxA_TOPLEFT_Y(_x)                 ((_x) << 0)
24082 +
24083 +#define VIDOSDxB_BOTRIGHT_X_MASK               (0x7ff << 11)
24084 +#define VIDOSDxB_BOTRIGHT_X_SHIFT              (11)
24085 +#define VIDOSDxB_BOTRIGHT_X_LIMIT              (0x7ff)
24086 +#define VIDOSDxB_BOTRIGHT_X(_x)                        ((_x) << 11)
24087 +
24088 +#define VIDOSDxB_BOTRIGHT_Y_MASK               (0x7ff << 0)
24089 +#define VIDOSDxB_BOTRIGHT_Y_SHIFT              (0)
24090 +#define VIDOSDxB_BOTRIGHT_Y_LIMIT              (0x7ff)
24091 +#define VIDOSDxB_BOTRIGHT_Y(_x)                        ((_x) << 0)
24092 +
24093 +/* For VIDOSD[1..4]C */
24094 +#define VIDISD14C_ALPHA0_R(_x)                 ((_x) << 20)
24095 +#define VIDISD14C_ALPHA0_G_MASK                        (0xf << 16)
24096 +#define VIDISD14C_ALPHA0_G_SHIFT               (16)
24097 +#define VIDISD14C_ALPHA0_G_LIMIT               (0xf)
24098 +#define VIDISD14C_ALPHA0_G(_x)                 ((_x) << 16)
24099 +#define VIDISD14C_ALPHA0_B_MASK                        (0xf << 12)
24100 +#define VIDISD14C_ALPHA0_B_SHIFT               (12)
24101 +#define VIDISD14C_ALPHA0_B_LIMIT               (0xf)
24102 +#define VIDISD14C_ALPHA0_B(_x)                 ((_x) << 12)
24103 +#define VIDISD14C_ALPHA1_R_MASK                        (0xf << 8)
24104 +#define VIDISD14C_ALPHA1_R_SHIFT               (8)
24105 +#define VIDISD14C_ALPHA1_R_LIMIT               (0xf)
24106 +#define VIDISD14C_ALPHA1_R(_x)                 ((_x) << 8)
24107 +#define VIDISD14C_ALPHA1_G_MASK                        (0xf << 4)
24108 +#define VIDISD14C_ALPHA1_G_SHIFT               (4)
24109 +#define VIDISD14C_ALPHA1_G_LIMIT               (0xf)
24110 +#define VIDISD14C_ALPHA1_G(_x)                 ((_x) << 4)
24111 +#define VIDISD14C_ALPHA1_B_MASK                        (0xf << 0)
24112 +#define VIDISD14C_ALPHA1_B_SHIFT               (0)
24113 +#define VIDISD14C_ALPHA1_B_LIMIT               (0xf)
24114 +#define VIDISD14C_ALPHA1_B(_x)                 ((_x) << 0)
24115 +
24116 +/* Video buffer addresses */
24117 +#define VIDW_BUF_START(_buff)                  (0xA0 + ((_buff) * 8))
24118 +#define VIDW_BUF_START1(_buff)                 (0xA4 + ((_buff) * 8))
24119 +#define VIDW_BUF_END(_buff)                    (0xD0 + ((_buff) * 8))
24120 +#define VIDW_BUF_END1(_buff)                   (0xD4 + ((_buff) * 8))
24121 +#define VIDW_BUF_SIZE(_buff)                   (0x100 + ((_buff) * 4))
24122 +
24123 +#define VIDW_BUF_SIZE_OFFSET_MASK              (0x1fff << 13)
24124 +#define VIDW_BUF_SIZE_OFFSET_SHIFT             (13)
24125 +#define VIDW_BUF_SIZE_OFFSET_LIMIT             (0x1fff)
24126 +#define VIDW_BUF_SIZE_OFFSET(_x)               ((_x) << 13)
24127 +
24128 +#define VIDW_BUF_SIZE_PAGEWIDTH_MASK           (0x1fff << 0)
24129 +#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT          (0)
24130 +#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT          (0x1fff)
24131 +#define VIDW_BUF_SIZE_PAGEWIDTH(_x)            ((_x) << 0)
24132 +
24133 +/* Interrupt controls and status */
24134 +
24135 +#define VIDINTCON0_FIFOINTERVAL_MASK           (0x3f << 20)
24136 +#define VIDINTCON0_FIFOINTERVAL_SHIFT          (20)
24137 +#define VIDINTCON0_FIFOINTERVAL_LIMIT          (0x3f)
24138 +#define VIDINTCON0_FIFOINTERVAL(_x)            ((_x) << 20)
24139 +
24140 +#define VIDINTCON0_INT_SYSMAINCON              (1 << 19)
24141 +#define VIDINTCON0_INT_SYSSUBCON               (1 << 18)
24142 +#define VIDINTCON0_INT_I80IFDONE               (1 << 17)
24143 +
24144 +#define VIDINTCON0_FRAMESEL0_MASK              (0x3 << 15)
24145 +#define VIDINTCON0_FRAMESEL0_SHIFT             (15)
24146 +#define VIDINTCON0_FRAMESEL0_BACKPORCH         (0x0 << 15)
24147 +#define VIDINTCON0_FRAMESEL0_VSYNC             (0x1 << 15)
24148 +#define VIDINTCON0_FRAMESEL0_ACTIVE            (0x2 << 15)
24149 +#define VIDINTCON0_FRAMESEL0_FRONTPORCH                (0x3 << 15)
24150 +
24151 +#define VIDINTCON0_FRAMESEL1                   (1 << 14)
24152 +#define VIDINTCON0_FRAMESEL1_NONE              (0x0 << 14)
24153 +#define VIDINTCON0_FRAMESEL1_BACKPORCH         (0x1 << 14)
24154 +#define VIDINTCON0_FRAMESEL1_VSYNC             (0x2 << 14)
24155 +#define VIDINTCON0_FRAMESEL1_FRONTPORCH                (0x3 << 14)
24156 +
24157 +#define VIDINTCON0_INT_FRAME                   (1 << 12)
24158 +#define VIDINTCON0_FIFIOSEL_MASK               (0x7f << 5)
24159 +#define VIDINTCON0_FIFIOSEL_SHIFT              (5)
24160 +#define VIDINTCON0_FIFIOSEL_WINDOW0            (0x1 << 5)
24161 +#define VIDINTCON0_FIFIOSEL_WINDOW1            (0x2 << 5)
24162 +
24163 +#define VIDINTCON0_FIFOLEVEL_MASK              (0x7 << 2)
24164 +#define VIDINTCON0_FIFOLEVEL_SHIFT             (2)
24165 +#define VIDINTCON0_FIFOLEVEL_TO25PC            (0x0 << 2)
24166 +#define VIDINTCON0_FIFOLEVEL_TO50PC            (0x1 << 2)
24167 +#define VIDINTCON0_FIFOLEVEL_TO75PC            (0x2 << 2)
24168 +#define VIDINTCON0_FIFOLEVEL_EMPTY             (0x3 << 2)
24169 +#define VIDINTCON0_FIFOLEVEL_FULL              (0x4 << 2)
24170 +
24171 +#define VIDINTCON0_INT_FIFO_MASK               (0x3 << 0)
24172 +#define VIDINTCON0_INT_FIFO_SHIFT              (0)
24173 +#define VIDINTCON0_INT_ENABLE                  (1 << 0)
24174 +
24175 +#define VIDINTCON1                             (0x134)
24176 +#define VIDINTCON1_INT_I180                    (1 << 2)
24177 +#define VIDINTCON1_INT_FRAME                   (1 << 1)
24178 +#define VIDINTCON1_INT_FIFO                    (1 << 0)
24179 +
24180 +/* Window colour-key control registers */
24181 +
24182 +#define WxKEYCON0_KEYBL_EN                     (1 << 26)
24183 +#define WxKEYCON0_KEYEN_F                      (1 << 25)
24184 +#define WxKEYCON0_DIRCON                       (1 << 24)
24185 +#define WxKEYCON0_COMPKEY_MASK                 (0xffffff << 0)
24186 +#define WxKEYCON0_COMPKEY_SHIFT                        (0)
24187 +#define WxKEYCON0_COMPKEY_LIMIT                        (0xffffff)
24188 +#define WxKEYCON0_COMPKEY(_x)                  ((_x) << 0)
24189 +#define WxKEYCON1_COLVAL_MASK                  (0xffffff << 0)
24190 +#define WxKEYCON1_COLVAL_SHIFT                 (0)
24191 +#define WxKEYCON1_COLVAL_LIMIT                 (0xffffff)
24192 +#define WxKEYCON1_COLVAL(_x)                   ((_x) << 0)
24193 +
24194 +
24195 +/* Window blanking (MAP) */
24196 +
24197 +#define WINxMAP_MAP                            (1 << 24)
24198 +#define WINxMAP_MAP_COLOUR_MASK                        (0xffffff << 0)
24199 +#define WINxMAP_MAP_COLOUR_SHIFT               (0)
24200 +#define WINxMAP_MAP_COLOUR_LIMIT               (0xffffff)
24201 +#define WINxMAP_MAP_COLOUR(_x)                 ((_x) << 0)
24202 +
24203 +#define WPALCON_PAL_UPDATE                     (1 << 9)
24204 +#define WPALCON_W1PAL_MASK                     (0x7 << 3)
24205 +#define WPALCON_W1PAL_SHIFT                    (3)
24206 +#define WPALCON_W1PAL_25BPP_A888               (0x0 << 3)
24207 +#define WPALCON_W1PAL_24BPP                    (0x1 << 3)
24208 +#define WPALCON_W1PAL_19BPP_A666               (0x2 << 3)
24209 +#define WPALCON_W1PAL_18BPP_A665               (0x3 << 3)
24210 +#define WPALCON_W1PAL_18BPP                    (0x4 << 3)
24211 +#define WPALCON_W1PAL_16BPP_A555               (0x5 << 3)
24212 +#define WPALCON_W1PAL_16BPP_565                        (0x6 << 3)
24213 +
24214 +#define WPALCON_W0PAL_MASK                     (0x7 << 0)
24215 +#define WPALCON_W0PAL_SHIFT                    (0)
24216 +#define WPALCON_W0PAL_25BPP_A888               (0x0 << 0)
24217 +#define WPALCON_W0PAL_24BPP                    (0x1 << 0)
24218 +#define WPALCON_W0PAL_19BPP_A666               (0x2 << 0)
24219 +#define WPALCON_W0PAL_18BPP_A665               (0x3 << 0)
24220 +#define WPALCON_W0PAL_18BPP                    (0x4 << 0)
24221 +#define WPALCON_W0PAL_16BPP_A555               (0x5 << 0)
24222 +#define WPALCON_W0PAL_16BPP_565                        (0x6 << 0)
24223 +
24224 --- /dev/null
24225 +++ b/arch/arm/plat-s3c/include/plat/regs-iic.h
24226 @@ -0,0 +1,56 @@
24227 +/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
24228 + *
24229 + * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
24230 + *             http://www.simtec.co.uk/products/SWLINUX/
24231 + *
24232 + * This program is free software; you can redistribute it and/or modify
24233 + * it under the terms of the GNU General Public License version 2 as
24234 + * published by the Free Software Foundation.
24235 + *
24236 + * S3C2410 I2C Controller
24237 +*/
24238 +
24239 +#ifndef __ASM_ARCH_REGS_IIC_H
24240 +#define __ASM_ARCH_REGS_IIC_H __FILE__
24241 +
24242 +/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
24243 +
24244 +#define S3C2410_IICREG(x) (x)
24245 +
24246 +#define S3C2410_IICCON    S3C2410_IICREG(0x00)
24247 +#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
24248 +#define S3C2410_IICADD    S3C2410_IICREG(0x08)
24249 +#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
24250 +#define S3C2440_IICLC    S3C2410_IICREG(0x10)
24251 +
24252 +#define S3C2410_IICCON_ACKEN           (1<<7)
24253 +#define S3C2410_IICCON_TXDIV_16                (0<<6)
24254 +#define S3C2410_IICCON_TXDIV_512       (1<<6)
24255 +#define S3C2410_IICCON_IRQEN           (1<<5)
24256 +#define S3C2410_IICCON_IRQPEND         (1<<4)
24257 +#define S3C2410_IICCON_SCALE(x)                ((x)&15)
24258 +#define S3C2410_IICCON_SCALEMASK       (0xf)
24259 +
24260 +#define S3C2410_IICSTAT_MASTER_RX      (2<<6)
24261 +#define S3C2410_IICSTAT_MASTER_TX      (3<<6)
24262 +#define S3C2410_IICSTAT_SLAVE_RX       (0<<6)
24263 +#define S3C2410_IICSTAT_SLAVE_TX       (1<<6)
24264 +#define S3C2410_IICSTAT_MODEMASK       (3<<6)
24265 +
24266 +#define S3C2410_IICSTAT_START          (1<<5)
24267 +#define S3C2410_IICSTAT_BUSBUSY                (1<<5)
24268 +#define S3C2410_IICSTAT_TXRXEN         (1<<4)
24269 +#define S3C2410_IICSTAT_ARBITR         (1<<3)
24270 +#define S3C2410_IICSTAT_ASSLAVE                (1<<2)
24271 +#define S3C2410_IICSTAT_ADDR0          (1<<1)
24272 +#define S3C2410_IICSTAT_LASTBIT                (1<<0)
24273 +
24274 +#define S3C2410_IICLC_SDA_DELAY0       (0 << 0)
24275 +#define S3C2410_IICLC_SDA_DELAY5       (1 << 0)
24276 +#define S3C2410_IICLC_SDA_DELAY10      (2 << 0)
24277 +#define S3C2410_IICLC_SDA_DELAY15      (3 << 0)
24278 +#define S3C2410_IICLC_SDA_DELAY_MASK   (3 << 0)
24279 +
24280 +#define S3C2410_IICLC_FILTER_ON                (1<<2)
24281 +
24282 +#endif /* __ASM_ARCH_REGS_IIC_H */
24283 --- /dev/null
24284 +++ b/arch/arm/plat-s3c/include/plat/regs-irqtype.h
24285 @@ -0,0 +1,21 @@
24286 +/* arch/arm/plat-s3c/include/plat/regs-irqtype.h
24287 + *
24288 + * Copyright 2008 Simtec Electronics
24289 + *      Ben Dooks <ben@simtec.co.uk>
24290 + *      http://armlinux.simtec.co.uk/
24291 + *
24292 + * S3C - IRQ detection types.
24293 + *
24294 + * This program is free software; you can redistribute it and/or modify
24295 + * it under the terms of the GNU General Public License version 2 as
24296 + * published by the Free Software Foundation.
24297 + */
24298 +
24299 +/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including
24300 + * the S3C64XX
24301 +*/
24302 +#define S3C2410_EXTINT_LOWLEV   (0x00)
24303 +#define S3C2410_EXTINT_HILEV    (0x01)
24304 +#define S3C2410_EXTINT_FALLEDGE         (0x02)
24305 +#define S3C2410_EXTINT_RISEEDGE         (0x04)
24306 +#define S3C2410_EXTINT_BOTHEDGE         (0x06)
24307 --- /dev/null
24308 +++ b/arch/arm/plat-s3c/include/plat/regs-nand.h
24309 @@ -0,0 +1,123 @@
24310 +/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
24311 + *
24312 + * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
24313 + *                   http://www.simtec.co.uk/products/SWLINUX/
24314 + *
24315 + * This program is free software; you can redistribute it and/or modify
24316 + * it under the terms of the GNU General Public License version 2 as
24317 + * published by the Free Software Foundation.
24318 + *
24319 + * S3C2410 NAND register definitions
24320 +*/
24321 +
24322 +#ifndef __ASM_ARM_REGS_NAND
24323 +#define __ASM_ARM_REGS_NAND
24324 +
24325 +
24326 +#define S3C2410_NFREG(x) (x)
24327 +
24328 +#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
24329 +#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
24330 +#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
24331 +#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
24332 +#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
24333 +#define S3C2410_NFECC   S3C2410_NFREG(0x14)
24334 +
24335 +#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
24336 +#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
24337 +#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
24338 +#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
24339 +#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
24340 +#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
24341 +#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
24342 +#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
24343 +#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
24344 +#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
24345 +#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
24346 +#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
24347 +#define S3C2440_NFSECC   S3C2410_NFREG(0x34)
24348 +#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
24349 +#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
24350 +
24351 +#define S3C2412_NFSBLK         S3C2410_NFREG(0x20)
24352 +#define S3C2412_NFEBLK         S3C2410_NFREG(0x24)
24353 +#define S3C2412_NFSTAT         S3C2410_NFREG(0x28)
24354 +#define S3C2412_NFMECC_ERR0    S3C2410_NFREG(0x2C)
24355 +#define S3C2412_NFMECC_ERR1    S3C2410_NFREG(0x30)
24356 +#define S3C2412_NFMECC0                S3C2410_NFREG(0x34)
24357 +#define S3C2412_NFMECC1                S3C2410_NFREG(0x38)
24358 +#define S3C2412_NFSECC         S3C2410_NFREG(0x3C)
24359 +
24360 +#define S3C2410_NFCONF_EN          (1<<15)
24361 +#define S3C2410_NFCONF_512BYTE     (1<<14)
24362 +#define S3C2410_NFCONF_4STEP       (1<<13)
24363 +#define S3C2410_NFCONF_INITECC     (1<<12)
24364 +#define S3C2410_NFCONF_nFCE        (1<<11)
24365 +#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
24366 +#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
24367 +#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
24368 +
24369 +#define S3C2410_NFSTAT_BUSY        (1<<0)
24370 +
24371 +#define S3C2440_NFCONF_BUSWIDTH_8      (0<<0)
24372 +#define S3C2440_NFCONF_BUSWIDTH_16     (1<<0)
24373 +#define S3C2440_NFCONF_ADVFLASH                (1<<3)
24374 +#define S3C2440_NFCONF_TACLS(x)                ((x)<<12)
24375 +#define S3C2440_NFCONF_TWRPH0(x)       ((x)<<8)
24376 +#define S3C2440_NFCONF_TWRPH1(x)       ((x)<<4)
24377 +
24378 +#define S3C2440_NFCONT_LOCKTIGHT       (1<<13)
24379 +#define S3C2440_NFCONT_SOFTLOCK                (1<<12)
24380 +#define S3C2440_NFCONT_ILLEGALACC_EN   (1<<10)
24381 +#define S3C2440_NFCONT_RNBINT_EN       (1<<9)
24382 +#define S3C2440_NFCONT_RN_FALLING      (1<<8)
24383 +#define S3C2440_NFCONT_SPARE_ECCLOCK   (1<<6)
24384 +#define S3C2440_NFCONT_MAIN_ECCLOCK    (1<<5)
24385 +#define S3C2440_NFCONT_INITECC         (1<<4)
24386 +#define S3C2440_NFCONT_nFCE            (1<<1)
24387 +#define S3C2440_NFCONT_ENABLE          (1<<0)
24388 +
24389 +#define S3C2440_NFSTAT_READY           (1<<0)
24390 +#define S3C2440_NFSTAT_nCE             (1<<1)
24391 +#define S3C2440_NFSTAT_RnB_CHANGE      (1<<2)
24392 +#define S3C2440_NFSTAT_ILLEGAL_ACCESS  (1<<3)
24393 +
24394 +#define S3C2412_NFCONF_NANDBOOT                (1<<31)
24395 +#define S3C2412_NFCONF_ECCCLKCON       (1<<30)
24396 +#define S3C2412_NFCONF_ECC_MLC         (1<<24)
24397 +#define S3C2412_NFCONF_TACLS_MASK      (7<<12) /* 1 extra bit of Tacls */
24398 +
24399 +#define S3C2412_NFCONT_ECC4_DIRWR      (1<<18)
24400 +#define S3C2412_NFCONT_LOCKTIGHT       (1<<17)
24401 +#define S3C2412_NFCONT_SOFTLOCK                (1<<16)
24402 +#define S3C2412_NFCONT_ECC4_ENCINT     (1<<13)
24403 +#define S3C2412_NFCONT_ECC4_DECINT     (1<<12)
24404 +#define S3C2412_NFCONT_MAIN_ECC_LOCK   (1<<7)
24405 +#define S3C2412_NFCONT_INIT_MAIN_ECC   (1<<5)
24406 +#define S3C2412_NFCONT_nFCE1           (1<<2)
24407 +#define S3C2412_NFCONT_nFCE0           (1<<1)
24408 +
24409 +#define S3C2412_NFSTAT_ECC_ENCDONE     (1<<7)
24410 +#define S3C2412_NFSTAT_ECC_DECDONE     (1<<6)
24411 +#define S3C2412_NFSTAT_ILLEGAL_ACCESS  (1<<5)
24412 +#define S3C2412_NFSTAT_RnB_CHANGE      (1<<4)
24413 +#define S3C2412_NFSTAT_nFCE1           (1<<3)
24414 +#define S3C2412_NFSTAT_nFCE0           (1<<2)
24415 +#define S3C2412_NFSTAT_Res1            (1<<1)
24416 +#define S3C2412_NFSTAT_READY           (1<<0)
24417 +
24418 +#define S3C2412_NFECCERR_SERRDATA(x)   (((x) >> 21) & 0xf)
24419 +#define S3C2412_NFECCERR_SERRBIT(x)    (((x) >> 18) & 0x7)
24420 +#define S3C2412_NFECCERR_MERRDATA(x)   (((x) >> 7) & 0x3ff)
24421 +#define S3C2412_NFECCERR_MERRBIT(x)    (((x) >> 4) & 0x7)
24422 +#define S3C2412_NFECCERR_SPARE_ERR(x)  (((x) >> 2) & 0x3)
24423 +#define S3C2412_NFECCERR_MAIN_ERR(x)   (((x) >> 2) & 0x3)
24424 +#define S3C2412_NFECCERR_NONE          (0)
24425 +#define S3C2412_NFECCERR_1BIT          (1)
24426 +#define S3C2412_NFECCERR_MULTIBIT      (2)
24427 +#define S3C2412_NFECCERR_ECCAREA       (3)
24428 +
24429 +
24430 +
24431 +#endif /* __ASM_ARM_REGS_NAND */
24432 +
24433 --- /dev/null
24434 +++ b/arch/arm/plat-s3c/include/plat/regs-rtc.h
24435 @@ -0,0 +1,61 @@
24436 +/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
24437 + *
24438 + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
24439 + *                   http://www.simtec.co.uk/products/SWLINUX/
24440 + *
24441 + * This program is free software; you can redistribute it and/or modify
24442 + * it under the terms of the GNU General Public License version 2 as
24443 + * published by the Free Software Foundation.
24444 + *
24445 + * S3C2410 Internal RTC register definition
24446 +*/
24447 +
24448 +#ifndef __ASM_ARCH_REGS_RTC_H
24449 +#define __ASM_ARCH_REGS_RTC_H __FILE__
24450 +
24451 +#define S3C2410_RTCREG(x) (x)
24452 +
24453 +#define S3C2410_RTCCON       S3C2410_RTCREG(0x40)
24454 +#define S3C2410_RTCCON_RTCEN  (1<<0)
24455 +#define S3C2410_RTCCON_CLKSEL (1<<1)
24456 +#define S3C2410_RTCCON_CNTSEL (1<<2)
24457 +#define S3C2410_RTCCON_CLKRST (1<<3)
24458 +
24459 +#define S3C2410_TICNT        S3C2410_RTCREG(0x44)
24460 +#define S3C2410_TICNT_ENABLE  (1<<7)
24461 +
24462 +#define S3C2410_RTCALM       S3C2410_RTCREG(0x50)
24463 +#define S3C2410_RTCALM_ALMEN  (1<<6)
24464 +#define S3C2410_RTCALM_YEAREN (1<<5)
24465 +#define S3C2410_RTCALM_MONEN  (1<<4)
24466 +#define S3C2410_RTCALM_DAYEN  (1<<3)
24467 +#define S3C2410_RTCALM_HOUREN (1<<2)
24468 +#define S3C2410_RTCALM_MINEN  (1<<1)
24469 +#define S3C2410_RTCALM_SECEN  (1<<0)
24470 +
24471 +#define S3C2410_RTCALM_ALL \
24472 +  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
24473 +  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
24474 +  S3C2410_RTCALM_SECEN
24475 +
24476 +
24477 +#define S3C2410_ALMSEC       S3C2410_RTCREG(0x54)
24478 +#define S3C2410_ALMMIN       S3C2410_RTCREG(0x58)
24479 +#define S3C2410_ALMHOUR              S3C2410_RTCREG(0x5c)
24480 +
24481 +#define S3C2410_ALMDATE              S3C2410_RTCREG(0x60)
24482 +#define S3C2410_ALMMON       S3C2410_RTCREG(0x64)
24483 +#define S3C2410_ALMYEAR              S3C2410_RTCREG(0x68)
24484 +
24485 +#define S3C2410_RTCRST       S3C2410_RTCREG(0x6c)
24486 +
24487 +#define S3C2410_RTCSEC       S3C2410_RTCREG(0x70)
24488 +#define S3C2410_RTCMIN       S3C2410_RTCREG(0x74)
24489 +#define S3C2410_RTCHOUR              S3C2410_RTCREG(0x78)
24490 +#define S3C2410_RTCDATE              S3C2410_RTCREG(0x7c)
24491 +#define S3C2410_RTCDAY       S3C2410_RTCREG(0x80)
24492 +#define S3C2410_RTCMON       S3C2410_RTCREG(0x84)
24493 +#define S3C2410_RTCYEAR              S3C2410_RTCREG(0x88)
24494 +
24495 +
24496 +#endif /* __ASM_ARCH_REGS_RTC_H */
24497 --- /dev/null
24498 +++ b/arch/arm/plat-s3c/include/plat/regs-sdhci.h
24499 @@ -0,0 +1,87 @@
24500 +/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
24501 + *
24502 + * Copyright 2008 Openmoko, Inc.
24503 + * Copyright 2008 Simtec Electronics
24504 + *     http://armlinux.simtec.co.uk/
24505 + *     Ben Dooks <ben@simtec.co.uk>
24506 + *
24507 + * S3C Platform - SDHCI (HSMMC) register definitions
24508 + *
24509 + * This program is free software; you can redistribute it and/or modify
24510 + * it under the terms of the GNU General Public License version 2 as
24511 + * published by the Free Software Foundation.
24512 +*/
24513 +
24514 +#ifndef __PLAT_S3C_SDHCI_REGS_H
24515 +#define __PLAT_S3C_SDHCI_REGS_H __FILE__
24516 +
24517 +#define S3C_SDHCI_CONTROL2                     (0x80)
24518 +#define S3C_SDHCI_CONTROL3                     (0x84)
24519 +#define S3C64XX_SDHCI_CONTROL4                 (0x8C)
24520 +
24521 +#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR      (1 << 31)
24522 +#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK                (1 << 30)
24523 +#define S3C_SDHCI_CTRL2_CDINVRXD3              (1 << 29)
24524 +#define S3C_SDHCI_CTRL2_SLCARDOUT              (1 << 28)
24525 +
24526 +#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK         (0xf << 24)
24527 +#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT                (24)
24528 +#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x)          ((_x) << 24)
24529 +
24530 +#define S3C_SDHCI_CTRL2_LVLDAT_MASK            (0xff << 16)
24531 +#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT           (16)
24532 +#define S3C_SDHCI_CTRL2_LVLDAT(_x)             ((_x) << 16)
24533 +
24534 +#define S3C_SDHCI_CTRL2_ENFBCLKTX              (1 << 15)
24535 +#define S3C_SDHCI_CTRL2_ENFBCLKRX              (1 << 14)
24536 +#define S3C_SDHCI_CTRL2_SDCDSEL                        (1 << 13)
24537 +#define S3C_SDHCI_CTRL2_SDSIGPC                        (1 << 12)
24538 +#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART       (1 << 11)
24539 +
24540 +#define S3C_SDHCI_CTRL2_DFCNT_MASK             (0x3 << 9)
24541 +#define S3C_SDHCI_CTRL2_DFCNT_SHIFT            (9)
24542 +#define S3C_SDHCI_CTRL2_DFCNT_NONE             (0x0 << 9)
24543 +#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK           (0x1 << 9)
24544 +#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK          (0x2 << 9)
24545 +#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK          (0x3 << 9)
24546 +
24547 +#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD           (1 << 8)
24548 +#define S3C_SDHCI_CTRL2_RWAITMODE              (1 << 7)
24549 +#define S3C_SDHCI_CTRL2_DISBUFRD               (1 << 6)
24550 +#define S3C_SDHCI_CTRL2_SELBASECLK_MASK                (0x3 << 4)
24551 +#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT       (4)
24552 +#define S3C_SDHCI_CTRL2_PWRSYNC                        (1 << 3)
24553 +#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON         (1 << 1)
24554 +#define S3C_SDHCI_CTRL2_HWINITFIN              (1 << 0)
24555 +
24556 +#define S3C_SDHCI_CTRL3_FCSEL3                 (1 << 31)
24557 +#define S3C_SDHCI_CTRL3_FCSEL2                 (1 << 23)
24558 +#define S3C_SDHCI_CTRL3_FCSEL1                 (1 << 15)
24559 +#define S3C_SDHCI_CTRL3_FCSEL0                 (1 << 7)
24560 +
24561 +#define S3C_SDHCI_CTRL3_FIA3_MASK              (0x7f << 24)
24562 +#define S3C_SDHCI_CTRL3_FIA3_SHIFT             (24)
24563 +#define S3C_SDHCI_CTRL3_FIA3(_x)               ((_x) << 24)
24564 +
24565 +#define S3C_SDHCI_CTRL3_FIA2_MASK              (0x7f << 16)
24566 +#define S3C_SDHCI_CTRL3_FIA2_SHIFT             (16)
24567 +#define S3C_SDHCI_CTRL3_FIA2(_x)               ((_x) << 16)
24568 +
24569 +#define S3C_SDHCI_CTRL3_FIA1_MASK              (0x7f << 8)
24570 +#define S3C_SDHCI_CTRL3_FIA1_SHIFT             (8)
24571 +#define S3C_SDHCI_CTRL3_FIA1(_x)               ((_x) << 8)
24572 +
24573 +#define S3C_SDHCI_CTRL3_FIA0_MASK              (0x7f << 0)
24574 +#define S3C_SDHCI_CTRL3_FIA0_SHIFT             (0)
24575 +#define S3C_SDHCI_CTRL3_FIA0(_x)               ((_x) << 0)
24576 +
24577 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK      (0x3 << 16)
24578 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT     (16)
24579 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA       (0x0 << 16)
24580 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA       (0x1 << 16)
24581 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA       (0x2 << 16)
24582 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA       (0x3 << 16)
24583 +
24584 +#define S3C64XX_SDHCI_CONTROL4_BUSY            (1)
24585 +
24586 +#endif /* __PLAT_S3C_SDHCI_REGS_H */
24587 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h
24588 +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
24589 @@ -77,6 +77,12 @@
24590  #define S3C2440_UCON_FCLK        (3<<10)
24591  #define S3C2443_UCON_EPLL        (3<<10)
24592
24593 +#define S3C6400_UCON_CLKMASK   (3<<10)
24594 +#define S3C6400_UCON_PCLK      (0<<10)
24595 +#define S3C6400_UCON_PCLK2     (2<<10)
24596 +#define S3C6400_UCON_UCLK0     (1<<10)
24597 +#define S3C6400_UCON_UCLK1     (3<<10)
24598 +
24599  #define S3C2440_UCON2_FCLK_EN    (1<<15)
24600  #define S3C2440_UCON0_DIVMASK    (15 << 12)
24601  #define S3C2440_UCON1_DIVMASK    (15 << 12)
24602 @@ -149,6 +155,14 @@
24603  #define S3C2410_UFSTAT_RXMASK    (15<<0)
24604  #define S3C2410_UFSTAT_RXSHIFT   (0)
24605
24606 +/* UFSTAT S3C24A0 */
24607 +#define S3C24A0_UFSTAT_TXFULL    (1 << 14)
24608 +#define S3C24A0_UFSTAT_RXFULL    (1 << 6)
24609 +#define S3C24A0_UFSTAT_TXMASK    (63 << 8)
24610 +#define S3C24A0_UFSTAT_TXSHIFT   (8)
24611 +#define S3C24A0_UFSTAT_RXMASK    (63)
24612 +#define S3C24A0_UFSTAT_RXSHIFT   (0)
24613 +
24614  /* UFSTAT S3C2443 same as S3C2440 */
24615  #define S3C2440_UFSTAT_TXFULL    (1<<14)
24616  #define S3C2440_UFSTAT_RXFULL    (1<<6)
24617 @@ -175,6 +189,11 @@
24618
24619  #define S3C2443_DIVSLOT                  (0x2C)
24620
24621 +/* S3C64XX interrupt registers. */
24622 +#define S3C64XX_UINTP          0x30
24623 +#define S3C64XX_UINTSP         0x34
24624 +#define S3C64XX_UINTM          0x38
24625 +
24626  #ifndef __ASSEMBLY__
24627
24628  /* struct s3c24xx_uart_clksrc
24629 @@ -224,7 +243,7 @@ struct s3c2410_uartcfg {
24630   * or platform_add_device() before the console_initcall()
24631  */
24632
24633 -extern struct platform_device *s3c24xx_uart_devs[3];
24634 +extern struct platform_device *s3c24xx_uart_devs[4];
24635
24636  #endif /* __ASSEMBLY__ */
24637
24638 --- a/arch/arm/plat-s3c/include/plat/regs-timer.h
24639 +++ b/arch/arm/plat-s3c/include/plat/regs-timer.h
24640 @@ -10,7 +10,6 @@
24641   * S3C2410 Timer configuration
24642  */
24643
24644 -
24645  #ifndef __ASM_ARCH_REGS_TIMER_H
24646  #define __ASM_ARCH_REGS_TIMER_H
24647
24648 @@ -21,6 +20,8 @@
24649  #define S3C2410_TCFG1        S3C_TIMERREG(0x04)
24650  #define S3C2410_TCON         S3C_TIMERREG(0x08)
24651
24652 +#define S3C64XX_TINT_CSTAT    S3C_TIMERREG(0x44)
24653 +
24654  #define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
24655  #define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
24656  #define S3C2410_TCFG_PRESCALER1_SHIFT (8)
24657 @@ -72,6 +73,14 @@
24658  #define S3C2410_TCFG1_MUX_TCLK    (4<<0)
24659  #define S3C2410_TCFG1_MUX_MASK   (15<<0)
24660
24661 +#define S3C64XX_TCFG1_MUX_DIV1   (0<<0)
24662 +#define S3C64XX_TCFG1_MUX_DIV2   (1<<0)
24663 +#define S3C64XX_TCFG1_MUX_DIV4   (2<<0)
24664 +#define S3C64XX_TCFG1_MUX_DIV8    (3<<0)
24665 +#define S3C64XX_TCFG1_MUX_DIV16   (4<<0)
24666 +#define S3C64XX_TCFG1_MUX_TCLK    (5<<0)  /* 3 sets of TCLK */
24667 +#define S3C64XX_TCFG1_MUX_MASK   (15<<0)
24668 +
24669  #define S3C2410_TCFG1_SHIFT(x)   ((x) * 4)
24670
24671  /* for each timer, we have an count buffer, an compare buffer and
24672 --- /dev/null
24673 +++ b/arch/arm/plat-s3c/include/plat/regs-watchdog.h
24674 @@ -0,0 +1,41 @@
24675 +/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
24676 + *
24677 + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
24678 + *                   http://www.simtec.co.uk/products/SWLINUX/
24679 + *
24680 + * This program is free software; you can redistribute it and/or modify
24681 + * it under the terms of the GNU General Public License version 2 as
24682 + * published by the Free Software Foundation.
24683 + *
24684 + * S3C2410 Watchdog timer control
24685 +*/
24686 +
24687 +
24688 +#ifndef __ASM_ARCH_REGS_WATCHDOG_H
24689 +#define __ASM_ARCH_REGS_WATCHDOG_H
24690 +
24691 +#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
24692 +
24693 +#define S3C2410_WTCON     S3C_WDOGREG(0x00)
24694 +#define S3C2410_WTDAT     S3C_WDOGREG(0x04)
24695 +#define S3C2410_WTCNT     S3C_WDOGREG(0x08)
24696 +
24697 +/* the watchdog can either generate a reset pulse, or an
24698 + * interrupt.
24699 + */
24700 +
24701 +#define S3C2410_WTCON_RSTEN   (0x01)
24702 +#define S3C2410_WTCON_INTEN   (1<<2)
24703 +#define S3C2410_WTCON_ENABLE  (1<<5)
24704 +
24705 +#define S3C2410_WTCON_DIV16   (0<<3)
24706 +#define S3C2410_WTCON_DIV32   (1<<3)
24707 +#define S3C2410_WTCON_DIV64   (2<<3)
24708 +#define S3C2410_WTCON_DIV128  (3<<3)
24709 +
24710 +#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
24711 +#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
24712 +
24713 +#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
24714 +
24715 +
24716 --- /dev/null
24717 +++ b/arch/arm/plat-s3c/include/plat/sdhci.h
24718 @@ -0,0 +1,112 @@
24719 +/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
24720 + *
24721 + * Copyright 2008 Openmoko, Inc.
24722 + * Copyright 2008 Simtec Electronics
24723 + *     http://armlinux.simtec.co.uk/
24724 + *     Ben Dooks <ben@simtec.co.uk>
24725 + *
24726 + * S3C Platform - SDHCI (HSMMC) platform data definitions
24727 + *
24728 + * This program is free software; you can redistribute it and/or modify
24729 + * it under the terms of the GNU General Public License version 2 as
24730 + * published by the Free Software Foundation.
24731 +*/
24732 +
24733 +#ifndef __PLAT_S3C_SDHCI_H
24734 +#define __PLAT_S3C_SDHCI_H __FILE__
24735 +
24736 +struct platform_device;
24737 +struct mmc_host;
24738 +struct mmc_card;
24739 +struct mmc_ios;
24740 +
24741 +/**
24742 + * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
24743 + * @max_width: The maximum number of data bits supported.
24744 + * @host_caps: Standard MMC host capabilities bit field.
24745 + * @cfg_gpio: Configure the GPIO for a specific card bit-width
24746 + * @cfg_card: Configure the interface for a specific card and speed. This
24747 + *            is necessary the controllers and/or GPIO blocks require the
24748 + *           changing of driver-strength and other controls dependant on
24749 + *           the card and speed of operation.
24750 + * sdhci_host: Pointer kept during init, allows presence change notification
24751 + *
24752 + * Initialisation data specific to either the machine or the platform
24753 + * for the device driver to use or call-back when configuring gpio or
24754 + * card speed information.
24755 +*/
24756 +struct s3c_sdhci_platdata {
24757 +       unsigned int    max_width;
24758 +       unsigned int    host_caps;
24759 +
24760 +       char            **clocks;       /* set of clock sources */
24761 +
24762 +       void    (*cfg_gpio)(struct platform_device *dev, int width);
24763 +       void    (*cfg_card)(struct platform_device *dev,
24764 +                           void __iomem *regbase,
24765 +                           struct mmc_ios *ios,
24766 +                           struct mmc_card *card);
24767 +       struct sdhci_host * sdhci_host;
24768 +};
24769 +
24770 +extern void sdhci_s3c_force_presence_change(struct platform_device *pdev);
24771 +
24772 +/**
24773 + * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
24774 + * @pd: Platform data to register to device.
24775 + *
24776 + * Register the given platform data for use withe S3C SDHCI device.
24777 + * The call will copy the platform data, so the board definitions can
24778 + * make the structure itself __initdata.
24779 + */
24780 +extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
24781 +extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
24782 +
24783 +/* Default platform data, exported so that per-cpu initialisation can
24784 + * set the correct one when there are more than one cpu type selected.
24785 +*/
24786 +
24787 +extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
24788 +extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
24789 +
24790 +/* Helper function availablity */
24791 +
24792 +#ifdef CONFIG_S3C6410_SETUP_SDHCI
24793 +extern char *s3c6410_hsmmc_clksrcs[4];
24794 +
24795 +extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
24796 +extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
24797 +
24798 +extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
24799 +                                          void __iomem *r,
24800 +                                          struct mmc_ios *ios,
24801 +                                          struct mmc_card *card);
24802 +
24803 +#ifdef CONFIG_S3C_DEV_HSMMC
24804 +static inline void s3c6410_default_sdhci0(void)
24805 +{
24806 +       s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
24807 +       s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
24808 +       s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
24809 +}
24810 +#else
24811 +static inline void s3c6410_default_sdhci0(void) { }
24812 +#endif /* CONFIG_S3C_DEV_HSMMC */
24813 +
24814 +#ifdef CONFIG_S3C_DEV_HSMMC1
24815 +static inline void s3c6410_default_sdhci1(void)
24816 +{
24817 +       s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
24818 +       s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
24819 +       s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
24820 +}
24821 +#else
24822 +static inline void s3c6410_default_sdhci1(void) { }
24823 +#endif /* CONFIG_S3C_DEV_HSMMC1 */
24824 +
24825 +#else
24826 +static inline void s3c6410_default_sdhci0(void) { }
24827 +static inline void s3c6410_default_sdhci1(void) { }
24828 +#endif /* CONFIG_S3C6410_SETUP_SDHCI */
24829 +
24830 +#endif /* __PLAT_S3C_SDHCI_H */
24831 --- a/arch/arm/plat-s3c/include/plat/uncompress.h
24832 +++ b/arch/arm/plat-s3c/include/plat/uncompress.h
24833 @@ -28,7 +28,7 @@ static void arch_detect_cpu(void);
24834  /* defines for UART registers */
24835
24836  #include <plat/regs-serial.h>
24837 -#include <asm/plat-s3c/regs-watchdog.h>
24838 +#include <plat/regs-watchdog.h>
24839
24840  /* working in physical space... */
24841  #undef S3C2410_WDOGREG
24842 @@ -37,7 +37,7 @@ static void arch_detect_cpu(void);
24843  /* how many bytes we allow into the FIFO at a time in FIFO mode */
24844  #define FIFO_MAX        (14)
24845
24846 -#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
24847 +#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
24848
24849  static __inline__ void
24850  uart_wr(unsigned int reg, unsigned int val)
24851 @@ -139,6 +139,28 @@ static void arch_decomp_error(const char
24852
24853  static void error(char *err);
24854
24855 +#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
24856 +static inline void arch_enable_uart_fifo(void)
24857 +{
24858 +       u32 fifocon = uart_rd(S3C2410_UFCON);
24859 +
24860 +       if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
24861 +               fifocon |= S3C2410_UFCON_RESETBOTH;
24862 +               uart_wr(S3C2410_UFCON, fifocon);
24863 +
24864 +               /* wait for fifo reset to complete */
24865 +               while (1) {
24866 +                       fifocon = uart_rd(S3C2410_UFCON);
24867 +                       if (!(fifocon & S3C2410_UFCON_RESETBOTH))
24868 +                               break;
24869 +               }
24870 +       }
24871 +}
24872 +#else
24873 +#define arch_enable_uart_fifo() do { } while(0)
24874 +#endif
24875 +
24876 +
24877  static void
24878  arch_decomp_setup(void)
24879  {
24880 @@ -149,6 +171,12 @@ arch_decomp_setup(void)
24881
24882         arch_detect_cpu();
24883         arch_decomp_wdog_start();
24884 +
24885 +       /* Enable the UART FIFOs if they where not enabled and our
24886 +        * configuration says we should turn them on.
24887 +        */
24888 +
24889 +       arch_enable_uart_fifo();
24890  }
24891
24892
24893 --- /dev/null
24894 +++ b/arch/arm/plat-s3c/init.c
24895 @@ -0,0 +1,161 @@
24896 +/* linux/arch/arm/plat-s3c/init.c
24897 + *
24898 + * Copyright (c) 2008 Simtec Electronics
24899 + *     Ben Dooks <ben@simtec.co.uk>
24900 + *     http://armlinux.simtec.co.uk/
24901 + *
24902 + * S3C series CPU initialisation
24903 + *
24904 + * This program is free software; you can redistribute it and/or modify
24905 + * it under the terms of the GNU General Public License version 2 as
24906 + * published by the Free Software Foundation.
24907 +*/
24908 +
24909 +#include <linux/init.h>
24910 +#include <linux/module.h>
24911 +#include <linux/interrupt.h>
24912 +#include <linux/ioport.h>
24913 +#include <linux/serial_core.h>
24914 +#include <linux/platform_device.h>
24915 +#include <linux/delay.h>
24916 +
24917 +#include <mach/hardware.h>
24918 +
24919 +#include <asm/mach/arch.h>
24920 +#include <asm/mach/map.h>
24921 +
24922 +#include <plat/cpu.h>
24923 +#include <plat/devs.h>
24924 +#include <plat/clock.h>
24925 +
24926 +#include <plat/regs-serial.h>
24927 +
24928 +static struct cpu_table *cpu;
24929 +
24930 +static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
24931 +                                               struct cpu_table *tab,
24932 +                                               unsigned int count)
24933 +{
24934 +       for (; count != 0; count--, tab++) {
24935 +               if ((idcode & tab->idmask) == tab->idcode)
24936 +                       return tab;
24937 +       }
24938 +
24939 +       return NULL;
24940 +}
24941 +
24942 +void __init s3c_init_cpu(unsigned long idcode,
24943 +                        struct cpu_table *cputab, unsigned int cputab_size)
24944 +{
24945 +       cpu = s3c_lookup_cpu(idcode, cputab, cputab_size);
24946 +
24947 +       if (cpu == NULL) {
24948 +               printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
24949 +               panic("Unknown S3C24XX CPU");
24950 +       }
24951 +
24952 +       printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
24953 +
24954 +       if (cpu->map_io == NULL || cpu->init == NULL) {
24955 +               printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
24956 +               panic("Unsupported Samsung CPU");
24957 +       }
24958 +
24959 +       cpu->map_io();
24960 +}
24961 +
24962 +/* s3c24xx_init_clocks
24963 + *
24964 + * Initialise the clock subsystem and associated information from the
24965 + * given master crystal value.
24966 + *
24967 + * xtal  = 0 -> use default PLL crystal value (normally 12MHz)
24968 + *      != 0 -> PLL crystal value in Hz
24969 +*/
24970 +
24971 +void __init s3c24xx_init_clocks(int xtal)
24972 +{
24973 +       if (xtal == 0)
24974 +               xtal = 12*1000*1000;
24975 +
24976 +       if (cpu == NULL)
24977 +               panic("s3c24xx_init_clocks: no cpu setup?\n");
24978 +
24979 +       if (cpu->init_clocks == NULL)
24980 +               panic("s3c24xx_init_clocks: cpu has no clock init\n");
24981 +       else
24982 +               (cpu->init_clocks)(xtal);
24983 +}
24984 +
24985 +/* uart management */
24986 +
24987 +static int nr_uarts __initdata = 0;
24988 +
24989 +static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
24990 +
24991 +/* s3c24xx_init_uartdevs
24992 + *
24993 + * copy the specified platform data and configuration into our central
24994 + * set of devices, before the data is thrown away after the init process.
24995 + *
24996 + * This also fills in the array passed to the serial driver for the
24997 + * early initialisation of the console.
24998 +*/
24999 +
25000 +void __init s3c24xx_init_uartdevs(char *name,
25001 +                                 struct s3c24xx_uart_resources *res,
25002 +                                 struct s3c2410_uartcfg *cfg, int no)
25003 +{
25004 +       struct platform_device *platdev;
25005 +       struct s3c2410_uartcfg *cfgptr = uart_cfgs;
25006 +       struct s3c24xx_uart_resources *resp;
25007 +       int uart;
25008 +
25009 +       memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
25010 +
25011 +       for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
25012 +               platdev = s3c24xx_uart_src[cfgptr->hwport];
25013 +
25014 +               resp = res + cfgptr->hwport;
25015 +
25016 +               s3c24xx_uart_devs[uart] = platdev;
25017 +
25018 +               platdev->name = name;
25019 +               platdev->resource = resp->resources;
25020 +               platdev->num_resources = resp->nr_resources;
25021 +
25022 +               platdev->dev.platform_data = cfgptr;
25023 +       }
25024 +
25025 +       nr_uarts = no;
25026 +}
25027 +
25028 +void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
25029 +{
25030 +       if (cpu == NULL)
25031 +               return;
25032 +
25033 +       if (cpu->init_uarts == NULL) {
25034 +               printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
25035 +       } else
25036 +               (cpu->init_uarts)(cfg, no);
25037 +}
25038 +
25039 +static int __init s3c_arch_init(void)
25040 +{
25041 +       int ret;
25042 +
25043 +       // do the correct init for cpu
25044 +
25045 +       if (cpu == NULL)
25046 +               panic("s3c_arch_init: NULL cpu\n");
25047 +
25048 +       ret = (cpu->init)();
25049 +       if (ret != 0)
25050 +               return ret;
25051 +
25052 +       ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
25053 +       return ret;
25054 +}
25055 +
25056 +arch_initcall(s3c_arch_init);
25057 --- a/arch/arm/plat-s3c/Kconfig
25058 +++ b/arch/arm/plat-s3c/Kconfig
25059 @@ -6,8 +6,8 @@
25060
25061  config PLAT_S3C
25062         bool
25063 -       depends on ARCH_S3C2410
25064 -       default y if ARCH_S3C2410
25065 +       depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX
25066 +       default y
25067         select NO_IOPORT
25068         help
25069           Base platform code for any Samsung S3C device
25070 @@ -16,24 +16,24 @@ config PLAT_S3C
25071
25072  config CPU_LLSERIAL_S3C2410_ONLY
25073         bool
25074 -       depends on ARCH_S3C2410
25075 +       depends on PLAT_S3C
25076         default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
25077
25078  config CPU_LLSERIAL_S3C2440_ONLY
25079         bool
25080 -       depends on ARCH_S3C2410
25081 +       depends on PLAT_S3C
25082         default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
25083
25084  config CPU_LLSERIAL_S3C2410
25085         bool
25086 -       depends on ARCH_S3C2410
25087 +       depends on PLAT_S3C
25088         help
25089           Selected if there is an S3C2410 (or register compatible) serial
25090           low-level implementation needed
25091
25092  config CPU_LLSERIAL_S3C2440
25093         bool
25094 -       depends on ARCH_S3C2410
25095 +       depends on PLAT_S3C
25096         help
25097           Selected if there is an S3C2440 (or register compatible) serial
25098           low-level implementation needed
25099 @@ -57,6 +57,14 @@ config S3C_BOOT_ERROR_RESET
25100           Say y here to use the watchdog to reset the system if the
25101           kernel decompressor detects an error during decompression.
25102
25103 +config S3C_BOOT_UART_FORCE_FIFO
25104 +       bool "Force UART FIFO on during boot process"
25105 +       depends on PLAT_S3C
25106 +       default y
25107 +       help
25108 +         Say Y here to force the UART FIFOs on during the kernel
25109 +        uncompressor
25110 +
25111  comment "Power management"
25112
25113  config S3C2410_PM_DEBUG
25114 @@ -67,6 +75,15 @@ config S3C2410_PM_DEBUG
25115           Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
25116           for more information.
25117
25118 +config S3C_PM_DEBUG_LED_SMDK
25119 +       bool "SMDK LED suspend/resume debugging"
25120 +       depends on PM && (MACH_SMDK6410)
25121 +       help
25122 +         Say Y here to enable the use of the SMDK LEDs on the baseboard
25123 +        for debugging of the state of the suspend and resume process.
25124 +
25125 +        Note, this currently only works for S3C64XX based SMDK boards.
25126 +
25127  config S3C2410_PM_CHECK
25128         bool "S3C2410 PM Suspend Memory CRC"
25129         depends on PLAT_S3C && PM && CRC32
25130 @@ -102,3 +119,73 @@ config S3C_LOWLEVEL_UART_PORT
25131           such as the `Uncompressing...` at start time. The value of
25132           this configuration should be between zero and two. The port
25133           must have been initialised by the boot-loader before use.
25134 +
25135 +# options for gpiolib support
25136 +
25137 +config S3C_GPIO_SPACE
25138 +       int "Space between gpio banks"
25139 +       default 0
25140 +       help
25141 +         Add a number of spare GPIO entries between each bank for debugging
25142 +         purposes. This allows any problems where an counter overflows from
25143 +         one bank to another to be caught, at the expense of using a little
25144 +         more memory.
25145 +
25146 +config S3C_GPIO_TRACK
25147 +       bool
25148 +       help
25149 +         Internal configuration option to enable the s3c specific gpio
25150 +         chip tracking if the platform requires it.
25151 +
25152 +config S3C_GPIO_PULL_UPDOWN
25153 +       bool
25154 +       help
25155 +         Internal configuration to enable the correct GPIO pull helper
25156 +
25157 +config S3C_GPIO_PULL_DOWN
25158 +       bool
25159 +       help
25160 +         Internal configuration to enable the correct GPIO pull helper
25161 +
25162 +config S3C_GPIO_PULL_UP
25163 +       bool
25164 +       help
25165 +         Internal configuration to enable the correct GPIO pull helper
25166 +
25167 +config S3C_GPIO_CFG_S3C24XX
25168 +       bool
25169 +       help
25170 +         Internal configuration to enable S3C24XX style GPIO configuration
25171 +         functions.
25172 +
25173 +config S3C_GPIO_CFG_S3C64XX
25174 +       bool
25175 +       help
25176 +         Internal configuration to enable S3C64XX style GPIO configuration
25177 +         functions.
25178 +
25179 +# device definitions to compile in
25180 +
25181 +config S3C_DEV_HSMMC
25182 +       bool
25183 +       depends on PLAT_S3C
25184 +       help
25185 +         Compile in platform device definitions for HSMMC code
25186 +
25187 +config S3C_DEV_HSMMC1
25188 +       bool
25189 +       depends on PLAT_S3C
25190 +       help
25191 +         Compile in platform device definitions for HSMMC channel 1
25192 +
25193 +config S3C_DEV_I2C1
25194 +       bool
25195 +       depends on PLAT_S3C
25196 +       help
25197 +         Compile in platform device definitions for I2C channel 1
25198 +
25199 +config S3C_DEV_FB
25200 +       bool
25201 +       depends on PLAT_S3C
25202 +       help
25203 +         Compile in platform device definition for framebuffer
25204 --- a/arch/arm/plat-s3c/Makefile
25205 +++ b/arch/arm/plat-s3c/Makefile
25206 @@ -1,3 +1,33 @@
25207 -# dummy makefile, currently just including asm/arm/plat-s3c/include/plat
25208 +# arch/arm/plat-s3c/Makefile
25209 +#
25210 +# Copyright 2008 Simtec Electronics
25211 +#
25212 +# Licensed under GPLv2
25213
25214 -obj-n  := dummy.o
25215 +obj-y                          :=
25216 +obj-m                          :=
25217 +obj-n                          :=
25218 +obj-                           :=
25219 +
25220 +# Core support for all Samsung SoCs
25221 +
25222 +obj-y                          +=  init.o
25223 +obj-y                          += time.o
25224 +obj-y                          += clock.o
25225 +obj-y                          += pwm-clock.o
25226 +obj-y                          += gpio.o
25227 +obj-y                          += gpio-config.o
25228 +
25229 +# PM support
25230 +
25231 +obj-$(CONFIG_PM)               += pm.o
25232 +obj-$(CONFIG_PM)               += pm-gpio.o
25233 +obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o
25234 +
25235 +# devices
25236 +
25237 +obj-$(CONFIG_S3C_DEV_HSMMC)    += dev-hsmmc.o
25238 +obj-$(CONFIG_S3C_DEV_HSMMC1)   += dev-hsmmc1.o
25239 +obj-y                          += dev-i2c0.o
25240 +obj-$(CONFIG_S3C_DEV_I2C1)     += dev-i2c1.o
25241 +obj-$(CONFIG_S3C_DEV_FB)       += dev-fb.o
25242 --- /dev/null
25243 +++ b/arch/arm/plat-s3c/pm.c
25244 @@ -0,0 +1,387 @@
25245 +/* linux/arch/arm/plat-s3c/pm.c
25246 + *
25247 + * Copyright 2008 Openmoko, Inc.
25248 + * Copyright 2004,2006,2008 Simtec Electronics
25249 + *     Ben Dooks <ben@simtec.co.uk>
25250 + *     http://armlinux.simtec.co.uk/
25251 + *
25252 + * S3C common power management (suspend to ram) support.
25253 + *
25254 + * This program is free software; you can redistribute it and/or modify
25255 + * it under the terms of the GNU General Public License version 2 as
25256 + * published by the Free Software Foundation.
25257 +*/
25258 +
25259 +#include <linux/init.h>
25260 +#include <linux/suspend.h>
25261 +#include <linux/errno.h>
25262 +#include <linux/delay.h>
25263 +#include <linux/serial_core.h>
25264 +#include <linux/io.h>
25265 +#include <linux/regulator/machine.h>
25266 +
25267 +#include <asm/cacheflush.h>
25268 +#include <mach/hardware.h>
25269 +#include <mach/map.h>
25270 +
25271 +#include <plat/regs-serial.h>
25272 +#include <mach/regs-clock.h>
25273 +#include <mach/regs-irq.h>
25274 +#include <asm/irq.h>
25275 +
25276 +#include <plat/pm.h>
25277 +#include <plat/pm-core.h>
25278 +
25279 +/* for external use */
25280 +
25281 +unsigned long s3c_pm_flags;
25282 +
25283 +/* Debug code:
25284 + *
25285 + * This code supports debug output to the low level UARTs for use on
25286 + * resume before the console layer is available.
25287 +*/
25288 +
25289 +#ifdef CONFIG_S3C2410_PM_DEBUG
25290 +extern void printascii(const char *);
25291 +
25292 +void s3c_pm_dbg(const char *fmt, ...)
25293 +{
25294 +       va_list va;
25295 +       char buff[256];
25296 +
25297 +       va_start(va, fmt);
25298 +       vsprintf(buff, fmt, va);
25299 +       va_end(va);
25300 +
25301 +       printascii(buff);
25302 +}
25303 +
25304 +static inline void s3c_pm_debug_init(void)
25305 +{
25306 +       /* restart uart clocks so we can use them to output */
25307 +       s3c_pm_debug_init_uart();
25308 +}
25309 +
25310 +#else
25311 +#define s3c_pm_debug_init() do { } while(0)
25312 +
25313 +#endif /* CONFIG_S3C2410_PM_DEBUG */
25314 +
25315 +/* Save the UART configurations if we are configured for debug. */
25316 +
25317 +unsigned char pm_uart_udivslot;
25318 +
25319 +#ifdef CONFIG_S3C2410_PM_DEBUG
25320 +
25321 +struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
25322 +
25323 +static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
25324 +{
25325 +       void __iomem *regs = S3C_VA_UARTx(uart);
25326 +
25327 +       save->ulcon = __raw_readl(regs + S3C2410_ULCON);
25328 +       save->ucon = __raw_readl(regs + S3C2410_UCON);
25329 +       save->ufcon = __raw_readl(regs + S3C2410_UFCON);
25330 +       save->umcon = __raw_readl(regs + S3C2410_UMCON);
25331 +       save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
25332 +
25333 +       if (pm_uart_udivslot)
25334 +               save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
25335 +
25336 +       S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
25337 +                 uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
25338 +}
25339 +
25340 +static void s3c_pm_save_uarts(void)
25341 +{
25342 +       struct pm_uart_save *save = uart_save;
25343 +       unsigned int uart;
25344 +
25345 +       for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
25346 +               s3c_pm_save_uart(uart, save);
25347 +}
25348 +
25349 +static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
25350 +{
25351 +       void __iomem *regs = S3C_VA_UARTx(uart);
25352 +
25353 +       s3c_pm_arch_update_uart(regs, save);
25354 +
25355 +       __raw_writel(save->ulcon, regs + S3C2410_ULCON);
25356 +       __raw_writel(save->ucon,  regs + S3C2410_UCON);
25357 +       __raw_writel(save->ufcon, regs + S3C2410_UFCON);
25358 +       __raw_writel(save->umcon, regs + S3C2410_UMCON);
25359 +       __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
25360 +
25361 +       if (pm_uart_udivslot)
25362 +               __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
25363 +}
25364 +
25365 +static void s3c_pm_restore_uarts(void)
25366 +{
25367 +       struct pm_uart_save *save = uart_save;
25368 +       unsigned int uart;
25369 +
25370 +       for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
25371 +               s3c_pm_restore_uart(uart, save);
25372 +}
25373 +#else
25374 +static void s3c_pm_save_uarts(void) { }
25375 +static void s3c_pm_restore_uarts(void) { }
25376 +#endif
25377 +
25378 +/* The IRQ ext-int code goes here, it is too small to currently bother
25379 + * with its own file. */
25380 +
25381 +unsigned long s3c_irqwake_intmask      = 0xffffffffL;
25382 +unsigned long s3c_irqwake_eintmask     = 0xffffffffL;
25383 +
25384 +int s3c_irqext_wake(unsigned int irqno, unsigned int state)
25385 +{
25386 +       unsigned long bit = 1L << IRQ_EINT_BIT(irqno);
25387 +
25388 +       if (!(s3c_irqwake_eintallow & bit))
25389 +               return -ENOENT;
25390 +
25391 +       printk(KERN_INFO "wake %s for irq %d\n",
25392 +              state ? "enabled" : "disabled", irqno);
25393 +
25394 +       if (!state)
25395 +               s3c_irqwake_eintmask |= bit;
25396 +       else
25397 +               s3c_irqwake_eintmask &= ~bit;
25398 +
25399 +       return 0;
25400 +}
25401 +
25402 +/* helper functions to save and restore register state */
25403 +
25404 +/**
25405 + * s3c_pm_do_save() - save a set of registers for restoration on resume.
25406 + * @ptr: Pointer to an array of registers.
25407 + * @count: Size of the ptr array.
25408 + *
25409 + * Run through the list of registers given, saving their contents in the
25410 + * array for later restoration when we wakeup.
25411 + */
25412 +void s3c_pm_do_save(struct sleep_save *ptr, int count)
25413 +{
25414 +       for (; count > 0; count--, ptr++) {
25415 +               ptr->val = __raw_readl(ptr->reg);
25416 +               S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
25417 +       }
25418 +}
25419 +
25420 +/**
25421 + * s3c_pm_do_restore() - restore register values from the save list.
25422 + * @ptr: Pointer to an array of registers.
25423 + * @count: Size of the ptr array.
25424 + *
25425 + * Restore the register values saved from s3c_pm_do_save().
25426 + *
25427 + * Note, we do not use S3C_PMDBG() in here, as the system may not have
25428 + * restore the UARTs state yet
25429 +*/
25430 +
25431 +void s3c_pm_do_restore(struct sleep_save *ptr, int count)
25432 +{
25433 +       for (; count > 0; count--, ptr++) {
25434 +               printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
25435 +                      ptr->reg, ptr->val, __raw_readl(ptr->reg));
25436 +
25437 +               __raw_writel(ptr->val, ptr->reg);
25438 +       }
25439 +}
25440 +
25441 +/**
25442 + * s3c_pm_do_restore_core() - early restore register values from save list.
25443 + *
25444 + * This is similar to s3c_pm_do_restore() except we try and minimise the
25445 + * side effects of the function in case registers that hardware might need
25446 + * to work has been restored.
25447 + *
25448 + * WARNING: Do not put any debug in here that may effect memory or use
25449 + * peripherals, as things may be changing!
25450 +*/
25451 +
25452 +void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
25453 +{
25454 +       for (; count > 0; count--, ptr++)
25455 +               __raw_writel(ptr->val, ptr->reg);
25456 +}
25457 +
25458 +/* s3c2410_pm_show_resume_irqs
25459 + *
25460 + * print any IRQs asserted at resume time (ie, we woke from)
25461 +*/
25462 +static void s3c_pm_show_resume_irqs(int start, unsigned long which,
25463 +                                   unsigned long mask)
25464 +{
25465 +       int i;
25466 +
25467 +       which &= ~mask;
25468 +
25469 +       for (i = 0; i <= 31; i++) {
25470 +               if (which & (1L<<i)) {
25471 +                       S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
25472 +               }
25473 +       }
25474 +}
25475 +
25476 +
25477 +void (*pm_cpu_prep)(void);
25478 +void (*pm_cpu_sleep)(void);
25479 +
25480 +#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
25481 +
25482 +/* s3c_pm_enter
25483 + *
25484 + * central control for sleep/resume process
25485 +*/
25486 +
25487 +static int s3c_pm_enter(suspend_state_t state)
25488 +{
25489 +       unsigned long regs_save[16];
25490 +
25491 +       /* ensure the debug is initialised (if enabled) */
25492 +
25493 +       s3c_pm_debug_init();
25494 +
25495 +       S3C_PMDBG("%s(%d)\n", __func__, state);
25496 +
25497 +       if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
25498 +               printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
25499 +               return -EINVAL;
25500 +       }
25501 +
25502 +       /* check if we have anything to wake-up with... bad things seem
25503 +        * to happen if you suspend with no wakeup (system will often
25504 +        * require a full power-cycle)
25505 +       */
25506 +
25507 +       if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
25508 +           !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
25509 +               printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
25510 +               printk(KERN_ERR "%s: Aborting sleep\n", __func__);
25511 +               return -EINVAL;
25512 +       }
25513 +
25514 +       /* store the physical address of the register recovery block */
25515 +
25516 +       s3c_sleep_save_phys = virt_to_phys(regs_save);
25517 +
25518 +       S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
25519 +
25520 +       /* save all necessary core registers not covered by the drivers */
25521 +
25522 +       s3c_pm_save_gpios();
25523 +       s3c_pm_save_uarts();
25524 +       s3c_pm_save_core();
25525 +
25526 +       /* set the irq configuration for wake */
25527 +
25528 +       s3c_pm_configure_extint();
25529 +
25530 +       S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
25531 +           s3c_irqwake_intmask, s3c_irqwake_eintmask);
25532 +
25533 +       s3c_pm_arch_prepare_irqs();
25534 +
25535 +       /* call cpu specific preparation */
25536 +
25537 +       pm_cpu_prep();
25538 +
25539 +       /* flush cache back to ram */
25540 +
25541 +       flush_cache_all();
25542 +
25543 +       s3c_pm_check_store();
25544 +
25545 +       /* send the cpu to sleep... */
25546 +
25547 +       s3c_pm_arch_stop_clocks();
25548 +
25549 +       /* s3c2410_cpu_save will also act as our return point from when
25550 +        * we resume as it saves its own register state, so use the return
25551 +        * code to differentiate return from save and return from sleep */
25552 +
25553 +       if (s3c_cpu_save(regs_save) == 0) {
25554 +               flush_cache_all();
25555 +               pm_cpu_sleep();
25556 +       }
25557 +
25558 +       /* restore the cpu state using the kernel's cpu init code. */
25559 +
25560 +       cpu_init();
25561 +
25562 +       /* restore the system state */
25563 +
25564 +       s3c_pm_restore_core();
25565 +       s3c_pm_restore_uarts();
25566 +       s3c_pm_restore_gpios();
25567 +
25568 +       s3c_pm_debug_init();
25569 +
25570 +       /* check what irq (if any) restored the system */
25571 +
25572 +       s3c_pm_arch_show_resume_irqs();
25573 +
25574 +       S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
25575 +
25576 +       s3c_pm_check_restore();
25577 +
25578 +       /* LEDs should now be 1110 */
25579 +       s3c_pm_debug_smdkled(1 << 1, 0);
25580 +
25581 +       /* ok, let's return from sleep */
25582 +
25583 +       S3C_PMDBG("S3C PM Resume (post-restore)\n");
25584 +       return 0;
25585 +}
25586 +
25587 +static int s3c_pm_prepare(void)
25588 +{
25589 +       /* prepare check area if configured */
25590 +
25591 +       s3c_pm_check_prepare();
25592 +       return 0;
25593 +}
25594 +
25595 +static void s3c_pm_finish(void)
25596 +{
25597 +       s3c_pm_check_cleanup();
25598 +}
25599 +
25600 +static int s3c_pm_begin(suspend_state_t state)
25601 +{
25602 +        int ret = 0;
25603 +
25604 +#ifdef CONFIG_REGULATOR
25605 +        ret = regulator_suspend_prepare(state);
25606 +#endif
25607 +        return ret;
25608 +}
25609 +
25610 +static struct platform_suspend_ops s3c_pm_ops = {
25611 +       .enter          = s3c_pm_enter,
25612 +       .prepare        = s3c_pm_prepare,
25613 +       .finish         = s3c_pm_finish,
25614 +       .valid          = suspend_valid_only_mem,
25615 +       .begin          = s3c_pm_begin,
25616 +};
25617 +
25618 +/* s3c_pm_init
25619 + *
25620 + * Attach the power management functions. This should be called
25621 + * from the board specific initialisation if the board supports
25622 + * it.
25623 +*/
25624 +
25625 +int __init s3c_pm_init(void)
25626 +{
25627 +       printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
25628 +
25629 +       suspend_set_ops(&s3c_pm_ops);
25630 +       return 0;
25631 +}
25632 --- /dev/null
25633 +++ b/arch/arm/plat-s3c/pm-check.c
25634 @@ -0,0 +1,242 @@
25635 +/* linux/arch/arm/plat-s3c/pm-check.c
25636 + *  originally in linux/arch/arm/plat-s3c24xx/pm.c
25637 + *
25638 + * Copyright (c) 2004,2006,2008 Simtec Electronics
25639 + *     http://armlinux.simtec.co.uk
25640 + *     Ben Dooks <ben@simtec.co.uk>
25641 + *
25642 + * S3C Power Mangament - suspend/resume memory corruptiuon check.
25643 + *
25644 + * This program is free software; you can redistribute it and/or modify
25645 + * it under the terms of the GNU General Public License version 2 as
25646 + * published by the Free Software Foundation.
25647 +*/
25648 +
25649 +#include <linux/kernel.h>
25650 +#include <linux/suspend.h>
25651 +#include <linux/init.h>
25652 +#include <linux/crc32.h>
25653 +#include <linux/ioport.h>
25654 +
25655 +#include <plat/pm.h>
25656 +
25657 +#if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1
25658 +#error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value
25659 +#endif
25660 +
25661 +/* suspend checking code...
25662 + *
25663 + * this next area does a set of crc checks over all the installed
25664 + * memory, so the system can verify if the resume was ok.
25665 + *
25666 + * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
25667 + * increasing it will mean that the area corrupted will be less easy to spot,
25668 + * and reducing the size will cause the CRC save area to grow
25669 +*/
25670 +
25671 +#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
25672 +
25673 +static u32 crc_size;   /* size needed for the crc block */
25674 +static u32 *crcs;      /* allocated over suspend/resume */
25675 +
25676 +typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
25677 +
25678 +/* s3c_pm_run_res
25679 + *
25680 + * go through the given resource list, and look for system ram
25681 +*/
25682 +
25683 +static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
25684 +{
25685 +       while (ptr != NULL) {
25686 +               if (ptr->child != NULL)
25687 +                       s3c_pm_run_res(ptr->child, fn, arg);
25688 +
25689 +               if ((ptr->flags & IORESOURCE_MEM) &&
25690 +                   strcmp(ptr->name, "System RAM") == 0) {
25691 +                       S3C_PMDBG("Found system RAM at %08lx..%08lx\n",
25692 +                                 (unsigned long)ptr->start,
25693 +                                 (unsigned long)ptr->end);
25694 +                       arg = (fn)(ptr, arg);
25695 +               }
25696 +
25697 +               ptr = ptr->sibling;
25698 +       }
25699 +}
25700 +
25701 +static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg)
25702 +{
25703 +       s3c_pm_run_res(&iomem_resource, fn, arg);
25704 +}
25705 +
25706 +static u32 *s3c_pm_countram(struct resource *res, u32 *val)
25707 +{
25708 +       u32 size = (u32)(res->end - res->start)+1;
25709 +
25710 +       size += CHECK_CHUNKSIZE-1;
25711 +       size /= CHECK_CHUNKSIZE;
25712 +
25713 +       S3C_PMDBG("Area %08lx..%08lx, %d blocks\n",
25714 +                 (unsigned long)res->start, (unsigned long)res->end, size);
25715 +
25716 +       *val += size * sizeof(u32);
25717 +       return val;
25718 +}
25719 +
25720 +/* s3c_pm_prepare_check
25721 + *
25722 + * prepare the necessary information for creating the CRCs. This
25723 + * must be done before the final save, as it will require memory
25724 + * allocating, and thus touching bits of the kernel we do not
25725 + * know about.
25726 +*/
25727 +
25728 +void s3c_pm_check_prepare(void)
25729 +{
25730 +       crc_size = 0;
25731 +
25732 +       s3c_pm_run_sysram(s3c_pm_countram, &crc_size);
25733 +
25734 +       S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size);
25735 +
25736 +       crcs = kmalloc(crc_size+4, GFP_KERNEL);
25737 +       if (crcs == NULL)
25738 +               printk(KERN_ERR "Cannot allocated CRC save area\n");
25739 +}
25740 +
25741 +static u32 *s3c_pm_makecheck(struct resource *res, u32 *val)
25742 +{
25743 +       unsigned long addr, left;
25744 +
25745 +       for (addr = res->start; addr < res->end;
25746 +            addr += CHECK_CHUNKSIZE) {
25747 +               left = res->end - addr;
25748 +
25749 +               if (left > CHECK_CHUNKSIZE)
25750 +                       left = CHECK_CHUNKSIZE;
25751 +
25752 +               *val = crc32_le(~0, phys_to_virt(addr), left);
25753 +               val++;
25754 +       }
25755 +
25756 +       return val;
25757 +}
25758 +
25759 +/* s3c_pm_check_store
25760 + *
25761 + * compute the CRC values for the memory blocks before the final
25762 + * sleep.
25763 +*/
25764 +
25765 +void s3c_pm_check_store(void)
25766 +{
25767 +       if (crcs != NULL)
25768 +               s3c_pm_run_sysram(s3c_pm_makecheck, crcs);
25769 +}
25770 +
25771 +/* in_region
25772 + *
25773 + * return TRUE if the area defined by ptr..ptr+size contains the
25774 + * what..what+whatsz
25775 +*/
25776 +
25777 +static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
25778 +{
25779 +       if ((what+whatsz) < ptr)
25780 +               return 0;
25781 +
25782 +       if (what > (ptr+size))
25783 +               return 0;
25784 +
25785 +       return 1;
25786 +}
25787 +
25788 +/**
25789 + * s3c_pm_runcheck() - helper to check a resource on restore.
25790 + * @res: The resource to check
25791 + * @vak: Pointer to list of CRC32 values to check.
25792 + *
25793 + * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this
25794 + * function runs the given memory resource checking it against the stored
25795 + * CRC to ensure that memory is restored. The function tries to skip as
25796 + * many of the areas used during the suspend process.
25797 + */
25798 +static u32 *s3c_pm_runcheck(struct resource *res, u32 *val)
25799 +{
25800 +       void *save_at = phys_to_virt(s3c_sleep_save_phys);
25801 +       unsigned long addr;
25802 +       unsigned long left;
25803 +       void *stkpage;
25804 +       void *ptr;
25805 +       u32 calc;
25806 +
25807 +       stkpage = (void *)((u32)&calc & ~PAGE_MASK);
25808 +
25809 +       for (addr = res->start; addr < res->end;
25810 +            addr += CHECK_CHUNKSIZE) {
25811 +               left = res->end - addr;
25812 +
25813 +               if (left > CHECK_CHUNKSIZE)
25814 +                       left = CHECK_CHUNKSIZE;
25815 +
25816 +               ptr = phys_to_virt(addr);
25817 +
25818 +               if (in_region(ptr, left, stkpage, 4096)) {
25819 +                       S3C_PMDBG("skipping %08lx, has stack in\n", addr);
25820 +                       goto skip_check;
25821 +               }
25822 +
25823 +               if (in_region(ptr, left, crcs, crc_size)) {
25824 +                       S3C_PMDBG("skipping %08lx, has crc block in\n", addr);
25825 +                       goto skip_check;
25826 +               }
25827 +
25828 +               if (in_region(ptr, left, save_at, 32*4 )) {
25829 +                       S3C_PMDBG("skipping %08lx, has save block in\n", addr);
25830 +                       goto skip_check;
25831 +               }
25832 +
25833 +               /* calculate and check the checksum */
25834 +
25835 +               calc = crc32_le(~0, ptr, left);
25836 +               if (calc != *val) {
25837 +                       printk(KERN_ERR "Restore CRC error at "
25838 +                              "%08lx (%08x vs %08x)\n", addr, calc, *val);
25839 +
25840 +                       S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n",
25841 +                           addr, calc, *val);
25842 +               }
25843 +
25844 +       skip_check:
25845 +               val++;
25846 +       }
25847 +
25848 +       return val;
25849 +}
25850 +
25851 +/**
25852 + * s3c_pm_check_restore() - memory check called on resume
25853 + *
25854 + * check the CRCs after the restore event and free the memory used
25855 + * to hold them
25856 +*/
25857 +void s3c_pm_check_restore(void)
25858 +{
25859 +       if (crcs != NULL)
25860 +               s3c_pm_run_sysram(s3c_pm_runcheck, crcs);
25861 +}
25862 +
25863 +/**
25864 + * s3c_pm_check_cleanup() - free memory resources
25865 + *
25866 + * Free the resources that where allocated by the suspend
25867 + * memory check code. We do this separately from the
25868 + * s3c_pm_check_restore() function as we cannot call any
25869 + * functions that might sleep during that resume.
25870 + */
25871 +void s3c_pm_check_cleanup(void)
25872 +{
25873 +       kfree(crcs);
25874 +       crcs = NULL;
25875 +}
25876 +
25877 --- /dev/null
25878 +++ b/arch/arm/plat-s3c/pm-gpio.c
25879 @@ -0,0 +1,378 @@
25880 +/* linux/arch/arm/plat-s3c/pm-gpio.c
25881 + *
25882 + * Copyright 2008 Openmoko, Inc.
25883 + * Copyright 2008 Simtec Electronics
25884 + *     Ben Dooks <ben@simtec.co.uk>
25885 + *     http://armlinux.simtec.co.uk/
25886 + *
25887 + * S3C series GPIO PM code
25888 + *
25889 + * This program is free software; you can redistribute it and/or modify
25890 + * it under the terms of the GNU General Public License version 2 as
25891 + * published by the Free Software Foundation.
25892 +*/
25893 +
25894 +#include <linux/kernel.h>
25895 +#include <linux/init.h>
25896 +#include <linux/io.h>
25897 +#include <linux/gpio.h>
25898 +
25899 +#include <mach/gpio-core.h>
25900 +#include <plat/pm.h>
25901 +
25902 +/* PM GPIO helpers */
25903 +
25904 +#define OFFS_CON       (0x00)
25905 +#define OFFS_DAT       (0X04)
25906 +#define OFFS_UP                (0X08)
25907 +
25908 +static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
25909 +{
25910 +       chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
25911 +       chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
25912 +}
25913 +
25914 +static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
25915 +{
25916 +       void __iomem *base = chip->base;
25917 +       u32 old_gpcon = __raw_readl(base + OFFS_CON);
25918 +       u32 old_gpdat = __raw_readl(base + OFFS_DAT);
25919 +       u32 gps_gpcon = chip->pm_save[0];
25920 +       u32 gps_gpdat = chip->pm_save[1];
25921 +       u32 gpcon;
25922 +
25923 +       /* GPACON only has one bit per control / data and no PULLUPs.
25924 +        * GPACON[x] = 0 => Output, 1 => SFN */
25925 +
25926 +       /* first set all SFN bits to SFN */
25927 +
25928 +       gpcon = old_gpcon | gps_gpcon;
25929 +       __raw_writel(gpcon, base + OFFS_CON);
25930 +
25931 +       /* now set all the other bits */
25932 +
25933 +       __raw_writel(gps_gpdat, base + OFFS_DAT);
25934 +       __raw_writel(gps_gpcon, base + OFFS_CON);
25935 +
25936 +       S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
25937 +                 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
25938 +}
25939 +
25940 +struct s3c_gpio_pm s3c_gpio_pm_1bit = {
25941 +       .save   = s3c_gpio_pm_1bit_save,
25942 +       .resume = s3c_gpio_pm_1bit_resume,
25943 +};
25944 +
25945 +static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
25946 +{
25947 +       chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
25948 +       chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
25949 +       chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
25950 +}
25951 +
25952 +/* Test whether the given masked+shifted bits of an GPIO configuration
25953 + * are one of the SFN (special function) modes. */
25954 +
25955 +static inline int is_sfn(unsigned long con)
25956 +{
25957 +       return con >= 2;
25958 +}
25959 +
25960 +/* Test if the given masked+shifted GPIO configuration is an input */
25961 +
25962 +static inline int is_in(unsigned long con)
25963 +{
25964 +       return con == 0;
25965 +}
25966 +
25967 +/* Test if the given masked+shifted GPIO configuration is an output */
25968 +
25969 +static inline int is_out(unsigned long con)
25970 +{
25971 +       return con == 1;
25972 +}
25973 +
25974 +/**
25975 + * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
25976 + * @chip: The chip information to resume.
25977 + *
25978 + * Restore one of the GPIO banks that was saved during suspend. This is
25979 + * not as simple as once thought, due to the possibility of glitches
25980 + * from the order that the CON and DAT registers are set in.
25981 + *
25982 + * The three states the pin can be are {IN,OUT,SFN} which gives us 9
25983 + * combinations of changes to check. Three of these, if the pin stays
25984 + * in the same configuration can be discounted. This leaves us with
25985 + * the following:
25986 + *
25987 + * { IN => OUT }  Change DAT first
25988 + * { IN => SFN }  Change CON first
25989 + * { OUT => SFN } Change CON first, so new data will not glitch
25990 + * { OUT => IN }  Change CON first, so new data will not glitch
25991 + * { SFN => IN }  Change CON first
25992 + * { SFN => OUT } Change DAT first, so new data will not glitch [1]
25993 + *
25994 + * We do not currently deal with the UP registers as these control
25995 + * weak resistors, so a small delay in change should not need to bring
25996 + * these into the calculations.
25997 + *
25998 + * [1] this assumes that writing to a pin DAT whilst in SFN will set the
25999 + *     state for when it is next output.
26000 + */
26001 +static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
26002 +{
26003 +       void __iomem *base = chip->base;
26004 +       u32 old_gpcon = __raw_readl(base + OFFS_CON);
26005 +       u32 old_gpdat = __raw_readl(base + OFFS_DAT);
26006 +       u32 gps_gpcon = chip->pm_save[0];
26007 +       u32 gps_gpdat = chip->pm_save[1];
26008 +       u32 gpcon, old, new, mask;
26009 +       u32 change_mask = 0x0;
26010 +       int nr;
26011 +
26012 +       /* restore GPIO pull-up settings */
26013 +       __raw_writel(chip->pm_save[2], base + OFFS_UP);
26014 +
26015 +       /* Create a change_mask of all the items that need to have
26016 +        * their CON value changed before their DAT value, so that
26017 +        * we minimise the work between the two settings.
26018 +        */
26019 +
26020 +       for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
26021 +               old = (old_gpcon & mask) >> nr;
26022 +               new = (gps_gpcon & mask) >> nr;
26023 +
26024 +               /* If there is no change, then skip */
26025 +
26026 +               if (old == new)
26027 +                       continue;
26028 +
26029 +               /* If both are special function, then skip */
26030 +
26031 +               if (is_sfn(old) && is_sfn(new))
26032 +                       continue;
26033 +
26034 +               /* Change is IN => OUT, do not change now */
26035 +
26036 +               if (is_in(old) && is_out(new))
26037 +                       continue;
26038 +
26039 +               /* Change is SFN => OUT, do not change now */
26040 +
26041 +               if (is_sfn(old) && is_out(new))
26042 +                       continue;
26043 +
26044 +               /* We should now be at the case of IN=>SFN,
26045 +                * OUT=>SFN, OUT=>IN, SFN=>IN. */
26046 +
26047 +               change_mask |= mask;
26048 +       }
26049 +
26050 +
26051 +       /* Write the new CON settings */
26052 +
26053 +       gpcon = old_gpcon & ~change_mask;
26054 +       gpcon |= gps_gpcon & change_mask;
26055 +
26056 +       __raw_writel(gpcon, base + OFFS_CON);
26057 +
26058 +       /* Now change any items that require DAT,CON */
26059 +
26060 +       __raw_writel(gps_gpdat, base + OFFS_DAT);
26061 +       __raw_writel(gps_gpcon, base + OFFS_CON);
26062 +
26063 +       S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
26064 +                 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
26065 +}
26066 +
26067 +struct s3c_gpio_pm s3c_gpio_pm_2bit = {
26068 +       .save   = s3c_gpio_pm_2bit_save,
26069 +       .resume = s3c_gpio_pm_2bit_resume,
26070 +};
26071 +
26072 +#ifdef CONFIG_ARCH_S3C64XX
26073 +static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
26074 +{
26075 +       chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
26076 +       chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
26077 +       chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
26078 +
26079 +       if (chip->chip.ngpio > 8)
26080 +               chip->pm_save[0] = __raw_readl(chip->base - 4);
26081 +}
26082 +
26083 +static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
26084 +{
26085 +       u32 old, new, mask;
26086 +       u32 change_mask = 0x0;
26087 +       int nr;
26088 +
26089 +       for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
26090 +               old = (old_gpcon & mask) >> nr;
26091 +               new = (gps_gpcon & mask) >> nr;
26092 +
26093 +               /* If there is no change, then skip */
26094 +
26095 +               if (old == new)
26096 +                       continue;
26097 +
26098 +               /* If both are special function, then skip */
26099 +
26100 +               if (is_sfn(old) && is_sfn(new))
26101 +                       continue;
26102 +
26103 +               /* Change is IN => OUT, do not change now */
26104 +
26105 +               if (is_in(old) && is_out(new))
26106 +                       continue;
26107 +
26108 +               /* Change is SFN => OUT, do not change now */
26109 +
26110 +               if (is_sfn(old) && is_out(new))
26111 +                       continue;
26112 +
26113 +               /* We should now be at the case of IN=>SFN,
26114 +                * OUT=>SFN, OUT=>IN, SFN=>IN. */
26115 +
26116 +               change_mask |= mask;
26117 +       }
26118 +
26119 +       return change_mask;
26120 +}
26121 +
26122 +static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
26123 +{
26124 +       void __iomem *con = chip->base + (index * 4);
26125 +       u32 old_gpcon = __raw_readl(con);
26126 +       u32 gps_gpcon = chip->pm_save[index + 1];
26127 +       u32 gpcon, mask;
26128 +
26129 +       mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
26130 +
26131 +       gpcon = old_gpcon & ~mask;
26132 +       gpcon |= gps_gpcon & mask;
26133 +
26134 +       __raw_writel(gpcon, con);
26135 +}
26136 +
26137 +static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
26138 +{
26139 +       void __iomem *base = chip->base;
26140 +       u32 old_gpcon[2];
26141 +       u32 old_gpdat = __raw_readl(base + OFFS_DAT);
26142 +       u32 gps_gpdat = chip->pm_save[2];
26143 +
26144 +       /* First, modify the CON settings */
26145 +
26146 +       old_gpcon[0] = 0;
26147 +       old_gpcon[1] = __raw_readl(base + OFFS_CON);
26148 +
26149 +       s3c_gpio_pm_4bit_con(chip, 0);
26150 +       if (chip->chip.ngpio > 8) {
26151 +               old_gpcon[0] = __raw_readl(base - 4);
26152 +               s3c_gpio_pm_4bit_con(chip, -1);
26153 +       }
26154 +
26155 +       /* Now change the configurations that require DAT,CON */
26156 +
26157 +       __raw_writel(chip->pm_save[2], base + OFFS_DAT);
26158 +       __raw_writel(chip->pm_save[1], base + OFFS_CON);
26159 +       if (chip->chip.ngpio > 8)
26160 +               __raw_writel(chip->pm_save[0], base - 4);
26161 +
26162 +       __raw_writel(chip->pm_save[2], base + OFFS_DAT);
26163 +       __raw_writel(chip->pm_save[3], base + OFFS_UP);
26164 +
26165 +       if (chip->chip.ngpio > 8) {
26166 +               S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
26167 +                         chip->chip.label, old_gpcon[0], old_gpcon[1],
26168 +                         __raw_readl(base - 4),
26169 +                         __raw_readl(base + OFFS_CON),
26170 +                         old_gpdat, gps_gpdat);
26171 +       } else
26172 +               S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
26173 +                         chip->chip.label, old_gpcon[1],
26174 +                         __raw_readl(base + OFFS_CON),
26175 +                         old_gpdat, gps_gpdat);
26176 +}
26177 +
26178 +struct s3c_gpio_pm s3c_gpio_pm_4bit = {
26179 +       .save   = s3c_gpio_pm_4bit_save,
26180 +       .resume = s3c_gpio_pm_4bit_resume,
26181 +};
26182 +#endif /* CONFIG_ARCH_S3C64XX */
26183 +
26184 +/**
26185 + * s3c_pm_save_gpio() - save gpio chip data for suspend
26186 + * @ourchip: The chip for suspend.
26187 + */
26188 +static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
26189 +{
26190 +       struct s3c_gpio_pm *pm = ourchip->pm;
26191 +
26192 +       if (pm == NULL || pm->save == NULL)
26193 +               S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
26194 +       else
26195 +               pm->save(ourchip);
26196 +}
26197 +
26198 +/**
26199 + * s3c_pm_save_gpios() - Save the state of the GPIO banks.
26200 + *
26201 + * For all the GPIO banks, save the state of each one ready for going
26202 + * into a suspend mode.
26203 + */
26204 +void s3c_pm_save_gpios(void)
26205 +{
26206 +       struct s3c_gpio_chip *ourchip;
26207 +       unsigned int gpio_nr;
26208 +
26209 +       for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
26210 +               ourchip = s3c_gpiolib_getchip(gpio_nr);
26211 +               if (!ourchip)
26212 +                       continue;
26213 +
26214 +               s3c_pm_save_gpio(ourchip);
26215 +
26216 +               S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
26217 +                         ourchip->chip.label,
26218 +                         ourchip->pm_save[0],
26219 +                         ourchip->pm_save[1],
26220 +                         ourchip->pm_save[2],
26221 +                         ourchip->pm_save[3]);
26222 +
26223 +               gpio_nr += ourchip->chip.ngpio;
26224 +               gpio_nr += CONFIG_S3C_GPIO_SPACE;
26225 +       }
26226 +}
26227 +
26228 +/**
26229 + * s3c_pm_resume_gpio() - restore gpio chip data after suspend
26230 + * @ourchip: The suspended chip.
26231 + */
26232 +static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
26233 +{
26234 +       struct s3c_gpio_pm *pm = ourchip->pm;
26235 +
26236 +       if (pm == NULL || pm->resume == NULL)
26237 +               S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
26238 +       else
26239 +               pm->resume(ourchip);
26240 +}
26241 +
26242 +void s3c_pm_restore_gpios(void)
26243 +{
26244 +       struct s3c_gpio_chip *ourchip;
26245 +       unsigned int gpio_nr;
26246 +
26247 +       for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
26248 +               ourchip = s3c_gpiolib_getchip(gpio_nr);
26249 +               if (!ourchip)
26250 +                       continue;
26251 +
26252 +               s3c_pm_resume_gpio(ourchip);
26253 +
26254 +               gpio_nr += ourchip->chip.ngpio;
26255 +               gpio_nr += CONFIG_S3C_GPIO_SPACE;
26256 +       }
26257 +}
26258 --- /dev/null
26259 +++ b/arch/arm/plat-s3c/pwm-clock.c
26260 @@ -0,0 +1,463 @@
26261 +/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
26262 + *
26263 + * Copyright (c) 2007 Simtec Electronics
26264 + * Copyright (c) 2007, 2008 Ben Dooks
26265 + *     Ben Dooks <ben-linux@fluff.org>
26266 + *
26267 + * This program is free software; you can redistribute it and/or modify
26268 + * it under the terms of the GNU General Public License as published by
26269 + * the Free Software Foundation; either version 2 of the License.
26270 +*/
26271 +
26272 +#include <linux/init.h>
26273 +#include <linux/module.h>
26274 +#include <linux/kernel.h>
26275 +#include <linux/list.h>
26276 +#include <linux/errno.h>
26277 +#include <linux/log2.h>
26278 +#include <linux/clk.h>
26279 +#include <linux/err.h>
26280 +#include <linux/io.h>
26281 +
26282 +#include <mach/hardware.h>
26283 +#include <mach/map.h>
26284 +#include <asm/irq.h>
26285 +
26286 +#include <plat/clock.h>
26287 +#include <plat/cpu.h>
26288 +
26289 +#include <plat/regs-timer.h>
26290 +#include <mach/pwm-clock.h>
26291 +
26292 +/* Each of the timers 0 through 5 go through the following
26293 + * clock tree, with the inputs depending on the timers.
26294 + *
26295 + * pclk ---- [ prescaler 0 ] -+---> timer 0
26296 + *                           +---> timer 1
26297 + *
26298 + * pclk ---- [ prescaler 1 ] -+---> timer 2
26299 + *                           +---> timer 3
26300 + *                           \---> timer 4
26301 + *
26302 + * Which are fed into the timers as so:
26303 + *
26304 + * prescaled 0 ---- [ div 2,4,8,16 ] ---\
26305 + *                                    [mux] -> timer 0
26306 + * tclk 0 ------------------------------/
26307 + *
26308 + * prescaled 0 ---- [ div 2,4,8,16 ] ---\
26309 + *                                    [mux] -> timer 1
26310 + * tclk 0 ------------------------------/
26311 + *
26312 + *
26313 + * prescaled 1 ---- [ div 2,4,8,16 ] ---\
26314 + *                                    [mux] -> timer 2
26315 + * tclk 1 ------------------------------/
26316 + *
26317 + * prescaled 1 ---- [ div 2,4,8,16 ] ---\
26318 + *                                    [mux] -> timer 3
26319 + * tclk 1 ------------------------------/
26320 + *
26321 + * prescaled 1 ---- [ div 2,4,8, 16 ] --\
26322 + *                                    [mux] -> timer 4
26323 + * tclk 1 ------------------------------/
26324 + *
26325 + * Since the mux and the divider are tied together in the
26326 + * same register space, it is impossible to set the parent
26327 + * and the rate at the same time. To avoid this, we add an
26328 + * intermediate 'prescaled-and-divided' clock to select
26329 + * as the parent for the timer input clock called tdiv.
26330 + *
26331 + * prescaled clk --> pwm-tdiv ---\
26332 + *                             [ mux ] --> timer X
26333 + * tclk -------------------------/
26334 +*/
26335 +
26336 +static struct clk clk_timer_scaler[];
26337 +
26338 +static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
26339 +{
26340 +       unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
26341 +
26342 +       if (clk == &clk_timer_scaler[1]) {
26343 +               tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
26344 +               tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
26345 +       } else {
26346 +               tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
26347 +       }
26348 +
26349 +       return clk_get_rate(clk->parent) / (tcfg0 + 1);
26350 +}
26351 +
26352 +static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
26353 +                                              unsigned long rate)
26354 +{
26355 +       unsigned long parent_rate = clk_get_rate(clk->parent);
26356 +       unsigned long divisor = parent_rate / rate;
26357 +
26358 +       if (divisor > 256)
26359 +               divisor = 256;
26360 +       else if (divisor < 2)
26361 +               divisor = 2;
26362 +
26363 +       return parent_rate / divisor;
26364 +}
26365 +
26366 +static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
26367 +{
26368 +       unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
26369 +       unsigned long tcfg0;
26370 +       unsigned long divisor;
26371 +       unsigned long flags;
26372 +
26373 +       divisor = clk_get_rate(clk->parent) / round;
26374 +       divisor--;
26375 +
26376 +       local_irq_save(flags);
26377 +       tcfg0 = __raw_readl(S3C2410_TCFG0);
26378 +
26379 +       if (clk == &clk_timer_scaler[1]) {
26380 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
26381 +               tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
26382 +       } else {
26383 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
26384 +               tcfg0 |= divisor;
26385 +       }
26386 +
26387 +       __raw_writel(tcfg0, S3C2410_TCFG0);
26388 +       local_irq_restore(flags);
26389 +
26390 +       return 0;
26391 +}
26392 +
26393 +static struct clk clk_timer_scaler[] = {
26394 +       [0]     = {
26395 +               .name           = "pwm-scaler0",
26396 +               .id             = -1,
26397 +               .get_rate       = clk_pwm_scaler_get_rate,
26398 +               .set_rate       = clk_pwm_scaler_set_rate,
26399 +               .round_rate     = clk_pwm_scaler_round_rate,
26400 +       },
26401 +       [1]     = {
26402 +               .name           = "pwm-scaler1",
26403 +               .id             = -1,
26404 +               .get_rate       = clk_pwm_scaler_get_rate,
26405 +               .set_rate       = clk_pwm_scaler_set_rate,
26406 +               .round_rate     = clk_pwm_scaler_round_rate,
26407 +       },
26408 +};
26409 +
26410 +static struct clk clk_timer_tclk[] = {
26411 +       [0]     = {
26412 +               .name           = "pwm-tclk0",
26413 +               .id             = -1,
26414 +       },
26415 +       [1]     = {
26416 +               .name           = "pwm-tclk1",
26417 +               .id             = -1,
26418 +       },
26419 +};
26420 +
26421 +struct pwm_tdiv_clk {
26422 +       struct clk      clk;
26423 +       unsigned int    divisor;
26424 +};
26425 +
26426 +static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
26427 +{
26428 +       return container_of(clk, struct pwm_tdiv_clk, clk);
26429 +}
26430 +
26431 +static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
26432 +{
26433 +       unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
26434 +       unsigned int divisor;
26435 +
26436 +       tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
26437 +       tcfg1 &= S3C2410_TCFG1_MUX_MASK;
26438 +
26439 +       if (pwm_cfg_src_is_tclk(tcfg1))
26440 +               divisor = to_tdiv(clk)->divisor;
26441 +       else
26442 +               divisor = tcfg_to_divisor(tcfg1);
26443 +
26444 +       return clk_get_rate(clk->parent) / divisor;
26445 +}
26446 +
26447 +static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
26448 +                                            unsigned long rate)
26449 +{
26450 +       unsigned long parent_rate;
26451 +       unsigned long divisor;
26452 +
26453 +       parent_rate = clk_get_rate(clk->parent);
26454 +       divisor = parent_rate / rate;
26455 +
26456 +       if (divisor <= 1 && pwm_tdiv_has_div1())
26457 +               divisor = 1;
26458 +       else if (divisor <= 2)
26459 +               divisor = 2;
26460 +       else if (divisor <= 4)
26461 +               divisor = 4;
26462 +       else if (divisor <= 8)
26463 +               divisor = 8;
26464 +       else
26465 +               divisor = 16;
26466 +
26467 +       return parent_rate / divisor;
26468 +}
26469 +
26470 +static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
26471 +{
26472 +       return pwm_tdiv_div_bits(divclk->divisor);
26473 +}
26474 +
26475 +static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
26476 +{
26477 +       unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
26478 +       unsigned long bits = clk_pwm_tdiv_bits(divclk);
26479 +       unsigned long flags;
26480 +       unsigned long shift =  S3C2410_TCFG1_SHIFT(divclk->clk.id);
26481 +
26482 +       local_irq_save(flags);
26483 +
26484 +       tcfg1 = __raw_readl(S3C2410_TCFG1);
26485 +       tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
26486 +       tcfg1 |= bits << shift;
26487 +       __raw_writel(tcfg1, S3C2410_TCFG1);
26488 +
26489 +       local_irq_restore(flags);
26490 +}
26491 +
26492 +static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
26493 +{
26494 +       struct pwm_tdiv_clk *divclk = to_tdiv(clk);
26495 +       unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
26496 +       unsigned long parent_rate = clk_get_rate(clk->parent);
26497 +       unsigned long divisor;
26498 +
26499 +       tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
26500 +       tcfg1 &= S3C2410_TCFG1_MUX_MASK;
26501 +
26502 +       rate = clk_round_rate(clk, rate);
26503 +       divisor = parent_rate / rate;
26504 +
26505 +       if (divisor > 16)
26506 +               return -EINVAL;
26507 +
26508 +       divclk->divisor = divisor;
26509 +
26510 +       /* Update the current MUX settings if we are currently
26511 +        * selected as the clock source for this clock. */
26512 +
26513 +       if (!pwm_cfg_src_is_tclk(tcfg1))
26514 +               clk_pwm_tdiv_update(divclk);
26515 +
26516 +       return 0;
26517 +}
26518 +
26519 +static struct pwm_tdiv_clk clk_timer_tdiv[] = {
26520 +       [0]     = {
26521 +               .clk    = {
26522 +                       .name           = "pwm-tdiv",
26523 +                       .parent         = &clk_timer_scaler[0],
26524 +                       .get_rate       = clk_pwm_tdiv_get_rate,
26525 +                       .set_rate       = clk_pwm_tdiv_set_rate,
26526 +                       .round_rate     = clk_pwm_tdiv_round_rate,
26527 +               },
26528 +       },
26529 +       [1]     = {
26530 +               .clk    = {
26531 +                       .name           = "pwm-tdiv",
26532 +                       .parent         = &clk_timer_scaler[0],
26533 +                       .get_rate       = clk_pwm_tdiv_get_rate,
26534 +                       .set_rate       = clk_pwm_tdiv_set_rate,
26535 +                       .round_rate     = clk_pwm_tdiv_round_rate,
26536 +               }
26537 +       },
26538 +       [2]     = {
26539 +               .clk    = {
26540 +                       .name           = "pwm-tdiv",
26541 +                       .parent         = &clk_timer_scaler[1],
26542 +                       .get_rate       = clk_pwm_tdiv_get_rate,
26543 +                       .set_rate       = clk_pwm_tdiv_set_rate,
26544 +                       .round_rate     = clk_pwm_tdiv_round_rate,
26545 +               },
26546 +       },
26547 +       [3]     = {
26548 +               .clk    = {
26549 +                       .name           = "pwm-tdiv",
26550 +                       .parent         = &clk_timer_scaler[1],
26551 +                       .get_rate       = clk_pwm_tdiv_get_rate,
26552 +                       .set_rate       = clk_pwm_tdiv_set_rate,
26553 +                       .round_rate     = clk_pwm_tdiv_round_rate,
26554 +               },
26555 +       },
26556 +       [4]     = {
26557 +               .clk    = {
26558 +                       .name           = "pwm-tdiv",
26559 +                       .parent         = &clk_timer_scaler[1],
26560 +                       .get_rate       = clk_pwm_tdiv_get_rate,
26561 +                       .set_rate       = clk_pwm_tdiv_set_rate,
26562 +                       .round_rate     = clk_pwm_tdiv_round_rate,
26563 +               },
26564 +       },
26565 +};
26566 +
26567 +static int __init clk_pwm_tdiv_register(unsigned int id)
26568 +{
26569 +       struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
26570 +       unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
26571 +
26572 +       tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
26573 +       tcfg1 &= S3C2410_TCFG1_MUX_MASK;
26574 +
26575 +       divclk->clk.id = id;
26576 +       divclk->divisor = tcfg_to_divisor(tcfg1);
26577 +
26578 +       return s3c24xx_register_clock(&divclk->clk);
26579 +}
26580 +
26581 +static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
26582 +{
26583 +       return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
26584 +}
26585 +
26586 +static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
26587 +{
26588 +       return &clk_timer_tdiv[id].clk;
26589 +}
26590 +
26591 +static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
26592 +{
26593 +       unsigned int id = clk->id;
26594 +       unsigned long tcfg1;
26595 +       unsigned long flags;
26596 +       unsigned long bits;
26597 +       unsigned long shift = S3C2410_TCFG1_SHIFT(id);
26598 +
26599 +       if (parent == s3c24xx_pwmclk_tclk(id))
26600 +               bits = S3C_TCFG1_MUX_TCLK << shift;
26601 +       else if (parent == s3c24xx_pwmclk_tdiv(id))
26602 +               bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
26603 +       else
26604 +               return -EINVAL;
26605 +
26606 +       clk->parent = parent;
26607 +
26608 +       local_irq_save(flags);
26609 +
26610 +       tcfg1 = __raw_readl(S3C2410_TCFG1);
26611 +       tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
26612 +       __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
26613 +
26614 +       local_irq_restore(flags);
26615 +
26616 +       return 0;
26617 +}
26618 +
26619 +static struct clk clk_tin[] = {
26620 +       [0]     = {
26621 +               .name           = "pwm-tin",
26622 +               .id             = 0,
26623 +               .set_parent     = clk_pwm_tin_set_parent,
26624 +       },
26625 +       [1]     = {
26626 +               .name           = "pwm-tin",
26627 +               .id             = 1,
26628 +               .set_parent     = clk_pwm_tin_set_parent,
26629 +       },
26630 +       [2]     = {
26631 +               .name           = "pwm-tin",
26632 +               .id             = 2,
26633 +               .set_parent     = clk_pwm_tin_set_parent,
26634 +       },
26635 +       [3]     = {
26636 +               .name           = "pwm-tin",
26637 +               .id             = 3,
26638 +               .set_parent     = clk_pwm_tin_set_parent,
26639 +       },
26640 +       [4]     = {
26641 +               .name           = "pwm-tin",
26642 +               .id             = 4,
26643 +               .set_parent     = clk_pwm_tin_set_parent,
26644 +       },
26645 +};
26646 +
26647 +static __init int clk_pwm_tin_register(struct clk *pwm)
26648 +{
26649 +       unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
26650 +       unsigned int id = pwm->id;
26651 +
26652 +       struct clk *parent;
26653 +       int ret;
26654 +
26655 +       ret = s3c24xx_register_clock(pwm);
26656 +       if (ret < 0)
26657 +               return ret;
26658 +
26659 +       tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
26660 +       tcfg1 &= S3C2410_TCFG1_MUX_MASK;
26661 +
26662 +       if (pwm_cfg_src_is_tclk(tcfg1))
26663 +               parent = s3c24xx_pwmclk_tclk(id);
26664 +       else
26665 +               parent = s3c24xx_pwmclk_tdiv(id);
26666 +
26667 +       return clk_set_parent(pwm, parent);
26668 +}
26669 +
26670 +/**
26671 + * s3c_pwmclk_init() - initialise pwm clocks
26672 + *
26673 + * Initialise and register the clocks which provide the inputs for the
26674 + * pwm timer blocks.
26675 + *
26676 + * Note, this call is required by the time core, so must be called after
26677 + * the base clocks are added and before any of the initcalls are run.
26678 + */
26679 +__init void s3c_pwmclk_init(void)
26680 +{
26681 +       struct clk *clk_timers;
26682 +       unsigned int clk;
26683 +       int ret;
26684 +
26685 +       clk_timers = clk_get(NULL, "timers");
26686 +       if (IS_ERR(clk_timers)) {
26687 +               printk(KERN_ERR "%s: no parent clock\n", __func__);
26688 +               return;
26689 +       }
26690 +
26691 +       for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
26692 +               clk_timer_scaler[clk].parent = clk_timers;
26693 +               ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
26694 +               if (ret < 0) {
26695 +                       printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
26696 +                       return;
26697 +               }
26698 +       }
26699 +
26700 +       for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
26701 +               ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
26702 +               if (ret < 0) {
26703 +                       printk(KERN_ERR "error adding pww tclk%d\n", clk);
26704 +                       return;
26705 +               }
26706 +       }
26707 +
26708 +       for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
26709 +               ret = clk_pwm_tdiv_register(clk);
26710 +               if (ret < 0) {
26711 +                       printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
26712 +                       return;
26713 +               }
26714 +       }
26715 +
26716 +       for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
26717 +               ret = clk_pwm_tin_register(&clk_tin[clk]);
26718 +               if (ret < 0) {
26719 +                       printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
26720 +                       return;
26721 +               }
26722 +       }
26723 +}
26724 --- /dev/null
26725 +++ b/arch/arm/plat-s3c/time.c
26726 @@ -0,0 +1,285 @@
26727 +/* linux/arch/arm/plat-s3c24xx/time.c
26728 + *
26729 + * Copyright (C) 2003-2005 Simtec Electronics
26730 + *     Ben Dooks, <ben@simtec.co.uk>
26731 + *
26732 + * This program is free software; you can redistribute it and/or modify
26733 + * it under the terms of the GNU General Public License as published by
26734 + * the Free Software Foundation; either version 2 of the License, or
26735 + * (at your option) any later version.
26736 + *
26737 + * This program is distributed in the hope that it will be useful,
26738 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
26739 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26740 + * GNU General Public License for more details.
26741 + *
26742 + * You should have received a copy of the GNU General Public License
26743 + * along with this program; if not, write to the Free Software
26744 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
26745 + */
26746 +
26747 +#include <linux/kernel.h>
26748 +#include <linux/sched.h>
26749 +#include <linux/init.h>
26750 +#include <linux/interrupt.h>
26751 +#include <linux/irq.h>
26752 +#include <linux/err.h>
26753 +#include <linux/clk.h>
26754 +#include <linux/io.h>
26755 +#include <linux/platform_device.h>
26756 +
26757 +#include <asm/system.h>
26758 +#include <asm/leds.h>
26759 +#include <asm/mach-types.h>
26760 +
26761 +#include <asm/irq.h>
26762 +#include <mach/map.h>
26763 +#include <plat/regs-timer.h>
26764 +#include <mach/regs-irq.h>
26765 +#include <asm/mach/time.h>
26766 +#include <mach/tick.h>
26767 +
26768 +#include <plat/clock.h>
26769 +#include <plat/cpu.h>
26770 +
26771 +static unsigned long timer_startval;
26772 +static unsigned long timer_usec_ticks;
26773 +
26774 +#ifndef TICK_MAX
26775 +#define TICK_MAX (0xffff)
26776 +#endif
26777 +
26778 +#define TIMER_USEC_SHIFT 16
26779 +
26780 +/* we use the shifted arithmetic to work out the ratio of timer ticks
26781 + * to usecs, as often the peripheral clock is not a nice even multiple
26782 + * of 1MHz.
26783 + *
26784 + * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
26785 + * for the current HZ value of 200 without producing overflows.
26786 + *
26787 + * Original patch by Dimitry Andric, updated by Ben Dooks
26788 +*/
26789 +
26790 +
26791 +/* timer_mask_usec_ticks
26792 + *
26793 + * given a clock and divisor, make the value to pass into timer_ticks_to_usec
26794 + * to scale the ticks into usecs
26795 +*/
26796 +
26797 +static inline unsigned long
26798 +timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
26799 +{
26800 +       unsigned long den = pclk / 1000;
26801 +
26802 +       return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
26803 +}
26804 +
26805 +/* timer_ticks_to_usec
26806 + *
26807 + * convert timer ticks to usec.
26808 +*/
26809 +
26810 +static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
26811 +{
26812 +       unsigned long res;
26813 +
26814 +       res = ticks * timer_usec_ticks;
26815 +       res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
26816 +
26817 +       return res >> TIMER_USEC_SHIFT;
26818 +}
26819 +
26820 +/***
26821 + * Returns microsecond  since last clock interrupt.  Note that interrupts
26822 + * will have been disabled by do_gettimeoffset()
26823 + * IRQs are disabled before entering here from do_gettimeofday()
26824 + */
26825 +
26826 +static unsigned long s3c2410_gettimeoffset (void)
26827 +{
26828 +       unsigned long tdone;
26829 +       unsigned long tval;
26830 +
26831 +       /* work out how many ticks have gone since last timer interrupt */
26832 +
26833 +       tval =  __raw_readl(S3C2410_TCNTO(4));
26834 +       tdone = timer_startval - tval;
26835 +
26836 +       /* check to see if there is an interrupt pending */
26837 +
26838 +       if (s3c24xx_ostimer_pending()) {
26839 +               /* re-read the timer, and try and fix up for the missed
26840 +                * interrupt. Note, the interrupt may go off before the
26841 +                * timer has re-loaded from wrapping.
26842 +                */
26843 +
26844 +               tval =  __raw_readl(S3C2410_TCNTO(4));
26845 +               tdone = timer_startval - tval;
26846 +
26847 +               if (tval != 0)
26848 +                       tdone += timer_startval;
26849 +       }
26850 +
26851 +       return timer_ticks_to_usec(tdone);
26852 +}
26853 +
26854 +
26855 +/*
26856 + * IRQ handler for the timer
26857 + */
26858 +static irqreturn_t
26859 +s3c2410_timer_interrupt(int irq, void *dev_id)
26860 +{
26861 +       timer_tick();
26862 +       return IRQ_HANDLED;
26863 +}
26864 +
26865 +static struct irqaction s3c2410_timer_irq = {
26866 +       .name           = "S3C2410 Timer Tick",
26867 +       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
26868 +       .handler        = s3c2410_timer_interrupt,
26869 +};
26870 +
26871 +#define use_tclk1_12() ( \
26872 +       machine_is_bast()       || \
26873 +       machine_is_vr1000()     || \
26874 +       machine_is_anubis()     || \
26875 +       machine_is_osiris())
26876 +
26877 +static struct clk *tin;
26878 +static struct clk *tdiv;
26879 +static struct clk *timerclk;
26880 +
26881 +/*
26882 + * Set up timer interrupt, and return the current time in seconds.
26883 + *
26884 + * Currently we only use timer4, as it is the only timer which has no
26885 + * other function that can be exploited externally
26886 + */
26887 +static void s3c2410_timer_setup (void)
26888 +{
26889 +       unsigned long tcon;
26890 +       unsigned long tcnt;
26891 +       unsigned long tcfg1;
26892 +       unsigned long tcfg0;
26893 +
26894 +       tcnt = TICK_MAX;  /* default value for tcnt */
26895 +
26896 +       /* configure the system for whichever machine is in use */
26897 +
26898 +       if (use_tclk1_12()) {
26899 +               /* timer is at 12MHz, scaler is 1 */
26900 +               timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
26901 +               tcnt = 12000000 / HZ;
26902 +
26903 +               tcfg1 = __raw_readl(S3C2410_TCFG1);
26904 +               tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
26905 +               tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
26906 +               __raw_writel(tcfg1, S3C2410_TCFG1);
26907 +       } else {
26908 +               unsigned long pclk;
26909 +               struct clk *tscaler;
26910 +
26911 +               /* for the h1940 (and others), we use the pclk from the core
26912 +                * to generate the timer values. since values around 50 to
26913 +                * 70MHz are not values we can directly generate the timer
26914 +                * value from, we need to pre-scale and divide before using it.
26915 +                *
26916 +                * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
26917 +                * (8.45 ticks per usec)
26918 +                */
26919 +
26920 +               pclk = clk_get_rate(timerclk);
26921 +
26922 +               /* configure clock tick */
26923 +
26924 +               timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
26925 +
26926 +               tscaler = clk_get_parent(tdiv);
26927 +
26928 +               clk_set_rate(tscaler, pclk / 3);
26929 +               clk_set_rate(tdiv, pclk / 6);
26930 +               clk_set_parent(tin, tdiv);
26931 +
26932 +               tcnt = clk_get_rate(tin) / HZ;
26933 +       }
26934 +
26935 +       tcon = __raw_readl(S3C2410_TCON);
26936 +       tcfg0 = __raw_readl(S3C2410_TCFG0);
26937 +       tcfg1 = __raw_readl(S3C2410_TCFG1);
26938 +
26939 +       /* timers reload after counting zero, so reduce the count by 1 */
26940 +
26941 +       tcnt--;
26942 +
26943 +       printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
26944 +              tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
26945 +
26946 +       /* check to see if timer is within 16bit range... */
26947 +       if (tcnt > TICK_MAX) {
26948 +               panic("setup_timer: HZ is too small, cannot configure timer!");
26949 +               return;
26950 +       }
26951 +
26952 +       __raw_writel(tcfg1, S3C2410_TCFG1);
26953 +       __raw_writel(tcfg0, S3C2410_TCFG0);
26954 +
26955 +       timer_startval = tcnt;
26956 +       __raw_writel(tcnt, S3C2410_TCNTB(4));
26957 +
26958 +       /* ensure timer is stopped... */
26959 +
26960 +       tcon &= ~(7<<20);
26961 +       tcon |= S3C2410_TCON_T4RELOAD;
26962 +       tcon |= S3C2410_TCON_T4MANUALUPD;
26963 +
26964 +       __raw_writel(tcon, S3C2410_TCON);
26965 +       __raw_writel(tcnt, S3C2410_TCNTB(4));
26966 +       __raw_writel(tcnt, S3C2410_TCMPB(4));
26967 +
26968 +       /* start the timer running */
26969 +       tcon |= S3C2410_TCON_T4START;
26970 +       tcon &= ~S3C2410_TCON_T4MANUALUPD;
26971 +       __raw_writel(tcon, S3C2410_TCON);
26972 +}
26973 +
26974 +static void __init s3c2410_timer_resources(void)
26975 +{
26976 +       struct platform_device tmpdev;
26977 +
26978 +       tmpdev.dev.bus = &platform_bus_type;
26979 +       tmpdev.id = 4;
26980 +
26981 +       timerclk = clk_get(NULL, "timers");
26982 +       if (IS_ERR(timerclk))
26983 +               panic("failed to get clock for system timer");
26984 +
26985 +       clk_enable(timerclk);
26986 +
26987 +       if (!use_tclk1_12()) {
26988 +               tin = clk_get(&tmpdev.dev, "pwm-tin");
26989 +               if (IS_ERR(tin))
26990 +                       panic("failed to get pwm-tin clock for system timer");
26991 +
26992 +               tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
26993 +               if (IS_ERR(tdiv))
26994 +                       panic("failed to get pwm-tdiv clock for system timer");
26995 +       }
26996 +
26997 +       clk_enable(tin);
26998 +}
26999 +
27000 +static void __init s3c2410_timer_init(void)
27001 +{
27002 +       s3c2410_timer_resources();
27003 +       s3c2410_timer_setup();
27004 +       setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
27005 +}
27006 +
27007 +struct sys_timer s3c24xx_timer = {
27008 +       .init           = s3c2410_timer_init,
27009 +       .offset         = s3c2410_gettimeoffset,
27010 +       .resume         = s3c2410_timer_setup
27011 +};
27012 --- a/arch/arm/plat-s3c24xx/clock.c
27013 +++ b/arch/arm/plat-s3c24xx/clock.c
27014 @@ -27,18 +27,8 @@
27015  */
27016
27017  #include <linux/init.h>
27018 -#include <linux/module.h>
27019  #include <linux/kernel.h>
27020 -#include <linux/list.h>
27021 -#include <linux/errno.h>
27022 -#include <linux/err.h>
27023 -#include <linux/platform_device.h>
27024 -#include <linux/sysdev.h>
27025 -#include <linux/interrupt.h>
27026 -#include <linux/ioport.h>
27027  #include <linux/clk.h>
27028 -#include <linux/mutex.h>
27029 -#include <linux/delay.h>
27030  #include <linux/io.h>
27031
27032  #include <mach/hardware.h>
27033 @@ -47,490 +37,23 @@
27034  #include <mach/regs-clock.h>
27035  #include <mach/regs-gpio.h>
27036
27037 +#include <plat/cpu-freq.h>
27038 +
27039  #include <plat/clock.h>
27040  #include <plat/cpu.h>
27041 -
27042 -/* clock information */
27043 -
27044 -static LIST_HEAD(clocks);
27045 -
27046 -DEFINE_MUTEX(clocks_mutex);
27047 -
27048 -/* enable and disable calls for use with the clk struct */
27049 -
27050 -static int clk_null_enable(struct clk *clk, int enable)
27051 -{
27052 -       return 0;
27053 -}
27054 -
27055 -/* Clock API calls */
27056 -
27057 -struct clk *clk_get(struct device *dev, const char *id)
27058 -{
27059 -       struct clk *p;
27060 -       struct clk *clk = ERR_PTR(-ENOENT);
27061 -       int idno;
27062 -
27063 -       if (dev == NULL || dev->bus != &platform_bus_type)
27064 -               idno = -1;
27065 -       else
27066 -               idno = to_platform_device(dev)->id;
27067 -
27068 -       mutex_lock(&clocks_mutex);
27069 -
27070 -       list_for_each_entry(p, &clocks, list) {
27071 -               if (p->id == idno &&
27072 -                   strcmp(id, p->name) == 0 &&
27073 -                   try_module_get(p->owner)) {
27074 -                       clk = p;
27075 -                       break;
27076 -               }
27077 -       }
27078 -
27079 -       /* check for the case where a device was supplied, but the
27080 -        * clock that was being searched for is not device specific */
27081 -
27082 -       if (IS_ERR(clk)) {
27083 -               list_for_each_entry(p, &clocks, list) {
27084 -                       if (p->id == -1 && strcmp(id, p->name) == 0 &&
27085 -                           try_module_get(p->owner)) {
27086 -                               clk = p;
27087 -                               break;
27088 -                       }
27089 -               }
27090 -       }
27091 -
27092 -       mutex_unlock(&clocks_mutex);
27093 -       return clk;
27094 -}
27095 -
27096 -void clk_put(struct clk *clk)
27097 -{
27098 -       module_put(clk->owner);
27099 -}
27100 -
27101 -int clk_enable(struct clk *clk)
27102 -{
27103 -       if (IS_ERR(clk) || clk == NULL)
27104 -               return -EINVAL;
27105 -
27106 -       clk_enable(clk->parent);
27107 -
27108 -       mutex_lock(&clocks_mutex);
27109 -
27110 -       if ((clk->usage++) == 0)
27111 -               (clk->enable)(clk, 1);
27112 -
27113 -       mutex_unlock(&clocks_mutex);
27114 -       return 0;
27115 -}
27116 -
27117 -void clk_disable(struct clk *clk)
27118 -{
27119 -       if (IS_ERR(clk) || clk == NULL)
27120 -               return;
27121 -
27122 -       mutex_lock(&clocks_mutex);
27123 -
27124 -       if ((--clk->usage) == 0)
27125 -               (clk->enable)(clk, 0);
27126 -
27127 -       mutex_unlock(&clocks_mutex);
27128 -       clk_disable(clk->parent);
27129 -}
27130 -
27131 -
27132 -unsigned long clk_get_rate(struct clk *clk)
27133 -{
27134 -       if (IS_ERR(clk))
27135 -               return 0;
27136 -
27137 -       if (clk->rate != 0)
27138 -               return clk->rate;
27139 -
27140 -       if (clk->get_rate != NULL)
27141 -               return (clk->get_rate)(clk);
27142 -
27143 -       if (clk->parent != NULL)
27144 -               return clk_get_rate(clk->parent);
27145 -
27146 -       return clk->rate;
27147 -}
27148 -
27149 -long clk_round_rate(struct clk *clk, unsigned long rate)
27150 -{
27151 -       if (!IS_ERR(clk) && clk->round_rate)
27152 -               return (clk->round_rate)(clk, rate);
27153 -
27154 -       return rate;
27155 -}
27156 -
27157 -int clk_set_rate(struct clk *clk, unsigned long rate)
27158 -{
27159 -       int ret;
27160 -
27161 -       if (IS_ERR(clk))
27162 -               return -EINVAL;
27163 -
27164 -       /* We do not default just do a clk->rate = rate as
27165 -        * the clock may have been made this way by choice.
27166 -        */
27167 -
27168 -       WARN_ON(clk->set_rate == NULL);
27169 -
27170 -       if (clk->set_rate == NULL)
27171 -               return -EINVAL;
27172 -
27173 -       mutex_lock(&clocks_mutex);
27174 -       ret = (clk->set_rate)(clk, rate);
27175 -       mutex_unlock(&clocks_mutex);
27176 -
27177 -       return ret;
27178 -}
27179 -
27180 -struct clk *clk_get_parent(struct clk *clk)
27181 -{
27182 -       return clk->parent;
27183 -}
27184 -
27185 -int clk_set_parent(struct clk *clk, struct clk *parent)
27186 -{
27187 -       int ret = 0;
27188 -
27189 -       if (IS_ERR(clk))
27190 -               return -EINVAL;
27191 -
27192 -       mutex_lock(&clocks_mutex);
27193 -
27194 -       if (clk->set_parent)
27195 -               ret = (clk->set_parent)(clk, parent);
27196 -
27197 -       mutex_unlock(&clocks_mutex);
27198 -
27199 -       return ret;
27200 -}
27201 -
27202 -EXPORT_SYMBOL(clk_get);
27203 -EXPORT_SYMBOL(clk_put);
27204 -EXPORT_SYMBOL(clk_enable);
27205 -EXPORT_SYMBOL(clk_disable);
27206 -EXPORT_SYMBOL(clk_get_rate);
27207 -EXPORT_SYMBOL(clk_round_rate);
27208 -EXPORT_SYMBOL(clk_set_rate);
27209 -EXPORT_SYMBOL(clk_get_parent);
27210 -EXPORT_SYMBOL(clk_set_parent);
27211 -
27212 -/* base clocks */
27213 -
27214 -static int clk_default_setrate(struct clk *clk, unsigned long rate)
27215 -{
27216 -       clk->rate = rate;
27217 -       return 0;
27218 -}
27219 -
27220 -struct clk clk_xtal = {
27221 -       .name           = "xtal",
27222 -       .id             = -1,
27223 -       .rate           = 0,
27224 -       .parent         = NULL,
27225 -       .ctrlbit        = 0,
27226 -};
27227 -
27228 -struct clk clk_mpll = {
27229 -       .name           = "mpll",
27230 -       .id             = -1,
27231 -       .set_rate       = clk_default_setrate,
27232 -};
27233 -
27234 -struct clk clk_upll = {
27235 -       .name           = "upll",
27236 -       .id             = -1,
27237 -       .parent         = NULL,
27238 -       .ctrlbit        = 0,
27239 -};
27240 -
27241 -struct clk clk_f = {
27242 -       .name           = "fclk",
27243 -       .id             = -1,
27244 -       .rate           = 0,
27245 -       .parent         = &clk_mpll,
27246 -       .ctrlbit        = 0,
27247 -       .set_rate       = clk_default_setrate,
27248 -};
27249 -
27250 -struct clk clk_h = {
27251 -       .name           = "hclk",
27252 -       .id             = -1,
27253 -       .rate           = 0,
27254 -       .parent         = NULL,
27255 -       .ctrlbit        = 0,
27256 -       .set_rate       = clk_default_setrate,
27257 -};
27258 -
27259 -struct clk clk_p = {
27260 -       .name           = "pclk",
27261 -       .id             = -1,
27262 -       .rate           = 0,
27263 -       .parent         = NULL,
27264 -       .ctrlbit        = 0,
27265 -       .set_rate       = clk_default_setrate,
27266 -};
27267 -
27268 -struct clk clk_usb_bus = {
27269 -       .name           = "usb-bus",
27270 -       .id             = -1,
27271 -       .rate           = 0,
27272 -       .parent         = &clk_upll,
27273 -};
27274 -
27275 -/* clocks that could be registered by external code */
27276 -
27277 -static int s3c24xx_dclk_enable(struct clk *clk, int enable)
27278 -{
27279 -       unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
27280 -
27281 -       if (enable)
27282 -               dclkcon |= clk->ctrlbit;
27283 -       else
27284 -               dclkcon &= ~clk->ctrlbit;
27285 -
27286 -       __raw_writel(dclkcon, S3C24XX_DCLKCON);
27287 -
27288 -       return 0;
27289 -}
27290 -
27291 -static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
27292 -{
27293 -       unsigned long dclkcon;
27294 -       unsigned int uclk;
27295 -
27296 -       if (parent == &clk_upll)
27297 -               uclk = 1;
27298 -       else if (parent == &clk_p)
27299 -               uclk = 0;
27300 -       else
27301 -               return -EINVAL;
27302 -
27303 -       clk->parent = parent;
27304 -
27305 -       dclkcon = __raw_readl(S3C24XX_DCLKCON);
27306 -
27307 -       if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
27308 -               if (uclk)
27309 -                       dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
27310 -               else
27311 -                       dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
27312 -       } else {
27313 -               if (uclk)
27314 -                       dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
27315 -               else
27316 -                       dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
27317 -       }
27318 -
27319 -       __raw_writel(dclkcon, S3C24XX_DCLKCON);
27320 -
27321 -       return 0;
27322 -}
27323 -
27324 -static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
27325 -{
27326 -       unsigned long div;
27327 -
27328 -       if ((rate == 0) || !clk->parent)
27329 -               return 0;
27330 -
27331 -       div = clk_get_rate(clk->parent) / rate;
27332 -       if (div < 2)
27333 -               div = 2;
27334 -       else if (div > 16)
27335 -               div = 16;
27336 -
27337 -       return div;
27338 -}
27339 -
27340 -static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
27341 -       unsigned long rate)
27342 -{
27343 -       unsigned long div = s3c24xx_calc_div(clk, rate);
27344 -
27345 -       if (div == 0)
27346 -               return 0;
27347 -
27348 -       return clk_get_rate(clk->parent) / div;
27349 -}
27350 -
27351 -static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
27352 -{
27353 -       unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
27354 -
27355 -       if (div == 0)
27356 -               return -EINVAL;
27357 -
27358 -       if (clk == &s3c24xx_dclk0) {
27359 -               mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
27360 -                       S3C2410_DCLKCON_DCLK0_CMP_MASK;
27361 -               data = S3C2410_DCLKCON_DCLK0_DIV(div) |
27362 -                       S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
27363 -       } else if (clk == &s3c24xx_dclk1) {
27364 -               mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
27365 -                       S3C2410_DCLKCON_DCLK1_CMP_MASK;
27366 -               data = S3C2410_DCLKCON_DCLK1_DIV(div) |
27367 -                       S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
27368 -       } else
27369 -               return -EINVAL;
27370 -
27371 -       clk->rate = clk_get_rate(clk->parent) / div;
27372 -       __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
27373 -               S3C24XX_DCLKCON);
27374 -       return clk->rate;
27375 -}
27376 -
27377 -static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
27378 -{
27379 -       unsigned long mask;
27380 -       unsigned long source;
27381 -
27382 -       /* calculate the MISCCR setting for the clock */
27383 -
27384 -       if (parent == &clk_xtal)
27385 -               source = S3C2410_MISCCR_CLK0_MPLL;
27386 -       else if (parent == &clk_upll)
27387 -               source = S3C2410_MISCCR_CLK0_UPLL;
27388 -       else if (parent == &clk_f)
27389 -               source = S3C2410_MISCCR_CLK0_FCLK;
27390 -       else if (parent == &clk_h)
27391 -               source = S3C2410_MISCCR_CLK0_HCLK;
27392 -       else if (parent == &clk_p)
27393 -               source = S3C2410_MISCCR_CLK0_PCLK;
27394 -       else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
27395 -               source = S3C2410_MISCCR_CLK0_DCLK0;
27396 -       else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
27397 -               source = S3C2410_MISCCR_CLK0_DCLK0;
27398 -       else
27399 -               return -EINVAL;
27400 -
27401 -       clk->parent = parent;
27402 -
27403 -       if (clk == &s3c24xx_clkout0)
27404 -               mask = S3C2410_MISCCR_CLK0_MASK;
27405 -       else {
27406 -               source <<= 4;
27407 -               mask = S3C2410_MISCCR_CLK1_MASK;
27408 -       }
27409 -
27410 -       s3c2410_modify_misccr(mask, source);
27411 -       return 0;
27412 -}
27413 -
27414 -/* external clock definitions */
27415 -
27416 -struct clk s3c24xx_dclk0 = {
27417 -       .name           = "dclk0",
27418 -       .id             = -1,
27419 -       .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
27420 -       .enable         = s3c24xx_dclk_enable,
27421 -       .set_parent     = s3c24xx_dclk_setparent,
27422 -       .set_rate       = s3c24xx_set_dclk_rate,
27423 -       .round_rate     = s3c24xx_round_dclk_rate,
27424 -};
27425 -
27426 -struct clk s3c24xx_dclk1 = {
27427 -       .name           = "dclk1",
27428 -       .id             = -1,
27429 -       .ctrlbit        = S3C2410_DCLKCON_DCLK1EN,
27430 -       .enable         = s3c24xx_dclk_enable,
27431 -       .set_parent     = s3c24xx_dclk_setparent,
27432 -       .set_rate       = s3c24xx_set_dclk_rate,
27433 -       .round_rate     = s3c24xx_round_dclk_rate,
27434 -};
27435 -
27436 -struct clk s3c24xx_clkout0 = {
27437 -       .name           = "clkout0",
27438 -       .id             = -1,
27439 -       .set_parent     = s3c24xx_clkout_setparent,
27440 -};
27441 -
27442 -struct clk s3c24xx_clkout1 = {
27443 -       .name           = "clkout1",
27444 -       .id             = -1,
27445 -       .set_parent     = s3c24xx_clkout_setparent,
27446 -};
27447 -
27448 -struct clk s3c24xx_uclk = {
27449 -       .name           = "uclk",
27450 -       .id             = -1,
27451 -};
27452 -
27453 -/* initialise the clock system */
27454 -
27455 -int s3c24xx_register_clock(struct clk *clk)
27456 -{
27457 -       clk->owner = THIS_MODULE;
27458 -
27459 -       if (clk->enable == NULL)
27460 -               clk->enable = clk_null_enable;
27461 -
27462 -       /* add to the list of available clocks */
27463 -
27464 -       mutex_lock(&clocks_mutex);
27465 -       list_add(&clk->list, &clocks);
27466 -       mutex_unlock(&clocks_mutex);
27467 -
27468 -       return 0;
27469 -}
27470 -
27471 -int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
27472 -{
27473 -       int fails = 0;
27474 -
27475 -       for (; nr_clks > 0; nr_clks--, clks++) {
27476 -               if (s3c24xx_register_clock(*clks) < 0)
27477 -                       fails++;
27478 -       }
27479 -
27480 -       return fails;
27481 -}
27482 +#include <plat/pll.h>
27483
27484  /* initalise all the clocks */
27485
27486 -int __init s3c24xx_setup_clocks(unsigned long xtal,
27487 -                               unsigned long fclk,
27488 -                               unsigned long hclk,
27489 -                               unsigned long pclk)
27490 +void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
27491 +                                          unsigned long hclk,
27492 +                                          unsigned long pclk)
27493  {
27494 -       printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
27495 -
27496 -       /* initialise the main system clocks */
27497 -
27498 -       clk_xtal.rate = xtal;
27499 -       clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
27500 +       clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
27501 +                                       clk_xtal.rate);
27502
27503         clk_mpll.rate = fclk;
27504         clk_h.rate = hclk;
27505         clk_p.rate = pclk;
27506         clk_f.rate = fclk;
27507 -
27508 -       /* assume uart clocks are correctly setup */
27509 -
27510 -       /* register our clocks */
27511 -
27512 -       if (s3c24xx_register_clock(&clk_xtal) < 0)
27513 -               printk(KERN_ERR "failed to register master xtal\n");
27514 -
27515 -       if (s3c24xx_register_clock(&clk_mpll) < 0)
27516 -               printk(KERN_ERR "failed to register mpll clock\n");
27517 -
27518 -       if (s3c24xx_register_clock(&clk_upll) < 0)
27519 -               printk(KERN_ERR "failed to register upll clock\n");
27520 -
27521 -       if (s3c24xx_register_clock(&clk_f) < 0)
27522 -               printk(KERN_ERR "failed to register cpu fclk\n");
27523 -
27524 -       if (s3c24xx_register_clock(&clk_h) < 0)
27525 -               printk(KERN_ERR "failed to register cpu hclk\n");
27526 -
27527 -       if (s3c24xx_register_clock(&clk_p) < 0)
27528 -               printk(KERN_ERR "failed to register cpu pclk\n");
27529 -
27530 -       return 0;
27531  }
27532 --- /dev/null
27533 +++ b/arch/arm/plat-s3c24xx/clock-dclk.c
27534 @@ -0,0 +1,194 @@
27535 +/* linux/arch/arm/plat-s3c24xx/clock-dclk.c
27536 + *
27537 + * Copyright (c) 2004,2008 Simtec Electronics
27538 + *     Ben Dooks <ben@simtec.co.uk>
27539 + *     http://armlinux.simtec.co.uk/
27540 + *
27541 + * This program is free software; you can redistribute it and/or modify
27542 + * it under the terms of the GNU General Public License version 2 as
27543 + * published by the Free Software Foundation.
27544 + *
27545 + * S3C24XX - definitions for DCLK and CLKOUT registers
27546 + */
27547 +
27548 +#include <linux/kernel.h>
27549 +#include <linux/errno.h>
27550 +#include <linux/clk.h>
27551 +#include <linux/io.h>
27552 +
27553 +#include <mach/regs-clock.h>
27554 +#include <mach/regs-gpio.h>
27555 +
27556 +#include <plat/clock.h>
27557 +#include <plat/cpu.h>
27558 +
27559 +/* clocks that could be registered by external code */
27560 +
27561 +static int s3c24xx_dclk_enable(struct clk *clk, int enable)
27562 +{
27563 +       unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
27564 +
27565 +       if (enable)
27566 +               dclkcon |= clk->ctrlbit;
27567 +       else
27568 +               dclkcon &= ~clk->ctrlbit;
27569 +
27570 +       __raw_writel(dclkcon, S3C24XX_DCLKCON);
27571 +
27572 +       return 0;
27573 +}
27574 +
27575 +static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
27576 +{
27577 +       unsigned long dclkcon;
27578 +       unsigned int uclk;
27579 +
27580 +       if (parent == &clk_upll)
27581 +               uclk = 1;
27582 +       else if (parent == &clk_p)
27583 +               uclk = 0;
27584 +       else
27585 +               return -EINVAL;
27586 +
27587 +       clk->parent = parent;
27588 +
27589 +       dclkcon = __raw_readl(S3C24XX_DCLKCON);
27590 +
27591 +       if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
27592 +               if (uclk)
27593 +                       dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
27594 +               else
27595 +                       dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
27596 +       } else {
27597 +               if (uclk)
27598 +                       dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
27599 +               else
27600 +                       dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
27601 +       }
27602 +
27603 +       __raw_writel(dclkcon, S3C24XX_DCLKCON);
27604 +
27605 +       return 0;
27606 +}
27607 +static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
27608 +{
27609 +       unsigned long div;
27610 +
27611 +       if ((rate == 0) || !clk->parent)
27612 +               return 0;
27613 +
27614 +       div = clk_get_rate(clk->parent) / rate;
27615 +       if (div < 2)
27616 +               div = 2;
27617 +       else if (div > 16)
27618 +               div = 16;
27619 +
27620 +       return div;
27621 +}
27622 +
27623 +static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
27624 +       unsigned long rate)
27625 +{
27626 +       unsigned long div = s3c24xx_calc_div(clk, rate);
27627 +
27628 +       if (div == 0)
27629 +               return 0;
27630 +
27631 +       return clk_get_rate(clk->parent) / div;
27632 +}
27633 +
27634 +static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
27635 +{
27636 +       unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
27637 +
27638 +       if (div == 0)
27639 +               return -EINVAL;
27640 +
27641 +       if (clk == &s3c24xx_dclk0) {
27642 +               mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
27643 +                       S3C2410_DCLKCON_DCLK0_CMP_MASK;
27644 +               data = S3C2410_DCLKCON_DCLK0_DIV(div) |
27645 +                       S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
27646 +       } else if (clk == &s3c24xx_dclk1) {
27647 +               mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
27648 +                       S3C2410_DCLKCON_DCLK1_CMP_MASK;
27649 +               data = S3C2410_DCLKCON_DCLK1_DIV(div) |
27650 +                       S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
27651 +       } else
27652 +               return -EINVAL;
27653 +
27654 +       clk->rate = clk_get_rate(clk->parent) / div;
27655 +       __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
27656 +               S3C24XX_DCLKCON);
27657 +       return clk->rate;
27658 +}
27659 +static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
27660 +{
27661 +       unsigned long mask;
27662 +       unsigned long source;
27663 +
27664 +       /* calculate the MISCCR setting for the clock */
27665 +
27666 +       if (parent == &clk_xtal)
27667 +               source = S3C2410_MISCCR_CLK0_MPLL;
27668 +       else if (parent == &clk_upll)
27669 +               source = S3C2410_MISCCR_CLK0_UPLL;
27670 +       else if (parent == &clk_f)
27671 +               source = S3C2410_MISCCR_CLK0_FCLK;
27672 +       else if (parent == &clk_h)
27673 +               source = S3C2410_MISCCR_CLK0_HCLK;
27674 +       else if (parent == &clk_p)
27675 +               source = S3C2410_MISCCR_CLK0_PCLK;
27676 +       else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
27677 +               source = S3C2410_MISCCR_CLK0_DCLK0;
27678 +       else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
27679 +               source = S3C2410_MISCCR_CLK0_DCLK0;
27680 +       else
27681 +               return -EINVAL;
27682 +
27683 +       clk->parent = parent;
27684 +
27685 +       if (clk == &s3c24xx_clkout0)
27686 +               mask = S3C2410_MISCCR_CLK0_MASK;
27687 +       else {
27688 +               source <<= 4;
27689 +               mask = S3C2410_MISCCR_CLK1_MASK;
27690 +       }
27691 +
27692 +       s3c2410_modify_misccr(mask, source);
27693 +       return 0;
27694 +}
27695 +
27696 +/* external clock definitions */
27697 +
27698 +struct clk s3c24xx_dclk0 = {
27699 +       .name           = "dclk0",
27700 +       .id             = -1,
27701 +       .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
27702 +       .enable         = s3c24xx_dclk_enable,
27703 +       .set_parent     = s3c24xx_dclk_setparent,
27704 +       .set_rate       = s3c24xx_set_dclk_rate,
27705 +       .round_rate     = s3c24xx_round_dclk_rate,
27706 +};
27707 +
27708 +struct clk s3c24xx_dclk1 = {
27709 +       .name           = "dclk1",
27710 +       .id             = -1,
27711 +       .ctrlbit        = S3C2410_DCLKCON_DCLK1EN,
27712 +       .enable         = s3c24xx_dclk_enable,
27713 +       .set_parent     = s3c24xx_dclk_setparent,
27714 +       .set_rate       = s3c24xx_set_dclk_rate,
27715 +       .round_rate     = s3c24xx_round_dclk_rate,
27716 +};
27717 +
27718 +struct clk s3c24xx_clkout0 = {
27719 +       .name           = "clkout0",
27720 +       .id             = -1,
27721 +       .set_parent     = s3c24xx_clkout_setparent,
27722 +};
27723 +
27724 +struct clk s3c24xx_clkout1 = {
27725 +       .name           = "clkout1",
27726 +       .id             = -1,
27727 +       .set_parent     = s3c24xx_clkout_setparent,
27728 +};
27729 --- a/arch/arm/plat-s3c24xx/common-smdk.c
27730 +++ b/arch/arm/plat-s3c24xx/common-smdk.c
27731 @@ -38,7 +38,7 @@
27732  #include <mach/regs-gpio.h>
27733  #include <mach/leds-gpio.h>
27734
27735 -#include <asm/plat-s3c/nand.h>
27736 +#include <plat/nand.h>
27737
27738  #include <plat/common-smdk.h>
27739  #include <plat/devs.h>
27740 @@ -201,5 +201,5 @@ void __init smdk_machine_init(void)
27741
27742         platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
27743
27744 -       s3c2410_pm_init();
27745 +       s3c_pm_init();
27746  }
27747 --- a/arch/arm/plat-s3c24xx/cpu.c
27748 +++ b/arch/arm/plat-s3c24xx/cpu.c
27749 @@ -55,16 +55,6 @@
27750  #include <plat/s3c2442.h>
27751  #include <plat/s3c2443.h>
27752
27753 -struct cpu_table {
27754 -       unsigned long   idcode;
27755 -       unsigned long   idmask;
27756 -       void            (*map_io)(struct map_desc *mach_desc, int size);
27757 -       void            (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
27758 -       void            (*init_clocks)(int xtal);
27759 -       int             (*init)(void);
27760 -       const char      *name;
27761 -};
27762 -
27763  /* table of supported CPUs */
27764
27765  static const char name_s3c2400[]  = "S3C2400";
27766 @@ -72,6 +62,7 @@ static const char name_s3c2410[]  = "S3C
27767  static const char name_s3c2412[]  = "S3C2412";
27768  static const char name_s3c2440[]  = "S3C2440";
27769  static const char name_s3c2442[]  = "S3C2442";
27770 +static const char name_s3c2442b[]  = "S3C2442B";
27771  static const char name_s3c2443[]  = "S3C2443";
27772  static const char name_s3c2410a[] = "S3C2410A";
27773  static const char name_s3c2440a[] = "S3C2440A";
27774 @@ -123,6 +114,15 @@ static struct cpu_table cpu_ids[] __init
27775                 .name           = name_s3c2442
27776         },
27777         {
27778 +               .idcode         = 0x32440aab,
27779 +               .idmask         = 0xffffffff,
27780 +               .map_io         = s3c244x_map_io,
27781 +               .init_clocks    = s3c244x_init_clocks,
27782 +               .init_uarts     = s3c244x_init_uarts,
27783 +               .init           = s3c2442_init,
27784 +               .name           = name_s3c2442b
27785 +       },
27786 +       {
27787                 .idcode         = 0x32412001,
27788                 .idmask         = 0xffffffff,
27789                 .map_io         = s3c2412_map_io,
27790 @@ -169,23 +169,7 @@ static struct map_desc s3c_iodesc[] __in
27791         IODESC_ENT(UART)
27792  };
27793
27794 -static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode)
27795 -{
27796 -       struct cpu_table *tab;
27797 -       int count;
27798 -
27799 -       tab = cpu_ids;
27800 -       for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
27801 -               if ((idcode & tab->idmask) == tab->idcode)
27802 -                       return tab;
27803 -       }
27804 -
27805 -       return NULL;
27806 -}
27807 -
27808 -/* cpu information */
27809 -
27810 -static struct cpu_table *cpu;
27811 +/* read cpu identificaiton code */
27812
27813  static unsigned long s3c24xx_read_idcode_v5(void)
27814  {
27815 @@ -231,6 +215,7 @@ void __init s3c24xx_init_io(struct map_d
27816         unsigned long idcode = 0x0;
27817
27818         /* initialise the io descriptors we need for initialisation */
27819 +       iotable_init(mach_desc, size);
27820         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
27821
27822         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
27823 @@ -239,117 +224,7 @@ void __init s3c24xx_init_io(struct map_d
27824                 idcode = s3c24xx_read_idcode_v4();
27825         }
27826
27827 -       cpu = s3c_lookup_cpu(idcode);
27828 -
27829 -       if (cpu == NULL) {
27830 -               printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
27831 -               panic("Unknown S3C24XX CPU");
27832 -       }
27833 -
27834 -       printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
27835 -
27836 -       if (cpu->map_io == NULL || cpu->init == NULL) {
27837 -               printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
27838 -               panic("Unsupported S3C24XX CPU");
27839 -       }
27840 -
27841         arm_pm_restart = s3c24xx_pm_restart;
27842
27843 -       (cpu->map_io)(mach_desc, size);
27844 -}
27845 -
27846 -/* s3c24xx_init_clocks
27847 - *
27848 - * Initialise the clock subsystem and associated information from the
27849 - * given master crystal value.
27850 - *
27851 - * xtal  = 0 -> use default PLL crystal value (normally 12MHz)
27852 - *      != 0 -> PLL crystal value in Hz
27853 -*/
27854 -
27855 -void __init s3c24xx_init_clocks(int xtal)
27856 -{
27857 -       if (xtal == 0)
27858 -               xtal = 12*1000*1000;
27859 -
27860 -       if (cpu == NULL)
27861 -               panic("s3c24xx_init_clocks: no cpu setup?\n");
27862 -
27863 -       if (cpu->init_clocks == NULL)
27864 -               panic("s3c24xx_init_clocks: cpu has no clock init\n");
27865 -       else
27866 -               (cpu->init_clocks)(xtal);
27867 +       s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
27868  }
27869 -
27870 -/* uart management */
27871 -
27872 -static int nr_uarts __initdata = 0;
27873 -
27874 -static struct s3c2410_uartcfg uart_cfgs[3];
27875 -
27876 -/* s3c24xx_init_uartdevs
27877 - *
27878 - * copy the specified platform data and configuration into our central
27879 - * set of devices, before the data is thrown away after the init process.
27880 - *
27881 - * This also fills in the array passed to the serial driver for the
27882 - * early initialisation of the console.
27883 -*/
27884 -
27885 -void __init s3c24xx_init_uartdevs(char *name,
27886 -                                 struct s3c24xx_uart_resources *res,
27887 -                                 struct s3c2410_uartcfg *cfg, int no)
27888 -{
27889 -       struct platform_device *platdev;
27890 -       struct s3c2410_uartcfg *cfgptr = uart_cfgs;
27891 -       struct s3c24xx_uart_resources *resp;
27892 -       int uart;
27893 -
27894 -       memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
27895 -
27896 -       for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
27897 -               platdev = s3c24xx_uart_src[cfgptr->hwport];
27898 -
27899 -               resp = res + cfgptr->hwport;
27900 -
27901 -               s3c24xx_uart_devs[uart] = platdev;
27902 -
27903 -               platdev->name = name;
27904 -               platdev->resource = resp->resources;
27905 -               platdev->num_resources = resp->nr_resources;
27906 -
27907 -               platdev->dev.platform_data = cfgptr;
27908 -       }
27909 -
27910 -       nr_uarts = no;
27911 -}
27912 -
27913 -void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
27914 -{
27915 -       if (cpu == NULL)
27916 -               return;
27917 -
27918 -       if (cpu->init_uarts == NULL) {
27919 -               printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
27920 -       } else
27921 -               (cpu->init_uarts)(cfg, no);
27922 -}
27923 -
27924 -static int __init s3c_arch_init(void)
27925 -{
27926 -       int ret;
27927 -
27928 -       // do the correct init for cpu
27929 -
27930 -       if (cpu == NULL)
27931 -               panic("s3c_arch_init: NULL cpu\n");
27932 -
27933 -       ret = (cpu->init)();
27934 -       if (ret != 0)
27935 -               return ret;
27936 -
27937 -       ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
27938 -       return ret;
27939 -}
27940 -
27941 -arch_initcall(s3c_arch_init);
27942 --- a/arch/arm/plat-s3c24xx/devs.c
27943 +++ b/arch/arm/plat-s3c24xx/devs.c
27944 @@ -26,14 +26,16 @@
27945  #include <asm/mach/irq.h>
27946  #include <mach/fb.h>
27947  #include <mach/hardware.h>
27948 +#include <mach/ts.h>
27949 +#include <asm/io.h>
27950  #include <asm/irq.h>
27951
27952  #include <plat/regs-serial.h>
27953 -#include <asm/plat-s3c24xx/udc.h>
27954 +#include <plat/udc.h>
27955
27956  #include <plat/devs.h>
27957  #include <plat/cpu.h>
27958 -#include <asm/plat-s3c24xx/regs-spi.h>
27959 +#include <plat/regs-spi.h>
27960
27961  /* Serial port registrations */
27962
27963 @@ -76,6 +78,19 @@ static struct resource s3c2410_uart2_res
27964         }
27965  };
27966
27967 +static struct resource s3c2410_uart3_resource[] = {
27968 +       [0] = {
27969 +               .start = S3C2443_PA_UART3,
27970 +               .end   = S3C2443_PA_UART3 + 0x3fff,
27971 +               .flags = IORESOURCE_MEM,
27972 +       },
27973 +       [1] = {
27974 +               .start = IRQ_S3CUART_RX3,
27975 +               .end   = IRQ_S3CUART_ERR3,
27976 +               .flags = IORESOURCE_IRQ,
27977 +       },
27978 +};
27979 +
27980  struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
27981         [0] = {
27982                 .resources      = s3c2410_uart0_resource,
27983 @@ -89,6 +104,10 @@ struct s3c24xx_uart_resources s3c2410_ua
27984                 .resources      = s3c2410_uart2_resource,
27985                 .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
27986         },
27987 +       [3] = {
27988 +               .resources      = s3c2410_uart3_resource,
27989 +               .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
27990 +       },
27991  };
27992
27993  /* yart devices */
27994 @@ -105,13 +124,18 @@ static struct platform_device s3c24xx_ua
27995         .id             = 2,
27996  };
27997
27998 -struct platform_device *s3c24xx_uart_src[3] = {
27999 +static struct platform_device s3c24xx_uart_device3 = {
28000 +       .id             = 3,
28001 +};
28002 +
28003 +struct platform_device *s3c24xx_uart_src[4] = {
28004         &s3c24xx_uart_device0,
28005         &s3c24xx_uart_device1,
28006         &s3c24xx_uart_device2,
28007 +       &s3c24xx_uart_device3,
28008  };
28009
28010 -struct platform_device *s3c24xx_uart_devs[3] = {
28011 +struct platform_device *s3c24xx_uart_devs[4] = {
28012  };
28013
28014  /* USB Host Controller */
28015 @@ -192,8 +216,8 @@ void __init s3c24xx_fb_set_platdata(stru
28016
28017  static struct resource s3c_nand_resource[] = {
28018         [0] = {
28019 -               .start = S3C2410_PA_NAND,
28020 -               .end   = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
28021 +               .start = S3C24XX_PA_NAND,
28022 +               .end   = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
28023                 .flags = IORESOURCE_MEM,
28024         }
28025  };
28026 @@ -207,6 +231,23 @@ struct platform_device s3c_device_nand =
28027
28028  EXPORT_SYMBOL(s3c_device_nand);
28029
28030 +/* Touchscreen */
28031 +struct platform_device s3c_device_ts = {
28032 +       .name             = "s3c2410-ts",
28033 +       .id               = -1,
28034 +};
28035 +
28036 +EXPORT_SYMBOL(s3c_device_ts);
28037 +
28038 +static struct s3c2410_ts_mach_info s3c2410ts_info;
28039 +
28040 +void set_s3c2410ts_info(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
28041 +{
28042 +       memcpy(&s3c2410ts_info,hard_s3c2410ts_info,sizeof(struct s3c2410_ts_mach_info));
28043 +       s3c_device_ts.dev.platform_data = &s3c2410ts_info;
28044 +}
28045 +EXPORT_SYMBOL(set_s3c2410ts_info);
28046 +
28047  /* USB Device (Gadget)*/
28048
28049  static struct resource s3c_usbgadget_resource[] = {
28050 @@ -271,31 +312,6 @@ struct platform_device s3c_device_wdt =
28051
28052  EXPORT_SYMBOL(s3c_device_wdt);
28053
28054 -/* I2C */
28055 -
28056 -static struct resource s3c_i2c_resource[] = {
28057 -       [0] = {
28058 -               .start = S3C24XX_PA_IIC,
28059 -               .end   = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
28060 -               .flags = IORESOURCE_MEM,
28061 -       },
28062 -       [1] = {
28063 -               .start = IRQ_IIC,
28064 -               .end   = IRQ_IIC,
28065 -               .flags = IORESOURCE_IRQ,
28066 -       }
28067 -
28068 -};
28069 -
28070 -struct platform_device s3c_device_i2c = {
28071 -       .name             = "s3c2410-i2c",
28072 -       .id               = -1,
28073 -       .num_resources    = ARRAY_SIZE(s3c_i2c_resource),
28074 -       .resource         = s3c_i2c_resource,
28075 -};
28076 -
28077 -EXPORT_SYMBOL(s3c_device_i2c);
28078 -
28079  /* IIS */
28080
28081  static struct resource s3c_iis_resource[] = {
28082 @@ -382,8 +398,8 @@ struct platform_device s3c_device_adc =
28083
28084  static struct resource s3c_sdi_resource[] = {
28085         [0] = {
28086 -               .start = S3C2410_PA_SDI,
28087 -               .end   = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
28088 +               .start = S3C24XX_PA_SDI,
28089 +               .end   = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,
28090                 .flags = IORESOURCE_MEM,
28091         },
28092         [1] = {
28093 @@ -403,36 +419,6 @@ struct platform_device s3c_device_sdi =
28094
28095  EXPORT_SYMBOL(s3c_device_sdi);
28096
28097 -/* High-speed MMC/SD */
28098 -
28099 -static struct resource s3c_hsmmc_resource[] = {
28100 -       [0] = {
28101 -               .start = S3C2443_PA_HSMMC,
28102 -               .end   = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
28103 -               .flags = IORESOURCE_MEM,
28104 -       },
28105 -       [1] = {
28106 -               .start = IRQ_S3C2443_HSMMC,
28107 -               .end   = IRQ_S3C2443_HSMMC,
28108 -               .flags = IORESOURCE_IRQ,
28109 -       }
28110 -};
28111 -
28112 -static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
28113 -
28114 -struct platform_device s3c_device_hsmmc = {
28115 -       .name             = "s3c-sdhci",
28116 -       .id               = -1,
28117 -       .num_resources    = ARRAY_SIZE(s3c_hsmmc_resource),
28118 -       .resource         = s3c_hsmmc_resource,
28119 -       .dev              = {
28120 -               .dma_mask = &s3c_device_hsmmc_dmamask,
28121 -               .coherent_dma_mask = 0xffffffffUL
28122 -       }
28123 -};
28124 -
28125 -
28126 -
28127  /* SPI (0) */
28128
28129  static struct resource s3c_spi0_resource[] = {
28130 --- a/arch/arm/plat-s3c24xx/gpio.c
28131 +++ b/arch/arm/plat-s3c24xx/gpio.c
28132 @@ -32,6 +32,7 @@
28133  #include <asm/irq.h>
28134
28135  #include <mach/regs-gpio.h>
28136 +#include <mach/regs-gpioj.h>
28137
28138  void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
28139  {
28140 @@ -215,3 +216,423 @@ int s3c2410_gpio_irq2pin(unsigned int ir
28141  }
28142
28143  EXPORT_SYMBOL(s3c2410_gpio_irq2pin);
28144 +
28145 +static void pretty_dump(u32 cfg, u32 state, u32 pull,
28146 +                       const char ** function_names_2,
28147 +                       const char ** function_names_3,
28148 +                       const char * prefix,
28149 +                       int count)
28150 +{
28151 +       int n;
28152 +       const char *tag_type = NULL,
28153 +                  *tag_state = NULL,
28154 +                  *tag_pulldown = NULL,
28155 +                  * level0 = "0",
28156 +                  * level1 = "1";
28157 +
28158 +       for (n = 0; n < count; n++) {
28159 +               switch ((cfg >> (2 * n)) & 3) {
28160 +               case 0:
28161 +                       tag_type = "input      ";
28162 +                       break;
28163 +               case 1:
28164 +                       tag_type = "OUTPUT     ";
28165 +                       break;
28166 +               case 2:
28167 +                       if (function_names_2) {
28168 +                               if (function_names_2[n])
28169 +                                       tag_type = function_names_2[n];
28170 +                               else
28171 +                                       tag_type = "*** ILLEGAL CFG (2) *** ";
28172 +                       } else
28173 +                               tag_type = "(function) ";
28174 +                       break;
28175 +               default:
28176 +                       if (function_names_3) {
28177 +                               if (function_names_3[n])
28178 +                                       tag_type = function_names_3[n];
28179 +                               else
28180 +                                       tag_type = "*** ILLEGAL CFG (3) *** ";
28181 +                       } else
28182 +                               tag_type = "(function) ";
28183 +                       break;
28184 +               }
28185 +               if ((state >> n) & 1)
28186 +                       tag_state = level1;
28187 +               else
28188 +                       tag_state = level0;
28189 +
28190 +               if (((pull >> n) & 1))
28191 +                       tag_pulldown = "";
28192 +               else
28193 +                       tag_pulldown = "(pulldown)";
28194 +
28195 +               printk(KERN_INFO"%s%02d: %s %s %s\n", prefix, n, tag_type,
28196 +                                                     tag_state, tag_pulldown);
28197 +       }
28198 +       printk(KERN_INFO"\n");
28199 +}
28200 +
28201 +static void pretty_dump_a(u32 cfg, u32 state,
28202 +                         const char ** function_names,
28203 +                         const char * prefix,
28204 +                         int count)
28205 +{
28206 +       int n;
28207 +       const char *tag_type = NULL,
28208 +                  *tag_state = NULL,
28209 +                  * level0 = "0",
28210 +                  * level1 = "1";
28211 +
28212 +       for (n = 0; n < count; n++) {
28213 +               switch ((cfg >> n) & 1) {
28214 +               case 0:
28215 +                       tag_type = "OUTPUT     ";
28216 +                       break;
28217 +               default:
28218 +                       if (function_names) {
28219 +                               if (function_names[n])
28220 +                                       tag_type = function_names[n];
28221 +                               else
28222 +                                       tag_type = "*** ILLEGAL CFG *** ";
28223 +                       } else
28224 +                               tag_type = "(function) ";
28225 +                       break;
28226 +               }
28227 +               if ((state >> n) & 1)
28228 +                       tag_state = level1;
28229 +               else
28230 +                       tag_state = level0;
28231 +
28232 +               printk(KERN_INFO"%s%02d: %s %s\n", prefix, n, tag_type,
28233 +                                                  tag_state);
28234 +       }
28235 +       printk(KERN_INFO"\n");
28236 +}
28237 +
28238 +static const char * funcs_a[] = {
28239 +       "ADDR0      ",
28240 +       "ADDR16     ",
28241 +       "ADDR17     ",
28242 +       "ADDR18     ",
28243 +       "ADDR19     ",
28244 +       "ADDR20     ",
28245 +       "ADDR21     ",
28246 +       "ADDR22     ",
28247 +       "ADDR23     ",
28248 +       "ADDR24     ",
28249 +       "ADDR25     ",
28250 +       "ADDR26     ",
28251 +       "nGCS[1]    ",
28252 +       "nGCS[2]    ",
28253 +       "nGCS[3]    ",
28254 +       "nGCS[4]    ",
28255 +       "nGCS[5]    ",
28256 +       "CLE        ",
28257 +       "ALE        ",
28258 +       "nFWE       ",
28259 +       "nFRE       ",
28260 +       "nRSTOUT    ",
28261 +       "nFCE       ",
28262 +       NULL,
28263 +       NULL
28264 +};
28265 +
28266 +
28267 +static const char * funcs_b2[] = {
28268 +       "TOUT0      ",
28269 +       "TOUT1      ",
28270 +       "TOUT2      ",
28271 +       "TOUT3      ",
28272 +       "TCLK[0]    ",
28273 +       "nXBACK     ",
28274 +       "nXBREQ     ",
28275 +       "nXDACK1    ",
28276 +       "nXDREQ1    ",
28277 +       "nXDACK0    ",
28278 +       "nXDREQ0    ",
28279 +};
28280 +static const char * funcs_b3[] = {
28281 +       NULL,
28282 +       NULL,
28283 +       NULL,
28284 +       NULL,
28285 +       NULL,
28286 +       NULL,
28287 +       NULL,
28288 +       NULL,
28289 +       NULL,
28290 +       NULL,
28291 +       NULL,
28292 +};
28293 +
28294 +static const char * funcs_c2[] = {
28295 +       "LEND       ",
28296 +       "VCLK       ",
28297 +       "VLINE      ",
28298 +       "VFRAME     ",
28299 +       "VM         ",
28300 +       "LCD_LPCOE  ",
28301 +       "LCD_LPCREV ",
28302 +       "LCD_LPCREVB",
28303 +       "VD[0]      ",
28304 +       "VD[1]      ",
28305 +       "VD[2]      ",
28306 +       "VD[3]      ",
28307 +       "VD[4]      ",
28308 +       "VD[5]      ",
28309 +       "VD[6]      ",
28310 +       "VD[7]      ",
28311 +};
28312 +static const char * funcs_c3[] = {
28313 +       NULL,
28314 +       NULL,
28315 +       NULL,
28316 +       NULL,
28317 +       "I2SSDI     ",
28318 +       NULL,
28319 +       NULL,
28320 +       NULL,
28321 +       NULL,
28322 +       NULL,
28323 +       NULL,
28324 +       NULL,
28325 +       NULL,
28326 +       NULL,
28327 +       NULL,
28328 +       NULL,
28329 +};
28330 +
28331 +static const char * funcs_d2[] = {
28332 +       "VD[8]      ",
28333 +       "VD[9]      ",
28334 +       "VD[10]     ",
28335 +       "VD[11]     ",
28336 +       "VD[12]     ",
28337 +       "VD[13]     ",
28338 +       "VD[14]     ",
28339 +       "VD[15]     ",
28340 +       "VD[16]     ",
28341 +       "VD[17]     ",
28342 +       "VD[18]     ",
28343 +       "VD[19]     ",
28344 +       "VD[20]     ",
28345 +       "VD[21]     ",
28346 +       "VD[22]     ",
28347 +       "VD[23]     ",
28348 +};
28349 +static const char * funcs_d3[] = {
28350 +       "nSPICS1    ",
28351 +       "SPICLK1    ",
28352 +       NULL,
28353 +       NULL,
28354 +       NULL,
28355 +       NULL,
28356 +       NULL,
28357 +       NULL,
28358 +       "SPIMISO1   ",
28359 +       "SPIMOSI1   ",
28360 +       "SPICLK1    ",
28361 +       NULL,
28362 +       NULL,
28363 +       NULL,
28364 +       "nSS1       ",
28365 +       "nSS0       ",
28366 +};
28367 +
28368 +static const char * funcs_e2[] = {
28369 +       "I2SLRCK    ",
28370 +       "I2SSCLK    ",
28371 +       "CDCLK      ",
28372 +       "I2SDI      ",
28373 +       "I2SDO      ",
28374 +       "SDCLK      ",
28375 +       "SDCMD      ",
28376 +       "SDDAT0     ",
28377 +       "SDDAT1     ",
28378 +       "SDDAT2     ",
28379 +       "SDDAT3     ",
28380 +       "SPIMISO0   ",
28381 +       "SPIMOSI0   ",
28382 +       "SPICLK0    ",
28383 +       "IICSCL     ",
28384 +       "IICSDA     ",
28385 +};
28386 +static const char * funcs_e3[] = {
28387 +       NULL,
28388 +       NULL,
28389 +       NULL,
28390 +       NULL,
28391 +       NULL,
28392 +       NULL,
28393 +       NULL,
28394 +       NULL,
28395 +       NULL,
28396 +       NULL,
28397 +       NULL,
28398 +       NULL,
28399 +       NULL,
28400 +       NULL,
28401 +       NULL,
28402 +       NULL,
28403 +};
28404 +
28405 +static const char * funcs_f2[] = {
28406 +       "EINT[0]    ",
28407 +       "EINT[1]    ",
28408 +       "EINT[2]    ",
28409 +       "EINT[3]    ",
28410 +       "EINT[4]    ",
28411 +       "EINT[5]    ",
28412 +       "EINT[6]    ",
28413 +       "EINT[7]    ",
28414 +};
28415 +static const char * funcs_f3[] = {
28416 +       NULL,
28417 +       NULL,
28418 +       NULL,
28419 +       NULL,
28420 +       NULL,
28421 +       NULL,
28422 +       NULL,
28423 +       NULL,
28424 +};
28425 +
28426 +
28427 +static const char * funcs_g2[] = {
28428 +       "EINT[8]    ",
28429 +       "EINT[9]    ",
28430 +       "EINT[10]   ",
28431 +       "EINT[11]   ",
28432 +       "EINT[12]   ",
28433 +       "EINT[13]   ",
28434 +       "EINT[14]   ",
28435 +       "EINT[15]   ",
28436 +       "EINT[16]   ",
28437 +       "EINT[17]   ",
28438 +       "EINT[18]   ",
28439 +       "EINT[19]   ",
28440 +       "EINT[20]   ",
28441 +       "EINT[21]   ",
28442 +       "EINT[22]   ",
28443 +       "EINT[23]   ",
28444 +};
28445 +static const char * funcs_g3[] = {
28446 +       NULL,
28447 +       NULL,
28448 +       "nSS0       ",
28449 +       "nSS1       ",
28450 +       "LCD_PWRDN  ",
28451 +       "SPIMISO1   ",
28452 +       "SPIMOSI1   ",
28453 +       "SPICLK1    ",
28454 +       NULL,
28455 +       "nRTS1      ",
28456 +       "nCTS1      ",
28457 +       "TCLK[1]    ",
28458 +       "nSPICS0    ",
28459 +       NULL,
28460 +       NULL,
28461 +       NULL,
28462 +};
28463 +
28464 +static const char * funcs_h2[] = {
28465 +       "nCTS0      ",
28466 +       "nRTS0      ",
28467 +       "TXD[0]     ",
28468 +       "RXD[0]     ",
28469 +       "TXD[1]     ",
28470 +       "RXD[1]     ",
28471 +       "TXD[2]     ",
28472 +       "RXD[2]     ",
28473 +       "UEXTCLK    ",
28474 +       "CLKOUT0    ",
28475 +       "CLKOUT1    ",
28476 +};
28477 +static const char * funcs_h3[] = {
28478 +       NULL,
28479 +       NULL,
28480 +       NULL,
28481 +       NULL,
28482 +       NULL,
28483 +       NULL,
28484 +       "nRTS1      ",
28485 +       "nCTS1      ",
28486 +       NULL,
28487 +       "nSPICS0    ",
28488 +       NULL,
28489 +};
28490 +
28491 +static const char * funcs_j2[] = {
28492 +       "CAMDATA[0] ",
28493 +       "CAMDATA[1] ",
28494 +       "CAMDATA[2] ",
28495 +       "CAMDATA[3] ",
28496 +       "CAMDATA[4] ",
28497 +       "CAMDATA[5] ",
28498 +       "CAMDATA[6] ",
28499 +       "CAMDATA[7] ",
28500 +       "CAMPCLK    ",
28501 +       "CAMVSYNC   ",
28502 +       "CAMHREF    ",
28503 +       "CAMCLKOUT  ",
28504 +       "CAMRESET   ",
28505 +};
28506 +static const char * funcs_j3[] = {
28507 +       NULL,
28508 +       NULL,
28509 +       NULL,
28510 +       NULL,
28511 +       NULL,
28512 +       NULL,
28513 +       NULL,
28514 +       NULL,
28515 +       NULL,
28516 +       NULL,
28517 +       NULL,
28518 +       NULL,
28519 +       NULL,
28520 +};
28521 +
28522 +/* used to dump GPIO states at suspend */
28523 +void s3c24xx_dump_gpio_states(void)
28524 +{
28525 +       pretty_dump_a(__raw_readl(S3C2410_GPACON),
28526 +                     __raw_readl(S3C2410_GPADAT),
28527 +                     funcs_a, "GPA", 25);
28528 +       pretty_dump(__raw_readl(S3C2410_GPBCON),
28529 +                   __raw_readl(S3C2410_GPBDAT),
28530 +                   __raw_readl(S3C2410_GPBUP),
28531 +                   funcs_b2, funcs_b3, "GPB", 11);
28532 +       pretty_dump(__raw_readl(S3C2410_GPCCON),
28533 +                   __raw_readl(S3C2410_GPCDAT),
28534 +                   __raw_readl(S3C2410_GPCUP),
28535 +                   funcs_c2, funcs_c3, "GPC", 16);
28536 +       pretty_dump(__raw_readl(S3C2410_GPDCON),
28537 +                   __raw_readl(S3C2410_GPDDAT),
28538 +                   __raw_readl(S3C2410_GPDUP),
28539 +                   funcs_d2, funcs_d3, "GPD", 16);
28540 +       pretty_dump(__raw_readl(S3C2410_GPECON),
28541 +                   __raw_readl(S3C2410_GPEDAT),
28542 +                   __raw_readl(S3C2410_GPEUP),
28543 +                   funcs_e2, funcs_e3, "GPE", 16);
28544 +       pretty_dump(__raw_readl(S3C2410_GPFCON),
28545 +                   __raw_readl(S3C2410_GPFDAT),
28546 +                   __raw_readl(S3C2410_GPFUP),
28547 +                   funcs_f2, funcs_f3, "GPF", 8);
28548 +       pretty_dump(__raw_readl(S3C2410_GPGCON),
28549 +                   __raw_readl(S3C2410_GPGDAT),
28550 +                   __raw_readl(S3C2410_GPGUP),
28551 +                   funcs_g2, funcs_g3, "GPG", 16);
28552 +       pretty_dump(__raw_readl(S3C2410_GPHCON),
28553 +                   __raw_readl(S3C2410_GPHDAT),
28554 +                   __raw_readl(S3C2410_GPHUP),
28555 +                   funcs_h2, funcs_h3, "GPH", 11);
28556 +       pretty_dump(__raw_readl(S3C2440_GPJCON),
28557 +                   __raw_readl(S3C2440_GPJDAT),
28558 +                   __raw_readl(S3C2440_GPJUP),
28559 +                   funcs_j2, funcs_j3, "GPJ", 13);
28560 +
28561 +}
28562 +EXPORT_SYMBOL(s3c24xx_dump_gpio_states);
28563 +
28564 --- a/arch/arm/plat-s3c24xx/gpiolib.c
28565 +++ b/arch/arm/plat-s3c24xx/gpiolib.c
28566 @@ -19,104 +19,13 @@
28567  #include <linux/io.h>
28568  #include <linux/gpio.h>
28569
28570 +#include <plat/gpio-core.h>
28571  #include <mach/hardware.h>
28572  #include <asm/irq.h>
28573 +#include <plat/pm.h>
28574
28575  #include <mach/regs-gpio.h>
28576
28577 -struct s3c24xx_gpio_chip {
28578 -       struct gpio_chip        chip;
28579 -       void __iomem            *base;
28580 -};
28581 -
28582 -static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
28583 -{
28584 -       return container_of(gpc, struct s3c24xx_gpio_chip, chip);
28585 -}
28586 -
28587 -/* these routines are exported for use by other parts of the platform
28588 - * and system support, but are not intended to be used directly by the
28589 - * drivers themsevles.
28590 - */
28591 -
28592 -static int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
28593 -{
28594 -       struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
28595 -       void __iomem *base = ourchip->base;
28596 -       unsigned long flags;
28597 -       unsigned long con;
28598 -
28599 -       local_irq_save(flags);
28600 -
28601 -       con = __raw_readl(base + 0x00);
28602 -       con &= ~(3 << (offset * 2));
28603 -       con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
28604 -
28605 -       __raw_writel(con, base + 0x00);
28606 -
28607 -       local_irq_restore(flags);
28608 -       return 0;
28609 -}
28610 -
28611 -static int s3c24xx_gpiolib_output(struct gpio_chip *chip,
28612 -                                 unsigned offset, int value)
28613 -{
28614 -       struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
28615 -       void __iomem *base = ourchip->base;
28616 -       unsigned long flags;
28617 -       unsigned long dat;
28618 -       unsigned long con;
28619 -
28620 -       local_irq_save(flags);
28621 -
28622 -       dat = __raw_readl(base + 0x04);
28623 -       dat &= ~(1 << offset);
28624 -       if (value)
28625 -               dat |= 1 << offset;
28626 -       __raw_writel(dat, base + 0x04);
28627 -
28628 -       con = __raw_readl(base + 0x00);
28629 -       con &= ~(3 << (offset * 2));
28630 -       con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
28631 -
28632 -       __raw_writel(con, base + 0x00);
28633 -       __raw_writel(dat, base + 0x04);
28634 -
28635 -       local_irq_restore(flags);
28636 -       return 0;
28637 -}
28638 -
28639 -static void s3c24xx_gpiolib_set(struct gpio_chip *chip,
28640 -                               unsigned offset, int value)
28641 -{
28642 -       struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
28643 -       void __iomem *base = ourchip->base;
28644 -       unsigned long flags;
28645 -       unsigned long dat;
28646 -
28647 -       local_irq_save(flags);
28648 -
28649 -       dat = __raw_readl(base + 0x04);
28650 -       dat &= ~(1 << offset);
28651 -       if (value)
28652 -               dat |= 1 << offset;
28653 -       __raw_writel(dat, base + 0x04);
28654 -
28655 -       local_irq_restore(flags);
28656 -}
28657 -
28658 -static int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
28659 -{
28660 -       struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
28661 -       unsigned long val;
28662 -
28663 -       val = __raw_readl(ourchip->base + 0x04);
28664 -       val >>= offset;
28665 -       val &= 1;
28666 -
28667 -       return val;
28668 -}
28669 -
28670  static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
28671  {
28672         return -EINVAL;
28673 @@ -125,7 +34,7 @@ static int s3c24xx_gpiolib_banka_input(s
28674  static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
28675                                         unsigned offset, int value)
28676  {
28677 -       struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
28678 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
28679         void __iomem *base = ourchip->base;
28680         unsigned long flags;
28681         unsigned long dat;
28682 @@ -151,9 +60,10 @@ static int s3c24xx_gpiolib_banka_output(
28683         return 0;
28684  }
28685
28686 -static struct s3c24xx_gpio_chip gpios[] = {
28687 +struct s3c_gpio_chip s3c24xx_gpios[] = {
28688         [0] = {
28689                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPA0),
28690 +               .pm     = __gpio_pm(&s3c_gpio_pm_1bit),
28691                 .chip   = {
28692                         .base                   = S3C2410_GPA0,
28693                         .owner                  = THIS_MODULE,
28694 @@ -161,97 +71,87 @@ static struct s3c24xx_gpio_chip gpios[]
28695                         .ngpio                  = 24,
28696                         .direction_input        = s3c24xx_gpiolib_banka_input,
28697                         .direction_output       = s3c24xx_gpiolib_banka_output,
28698 -                       .set                    = s3c24xx_gpiolib_set,
28699 -                       .get                    = s3c24xx_gpiolib_get,
28700                 },
28701         },
28702         [1] = {
28703                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPB0),
28704 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
28705                 .chip   = {
28706                         .base                   = S3C2410_GPB0,
28707                         .owner                  = THIS_MODULE,
28708                         .label                  = "GPIOB",
28709                         .ngpio                  = 16,
28710 -                       .direction_input        = s3c24xx_gpiolib_input,
28711 -                       .direction_output       = s3c24xx_gpiolib_output,
28712 -                       .set                    = s3c24xx_gpiolib_set,
28713 -                       .get                    = s3c24xx_gpiolib_get,
28714                 },
28715         },
28716         [2] = {
28717                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPC0),
28718 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
28719                 .chip   = {
28720                         .base                   = S3C2410_GPC0,
28721                         .owner                  = THIS_MODULE,
28722                         .label                  = "GPIOC",
28723                         .ngpio                  = 16,
28724 -                       .direction_input        = s3c24xx_gpiolib_input,
28725 -                       .direction_output       = s3c24xx_gpiolib_output,
28726 -                       .set                    = s3c24xx_gpiolib_set,
28727 -                       .get                    = s3c24xx_gpiolib_get,
28728                 },
28729         },
28730         [3] = {
28731                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPD0),
28732 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
28733                 .chip   = {
28734                         .base                   = S3C2410_GPD0,
28735                         .owner                  = THIS_MODULE,
28736                         .label                  = "GPIOD",
28737                         .ngpio                  = 16,
28738 -                       .direction_input        = s3c24xx_gpiolib_input,
28739 -                       .direction_output       = s3c24xx_gpiolib_output,
28740 -                       .set                    = s3c24xx_gpiolib_set,
28741 -                       .get                    = s3c24xx_gpiolib_get,
28742                 },
28743         },
28744         [4] = {
28745                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPE0),
28746 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
28747                 .chip   = {
28748                         .base                   = S3C2410_GPE0,
28749                         .label                  = "GPIOE",
28750                         .owner                  = THIS_MODULE,
28751                         .ngpio                  = 16,
28752 -                       .direction_input        = s3c24xx_gpiolib_input,
28753 -                       .direction_output       = s3c24xx_gpiolib_output,
28754 -                       .set                    = s3c24xx_gpiolib_set,
28755 -                       .get                    = s3c24xx_gpiolib_get,
28756                 },
28757         },
28758         [5] = {
28759                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPF0),
28760 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
28761                 .chip   = {
28762                         .base                   = S3C2410_GPF0,
28763                         .owner                  = THIS_MODULE,
28764                         .label                  = "GPIOF",
28765                         .ngpio                  = 8,
28766 -                       .direction_input        = s3c24xx_gpiolib_input,
28767 -                       .direction_output       = s3c24xx_gpiolib_output,
28768 -                       .set                    = s3c24xx_gpiolib_set,
28769 -                       .get                    = s3c24xx_gpiolib_get,
28770                 },
28771         },
28772         [6] = {
28773                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPG0),
28774 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
28775                 .chip   = {
28776                         .base                   = S3C2410_GPG0,
28777                         .owner                  = THIS_MODULE,
28778                         .label                  = "GPIOG",
28779 -                       .ngpio                  = 10,
28780 -                       .direction_input        = s3c24xx_gpiolib_input,
28781 -                       .direction_output       = s3c24xx_gpiolib_output,
28782 -                       .set                    = s3c24xx_gpiolib_set,
28783 -                       .get                    = s3c24xx_gpiolib_get,
28784 +                       .ngpio                  = 16,
28785 +               },
28786 +       },
28787 +       [7] = {
28788 +               .base   = S3C24XX_GPIO_BASE(S3C2410_GPH0),
28789 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
28790 +               .chip   = {
28791 +                       .base                   = S3C2410_GPH0,
28792 +                       .owner                  = THIS_MODULE,
28793 +                       .label                  = "GPIOH",
28794 +                       .ngpio                  = 11,
28795                 },
28796         },
28797  };
28798
28799  static __init int s3c24xx_gpiolib_init(void)
28800  {
28801 -       struct s3c24xx_gpio_chip *chip = gpios;
28802 +       struct s3c_gpio_chip *chip = s3c24xx_gpios;
28803         int gpn;
28804
28805 -       for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++)
28806 -               gpiochip_add(&chip->chip);
28807 +       for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
28808 +               s3c_gpiolib_add(chip);
28809
28810         return 0;
28811  }
28812 --- /dev/null
28813 +++ b/arch/arm/plat-s3c24xx/gta02_pm_wlan.c
28814 @@ -0,0 +1,161 @@
28815 +/*
28816 + * GTA02 WLAN power management
28817 + *
28818 + * (C) 2008 by Openmoko Inc.
28819 + * Author: Andy Green <andy@openmoko.com>
28820 + * All rights reserved.
28821 + *
28822 + * This program is free software; you can redistribute it and/or modify
28823 + * it under the terms of the GNU General Public License version 2 as
28824 + * published by the Free Software Foundation
28825 + *
28826 + */
28827 +
28828 +#include <linux/module.h>
28829 +#include <linux/init.h>
28830 +#include <linux/kernel.h>
28831 +#include <linux/mutex.h>
28832 +#include <linux/platform_device.h>
28833 +
28834 +#include <mach/hardware.h>
28835 +#include <asm/mach-types.h>
28836 +#include <asm/plat-s3c24xx/neo1973.h>
28837 +
28838 +#include <mach/gta02.h>
28839 +#include <mach/gta02-pm-wlan.h>
28840 +#include <mach/regs-gpio.h>
28841 +#include <mach/regs-gpioj.h>
28842 +
28843 +#include <linux/delay.h>
28844 +
28845 +
28846 +static void __gta02_wlan_power(int on)
28847 +{
28848 +       if (!on) {
28849 +               s3c2410_gpio_setpin(GTA02_CHIP_PWD, 1);
28850 +               s3c2410_gpio_setpin(GTA02_GPIO_nWLAN_RESET, 0);
28851 +               return;
28852 +       }
28853 +
28854 +       /* power up sequencing */
28855 +
28856 +       s3c2410_gpio_setpin(GTA02_CHIP_PWD, 1);
28857 +       s3c2410_gpio_setpin(GTA02_GPIO_nWLAN_RESET, 0);
28858 +       msleep(100);
28859 +       s3c2410_gpio_setpin(GTA02_CHIP_PWD, 0);
28860 +       msleep(100);
28861 +       s3c2410_gpio_setpin(GTA02_GPIO_nWLAN_RESET, 1);
28862 +}
28863 +
28864 +void gta02_wlan_power(int on)
28865 +{
28866 +       static DEFINE_MUTEX(lock);
28867 +       static int is_on = -1; /* initial state is unknown */
28868 +
28869 +       on = !!on; /* normalize */
28870 +       mutex_lock(&lock);
28871 +       if (on != is_on)
28872 +               __gta02_wlan_power(on);
28873 +       is_on = on;
28874 +       mutex_unlock(&lock);
28875 +}
28876 +
28877 +static ssize_t gta02_wlan_read(struct device *dev,
28878 +                                      struct device_attribute *attr, char *buf)
28879 +{
28880 +       if (s3c2410_gpio_getpin(GTA02_CHIP_PWD))
28881 +               return strlcpy(buf, "0\n", 3);
28882 +
28883 +       return strlcpy(buf, "1\n", 3);
28884 +}
28885 +
28886 +static ssize_t gta02_wlan_write(struct device *dev,
28887 +                  struct device_attribute *attr, const char *buf, size_t count)
28888 +{
28889 +       unsigned long on = simple_strtoul(buf, NULL, 10) & 1;
28890 +
28891 +       gta02_wlan_power(on);
28892 +       return count;
28893 +}
28894 +
28895 +static DEVICE_ATTR(power_on, 0644, gta02_wlan_read, gta02_wlan_write);
28896 +
28897 +#ifdef CONFIG_PM
28898 +static int gta02_wlan_suspend(struct platform_device *pdev, pm_message_t state)
28899 +{
28900 +       dev_dbg(&pdev->dev, "suspending\n");
28901 +
28902 +       return 0;
28903 +}
28904 +
28905 +static int gta02_wlan_resume(struct platform_device *pdev)
28906 +{
28907 +       dev_dbg(&pdev->dev, "resuming\n");
28908 +
28909 +       return 0;
28910 +}
28911 +#else
28912 +#define gta02_wlan_suspend     NULL
28913 +#define gta02_wlan_resume              NULL
28914 +#endif
28915 +
28916 +static struct attribute *gta02_wlan_sysfs_entries[] = {
28917 +       &dev_attr_power_on.attr,
28918 +       NULL
28919 +};
28920 +
28921 +static struct attribute_group gta02_wlan_attr_group = {
28922 +       .name   = NULL,
28923 +       .attrs  = gta02_wlan_sysfs_entries,
28924 +};
28925 +
28926 +static int __init gta02_wlan_probe(struct platform_device *pdev)
28927 +{
28928 +       /* default-on for now */
28929 +       const int default_state = 1;
28930 +
28931 +       if (!machine_is_neo1973_gta02())
28932 +               return -EINVAL;
28933 +
28934 +       dev_info(&pdev->dev, "starting\n");
28935 +
28936 +       s3c2410_gpio_cfgpin(GTA02_CHIP_PWD, S3C2410_GPIO_OUTPUT);
28937 +       s3c2410_gpio_cfgpin(GTA02_GPIO_nWLAN_RESET, S3C2410_GPIO_OUTPUT);
28938 +       gta02_wlan_power(default_state);
28939 +
28940 +       return sysfs_create_group(&pdev->dev.kobj, &gta02_wlan_attr_group);
28941 +}
28942 +
28943 +static int gta02_wlan_remove(struct platform_device *pdev)
28944 +{
28945 +       sysfs_remove_group(&pdev->dev.kobj, &gta02_wlan_attr_group);
28946 +
28947 +       return 0;
28948 +}
28949 +
28950 +static struct platform_driver gta02_wlan_driver = {
28951 +       .probe          = gta02_wlan_probe,
28952 +       .remove         = gta02_wlan_remove,
28953 +       .suspend        = gta02_wlan_suspend,
28954 +       .resume         = gta02_wlan_resume,
28955 +       .driver         = {
28956 +               .name           = "gta02-pm-wlan",
28957 +       },
28958 +};
28959 +
28960 +static int __devinit gta02_wlan_init(void)
28961 +{
28962 +       return platform_driver_register(&gta02_wlan_driver);
28963 +}
28964 +
28965 +static void gta02_wlan_exit(void)
28966 +{
28967 +       platform_driver_unregister(&gta02_wlan_driver);
28968 +}
28969 +
28970 +module_init(gta02_wlan_init);
28971 +module_exit(gta02_wlan_exit);
28972 +
28973 +MODULE_LICENSE("GPL");
28974 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
28975 +MODULE_DESCRIPTION("Openmoko GTA02 WLAN power management");
28976 --- /dev/null
28977 +++ b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
28978 @@ -0,0 +1,55 @@
28979 +/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
28980 + *
28981 + * Copyright 2008 Simtec Electronics
28982 + *      Ben Dooks <ben@simtec.co.uk>
28983 + *      http://armlinux.simtec.co.uk/
28984 + *
28985 + * S3C24xx - pwm clock and timer support
28986 + */
28987 +
28988 +/**
28989 + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
28990 + * @cfg: The timer TCFG1 register bits shifted down to 0.
28991 + *
28992 + * Return true if the given configuration from TCFG1 is a TCLK instead
28993 + * any of the TDIV clocks.
28994 + */
28995 +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
28996 +{
28997 +       return tcfg == S3C2410_TCFG1_MUX_TCLK;
28998 +}
28999 +
29000 +/**
29001 + * tcfg_to_divisor() - convert tcfg1 setting to a divisor
29002 + * @tcfg1: The tcfg1 setting, shifted down.
29003 + *
29004 + * Get the divisor value for the given tcfg1 setting. We assume the
29005 + * caller has already checked to see if this is not a TCLK source.
29006 + */
29007 +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
29008 +{
29009 +       return 1 << (1 + tcfg1);
29010 +}
29011 +
29012 +/**
29013 + * pwm_tdiv_has_div1() - does the tdiv setting have a /1
29014 + *
29015 + * Return true if we have a /1 in the tdiv setting.
29016 + */
29017 +static inline unsigned int pwm_tdiv_has_div1(void)
29018 +{
29019 +       return 0;
29020 +}
29021 +
29022 +/**
29023 + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
29024 + * @div: The divisor to calculate the bit information for.
29025 + *
29026 + * Turn a divisor into the necessary bit field for TCFG1.
29027 + */
29028 +static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
29029 +{
29030 +       return ilog2(div) - 1;
29031 +}
29032 +
29033 +#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
29034 --- a/arch/arm/plat-s3c24xx/include/plat/clock.h
29035 +++ /dev/null
29036 @@ -1,64 +0,0 @@
29037 -/* linux/include/asm-arm/plat-s3c24xx/clock.h
29038 - * linux/arch/arm/mach-s3c2410/clock.h
29039 - *
29040 - * Copyright (c) 2004-2005 Simtec Electronics
29041 - *     http://www.simtec.co.uk/products/SWLINUX/
29042 - *     Written by Ben Dooks, <ben@simtec.co.uk>
29043 - *
29044 - * This program is free software; you can redistribute it and/or modify
29045 - * it under the terms of the GNU General Public License version 2 as
29046 - * published by the Free Software Foundation.
29047 -*/
29048 -
29049 -struct clk {
29050 -       struct list_head      list;
29051 -       struct module        *owner;
29052 -       struct clk           *parent;
29053 -       const char           *name;
29054 -       int                   id;
29055 -       int                   usage;
29056 -       unsigned long         rate;
29057 -       unsigned long         ctrlbit;
29058 -
29059 -       int                 (*enable)(struct clk *, int enable);
29060 -       int                 (*set_rate)(struct clk *c, unsigned long rate);
29061 -       unsigned long       (*get_rate)(struct clk *c);
29062 -       unsigned long       (*round_rate)(struct clk *c, unsigned long rate);
29063 -       int                 (*set_parent)(struct clk *c, struct clk *parent);
29064 -};
29065 -
29066 -/* other clocks which may be registered by board support */
29067 -
29068 -extern struct clk s3c24xx_dclk0;
29069 -extern struct clk s3c24xx_dclk1;
29070 -extern struct clk s3c24xx_clkout0;
29071 -extern struct clk s3c24xx_clkout1;
29072 -extern struct clk s3c24xx_uclk;
29073 -
29074 -extern struct clk clk_usb_bus;
29075 -
29076 -/* core clock support */
29077 -
29078 -extern struct clk clk_f;
29079 -extern struct clk clk_h;
29080 -extern struct clk clk_p;
29081 -extern struct clk clk_mpll;
29082 -extern struct clk clk_upll;
29083 -extern struct clk clk_xtal;
29084 -
29085 -/* exports for arch/arm/mach-s3c2410
29086 - *
29087 - * Please DO NOT use these outside of arch/arm/mach-s3c2410
29088 -*/
29089 -
29090 -extern struct mutex clocks_mutex;
29091 -
29092 -extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
29093 -
29094 -extern int s3c24xx_register_clock(struct clk *clk);
29095 -extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
29096 -
29097 -extern int s3c24xx_setup_clocks(unsigned long xtal,
29098 -                               unsigned long fclk,
29099 -                               unsigned long hclk,
29100 -                               unsigned long pclk);
29101 --- a/arch/arm/plat-s3c24xx/include/plat/cpu.h
29102 +++ /dev/null
29103 @@ -1,54 +0,0 @@
29104 -/* linux/include/asm-arm/plat-s3c24xx/cpu.h
29105 - *
29106 - * Copyright (c) 2004-2005 Simtec Electronics
29107 - *     Ben Dooks <ben@simtec.co.uk>
29108 - *
29109 - * Header file for S3C24XX CPU support
29110 - *
29111 - * This program is free software; you can redistribute it and/or modify
29112 - * it under the terms of the GNU General Public License version 2 as
29113 - * published by the Free Software Foundation.
29114 -*/
29115 -
29116 -/* todo - fix when rmk changes iodescs to use `void __iomem *` */
29117 -
29118 -#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
29119 -
29120 -#ifndef MHZ
29121 -#define MHZ (1000*1000)
29122 -#endif
29123 -
29124 -#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
29125 -
29126 -/* forward declaration */
29127 -struct s3c24xx_uart_resources;
29128 -struct platform_device;
29129 -struct s3c2410_uartcfg;
29130 -struct map_desc;
29131 -
29132 -/* core initialisation functions */
29133 -
29134 -extern void s3c24xx_init_irq(void);
29135 -
29136 -extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
29137 -
29138 -extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
29139 -
29140 -extern void s3c24xx_init_clocks(int xtal);
29141 -
29142 -extern void s3c24xx_init_uartdevs(char *name,
29143 -                                 struct s3c24xx_uart_resources *res,
29144 -                                 struct s3c2410_uartcfg *cfg, int no);
29145 -
29146 -/* timer for 2410/2440 */
29147 -
29148 -struct sys_timer;
29149 -extern struct sys_timer s3c24xx_timer;
29150 -
29151 -/* system device classes */
29152 -
29153 -extern struct sysdev_class s3c2410_sysclass;
29154 -extern struct sysdev_class s3c2412_sysclass;
29155 -extern struct sysdev_class s3c2440_sysclass;
29156 -extern struct sysdev_class s3c2442_sysclass;
29157 -extern struct sysdev_class s3c2443_sysclass;
29158 --- a/arch/arm/plat-s3c24xx/include/plat/devs.h
29159 +++ /dev/null
29160 @@ -1,49 +0,0 @@
29161 -/* linux/include/asm-arm/plat-s3c24xx/devs.h
29162 - *
29163 - * Copyright (c) 2004 Simtec Electronics
29164 - * Ben Dooks <ben@simtec.co.uk>
29165 - *
29166 - * Header file for s3c2410 standard platform devices
29167 - *
29168 - * This program is free software; you can redistribute it and/or modify
29169 - * it under the terms of the GNU General Public License version 2 as
29170 - * published by the Free Software Foundation.
29171 -*/
29172 -#include <linux/platform_device.h>
29173 -
29174 -struct s3c24xx_uart_resources {
29175 -       struct resource         *resources;
29176 -       unsigned long            nr_resources;
29177 -};
29178 -
29179 -extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
29180 -
29181 -extern struct platform_device *s3c24xx_uart_devs[];
29182 -extern struct platform_device *s3c24xx_uart_src[];
29183 -
29184 -extern struct platform_device s3c_device_timer[];
29185 -
29186 -extern struct platform_device s3c_device_usb;
29187 -extern struct platform_device s3c_device_lcd;
29188 -extern struct platform_device s3c_device_wdt;
29189 -extern struct platform_device s3c_device_i2c;
29190 -extern struct platform_device s3c_device_iis;
29191 -extern struct platform_device s3c_device_rtc;
29192 -extern struct platform_device s3c_device_adc;
29193 -extern struct platform_device s3c_device_sdi;
29194 -extern struct platform_device s3c_device_hsmmc;
29195 -
29196 -extern struct platform_device s3c_device_spi0;
29197 -extern struct platform_device s3c_device_spi1;
29198 -
29199 -extern struct platform_device s3c_device_nand;
29200 -
29201 -extern struct platform_device s3c_device_usbgadget;
29202 -
29203 -/* s3c2440 specific devices */
29204 -
29205 -#ifdef CONFIG_CPU_S3C2440
29206 -
29207 -extern struct platform_device s3c_device_camif;
29208 -
29209 -#endif
29210 --- a/arch/arm/plat-s3c24xx/include/plat/irq.h
29211 +++ b/arch/arm/plat-s3c24xx/include/plat/irq.h
29212 @@ -10,6 +10,12 @@
29213   * published by the Free Software Foundation.
29214  */
29215
29216 +#include <linux/io.h>
29217 +
29218 +#include <mach/hardware.h>
29219 +#include <mach/regs-irq.h>
29220 +#include <mach/regs-gpio.h>
29221 +
29222  #define irqdbf(x...)
29223  #define irqdbf2(x...)
29224
29225 @@ -25,8 +31,15 @@ s3c_irqsub_mask(unsigned int irqno, unsi
29226  {
29227         unsigned long mask;
29228         unsigned long submask;
29229 +#ifdef CONFIG_S3C2440_C_FIQ
29230 +       unsigned long flags;
29231 +#endif
29232
29233         submask = __raw_readl(S3C2410_INTSUBMSK);
29234 +#ifdef CONFIG_S3C2440_C_FIQ
29235 +       local_save_flags(flags);
29236 +       local_fiq_disable();
29237 +#endif
29238         mask = __raw_readl(S3C2410_INTMSK);
29239
29240         submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
29241 @@ -39,6 +52,9 @@ s3c_irqsub_mask(unsigned int irqno, unsi
29242
29243         /* write back masks */
29244         __raw_writel(submask, S3C2410_INTSUBMSK);
29245 +#ifdef CONFIG_S3C2440_C_FIQ
29246 +       local_irq_restore(flags);
29247 +#endif
29248
29249  }
29250
29251 @@ -47,8 +63,15 @@ s3c_irqsub_unmask(unsigned int irqno, un
29252  {
29253         unsigned long mask;
29254         unsigned long submask;
29255 +#ifdef CONFIG_S3C2440_C_FIQ
29256 +       unsigned long flags;
29257 +#endif
29258
29259         submask = __raw_readl(S3C2410_INTSUBMSK);
29260 +#ifdef CONFIG_S3C2440_C_FIQ
29261 +       local_save_flags(flags);
29262 +       local_fiq_disable();
29263 +#endif
29264         mask = __raw_readl(S3C2410_INTMSK);
29265
29266         submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
29267 @@ -57,6 +80,9 @@ s3c_irqsub_unmask(unsigned int irqno, un
29268         /* write back masks */
29269         __raw_writel(submask, S3C2410_INTSUBMSK);
29270         __raw_writel(mask, S3C2410_INTMSK);
29271 +#ifdef CONFIG_S3C2440_C_FIQ
29272 +       local_irq_restore(flags);
29273 +#endif
29274  }
29275
29276
29277 --- /dev/null
29278 +++ b/arch/arm/plat-s3c24xx/include/plat/map.h
29279 @@ -0,0 +1,101 @@
29280 +/* linux/include/asm-arm/plat-s3c24xx/map.h
29281 + *
29282 + * Copyright (c) 2008 Simtec Electronics
29283 + *     Ben Dooks <ben@simtec.co.uk>
29284 + *
29285 + * S3C24XX - Memory map definitions
29286 + *
29287 + * This program is free software; you can redistribute it and/or modify
29288 + * it under the terms of the GNU General Public License version 2 as
29289 + * published by the Free Software Foundation.
29290 +*/
29291 +
29292 +#ifndef __ASM_PLAT_S3C24XX_MAP_H
29293 +#define __ASM_PLAT_S3C24XX_MAP_H
29294 +
29295 +/* interrupt controller is the first thing we put in, to make
29296 + * the assembly code for the irq detection easier
29297 + */
29298 +#define S3C24XX_VA_IRQ    S3C_VA_IRQ
29299 +#define S3C2410_PA_IRQ    (0x4A000000)
29300 +#define S3C24XX_SZ_IRQ    SZ_1M
29301 +
29302 +/* memory controller registers */
29303 +#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
29304 +#define S3C2410_PA_MEMCTRL (0x48000000)
29305 +#define S3C24XX_SZ_MEMCTRL SZ_1M
29306 +
29307 +/* UARTs */
29308 +#define S3C24XX_VA_UART           S3C_VA_UART
29309 +#define S3C2410_PA_UART           (0x50000000)
29310 +#define S3C24XX_SZ_UART           SZ_1M
29311 +#define S3C_UART_OFFSET           (0x4000)
29312 +
29313 +#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
29314 +
29315 +/* Timers */
29316 +#define S3C24XX_VA_TIMER   S3C_VA_TIMER
29317 +#define S3C2410_PA_TIMER   (0x51000000)
29318 +#define S3C24XX_SZ_TIMER   SZ_1M
29319 +
29320 +/* Clock and Power management */
29321 +#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
29322 +#define S3C24XX_SZ_CLKPWR  SZ_1M
29323 +
29324 +/* USB Device port */
29325 +#define S3C2410_PA_USBDEV  (0x52000000)
29326 +#define S3C24XX_SZ_USBDEV  SZ_1M
29327 +
29328 +/* Watchdog */
29329 +#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
29330 +#define S3C2410_PA_WATCHDOG (0x53000000)
29331 +#define S3C24XX_SZ_WATCHDOG SZ_1M
29332 +
29333 +/* Standard size definitions for peripheral blocks. */
29334 +
29335 +#define S3C24XX_SZ_IIS         SZ_1M
29336 +#define S3C24XX_SZ_ADC         SZ_1M
29337 +#define S3C24XX_SZ_SPI         SZ_1M
29338 +#define S3C24XX_SZ_SDI         SZ_1M
29339 +#define S3C24XX_SZ_NAND                SZ_1M
29340 +#define S3C24XX_SZ_USBHOST     SZ_1M
29341 +
29342 +/* GPIO ports */
29343 +
29344 +/* the calculation for the VA of this must ensure that
29345 + * it is the same distance apart from the UART in the
29346 + * phsyical address space, as the initial mapping for the IO
29347 + * is done as a 1:1 maping. This puts it (currently) at
29348 + * 0xFA800000, which is not in the way of any current mapping
29349 + * by the base system.
29350 +*/
29351 +
29352 +#define S3C2410_PA_GPIO           (0x56000000)
29353 +#define S3C24XX_VA_GPIO           ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
29354 +#define S3C24XX_SZ_GPIO           SZ_1M
29355 +
29356 +
29357 +/* ISA style IO, for each machine to sort out mappings for, if it
29358 + * implements it. We reserve two 16M regions for ISA.
29359 + */
29360 +
29361 +#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
29362 +#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
29363 +
29364 +/* deal with the registers that move under the 2412/2413 */
29365 +
29366 +#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
29367 +#ifndef __ASSEMBLY__
29368 +extern void __iomem *s3c24xx_va_gpio2;
29369 +#endif
29370 +#ifdef CONFIG_CPU_S3C2412_ONLY
29371 +#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
29372 +#else
29373 +#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
29374 +#endif
29375 +#else
29376 +#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
29377 +#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
29378 +#endif
29379 +
29380 +#endif /* __ASM_PLAT_S3C24XX_MAP_H */
29381 --- /dev/null
29382 +++ b/arch/arm/plat-s3c24xx/include/plat/mci.h
29383 @@ -0,0 +1,15 @@
29384 +#ifndef _ARCH_MCI_H
29385 +#define _ARCH_MCI_H
29386 +
29387 +struct s3c24xx_mci_pdata {
29388 +       unsigned int    wprotect_invert : 1;
29389 +       unsigned int    detect_invert : 1;   /* set => detect active high. */
29390 +
29391 +       unsigned int    gpio_detect;
29392 +       unsigned int    gpio_wprotect;
29393 +       unsigned long   ocr_avail;
29394 +       void            (*set_power)(unsigned char power_mode,
29395 +                                    unsigned short vdd);
29396 +};
29397 +
29398 +#endif /* _ARCH_NCI_H */
29399 --- /dev/null
29400 +++ b/arch/arm/plat-s3c24xx/include/plat/pll.h
29401 @@ -0,0 +1,37 @@
29402 +/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
29403 + *
29404 + * Copyright 2008 Simtec Electronics
29405 + *      Ben Dooks <ben@simtec.co.uk>
29406 + *      http://armlinux.simtec.co.uk/
29407 + *
29408 + * S3C24xx - common pll registers and code
29409 + */
29410 +
29411 +#define S3C24XX_PLLCON_MDIVSHIFT       12
29412 +#define S3C24XX_PLLCON_PDIVSHIFT       4
29413 +#define S3C24XX_PLLCON_SDIVSHIFT       0
29414 +#define S3C24XX_PLLCON_MDIVMASK                ((1<<(1+(19-12)))-1)
29415 +#define S3C24XX_PLLCON_PDIVMASK                ((1<<5)-1)
29416 +#define S3C24XX_PLLCON_SDIVMASK                3
29417 +
29418 +#include <asm/div64.h>
29419 +
29420 +static inline unsigned int
29421 +s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
29422 +{
29423 +       unsigned int mdiv, pdiv, sdiv;
29424 +       uint64_t fvco;
29425 +
29426 +       mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
29427 +       pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
29428 +       sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
29429 +
29430 +       mdiv &= S3C24XX_PLLCON_MDIVMASK;
29431 +       pdiv &= S3C24XX_PLLCON_PDIVMASK;
29432 +       sdiv &= S3C24XX_PLLCON_SDIVMASK;
29433 +
29434 +       fvco = (uint64_t)baseclk * (mdiv + 8);
29435 +       do_div(fvco, (pdiv + 2) << sdiv);
29436 +
29437 +       return (unsigned int)fvco;
29438 +}
29439 --- /dev/null
29440 +++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
29441 @@ -0,0 +1,64 @@
29442 +/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
29443 + *
29444 + * Copyright 2008 Simtec Electronics
29445 + *      Ben Dooks <ben@simtec.co.uk>
29446 + *      http://armlinux.simtec.co.uk/
29447 + *
29448 + * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
29449 + *
29450 + * This program is free software; you can redistribute it and/or modify
29451 + * it under the terms of the GNU General Public License version 2 as
29452 + * published by the Free Software Foundation.
29453 + */
29454 +
29455 +static inline void s3c_pm_debug_init_uart(void)
29456 +{
29457 +       unsigned long tmp = __raw_readl(S3C2410_CLKCON);
29458 +
29459 +       /* re-start uart clocks */
29460 +       tmp |= S3C2410_CLKCON_UART0;
29461 +       tmp |= S3C2410_CLKCON_UART1;
29462 +       tmp |= S3C2410_CLKCON_UART2;
29463 +
29464 +       __raw_writel(tmp, S3C2410_CLKCON);
29465 +       udelay(10);
29466 +}
29467 +
29468 +static inline void s3c_pm_arch_prepare_irqs(void)
29469 +{
29470 +       __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
29471 +       __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
29472 +
29473 +       /* ack any outstanding external interrupts before we go to sleep */
29474 +
29475 +       __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
29476 +       __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
29477 +       __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
29478 +
29479 +}
29480 +
29481 +static inline void s3c_pm_arch_stop_clocks(void)
29482 +{
29483 +       __raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */
29484 +}
29485 +
29486 +static void s3c_pm_show_resume_irqs(int start, unsigned long which,
29487 +                                   unsigned long mask);
29488 +
29489 +static inline void s3c_pm_arch_show_resume_irqs(void)
29490 +{
29491 +       S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
29492 +                 __raw_readl(S3C2410_SRCPND),
29493 +                 __raw_readl(S3C2410_EINTPEND));
29494 +
29495 +       s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
29496 +                               s3c_irqwake_intmask);
29497 +
29498 +       s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
29499 +                               s3c_irqwake_eintmask);
29500 +}
29501 +
29502 +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
29503 +                                          struct pm_uart_save *save)
29504 +{
29505 +}
29506 --- a/arch/arm/plat-s3c24xx/include/plat/pm.h
29507 +++ /dev/null
29508 @@ -1,73 +0,0 @@
29509 -/* linux/include/asm-arm/plat-s3c24xx/pm.h
29510 - *
29511 - * Copyright (c) 2004 Simtec Electronics
29512 - *     Written by Ben Dooks, <ben@simtec.co.uk>
29513 - *
29514 - * This program is free software; you can redistribute it and/or modify
29515 - * it under the terms of the GNU General Public License version 2 as
29516 - * published by the Free Software Foundation.
29517 -*/
29518 -
29519 -/* s3c2410_pm_init
29520 - *
29521 - * called from board at initialisation time to setup the power
29522 - * management
29523 -*/
29524 -
29525 -#ifdef CONFIG_PM
29526 -
29527 -extern __init int s3c2410_pm_init(void);
29528 -
29529 -#else
29530 -
29531 -static inline int s3c2410_pm_init(void)
29532 -{
29533 -       return 0;
29534 -}
29535 -#endif
29536 -
29537 -/* configuration for the IRQ mask over sleep */
29538 -extern unsigned long s3c_irqwake_intmask;
29539 -extern unsigned long s3c_irqwake_eintmask;
29540 -
29541 -/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
29542 -extern unsigned long s3c_irqwake_intallow;
29543 -extern unsigned long s3c_irqwake_eintallow;
29544 -
29545 -/* per-cpu sleep functions */
29546 -
29547 -extern void (*pm_cpu_prep)(void);
29548 -extern void (*pm_cpu_sleep)(void);
29549 -
29550 -/* Flags for PM Control */
29551 -
29552 -extern unsigned long s3c_pm_flags;
29553 -
29554 -/* from sleep.S */
29555 -
29556 -extern int  s3c2410_cpu_save(unsigned long *saveblk);
29557 -extern void s3c2410_cpu_suspend(void);
29558 -extern void s3c2410_cpu_resume(void);
29559 -
29560 -extern unsigned long s3c2410_sleep_save_phys;
29561 -
29562 -/* sleep save info */
29563 -
29564 -struct sleep_save {
29565 -       void __iomem    *reg;
29566 -       unsigned long   val;
29567 -};
29568 -
29569 -#define SAVE_ITEM(x) \
29570 -       { .reg = (x) }
29571 -
29572 -extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
29573 -extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
29574 -
29575 -#ifdef CONFIG_PM
29576 -extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
29577 -extern int s3c24xx_irq_resume(struct sys_device *dev);
29578 -#else
29579 -#define s3c24xx_irq_suspend NULL
29580 -#define s3c24xx_irq_resume  NULL
29581 -#endif
29582 --- /dev/null
29583 +++ b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
29584 @@ -0,0 +1,82 @@
29585 +/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
29586 + *
29587 + * Copyright (c) 2004 Fetron GmbH
29588 + *
29589 + * This program is free software; you can redistribute it and/or modify
29590 + * it under the terms of the GNU General Public License version 2 as
29591 + * published by the Free Software Foundation.
29592 + *
29593 + * S3C2410 SPI register definition
29594 +*/
29595 +
29596 +#ifndef __ASM_ARCH_REGS_SPI_H
29597 +#define __ASM_ARCH_REGS_SPI_H
29598 +
29599 +#define S3C2410_SPI1   (0x20)
29600 +#define S3C2412_SPI1   (0x100)
29601 +
29602 +#define S3C2410_SPCON  (0x00)
29603 +
29604 +#define S3C2412_SPCON_RXFIFO_RB2       (0<<14)
29605 +#define S3C2412_SPCON_RXFIFO_RB4       (1<<14)
29606 +#define S3C2412_SPCON_RXFIFO_RB12      (2<<14)
29607 +#define S3C2412_SPCON_RXFIFO_RB14      (3<<14)
29608 +#define S3C2412_SPCON_TXFIFO_RB2       (0<<12)
29609 +#define S3C2412_SPCON_TXFIFO_RB4       (1<<12)
29610 +#define S3C2412_SPCON_TXFIFO_RB12      (2<<12)
29611 +#define S3C2412_SPCON_TXFIFO_RB14      (3<<12)
29612 +#define S3C2412_SPCON_RXFIFO_RESET     (1<<11) /* RxFIFO reset */
29613 +#define S3C2412_SPCON_TXFIFO_RESET     (1<<10) /* TxFIFO reset */
29614 +#define S3C2412_SPCON_RXFIFO_EN                (1<<9)  /* RxFIFO Enable */
29615 +#define S3C2412_SPCON_TXFIFO_EN                (1<<8)  /* TxFIFO Enable */
29616 +
29617 +#define S3C2412_SPCON_DIRC_RX    (1<<7)
29618 +
29619 +#define S3C2410_SPCON_SMOD_DMA   (2<<5)        /* DMA mode */
29620 +#define S3C2410_SPCON_SMOD_INT   (1<<5)        /* interrupt mode */
29621 +#define S3C2410_SPCON_SMOD_POLL   (0<<5)       /* polling mode */
29622 +#define S3C2410_SPCON_ENSCK      (1<<4)        /* Enable SCK */
29623 +#define S3C2410_SPCON_MSTR       (1<<3)        /* Master/Slave select
29624 +                                                  0: slave, 1: master */
29625 +#define S3C2410_SPCON_CPOL_HIGH          (1<<2)        /* Clock polarity select */
29626 +#define S3C2410_SPCON_CPOL_LOW   (0<<2)        /* Clock polarity select */
29627 +
29628 +#define S3C2410_SPCON_CPHA_FMTB          (1<<1)        /* Clock Phase Select */
29629 +#define S3C2410_SPCON_CPHA_FMTA          (0<<1)        /* Clock Phase Select */
29630 +
29631 +#define S3C2410_SPCON_TAGD       (1<<0)        /* Tx auto garbage data mode */
29632 +
29633 +
29634 +#define S3C2410_SPSTA   (0x04)
29635 +
29636 +#define S3C2412_SPSTA_RXFIFO_AE                (1<<11)
29637 +#define S3C2412_SPSTA_TXFIFO_AE                (1<<10)
29638 +#define S3C2412_SPSTA_RXFIFO_ERROR     (1<<9)
29639 +#define S3C2412_SPSTA_TXFIFO_ERROR     (1<<8)
29640 +#define S3C2412_SPSTA_RXFIFO_FIFO      (1<<7)
29641 +#define S3C2412_SPSTA_RXFIFO_EMPTY     (1<<6)
29642 +#define S3C2412_SPSTA_TXFIFO_NFULL     (1<<5)
29643 +#define S3C2412_SPSTA_TXFIFO_EMPTY     (1<<4)
29644 +
29645 +#define S3C2410_SPSTA_DCOL       (1<<2)        /* Data Collision Error */
29646 +#define S3C2410_SPSTA_MULD       (1<<1)        /* Multi Master Error */
29647 +#define S3C2410_SPSTA_READY      (1<<0)        /* Data Tx/Rx ready */
29648 +#define S3C2412_SPSTA_READY_ORG          (1<<3)
29649 +
29650 +#define S3C2410_SPPIN   (0x08)
29651 +
29652 +#define S3C2410_SPPIN_ENMUL      (1<<2)        /* Multi Master Error detect */
29653 +#define S3C2410_SPPIN_RESERVED   (1<<1)
29654 +#define S3C2400_SPPIN_nCS        (1<<1)        /* SPI Card Select */
29655 +#define S3C2410_SPPIN_KEEP       (1<<0)        /* Master Out keep */
29656 +
29657 +#define S3C2410_SPPRE   (0x0C)
29658 +#define S3C2410_SPTDAT  (0x10)
29659 +#define S3C2410_SPRDAT  (0x14)
29660 +
29661 +#define S3C2412_TXFIFO  (0x18)
29662 +#define S3C2412_RXFIFO  (0x18)
29663 +#define S3C2412_SPFIC   (0x24)
29664 +
29665 +
29666 +#endif /* __ASM_ARCH_REGS_SPI_H */
29667 --- /dev/null
29668 +++ b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
29669 @@ -0,0 +1,153 @@
29670 +/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
29671 + *
29672 + * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
29673 + *
29674 + * This include file is free software; you can redistribute it and/or
29675 + * modify it under the terms of the GNU General Public License as
29676 + * published by the Free Software Foundation; either version 2 of
29677 + * the License, or (at your option) any later version.
29678 +*/
29679 +
29680 +#ifndef __ASM_ARCH_REGS_UDC_H
29681 +#define __ASM_ARCH_REGS_UDC_H
29682 +
29683 +#define S3C2410_USBDREG(x) (x)
29684 +
29685 +#define S3C2410_UDC_FUNC_ADDR_REG      S3C2410_USBDREG(0x0140)
29686 +#define S3C2410_UDC_PWR_REG            S3C2410_USBDREG(0x0144)
29687 +#define S3C2410_UDC_EP_INT_REG         S3C2410_USBDREG(0x0148)
29688 +
29689 +#define S3C2410_UDC_USB_INT_REG                S3C2410_USBDREG(0x0158)
29690 +#define S3C2410_UDC_EP_INT_EN_REG      S3C2410_USBDREG(0x015c)
29691 +
29692 +#define S3C2410_UDC_USB_INT_EN_REG     S3C2410_USBDREG(0x016c)
29693 +
29694 +#define S3C2410_UDC_FRAME_NUM1_REG     S3C2410_USBDREG(0x0170)
29695 +#define S3C2410_UDC_FRAME_NUM2_REG     S3C2410_USBDREG(0x0174)
29696 +
29697 +#define S3C2410_UDC_EP0_FIFO_REG       S3C2410_USBDREG(0x01c0)
29698 +#define S3C2410_UDC_EP1_FIFO_REG       S3C2410_USBDREG(0x01c4)
29699 +#define S3C2410_UDC_EP2_FIFO_REG       S3C2410_USBDREG(0x01c8)
29700 +#define S3C2410_UDC_EP3_FIFO_REG       S3C2410_USBDREG(0x01cc)
29701 +#define S3C2410_UDC_EP4_FIFO_REG       S3C2410_USBDREG(0x01d0)
29702 +
29703 +#define S3C2410_UDC_EP1_DMA_CON                S3C2410_USBDREG(0x0200)
29704 +#define S3C2410_UDC_EP1_DMA_UNIT       S3C2410_USBDREG(0x0204)
29705 +#define S3C2410_UDC_EP1_DMA_FIFO       S3C2410_USBDREG(0x0208)
29706 +#define S3C2410_UDC_EP1_DMA_TTC_L      S3C2410_USBDREG(0x020c)
29707 +#define S3C2410_UDC_EP1_DMA_TTC_M      S3C2410_USBDREG(0x0210)
29708 +#define S3C2410_UDC_EP1_DMA_TTC_H      S3C2410_USBDREG(0x0214)
29709 +
29710 +#define S3C2410_UDC_EP2_DMA_CON                S3C2410_USBDREG(0x0218)
29711 +#define S3C2410_UDC_EP2_DMA_UNIT       S3C2410_USBDREG(0x021c)
29712 +#define S3C2410_UDC_EP2_DMA_FIFO       S3C2410_USBDREG(0x0220)
29713 +#define S3C2410_UDC_EP2_DMA_TTC_L      S3C2410_USBDREG(0x0224)
29714 +#define S3C2410_UDC_EP2_DMA_TTC_M      S3C2410_USBDREG(0x0228)
29715 +#define S3C2410_UDC_EP2_DMA_TTC_H      S3C2410_USBDREG(0x022c)
29716 +
29717 +#define S3C2410_UDC_EP3_DMA_CON                S3C2410_USBDREG(0x0240)
29718 +#define S3C2410_UDC_EP3_DMA_UNIT       S3C2410_USBDREG(0x0244)
29719 +#define S3C2410_UDC_EP3_DMA_FIFO       S3C2410_USBDREG(0x0248)
29720 +#define S3C2410_UDC_EP3_DMA_TTC_L      S3C2410_USBDREG(0x024c)
29721 +#define S3C2410_UDC_EP3_DMA_TTC_M      S3C2410_USBDREG(0x0250)
29722 +#define S3C2410_UDC_EP3_DMA_TTC_H      S3C2410_USBDREG(0x0254)
29723 +
29724 +#define S3C2410_UDC_EP4_DMA_CON                S3C2410_USBDREG(0x0258)
29725 +#define S3C2410_UDC_EP4_DMA_UNIT       S3C2410_USBDREG(0x025c)
29726 +#define S3C2410_UDC_EP4_DMA_FIFO       S3C2410_USBDREG(0x0260)
29727 +#define S3C2410_UDC_EP4_DMA_TTC_L      S3C2410_USBDREG(0x0264)
29728 +#define S3C2410_UDC_EP4_DMA_TTC_M      S3C2410_USBDREG(0x0268)
29729 +#define S3C2410_UDC_EP4_DMA_TTC_H      S3C2410_USBDREG(0x026c)
29730 +
29731 +#define S3C2410_UDC_INDEX_REG          S3C2410_USBDREG(0x0178)
29732 +
29733 +/* indexed registers */
29734 +
29735 +#define S3C2410_UDC_MAXP_REG           S3C2410_USBDREG(0x0180)
29736 +
29737 +#define S3C2410_UDC_EP0_CSR_REG                S3C2410_USBDREG(0x0184)
29738 +
29739 +#define S3C2410_UDC_IN_CSR1_REG                S3C2410_USBDREG(0x0184)
29740 +#define S3C2410_UDC_IN_CSR2_REG                S3C2410_USBDREG(0x0188)
29741 +
29742 +#define S3C2410_UDC_OUT_CSR1_REG       S3C2410_USBDREG(0x0190)
29743 +#define S3C2410_UDC_OUT_CSR2_REG       S3C2410_USBDREG(0x0194)
29744 +#define S3C2410_UDC_OUT_FIFO_CNT1_REG  S3C2410_USBDREG(0x0198)
29745 +#define S3C2410_UDC_OUT_FIFO_CNT2_REG  S3C2410_USBDREG(0x019c)
29746 +
29747 +#define S3C2410_UDC_FUNCADDR_UPDATE    (1<<7)
29748 +
29749 +#define S3C2410_UDC_PWR_ISOUP          (1<<7) // R/W
29750 +#define S3C2410_UDC_PWR_RESET          (1<<3) // R
29751 +#define S3C2410_UDC_PWR_RESUME         (1<<2) // R/W
29752 +#define S3C2410_UDC_PWR_SUSPEND                (1<<1) // R
29753 +#define S3C2410_UDC_PWR_ENSUSPEND      (1<<0) // R/W
29754 +
29755 +#define S3C2410_UDC_PWR_DEFAULT                0x00
29756 +
29757 +#define S3C2410_UDC_INT_EP4            (1<<4) // R/W (clear only)
29758 +#define S3C2410_UDC_INT_EP3            (1<<3) // R/W (clear only)
29759 +#define S3C2410_UDC_INT_EP2            (1<<2) // R/W (clear only)
29760 +#define S3C2410_UDC_INT_EP1            (1<<1) // R/W (clear only)
29761 +#define S3C2410_UDC_INT_EP0            (1<<0) // R/W (clear only)
29762 +
29763 +#define S3C2410_UDC_USBINT_RESET       (1<<2) // R/W (clear only)
29764 +#define S3C2410_UDC_USBINT_RESUME      (1<<1) // R/W (clear only)
29765 +#define S3C2410_UDC_USBINT_SUSPEND     (1<<0) // R/W (clear only)
29766 +
29767 +#define S3C2410_UDC_INTE_EP4           (1<<4) // R/W
29768 +#define S3C2410_UDC_INTE_EP3           (1<<3) // R/W
29769 +#define S3C2410_UDC_INTE_EP2           (1<<2) // R/W
29770 +#define S3C2410_UDC_INTE_EP1           (1<<1) // R/W
29771 +#define S3C2410_UDC_INTE_EP0           (1<<0) // R/W
29772 +
29773 +#define S3C2410_UDC_USBINTE_RESET      (1<<2) // R/W
29774 +#define S3C2410_UDC_USBINTE_SUSPEND    (1<<0) // R/W
29775 +
29776 +
29777 +#define S3C2410_UDC_INDEX_EP0          (0x00)
29778 +#define S3C2410_UDC_INDEX_EP1          (0x01) // ??
29779 +#define S3C2410_UDC_INDEX_EP2          (0x02) // ??
29780 +#define S3C2410_UDC_INDEX_EP3          (0x03) // ??
29781 +#define S3C2410_UDC_INDEX_EP4          (0x04) // ??
29782 +
29783 +#define S3C2410_UDC_ICSR1_CLRDT                (1<<6) // R/W
29784 +#define S3C2410_UDC_ICSR1_SENTSTL      (1<<5) // R/W (clear only)
29785 +#define S3C2410_UDC_ICSR1_SENDSTL      (1<<4) // R/W
29786 +#define S3C2410_UDC_ICSR1_FFLUSH       (1<<3) // W   (set only)
29787 +#define S3C2410_UDC_ICSR1_UNDRUN       (1<<2) // R/W (clear only)
29788 +#define S3C2410_UDC_ICSR1_PKTRDY       (1<<0) // R/W (set only)
29789 +
29790 +#define S3C2410_UDC_ICSR2_AUTOSET      (1<<7) // R/W
29791 +#define S3C2410_UDC_ICSR2_ISO          (1<<6) // R/W
29792 +#define S3C2410_UDC_ICSR2_MODEIN       (1<<5) // R/W
29793 +#define S3C2410_UDC_ICSR2_DMAIEN       (1<<4) // R/W
29794 +
29795 +#define S3C2410_UDC_OCSR1_CLRDT                (1<<7) // R/W
29796 +#define S3C2410_UDC_OCSR1_SENTSTL      (1<<6) // R/W (clear only)
29797 +#define S3C2410_UDC_OCSR1_SENDSTL      (1<<5) // R/W
29798 +#define S3C2410_UDC_OCSR1_FFLUSH       (1<<4) // R/W
29799 +#define S3C2410_UDC_OCSR1_DERROR       (1<<3) // R
29800 +#define S3C2410_UDC_OCSR1_OVRRUN       (1<<2) // R/W (clear only)
29801 +#define S3C2410_UDC_OCSR1_PKTRDY       (1<<0) // R/W (clear only)
29802 +
29803 +#define S3C2410_UDC_OCSR2_AUTOCLR      (1<<7) // R/W
29804 +#define S3C2410_UDC_OCSR2_ISO          (1<<6) // R/W
29805 +#define S3C2410_UDC_OCSR2_DMAIEN       (1<<5) // R/W
29806 +
29807 +#define S3C2410_UDC_EP0_CSR_OPKRDY     (1<<0)
29808 +#define S3C2410_UDC_EP0_CSR_IPKRDY     (1<<1)
29809 +#define S3C2410_UDC_EP0_CSR_SENTSTL    (1<<2)
29810 +#define S3C2410_UDC_EP0_CSR_DE         (1<<3)
29811 +#define S3C2410_UDC_EP0_CSR_SE         (1<<4)
29812 +#define S3C2410_UDC_EP0_CSR_SENDSTL    (1<<5)
29813 +#define S3C2410_UDC_EP0_CSR_SOPKTRDY   (1<<6)
29814 +#define S3C2410_UDC_EP0_CSR_SSE        (1<<7)
29815 +
29816 +#define S3C2410_UDC_MAXP_8             (1<<0)
29817 +#define S3C2410_UDC_MAXP_16            (1<<1)
29818 +#define S3C2410_UDC_MAXP_32            (1<<2)
29819 +#define S3C2410_UDC_MAXP_64            (1<<3)
29820 +
29821 +
29822 +#endif
29823 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
29824 +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
29825 @@ -17,7 +17,7 @@
29826
29827  extern  int s3c2400_init(void);
29828
29829 -extern void s3c2400_map_io(struct map_desc *mach_desc, int size);
29830 +extern void s3c2400_map_io(void);
29831
29832  extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
29833
29834 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
29835 +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
29836 @@ -15,7 +15,7 @@
29837
29838  extern  int s3c2410_init(void);
29839
29840 -extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
29841 +extern void s3c2410_map_io(void);
29842
29843  extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
29844
29845 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
29846 +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
29847 @@ -14,7 +14,7 @@
29848
29849  extern  int s3c2412_init(void);
29850
29851 -extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
29852 +extern void s3c2412_map_io(void);
29853
29854  extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
29855
29856 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
29857 +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
29858 @@ -16,7 +16,7 @@ struct s3c2410_uartcfg;
29859
29860  extern  int s3c2443_init(void);
29861
29862 -extern void s3c2443_map_io(struct map_desc *mach_desc, int size);
29863 +extern void s3c2443_map_io(void);
29864
29865  extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
29866
29867 --- /dev/null
29868 +++ b/arch/arm/plat-s3c24xx/include/plat/udc.h
29869 @@ -0,0 +1,36 @@
29870 +/* arch/arm/mach-s3c2410/include/mach/udc.h
29871 + *
29872 + * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
29873 + *
29874 + *
29875 + * This program is free software; you can redistribute it and/or modify
29876 + * it under the terms of the GNU General Public License version 2 as
29877 + * published by the Free Software Foundation.
29878 + *
29879 + *
29880 + *  Changelog:
29881 + *     14-Mar-2005     RTP     Created file
29882 + *     02-Aug-2005     RTP     File rename
29883 + *     07-Sep-2005     BJD     Minor cleanups, changed cmd to enum
29884 + *     18-Jan-2007     HMW     Add per-platform vbus_draw function
29885 +*/
29886 +
29887 +#ifndef __ASM_ARM_ARCH_UDC_H
29888 +#define __ASM_ARM_ARCH_UDC_H
29889 +
29890 +enum s3c2410_udc_cmd_e {
29891 +       S3C2410_UDC_P_ENABLE    = 1,    /* Pull-up enable        */
29892 +       S3C2410_UDC_P_DISABLE   = 2,    /* Pull-up disable       */
29893 +       S3C2410_UDC_P_RESET     = 3,    /* UDC reset, in case of */
29894 +};
29895 +
29896 +struct s3c2410_udc_mach_info {
29897 +       void    (*udc_command)(enum s3c2410_udc_cmd_e);
29898 +       void    (*vbus_draw)(unsigned int ma);
29899 +       unsigned int vbus_pin;
29900 +       unsigned char vbus_pin_inverted;
29901 +};
29902 +
29903 +extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
29904 +
29905 +#endif /* __ASM_ARM_ARCH_UDC_H */
29906 --- a/arch/arm/plat-s3c24xx/irq.c
29907 +++ b/arch/arm/plat-s3c24xx/irq.c
29908 @@ -1,6 +1,6 @@
29909  /* linux/arch/arm/plat-s3c24xx/irq.c
29910   *
29911 - * Copyright (c) 2003,2004 Simtec Electronics
29912 + * Copyright (c) 2003,2004 Simtec Electronics
29913   *     Ben Dooks <ben@simtec.co.uk>
29914   *
29915   * This program is free software; you can redistribute it and/or modify
29916 @@ -16,38 +16,6 @@
29917   * You should have received a copy of the GNU General Public License
29918   * along with this program; if not, write to the Free Software
29919   * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
29920 - *
29921 - * Changelog:
29922 - *
29923 - *   22-Jul-2004  Ben Dooks <ben@simtec.co.uk>
29924 - *                Fixed compile warnings
29925 - *
29926 - *   22-Jul-2004  Roc Wu <cooloney@yahoo.com.cn>
29927 - *                Fixed s3c_extirq_type
29928 - *
29929 - *   21-Jul-2004  Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
29930 - *                Addition of ADC/TC demux
29931 - *
29932 - *   04-Oct-2004  Klaus Fetscher <k.fetscher@fetron.de>
29933 - *               Fix for set_irq_type() on low EINT numbers
29934 - *
29935 - *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk>
29936 - *               Tidy up KF's patch and sort out new release
29937 - *
29938 - *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk>
29939 - *               Add support for power management controls
29940 - *
29941 - *   04-Nov-2004  Ben Dooks
29942 - *               Fix standard IRQ wake for EINT0..4 and RTC
29943 - *
29944 - *   22-Feb-2005  Ben Dooks
29945 - *               Fixed edge-triggering on ADC IRQ
29946 - *
29947 - *   28-Jun-2005  Ben Dooks
29948 - *               Mark IRQ_LCD valid
29949 - *
29950 - *   25-Jul-2005  Ben Dooks
29951 - *               Split the S3C2440 IRQ code to separate file
29952  */
29953
29954  #include <linux/init.h>
29955 @@ -55,90 +23,34 @@
29956  #include <linux/interrupt.h>
29957  #include <linux/ioport.h>
29958  #include <linux/sysdev.h>
29959 -#include <linux/io.h>
29960
29961 -#include <mach/hardware.h>
29962  #include <asm/irq.h>
29963 -
29964  #include <asm/mach/irq.h>
29965
29966 -#include <mach/regs-irq.h>
29967 -#include <mach/regs-gpio.h>
29968 +#include <plat/regs-irqtype.h>
29969
29970  #include <plat/cpu.h>
29971  #include <plat/pm.h>
29972  #include <plat/irq.h>
29973
29974 -/* wakeup irq control */
29975 -
29976 -#ifdef CONFIG_PM
29977 -
29978 -/* state for IRQs over sleep */
29979 -
29980 -/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
29981 - *
29982 - * set bit to 1 in allow bitfield to enable the wakeup settings on it
29983 -*/
29984 -
29985 -unsigned long s3c_irqwake_intallow     = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
29986 -unsigned long s3c_irqwake_intmask      = 0xffffffffL;
29987 -unsigned long s3c_irqwake_eintallow    = 0x0000fff0L;
29988 -unsigned long s3c_irqwake_eintmask     = 0xffffffffL;
29989 -
29990 -int
29991 -s3c_irq_wake(unsigned int irqno, unsigned int state)
29992 -{
29993 -       unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
29994 -
29995 -       if (!(s3c_irqwake_intallow & irqbit))
29996 -               return -ENOENT;
29997 -
29998 -       printk(KERN_INFO "wake %s for irq %d\n",
29999 -              state ? "enabled" : "disabled", irqno);
30000 -
30001 -       if (!state)
30002 -               s3c_irqwake_intmask |= irqbit;
30003 -       else
30004 -               s3c_irqwake_intmask &= ~irqbit;
30005 -
30006 -       return 0;
30007 -}
30008 -
30009 -static int
30010 -s3c_irqext_wake(unsigned int irqno, unsigned int state)
30011 -{
30012 -       unsigned long bit = 1L << (irqno - EXTINT_OFF);
30013 -
30014 -       if (!(s3c_irqwake_eintallow & bit))
30015 -               return -ENOENT;
30016 -
30017 -       printk(KERN_INFO "wake %s for irq %d\n",
30018 -              state ? "enabled" : "disabled", irqno);
30019 -
30020 -       if (!state)
30021 -               s3c_irqwake_eintmask |= bit;
30022 -       else
30023 -               s3c_irqwake_eintmask &= ~bit;
30024 -
30025 -       return 0;
30026 -}
30027 -
30028 -#else
30029 -#define s3c_irqext_wake NULL
30030 -#define s3c_irq_wake NULL
30031 -#endif
30032 -
30033 -
30034  static void
30035  s3c_irq_mask(unsigned int irqno)
30036  {
30037         unsigned long mask;
30038 -
30039 +#ifdef CONFIG_S3C2440_C_FIQ
30040 +       unsigned long flags;
30041 +#endif
30042         irqno -= IRQ_EINT0;
30043 -
30044 +#ifdef CONFIG_S3C2440_C_FIQ
30045 +       local_save_flags(flags);
30046 +       local_fiq_disable();
30047 +#endif
30048         mask = __raw_readl(S3C2410_INTMSK);
30049         mask |= 1UL << irqno;
30050         __raw_writel(mask, S3C2410_INTMSK);
30051 +#ifdef CONFIG_S3C2440_C_FIQ
30052 +       local_irq_restore(flags);
30053 +#endif
30054  }
30055
30056  static inline void
30057 @@ -155,9 +67,19 @@ s3c_irq_maskack(unsigned int irqno)
30058  {
30059         unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
30060         unsigned long mask;
30061 +#ifdef CONFIG_S3C2440_C_FIQ
30062 +       unsigned long flags;
30063 +#endif
30064
30065 +#ifdef CONFIG_S3C2440_C_FIQ
30066 +       local_save_flags(flags);
30067 +       local_fiq_disable();
30068 +#endif
30069         mask = __raw_readl(S3C2410_INTMSK);
30070         __raw_writel(mask|bitval, S3C2410_INTMSK);
30071 +#ifdef CONFIG_S3C2440_C_FIQ
30072 +       local_irq_restore(flags);
30073 +#endif
30074
30075         __raw_writel(bitval, S3C2410_SRCPND);
30076         __raw_writel(bitval, S3C2410_INTPND);
30077 @@ -168,15 +90,25 @@ static void
30078  s3c_irq_unmask(unsigned int irqno)
30079  {
30080         unsigned long mask;
30081 +#ifdef CONFIG_S3C2440_C_FIQ
30082 +       unsigned long flags;
30083 +#endif
30084
30085         if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
30086                 irqdbf2("s3c_irq_unmask %d\n", irqno);
30087
30088         irqno -= IRQ_EINT0;
30089
30090 +#ifdef CONFIG_S3C2440_C_FIQ
30091 +       local_save_flags(flags);
30092 +       local_fiq_disable();
30093 +#endif
30094         mask = __raw_readl(S3C2410_INTMSK);
30095         mask &= ~(1UL << irqno);
30096         __raw_writel(mask, S3C2410_INTMSK);
30097 +#ifdef CONFIG_S3C2440_C_FIQ
30098 +       local_irq_restore(flags);
30099 +#endif
30100  }
30101
30102  struct irq_chip s3c_irq_level_chip = {
30103 @@ -589,59 +521,6 @@ s3c_irq_demux_extint4t7(unsigned int irq
30104         }
30105  }
30106
30107 -#ifdef CONFIG_PM
30108 -
30109 -static struct sleep_save irq_save[] = {
30110 -       SAVE_ITEM(S3C2410_INTMSK),
30111 -       SAVE_ITEM(S3C2410_INTSUBMSK),
30112 -};
30113 -
30114 -/* the extint values move between the s3c2410/s3c2440 and the s3c2412
30115 - * so we use an array to hold them, and to calculate the address of
30116 - * the register at run-time
30117 -*/
30118 -
30119 -static unsigned long save_extint[3];
30120 -static unsigned long save_eintflt[4];
30121 -static unsigned long save_eintmask;
30122 -
30123 -int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
30124 -{
30125 -       unsigned int i;
30126 -
30127 -       for (i = 0; i < ARRAY_SIZE(save_extint); i++)
30128 -               save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
30129 -
30130 -       for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
30131 -               save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
30132 -
30133 -       s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
30134 -       save_eintmask = __raw_readl(S3C24XX_EINTMASK);
30135 -
30136 -       return 0;
30137 -}
30138 -
30139 -int s3c24xx_irq_resume(struct sys_device *dev)
30140 -{
30141 -       unsigned int i;
30142 -
30143 -       for (i = 0; i < ARRAY_SIZE(save_extint); i++)
30144 -               __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
30145 -
30146 -       for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
30147 -               __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
30148 -
30149 -       s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
30150 -       __raw_writel(save_eintmask, S3C24XX_EINTMASK);
30151 -
30152 -       return 0;
30153 -}
30154 -
30155 -#else
30156 -#define s3c24xx_irq_suspend NULL
30157 -#define s3c24xx_irq_resume  NULL
30158 -#endif
30159 -
30160  /* s3c24xx_init_irq
30161   *
30162   * Initialise S3C2410 IRQ system
30163 @@ -672,26 +551,26 @@ void __init s3c24xx_init_irq(void)
30164
30165         last = 0;
30166         for (i = 0; i < 4; i++) {
30167 -               pend = __raw_readl(S3C2410_INTPND);
30168 +               pend = __raw_readl(S3C2410_SUBSRCPND);
30169
30170                 if (pend == 0 || pend == last)
30171                         break;
30172
30173 -               __raw_writel(pend, S3C2410_SRCPND);
30174 -               __raw_writel(pend, S3C2410_INTPND);
30175 -               printk("irq: clearing pending status %08x\n", (int)pend);
30176 +               printk("irq: clearing subpending status %08x\n", (int)pend);
30177 +               __raw_writel(pend, S3C2410_SUBSRCPND);
30178                 last = pend;
30179         }
30180
30181         last = 0;
30182         for (i = 0; i < 4; i++) {
30183 -               pend = __raw_readl(S3C2410_SUBSRCPND);
30184 +               pend = __raw_readl(S3C2410_INTPND);
30185
30186                 if (pend == 0 || pend == last)
30187                         break;
30188
30189 -               printk("irq: clearing subpending status %08x\n", (int)pend);
30190 -               __raw_writel(pend, S3C2410_SUBSRCPND);
30191 +               __raw_writel(pend, S3C2410_SRCPND);
30192 +               __raw_writel(pend, S3C2410_INTPND);
30193 +               printk("irq: clearing pending status %08x\n", (int)pend);
30194                 last = pend;
30195         }
30196
30197 --- /dev/null
30198 +++ b/arch/arm/plat-s3c24xx/irq-pm.c
30199 @@ -0,0 +1,118 @@
30200 +/* linux/arch/arm/plat-s3c24xx/irq-om.c
30201 + *
30202 + * Copyright (c) 2003,2004 Simtec Electronics
30203 + *     Ben Dooks <ben@simtec.co.uk>
30204 + *     http://armlinux.simtec.co.uk/
30205 + *
30206 + * S3C24XX - IRQ PM code
30207 + *
30208 + * This program is free software; you can redistribute it and/or modify
30209 + * it under the terms of the GNU General Public License version 2 as
30210 + * published by the Free Software Foundation.
30211 + */
30212 +
30213 +#include <linux/init.h>
30214 +#include <linux/module.h>
30215 +#include <linux/interrupt.h>
30216 +#include <linux/sysdev.h>
30217 +#include <linux/irq.h>
30218 +
30219 +#include <plat/cpu.h>
30220 +#include <plat/pm.h>
30221 +#include <plat/irq.h>
30222 +
30223 +/* state for IRQs over sleep */
30224 +
30225 +/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
30226 + *
30227 + * set bit to 1 in allow bitfield to enable the wakeup settings on it
30228 +*/
30229 +
30230 +unsigned long s3c_irqwake_intallow     = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
30231 +unsigned long s3c_irqwake_eintallow    = 0x0000fff0L;
30232 +
30233 +int s3c_irq_wake(unsigned int irqno, unsigned int state)
30234 +{
30235 +       unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
30236 +
30237 +       if (!(s3c_irqwake_intallow & irqbit))
30238 +               return -ENOENT;
30239 +
30240 +       printk(KERN_INFO "wake %s for irq %d\n",
30241 +              state ? "enabled" : "disabled", irqno);
30242 +
30243 +       if (!state)
30244 +               s3c_irqwake_intmask |= irqbit;
30245 +       else
30246 +               s3c_irqwake_intmask &= ~irqbit;
30247 +
30248 +       return 0;
30249 +}
30250 +
30251 +static struct sleep_save irq_save[] = {
30252 +       SAVE_ITEM(S3C2410_INTMSK),
30253 +       SAVE_ITEM(S3C2410_INTSUBMSK),
30254 +};
30255 +
30256 +/* the extint values move between the s3c2410/s3c2440 and the s3c2412
30257 + * so we use an array to hold them, and to calculate the address of
30258 + * the register at run-time
30259 +*/
30260 +
30261 +static unsigned long save_extint[3];
30262 +static unsigned long save_eintflt[4];
30263 +static unsigned long save_eintmask;
30264 +
30265 +int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
30266 +{
30267 +       unsigned int i;
30268 +
30269 +       for (i = 0; i < ARRAY_SIZE(save_extint); i++)
30270 +               save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
30271 +
30272 +       for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
30273 +               save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
30274 +
30275 +       s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
30276 +       save_eintmask = __raw_readl(S3C24XX_EINTMASK);
30277 +
30278 +       return 0;
30279 +}
30280 +
30281 +int s3c24xx_irq_resume(struct sys_device *dev)
30282 +{
30283 +       unsigned int i, irq;
30284 +       unsigned long eintpnd;
30285 +       struct irq_desc *desc;
30286 +
30287 +       for (i = 0; i < ARRAY_SIZE(save_extint); i++)
30288 +               __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
30289 +
30290 +       for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
30291 +               __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
30292 +
30293 +       s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
30294 +       __raw_writel(save_eintmask, S3C24XX_EINTMASK);
30295 +
30296 +       /*
30297 +        * ACK those interrupts which are now masked and pending.
30298 +        * Level interrupts if not ACKed here, create an interrupt storm
30299 +        * because they are not handled at all.
30300 +        */
30301 +
30302 +       eintpnd = __raw_readl(S3C24XX_EINTPEND);
30303 +
30304 +       eintpnd &= save_eintmask;
30305 +       eintpnd &= ~0xff;       /* ignore lower irqs */
30306 +
30307 +       while (eintpnd) {
30308 +               irq = __ffs(eintpnd);
30309 +               eintpnd &= ~(1 << irq);
30310 +
30311 +               irq += (IRQ_EINT4 - 4);
30312 +               desc = irq_to_desc(irq);
30313 +               desc->chip->ack(irq);
30314 +       }
30315 +
30316 +       return 0;
30317 +}
30318 --- a/arch/arm/plat-s3c24xx/Kconfig
30319 +++ b/arch/arm/plat-s3c24xx/Kconfig
30320 @@ -6,18 +6,32 @@
30321
30322  config PLAT_S3C24XX
30323         bool
30324 -       depends on ARCH_S3C2410
30325 -       default y if ARCH_S3C2410
30326 +       depends on ARCH_S3C2410 || ARCH_S3C24A0
30327 +       default y
30328         select NO_IOPORT
30329         select ARCH_REQUIRE_GPIOLIB
30330 +       select S3C_GPIO_TRACK
30331         help
30332           Base platform code for any Samsung S3C24XX device
30333
30334  if PLAT_S3C24XX
30335
30336 +# code that is shared between a number of the s3c24xx implementations
30337 +
30338 +config S3C2410_CLOCK
30339 +       bool
30340 +       help
30341 +         Clock code for the S3C2410, and similar processors which
30342 +         is currently includes the S3C2410, S3C2440, S3C2442.
30343 +
30344 +config S3C24XX_DCLK
30345 +       bool
30346 +       help
30347 +         Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
30348 +
30349  config CPU_S3C244X
30350         bool
30351 -       depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
30352 +       default y if CPU_S3C2440 || CPU_S3C2442
30353         help
30354           Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
30355
30356 @@ -49,9 +63,31 @@ config S3C2410_DMA_DEBUG
30357           Enable debugging output for the DMA code. This option sends info
30358           to the kernel log, at priority KERN_DEBUG.
30359
30360 +# SPI default pin configuration code
30361 +
30362 +config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13
30363 +       bool
30364 +       help
30365 +         SPI GPIO configuration code for BUS0 when connected to
30366 +         GPE11, GPE12 and GPE13.
30367 +
30368 +config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
30369 +       bool
30370 +       help
30371 +         SPI GPIO configuration code for BUS 1 when connected to
30372 +         GPG5, GPG6 and GPG7.
30373 +
30374 +# common code for s3c24xx based machines, such as the SMDKs.
30375 +
30376  config MACH_SMDK
30377         bool
30378         help
30379           Common machine code for SMDK2410 and SMDK2440
30380
30381 +config MACH_NEO1973
30382 +       bool
30383 +       select RFKILL
30384 +       help
30385 +         Common machine code for Neo1973 hardware
30386 +
30387  endif
30388 --- a/arch/arm/plat-s3c24xx/Makefile
30389 +++ b/arch/arm/plat-s3c24xx/Makefile
30390 @@ -17,9 +17,8 @@ obj-y                         += irq.o
30391  obj-y                          += devs.o
30392  obj-y                          += gpio.o
30393  obj-y                          += gpiolib.o
30394 -obj-y                          += time.o
30395  obj-y                          += clock.o
30396 -obj-y                          += pwm-clock.o
30397 +obj-$(CONFIG_S3C24XX_DCLK)     += clock-dclk.o
30398
30399  # Architecture dependant builds
30400
30401 @@ -28,7 +27,26 @@ obj-$(CONFIG_CPU_S3C244X)    += s3c244x-irq
30402  obj-$(CONFIG_CPU_S3C244X)      += s3c244x-clock.o
30403  obj-$(CONFIG_PM_SIMTEC)                += pm-simtec.o
30404  obj-$(CONFIG_PM)               += pm.o
30405 +obj-$(CONFIG_PM)               += irq-pm.o
30406  obj-$(CONFIG_PM)               += sleep.o
30407  obj-$(CONFIG_HAVE_PWM)         += pwm.o
30408 +obj-$(CONFIG_S3C2410_CLOCK)    += s3c2410-clock.o
30409  obj-$(CONFIG_S3C2410_DMA)      += dma.o
30410 +
30411 +# device specific setup and/or initialisation
30412 +obj-$(CONFIG_ARCH_S3C2410)     += setup-i2c.o
30413 +
30414 +# SPI gpio central GPIO functions
30415 +
30416 +obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
30417 +obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7)    += spi-bus1-gpg5_6_7.o
30418 +
30419 +# machine common support
30420 +
30421  obj-$(CONFIG_MACH_SMDK)                += common-smdk.o
30422 +obj-$(CONFIG_MACH_NEO1973)     += \
30423 +                                   neo1973_pm_gsm.o \
30424 +                                   neo1973_pm_gps.o \
30425 +                                   neo1973_pm_bt.o  \
30426 +                                   gta02_pm_wlan.o  \
30427 +                                   neo1973_shadow.o
30428 --- /dev/null
30429 +++ b/arch/arm/plat-s3c24xx/neo1973_pm_bt.c
30430 @@ -0,0 +1,323 @@
30431 +/*
30432 + * Bluetooth PM code for the FIC Neo1973 GSM Phone
30433 + *
30434 + * (C) 2007 by Openmoko Inc.
30435 + * Author: Harald Welte <laforge@openmoko.org>
30436 + * All rights reserved.
30437 + *
30438 + * This program is free software; you can redistribute it and/or modify
30439 + * it under the terms of the GNU General Public License version 2 as
30440 + * published by the Free Software Foundation
30441 + *
30442 + */
30443 +
30444 +#include <linux/module.h>
30445 +#include <linux/init.h>
30446 +#include <linux/kernel.h>
30447 +#include <linux/platform_device.h>
30448 +#include <linux/rfkill.h>
30449 +#include <linux/err.h>
30450 +
30451 +#include <mach/hardware.h>
30452 +#include <asm/mach-types.h>
30453 +#include <asm/plat-s3c24xx/neo1973.h>
30454 +
30455 +/* For GTA01 */
30456 +#include <mach/gta01.h>
30457 +#include <linux/pcf50606.h>
30458 +
30459 +/* For GTA02 */
30460 +#include <mach/gta02.h>
30461 +#include <linux/mfd/pcf50633/gpio.h>
30462 +
30463 +#include <linux/regulator/consumer.h>
30464 +
30465 +#define DRVMSG "FIC Neo1973 Bluetooth Power Management"
30466 +
30467 +struct gta01_pm_bt_data {
30468 +       struct regulator *regulator;
30469 +       struct rfkill *rfkill;
30470 +       int pre_resume_state;
30471 +};
30472 +
30473 +static ssize_t bt_read(struct device *dev, struct device_attribute *attr,
30474 +                      char *buf)
30475 +{
30476 +       int ret = 0;
30477 +
30478 +       if (!strcmp(attr->attr.name, "power_on")) {
30479 +
30480 +               if (machine_is_neo1973_gta01()) {
30481 +                       if (pcf50606_onoff_get(pcf50606_global,
30482 +                                               PCF50606_REGULATOR_D1REG) &&
30483 +                           pcf50606_voltage_get(pcf50606_global,
30484 +                                                PCF50606_REGULATOR_D1REG) == 3100)
30485 +                               ret = 1;
30486 +               } else if (machine_is_neo1973_gta02()) {
30487 +                       if (s3c2410_gpio_getpin(GTA02_GPIO_BT_EN))
30488 +                               ret = 1;
30489 +               }
30490 +       } else if (!strcmp(attr->attr.name, "reset")) {
30491 +               if (machine_is_neo1973_gta01()) {
30492 +                       if (s3c2410_gpio_getpin(GTA01_GPIO_BT_EN) == 0)
30493 +                               ret = 1;
30494 +               } else if (machine_is_neo1973_gta02()) {
30495 +                       if (s3c2410_gpio_getpin(GTA02_GPIO_BT_EN) == 0)
30496 +                               ret = 1;
30497 +               }
30498 +       }
30499 +
30500 +       if (!ret) {
30501 +               return strlcpy(buf, "0\n", 3);
30502 +       } else {
30503 +               return strlcpy(buf, "1\n", 3);
30504 +       }
30505 +}
30506 +
30507 +static void __gta02_pm_bt_toggle_radio(struct device *dev, unsigned int on)
30508 +{
30509 +       struct gta01_pm_bt_data *bt_data = dev_get_drvdata(dev);
30510 +
30511 +       dev_info(dev, "__gta02_pm_bt_toggle_radio %d\n", on);
30512 +
30513 +       if (machine_is_neo1973_gta02()) {
30514 +
30515 +               bt_data = dev_get_drvdata(dev);
30516 +
30517 +               neo1973_gpb_setpin(GTA02_GPIO_BT_EN, !on);
30518 +
30519 +               if (on) {
30520 +                       if (!regulator_is_enabled(bt_data->regulator))
30521 +                               regulator_enable(bt_data->regulator);
30522 +               } else {
30523 +                       if (regulator_is_enabled(bt_data->regulator))
30524 +                               regulator_disable(bt_data->regulator);
30525 +               }
30526 +
30527 +               neo1973_gpb_setpin(GTA02_GPIO_BT_EN, on);
30528 +       }
30529 +}
30530 +
30531 +
30532 +static int bt_rfkill_toggle_radio(void *data, enum rfkill_state state)
30533 +{
30534 +       struct device *dev = data;
30535 +       unsigned long on = (state == RFKILL_STATE_ON);
30536 +
30537 +       if (machine_is_neo1973_gta01()) {
30538 +               /* if we are powering up, assert reset, then power,
30539 +                * then release reset */
30540 +               if (on) {
30541 +                       neo1973_gpb_setpin(GTA01_GPIO_BT_EN, 0);
30542 +                       pcf50606_voltage_set(pcf50606_global,
30543 +                                            PCF50606_REGULATOR_D1REG,
30544 +                                            3100);
30545 +               }
30546 +               pcf50606_onoff_set(pcf50606_global,
30547 +                                  PCF50606_REGULATOR_D1REG, on);
30548 +               neo1973_gpb_setpin(GTA01_GPIO_BT_EN, on);
30549 +       } else if (machine_is_neo1973_gta02())
30550 +               __gta02_pm_bt_toggle_radio(dev, on);
30551 +
30552 +       return 0;
30553 +}
30554 +
30555 +static ssize_t bt_write(struct device *dev, struct device_attribute *attr,
30556 +                       const char *buf, size_t count)
30557 +{
30558 +       unsigned long on = simple_strtoul(buf, NULL, 10);
30559 +       struct gta01_pm_bt_data *bt_data = dev_get_drvdata(dev);
30560 +
30561 +       if (!strcmp(attr->attr.name, "power_on")) {
30562 +               enum rfkill_state state = on ? RFKILL_STATE_ON : RFKILL_STATE_OFF;
30563 +               bt_rfkill_toggle_radio(dev, state);
30564 +               bt_data->rfkill->state = state;
30565 +
30566 +               if (machine_is_neo1973_gta01()) {
30567 +                       /* if we are powering up, assert reset, then power,
30568 +                        * then release reset */
30569 +                       if (on) {
30570 +                               neo1973_gpb_setpin(GTA01_GPIO_BT_EN, 0);
30571 +                               pcf50606_voltage_set(pcf50606_global,
30572 +                                                    PCF50606_REGULATOR_D1REG,
30573 +                                                    3100);
30574 +                       }
30575 +                       pcf50606_onoff_set(pcf50606_global,
30576 +                                          PCF50606_REGULATOR_D1REG, on);
30577 +                       neo1973_gpb_setpin(GTA01_GPIO_BT_EN, on);
30578 +               } else if (machine_is_neo1973_gta02())
30579 +                       __gta02_pm_bt_toggle_radio(dev, on);
30580 +
30581 +       } else if (!strcmp(attr->attr.name, "reset")) {
30582 +               /* reset is low-active, so we need to invert */
30583 +               if (machine_is_neo1973_gta01()) {
30584 +                       neo1973_gpb_setpin(GTA01_GPIO_BT_EN, on ? 0 : 1);
30585 +               } else if (machine_is_neo1973_gta02()) {
30586 +                       neo1973_gpb_setpin(GTA02_GPIO_BT_EN, on ? 0 : 1);
30587 +               }
30588 +       }
30589 +
30590 +       return count;
30591 +}
30592 +
30593 +static DEVICE_ATTR(power_on, 0644, bt_read, bt_write);
30594 +static DEVICE_ATTR(reset, 0644, bt_read, bt_write);
30595 +
30596 +#ifdef CONFIG_PM
30597 +static int gta01_bt_suspend(struct platform_device *pdev, pm_message_t state)
30598 +{
30599 +       struct gta01_pm_bt_data *bt_data = dev_get_drvdata(&pdev->dev);
30600 +
30601 +       dev_dbg(&pdev->dev, DRVMSG ": suspending\n");
30602 +
30603 +       if (machine_is_neo1973_gta02()) {
30604 +               bt_data->pre_resume_state =
30605 +                                         s3c2410_gpio_getpin(GTA02_GPIO_BT_EN);
30606 +               __gta02_pm_bt_toggle_radio(&pdev->dev, 0);
30607 +       }
30608 +
30609 +       return 0;
30610 +}
30611 +
30612 +static int gta01_bt_resume(struct platform_device *pdev)
30613 +{
30614 +       struct gta01_pm_bt_data *bt_data = dev_get_drvdata(&pdev->dev);
30615 +       dev_dbg(&pdev->dev, DRVMSG ": resuming\n");
30616 +
30617 +       if (machine_is_neo1973_gta02()) {
30618 +               __gta02_pm_bt_toggle_radio(&pdev->dev,
30619 +                                                    bt_data->pre_resume_state);
30620 +       }
30621 +
30622 +       return 0;
30623 +}
30624 +#else
30625 +#define gta01_bt_suspend       NULL
30626 +#define gta01_bt_resume                NULL
30627 +#endif
30628 +
30629 +static struct attribute *gta01_bt_sysfs_entries[] = {
30630 +       &dev_attr_power_on.attr,
30631 +       &dev_attr_reset.attr,
30632 +       NULL
30633 +};
30634 +
30635 +static struct attribute_group gta01_bt_attr_group = {
30636 +       .name   = NULL,
30637 +       .attrs  = gta01_bt_sysfs_entries,
30638 +};
30639 +
30640 +static int __init gta01_bt_probe(struct platform_device *pdev)
30641 +{
30642 +       struct rfkill *rfkill;
30643 +       struct regulator *regulator;
30644 +       struct gta01_pm_bt_data *bt_data;
30645 +       int ret;
30646 +
30647 +       dev_info(&pdev->dev, DRVMSG ": starting\n");
30648 +
30649 +       bt_data = kzalloc(sizeof(*bt_data), GFP_KERNEL);
30650 +       dev_set_drvdata(&pdev->dev, bt_data);
30651 +
30652 +       if (machine_is_neo1973_gta01()) {
30653 +               /* we make sure that the voltage is off */
30654 +               pcf50606_onoff_set(pcf50606_global,
30655 +                                  PCF50606_REGULATOR_D1REG, 0);
30656 +               /* we pull reset to low to make sure that the chip doesn't
30657 +                * drain power through the reset line */
30658 +               neo1973_gpb_setpin(GTA01_GPIO_BT_EN, 0);
30659 +       } else if (machine_is_neo1973_gta02()) {
30660 +               regulator = regulator_get(&pdev->dev, "BT_3V2");
30661 +               if (IS_ERR(regulator))
30662 +                       return -ENODEV;
30663 +
30664 +               bt_data->regulator = regulator;
30665 +
30666 +               /* this tests the true physical state of the regulator... */
30667 +               if (regulator_is_enabled(regulator)) {
30668 +                       /*
30669 +                        * but these only operate on the logical state of the
30670 +                        * regulator... so we need to logicaly "adopt" it on
30671 +                        * to turn it off
30672 +                        */
30673 +                       regulator_enable(regulator);
30674 +                       regulator_disable(regulator);
30675 +               }
30676 +
30677 +               /* we pull reset to low to make sure that the chip doesn't
30678 +                * drain power through the reset line */
30679 +               neo1973_gpb_setpin(GTA02_GPIO_BT_EN, 0);
30680 +       }
30681 +
30682 +       rfkill = rfkill_allocate(&pdev->dev, RFKILL_TYPE_BLUETOOTH);
30683 +
30684 +       rfkill->name = pdev->name;
30685 +       rfkill->data = &pdev->dev;
30686 +       rfkill->state = RFKILL_STATE_OFF;
30687 +       rfkill->toggle_radio = bt_rfkill_toggle_radio;
30688 +
30689 +       ret = rfkill_register(rfkill);
30690 +       if (ret) {
30691 +               dev_err(&pdev->dev, "Failed to register rfkill\n");
30692 +               return ret;
30693 +       }
30694 +
30695 +       bt_data->rfkill = rfkill;
30696 +
30697 +       return sysfs_create_group(&pdev->dev.kobj, &gta01_bt_attr_group);
30698 +}
30699 +
30700 +static int gta01_bt_remove(struct platform_device *pdev)
30701 +{
30702 +       struct gta01_pm_bt_data *bt_data = dev_get_drvdata(&pdev->dev);
30703 +       struct regulator *regulator;
30704 +
30705 +       sysfs_remove_group(&pdev->dev.kobj, &gta01_bt_attr_group);
30706 +
30707 +       if (bt_data->rfkill) {
30708 +               rfkill_unregister(bt_data->rfkill);
30709 +               rfkill_free(bt_data->rfkill);
30710 +       }
30711 +
30712 +       if (!bt_data || !bt_data->regulator)
30713 +               return 0;
30714 +
30715 +       regulator = bt_data->regulator;
30716 +
30717 +       /* Make sure regulator is disabled before calling regulator_put */
30718 +       if (regulator_is_enabled(regulator))
30719 +               regulator_disable(regulator);
30720 +
30721 +       regulator_put(regulator);
30722 +
30723 +       kfree(bt_data);
30724 +
30725 +       return 0;
30726 +}
30727 +
30728 +static struct platform_driver gta01_bt_driver = {
30729 +       .probe          = gta01_bt_probe,
30730 +       .remove         = gta01_bt_remove,
30731 +       .suspend        = gta01_bt_suspend,
30732 +       .resume         = gta01_bt_resume,
30733 +       .driver         = {
30734 +               .name           = "neo1973-pm-bt",
30735 +       },
30736 +};
30737 +
30738 +static int __devinit gta01_bt_init(void)
30739 +{
30740 +       return platform_driver_register(&gta01_bt_driver);
30741 +}
30742 +
30743 +static void gta01_bt_exit(void)
30744 +{
30745 +       platform_driver_unregister(&gta01_bt_driver);
30746 +}
30747 +
30748 +module_init(gta01_bt_init);
30749 +module_exit(gta01_bt_exit);
30750 +
30751 +MODULE_LICENSE("GPL");
30752 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
30753 +MODULE_DESCRIPTION(DRVMSG);
30754 --- /dev/null
30755 +++ b/arch/arm/plat-s3c24xx/neo1973_pm_gps.c
30756 @@ -0,0 +1,699 @@
30757 +/*
30758 + * GPS Power Management code for the FIC Neo1973 GSM Phone
30759 + *
30760 + * (C) 2007 by Openmoko Inc.
30761 + * Author: Harald Welte <laforge@openmoko.org>
30762 + * All rights reserved.
30763 + *
30764 + * This program is free software; you can redistribute it and/or modify
30765 + * it under the terms of the GNU General Public License version 2 as
30766 + * published by the Free Software Foundation
30767 + *
30768 + */
30769 +
30770 +#include <linux/module.h>
30771 +#include <linux/init.h>
30772 +#include <linux/kernel.h>
30773 +#include <linux/delay.h>
30774 +#include <linux/platform_device.h>
30775 +
30776 +#include <mach/hardware.h>
30777 +
30778 +#include <asm/mach-types.h>
30779 +
30780 +#include <asm/plat-s3c24xx/neo1973.h>
30781 +
30782 +/* For GTA01 */
30783 +#include <mach/gta01.h>
30784 +#include <linux/pcf50606.h>
30785 +
30786 +/* For GTA02 */
30787 +#include <mach/gta02.h>
30788 +
30789 +#include <linux/regulator/consumer.h>
30790 +
30791 +struct neo1973_pm_gps_data {
30792 +       int power_was_on;
30793 +       struct regulator *regulator;
30794 +};
30795 +
30796 +static struct neo1973_pm_gps_data neo1973_gps;
30797 +
30798 +int neo1973_pm_gps_is_on(void)
30799 +{
30800 +       return neo1973_gps.power_was_on;
30801 +}
30802 +EXPORT_SYMBOL_GPL(neo1973_pm_gps_is_on);
30803 +
30804 +#ifdef CONFIG_MACH_NEO1973_GTA01
30805 +
30806 +/* This is the 2.8V supply for the RTC crystal, the mail clock crystal and
30807 + * the input to VDD_RF */
30808 +static void gps_power_2v8_set(int on)
30809 +{
30810 +       switch (system_rev) {
30811 +       case GTA01v3_SYSTEM_REV:
30812 +       case GTA01v4_SYSTEM_REV:
30813 +               if (on)
30814 +                       pcf50606_voltage_set(pcf50606_global,
30815 +                                            PCF50606_REGULATOR_IOREG, 2800);
30816 +               pcf50606_onoff_set(pcf50606_global,
30817 +                                  PCF50606_REGULATOR_IOREG, on);
30818 +               break;
30819 +       case GTA01Bv2_SYSTEM_REV:
30820 +               s3c2410_gpio_setpin(GTA01_GPIO_GPS_EN_2V8, on);
30821 +                       break;
30822 +       case GTA01Bv3_SYSTEM_REV:
30823 +       case GTA01Bv4_SYSTEM_REV:
30824 +               break;
30825 +       }
30826 +}
30827 +
30828 +static int gps_power_2v8_get(void)
30829 +{
30830 +       int ret = 0;
30831 +
30832 +       switch (system_rev) {
30833 +       case GTA01v3_SYSTEM_REV:
30834 +       case GTA01v4_SYSTEM_REV:
30835 +               if (pcf50606_onoff_get(pcf50606_global,
30836 +                                       PCF50606_REGULATOR_IOREG) &&
30837 +                   pcf50606_voltage_get(pcf50606_global,
30838 +                                        PCF50606_REGULATOR_IOREG) == 2800)
30839 +                       ret = 1;
30840 +               break;
30841 +       case GTA01Bv2_SYSTEM_REV:
30842 +               if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_EN_2V8))
30843 +                       ret = 1;
30844 +               break;
30845 +       case GTA01Bv3_SYSTEM_REV:
30846 +       case GTA01Bv4_SYSTEM_REV:
30847 +               break;
30848 +       }
30849 +
30850 +       return ret;
30851 +}
30852 +
30853 +/* This is the 3V supply (AVDD) for the external RF frontend (LNA bias) */
30854 +static void gps_power_3v_set(int on)
30855 +{
30856 +       switch (system_rev) {
30857 +       case GTA01v3_SYSTEM_REV:
30858 +       case GTA01v4_SYSTEM_REV:
30859 +               if (on)
30860 +                       pcf50606_voltage_set(pcf50606_global,
30861 +                                            PCF50606_REGULATOR_D1REG, 3000);
30862 +               pcf50606_onoff_set(pcf50606_global,
30863 +                                  PCF50606_REGULATOR_D1REG, on);
30864 +               break;
30865 +       case GTA01Bv2_SYSTEM_REV:
30866 +       case GTA01Bv3_SYSTEM_REV:
30867 +       case GTA01Bv4_SYSTEM_REV:
30868 +               s3c2410_gpio_setpin(GTA01_GPIO_GPS_EN_3V, on);
30869 +               break;
30870 +       }
30871 +}
30872 +
30873 +static int gps_power_3v_get(void)
30874 +{
30875 +       int ret = 0;
30876 +
30877 +       switch (system_rev) {
30878 +       case GTA01v3_SYSTEM_REV:
30879 +       case GTA01v4_SYSTEM_REV:
30880 +               if (pcf50606_onoff_get(pcf50606_global,
30881 +                                      PCF50606_REGULATOR_D1REG) &&
30882 +                   pcf50606_voltage_get(pcf50606_global,
30883 +                                        PCF50606_REGULATOR_D1REG) == 3000)
30884 +                       ret = 1;
30885 +               break;
30886 +       case GTA01Bv2_SYSTEM_REV:
30887 +       case GTA01Bv3_SYSTEM_REV:
30888 +       case GTA01Bv4_SYSTEM_REV:
30889 +               if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_EN_3V))
30890 +                       ret = 1;
30891 +               break;
30892 +       }
30893 +
30894 +       return ret;
30895 +}
30896 +
30897 +/* This is the 3.3V supply for VDD_IO and VDD_LPREG input */
30898 +static void gps_power_3v3_set(int on)
30899 +{
30900 +       switch (system_rev) {
30901 +       case GTA01v3_SYSTEM_REV:
30902 +       case GTA01v4_SYSTEM_REV:
30903 +       case GTA01Bv2_SYSTEM_REV:
30904 +               if (on)
30905 +                       pcf50606_voltage_set(pcf50606_global,
30906 +                                            PCF50606_REGULATOR_DCD, 3300);
30907 +               pcf50606_onoff_set(pcf50606_global,
30908 +                                  PCF50606_REGULATOR_DCD, on);
30909 +               break;
30910 +       case GTA01Bv3_SYSTEM_REV:
30911 +       case GTA01Bv4_SYSTEM_REV:
30912 +               s3c2410_gpio_setpin(GTA01_GPIO_GPS_EN_3V3, on);
30913 +               break;
30914 +       }
30915 +}
30916 +
30917 +static int gps_power_3v3_get(void)
30918 +{
30919 +       int ret = 0;
30920 +
30921 +       switch (system_rev) {
30922 +       case GTA01v3_SYSTEM_REV:
30923 +       case GTA01v4_SYSTEM_REV:
30924 +       case GTA01Bv2_SYSTEM_REV:
30925 +               if (pcf50606_onoff_get(pcf50606_global,
30926 +                                      PCF50606_REGULATOR_DCD) &&
30927 +                   pcf50606_voltage_get(pcf50606_global,
30928 +                                        PCF50606_REGULATOR_DCD) == 3300)
30929 +                       ret = 1;
30930 +               break;
30931 +       case GTA01Bv3_SYSTEM_REV:
30932 +       case GTA01Bv4_SYSTEM_REV:
30933 +               if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_EN_3V3))
30934 +                       ret = 1;
30935 +               break;
30936 +       }
30937 +
30938 +       return ret;
30939 +}
30940 +
30941 +/* This is the 2.5V supply for VDD_PLLREG and VDD_COREREG input */
30942 +static void gps_power_2v5_set(int on)
30943 +{
30944 +       switch (system_rev) {
30945 +       case GTA01v3_SYSTEM_REV:
30946 +               /* This is CORE_1V8 and cannot be disabled */
30947 +               break;
30948 +       case GTA01v4_SYSTEM_REV:
30949 +       case GTA01Bv2_SYSTEM_REV:
30950 +       case GTA01Bv3_SYSTEM_REV:
30951 +       case GTA01Bv4_SYSTEM_REV:
30952 +               if (on)
30953 +                       pcf50606_voltage_set(pcf50606_global,
30954 +                                            PCF50606_REGULATOR_D2REG, 2500);
30955 +               pcf50606_onoff_set(pcf50606_global,
30956 +                                  PCF50606_REGULATOR_D2REG, on);
30957 +               break;
30958 +       }
30959 +}
30960 +
30961 +static int gps_power_2v5_get(void)
30962 +{
30963 +       int ret = 0;
30964 +
30965 +       switch (system_rev) {
30966 +       case GTA01v3_SYSTEM_REV:
30967 +               /* This is CORE_1V8 and cannot be disabled */
30968 +               ret = 1;
30969 +               break;
30970 +       case GTA01v4_SYSTEM_REV:
30971 +       case GTA01Bv2_SYSTEM_REV:
30972 +       case GTA01Bv3_SYSTEM_REV:
30973 +       case GTA01Bv4_SYSTEM_REV:
30974 +               if (pcf50606_onoff_get(pcf50606_global,
30975 +                                      PCF50606_REGULATOR_D2REG) &&
30976 +                   pcf50606_voltage_get(pcf50606_global,
30977 +                                        PCF50606_REGULATOR_D2REG) == 2500)
30978 +                       ret = 1;
30979 +               break;
30980 +       }
30981 +
30982 +       return ret;
30983 +}
30984 +
30985 +/* This is the 1.5V supply for VDD_CORE */
30986 +static void gps_power_1v5_set(int on)
30987 +{
30988 +       switch (system_rev) {
30989 +       case GTA01v3_SYSTEM_REV:
30990 +       case GTA01v4_SYSTEM_REV:
30991 +       case GTA01Bv2_SYSTEM_REV:
30992 +               /* This is switched via 2v5 */
30993 +               break;
30994 +       case GTA01Bv3_SYSTEM_REV:
30995 +       case GTA01Bv4_SYSTEM_REV:
30996 +               if (on)
30997 +                       pcf50606_voltage_set(pcf50606_global,
30998 +                                            PCF50606_REGULATOR_DCD, 1500);
30999 +               pcf50606_onoff_set(pcf50606_global,
31000 +                                  PCF50606_REGULATOR_DCD, on);
31001 +               break;
31002 +       }
31003 +}
31004 +
31005 +static int gps_power_1v5_get(void)
31006 +{
31007 +       int ret = 0;
31008 +
31009 +       switch (system_rev) {
31010 +       case GTA01v3_SYSTEM_REV:
31011 +       case GTA01v4_SYSTEM_REV:
31012 +       case GTA01Bv2_SYSTEM_REV:
31013 +               /* This is switched via 2v5 */
31014 +               ret = 1;
31015 +               break;
31016 +       case GTA01Bv3_SYSTEM_REV:
31017 +       case GTA01Bv4_SYSTEM_REV:
31018 +               if (pcf50606_onoff_get(pcf50606_global,
31019 +                                      PCF50606_REGULATOR_DCD) &&
31020 +                   pcf50606_voltage_get(pcf50606_global,
31021 +                                        PCF50606_REGULATOR_DCD) == 1500)
31022 +                       ret = 1;
31023 +               break;
31024 +       }
31025 +
31026 +       return ret;
31027 +}
31028 +#endif
31029 +
31030 +/* This is the POWERON pin */
31031 +static void gps_pwron_set(int on)
31032 +{
31033 +
31034 +       if (machine_is_neo1973_gta01())
31035 +               neo1973_gpb_setpin(GTA01_GPIO_GPS_PWRON, on);
31036 +
31037 +       if (machine_is_neo1973_gta02()) {
31038 +               if (on) {
31039 +                       /* return UART pins to being UART pins */
31040 +                       s3c2410_gpio_cfgpin(S3C2410_GPH4, S3C2410_GPH4_TXD1);
31041 +                       /* remove pulldown now it won't be floating any more */
31042 +                       s3c2410_gpio_pullup(S3C2410_GPH5, 0);
31043 +               } else {
31044 +                       /*
31045 +                        * take care not to power unpowered GPS from UART TX
31046 +                        * return them to GPIO and force low
31047 +                        */
31048 +                       s3c2410_gpio_cfgpin(S3C2410_GPH4, S3C2410_GPH4_OUTP);
31049 +                       s3c2410_gpio_setpin(S3C2410_GPH4, 0);
31050 +                       /* don't let RX from unpowered GPS float */
31051 +                       s3c2410_gpio_pullup(S3C2410_GPH5, 1);
31052 +               }
31053 +               if ((on) && (!neo1973_gps.power_was_on))
31054 +                       regulator_enable(neo1973_gps.regulator);
31055 +
31056 +               if ((!on) && (neo1973_gps.power_was_on))
31057 +                       regulator_disable(neo1973_gps.regulator);
31058 +       }
31059 +
31060 +       neo1973_gps.power_was_on = !!on;
31061 +}
31062 +
31063 +static int gps_pwron_get(void)
31064 +{
31065 +       if (machine_is_neo1973_gta01())
31066 +               return !!s3c2410_gpio_getpin(GTA01_GPIO_GPS_PWRON);
31067 +
31068 +       if (machine_is_neo1973_gta02())
31069 +               return regulator_is_enabled(neo1973_gps.regulator);
31070 +       return -1;
31071 +}
31072 +
31073 +
31074 +#ifdef CONFIG_MACH_NEO1973_GTA01
31075 +static void gps_rst_set(int on);
31076 +static int gps_rst_get(void);
31077 +#endif
31078 +
31079 +static ssize_t power_gps_read(struct device *dev,
31080 +                             struct device_attribute *attr, char *buf)
31081 +{
31082 +       int ret = 0;
31083 +
31084 +       if (!strcmp(attr->attr.name, "pwron"))
31085 +#ifdef CONFIG_MACH_NEO1973_GTA01
31086 +       {
31087 +#endif
31088 +               ret = gps_pwron_get();
31089 +#ifdef CONFIG_MACH_NEO1973_GTA01
31090 +       } else if (!strcmp(attr->attr.name, "power_avdd_3v")) {
31091 +               ret = gps_power_3v_get();
31092 +       } else if (!strcmp(attr->attr.name, "power_tcxo_2v8")) {
31093 +               ret = gps_power_2v8_get();
31094 +       } else if (!strcmp(attr->attr.name, "reset")) {
31095 +               ret = gps_rst_get();
31096 +       } else if (!strcmp(attr->attr.name, "power_lp_io_3v3")) {
31097 +               ret = gps_power_3v3_get();
31098 +       } else if (!strcmp(attr->attr.name, "power_pll_core_2v5")) {
31099 +               ret = gps_power_2v5_get();
31100 +       } else if (!strcmp(attr->attr.name, "power_core_1v5") ||
31101 +                  !strcmp(attr->attr.name, "power_vdd_core_1v5")) {
31102 +               ret = gps_power_1v5_get();
31103 +       }
31104 +#endif
31105 +       if (ret)
31106 +               return strlcpy(buf, "1\n", 3);
31107 +       else
31108 +               return strlcpy(buf, "0\n", 3);
31109 +}
31110 +
31111 +static ssize_t power_gps_write(struct device *dev,
31112 +                              struct device_attribute *attr, const char *buf,
31113 +                              size_t count)
31114 +{
31115 +       unsigned long on = simple_strtoul(buf, NULL, 10);
31116 +
31117 +       if (!strcmp(attr->attr.name, "pwron"))
31118 +#ifdef CONFIG_MACH_NEO1973_GTA01
31119 +{
31120 +#endif
31121 +               gps_pwron_set(on);
31122 +#ifdef CONFIG_MACH_NEO1973_GTA01
31123 +       } else if (!strcmp(attr->attr.name, "power_avdd_3v")) {
31124 +               gps_power_3v_set(on);
31125 +       } else if (!strcmp(attr->attr.name, "power_tcxo_2v8")) {
31126 +               gps_power_2v8_set(on);
31127 +       } else if (!strcmp(attr->attr.name, "reset")) {
31128 +               gps_rst_set(on);
31129 +       } else if (!strcmp(attr->attr.name, "power_lp_io_3v3")) {
31130 +               gps_power_3v3_set(on);
31131 +       } else if (!strcmp(attr->attr.name, "power_pll_core_2v5")) {
31132 +               gps_power_2v5_set(on);
31133 +       } else if (!strcmp(attr->attr.name, "power_core_1v5") ||
31134 +                  !strcmp(attr->attr.name, "power_vdd_core_1v5")) {
31135 +               gps_power_1v5_set(on);
31136 +       }
31137 +#endif
31138 +       return count;
31139 +}
31140 +
31141 +
31142 +#ifdef CONFIG_MACH_NEO1973_GTA01
31143 +
31144 +/* This is the nRESET pin */
31145 +static void gps_rst_set(int on)
31146 +{
31147 +       switch (system_rev) {
31148 +       case GTA01v3_SYSTEM_REV:
31149 +               pcf50606_gpo0_set(pcf50606_global, on);
31150 +               break;
31151 +       case GTA01v4_SYSTEM_REV:
31152 +       case GTA01Bv2_SYSTEM_REV:
31153 +       case GTA01Bv3_SYSTEM_REV:
31154 +       case GTA01Bv4_SYSTEM_REV:
31155 +               s3c2410_gpio_setpin(GTA01_GPIO_GPS_RESET, on);
31156 +               break;
31157 +       }
31158 +}
31159 +
31160 +static int gps_rst_get(void)
31161 +{
31162 +       switch (system_rev) {
31163 +       case GTA01v3_SYSTEM_REV:
31164 +               if (pcf50606_gpo0_get(pcf50606_global))
31165 +                       return 1;
31166 +               break;
31167 +       case GTA01v4_SYSTEM_REV:
31168 +       case GTA01Bv2_SYSTEM_REV:
31169 +       case GTA01Bv3_SYSTEM_REV:
31170 +       case GTA01Bv4_SYSTEM_REV:
31171 +               if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_RESET))
31172 +                       return 1;
31173 +               break;
31174 +       }
31175 +
31176 +       return 0;
31177 +}
31178 +
31179 +
31180 +static void gps_power_sequence_up(void)
31181 +{
31182 +       /* According to PMB2520 Data Sheet, Rev. 2006-06-05,
31183 +        * Chapter 4.2.2 */
31184 +
31185 +       /* nRESET must be asserted low */
31186 +       gps_rst_set(0);
31187 +
31188 +       /* POWERON must be de-asserted (low) */
31189 +       gps_pwron_set(0);
31190 +
31191 +       /* Apply VDD_IO and VDD_LPREG_IN */
31192 +       gps_power_3v3_set(1);
31193 +
31194 +       /* VDD_COREREG_IN, VDD_PLLREG_IN */
31195 +       gps_power_1v5_set(1);
31196 +       gps_power_2v5_set(1);
31197 +
31198 +       /* and VDD_RF may be applied */
31199 +       gps_power_2v8_set(1);
31200 +
31201 +       /* We need to enable AVDD, since in GTA01Bv3 it is
31202 +        * shared with RFREG_IN */
31203 +       gps_power_3v_set(1);
31204 +
31205 +       msleep(3);      /* Is 3ms enough? */
31206 +
31207 +       /* De-asert nRESET */
31208 +       gps_rst_set(1);
31209 +
31210 +       /* Switch power on */
31211 +       gps_pwron_set(1);
31212 +
31213 +}
31214 +
31215 +static void gps_power_sequence_down(void)
31216 +{
31217 +       /* According to PMB2520 Data Sheet, Rev. 2006-06-05,
31218 +        * Chapter 4.2.3.1 */
31219 +       gps_pwron_set(0);
31220 +
31221 +       /* Don't disable AVDD before PWRON is cleared, since
31222 +        * in GTA01Bv3, AVDD and RFREG_IN are shared */
31223 +       gps_power_3v_set(0);
31224 +
31225 +       /* Remove VDD_COREREG_IN, VDD_PLLREG_IN and VDD_REFREG_IN */
31226 +       gps_power_1v5_set(0);
31227 +       gps_power_2v5_set(0);
31228 +       gps_power_2v8_set(0);
31229 +
31230 +       /* Remove VDD_LPREG_IN and VDD_IO */
31231 +       gps_power_3v3_set(0);
31232 +}
31233 +
31234 +
31235 +static ssize_t power_sequence_read(struct device *dev,
31236 +                                  struct device_attribute *attr,
31237 +                                  char *buf)
31238 +{
31239 +       return strlcpy(buf, "power_up power_down\n", PAGE_SIZE);
31240 +}
31241 +
31242 +static ssize_t power_sequence_write(struct device *dev,
31243 +                                   struct device_attribute *attr,
31244 +                                   const char *buf, size_t count)
31245 +{
31246 +       dev_dbg(dev, "wrote: '%s'\n", buf);
31247 +
31248 +       if (!strncmp(buf, "power_up", 8))
31249 +               gps_power_sequence_up();
31250 +       else if (!strncmp(buf, "power_down", 10))
31251 +               gps_power_sequence_down();
31252 +       else
31253 +               return -EINVAL;
31254 +
31255 +       return count;
31256 +}
31257 +
31258 +static DEVICE_ATTR(power_tcxo_2v8, 0644, power_gps_read, power_gps_write);
31259 +static DEVICE_ATTR(power_avdd_3v, 0644, power_gps_read, power_gps_write);
31260 +static DEVICE_ATTR(reset, 0644, power_gps_read, power_gps_write);
31261 +static DEVICE_ATTR(power_lp_io_3v3, 0644, power_gps_read, power_gps_write);
31262 +static DEVICE_ATTR(power_pll_core_2v5, 0644, power_gps_read, power_gps_write);
31263 +static DEVICE_ATTR(power_core_1v5, 0644, power_gps_read, power_gps_write);
31264 +static DEVICE_ATTR(power_vdd_core_1v5, 0644, power_gps_read, power_gps_write);
31265 +static DEVICE_ATTR(power_sequence, 0644, power_sequence_read,
31266 +                  power_sequence_write);
31267 +#endif
31268 +
31269 +#ifdef CONFIG_PM
31270 +static int gta01_pm_gps_suspend(struct platform_device *pdev,
31271 +                               pm_message_t state)
31272 +{
31273 +#ifdef CONFIG_MACH_NEO1973_GTA01
31274 +       if (machine_is_neo1973_gta01())
31275 +               /* FIXME */
31276 +               gps_power_sequence_down();
31277 +#endif
31278 +       if (machine_is_neo1973_gta02())
31279 +               gps_pwron_set(0);
31280 +
31281 +       return 0;
31282 +}
31283 +
31284 +static int gta01_pm_gps_resume(struct platform_device *pdev)
31285 +{
31286 +#ifdef CONFIG_MACH_NEO1973_GTA01
31287 +       if (machine_is_neo1973_gta01())
31288 +               if (neo1973_gps.power_was_on)
31289 +                       gps_power_sequence_up();
31290 +#endif
31291 +       if (machine_is_neo1973_gta02())
31292 +               if (neo1973_gps.power_was_on)
31293 +                   gps_pwron_set(1);
31294 +
31295 +       return 0;
31296 +}
31297 +#else
31298 +#define gta01_pm_gps_suspend   NULL
31299 +#define gta01_pm_gps_resume    NULL
31300 +#endif
31301 +
31302 +static DEVICE_ATTR(pwron, 0644, power_gps_read, power_gps_write);
31303 +
31304 +
31305 +static struct attribute *gta01_gps_sysfs_entries[] = {
31306 +       &dev_attr_pwron.attr,
31307 +#ifdef CONFIG_MACH_NEO1973_GTA01
31308 +       &dev_attr_power_avdd_3v.attr,
31309 +       &dev_attr_reset.attr,
31310 +       &dev_attr_power_lp_io_3v3.attr,
31311 +       &dev_attr_power_pll_core_2v5.attr,
31312 +       &dev_attr_power_sequence.attr,
31313 +       NULL,   /* power_core_1v5 */
31314 +       NULL,   /* power_vdd_core_1v5 */
31315 +#endif
31316 +       NULL    /* terminating entry */
31317 +};
31318 +
31319 +static struct attribute_group gta01_gps_attr_group = {
31320 +       .name   = NULL,
31321 +       .attrs  = gta01_gps_sysfs_entries,
31322 +};
31323 +
31324 +static struct attribute *gta02_gps_sysfs_entries[] = {
31325 +       &dev_attr_pwron.attr,
31326 +       NULL
31327 +};
31328 +
31329 +static struct attribute_group gta02_gps_attr_group = {
31330 +       .name   = NULL,
31331 +       .attrs  = gta02_gps_sysfs_entries,
31332 +};
31333 +
31334 +static int __init gta01_pm_gps_probe(struct platform_device *pdev)
31335 +{
31336 +       if (machine_is_neo1973_gta01()) {
31337 +               s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_PWRON, S3C2410_GPIO_OUTPUT);
31338 +
31339 +               switch (system_rev) {
31340 +               case GTA01v3_SYSTEM_REV:
31341 +                       break;
31342 +               case GTA01v4_SYSTEM_REV:
31343 +                       s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_RESET, S3C2410_GPIO_OUTPUT);
31344 +                       break;
31345 +               case GTA01Bv3_SYSTEM_REV:
31346 +               case GTA01Bv4_SYSTEM_REV:
31347 +                       s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_EN_3V3, S3C2410_GPIO_OUTPUT);
31348 +                       /* fallthrough */
31349 +               case GTA01Bv2_SYSTEM_REV:
31350 +                       s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_EN_2V8, S3C2410_GPIO_OUTPUT);
31351 +                       s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_EN_3V, S3C2410_GPIO_OUTPUT);
31352 +                       s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_RESET, S3C2410_GPIO_OUTPUT);
31353 +                       break;
31354 +               default:
31355 +                       dev_warn(&pdev->dev, "Unknown GTA01 Revision 0x%x, "
31356 +                               "AGPS PM features not available!!!\n",
31357 +                               system_rev);
31358 +                       return -1;
31359 +                       break;
31360 +               }
31361 +
31362 +#ifdef CONFIG_MACH_NEO1973_GTA01
31363 +               gps_power_sequence_down();
31364 +
31365 +               switch (system_rev) {
31366 +               case GTA01v3_SYSTEM_REV:
31367 +               case GTA01v4_SYSTEM_REV:
31368 +               case GTA01Bv2_SYSTEM_REV:
31369 +                       gta01_gps_sysfs_entries[ARRAY_SIZE(gta01_gps_sysfs_entries)-3] =
31370 +                                               &dev_attr_power_tcxo_2v8.attr;
31371 +                       break;
31372 +               case GTA01Bv3_SYSTEM_REV:
31373 +               case GTA01Bv4_SYSTEM_REV:
31374 +                       gta01_gps_sysfs_entries[ARRAY_SIZE(gta01_gps_sysfs_entries)-3] =
31375 +                                               &dev_attr_power_core_1v5.attr;
31376 +                       gta01_gps_sysfs_entries[ARRAY_SIZE(gta01_gps_sysfs_entries)-2] =
31377 +                                               &dev_attr_power_vdd_core_1v5.attr;
31378 +                       break;
31379 +               }
31380 +#endif
31381 +               return sysfs_create_group(&pdev->dev.kobj, &gta01_gps_attr_group);
31382 +       }
31383 +
31384 +       if (machine_is_neo1973_gta02()) {
31385 +               switch (system_rev) {
31386 +               case GTA02v2_SYSTEM_REV:
31387 +               case GTA02v3_SYSTEM_REV:
31388 +               case GTA02v4_SYSTEM_REV:
31389 +               case GTA02v5_SYSTEM_REV:
31390 +               case GTA02v6_SYSTEM_REV:
31391 +                       neo1973_gps.regulator = regulator_get(
31392 +                                                       &pdev->dev, "RF_3V");
31393 +                       if (IS_ERR(neo1973_gps.regulator)) {
31394 +                               dev_err(&pdev->dev, "probe failed %d\n",
31395 +                                                   (int)neo1973_gps.regulator);
31396 +                               return (int)neo1973_gps.regulator;
31397 +                       }
31398 +
31399 +                       dev_info(&pdev->dev, "FIC Neo1973 GPS Power Management:"
31400 +                                "starting\n");
31401 +                       break;
31402 +               default:
31403 +                       dev_warn(&pdev->dev, "Unknown GTA02 Revision 0x%x, "
31404 +                               "AGPS PM features not available!!!\n",
31405 +                               system_rev);
31406 +                       return -1;
31407 +                       break;
31408 +               }
31409 +               return sysfs_create_group(&pdev->dev.kobj, &gta02_gps_attr_group);
31410 +       }
31411 +       return -1;
31412 +}
31413 +
31414 +static int gta01_pm_gps_remove(struct platform_device *pdev)
31415 +{
31416 +       if (machine_is_neo1973_gta01()) {
31417 +#ifdef CONFIG_MACH_NEO1973_GTA01
31418 +               gps_power_sequence_down();
31419 +#endif
31420 +               sysfs_remove_group(&pdev->dev.kobj, &gta01_gps_attr_group);
31421 +       }
31422 +
31423 +       if (machine_is_neo1973_gta02()) {
31424 +               regulator_put(neo1973_gps.regulator);
31425 +               sysfs_remove_group(&pdev->dev.kobj, &gta02_gps_attr_group);
31426 +       }
31427 +       return 0;
31428 +}
31429 +
31430 +static struct platform_driver gta01_pm_gps_driver = {
31431 +       .probe          = gta01_pm_gps_probe,
31432 +       .remove         = gta01_pm_gps_remove,
31433 +       .suspend        = gta01_pm_gps_suspend,
31434 +       .resume         = gta01_pm_gps_resume,
31435 +       .driver         = {
31436 +               .name           = "neo1973-pm-gps",
31437 +       },
31438 +};
31439 +
31440 +static int __devinit gta01_pm_gps_init(void)
31441 +{
31442 +       return platform_driver_register(&gta01_pm_gps_driver);
31443 +}
31444 +
31445 +static void gta01_pm_gps_exit(void)
31446 +{
31447 +       platform_driver_unregister(&gta01_pm_gps_driver);
31448 +}
31449 +
31450 +module_init(gta01_pm_gps_init);
31451 +module_exit(gta01_pm_gps_exit);
31452 +
31453 +MODULE_LICENSE("GPL");
31454 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
31455 +MODULE_DESCRIPTION("FIC Neo1973 GPS Power Management");
31456 --- /dev/null
31457 +++ b/arch/arm/plat-s3c24xx/neo1973_pm_gps.h
31458 @@ -0,0 +1 @@
31459 +extern int neo1973_pm_gps_is_on(void);
31460 --- /dev/null
31461 +++ b/arch/arm/plat-s3c24xx/neo1973_pm_gsm.c
31462 @@ -0,0 +1,360 @@
31463 +/*
31464 + * GSM Management code for the FIC Neo1973 GSM Phone
31465 + *
31466 + * (C) 2007 by Openmoko Inc.
31467 + * Author: Harald Welte <laforge@openmoko.org>
31468 + * All rights reserved.
31469 + *
31470 + * This program is free software; you can redistribute it and/or modify
31471 + * it under the terms of the GNU General Public License version 2 as
31472 + * published by the Free Software Foundation
31473 + *
31474 + */
31475 +
31476 +#include <linux/module.h>
31477 +#include <linux/init.h>
31478 +#include <linux/kernel.h>
31479 +#include <linux/platform_device.h>
31480 +#include <linux/console.h>
31481 +#include <linux/errno.h>
31482 +#include <linux/interrupt.h>
31483 +
31484 +#include <mach/gpio.h>
31485 +#include <asm/mach-types.h>
31486 +#include <mach/gta01.h>
31487 +#include <asm/plat-s3c24xx/neo1973.h>
31488 +#include <mach/s3c24xx-serial.h>
31489 +
31490 +#include <mach/hardware.h>
31491 +
31492 +/* For GTA02 */
31493 +#include <mach/gta02.h>
31494 +#include <linux/mfd/pcf50633/gpio.h>
31495 +#include <mach/regs-gpio.h>
31496 +#include <mach/regs-gpioj.h>
31497 +
31498 +int gta_gsm_interrupts;
31499 +EXPORT_SYMBOL(gta_gsm_interrupts);
31500 +
31501 +extern void s3c24xx_serial_console_set_silence(int);
31502 +
31503 +struct gta01pm_priv {
31504 +       int gpio_ngsm_en;
31505 +        int gpio_ndl_gsm;
31506 +
31507 +       struct console *con;
31508 +};
31509 +
31510 +static struct gta01pm_priv gta01_gsm;
31511 +
31512 +static struct console *find_s3c24xx_console(void)
31513 +{
31514 +       struct console *con;
31515 +
31516 +       acquire_console_sem();
31517 +
31518 +       for (con = console_drivers; con; con = con->next) {
31519 +               if (!strcmp(con->name, "ttySAC"))
31520 +                       break;
31521 +       }
31522 +
31523 +       release_console_sem();
31524 +
31525 +       return con;
31526 +}
31527 +
31528 +static ssize_t gsm_read(struct device *dev, struct device_attribute *attr,
31529 +                       char *buf)
31530 +{
31531 +       if (!strcmp(attr->attr.name, "power_on")) {
31532 +               if (s3c2410_gpio_getpin(GTA01_GPIO_MODEM_ON))
31533 +                       goto out_1;
31534 +       } else if (!strcmp(attr->attr.name, "reset")) {
31535 +               if (machine_is_neo1973_gta01() && s3c2410_gpio_getpin(GTA01_GPIO_MODEM_RST))
31536 +                       goto out_1;
31537 +               else if (machine_is_neo1973_gta02() && s3c2410_gpio_getpin(GTA02_GPIO_MODEM_RST))
31538 +                       goto out_1;
31539 +       } else if (!strcmp(attr->attr.name, "download")) {
31540 +               if (machine_is_neo1973_gta01()) {
31541 +                       if (s3c2410_gpio_getpin(GTA01_GPIO_MODEM_DNLOAD))
31542 +                               goto out_1;
31543 +               } else if (machine_is_neo1973_gta02()) {
31544 +                       if (!s3c2410_gpio_getpin(GTA02_GPIO_nDL_GSM))
31545 +                               goto out_1;
31546 +               }
31547 +       } else if (!strcmp(attr->attr.name, "flowcontrolled")) {
31548 +               if (s3c2410_gpio_getcfg(S3C2410_GPH1) == S3C2410_GPIO_OUTPUT)
31549 +                       goto out_1;
31550 +       }
31551 +
31552 +       return strlcpy(buf, "0\n", 3);
31553 +out_1:
31554 +       return strlcpy(buf, "1\n", 3);
31555 +}
31556 +
31557 +static ssize_t gsm_write(struct device *dev, struct device_attribute *attr,
31558 +                        const char *buf, size_t count)
31559 +{
31560 +       unsigned long on = simple_strtoul(buf, NULL, 10);
31561 +
31562 +       if (!strcmp(attr->attr.name, "power_on")) {
31563 +               if (on) {
31564 +                       if (gta01_gsm.con) {
31565 +                               dev_dbg(dev, "powering up GSM, thus "
31566 +                                        "disconnecting serial console\n");
31567 +
31568 +                               console_stop(gta01_gsm.con);
31569 +                               s3c24xx_serial_console_set_silence(1);
31570 +                       }
31571 +
31572 +                       if (gta01_gsm.gpio_ngsm_en)
31573 +                               s3c2410_gpio_setpin(gta01_gsm.gpio_ngsm_en, 0);
31574 +
31575 +                       if (machine_is_neo1973_gta02()) {
31576 +                               switch (system_rev) {
31577 +                               case GTA02v2_SYSTEM_REV:
31578 +                               case GTA02v3_SYSTEM_REV:
31579 +                               case GTA02v4_SYSTEM_REV:
31580 +                               case GTA02v5_SYSTEM_REV:
31581 +                               case GTA02v6_SYSTEM_REV:
31582 +                                       pcf50633_gpio_set(gta02_pcf_pdata.pcf,
31583 +                                                         PCF50633_GPIO2, 1);
31584 +                                       break;
31585 +                               }
31586 +                       }
31587 +
31588 +                       neo1973_gpb_setpin(GTA01_GPIO_MODEM_ON, 1);
31589 +               } else {
31590 +                       neo1973_gpb_setpin(GTA01_GPIO_MODEM_ON, 0);
31591 +
31592 +                       if (machine_is_neo1973_gta02()) {
31593 +                               switch (system_rev) {
31594 +                               case GTA02v2_SYSTEM_REV:
31595 +                               case GTA02v3_SYSTEM_REV:
31596 +                               case GTA02v4_SYSTEM_REV:
31597 +                               case GTA02v5_SYSTEM_REV:
31598 +                               case GTA02v6_SYSTEM_REV:
31599 +                                       pcf50633_gpio_set(gta02_pcf_pdata.pcf,
31600 +                                                         PCF50633_GPIO2, 0);
31601 +                                       break;
31602 +                               }
31603 +                       }
31604 +
31605 +                       if (gta01_gsm.gpio_ngsm_en)
31606 +                               s3c2410_gpio_setpin(gta01_gsm.gpio_ngsm_en, 1);
31607 +
31608 +                       if (gta01_gsm.con) {
31609 +                               s3c24xx_serial_console_set_silence(0);
31610 +                               console_start(gta01_gsm.con);
31611 +
31612 +                               dev_dbg(dev, "powered down GSM, thus enabling "
31613 +                                        "serial console\n");
31614 +                       }
31615 +               }
31616 +       } else if (!strcmp(attr->attr.name, "reset")) {
31617 +               if (machine_is_neo1973_gta01())
31618 +                       neo1973_gpb_setpin(GTA01_GPIO_MODEM_RST, on);
31619 +               else if (machine_is_neo1973_gta02())
31620 +                       neo1973_gpb_setpin(GTA02_GPIO_MODEM_RST, on);
31621 +       } else if (!strcmp(attr->attr.name, "download")) {
31622 +               if (machine_is_neo1973_gta01())
31623 +                       s3c2410_gpio_setpin(GTA01_GPIO_MODEM_DNLOAD, on);
31624 +
31625 +               if (machine_is_neo1973_gta02()) {
31626 +                       /*
31627 +                        * the keyboard / buttons driver requests and enables
31628 +                        * the JACK_INSERT IRQ.  We have to take care about
31629 +                        * not enabling and disabling the IRQ when it was
31630 +                        * already in that state or we get "unblanaced IRQ"
31631 +                        * kernel warnings and stack dumps.  So we use the
31632 +                        * copy of the ndl_gsm state to figure out if we should
31633 +                        * enable or disable the jack interrupt
31634 +                        */
31635 +                       if (on) {
31636 +                               if (gta01_gsm.gpio_ndl_gsm)
31637 +                                       disable_irq(gpio_to_irq(
31638 +                                                      GTA02_GPIO_JACK_INSERT));
31639 +                       } else {
31640 +                               if (!gta01_gsm.gpio_ndl_gsm)
31641 +                                       enable_irq(gpio_to_irq(
31642 +                                                      GTA02_GPIO_JACK_INSERT));
31643 +                       }
31644 +
31645 +                       gta01_gsm.gpio_ndl_gsm = !on;
31646 +                       s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, !on);
31647 +               }
31648 +       } else if (!strcmp(attr->attr.name, "flowcontrolled")) {
31649 +               if (on) {
31650 +                       gta_gsm_interrupts = 0;
31651 +                       s3c2410_gpio_setpin(S3C2410_GPH1, 1);
31652 +                       s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP);
31653 +               } else
31654 +                       s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_nRTS0);
31655 +       }
31656 +
31657 +       return count;
31658 +}
31659 +
31660 +static DEVICE_ATTR(power_on, 0644, gsm_read, gsm_write);
31661 +static DEVICE_ATTR(reset, 0644, gsm_read, gsm_write);
31662 +static DEVICE_ATTR(download, 0644, gsm_read, gsm_write);
31663 +static DEVICE_ATTR(flowcontrolled, 0644, gsm_read, gsm_write);
31664 +
31665 +#ifdef CONFIG_PM
31666 +
31667 +static int gta01_gsm_resume(struct platform_device *pdev);
31668 +static int gta01_gsm_suspend(struct platform_device *pdev, pm_message_t state)
31669 +{
31670 +       /* GPIO state is saved/restored by S3C2410 core GPIO driver, so we
31671 +        * don't need to do much here. */
31672 +
31673 +       /* If flowcontrol asserted, abort if GSM already interrupted */
31674 +       if (s3c2410_gpio_getcfg(S3C2410_GPH1) == S3C2410_GPIO_OUTPUT) {
31675 +               if (gta_gsm_interrupts)
31676 +                       goto busy;
31677 +       }
31678 +
31679 +       /* disable DL GSM to prevent jack_insert becoming 'floating' */
31680 +       if (machine_is_neo1973_gta02())
31681 +               s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, 1);
31682 +       return 0;
31683 +
31684 +busy:
31685 +       return -EBUSY;
31686 +}
31687 +
31688 +static int
31689 +gta01_gsm_suspend_late(struct platform_device *pdev, pm_message_t state)
31690 +{
31691 +       /* Last chance: abort if GSM already interrupted */
31692 +       if (s3c2410_gpio_getcfg(S3C2410_GPH1) == S3C2410_GPIO_OUTPUT) {
31693 +               if (gta_gsm_interrupts)
31694 +                       return -EBUSY;
31695 +       }
31696 +       return 0;
31697 +}
31698 +
31699 +static int gta01_gsm_resume(struct platform_device *pdev)
31700 +{
31701 +       /* GPIO state is saved/restored by S3C2410 core GPIO driver, so we
31702 +        * don't need to do much here. */
31703 +
31704 +       /* Make sure that the kernel console on the serial port is still
31705 +        * disabled. FIXME: resume ordering race with serial driver! */
31706 +       if (gta01_gsm.con && s3c2410_gpio_getpin(GTA01_GPIO_MODEM_ON))
31707 +               console_stop(gta01_gsm.con);
31708 +
31709 +       if (machine_is_neo1973_gta02())
31710 +               s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, gta01_gsm.gpio_ndl_gsm);
31711 +
31712 +       return 0;
31713 +}
31714 +#else
31715 +#define gta01_gsm_suspend      NULL
31716 +#define gta01_gsm_suspend_late NULL
31717 +#define gta01_gsm_resume       NULL
31718 +#endif /* CONFIG_PM */
31719 +
31720 +static struct attribute *gta01_gsm_sysfs_entries[] = {
31721 +       &dev_attr_power_on.attr,
31722 +       &dev_attr_reset.attr,
31723 +       &dev_attr_download.attr,
31724 +       &dev_attr_flowcontrolled.attr,
31725 +       NULL
31726 +};
31727 +
31728 +static struct attribute_group gta01_gsm_attr_group = {
31729 +       .name   = NULL,
31730 +       .attrs  = gta01_gsm_sysfs_entries,
31731 +};
31732 +
31733 +static int __init gta01_gsm_probe(struct platform_device *pdev)
31734 +{
31735 +       switch (system_rev) {
31736 +       case GTA01v3_SYSTEM_REV:
31737 +               gta01_gsm.gpio_ngsm_en = GTA01v3_GPIO_nGSM_EN;
31738 +               break;
31739 +       case GTA01v4_SYSTEM_REV:
31740 +               gta01_gsm.gpio_ngsm_en = 0;
31741 +               break;
31742 +       case GTA01Bv2_SYSTEM_REV:
31743 +       case GTA01Bv3_SYSTEM_REV:
31744 +       case GTA01Bv4_SYSTEM_REV:
31745 +               gta01_gsm.gpio_ngsm_en = GTA01Bv2_GPIO_nGSM_EN;
31746 +               s3c2410_gpio_setpin(GTA01v3_GPIO_nGSM_EN, 0);
31747 +               break;
31748 +       case GTA02v1_SYSTEM_REV:
31749 +       case GTA02v2_SYSTEM_REV:
31750 +       case GTA02v3_SYSTEM_REV:
31751 +       case GTA02v4_SYSTEM_REV:
31752 +       case GTA02v5_SYSTEM_REV:
31753 +       case GTA02v6_SYSTEM_REV:
31754 +               gta01_gsm.gpio_ngsm_en = 0;
31755 +               break;
31756 +       default:
31757 +               dev_warn(&pdev->dev, "Unknown Neo1973 Revision 0x%x, "
31758 +                        "some PM features not available!!!\n",
31759 +                        system_rev);
31760 +               break;
31761 +       }
31762 +
31763 +       switch (system_rev) {
31764 +       case GTA01v4_SYSTEM_REV:
31765 +       case GTA01Bv2_SYSTEM_REV:
31766 +               gta01_gsm_sysfs_entries[ARRAY_SIZE(gta01_gsm_sysfs_entries)-2] =
31767 +                                                       &dev_attr_download.attr;
31768 +               break;
31769 +       default:
31770 +               break;
31771 +       }
31772 +
31773 +       if (machine_is_neo1973_gta01()) {
31774 +               gta01_gsm.con = find_s3c24xx_console();
31775 +               if (!gta01_gsm.con)
31776 +                       dev_warn(&pdev->dev,
31777 +                                "cannot find S3C24xx console driver\n");
31778 +       } else
31779 +               gta01_gsm.con = NULL;
31780 +
31781 +       /* note that download initially disabled, and enforce that */
31782 +       gta01_gsm.gpio_ndl_gsm = 1;
31783 +       if (machine_is_neo1973_gta02())
31784 +               s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, 1);
31785 +
31786 +       return sysfs_create_group(&pdev->dev.kobj, &gta01_gsm_attr_group);
31787 +}
31788 +
31789 +static int gta01_gsm_remove(struct platform_device *pdev)
31790 +{
31791 +       sysfs_remove_group(&pdev->dev.kobj, &gta01_gsm_attr_group);
31792 +
31793 +       return 0;
31794 +}
31795 +
31796 +static struct platform_driver gta01_gsm_driver = {
31797 +       .probe          = gta01_gsm_probe,
31798 +       .remove         = gta01_gsm_remove,
31799 +       .suspend        = gta01_gsm_suspend,
31800 +       .suspend_late   = gta01_gsm_suspend_late,
31801 +       .resume         = gta01_gsm_resume,
31802 +       .driver         = {
31803 +               .name           = "neo1973-pm-gsm",
31804 +       },
31805 +};
31806 +
31807 +static int __devinit gta01_gsm_init(void)
31808 +{
31809 +       return platform_driver_register(&gta01_gsm_driver);
31810 +}
31811 +
31812 +static void gta01_gsm_exit(void)
31813 +{
31814 +       platform_driver_unregister(&gta01_gsm_driver);
31815 +}
31816 +
31817 +module_init(gta01_gsm_init);
31818 +module_exit(gta01_gsm_exit);
31819 +
31820 +MODULE_LICENSE("GPL");
31821 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
31822 +MODULE_DESCRIPTION("FIC Neo1973 GSM Power Management");
31823 --- /dev/null
31824 +++ b/arch/arm/plat-s3c24xx/neo1973_shadow.c
31825 @@ -0,0 +1,88 @@
31826 +/*
31827 + * include/asm-arm/plat-s3c24xx/neo1973.h
31828 + *
31829 + * Common utility code for GTA01 and GTA02
31830 + *
31831 + * Copyright (C) 2008 by Openmoko, Inc.
31832 + * Author: Holger Hans Peter Freyther <freyther@openmoko.org>
31833 + * All rights reserved.
31834 + *
31835 + * This program is free software; you can redistribute it and/or
31836 + * modify it under the terms of the GNU General Public License as
31837 + * published by the Free Software Foundation; either version 2 of
31838 + * the License, or (at your option) any later version.
31839 + *
31840 + * This program is distributed in the hope that it will be useful,
31841 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
31842 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
31843 + * GNU General Public License for more details.
31844 + *
31845 + * You should have received a copy of the GNU General Public License
31846 + * along with this program; if not, write to the Free Software
31847 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31848 + * MA 02111-1307 USA
31849 + *
31850 + */
31851 +
31852 +#include <linux/module.h>
31853 +#include <linux/io.h>
31854 +#include <linux/irq.h>
31855 +
31856 +#include <asm/gpio.h>
31857 +#include <mach/regs-gpio.h>
31858 +#include <asm/plat-s3c24xx/neo1973.h>
31859 +
31860 +/**
31861 + * Shadow GPIO bank B handling. For the LEDs we need to keep track of the state
31862 + * in software. The s3c2410_gpio_setpin must not be used for GPIOs on bank B
31863 + */
31864 +static unsigned long gpb_mask;
31865 +static unsigned long gpb_state;
31866 +
31867 +void neo1973_gpb_add_shadow_gpio(unsigned int gpio)
31868 +{
31869 +       unsigned long offset = S3C2410_GPIO_OFFSET(gpio);
31870 +       unsigned long flags;
31871 +
31872 +       local_irq_save(flags);
31873 +       gpb_mask |= 1L << offset;
31874 +       local_irq_restore(flags);
31875 +}
31876 +EXPORT_SYMBOL(neo1973_gpb_add_shadow_gpio);
31877 +
31878 +static void set_shadow_gpio(unsigned long offset, unsigned int value)
31879 +{
31880 +       unsigned long state = value != 0;
31881 +
31882 +       gpb_state &= ~(1L << offset);
31883 +       gpb_state |= state << offset;
31884 +}
31885 +
31886 +void neo1973_gpb_setpin(unsigned int pin, unsigned to)
31887 +{
31888 +       void __iomem *base = S3C24XX_GPIO_BASE(S3C2410_GPB0);
31889 +       unsigned long offset = S3C2410_GPIO_OFFSET(pin);
31890 +       unsigned long flags;
31891 +       unsigned long dat;
31892 +
31893 +       BUG_ON(base != S3C24XX_GPIO_BASE(pin));
31894 +
31895 +       local_irq_save(flags);
31896 +       dat = __raw_readl(base + 0x04);
31897 +
31898 +       /* Add the shadow values */
31899 +       dat &= ~gpb_mask;
31900 +       dat |= gpb_state;
31901 +
31902 +       /* Do the operation like s3c2410_gpio_setpin */
31903 +       dat &= ~(1L << offset);
31904 +       dat |= to << offset;
31905 +
31906 +       /* Update the shadow state */
31907 +       if ((1L << offset) & gpb_mask)
31908 +               set_shadow_gpio(offset, to);
31909 +
31910 +       __raw_writel(dat, base + 0x04);
31911 +       local_irq_restore(flags);
31912 +}
31913 +EXPORT_SYMBOL(neo1973_gpb_setpin);
31914 --- a/arch/arm/plat-s3c24xx/pm.c
31915 +++ b/arch/arm/plat-s3c24xx/pm.c
31916 @@ -31,14 +31,9 @@
31917  #include <linux/errno.h>
31918  #include <linux/time.h>
31919  #include <linux/interrupt.h>
31920 -#include <linux/crc32.h>
31921 -#include <linux/ioport.h>
31922 -#include <linux/delay.h>
31923  #include <linux/serial_core.h>
31924  #include <linux/io.h>
31925 -
31926 -#include <asm/cacheflush.h>
31927 -#include <mach/hardware.h>
31928 +#include <linux/regulator/machine.h>
31929
31930  #include <plat/regs-serial.h>
31931  #include <mach/regs-clock.h>
31932 @@ -50,10 +45,6 @@
31933
31934  #include <plat/pm.h>
31935
31936 -/* for external use */
31937 -
31938 -unsigned long s3c_pm_flags;
31939 -
31940  #define PFX "s3c24xx-pm: "
31941
31942  static struct sleep_save core_save[] = {
31943 @@ -76,371 +67,26 @@ static struct sleep_save core_save[] = {
31944         SAVE_ITEM(S3C2410_BANKCON4),
31945         SAVE_ITEM(S3C2410_BANKCON5),
31946
31947 +#ifndef CONFIG_CPU_FREQ
31948         SAVE_ITEM(S3C2410_CLKDIVN),
31949         SAVE_ITEM(S3C2410_MPLLCON),
31950 +       SAVE_ITEM(S3C2410_REFRESH),
31951 +#endif
31952         SAVE_ITEM(S3C2410_UPLLCON),
31953         SAVE_ITEM(S3C2410_CLKSLOW),
31954 -       SAVE_ITEM(S3C2410_REFRESH),
31955 -};
31956 -
31957 -static struct gpio_sleep {
31958 -       void __iomem    *base;
31959 -       unsigned int     gpcon;
31960 -       unsigned int     gpdat;
31961 -       unsigned int     gpup;
31962 -} gpio_save[] = {
31963 -       [0] = {
31964 -               .base   = S3C2410_GPACON,
31965 -       },
31966 -       [1] = {
31967 -               .base   = S3C2410_GPBCON,
31968 -       },
31969 -       [2] = {
31970 -               .base   = S3C2410_GPCCON,
31971 -       },
31972 -       [3] = {
31973 -               .base   = S3C2410_GPDCON,
31974 -       },
31975 -       [4] = {
31976 -               .base   = S3C2410_GPECON,
31977 -       },
31978 -       [5] = {
31979 -               .base   = S3C2410_GPFCON,
31980 -       },
31981 -       [6] = {
31982 -               .base   = S3C2410_GPGCON,
31983 -       },
31984 -       [7] = {
31985 -               .base   = S3C2410_GPHCON,
31986 -       },
31987  };
31988
31989  static struct sleep_save misc_save[] = {
31990         SAVE_ITEM(S3C2410_DCLKCON),
31991  };
31992
31993 -#ifdef CONFIG_S3C2410_PM_DEBUG
31994 -
31995 -#define SAVE_UART(va) \
31996 -       SAVE_ITEM((va) + S3C2410_ULCON), \
31997 -       SAVE_ITEM((va) + S3C2410_UCON), \
31998 -       SAVE_ITEM((va) + S3C2410_UFCON), \
31999 -       SAVE_ITEM((va) + S3C2410_UMCON), \
32000 -       SAVE_ITEM((va) + S3C2410_UBRDIV)
32001 -
32002 -static struct sleep_save uart_save[] = {
32003 -       SAVE_UART(S3C24XX_VA_UART0),
32004 -       SAVE_UART(S3C24XX_VA_UART1),
32005 -#ifndef CONFIG_CPU_S3C2400
32006 -       SAVE_UART(S3C24XX_VA_UART2),
32007 -#endif
32008 -};
32009 -
32010 -/* debug
32011 - *
32012 - * we send the debug to printascii() to allow it to be seen if the
32013 - * system never wakes up from the sleep
32014 -*/
32015 -
32016 -extern void printascii(const char *);
32017 -
32018 -void pm_dbg(const char *fmt, ...)
32019 -{
32020 -       va_list va;
32021 -       char buff[256];
32022 -
32023 -       va_start(va, fmt);
32024 -       vsprintf(buff, fmt, va);
32025 -       va_end(va);
32026 -
32027 -       printascii(buff);
32028 -}
32029 -
32030 -static void s3c2410_pm_debug_init(void)
32031 -{
32032 -       unsigned long tmp = __raw_readl(S3C2410_CLKCON);
32033 -
32034 -       /* re-start uart clocks */
32035 -       tmp |= S3C2410_CLKCON_UART0;
32036 -       tmp |= S3C2410_CLKCON_UART1;
32037 -       tmp |= S3C2410_CLKCON_UART2;
32038 -
32039 -       __raw_writel(tmp, S3C2410_CLKCON);
32040 -       udelay(10);
32041 -}
32042 -
32043 -#define DBG(fmt...) pm_dbg(fmt)
32044 -#else
32045 -#define DBG(fmt...) printk(KERN_DEBUG fmt)
32046 -
32047 -#define s3c2410_pm_debug_init() do { } while(0)
32048 -
32049 -static struct sleep_save uart_save[] = {};
32050 -#endif
32051 -
32052 -#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
32053 -
32054 -/* suspend checking code...
32055 - *
32056 - * this next area does a set of crc checks over all the installed
32057 - * memory, so the system can verify if the resume was ok.
32058 - *
32059 - * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
32060 - * increasing it will mean that the area corrupted will be less easy to spot,
32061 - * and reducing the size will cause the CRC save area to grow
32062 -*/
32063 -
32064 -#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
32065 -
32066 -static u32 crc_size;   /* size needed for the crc block */
32067 -static u32 *crcs;      /* allocated over suspend/resume */
32068 -
32069 -typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
32070 -
32071 -/* s3c2410_pm_run_res
32072 - *
32073 - * go thorugh the given resource list, and look for system ram
32074 -*/
32075 -
32076 -static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
32077 -{
32078 -       while (ptr != NULL) {
32079 -               if (ptr->child != NULL)
32080 -                       s3c2410_pm_run_res(ptr->child, fn, arg);
32081 -
32082 -               if ((ptr->flags & IORESOURCE_MEM) &&
32083 -                   strcmp(ptr->name, "System RAM") == 0) {
32084 -                       DBG("Found system RAM at %08lx..%08lx\n",
32085 -                           ptr->start, ptr->end);
32086 -                       arg = (fn)(ptr, arg);
32087 -               }
32088 -
32089 -               ptr = ptr->sibling;
32090 -       }
32091 -}
32092 -
32093 -static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
32094 -{
32095 -       s3c2410_pm_run_res(&iomem_resource, fn, arg);
32096 -}
32097 -
32098 -static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
32099 -{
32100 -       u32 size = (u32)(res->end - res->start)+1;
32101 -
32102 -       size += CHECK_CHUNKSIZE-1;
32103 -       size /= CHECK_CHUNKSIZE;
32104 -
32105 -       DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
32106 -
32107 -       *val += size * sizeof(u32);
32108 -       return val;
32109 -}
32110 -
32111 -/* s3c2410_pm_prepare_check
32112 - *
32113 - * prepare the necessary information for creating the CRCs. This
32114 - * must be done before the final save, as it will require memory
32115 - * allocating, and thus touching bits of the kernel we do not
32116 - * know about.
32117 -*/
32118 -
32119 -static void s3c2410_pm_check_prepare(void)
32120 -{
32121 -       crc_size = 0;
32122 -
32123 -       s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
32124 -
32125 -       DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
32126 -
32127 -       crcs = kmalloc(crc_size+4, GFP_KERNEL);
32128 -       if (crcs == NULL)
32129 -               printk(KERN_ERR "Cannot allocated CRC save area\n");
32130 -}
32131 -
32132 -static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
32133 -{
32134 -       unsigned long addr, left;
32135 -
32136 -       for (addr = res->start; addr < res->end;
32137 -            addr += CHECK_CHUNKSIZE) {
32138 -               left = res->end - addr;
32139 -
32140 -               if (left > CHECK_CHUNKSIZE)
32141 -                       left = CHECK_CHUNKSIZE;
32142 -
32143 -               *val = crc32_le(~0, phys_to_virt(addr), left);
32144 -               val++;
32145 -       }
32146 -
32147 -       return val;
32148 -}
32149 -
32150 -/* s3c2410_pm_check_store
32151 - *
32152 - * compute the CRC values for the memory blocks before the final
32153 - * sleep.
32154 -*/
32155 -
32156 -static void s3c2410_pm_check_store(void)
32157 -{
32158 -       if (crcs != NULL)
32159 -               s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
32160 -}
32161 -
32162 -/* in_region
32163 - *
32164 - * return TRUE if the area defined by ptr..ptr+size contatins the
32165 - * what..what+whatsz
32166 -*/
32167 -
32168 -static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
32169 -{
32170 -       if ((what+whatsz) < ptr)
32171 -               return 0;
32172 -
32173 -       if (what > (ptr+size))
32174 -               return 0;
32175 -
32176 -       return 1;
32177 -}
32178 -
32179 -static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
32180 -{
32181 -       void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
32182 -       unsigned long addr;
32183 -       unsigned long left;
32184 -       void *ptr;
32185 -       u32 calc;
32186 -
32187 -       for (addr = res->start; addr < res->end;
32188 -            addr += CHECK_CHUNKSIZE) {
32189 -               left = res->end - addr;
32190 -
32191 -               if (left > CHECK_CHUNKSIZE)
32192 -                       left = CHECK_CHUNKSIZE;
32193 -
32194 -               ptr = phys_to_virt(addr);
32195 -
32196 -               if (in_region(ptr, left, crcs, crc_size)) {
32197 -                       DBG("skipping %08lx, has crc block in\n", addr);
32198 -                       goto skip_check;
32199 -               }
32200 -
32201 -               if (in_region(ptr, left, save_at, 32*4 )) {
32202 -                       DBG("skipping %08lx, has save block in\n", addr);
32203 -                       goto skip_check;
32204 -               }
32205 -
32206 -               /* calculate and check the checksum */
32207 -
32208 -               calc = crc32_le(~0, ptr, left);
32209 -               if (calc != *val) {
32210 -                       printk(KERN_ERR PFX "Restore CRC error at "
32211 -                              "%08lx (%08x vs %08x)\n", addr, calc, *val);
32212 -
32213 -                       DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
32214 -                           addr, calc, *val);
32215 -               }
32216 -
32217 -       skip_check:
32218 -               val++;
32219 -       }
32220 -
32221 -       return val;
32222 -}
32223 -
32224 -/* s3c2410_pm_check_restore
32225 - *
32226 - * check the CRCs after the restore event and free the memory used
32227 - * to hold them
32228 -*/
32229 -
32230 -static void s3c2410_pm_check_restore(void)
32231 -{
32232 -       if (crcs != NULL) {
32233 -               s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
32234 -               kfree(crcs);
32235 -               crcs = NULL;
32236 -       }
32237 -}
32238 -
32239 -#else
32240 -
32241 -#define s3c2410_pm_check_prepare() do { } while(0)
32242 -#define s3c2410_pm_check_restore() do { } while(0)
32243 -#define s3c2410_pm_check_store()   do { } while(0)
32244 -#endif
32245 -
32246 -/* helper functions to save and restore register state */
32247 -
32248 -void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
32249 -{
32250 -       for (; count > 0; count--, ptr++) {
32251 -               ptr->val = __raw_readl(ptr->reg);
32252 -               DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
32253 -       }
32254 -}
32255 -
32256 -/* s3c2410_pm_do_restore
32257 - *
32258 - * restore the system from the given list of saved registers
32259 - *
32260 - * Note, we do not use DBG() in here, as the system may not have
32261 - * restore the UARTs state yet
32262 -*/
32263 -
32264 -void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
32265 -{
32266 -       for (; count > 0; count--, ptr++) {
32267 -               printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
32268 -                      ptr->reg, ptr->val, __raw_readl(ptr->reg));
32269 -
32270 -               __raw_writel(ptr->val, ptr->reg);
32271 -       }
32272 -}
32273 -
32274 -/* s3c2410_pm_do_restore_core
32275 - *
32276 - * similar to s3c2410_pm_do_restore_core
32277 - *
32278 - * WARNING: Do not put any debug in here that may effect memory or use
32279 - * peripherals, as things may be changing!
32280 -*/
32281 -
32282 -static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
32283 -{
32284 -       for (; count > 0; count--, ptr++) {
32285 -               __raw_writel(ptr->val, ptr->reg);
32286 -       }
32287 -}
32288 -
32289 -/* s3c2410_pm_show_resume_irqs
32290 - *
32291 - * print any IRQs asserted at resume time (ie, we woke from)
32292 -*/
32293 -
32294 -static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
32295 -                                       unsigned long mask)
32296 -{
32297 -       int i;
32298 -
32299 -       which &= ~mask;
32300 -
32301 -       for (i = 0; i <= 31; i++) {
32302 -               if ((which) & (1L<<i)) {
32303 -                       DBG("IRQ %d asserted at resume\n", start+i);
32304 -               }
32305 -       }
32306 -}
32307 -
32308 -/* s3c2410_pm_check_resume_pin
32309 +/* s3c_pm_check_resume_pin
32310   *
32311   * check to see if the pin is configured correctly for sleep mode, and
32312   * make any necessary adjustments if it is not
32313  */
32314
32315 -static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
32316 +static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
32317  {
32318         unsigned long irqstate;
32319         unsigned long pinstate;
32320 @@ -455,21 +101,21 @@ static void s3c2410_pm_check_resume_pin(
32321
32322         if (!irqstate) {
32323                 if (pinstate == S3C2410_GPIO_IRQ)
32324 -                       DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
32325 +                       S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
32326         } else {
32327                 if (pinstate == S3C2410_GPIO_IRQ) {
32328 -                       DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
32329 +                       S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
32330                         s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
32331                 }
32332         }
32333  }
32334
32335 -/* s3c2410_pm_configure_extint
32336 +/* s3c_pm_configure_extint
32337   *
32338   * configure all external interrupt pins
32339  */
32340
32341 -static void s3c2410_pm_configure_extint(void)
32342 +void s3c_pm_configure_extint(void)
32343  {
32344         int pin;
32345
32346 @@ -479,336 +125,24 @@ static void s3c2410_pm_configure_extint(
32347         */
32348
32349         for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
32350 -               s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
32351 +               s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
32352         }
32353
32354         for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
32355 -               s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
32356 +               s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
32357         }
32358  }
32359
32360 -/* offsets for CON/DAT/UP registers */
32361 -
32362 -#define OFFS_CON       (S3C2410_GPACON - S3C2410_GPACON)
32363 -#define OFFS_DAT       (S3C2410_GPADAT - S3C2410_GPACON)
32364 -#define OFFS_UP                (S3C2410_GPBUP  - S3C2410_GPBCON)
32365 -
32366 -/* s3c2410_pm_save_gpios()
32367 - *
32368 - * Save the state of the GPIOs
32369 - */
32370
32371 -static void s3c2410_pm_save_gpios(void)
32372 +void s3c_pm_restore_core(void)
32373  {
32374 -       struct gpio_sleep *gps = gpio_save;
32375 -       unsigned int gpio;
32376 -
32377 -       for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
32378 -               void __iomem *base = gps->base;
32379 -
32380 -               gps->gpcon = __raw_readl(base + OFFS_CON);
32381 -               gps->gpdat = __raw_readl(base + OFFS_DAT);
32382 -
32383 -               if (gpio > 0)
32384 -                       gps->gpup = __raw_readl(base + OFFS_UP);
32385 -
32386 -       }
32387 -}
32388 -
32389 -/* Test whether the given masked+shifted bits of an GPIO configuration
32390 - * are one of the SFN (special function) modes. */
32391 -
32392 -static inline int is_sfn(unsigned long con)
32393 -{
32394 -       return (con == 2 || con == 3);
32395 -}
32396 -
32397 -/* Test if the given masked+shifted GPIO configuration is an input */
32398 -
32399 -static inline int is_in(unsigned long con)
32400 -{
32401 -       return con == 0;
32402 -}
32403 -
32404 -/* Test if the given masked+shifted GPIO configuration is an output */
32405 -
32406 -static inline int is_out(unsigned long con)
32407 -{
32408 -       return con == 1;
32409 +       s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
32410 +       s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
32411  }
32412
32413 -/* s3c2410_pm_restore_gpio()
32414 - *
32415 - * Restore one of the GPIO banks that was saved during suspend. This is
32416 - * not as simple as once thought, due to the possibility of glitches
32417 - * from the order that the CON and DAT registers are set in.
32418 - *
32419 - * The three states the pin can be are {IN,OUT,SFN} which gives us 9
32420 - * combinations of changes to check. Three of these, if the pin stays
32421 - * in the same configuration can be discounted. This leaves us with
32422 - * the following:
32423 - *
32424 - * { IN => OUT }  Change DAT first
32425 - * { IN => SFN }  Change CON first
32426 - * { OUT => SFN } Change CON first, so new data will not glitch
32427 - * { OUT => IN }  Change CON first, so new data will not glitch
32428 - * { SFN => IN }  Change CON first
32429 - * { SFN => OUT } Change DAT first, so new data will not glitch [1]
32430 - *
32431 - * We do not currently deal with the UP registers as these control
32432 - * weak resistors, so a small delay in change should not need to bring
32433 - * these into the calculations.
32434 - *
32435 - * [1] this assumes that writing to a pin DAT whilst in SFN will set the
32436 - *     state for when it is next output.
32437 - */
32438 -
32439 -static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
32440 +void s3c_pm_save_core(void)
32441  {
32442 -       void __iomem *base = gps->base;
32443 -       unsigned long gps_gpcon = gps->gpcon;
32444 -       unsigned long gps_gpdat = gps->gpdat;
32445 -       unsigned long old_gpcon;
32446 -       unsigned long old_gpdat;
32447 -       unsigned long old_gpup = 0x0;
32448 -       unsigned long gpcon;
32449 -       int nr;
32450 -
32451 -       old_gpcon = __raw_readl(base + OFFS_CON);
32452 -       old_gpdat = __raw_readl(base + OFFS_DAT);
32453 -
32454 -       if (base == S3C2410_GPACON) {
32455 -               /* GPACON only has one bit per control / data and no PULLUPs.
32456 -                * GPACON[x] = 0 => Output, 1 => SFN */
32457 -
32458 -               /* first set all SFN bits to SFN */
32459 -
32460 -               gpcon = old_gpcon | gps->gpcon;
32461 -               __raw_writel(gpcon, base + OFFS_CON);
32462 -
32463 -               /* now set all the other bits */
32464 -
32465 -               __raw_writel(gps_gpdat, base + OFFS_DAT);
32466 -               __raw_writel(gps_gpcon, base + OFFS_CON);
32467 -       } else {
32468 -               unsigned long old, new, mask;
32469 -               unsigned long change_mask = 0x0;
32470 -
32471 -               old_gpup = __raw_readl(base + OFFS_UP);
32472 -
32473 -               /* Create a change_mask of all the items that need to have
32474 -                * their CON value changed before their DAT value, so that
32475 -                * we minimise the work between the two settings.
32476 -                */
32477 -
32478 -               for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
32479 -                       old = (old_gpcon & mask) >> nr;
32480 -                       new = (gps_gpcon & mask) >> nr;
32481 -
32482 -                       /* If there is no change, then skip */
32483 -
32484 -                       if (old == new)
32485 -                               continue;
32486 -
32487 -                       /* If both are special function, then skip */
32488 -
32489 -                       if (is_sfn(old) && is_sfn(new))
32490 -                               continue;
32491 -
32492 -                       /* Change is IN => OUT, do not change now */
32493 -
32494 -                       if (is_in(old) && is_out(new))
32495 -                               continue;
32496 -
32497 -                       /* Change is SFN => OUT, do not change now */
32498 -
32499 -                       if (is_sfn(old) && is_out(new))
32500 -                               continue;
32501 -
32502 -                       /* We should now be at the case of IN=>SFN,
32503 -                        * OUT=>SFN, OUT=>IN, SFN=>IN. */
32504 -
32505 -                       change_mask |= mask;
32506 -               }
32507 -
32508 -               /* Write the new CON settings */
32509 -
32510 -               gpcon = old_gpcon & ~change_mask;
32511 -               gpcon |= gps_gpcon & change_mask;
32512 -
32513 -               __raw_writel(gpcon, base + OFFS_CON);
32514 -
32515 -               /* Now change any items that require DAT,CON */
32516 -
32517 -               __raw_writel(gps_gpdat, base + OFFS_DAT);
32518 -               __raw_writel(gps_gpcon, base + OFFS_CON);
32519 -               __raw_writel(gps->gpup, base + OFFS_UP);
32520 -       }
32521 -
32522 -       DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
32523 -           index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
32524 +       s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
32525 +       s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
32526  }
32527
32528 -
32529 -/** s3c2410_pm_restore_gpios()
32530 - *
32531 - * Restore the state of the GPIOs
32532 - */
32533 -
32534 -static void s3c2410_pm_restore_gpios(void)
32535 -{
32536 -       struct gpio_sleep *gps = gpio_save;
32537 -       int gpio;
32538 -
32539 -       for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
32540 -               s3c2410_pm_restore_gpio(gpio, gps);
32541 -       }
32542 -}
32543 -
32544 -void (*pm_cpu_prep)(void);
32545 -void (*pm_cpu_sleep)(void);
32546 -
32547 -#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
32548 -
32549 -/* s3c2410_pm_enter
32550 - *
32551 - * central control for sleep/resume process
32552 -*/
32553 -
32554 -static int s3c2410_pm_enter(suspend_state_t state)
32555 -{
32556 -       unsigned long regs_save[16];
32557 -
32558 -       /* ensure the debug is initialised (if enabled) */
32559 -
32560 -       s3c2410_pm_debug_init();
32561 -
32562 -       DBG("s3c2410_pm_enter(%d)\n", state);
32563 -
32564 -       if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
32565 -               printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
32566 -               return -EINVAL;
32567 -       }
32568 -
32569 -       /* check if we have anything to wake-up with... bad things seem
32570 -        * to happen if you suspend with no wakeup (system will often
32571 -        * require a full power-cycle)
32572 -       */
32573 -
32574 -       if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
32575 -           !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
32576 -               printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
32577 -               printk(KERN_ERR PFX "Aborting sleep\n");
32578 -               return -EINVAL;
32579 -       }
32580 -
32581 -       /* prepare check area if configured */
32582 -
32583 -       s3c2410_pm_check_prepare();
32584 -
32585 -       /* store the physical address of the register recovery block */
32586 -
32587 -       s3c2410_sleep_save_phys = virt_to_phys(regs_save);
32588 -
32589 -       DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
32590 -
32591 -       /* save all necessary core registers not covered by the drivers */
32592 -
32593 -       s3c2410_pm_save_gpios();
32594 -       s3c2410_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
32595 -       s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
32596 -       s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
32597 -
32598 -       /* set the irq configuration for wake */
32599 -
32600 -       s3c2410_pm_configure_extint();
32601 -
32602 -       DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
32603 -           s3c_irqwake_intmask, s3c_irqwake_eintmask);
32604 -
32605 -       __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
32606 -       __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
32607 -
32608 -       /* ack any outstanding external interrupts before we go to sleep */
32609 -
32610 -       __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
32611 -       __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
32612 -       __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
32613 -
32614 -       /* call cpu specific preparation */
32615 -
32616 -       pm_cpu_prep();
32617 -
32618 -       /* flush cache back to ram */
32619 -
32620 -       flush_cache_all();
32621 -
32622 -       s3c2410_pm_check_store();
32623 -
32624 -       /* send the cpu to sleep... */
32625 -
32626 -       __raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */
32627 -
32628 -       /* s3c2410_cpu_save will also act as our return point from when
32629 -        * we resume as it saves its own register state, so use the return
32630 -        * code to differentiate return from save and return from sleep */
32631 -
32632 -       if (s3c2410_cpu_save(regs_save) == 0) {
32633 -               flush_cache_all();
32634 -               pm_cpu_sleep();
32635 -       }
32636 -
32637 -       /* restore the cpu state */
32638 -
32639 -       cpu_init();
32640 -
32641 -       /* restore the system state */
32642 -
32643 -       s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
32644 -       s3c2410_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
32645 -       s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
32646 -       s3c2410_pm_restore_gpios();
32647 -
32648 -       s3c2410_pm_debug_init();
32649 -
32650 -       /* check what irq (if any) restored the system */
32651 -
32652 -       DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
32653 -           __raw_readl(S3C2410_SRCPND),
32654 -           __raw_readl(S3C2410_EINTPEND));
32655 -
32656 -       s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
32657 -                                   s3c_irqwake_intmask);
32658 -
32659 -       s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
32660 -                                   s3c_irqwake_eintmask);
32661 -
32662 -       DBG("post sleep, preparing to return\n");
32663 -
32664 -       s3c2410_pm_check_restore();
32665 -
32666 -       /* ok, let's return from sleep */
32667 -
32668 -       DBG("S3C2410 PM Resume (post-restore)\n");
32669 -       return 0;
32670 -}
32671 -
32672 -static struct platform_suspend_ops s3c2410_pm_ops = {
32673 -       .enter          = s3c2410_pm_enter,
32674 -       .valid          = suspend_valid_only_mem,
32675 -};
32676 -
32677 -/* s3c2410_pm_init
32678 - *
32679 - * Attach the power management functions. This should be called
32680 - * from the board specific initialisation if the board supports
32681 - * it.
32682 -*/
32683 -
32684 -int __init s3c2410_pm_init(void)
32685 -{
32686 -       printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
32687 -
32688 -       suspend_set_ops(&s3c2410_pm_ops);
32689 -       return 0;
32690 -}
32691 --- a/arch/arm/plat-s3c24xx/pm-simtec.c
32692 +++ b/arch/arm/plat-s3c24xx/pm-simtec.c
32693 @@ -61,7 +61,7 @@ static __init int pm_simtec_init(void)
32694
32695         __raw_writel(gstatus4, S3C2410_GSTATUS4);
32696
32697 -       return s3c2410_pm_init();
32698 +       return s3c_pm_init();
32699  }
32700
32701  arch_initcall(pm_simtec_init);
32702 --- a/arch/arm/plat-s3c24xx/pwm-clock.c
32703 +++ b/arch/arm/plat-s3c24xx/pwm-clock.c
32704 @@ -24,10 +24,10 @@
32705  #include <mach/regs-clock.h>
32706  #include <mach/regs-gpio.h>
32707
32708 -#include <plat/clock.h>
32709 -#include <plat/cpu.h>
32710 +#include <asm/plat-s3c24xx/clock.h>
32711 +#include <asm/plat-s3c24xx/cpu.h>
32712
32713 -#include <plat/regs-timer.h>
32714 +#include <asm/plat-s3c/regs-timer.h>
32715
32716  /* Each of the timers 0 through 5 go through the following
32717   * clock tree, with the inputs depending on the timers.
32718 --- /dev/null
32719 +++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
32720 @@ -0,0 +1,277 @@
32721 +/* linux/arch/arm/mach-s3c2410/clock.c
32722 + *
32723 + * Copyright (c) 2006 Simtec Electronics
32724 + *     Ben Dooks <ben@simtec.co.uk>
32725 + *
32726 + * S3C2410,S3C2440,S3C2442 Clock control support
32727 + *
32728 + * This program is free software; you can redistribute it and/or modify
32729 + * it under the terms of the GNU General Public License as published by
32730 + * the Free Software Foundation; either version 2 of the License, or
32731 + * (at your option) any later version.
32732 + *
32733 + * This program is distributed in the hope that it will be useful,
32734 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
32735 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
32736 + * GNU General Public License for more details.
32737 + *
32738 + * You should have received a copy of the GNU General Public License
32739 + * along with this program; if not, write to the Free Software
32740 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
32741 +*/
32742 +
32743 +#include <linux/init.h>
32744 +#include <linux/module.h>
32745 +#include <linux/kernel.h>
32746 +#include <linux/list.h>
32747 +#include <linux/errno.h>
32748 +#include <linux/err.h>
32749 +#include <linux/sysdev.h>
32750 +#include <linux/clk.h>
32751 +#include <linux/mutex.h>
32752 +#include <linux/delay.h>
32753 +#include <linux/serial_core.h>
32754 +#include <linux/io.h>
32755 +
32756 +#include <asm/mach/map.h>
32757 +
32758 +#include <mach/hardware.h>
32759 +
32760 +#include <plat/regs-serial.h>
32761 +#include <mach/regs-clock.h>
32762 +#include <mach/regs-gpio.h>
32763 +
32764 +#include <plat/s3c2410.h>
32765 +#include <plat/clock.h>
32766 +#include <plat/cpu.h>
32767 +
32768 +int s3c2410_clkcon_enable(struct clk *clk, int enable)
32769 +{
32770 +       unsigned int clocks = clk->ctrlbit;
32771 +       unsigned long clkcon;
32772 +
32773 +       clkcon = __raw_readl(S3C2410_CLKCON);
32774 +
32775 +       if (enable)
32776 +               clkcon |= clocks;
32777 +       else
32778 +               clkcon &= ~clocks;
32779 +
32780 +       /* ensure none of the special function bits set */
32781 +       clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
32782 +
32783 +       __raw_writel(clkcon, S3C2410_CLKCON);
32784 +
32785 +       return 0;
32786 +}
32787 +
32788 +static int s3c2410_upll_enable(struct clk *clk, int enable)
32789 +{
32790 +       unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
32791 +       unsigned long orig = clkslow;
32792 +
32793 +       if (enable)
32794 +               clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
32795 +       else
32796 +               clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
32797 +
32798 +       __raw_writel(clkslow, S3C2410_CLKSLOW);
32799 +
32800 +       /* if we started the UPLL, then allow to settle */
32801 +
32802 +       if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
32803 +               udelay(200);
32804 +
32805 +       return 0;
32806 +}
32807 +
32808 +/* standard clock definitions */
32809 +
32810 +static struct clk init_clocks_disable[] = {
32811 +       {
32812 +               .name           = "nand",
32813 +               .id             = -1,
32814 +               .parent         = &clk_h,
32815 +               .enable         = s3c2410_clkcon_enable,
32816 +               .ctrlbit        = S3C2410_CLKCON_NAND,
32817 +       }, {
32818 +               .name           = "sdi",
32819 +               .id             = -1,
32820 +               .parent         = &clk_p,
32821 +               .enable         = s3c2410_clkcon_enable,
32822 +               .ctrlbit        = S3C2410_CLKCON_SDI,
32823 +       }, {
32824 +               .name           = "adc",
32825 +               .id             = -1,
32826 +               .parent         = &clk_p,
32827 +               .enable         = s3c2410_clkcon_enable,
32828 +               .ctrlbit        = S3C2410_CLKCON_ADC,
32829 +       }, {
32830 +               .name           = "i2c",
32831 +               .id             = -1,
32832 +               .parent         = &clk_p,
32833 +               .enable         = s3c2410_clkcon_enable,
32834 +               .ctrlbit        = S3C2410_CLKCON_IIC,
32835 +       }, {
32836 +               .name           = "iis",
32837 +               .id             = -1,
32838 +               .parent         = &clk_p,
32839 +               .enable         = s3c2410_clkcon_enable,
32840 +               .ctrlbit        = S3C2410_CLKCON_IIS,
32841 +       }, {
32842 +               .name           = "spi",
32843 +               .id             = -1,
32844 +               .parent         = &clk_p,
32845 +               .enable         = s3c2410_clkcon_enable,
32846 +               .ctrlbit        = S3C2410_CLKCON_SPI,
32847 +       }
32848 +};
32849 +
32850 +static struct clk init_clocks[] = {
32851 +       {
32852 +               .name           = "lcd",
32853 +               .id             = -1,
32854 +               .parent         = &clk_h,
32855 +               .enable         = s3c2410_clkcon_enable,
32856 +               .ctrlbit        = S3C2410_CLKCON_LCDC,
32857 +       }, {
32858 +               .name           = "gpio",
32859 +               .id             = -1,
32860 +               .parent         = &clk_p,
32861 +               .enable         = s3c2410_clkcon_enable,
32862 +               .ctrlbit        = S3C2410_CLKCON_GPIO,
32863 +       }, {
32864 +               .name           = "usb-host",
32865 +               .id             = -1,
32866 +               .parent         = &clk_h,
32867 +               .enable         = s3c2410_clkcon_enable,
32868 +               .ctrlbit        = S3C2410_CLKCON_USBH,
32869 +       }, {
32870 +               .name           = "usb-device",
32871 +               .id             = -1,
32872 +               .parent         = &clk_h,
32873 +               .enable         = s3c2410_clkcon_enable,
32874 +               .ctrlbit        = S3C2410_CLKCON_USBD,
32875 +       }, {
32876 +               .name           = "timers",
32877 +               .id             = -1,
32878 +               .parent         = &clk_p,
32879 +               .enable         = s3c2410_clkcon_enable,
32880 +               .ctrlbit        = S3C2410_CLKCON_PWMT,
32881 +       }, {
32882 +               .name           = "uart",
32883 +               .id             = 0,
32884 +               .parent         = &clk_p,
32885 +               .enable         = s3c2410_clkcon_enable,
32886 +               .ctrlbit        = S3C2410_CLKCON_UART0,
32887 +       }, {
32888 +               .name           = "uart",
32889 +               .id             = 1,
32890 +               .parent         = &clk_p,
32891 +               .enable         = s3c2410_clkcon_enable,
32892 +               .ctrlbit        = S3C2410_CLKCON_UART1,
32893 +       }, {
32894 +               .name           = "uart",
32895 +               .id             = 2,
32896 +               .parent         = &clk_p,
32897 +               .enable         = s3c2410_clkcon_enable,
32898 +               .ctrlbit        = S3C2410_CLKCON_UART2,
32899 +       }, {
32900 +               .name           = "rtc",
32901 +               .id             = -1,
32902 +               .parent         = &clk_p,
32903 +               .enable         = s3c2410_clkcon_enable,
32904 +               .ctrlbit        = S3C2410_CLKCON_RTC,
32905 +       }, {
32906 +               .name           = "watchdog",
32907 +               .id             = -1,
32908 +               .parent         = &clk_p,
32909 +               .ctrlbit        = 0,
32910 +       }, {
32911 +               .name           = "usb-bus-host",
32912 +               .id             = -1,
32913 +               .parent         = &clk_usb_bus,
32914 +       }, {
32915 +               .name           = "usb-bus-gadget",
32916 +               .id             = -1,
32917 +               .parent         = &clk_usb_bus,
32918 +       },
32919 +};
32920 +
32921 +/* s3c2410_baseclk_add()
32922 + *
32923 + * Add all the clocks used by the s3c2410 or compatible CPUs
32924 + * such as the S3C2440 and S3C2442.
32925 + *
32926 + * We cannot use a system device as we are needed before any
32927 + * of the init-calls that initialise the devices are actually
32928 + * done.
32929 +*/
32930 +
32931 +int __init s3c2410_baseclk_add(void)
32932 +{
32933 +       unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
32934 +       unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
32935 +       struct clk *clkp;
32936 +       struct clk *xtal;
32937 +       int ret;
32938 +       int ptr;
32939 +
32940 +       clk_upll.enable = s3c2410_upll_enable;
32941 +
32942 +       if (s3c24xx_register_clock(&clk_usb_bus) < 0)
32943 +               printk(KERN_ERR "failed to register usb bus clock\n");
32944 +
32945 +       /* register clocks from clock array */
32946 +
32947 +       clkp = init_clocks;
32948 +       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
32949 +               /* ensure that we note the clock state */
32950 +
32951 +               clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
32952 +
32953 +               ret = s3c24xx_register_clock(clkp);
32954 +               if (ret < 0) {
32955 +                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
32956 +                              clkp->name, ret);
32957 +               }
32958 +       }
32959 +
32960 +       /* We must be careful disabling the clocks we are not intending to
32961 +        * be using at boot time, as subsystems such as the LCD which do
32962 +        * their own DMA requests to the bus can cause the system to lockup
32963 +        * if they where in the middle of requesting bus access.
32964 +        *
32965 +        * Disabling the LCD clock if the LCD is active is very dangerous,
32966 +        * and therefore the bootloader should be careful to not enable
32967 +        * the LCD clock if it is not needed.
32968 +       */
32969 +
32970 +       /* install (and disable) the clocks we do not need immediately */
32971 +
32972 +       clkp = init_clocks_disable;
32973 +       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
32974 +
32975 +               ret = s3c24xx_register_clock(clkp);
32976 +               if (ret < 0) {
32977 +                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
32978 +                              clkp->name, ret);
32979 +               }
32980 +
32981 +               s3c2410_clkcon_enable(clkp, 0);
32982 +       }
32983 +
32984 +       /* show the clock-slow value */
32985 +
32986 +       xtal = clk_get(NULL, "xtal");
32987 +
32988 +       printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
32989 +              print_mhz(clk_get_rate(xtal) /
32990 +                        ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
32991 +              (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
32992 +              (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
32993 +              (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
32994 +
32995 +       s3c_pwmclk_init();
32996 +       return 0;
32997 +}
32998 --- a/arch/arm/plat-s3c24xx/s3c244x.c
32999 +++ b/arch/arm/plat-s3c24xx/s3c244x.c
33000 @@ -29,6 +29,8 @@
33001  #include <mach/hardware.h>
33002  #include <asm/irq.h>
33003
33004 +#include <plat/cpu-freq.h>
33005 +
33006  #include <mach/regs-clock.h>
33007  #include <plat/regs-serial.h>
33008  #include <mach/regs-gpio.h>
33009 @@ -42,6 +44,7 @@
33010  #include <plat/devs.h>
33011  #include <plat/cpu.h>
33012  #include <plat/pm.h>
33013 +#include <plat/pll.h>
33014
33015  static struct map_desc s3c244x_iodesc[] __initdata = {
33016         IODESC_ENT(CLKPWR),
33017 @@ -56,32 +59,37 @@ void __init s3c244x_init_uarts(struct s3
33018         s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
33019  }
33020
33021 -void __init s3c244x_map_io(struct map_desc *mach_desc, int size)
33022 +extern struct platform_device s3c_device_ts;
33023 +
33024 +void __init s3c244x_map_io(void)
33025  {
33026         /* register our io-tables */
33027
33028         iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
33029 -       iotable_init(mach_desc, size);
33030
33031         /* rename any peripherals used differing from the s3c2410 */
33032
33033         s3c_device_sdi.name  = "s3c2440-sdi";
33034 -       s3c_device_i2c.name  = "s3c2440-i2c";
33035 +       s3c_device_i2c0.name  = "s3c2440-i2c";
33036         s3c_device_nand.name = "s3c2440-nand";
33037 +       s3c_device_ts.name = "s3c2440-ts";
33038         s3c_device_usbgadget.name = "s3c2440-usbgadget";
33039  }
33040
33041 -void __init s3c244x_init_clocks(int xtal)
33042 +void __init_or_cpufreq s3c244x_setup_clocks(void)
33043  {
33044 +       struct clk *xtal_clk;
33045         unsigned long clkdiv;
33046         unsigned long camdiv;
33047 +       unsigned long xtal;
33048         unsigned long hclk, fclk, pclk;
33049         int hdiv = 1;
33050
33051 -       /* now we've got our machine bits initialised, work out what
33052 -        * clocks we've got */
33053 +       xtal_clk = clk_get(NULL, "xtal");
33054 +       xtal = clk_get_rate(xtal_clk);
33055 +       clk_put(xtal_clk);
33056
33057 -       fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
33058 +       fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
33059
33060         clkdiv = __raw_readl(S3C2410_CLKDIVN);
33061         camdiv = __raw_readl(S3C2440_CAMDIVN);
33062 @@ -107,18 +115,24 @@ void __init s3c244x_init_clocks(int xtal
33063         }
33064
33065         hclk = fclk / hdiv;
33066 -       pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
33067 +       pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
33068
33069         /* print brief summary of clocks, etc */
33070
33071         printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
33072                print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
33073
33074 +       s3c24xx_setup_clocks(fclk, hclk, pclk);
33075 +}
33076 +
33077 +void __init s3c244x_init_clocks(int xtal)
33078 +{
33079         /* initialise the clocks here, to allow other things like the
33080          * console to use them, and to add new ones after the initialisation
33081          */
33082
33083 -       s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
33084 +       s3c24xx_register_baseclocks(xtal);
33085 +       s3c244x_setup_clocks();
33086         s3c2410_baseclk_add();
33087  }
33088
33089 @@ -134,13 +148,13 @@ static struct sleep_save s3c244x_sleep[]
33090
33091  static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
33092  {
33093 -       s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
33094 +       s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
33095         return 0;
33096  }
33097
33098  static int s3c244x_resume(struct sys_device *dev)
33099  {
33100 -       s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
33101 +       s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
33102         return 0;
33103  }
33104
33105 --- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
33106 +++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c
33107 @@ -31,7 +31,6 @@
33108  #include <linux/sysdev.h>
33109  #include <linux/interrupt.h>
33110  #include <linux/ioport.h>
33111 -#include <linux/mutex.h>
33112  #include <linux/clk.h>
33113  #include <linux/io.h>
33114
33115 @@ -102,13 +101,13 @@ static int s3c244x_clk_add(struct sys_de
33116         if (clk_get_rate(clock_upll) > (94 * MHZ)) {
33117                 clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
33118
33119 -               mutex_lock(&clocks_mutex);
33120 +               spin_lock(&clocks_lock);
33121
33122                 clkdivn = __raw_readl(S3C2410_CLKDIVN);
33123                 clkdivn |= S3C2440_CLKDIVN_UCLK;
33124                 __raw_writel(clkdivn, S3C2410_CLKDIVN);
33125
33126 -               mutex_unlock(&clocks_mutex);
33127 +               spin_unlock(&clocks_lock);
33128         }
33129
33130         return 0;
33131 --- a/arch/arm/plat-s3c24xx/s3c244x.h
33132 +++ b/arch/arm/plat-s3c24xx/s3c244x.h
33133 @@ -12,7 +12,7 @@
33134
33135  #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
33136
33137 -extern void s3c244x_map_io(struct map_desc *mach_desc, int size);
33138 +extern void s3c244x_map_io(void);
33139
33140  extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
33141
33142 --- /dev/null
33143 +++ b/arch/arm/plat-s3c24xx/setup-i2c.c
33144 @@ -0,0 +1,25 @@
33145 +/* linux/arch/arm/plat-s3c24xx/setup-i2c.c
33146 + *
33147 + * Copyright 2008 Simtec Electronics
33148 + *     Ben Dooks <ben@simtec.co.uk>
33149 + *
33150 + * S3C24XX Base setup for i2c device
33151 + *
33152 + * This program is free software; you can redistribute it and/or modify
33153 + * it under the terms of the GNU General Public License version 2 as
33154 + * published by the Free Software Foundation.
33155 +*/
33156 +
33157 +#include <linux/kernel.h>
33158 +
33159 +struct platform_device;
33160 +
33161 +#include <plat/iic.h>
33162 +#include <mach/hardware.h>
33163 +#include <mach/regs-gpio.h>
33164 +
33165 +void s3c_i2c0_cfg_gpio(struct platform_device *dev)
33166 +{
33167 +       s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
33168 +       s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
33169 +}
33170 --- a/arch/arm/plat-s3c24xx/sleep.S
33171 +++ b/arch/arm/plat-s3c24xx/sleep.S
33172 @@ -41,7 +41,7 @@
33173
33174         .text
33175
33176 -       /* s3c2410_cpu_save
33177 +       /* s3c_cpu_save
33178          *
33179          * save enough of the CPU state to allow us to re-start
33180          * pm.c code. as we store items like the sp/lr, we will
33181 @@ -59,7 +59,7 @@
33182          *           1 => resumed from sleep
33183         */
33184
33185 -ENTRY(s3c2410_cpu_save)
33186 +ENTRY(s3c_cpu_save)
33187         stmfd   sp!, { r4 - r12, lr }
33188
33189         @@ store co-processor registers
33190 @@ -84,7 +84,7 @@ resume_with_mmu:
33191         .ltorg
33192
33193         @@ the next bits sit in the .data segment, even though they
33194 -       @@ happen to be code... the s3c2410_sleep_save_phys needs to be
33195 +       @@ happen to be code... the s3c_sleep_save_phys needs to be
33196         @@ accessed by the resume code before it can restore the MMU.
33197         @@ This means that the variable has to be close enough for the
33198         @@ code to read it... since the .text segment needs to be RO,
33199 @@ -92,19 +92,19 @@ resume_with_mmu:
33200
33201         .data
33202
33203 -       .global s3c2410_sleep_save_phys
33204 -s3c2410_sleep_save_phys:
33205 +       .global s3c_sleep_save_phys
33206 +s3c_sleep_save_phys:
33207         .word   0
33208
33209
33210         /* sleep magic, to allow the bootloader to check for an valid
33211          * image to resume to. Must be the first word before the
33212 -        * s3c2410_cpu_resume entry.
33213 +        * s3c_cpu_resume entry.
33214         */
33215
33216         .word   0x2bedf00d
33217
33218 -       /* s3c2410_cpu_resume
33219 +       /* s3c_cpu_resume
33220          *
33221          * resume code entry for bootloader to call
33222          *
33223 @@ -113,7 +113,7 @@ s3c2410_sleep_save_phys:
33224          * must not write to the code segment (code is read-only)
33225         */
33226
33227 -ENTRY(s3c2410_cpu_resume)
33228 +ENTRY(s3c_cpu_resume)
33229         mov     r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
33230         msr     cpsr_c, r0
33231
33232 @@ -145,7 +145,7 @@ ENTRY(s3c2410_cpu_resume)
33233         mcr     p15, 0, r1, c8, c7, 0           @@ invalidate I & D TLBs
33234         mcr     p15, 0, r1, c7, c7, 0           @@ invalidate I & D caches
33235
33236 -       ldr     r0, s3c2410_sleep_save_phys     @ address of restore block
33237 +       ldr     r0, s3c_sleep_save_phys         @ address of restore block
33238         ldmia   r0, { r4 - r13 }
33239
33240         mcr     p15, 0, r4, c13, c0, 0          @ PID
33241 --- /dev/null
33242 +++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
33243 @@ -0,0 +1,37 @@
33244 +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
33245 + *
33246 + * Copyright (c) 2008 Simtec Electronics
33247 + *     http://armlinux.simtec.co.uk/
33248 + *     Ben Dooks <ben@simtec.co.uk>
33249 + *
33250 + * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13
33251 + *
33252 + * This program is free software; you can redistribute it and/or modify
33253 + * it under the terms of the GNU General Public License as published by
33254 + * the Free Software Foundation; either version 2 of the License.
33255 +*/
33256 +
33257 +#include <linux/kernel.h>
33258 +
33259 +#include <mach/hardware.h>
33260 +
33261 +#include <mach/spi.h>
33262 +#include <mach/regs-gpio.h>
33263 +
33264 +void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
33265 +                                         int enable)
33266 +{
33267 +       if (enable) {
33268 +               s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
33269 +               s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
33270 +               s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
33271 +               s3c2410_gpio_pullup(S3C2410_GPE11, 0);
33272 +               s3c2410_gpio_pullup(S3C2410_GPE13, 0);
33273 +       } else {
33274 +               s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT);
33275 +               s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT);
33276 +               s3c2410_gpio_pullup(S3C2410_GPE11, 1);
33277 +               s3c2410_gpio_pullup(S3C2410_GPE12, 1);
33278 +               s3c2410_gpio_pullup(S3C2410_GPE13, 1);
33279 +       }
33280 +}
33281 --- /dev/null
33282 +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
33283 @@ -0,0 +1,37 @@
33284 +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c
33285 + *
33286 + * Copyright (c) 2008 Simtec Electronics
33287 + *     http://armlinux.simtec.co.uk/
33288 + *     Ben Dooks <ben@simtec.co.uk>
33289 + *
33290 + * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7
33291 + *
33292 + * This program is free software; you can redistribute it and/or modify
33293 + * it under the terms of the GNU General Public License as published by
33294 + * the Free Software Foundation; either version 2 of the License.
33295 +*/
33296 +
33297 +#include <linux/kernel.h>
33298 +
33299 +#include <mach/hardware.h>
33300 +
33301 +#include <mach/spi.h>
33302 +#include <mach/regs-gpio.h>
33303 +
33304 +void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
33305 +                                      int enable)
33306 +{
33307 +       if (enable) {
33308 +               s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1);
33309 +               s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1);
33310 +               s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1);
33311 +               s3c2410_gpio_pullup(S3C2410_GPG5, 0);
33312 +               s3c2410_gpio_pullup(S3C2410_GPG6, 0);
33313 +       } else {
33314 +               s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT);
33315 +               s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT);
33316 +               s3c2410_gpio_pullup(S3C2410_GPG5, 1);
33317 +               s3c2410_gpio_pullup(S3C2410_GPG6, 1);
33318 +               s3c2410_gpio_pullup(S3C2410_GPG7, 1);
33319 +       }
33320 +}
33321 --- a/arch/arm/plat-s3c24xx/time.c
33322 +++ b/arch/arm/plat-s3c24xx/time.c
33323 @@ -3,6 +3,8 @@
33324   * Copyright (C) 2003-2005 Simtec Electronics
33325   *     Ben Dooks, <ben@simtec.co.uk>
33326   *
33327 + * dyn_tick support by Andrzej Zaborowski based on omap_dyn_tick_timer.
33328 + *
33329   * This program is free software; you can redistribute it and/or modify
33330   * it under the terms of the GNU General Public License as published by
33331   * the Free Software Foundation; either version 2 of the License, or
33332 @@ -25,23 +27,27 @@
33333  #include <linux/irq.h>
33334  #include <linux/err.h>
33335  #include <linux/clk.h>
33336 -#include <linux/io.h>
33337
33338  #include <asm/system.h>
33339  #include <asm/leds.h>
33340  #include <asm/mach-types.h>
33341
33342 +#include <asm/io.h>
33343  #include <asm/irq.h>
33344  #include <mach/map.h>
33345 -#include <plat/regs-timer.h>
33346 +#include <asm/plat-s3c/regs-timer.h>
33347  #include <mach/regs-irq.h>
33348  #include <asm/mach/time.h>
33349
33350 -#include <plat/clock.h>
33351 -#include <plat/cpu.h>
33352 +#include <asm/plat-s3c24xx/clock.h>
33353 +#include <asm/plat-s3c24xx/cpu.h>
33354
33355  static unsigned long timer_startval;
33356  static unsigned long timer_usec_ticks;
33357 +static struct work_struct resume_work;
33358 +
33359 +unsigned long pclk;
33360 +struct clk *clk;
33361
33362  #define TIMER_USEC_SHIFT 16
33363
33364 @@ -177,11 +183,7 @@ static void s3c2410_timer_setup (void)
33365                 tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
33366                 tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
33367         } else {
33368 -               unsigned long pclk;
33369 -               struct clk *clk;
33370 -
33371 -               /* for the h1940 (and others), we use the pclk from the core
33372 -                * to generate the timer values. since values around 50 to
33373 +               /* since values around 50 to
33374                  * 70MHz are not values we can directly generate the timer
33375                  * value from, we need to pre-scale and divide before using it.
33376                  *
33377 @@ -189,19 +191,9 @@ static void s3c2410_timer_setup (void)
33378                  * (8.45 ticks per usec)
33379                  */
33380
33381 -               /* this is used as default if no other timer can be found */
33382 -
33383 -               clk = clk_get(NULL, "timers");
33384 -               if (IS_ERR(clk))
33385 -                       panic("failed to get clock for system timer");
33386 -
33387 -               clk_enable(clk);
33388 -
33389 -               pclk = clk_get_rate(clk);
33390 -
33391                 /* configure clock tick */
33392 -
33393                 timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
33394 +               printk("timer_usec_ticks = %lu\n", timer_usec_ticks);
33395
33396                 tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
33397                 tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
33398 @@ -245,16 +237,244 @@ static void s3c2410_timer_setup (void)
33399         tcon |= S3C2410_TCON_T4START;
33400         tcon &= ~S3C2410_TCON_T4MANUALUPD;
33401         __raw_writel(tcon, S3C2410_TCON);
33402 +
33403 +       __raw_writel(__raw_readl(S3C2410_INTMSK) & (~(1UL << 14)),
33404 +                    S3C2410_INTMSK);
33405 +
33406 +}
33407 +
33408 +struct sys_timer s3c24xx_timer;
33409 +static void timer_resume_work(struct work_struct *work)
33410 +{
33411 +       clk_enable(clk);
33412 +
33413 +#ifdef CONFIG_NO_IDLE_HZ
33414 +       if (s3c24xx_timer.dyn_tick->state & DYN_TICK_ENABLED)
33415 +               s3c24xx_timer.dyn_tick->enable();
33416 +       else
33417 +#endif
33418 +               s3c2410_timer_setup();
33419  }
33420
33421  static void __init s3c2410_timer_init (void)
33422  {
33423 +       if (!use_tclk1_12()) {
33424 +               /* for the h1940 (and others), we use the pclk from the core
33425 +                * to generate the timer values.
33426 +                */
33427 +
33428 +               /* this is used as default if no other timer can be found */
33429 +               clk = clk_get(NULL, "timers");
33430 +               if (IS_ERR(clk))
33431 +                       panic("failed to get clock for system timer");
33432 +
33433 +               clk_enable(clk);
33434 +
33435 +               pclk = clk_get_rate(clk);
33436 +               printk("pclk = %lu\n", pclk);
33437 +       }
33438 +
33439 +       INIT_WORK(&resume_work, timer_resume_work);
33440         s3c2410_timer_setup();
33441         setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
33442  }
33443
33444 +static void s3c2410_timer_resume_work(struct work_struct *work)
33445 +{
33446 +       s3c2410_timer_setup();
33447 +}
33448 +
33449 +static void s3c2410_timer_resume(void)
33450 +{
33451 +       static DECLARE_WORK(work, s3c2410_timer_resume_work);
33452 +       int res;
33453 +
33454 +       res = schedule_work(&work);
33455 +       if (!res)
33456 +               printk(KERN_ERR
33457 +                   "s3c2410_timer_resume_work already queued ???\n");
33458 +}
33459 +
33460 +#ifdef CONFIG_NO_IDLE_HZ
33461 +/*
33462 + * We'll set a constant prescaler so we don't have to bother setting it
33463 + * when reprogramming and so that we avoid costly divisions.
33464 + *
33465 + * (2 * HZ) << INPUT_FREQ_SHIFT is the desired frequency after prescaler.
33466 + * At HZ == 200, HZ * 1024 should work for PCLKs of up to ~53.5 MHz.
33467 + */
33468 +#define INPUT_FREQ_SHIFT       9
33469 +
33470 +static int ticks_last;
33471 +static int ticks_left;
33472 +static uint32_t tcnto_last;
33473 +
33474 +static inline int s3c24xx_timer_read(void)
33475 +{
33476 +       uint32_t tcnto = __raw_readl(S3C2410_TCNTO(4));
33477 +
33478 +       /*
33479 +        * WARNING: sometimes we get called before TCNTB has been
33480 +        * loaded into the counter and TCNTO then returns its previous
33481 +        * value and kill us, so don't do anything before counter is
33482 +        * reloaded.
33483 +        */
33484 +       if (unlikely(tcnto == tcnto_last))
33485 +               return ticks_last;
33486 +
33487 +       tcnto_last = -1;
33488 +       return tcnto <<
33489 +               ((__raw_readl(S3C2410_TCFG1) >> S3C2410_TCFG1_MUX4_SHIFT) & 3);
33490 +}
33491 +
33492 +static inline void s3c24xx_timer_program(int ticks)
33493 +{
33494 +       uint32_t tcon = __raw_readl(S3C2410_TCON) & ~(7 << 20);
33495 +       uint32_t tcfg1 = __raw_readl(S3C2410_TCFG1) & ~S3C2410_TCFG1_MUX4_MASK;
33496 +
33497 +       /* Just make sure the timer is stopped.  */
33498 +       __raw_writel(tcon, S3C2410_TCON);
33499 +
33500 +       /* TODO: add likely()ies / unlikely()ies */
33501 +       if (ticks >> 18) {
33502 +               ticks_last = min(ticks, 0xffff << 3);
33503 +               ticks_left = ticks - ticks_last;
33504 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV16, S3C2410_TCFG1);
33505 +               __raw_writel(ticks_last >> 3, S3C2410_TCNTB(4));
33506 +       } else if (ticks >> 17) {
33507 +               ticks_last = ticks;
33508 +               ticks_left = 0;
33509 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV8, S3C2410_TCFG1);
33510 +               __raw_writel(ticks_last >> 2, S3C2410_TCNTB(4));
33511 +       } else if (ticks >> 16) {
33512 +               ticks_last = ticks;
33513 +               ticks_left = 0;
33514 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV4, S3C2410_TCFG1);
33515 +               __raw_writel(ticks_last >> 1, S3C2410_TCNTB(4));
33516 +       } else {
33517 +               ticks_last = ticks;
33518 +               ticks_left = 0;
33519 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV2, S3C2410_TCFG1);
33520 +               __raw_writel(ticks_last >> 0, S3C2410_TCNTB(4));
33521 +       }
33522 +
33523 +       tcnto_last = __raw_readl(S3C2410_TCNTO(4));
33524 +       __raw_writel(tcon | S3C2410_TCON_T4MANUALUPD,
33525 +                       S3C2410_TCON);
33526 +       __raw_writel(tcon | S3C2410_TCON_T4START,
33527 +                       S3C2410_TCON);
33528 +}
33529 +
33530 +/*
33531 + * If we have already waited all the time we were supposed to wait,
33532 + * kick the timer, setting the longest allowed timeout value just
33533 + * for time-keeping.
33534 + */
33535 +static inline void s3c24xx_timer_program_idle(void)
33536 +{
33537 +       s3c24xx_timer_program(0xffff << 3);
33538 +}
33539 +
33540 +static inline void s3c24xx_timer_update(int restart)
33541 +{
33542 +       int ticks_cur = s3c24xx_timer_read();
33543 +       int jiffies_elapsed = (ticks_last - ticks_cur) >> INPUT_FREQ_SHIFT;
33544 +       int subjiffy = ticks_last - (jiffies_elapsed << INPUT_FREQ_SHIFT);
33545 +
33546 +       if (restart) {
33547 +               if (ticks_left >= (1 << INPUT_FREQ_SHIFT))
33548 +                       s3c24xx_timer_program(ticks_left);
33549 +               else
33550 +                       s3c24xx_timer_program_idle();
33551 +               ticks_last += subjiffy;
33552 +       } else
33553 +               ticks_last = subjiffy;
33554 +
33555 +       while (jiffies_elapsed --)
33556 +               timer_tick();
33557 +}
33558 +
33559 +/* Called when the timer expires.  */
33560 +static irqreturn_t s3c24xx_timer_handler(int irq, void *dev_id)
33561 +{
33562 +       tcnto_last = -1;
33563 +       s3c24xx_timer_update(1);
33564 +
33565 +       return IRQ_HANDLED;
33566 +}
33567 +
33568 +/* Called to update jiffies with time elapsed.  */
33569 +static irqreturn_t s3c24xx_timer_handler_dyn_tick(int irq, void *dev_id)
33570 +{
33571 +       s3c24xx_timer_update(0);
33572 +
33573 +       return IRQ_HANDLED;
33574 +}
33575 +
33576 +/*
33577 + * Programs the next timer interrupt needed.  Called when dynamic tick is
33578 + * enabled, and to reprogram the ticks to skip from pm_idle.  The CPU goes
33579 + * to sleep directly after this.
33580 + */
33581 +static void s3c24xx_timer_reprogram_dyn_tick(unsigned long next_jiffies)
33582 +{
33583 +       int subjiffy_left = ticks_last - s3c24xx_timer_read();
33584 +
33585 +       s3c24xx_timer_program(max((int) next_jiffies, 1) << INPUT_FREQ_SHIFT);
33586 +       ticks_last += subjiffy_left;
33587 +}
33588 +
33589 +static unsigned long s3c24xx_timer_offset_dyn_tick(void)
33590 +{
33591 +       /* TODO */
33592 +       return 0;
33593 +}
33594 +
33595 +static int s3c24xx_timer_enable_dyn_tick(void)
33596 +{
33597 +       /* Set our constant prescaler.  */
33598 +       uint32_t tcfg0 = __raw_readl(S3C2410_TCFG0);
33599 +       int prescaler =
33600 +               max(min(256, (int) pclk / (HZ << (INPUT_FREQ_SHIFT + 1))), 1);
33601 +
33602 +       tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
33603 +       tcfg0 |= (prescaler - 1) << S3C2410_TCFG_PRESCALER1_SHIFT;
33604 +       __raw_writel(tcfg0, S3C2410_TCFG0);
33605 +
33606 +       /* Override handlers.  */
33607 +       s3c2410_timer_irq.handler = s3c24xx_timer_handler;
33608 +       s3c24xx_timer.offset = s3c24xx_timer_offset_dyn_tick;
33609 +
33610 +       printk(KERN_INFO "dyn_tick enabled on s3c24xx timer 4, "
33611 +                       "%li Hz pclk with prescaler %i\n", pclk, prescaler);
33612 +
33613 +       s3c24xx_timer_program_idle();
33614 +
33615 +       return 0;
33616 +}
33617 +
33618 +static int s3c24xx_timer_disable_dyn_tick(void)
33619 +{
33620 +       s3c2410_timer_irq.handler = s3c2410_timer_interrupt;
33621 +       s3c24xx_timer.offset = s3c2410_gettimeoffset;
33622 +       s3c2410_timer_setup();
33623 +
33624 +       return 0;
33625 +}
33626 +
33627 +static struct dyn_tick_timer s3c24xx_dyn_tick_timer = {
33628 +       .enable         = s3c24xx_timer_enable_dyn_tick,
33629 +       .disable        = s3c24xx_timer_disable_dyn_tick,
33630 +       .reprogram      = s3c24xx_timer_reprogram_dyn_tick,
33631 +       .handler        = s3c24xx_timer_handler_dyn_tick,
33632 +};
33633 +#endif /* CONFIG_NO_IDLE_HZ */
33634 +
33635  struct sys_timer s3c24xx_timer = {
33636         .init           = s3c2410_timer_init,
33637         .offset         = s3c2410_gettimeoffset,
33638 -       .resume         = s3c2410_timer_setup
33639 +       .resume         = s3c2410_timer_resume,
33640 +#ifdef CONFIG_NO_IDLE_HZ
33641 +       .dyn_tick       = &s3c24xx_dyn_tick_timer,
33642 +#endif
33643  };
33644 --- /dev/null
33645 +++ b/arch/arm/plat-s3c64xx/clock.c
33646 @@ -0,0 +1,282 @@
33647 +/* linux/arch/arm/plat-s3c64xx/clock.c
33648 + *
33649 + * Copyright 2008 Openmoko, Inc.
33650 + * Copyright 2008 Simtec Electronics
33651 + *     Ben Dooks <ben@simtec.co.uk>
33652 + *     http://armlinux.simtec.co.uk/
33653 + *
33654 + * S3C64XX Base clock support
33655 + *
33656 + * This program is free software; you can redistribute it and/or modify
33657 + * it under the terms of the GNU General Public License version 2 as
33658 + * published by the Free Software Foundation.
33659 +*/
33660 +
33661 +#include <linux/init.h>
33662 +#include <linux/module.h>
33663 +#include <linux/interrupt.h>
33664 +#include <linux/ioport.h>
33665 +#include <linux/delay.h>
33666 +#include <linux/io.h>
33667 +
33668 +#include <mach/hardware.h>
33669 +#include <mach/map.h>
33670 +
33671 +#include <plat/regs-sys.h>
33672 +#include <plat/regs-clock.h>
33673 +#include <plat/cpu.h>
33674 +#include <plat/devs.h>
33675 +#include <plat/clock.h>
33676 +
33677 +struct clk clk_27m = {
33678 +       .name           = "clk_27m",
33679 +       .id             = -1,
33680 +       .rate           = 27000000,
33681 +};
33682 +
33683 +static int clk_48m_ctrl(struct clk *clk, int enable)
33684 +{
33685 +       unsigned long flags;
33686 +       u32 val;
33687 +
33688 +       /* can't rely on clock lock, this register has other usages */
33689 +       local_irq_save(flags);
33690 +
33691 +       val = __raw_readl(S3C64XX_OTHERS);
33692 +       if (enable)
33693 +               val |= S3C64XX_OTHERS_USBMASK;
33694 +       else
33695 +               val &= ~S3C64XX_OTHERS_USBMASK;
33696 +
33697 +       __raw_writel(val, S3C64XX_OTHERS);
33698 +       local_irq_restore(flags);
33699 +
33700 +       return 0;
33701 +}
33702 +
33703 +struct clk clk_48m = {
33704 +       .name           = "clk_48m",
33705 +       .id             = -1,
33706 +       .rate           = 48000000,
33707 +       .enable         = clk_48m_ctrl,
33708 +};
33709 +
33710 +static int inline s3c64xx_gate(void __iomem *reg,
33711 +                               struct clk *clk,
33712 +                               int enable)
33713 +{
33714 +       unsigned int ctrlbit = clk->ctrlbit;
33715 +       u32 con;
33716 +
33717 +       con = __raw_readl(reg);
33718 +
33719 +       if (enable)
33720 +               con |= ctrlbit;
33721 +       else
33722 +               con &= ~ctrlbit;
33723 +
33724 +       __raw_writel(con, reg);
33725 +       return 0;
33726 +}
33727 +
33728 +static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
33729 +{
33730 +       return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
33731 +}
33732 +
33733 +static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
33734 +{
33735 +       return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
33736 +}
33737 +
33738 +int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
33739 +{
33740 +       return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
33741 +}
33742 +
33743 +static struct clk init_clocks_disable[] = {
33744 +       {
33745 +               .name           = "nand",
33746 +               .id             = -1,
33747 +               .parent         = &clk_h,
33748 +       }, {
33749 +               .name           = "adc",
33750 +               .id             = -1,
33751 +               .parent         = &clk_p,
33752 +               .enable         = s3c64xx_pclk_ctrl,
33753 +               .ctrlbit        = S3C_CLKCON_PCLK_TSADC,
33754 +       }, {
33755 +               .name           = "i2c",
33756 +               .id             = -1,
33757 +               .parent         = &clk_p,
33758 +               .enable         = s3c64xx_pclk_ctrl,
33759 +               .ctrlbit        = S3C_CLKCON_PCLK_IIC,
33760 +       }, {
33761 +               .name           = "iis",
33762 +               .id             = 0,
33763 +               .parent         = &clk_p,
33764 +               .enable         = s3c64xx_pclk_ctrl,
33765 +               .ctrlbit        = S3C_CLKCON_PCLK_IIS0,
33766 +       }, {
33767 +               .name           = "iis",
33768 +               .id             = 1,
33769 +               .parent         = &clk_p,
33770 +               .enable         = s3c64xx_pclk_ctrl,
33771 +               .ctrlbit        = S3C_CLKCON_PCLK_IIS1,
33772 +       }, {
33773 +               .name           = "spi",
33774 +               .id             = 0,
33775 +               .parent         = &clk_p,
33776 +               .enable         = s3c64xx_pclk_ctrl,
33777 +               .ctrlbit        = S3C_CLKCON_PCLK_SPI0,
33778 +       }, {
33779 +               .name           = "spi",
33780 +               .id             = 1,
33781 +               .parent         = &clk_p,
33782 +               .enable         = s3c64xx_pclk_ctrl,
33783 +               .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
33784 +       }, {
33785 +               .name           = "48m",
33786 +               .id             = 0,
33787 +               .parent         = &clk_48m,
33788 +               .enable         = s3c64xx_sclk_ctrl,
33789 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC0_48,
33790 +       }, {
33791 +               .name           = "48m",
33792 +               .id             = 1,
33793 +               .parent         = &clk_48m,
33794 +               .enable         = s3c64xx_sclk_ctrl,
33795 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC1_48,
33796 +       }, {
33797 +               .name           = "48m",
33798 +               .id             = 2,
33799 +               .parent         = &clk_48m,
33800 +               .enable         = s3c64xx_sclk_ctrl,
33801 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
33802 +       },
33803 +};
33804 +
33805 +static struct clk init_clocks[] = {
33806 +       {
33807 +               .name           = "lcd",
33808 +               .id             = -1,
33809 +               .parent         = &clk_h,
33810 +               .enable         = s3c64xx_hclk_ctrl,
33811 +               .ctrlbit        = S3C_CLKCON_HCLK_LCD,
33812 +       }, {
33813 +               .name           = "gpio",
33814 +               .id             = -1,
33815 +               .parent         = &clk_p,
33816 +               .enable         = s3c64xx_pclk_ctrl,
33817 +               .ctrlbit        = S3C_CLKCON_PCLK_GPIO,
33818 +       }, {
33819 +               .name           = "usb-host",
33820 +               .id             = -1,
33821 +               .parent         = &clk_h,
33822 +               .enable         = s3c64xx_hclk_ctrl,
33823 +               .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
33824 +       }, {
33825 +               .name           = "hsmmc",
33826 +               .id             = 0,
33827 +               .parent         = &clk_h,
33828 +               .enable         = s3c64xx_hclk_ctrl,
33829 +               .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
33830 +       }, {
33831 +               .name           = "hsmmc",
33832 +               .id             = 1,
33833 +               .parent         = &clk_h,
33834 +               .enable         = s3c64xx_hclk_ctrl,
33835 +               .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
33836 +       }, {
33837 +               .name           = "hsmmc",
33838 +               .id             = 2,
33839 +               .parent         = &clk_h,
33840 +               .enable         = s3c64xx_hclk_ctrl,
33841 +               .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
33842 +       }, {
33843 +               .name           = "timers",
33844 +               .id             = -1,
33845 +               .parent         = &clk_p,
33846 +               .enable         = s3c64xx_pclk_ctrl,
33847 +               .ctrlbit        = S3C_CLKCON_PCLK_PWM,
33848 +       }, {
33849 +               .name           = "uart",
33850 +               .id             = 0,
33851 +               .parent         = &clk_p,
33852 +               .enable         = s3c64xx_pclk_ctrl,
33853 +               .ctrlbit        = S3C_CLKCON_PCLK_UART0,
33854 +       }, {
33855 +               .name           = "uart",
33856 +               .id             = 1,
33857 +               .parent         = &clk_p,
33858 +               .enable         = s3c64xx_pclk_ctrl,
33859 +               .ctrlbit        = S3C_CLKCON_PCLK_UART1,
33860 +       }, {
33861 +               .name           = "uart",
33862 +               .id             = 2,
33863 +               .parent         = &clk_p,
33864 +               .enable         = s3c64xx_pclk_ctrl,
33865 +               .ctrlbit        = S3C_CLKCON_PCLK_UART2,
33866 +       }, {
33867 +               .name           = "uart",
33868 +               .id             = 3,
33869 +               .parent         = &clk_p,
33870 +               .enable         = s3c64xx_pclk_ctrl,
33871 +               .ctrlbit        = S3C_CLKCON_PCLK_UART3,
33872 +       }, {
33873 +               .name           = "rtc",
33874 +               .id             = -1,
33875 +               .parent         = &clk_p,
33876 +               .enable         = s3c64xx_pclk_ctrl,
33877 +               .ctrlbit        = S3C_CLKCON_PCLK_RTC,
33878 +       }, {
33879 +               .name           = "watchdog",
33880 +               .id             = -1,
33881 +               .parent         = &clk_p,
33882 +               .ctrlbit        = S3C_CLKCON_PCLK_WDT,
33883 +       }, {
33884 +               .name           = "ac97",
33885 +               .id             = -1,
33886 +               .parent         = &clk_p,
33887 +               .ctrlbit        = S3C_CLKCON_PCLK_AC97,
33888 +       }
33889 +};
33890 +
33891 +static struct clk *clks[] __initdata = {
33892 +       &clk_ext,
33893 +       &clk_epll,
33894 +       &clk_27m,
33895 +       &clk_48m,
33896 +};
33897 +
33898 +void s3c64xx_register_clocks(void)
33899 +{
33900 +       struct clk *clkp;
33901 +       int ret;
33902 +       int ptr;
33903 +
33904 +       s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
33905 +
33906 +       clkp = init_clocks;
33907 +       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
33908 +               ret = s3c24xx_register_clock(clkp);
33909 +               if (ret < 0) {
33910 +                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
33911 +                              clkp->name, ret);
33912 +               }
33913 +       }
33914 +
33915 +       clkp = init_clocks_disable;
33916 +       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
33917 +
33918 +               ret = s3c24xx_register_clock(clkp);
33919 +               if (ret < 0) {
33920 +                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
33921 +                              clkp->name, ret);
33922 +               }
33923 +
33924 +               (clkp->enable)(clkp, 0);
33925 +       }
33926 +
33927 +       s3c_pwmclk_init();
33928 +}
33929 --- /dev/null
33930 +++ b/arch/arm/plat-s3c64xx/cpu.c
33931 @@ -0,0 +1,139 @@
33932 +/* linux/arch/arm/plat-s3c64xx/cpu.c
33933 + *
33934 + * Copyright 2008 Openmoko, Inc.
33935 + * Copyright 2008 Simtec Electronics
33936 + *     Ben Dooks <ben@simtec.co.uk>
33937 + *     http://armlinux.simtec.co.uk/
33938 + *
33939 + * S3C64XX CPU Support
33940 + *
33941 + * This program is free software; you can redistribute it and/or modify
33942 + * it under the terms of the GNU General Public License version 2 as
33943 + * published by the Free Software Foundation.
33944 +*/
33945 +
33946 +#include <linux/init.h>
33947 +#include <linux/module.h>
33948 +#include <linux/interrupt.h>
33949 +#include <linux/ioport.h>
33950 +#include <linux/sysdev.h>
33951 +#include <linux/serial_core.h>
33952 +#include <linux/platform_device.h>
33953 +#include <linux/delay.h>
33954 +#include <linux/io.h>
33955 +
33956 +#include <mach/hardware.h>
33957 +#include <mach/map.h>
33958 +
33959 +#include <asm/mach/arch.h>
33960 +#include <asm/mach/map.h>
33961 +
33962 +#include <plat/regs-serial.h>
33963 +
33964 +#include <plat/cpu.h>
33965 +#include <plat/devs.h>
33966 +#include <plat/clock.h>
33967 +
33968 +#include <plat/s3c6400.h>
33969 +#include <plat/s3c6410.h>
33970 +
33971 +/* table of supported CPUs */
33972 +
33973 +static const char name_s3c6400[] = "S3C6400";
33974 +static const char name_s3c6410[] = "S3C6410";
33975 +
33976 +static struct cpu_table cpu_ids[] __initdata = {
33977 +       {
33978 +               .idcode         = 0x36400000,
33979 +               .idmask         = 0xfffff000,
33980 +               .map_io         = s3c6400_map_io,
33981 +               .init_clocks    = s3c6400_init_clocks,
33982 +               .init_uarts     = s3c6400_init_uarts,
33983 +               .init           = s3c6400_init,
33984 +               .name           = name_s3c6400,
33985 +       }, {
33986 +               .idcode         = 0x36410100,
33987 +               .idmask         = 0xffffff00,
33988 +               .map_io         = s3c6410_map_io,
33989 +               .init_clocks    = s3c6410_init_clocks,
33990 +               .init_uarts     = s3c6410_init_uarts,
33991 +               .init           = s3c6410_init,
33992 +               .name           = name_s3c6410,
33993 +       },
33994 +};
33995 +
33996 +/* minimal IO mapping */
33997 +
33998 +/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
33999 +#define UART_OFFS (S3C_PA_UART & 0xfffff)
34000 +
34001 +static struct map_desc s3c_iodesc[] __initdata = {
34002 +       {
34003 +               .virtual        = (unsigned long)S3C_VA_SYS,
34004 +               .pfn            = __phys_to_pfn(S3C64XX_PA_SYSCON),
34005 +               .length         = SZ_4K,
34006 +               .type           = MT_DEVICE,
34007 +       }, {
34008 +               .virtual        = (unsigned long)(S3C_VA_UART + UART_OFFS),
34009 +               .pfn            = __phys_to_pfn(S3C_PA_UART),
34010 +               .length         = SZ_4K,
34011 +               .type           = MT_DEVICE,
34012 +       }, {
34013 +               .virtual        = (unsigned long)S3C_VA_VIC0,
34014 +               .pfn            = __phys_to_pfn(S3C64XX_PA_VIC0),
34015 +               .length         = SZ_16K,
34016 +               .type           = MT_DEVICE,
34017 +       }, {
34018 +               .virtual        = (unsigned long)S3C_VA_VIC1,
34019 +               .pfn            = __phys_to_pfn(S3C64XX_PA_VIC1),
34020 +               .length         = SZ_16K,
34021 +               .type           = MT_DEVICE,
34022 +       }, {
34023 +               .virtual        = (unsigned long)S3C_VA_TIMER,
34024 +               .pfn            = __phys_to_pfn(S3C_PA_TIMER),
34025 +               .length         = SZ_16K,
34026 +               .type           = MT_DEVICE,
34027 +       }, {
34028 +               .virtual        = (unsigned long)S3C64XX_VA_GPIO,
34029 +               .pfn            = __phys_to_pfn(S3C64XX_PA_GPIO),
34030 +               .length         = SZ_4K,
34031 +               .type           = MT_DEVICE,
34032 +       }, {
34033 +               .virtual        = (unsigned long)S3C64XX_VA_MODEM,
34034 +               .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
34035 +               .length         = SZ_4K,
34036 +               .type           = MT_DEVICE,
34037 +       },
34038 +};
34039 +
34040 +
34041 +struct sysdev_class s3c64xx_sysclass = {
34042 +       .name   = "s3c64xx-core",
34043 +};
34044 +
34045 +static struct sys_device s3c64xx_sysdev = {
34046 +       .cls    = &s3c64xx_sysclass,
34047 +};
34048 +
34049 +
34050 +/* read cpu identification code */
34051 +
34052 +void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
34053 +{
34054 +       unsigned long idcode;
34055 +
34056 +       /* initialise the io descriptors we need for initialisation */
34057 +       iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
34058 +       iotable_init(mach_desc, size);
34059 +
34060 +       idcode = __raw_readl(S3C_VA_SYS + 0x118);
34061 +       s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
34062 +}
34063 +
34064 +static __init int s3c64xx_sysdev_init(void)
34065 +{
34066 +       sysdev_class_register(&s3c64xx_sysclass);
34067 +       return sysdev_register(&s3c64xx_sysdev);
34068 +}
34069 +
34070 +core_initcall(s3c64xx_sysdev_init);
34071 --- /dev/null
34072 +++ b/arch/arm/plat-s3c64xx/dev-uart.c
34073 @@ -0,0 +1,176 @@
34074 +/* linux/arch/arm/plat-s3c64xx/dev-uart.c
34075 + *
34076 + * Copyright 2008 Openmoko, Inc.
34077 + * Copyright 2008 Simtec Electronics
34078 + *     Ben Dooks <ben@simtec.co.uk>
34079 + *     http://armlinux.simtec.co.uk/
34080 + *
34081 + * Base S3C64XX UART resource and device definitions
34082 + *
34083 + * This program is free software; you can redistribute it and/or modify
34084 + * it under the terms of the GNU General Public License version 2 as
34085 + * published by the Free Software Foundation.
34086 + *
34087 +*/
34088 +
34089 +#include <linux/kernel.h>
34090 +#include <linux/types.h>
34091 +#include <linux/interrupt.h>
34092 +#include <linux/list.h>
34093 +#include <linux/platform_device.h>
34094 +
34095 +#include <asm/mach/arch.h>
34096 +#include <asm/mach/irq.h>
34097 +#include <mach/hardware.h>
34098 +#include <mach/map.h>
34099 +
34100 +#include <plat/devs.h>
34101 +
34102 +/* Serial port registrations */
34103 +
34104 +/* 64xx uarts are closer together */
34105 +
34106 +static struct resource s3c64xx_uart0_resource[] = {
34107 +       [0] = {
34108 +               .start  = S3C_PA_UART0,
34109 +               .end    = S3C_PA_UART0 + 0x100,
34110 +               .flags  = IORESOURCE_MEM,
34111 +       },
34112 +       [1] = {
34113 +               .start  = IRQ_S3CUART_RX0,
34114 +               .end    = IRQ_S3CUART_RX0,
34115 +               .flags  = IORESOURCE_IRQ,
34116 +       },
34117 +       [2] = {
34118 +               .start  = IRQ_S3CUART_TX0,
34119 +               .end    = IRQ_S3CUART_TX0,
34120 +               .flags  = IORESOURCE_IRQ,
34121 +
34122 +       },
34123 +       [3] = {
34124 +               .start  = IRQ_S3CUART_ERR0,
34125 +               .end    = IRQ_S3CUART_ERR0,
34126 +               .flags  = IORESOURCE_IRQ,
34127 +       }
34128 +};
34129 +
34130 +static struct resource s3c64xx_uart1_resource[] = {
34131 +       [0] = {
34132 +               .start = S3C_PA_UART1,
34133 +               .end   = S3C_PA_UART1 + 0x100,
34134 +               .flags = IORESOURCE_MEM,
34135 +       },
34136 +       [1] = {
34137 +               .start  = IRQ_S3CUART_RX1,
34138 +               .end    = IRQ_S3CUART_RX1,
34139 +               .flags  = IORESOURCE_IRQ,
34140 +       },
34141 +       [2] = {
34142 +               .start  = IRQ_S3CUART_TX1,
34143 +               .end    = IRQ_S3CUART_TX1,
34144 +               .flags  = IORESOURCE_IRQ,
34145 +
34146 +       },
34147 +       [3] = {
34148 +               .start  = IRQ_S3CUART_ERR1,
34149 +               .end    = IRQ_S3CUART_ERR1,
34150 +               .flags  = IORESOURCE_IRQ,
34151 +       },
34152 +};
34153 +
34154 +static struct resource s3c6xx_uart2_resource[] = {
34155 +       [0] = {
34156 +               .start = S3C_PA_UART2,
34157 +               .end   = S3C_PA_UART2 + 0x100,
34158 +               .flags = IORESOURCE_MEM,
34159 +       },
34160 +       [1] = {
34161 +               .start  = IRQ_S3CUART_RX2,
34162 +               .end    = IRQ_S3CUART_RX2,
34163 +               .flags  = IORESOURCE_IRQ,
34164 +       },
34165 +       [2] = {
34166 +               .start  = IRQ_S3CUART_TX2,
34167 +               .end    = IRQ_S3CUART_TX2,
34168 +               .flags  = IORESOURCE_IRQ,
34169 +
34170 +       },
34171 +       [3] = {
34172 +               .start  = IRQ_S3CUART_ERR2,
34173 +               .end    = IRQ_S3CUART_ERR2,
34174 +               .flags  = IORESOURCE_IRQ,
34175 +       },
34176 +};
34177 +
34178 +static struct resource s3c64xx_uart3_resource[] = {
34179 +       [0] = {
34180 +               .start = S3C_PA_UART3,
34181 +               .end   = S3C_PA_UART3 + 0x100,
34182 +               .flags = IORESOURCE_MEM,
34183 +       },
34184 +       [1] = {
34185 +               .start  = IRQ_S3CUART_RX3,
34186 +               .end    = IRQ_S3CUART_RX3,
34187 +               .flags  = IORESOURCE_IRQ,
34188 +       },
34189 +       [2] = {
34190 +               .start  = IRQ_S3CUART_TX3,
34191 +               .end    = IRQ_S3CUART_TX3,
34192 +               .flags  = IORESOURCE_IRQ,
34193 +
34194 +       },
34195 +       [3] = {
34196 +               .start  = IRQ_S3CUART_ERR3,
34197 +               .end    = IRQ_S3CUART_ERR3,
34198 +               .flags  = IORESOURCE_IRQ,
34199 +       },
34200 +};
34201 +
34202 +
34203 +struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = {
34204 +       [0] = {
34205 +               .resources      = s3c64xx_uart0_resource,
34206 +               .nr_resources   = ARRAY_SIZE(s3c64xx_uart0_resource),
34207 +       },
34208 +       [1] = {
34209 +               .resources      = s3c64xx_uart1_resource,
34210 +               .nr_resources   = ARRAY_SIZE(s3c64xx_uart1_resource),
34211 +       },
34212 +       [2] = {
34213 +               .resources      = s3c6xx_uart2_resource,
34214 +               .nr_resources   = ARRAY_SIZE(s3c6xx_uart2_resource),
34215 +       },
34216 +       [3] = {
34217 +               .resources      = s3c64xx_uart3_resource,
34218 +               .nr_resources   = ARRAY_SIZE(s3c64xx_uart3_resource),
34219 +       },
34220 +};
34221 +
34222 +/* uart devices */
34223 +
34224 +static struct platform_device s3c24xx_uart_device0 = {
34225 +       .id             = 0,
34226 +};
34227 +
34228 +static struct platform_device s3c24xx_uart_device1 = {
34229 +       .id             = 1,
34230 +};
34231 +
34232 +static struct platform_device s3c24xx_uart_device2 = {
34233 +       .id             = 2,
34234 +};
34235 +
34236 +static struct platform_device s3c24xx_uart_device3 = {
34237 +       .id             = 3,
34238 +};
34239 +
34240 +struct platform_device *s3c24xx_uart_src[4] = {
34241 +       &s3c24xx_uart_device0,
34242 +       &s3c24xx_uart_device1,
34243 +       &s3c24xx_uart_device2,
34244 +       &s3c24xx_uart_device3,
34245 +};
34246 +
34247 +struct platform_device *s3c24xx_uart_devs[4] = {
34248 +};
34249 +
34250 --- /dev/null
34251 +++ b/arch/arm/plat-s3c64xx/gpiolib.c
34252 @@ -0,0 +1,428 @@
34253 +/* arch/arm/plat-s3c64xx/gpiolib.c
34254 + *
34255 + * Copyright 2008 Openmoko, Inc.
34256 + * Copyright 2008 Simtec Electronics
34257 + *      Ben Dooks <ben@simtec.co.uk>
34258 + *      http://armlinux.simtec.co.uk/
34259 + *
34260 + * S3C64XX - GPIOlib support
34261 + *
34262 + * This program is free software; you can redistribute it and/or modify
34263 + * it under the terms of the GNU General Public License version 2 as
34264 + * published by the Free Software Foundation.
34265 + */
34266 +
34267 +#include <linux/kernel.h>
34268 +#include <linux/irq.h>
34269 +#include <linux/io.h>
34270 +
34271 +#include <mach/map.h>
34272 +#include <mach/gpio.h>
34273 +#include <mach/gpio-core.h>
34274 +
34275 +#include <plat/gpio-cfg.h>
34276 +#include <plat/gpio-cfg-helpers.h>
34277 +#include <plat/regs-gpio.h>
34278 +
34279 +/* GPIO bank summary:
34280 + *
34281 + * Bank        GPIOs   Style   SlpCon  ExtInt Group
34282 + * A   8       4Bit    Yes     1
34283 + * B   7       4Bit    Yes     1
34284 + * C   8       4Bit    Yes     2
34285 + * D   5       4Bit    Yes     3
34286 + * E   5       4Bit    Yes     None
34287 + * F   16      2Bit    Yes     4 [1]
34288 + * G   7       4Bit    Yes     5
34289 + * H   10      4Bit[2] Yes     6
34290 + * I   16      2Bit    Yes     None
34291 + * J   12      2Bit    Yes     None
34292 + * K   16      4Bit[2] No      None
34293 + * L   15      4Bit[2] No      None
34294 + * M   6       4Bit    No      IRQ_EINT
34295 + * N   16      2Bit    No      IRQ_EINT
34296 + * O   16      2Bit    Yes     7
34297 + * P   15      2Bit    Yes     8
34298 + * Q   9       2Bit    Yes     9
34299 + *
34300 + * [1] BANKF pins 14,15 do not form part of the external interrupt sources
34301 + * [2] BANK has two control registers, GPxCON0 and GPxCON1
34302 + */
34303 +
34304 +#define OFF_GPCON      (0x00)
34305 +#define OFF_GPDAT      (0x04)
34306 +
34307 +#define con_4bit_shift(__off) ((__off) * 4)
34308 +
34309 +#if 1
34310 +#define gpio_dbg(x...) do { } while(0)
34311 +#else
34312 +#define gpio_dbg(x...) printk(KERN_DEBUG ## x)
34313 +#endif
34314 +
34315 +/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
34316 + * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
34317 + * following example:
34318 + *
34319 + * base + 0x00: Control register, 4 bits per gpio
34320 + *             gpio n: 4 bits starting at (4*n)
34321 + *             0000 = input, 0001 = output, others mean special-function
34322 + * base + 0x04: Data register, 1 bit per gpio
34323 + *             bit n: data bit n
34324 + *
34325 + * Note, since the data register is one bit per gpio and is at base + 0x4
34326 + * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
34327 + * the output.
34328 +*/
34329 +
34330 +static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset)
34331 +{
34332 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
34333 +       void __iomem *base = ourchip->base;
34334 +       unsigned long con;
34335 +
34336 +       con = __raw_readl(base + OFF_GPCON);
34337 +       con &= ~(0xf << con_4bit_shift(offset));
34338 +       __raw_writel(con, base + OFF_GPCON);
34339 +
34340 +       gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
34341 +
34342 +       return 0;
34343 +}
34344 +
34345 +static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip,
34346 +                                      unsigned offset, int value)
34347 +{
34348 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
34349 +       void __iomem *base = ourchip->base;
34350 +       unsigned long con;
34351 +       unsigned long dat;
34352 +
34353 +       con = __raw_readl(base + OFF_GPCON);
34354 +       con &= ~(0xf << con_4bit_shift(offset));
34355 +       con |= 0x1 << con_4bit_shift(offset);
34356 +
34357 +       dat = __raw_readl(base + OFF_GPDAT);
34358 +       if (value)
34359 +               dat |= 1 << offset;
34360 +       else
34361 +               dat &= ~(1 << offset);
34362 +
34363 +       __raw_writel(dat, base + OFF_GPDAT);
34364 +       __raw_writel(con, base + OFF_GPCON);
34365 +       __raw_writel(dat, base + OFF_GPDAT);
34366 +
34367 +       gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
34368 +
34369 +       return 0;
34370 +}
34371 +
34372 +/* The next set of routines are for the case where the GPIO configuration
34373 + * registers are 4 bits per GPIO but there is more than one register (the
34374 + * bank has more than 8 GPIOs.
34375 + *
34376 + * This case is the similar to the 4 bit case, but the registers are as
34377 + * follows:
34378 + *
34379 + * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
34380 + *             gpio n: 4 bits starting at (4*n)
34381 + *             0000 = input, 0001 = output, others mean special-function
34382 + * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
34383 + *             gpio n: 4 bits starting at (4*n)
34384 + *             0000 = input, 0001 = output, others mean special-function
34385 + * base + 0x08: Data register, 1 bit per gpio
34386 + *             bit n: data bit n
34387 + *
34388 + * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
34389 + * store the 'base + 0x4' address so that these routines see the data
34390 + * register at ourchip->base + 0x04.
34391 +*/
34392 +
34393 +static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset)
34394 +{
34395 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
34396 +       void __iomem *base = ourchip->base;
34397 +       void __iomem *regcon = base;
34398 +       unsigned long con;
34399 +
34400 +       if (offset > 7)
34401 +               offset -= 8;
34402 +       else
34403 +               regcon -= 4;
34404 +
34405 +       con = __raw_readl(regcon);
34406 +       con &= ~(0xf << con_4bit_shift(offset));
34407 +       __raw_writel(con, regcon);
34408 +
34409 +       gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
34410 +
34411 +       return 0;
34412 +
34413 +}
34414 +
34415 +static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip,
34416 +                                      unsigned offset, int value)
34417 +{
34418 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
34419 +       void __iomem *base = ourchip->base;
34420 +       void __iomem *regcon = base;
34421 +       unsigned long con;
34422 +       unsigned long dat;
34423 +
34424 +       if (offset > 7)
34425 +               offset -= 8;
34426 +       else
34427 +               regcon -= 4;
34428 +
34429 +       con = __raw_readl(regcon);
34430 +       con &= ~(0xf << con_4bit_shift(offset));
34431 +       con |= 0x1 << con_4bit_shift(offset);
34432 +
34433 +       dat = __raw_readl(base + OFF_GPDAT);
34434 +       if (value)
34435 +               dat |= 1 << offset;
34436 +       else
34437 +               dat &= ~(1 << offset);
34438 +
34439 +       __raw_writel(dat, base + OFF_GPDAT);
34440 +       __raw_writel(con, regcon);
34441 +       __raw_writel(dat, base + OFF_GPDAT);
34442 +
34443 +       gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
34444 +
34445 +       return 0;
34446 +}
34447 +
34448 +static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
34449 +       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
34450 +       .set_pull       = s3c_gpio_setpull_updown,
34451 +       .get_pull       = s3c_gpio_getpull_updown,
34452 +};
34453 +
34454 +static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
34455 +       .cfg_eint       = 7,
34456 +       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
34457 +       .set_pull       = s3c_gpio_setpull_updown,
34458 +       .get_pull       = s3c_gpio_getpull_updown,
34459 +};
34460 +
34461 +static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
34462 +       .cfg_eint       = 3,
34463 +       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
34464 +       .set_pull       = s3c_gpio_setpull_updown,
34465 +       .get_pull       = s3c_gpio_getpull_updown,
34466 +};
34467 +
34468 +static struct s3c_gpio_chip gpio_4bit[] = {
34469 +       {
34470 +               .base   = S3C64XX_GPA_BASE,
34471 +               .config = &gpio_4bit_cfg_eint0111,
34472 +               .chip   = {
34473 +                       .base   = S3C64XX_GPA(0),
34474 +                       .ngpio  = S3C64XX_GPIO_A_NR,
34475 +                       .label  = "GPA",
34476 +               },
34477 +       }, {
34478 +               .base   = S3C64XX_GPB_BASE,
34479 +               .config = &gpio_4bit_cfg_eint0111,
34480 +               .chip   = {
34481 +                       .base   = S3C64XX_GPB(0),
34482 +                       .ngpio  = S3C64XX_GPIO_B_NR,
34483 +                       .label  = "GPB",
34484 +               },
34485 +       }, {
34486 +               .base   = S3C64XX_GPC_BASE,
34487 +               .config = &gpio_4bit_cfg_eint0111,
34488 +               .chip   = {
34489 +                       .base   = S3C64XX_GPC(0),
34490 +                       .ngpio  = S3C64XX_GPIO_C_NR,
34491 +                       .label  = "GPC",
34492 +               },
34493 +       }, {
34494 +               .base   = S3C64XX_GPD_BASE,
34495 +               .config = &gpio_4bit_cfg_eint0111,
34496 +               .chip   = {
34497 +                       .base   = S3C64XX_GPD(0),
34498 +                       .ngpio  = S3C64XX_GPIO_D_NR,
34499 +                       .label  = "GPD",
34500 +               },
34501 +       }, {
34502 +               .base   = S3C64XX_GPE_BASE,
34503 +               .config = &gpio_4bit_cfg_noint,
34504 +               .chip   = {
34505 +                       .base   = S3C64XX_GPE(0),
34506 +                       .ngpio  = S3C64XX_GPIO_E_NR,
34507 +                       .label  = "GPE",
34508 +               },
34509 +       }, {
34510 +               .base   = S3C64XX_GPG_BASE,
34511 +               .config = &gpio_4bit_cfg_eint0111,
34512 +               .chip   = {
34513 +                       .base   = S3C64XX_GPG(0),
34514 +                       .ngpio  = S3C64XX_GPIO_G_NR,
34515 +                       .label  = "GPG",
34516 +               },
34517 +       }, {
34518 +               .base   = S3C64XX_GPM_BASE,
34519 +               .config = &gpio_4bit_cfg_eint0011,
34520 +               .chip   = {
34521 +                       .base   = S3C64XX_GPM(0),
34522 +                       .ngpio  = S3C64XX_GPIO_M_NR,
34523 +                       .label  = "GPM",
34524 +               },
34525 +       },
34526 +};
34527 +
34528 +static struct s3c_gpio_chip gpio_4bit2[] = {
34529 +       {
34530 +               .base   = S3C64XX_GPH_BASE + 0x4,
34531 +               .config = &gpio_4bit_cfg_eint0111,
34532 +               .chip   = {
34533 +                       .base   = S3C64XX_GPH(0),
34534 +                       .ngpio  = S3C64XX_GPIO_H_NR,
34535 +                       .label  = "GPH",
34536 +               },
34537 +       }, {
34538 +               .base   = S3C64XX_GPK_BASE + 0x4,
34539 +               .config = &gpio_4bit_cfg_noint,
34540 +               .chip   = {
34541 +                       .base   = S3C64XX_GPK(0),
34542 +                       .ngpio  = S3C64XX_GPIO_K_NR,
34543 +                       .label  = "GPK",
34544 +               },
34545 +       }, {
34546 +               .base   = S3C64XX_GPL_BASE + 0x4,
34547 +               .config = &gpio_4bit_cfg_eint0011,
34548 +               .chip   = {
34549 +                       .base   = S3C64XX_GPL(0),
34550 +                       .ngpio  = S3C64XX_GPIO_L_NR,
34551 +                       .label  = "GPL",
34552 +               },
34553 +       },
34554 +};
34555 +
34556 +static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
34557 +       .set_config     = s3c_gpio_setcfg_s3c24xx,
34558 +       .set_pull       = s3c_gpio_setpull_updown,
34559 +       .get_pull       = s3c_gpio_getpull_updown,
34560 +};
34561 +
34562 +static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
34563 +       .cfg_eint       = 2,
34564 +       .set_config     = s3c_gpio_setcfg_s3c24xx,
34565 +       .set_pull       = s3c_gpio_setpull_updown,
34566 +       .get_pull       = s3c_gpio_getpull_updown,
34567 +};
34568 +
34569 +static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
34570 +       .cfg_eint       = 3,
34571 +       .set_config     = s3c_gpio_setcfg_s3c24xx,
34572 +       .set_pull       = s3c_gpio_setpull_updown,
34573 +       .get_pull       = s3c_gpio_getpull_updown,
34574 +};
34575 +
34576 +static struct s3c_gpio_chip gpio_2bit[] = {
34577 +       {
34578 +               .base   = S3C64XX_GPF_BASE,
34579 +               .config = &gpio_2bit_cfg_eint11,
34580 +               .chip   = {
34581 +                       .base   = S3C64XX_GPF(0),
34582 +                       .ngpio  = S3C64XX_GPIO_F_NR,
34583 +                       .label  = "GPF",
34584 +               },
34585 +       }, {
34586 +               .base   = S3C64XX_GPI_BASE,
34587 +               .config = &gpio_2bit_cfg_noint,
34588 +               .chip   = {
34589 +                       .base   = S3C64XX_GPI(0),
34590 +                       .ngpio  = S3C64XX_GPIO_I_NR,
34591 +                       .label  = "GPI",
34592 +               },
34593 +       }, {
34594 +               .base   = S3C64XX_GPJ_BASE,
34595 +               .config = &gpio_2bit_cfg_noint,
34596 +               .chip   = {
34597 +                       .base   = S3C64XX_GPJ(0),
34598 +                       .ngpio  = S3C64XX_GPIO_J_NR,
34599 +                       .label  = "GPJ",
34600 +               },
34601 +       }, {
34602 +               .base   = S3C64XX_GPN_BASE,
34603 +               .config = &gpio_2bit_cfg_eint10,
34604 +               .chip   = {
34605 +                       .base   = S3C64XX_GPN(0),
34606 +                       .ngpio  = S3C64XX_GPIO_N_NR,
34607 +                       .label  = "GPN",
34608 +               },
34609 +       }, {
34610 +               .base   = S3C64XX_GPO_BASE,
34611 +               .config = &gpio_2bit_cfg_eint11,
34612 +               .chip   = {
34613 +                       .base   = S3C64XX_GPO(0),
34614 +                       .ngpio  = S3C64XX_GPIO_O_NR,
34615 +                       .label  = "GPO",
34616 +               },
34617 +       }, {
34618 +               .base   = S3C64XX_GPP_BASE,
34619 +               .config = &gpio_2bit_cfg_eint11,
34620 +               .chip   = {
34621 +                       .base   = S3C64XX_GPP(0),
34622 +                       .ngpio  = S3C64XX_GPIO_P_NR,
34623 +                       .label  = "GPP",
34624 +               },
34625 +       }, {
34626 +               .base   = S3C64XX_GPQ_BASE,
34627 +               .config = &gpio_2bit_cfg_eint11,
34628 +               .chip   = {
34629 +                       .base   = S3C64XX_GPQ(0),
34630 +                       .ngpio  = S3C64XX_GPIO_Q_NR,
34631 +                       .label  = "GPQ",
34632 +               },
34633 +       },
34634 +};
34635 +
34636 +static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
34637 +{
34638 +       chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
34639 +       chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
34640 +       chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
34641 +}
34642 +
34643 +static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
34644 +{
34645 +       chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
34646 +       chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
34647 +       chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
34648 +}
34649 +
34650 +static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
34651 +{
34652 +       chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
34653 +}
34654 +
34655 +static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
34656 +                                      int nr_chips,
34657 +                                      void (*fn)(struct s3c_gpio_chip *))
34658 +{
34659 +       for (; nr_chips > 0; nr_chips--, chips++) {
34660 +               if (fn)
34661 +                       (fn)(chips);
34662 +               s3c_gpiolib_add(chips);
34663 +       }
34664 +}
34665 +
34666 +static __init int s3c64xx_gpiolib_init(void)
34667 +{
34668 +       s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
34669 +                           s3c64xx_gpiolib_add_4bit);
34670 +
34671 +       s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
34672 +                           s3c64xx_gpiolib_add_4bit2);
34673 +
34674 +       s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
34675 +                           s3c64xx_gpiolib_add_2bit);
34676 +
34677 +       return 0;
34678 +}
34679 +
34680 +arch_initcall(s3c64xx_gpiolib_init);
34681 --- /dev/null
34682 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
34683 @@ -0,0 +1,48 @@
34684 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
34685 + *
34686 + * Copyright 2008 Openmoko, Inc.
34687 + * Copyright 2008 Simtec Electronics
34688 + *     Ben Dooks <ben@simtec.co.uk>
34689 + *     http://armlinux.simtec.co.uk/
34690 + *
34691 + * GPIO Bank A register and configuration definitions
34692 + *
34693 + * This program is free software; you can redistribute it and/or modify
34694 + * it under the terms of the GNU General Public License version 2 as
34695 + * published by the Free Software Foundation.
34696 +*/
34697 +
34698 +#define S3C64XX_GPACON                 (S3C64XX_GPA_BASE + 0x00)
34699 +#define S3C64XX_GPADAT                 (S3C64XX_GPA_BASE + 0x04)
34700 +#define S3C64XX_GPAPUD                 (S3C64XX_GPA_BASE + 0x08)
34701 +#define S3C64XX_GPACONSLP              (S3C64XX_GPA_BASE + 0x0c)
34702 +#define S3C64XX_GPAPUDSLP              (S3C64XX_GPA_BASE + 0x10)
34703 +
34704 +#define S3C64XX_GPA_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
34705 +#define S3C64XX_GPA_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
34706 +#define S3C64XX_GPA_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
34707 +
34708 +#define S3C64XX_GPA0_UART_RXD0         (0x02 << 0)
34709 +#define S3C64XX_GPA0_EINT_G1_0         (0x07 << 0)
34710 +
34711 +#define S3C64XX_GPA1_UART_TXD0         (0x02 << 4)
34712 +#define S3C64XX_GPA1_EINT_G1_1         (0x07 << 4)
34713 +
34714 +#define S3C64XX_GPA2_UART_nCTS0                (0x02 << 8)
34715 +#define S3C64XX_GPA2_EINT_G1_2         (0x07 << 8)
34716 +
34717 +#define S3C64XX_GPA3_UART_nRTS0                (0x02 << 12)
34718 +#define S3C64XX_GPA3_EINT_G1_3         (0x07 << 12)
34719 +
34720 +#define S3C64XX_GPA4_UART_RXD1         (0x02 << 16)
34721 +#define S3C64XX_GPA4_EINT_G1_4         (0x07 << 16)
34722 +
34723 +#define S3C64XX_GPA5_UART_TXD1         (0x02 << 20)
34724 +#define S3C64XX_GPA5_EINT_G1_5         (0x07 << 20)
34725 +
34726 +#define S3C64XX_GPA6_UART_nCTS1                (0x02 << 24)
34727 +#define S3C64XX_GPA6_EINT_G1_6         (0x07 << 24)
34728 +
34729 +#define S3C64XX_GPA7_UART_nRTS1                (0x02 << 28)
34730 +#define S3C64XX_GPA7_EINT_G1_7         (0x07 << 28)
34731 +
34732 --- /dev/null
34733 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
34734 @@ -0,0 +1,60 @@
34735 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
34736 + *
34737 + * Copyright 2008 Openmoko, Inc.
34738 + * Copyright 2008 Simtec Electronics
34739 + *     Ben Dooks <ben@simtec.co.uk>
34740 + *     http://armlinux.simtec.co.uk/
34741 + *
34742 + * GPIO Bank B register and configuration definitions
34743 + *
34744 + * This program is free software; you can redistribute it and/or modify
34745 + * it under the terms of the GNU General Public License version 2 as
34746 + * published by the Free Software Foundation.
34747 +*/
34748 +
34749 +#define S3C64XX_GPBCON                 (S3C64XX_GPB_BASE + 0x00)
34750 +#define S3C64XX_GPBDAT                 (S3C64XX_GPB_BASE + 0x04)
34751 +#define S3C64XX_GPBPUD                 (S3C64XX_GPB_BASE + 0x08)
34752 +#define S3C64XX_GPBCONSLP              (S3C64XX_GPB_BASE + 0x0c)
34753 +#define S3C64XX_GPBPUDSLP              (S3C64XX_GPB_BASE + 0x10)
34754 +
34755 +#define S3C64XX_GPB_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
34756 +#define S3C64XX_GPB_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
34757 +#define S3C64XX_GPB_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
34758 +
34759 +#define S3C64XX_GPB0_UART_RXD2         (0x02 << 0)
34760 +#define S3C64XX_GPB0_EXTDMA_REQ                (0x03 << 0)
34761 +#define S3C64XX_GPB0_IrDA_RXD          (0x04 << 0)
34762 +#define S3C64XX_GPB0_ADDR_CF0          (0x05 << 0)
34763 +#define S3C64XX_GPB0_EINT_G1_8         (0x07 << 0)
34764 +
34765 +#define S3C64XX_GPB1_UART_TXD2         (0x02 << 4)
34766 +#define S3C64XX_GPB1_EXTDMA_ACK                (0x03 << 4)
34767 +#define S3C64XX_GPB1_IrDA_TXD          (0x04 << 4)
34768 +#define S3C64XX_GPB1_ADDR_CF1          (0x05 << 4)
34769 +#define S3C64XX_GPB1_EINT_G1_9         (0x07 << 4)
34770 +
34771 +#define S3C64XX_GPB2_UART_RXD3         (0x02 << 8)
34772 +#define S3C64XX_GPB2_IrDA_RXD          (0x03 << 8)
34773 +#define S3C64XX_GPB2_EXTDMA_REQ                (0x04 << 8)
34774 +#define S3C64XX_GPB2_ADDR_CF2          (0x05 << 8)
34775 +#define S3C64XX_GPB2_I2C_SCL1          (0x06 << 8)
34776 +#define S3C64XX_GPB2_EINT_G1_10                (0x07 << 8)
34777 +
34778 +#define S3C64XX_GPB3_UART_TXD3         (0x02 << 12)
34779 +#define S3C64XX_GPB3_IrDA_TXD          (0x03 << 12)
34780 +#define S3C64XX_GPB3_EXTDMA_ACK                (0x04 << 12)
34781 +#define S3C64XX_GPB3_I2C_SDA1          (0x06 << 12)
34782 +#define S3C64XX_GPB3_EINT_G1_11                (0x07 << 12)
34783 +
34784 +#define S3C64XX_GPB4_IrDA_SDBW         (0x02 << 16)
34785 +#define S3C64XX_GPB4_CAM_FIELD         (0x03 << 16)
34786 +#define S3C64XX_GPB4_CF_DATA_DIR       (0x04 << 16)
34787 +#define S3C64XX_GPB4_EINT_G1_12                (0x07 << 16)
34788 +
34789 +#define S3C64XX_GPB5_I2C_SCL0          (0x02 << 20)
34790 +#define S3C64XX_GPB5_EINT_G1_13                (0x07 << 20)
34791 +
34792 +#define S3C64XX_GPB6_I2C_SDA0          (0x02 << 24)
34793 +#define S3C64XX_GPB6_EINT_G1_14                (0x07 << 24)
34794 +
34795 --- /dev/null
34796 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
34797 @@ -0,0 +1,53 @@
34798 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
34799 + *
34800 + * Copyright 2008 Openmoko, Inc.
34801 + * Copyright 2008 Simtec Electronics
34802 + *     Ben Dooks <ben@simtec.co.uk>
34803 + *     http://armlinux.simtec.co.uk/
34804 + *
34805 + * GPIO Bank C register and configuration definitions
34806 + *
34807 + * This program is free software; you can redistribute it and/or modify
34808 + * it under the terms of the GNU General Public License version 2 as
34809 + * published by the Free Software Foundation.
34810 +*/
34811 +
34812 +#define S3C64XX_GPCCON                 (S3C64XX_GPC_BASE + 0x00)
34813 +#define S3C64XX_GPCDAT                 (S3C64XX_GPC_BASE + 0x04)
34814 +#define S3C64XX_GPCPUD                 (S3C64XX_GPC_BASE + 0x08)
34815 +#define S3C64XX_GPCCONSLP              (S3C64XX_GPC_BASE + 0x0c)
34816 +#define S3C64XX_GPCPUDSLP              (S3C64XX_GPC_BASE + 0x10)
34817 +
34818 +#define S3C64XX_GPC_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
34819 +#define S3C64XX_GPC_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
34820 +#define S3C64XX_GPC_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
34821 +
34822 +#define S3C64XX_GPC0_SPI_MISO0         (0x02 << 0)
34823 +#define S3C64XX_GPC0_EINT_G2_0         (0x07 << 0)
34824 +
34825 +#define S3C64XX_GPC1_SPI_CLKO          (0x02 << 4)
34826 +#define S3C64XX_GPC1_EINT_G2_1         (0x07 << 4)
34827 +
34828 +#define S3C64XX_GPC2_SPI_MOSIO         (0x02 << 8)
34829 +#define S3C64XX_GPC2_EINT_G2_2         (0x07 << 8)
34830 +
34831 +#define S3C64XX_GPC3_SPI_nCSO          (0x02 << 12)
34832 +#define S3C64XX_GPC3_EINT_G2_3         (0x07 << 12)
34833 +
34834 +#define S3C64XX_GPC4_SPI_MISO1         (0x02 << 16)
34835 +#define S3C64XX_GPC4_MMC2_CMD          (0x03 << 16)
34836 +#define S3C64XX_GPC4_I2S0_V40_DO       (0x05 << 16)
34837 +#define S3C64XX_GPC4_EINT_G2_4         (0x07 << 16)
34838 +
34839 +#define S3C64XX_GPC5_SPI_CLK1          (0x02 << 20)
34840 +#define S3C64XX_GPC5_MMC2_CLK          (0x03 << 20)
34841 +#define S3C64XX_GPC5_I2S1_V40_DO       (0x05 << 20)
34842 +#define S3C64XX_GPC5_EINT_G2_5         (0x07 << 20)
34843 +
34844 +#define S3C64XX_GPC6_SPI_MOSI1         (0x02 << 24)
34845 +#define S3C64XX_GPC6_EINT_G2_6         (0x07 << 24)
34846 +
34847 +#define S3C64XX_GPC7_SPI_nCS1          (0x02 << 28)
34848 +#define S3C64XX_GPC7_I2S2_V40_DO       (0x05 << 28)
34849 +#define S3C64XX_GPC7_EINT_G2_7         (0x07 << 28)
34850 +
34851 --- /dev/null
34852 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
34853 @@ -0,0 +1,49 @@
34854 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
34855 + *
34856 + * Copyright 2008 Openmoko, Inc.
34857 + * Copyright 2008 Simtec Electronics
34858 + *     Ben Dooks <ben@simtec.co.uk>
34859 + *     http://armlinux.simtec.co.uk/
34860 + *
34861 + * GPIO Bank D register and configuration definitions
34862 + *
34863 + * This program is free software; you can redistribute it and/or modify
34864 + * it under the terms of the GNU General Public License version 2 as
34865 + * published by the Free Software Foundation.
34866 +*/
34867 +
34868 +#define S3C64XX_GPDCON                 (S3C64XX_GPD_BASE + 0x00)
34869 +#define S3C64XX_GPDDAT                 (S3C64XX_GPD_BASE + 0x04)
34870 +#define S3C64XX_GPDPUD                 (S3C64XX_GPD_BASE + 0x08)
34871 +#define S3C64XX_GPDCONSLP              (S3C64XX_GPD_BASE + 0x0c)
34872 +#define S3C64XX_GPDPUDSLP              (S3C64XX_GPD_BASE + 0x10)
34873 +
34874 +#define S3C64XX_GPD_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
34875 +#define S3C64XX_GPD_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
34876 +#define S3C64XX_GPD_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
34877 +
34878 +#define S3C64XX_GPD0_PCM0_SCLK         (0x02 << 0)
34879 +#define S3C64XX_GPD0_I2S0_CLK          (0x03 << 0)
34880 +#define S3C64XX_GPD0_AC97_BITCLK       (0x04 << 0)
34881 +#define S3C64XX_GPD0_EINT_G3_0         (0x07 << 0)
34882 +
34883 +#define S3C64XX_GPD1_PCM0_EXTCLK       (0x02 << 4)
34884 +#define S3C64XX_GPD1_I2S0_CDCLK                (0x03 << 4)
34885 +#define S3C64XX_GPD1_AC97_nRESET       (0x04 << 4)
34886 +#define S3C64XX_GPD1_EINT_G3_1         (0x07 << 4)
34887 +
34888 +#define S3C64XX_GPD2_PCM0_FSYNC                (0x02 << 8)
34889 +#define S3C64XX_GPD2_I2S0_LRCLK                (0x03 << 8)
34890 +#define S3C64XX_GPD2_AC97_SYNC         (0x04 << 8)
34891 +#define S3C64XX_GPD2_EINT_G3_2         (0x07 << 8)
34892 +
34893 +#define S3C64XX_GPD3_PCM0_SIN          (0x02 << 12)
34894 +#define S3C64XX_GPD3_I2S0_DI           (0x03 << 12)
34895 +#define S3C64XX_GPD3_AC97_SDI          (0x04 << 12)
34896 +#define S3C64XX_GPD3_EINT_G3_3         (0x07 << 12)
34897 +
34898 +#define S3C64XX_GPD4_PCM0_SOUT         (0x02 << 16)
34899 +#define S3C64XX_GPD4_I2S0_D0           (0x03 << 16)
34900 +#define S3C64XX_GPD4_AC97_SDO          (0x04 << 16)
34901 +#define S3C64XX_GPD4_EINT_G3_4         (0x07 << 16)
34902 +
34903 --- /dev/null
34904 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
34905 @@ -0,0 +1,44 @@
34906 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
34907 + *
34908 + * Copyright 2008 Openmoko, Inc.
34909 + * Copyright 2008 Simtec Electronics
34910 + *     Ben Dooks <ben@simtec.co.uk>
34911 + *     http://armlinux.simtec.co.uk/
34912 + *
34913 + * GPIO Bank E register and configuration definitions
34914 + *
34915 + * This program is free software; you can redistribute it and/or modify
34916 + * it under the terms of the GNU General Public License version 2 as
34917 + * published by the Free Software Foundation.
34918 +*/
34919 +
34920 +#define S3C64XX_GPECON                 (S3C64XX_GPE_BASE + 0x00)
34921 +#define S3C64XX_GPEDAT                 (S3C64XX_GPE_BASE + 0x04)
34922 +#define S3C64XX_GPEPUD                 (S3C64XX_GPE_BASE + 0x08)
34923 +#define S3C64XX_GPECONSLP              (S3C64XX_GPE_BASE + 0x0c)
34924 +#define S3C64XX_GPEPUDSLP              (S3C64XX_GPE_BASE + 0x10)
34925 +
34926 +#define S3C64XX_GPE_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
34927 +#define S3C64XX_GPE_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
34928 +#define S3C64XX_GPE_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
34929 +
34930 +#define S3C64XX_GPE0_PCM1_SCLK         (0x02 << 0)
34931 +#define S3C64XX_GPE0_I2S1_CLK          (0x03 << 0)
34932 +#define S3C64XX_GPE0_AC97_BITCLK       (0x04 << 0)
34933 +
34934 +#define S3C64XX_GPE1_PCM1_EXTCLK       (0x02 << 4)
34935 +#define S3C64XX_GPE1_I2S1_CDCLK                (0x03 << 4)
34936 +#define S3C64XX_GPE1_AC97_nRESET       (0x04 << 4)
34937 +
34938 +#define S3C64XX_GPE2_PCM1_FSYNC                (0x02 << 8)
34939 +#define S3C64XX_GPE2_I2S1_LRCLK                (0x03 << 8)
34940 +#define S3C64XX_GPE2_AC97_SYNC         (0x04 << 8)
34941 +
34942 +#define S3C64XX_GPE3_PCM1_SIN          (0x02 << 12)
34943 +#define S3C64XX_GPE3_I2S1_DI           (0x03 << 12)
34944 +#define S3C64XX_GPE3_AC97_SDI          (0x04 << 12)
34945 +
34946 +#define S3C64XX_GPE4_PCM1_SOUT         (0x02 << 16)
34947 +#define S3C64XX_GPE4_I2S1_D0           (0x03 << 16)
34948 +#define S3C64XX_GPE4_AC97_SDO          (0x04 << 16)
34949 +
34950 --- /dev/null
34951 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
34952 @@ -0,0 +1,71 @@
34953 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
34954 + *
34955 + * Copyright 2008 Openmoko, Inc.
34956 + * Copyright 2008 Simtec Electronics
34957 + *     Ben Dooks <ben@simtec.co.uk>
34958 + *     http://armlinux.simtec.co.uk/
34959 + *
34960 + * GPIO Bank F register and configuration definitions
34961 + *
34962 + * This program is free software; you can redistribute it and/or modify
34963 + * it under the terms of the GNU General Public License version 2 as
34964 + * published by the Free Software Foundation.
34965 +*/
34966 +
34967 +#define S3C64XX_GPFCON                 (S3C64XX_GPF_BASE + 0x00)
34968 +#define S3C64XX_GPFDAT                 (S3C64XX_GPF_BASE + 0x04)
34969 +#define S3C64XX_GPFPUD                 (S3C64XX_GPF_BASE + 0x08)
34970 +#define S3C64XX_GPFCONSLP              (S3C64XX_GPF_BASE + 0x0c)
34971 +#define S3C64XX_GPFPUDSLP              (S3C64XX_GPF_BASE + 0x10)
34972 +
34973 +#define S3C64XX_GPF_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
34974 +#define S3C64XX_GPF_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
34975 +#define S3C64XX_GPF_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
34976 +
34977 +#define S3C64XX_GPF0_CAMIF_CLK         (0x02 << 0)
34978 +#define S3C64XX_GPF0_EINT_G4_0         (0x03 << 0)
34979 +
34980 +#define S3C64XX_GPF1_CAMIF_HREF                (0x02 << 2)
34981 +#define S3C64XX_GPF1_EINT_G4_1         (0x03 << 2)
34982 +
34983 +#define S3C64XX_GPF2_CAMIF_PCLK                (0x02 << 4)
34984 +#define S3C64XX_GPF2_EINT_G4_2         (0x03 << 4)
34985 +
34986 +#define S3C64XX_GPF3_CAMIF_nRST                (0x02 << 6)
34987 +#define S3C64XX_GPF3_EINT_G4_3         (0x03 << 6)
34988 +
34989 +#define S3C64XX_GPF4_CAMIF_VSYNC       (0x02 << 8)
34990 +#define S3C64XX_GPF4_EINT_G4_4         (0x03 << 8)
34991 +
34992 +#define S3C64XX_GPF5_CAMIF_YDATA0      (0x02 << 10)
34993 +#define S3C64XX_GPF5_EINT_G4_5         (0x03 << 10)
34994 +
34995 +#define S3C64XX_GPF6_CAMIF_YDATA1      (0x02 << 12)
34996 +#define S3C64XX_GPF6_EINT_G4_6         (0x03 << 12)
34997 +
34998 +#define S3C64XX_GPF7_CAMIF_YDATA2      (0x02 << 14)
34999 +#define S3C64XX_GPF7_EINT_G4_7         (0x03 << 14)
35000 +
35001 +#define S3C64XX_GPF8_CAMIF_YDATA3      (0x02 << 16)
35002 +#define S3C64XX_GPF8_EINT_G4_8         (0x03 << 16)
35003 +
35004 +#define S3C64XX_GPF9_CAMIF_YDATA4      (0x02 << 18)
35005 +#define S3C64XX_GPF9_EINT_G4_9         (0x03 << 18)
35006 +
35007 +#define S3C64XX_GPF10_CAMIF_YDATA5     (0x02 << 20)
35008 +#define S3C64XX_GPF10_EINT_G4_10       (0x03 << 20)
35009 +
35010 +#define S3C64XX_GPF11_CAMIF_YDATA6     (0x02 << 22)
35011 +#define S3C64XX_GPF11_EINT_G4_11       (0x03 << 22)
35012 +
35013 +#define S3C64XX_GPF12_CAMIF_YDATA7     (0x02 << 24)
35014 +#define S3C64XX_GPF12_EINT_G4_12       (0x03 << 24)
35015 +
35016 +#define S3C64XX_GPF13_PWM_ECLK         (0x02 << 26)
35017 +#define S3C64XX_GPF13_EINT_G4_13       (0x03 << 26)
35018 +
35019 +#define S3C64XX_GPF14_PWM_TOUT0                (0x02 << 28)
35020 +#define S3C64XX_GPF14_CLKOUT0          (0x03 << 28)
35021 +
35022 +#define S3C64XX_GPF15_PWM_TOUT1                (0x02 << 30)
35023 +
35024 --- /dev/null
35025 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
35026 @@ -0,0 +1,42 @@
35027 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
35028 + *
35029 + * Copyright 2008 Openmoko, Inc.
35030 + * Copyright 2008 Simtec Electronics
35031 + *     Ben Dooks <ben@simtec.co.uk>
35032 + *     http://armlinux.simtec.co.uk/
35033 + *
35034 + * GPIO Bank G register and configuration definitions
35035 + *
35036 + * This program is free software; you can redistribute it and/or modify
35037 + * it under the terms of the GNU General Public License version 2 as
35038 + * published by the Free Software Foundation.
35039 +*/
35040 +
35041 +#define S3C64XX_GPGCON                 (S3C64XX_GPG_BASE + 0x00)
35042 +#define S3C64XX_GPGDAT                 (S3C64XX_GPG_BASE + 0x04)
35043 +#define S3C64XX_GPGPUD                 (S3C64XX_GPG_BASE + 0x08)
35044 +#define S3C64XX_GPGCONSLP              (S3C64XX_GPG_BASE + 0x0c)
35045 +#define S3C64XX_GPGPUDSLP              (S3C64XX_GPG_BASE + 0x10)
35046 +
35047 +#define S3C64XX_GPG_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
35048 +#define S3C64XX_GPG_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
35049 +#define S3C64XX_GPG_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
35050 +
35051 +#define S3C64XX_GPG0_MMC0_CLK          (0x02 << 0)
35052 +#define S3C64XX_GPG0_EINT_G5_0         (0x07 << 0)
35053 +
35054 +#define S3C64XX_GPG1_MMC0_CMD          (0x02 << 4)
35055 +#define S3C64XX_GPG1_EINT_G5_1         (0x07 << 4)
35056 +
35057 +#define S3C64XX_GPG2_MMC0_DATA0                (0x02 << 8)
35058 +#define S3C64XX_GPG2_EINT_G5_2         (0x07 << 8)
35059 +
35060 +#define S3C64XX_GPG3_MMC0_DATA1                (0x02 << 12)
35061 +#define S3C64XX_GPG3_EINT_G5_3         (0x07 << 12)
35062 +
35063 +#define S3C64XX_GPG4_MMC0_DATA2                (0x02 << 16)
35064 +#define S3C64XX_GPG4_EINT_G5_4         (0x07 << 16)
35065 +
35066 +#define S3C64XX_GPG5_MMC0_DATA3                (0x02 << 20)
35067 +#define S3C64XX_GPG5_EINT_G5_5         (0x07 << 20)
35068 +
35069 --- /dev/null
35070 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
35071 @@ -0,0 +1,74 @@
35072 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
35073 + *
35074 + * Copyright 2008 Openmoko, Inc.
35075 + * Copyright 2008 Simtec Electronics
35076 + *     Ben Dooks <ben@simtec.co.uk>
35077 + *     http://armlinux.simtec.co.uk/
35078 + *
35079 + * GPIO Bank H register and configuration definitions
35080 + *
35081 + * This program is free software; you can redistribute it and/or modify
35082 + * it under the terms of the GNU General Public License version 2 as
35083 + * published by the Free Software Foundation.
35084 +*/
35085 +
35086 +#define S3C64XX_GPHCON0                        (S3C64XX_GPH_BASE + 0x00)
35087 +#define S3C64XX_GPHCON1                        (S3C64XX_GPH_BASE + 0x04)
35088 +#define S3C64XX_GPHDAT                 (S3C64XX_GPH_BASE + 0x08)
35089 +#define S3C64XX_GPHPUD                 (S3C64XX_GPH_BASE + 0x0c)
35090 +#define S3C64XX_GPHCONSLP              (S3C64XX_GPH_BASE + 0x10)
35091 +#define S3C64XX_GPHPUDSLP              (S3C64XX_GPH_BASE + 0x14)
35092 +
35093 +#define S3C64XX_GPH_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
35094 +#define S3C64XX_GPH_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
35095 +#define S3C64XX_GPH_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
35096 +
35097 +#define S3C64XX_GPH0_MMC1_CLK          (0x02 << 0)
35098 +#define S3C64XX_GPH0_KP_COL0           (0x04 << 0)
35099 +#define S3C64XX_GPH0_EINT_G6_0         (0x07 << 0)
35100 +
35101 +#define S3C64XX_GPH1_MMC1_CMD          (0x02 << 4)
35102 +#define S3C64XX_GPH1_KP_COL1           (0x04 << 4)
35103 +#define S3C64XX_GPH1_EINT_G6_1         (0x07 << 4)
35104 +
35105 +#define S3C64XX_GPH2_MMC1_DATA0                (0x02 << 8)
35106 +#define S3C64XX_GPH2_KP_COL2           (0x04 << 8)
35107 +#define S3C64XX_GPH2_EINT_G6_2         (0x07 << 8)
35108 +
35109 +#define S3C64XX_GPH3_MMC1_DATA1                (0x02 << 12)
35110 +#define S3C64XX_GPH3_KP_COL3           (0x04 << 12)
35111 +#define S3C64XX_GPH3_EINT_G6_3         (0x07 << 12)
35112 +
35113 +#define S3C64XX_GPH4_MMC1_DATA2                (0x02 << 16)
35114 +#define S3C64XX_GPH4_KP_COL4           (0x04 << 16)
35115 +#define S3C64XX_GPH4_EINT_G6_4         (0x07 << 16)
35116 +
35117 +#define S3C64XX_GPH5_MMC1_DATA3                (0x02 << 20)
35118 +#define S3C64XX_GPH5_KP_COL5           (0x04 << 20)
35119 +#define S3C64XX_GPH5_EINT_G6_5         (0x07 << 20)
35120 +
35121 +#define S3C64XX_GPH6_MMC1_DATA4                (0x02 << 24)
35122 +#define S3C64XX_GPH6_MMC2_DATA0                (0x03 << 24)
35123 +#define S3C64XX_GPH6_KP_COL6           (0x04 << 24)
35124 +#define S3C64XX_GPH6_I2S_V40_BCLK      (0x05 << 24)
35125 +#define S3C64XX_GPH6_ADDR_CF0          (0x06 << 24)
35126 +#define S3C64XX_GPH6_EINT_G6_6         (0x07 << 24)
35127 +
35128 +#define S3C64XX_GPH7_MMC1_DATA5                (0x02 << 28)
35129 +#define S3C64XX_GPH7_MMC2_DATA1                (0x03 << 28)
35130 +#define S3C64XX_GPH7_KP_COL7           (0x04 << 28)
35131 +#define S3C64XX_GPH7_I2S_V40_CDCLK     (0x05 << 28)
35132 +#define S3C64XX_GPH7_ADDR_CF1          (0x06 << 28)
35133 +#define S3C64XX_GPH7_EINT_G6_7         (0x07 << 28)
35134 +
35135 +#define S3C64XX_GPH8_MMC1_DATA6                (0x02 << 32)
35136 +#define S3C64XX_GPH8_MMC2_DATA2                (0x03 << 32)
35137 +#define S3C64XX_GPH8_I2S_V40_LRCLK     (0x05 << 32)
35138 +#define S3C64XX_GPH8_ADDR_CF2          (0x06 << 32)
35139 +#define S3C64XX_GPH8_EINT_G6_8         (0x07 << 32)
35140 +
35141 +#define S3C64XX_GPH9_MMC1_DATA7                (0x02 << 36)
35142 +#define S3C64XX_GPH9_MMC2_DATA3                (0x03 << 36)
35143 +#define S3C64XX_GPH9_I2S_V40_DI                (0x05 << 36)
35144 +#define S3C64XX_GPH9_EINT_G6_9         (0x07 << 36)
35145 +
35146 --- /dev/null
35147 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
35148 @@ -0,0 +1,40 @@
35149 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
35150 + *
35151 + * Copyright 2008 Openmoko, Inc.
35152 + * Copyright 2008 Simtec Electronics
35153 + *     Ben Dooks <ben@simtec.co.uk>
35154 + *     http://armlinux.simtec.co.uk/
35155 + *
35156 + * GPIO Bank I register and configuration definitions
35157 + *
35158 + * This program is free software; you can redistribute it and/or modify
35159 + * it under the terms of the GNU General Public License version 2 as
35160 + * published by the Free Software Foundation.
35161 +*/
35162 +
35163 +#define S3C64XX_GPICON                 (S3C64XX_GPI_BASE + 0x00)
35164 +#define S3C64XX_GPIDAT                 (S3C64XX_GPI_BASE + 0x04)
35165 +#define S3C64XX_GPIPUD                 (S3C64XX_GPI_BASE + 0x08)
35166 +#define S3C64XX_GPICONSLP              (S3C64XX_GPI_BASE + 0x0c)
35167 +#define S3C64XX_GPIPUDSLP              (S3C64XX_GPI_BASE + 0x10)
35168 +
35169 +#define S3C64XX_GPI_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35170 +#define S3C64XX_GPI_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35171 +#define S3C64XX_GPI_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35172 +
35173 +#define S3C64XX_GPI0_VD0               (0x02 << 0)
35174 +#define S3C64XX_GPI1_VD1               (0x02 << 2)
35175 +#define S3C64XX_GPI2_VD2               (0x02 << 4)
35176 +#define S3C64XX_GPI3_VD3               (0x02 << 6)
35177 +#define S3C64XX_GPI4_VD4               (0x02 << 8)
35178 +#define S3C64XX_GPI5_VD5               (0x02 << 10)
35179 +#define S3C64XX_GPI6_VD6               (0x02 << 12)
35180 +#define S3C64XX_GPI7_VD7               (0x02 << 14)
35181 +#define S3C64XX_GPI8_VD8               (0x02 << 16)
35182 +#define S3C64XX_GPI9_VD9               (0x02 << 18)
35183 +#define S3C64XX_GPI10_VD10             (0x02 << 20)
35184 +#define S3C64XX_GPI11_VD11             (0x02 << 22)
35185 +#define S3C64XX_GPI12_VD12             (0x02 << 24)
35186 +#define S3C64XX_GPI13_VD13             (0x02 << 26)
35187 +#define S3C64XX_GPI14_VD14             (0x02 << 28)
35188 +#define S3C64XX_GPI15_VD15             (0x02 << 30)
35189 --- /dev/null
35190 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
35191 @@ -0,0 +1,36 @@
35192 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
35193 + *
35194 + * Copyright 2008 Openmoko, Inc.
35195 + * Copyright 2008 Simtec Electronics
35196 + *     Ben Dooks <ben@simtec.co.uk>
35197 + *     http://armlinux.simtec.co.uk/
35198 + *
35199 + * GPIO Bank J register and configuration definitions
35200 + *
35201 + * This program is free software; you can redistribute it and/or modify
35202 + * it under the terms of the GNU General Public License version 2 as
35203 + * published by the Free Software Foundation.
35204 +*/
35205 +
35206 +#define S3C64XX_GPJCON                 (S3C64XX_GPJ_BASE + 0x00)
35207 +#define S3C64XX_GPJDAT                 (S3C64XX_GPJ_BASE + 0x04)
35208 +#define S3C64XX_GPJPUD                 (S3C64XX_GPJ_BASE + 0x08)
35209 +#define S3C64XX_GPJCONSLP              (S3C64XX_GPJ_BASE + 0x0c)
35210 +#define S3C64XX_GPJPUDSLP              (S3C64XX_GPJ_BASE + 0x10)
35211 +
35212 +#define S3C64XX_GPJ_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35213 +#define S3C64XX_GPJ_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35214 +#define S3C64XX_GPJ_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35215 +
35216 +#define S3C64XX_GPJ0_VD16              (0x02 << 0)
35217 +#define S3C64XX_GPJ1_VD17              (0x02 << 2)
35218 +#define S3C64XX_GPJ2_VD18              (0x02 << 4)
35219 +#define S3C64XX_GPJ3_VD19              (0x02 << 6)
35220 +#define S3C64XX_GPJ4_VD20              (0x02 << 8)
35221 +#define S3C64XX_GPJ5_VD21              (0x02 << 10)
35222 +#define S3C64XX_GPJ6_VD22              (0x02 << 12)
35223 +#define S3C64XX_GPJ7_VD23              (0x02 << 14)
35224 +#define S3C64XX_GPJ8_LCD_HSYNC         (0x02 << 16)
35225 +#define S3C64XX_GPJ9_LCD_VSYNC         (0x02 << 18)
35226 +#define S3C64XX_GPJ10_LCD_VDEN         (0x02 << 20)
35227 +#define S3C64XX_GPJ11_LCD_VCLK         (0x02 << 22)
35228 --- /dev/null
35229 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
35230 @@ -0,0 +1,54 @@
35231 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
35232 + *
35233 + * Copyright 2008 Openmoko, Inc.
35234 + * Copyright 2008 Simtec Electronics
35235 + *     Ben Dooks <ben@simtec.co.uk>
35236 + *     http://armlinux.simtec.co.uk/
35237 + *
35238 + * GPIO Bank N register and configuration definitions
35239 + *
35240 + * This program is free software; you can redistribute it and/or modify
35241 + * it under the terms of the GNU General Public License version 2 as
35242 + * published by the Free Software Foundation.
35243 +*/
35244 +
35245 +#define S3C64XX_GPNCON                 (S3C64XX_GPN_BASE + 0x00)
35246 +#define S3C64XX_GPNDAT                 (S3C64XX_GPN_BASE + 0x04)
35247 +#define S3C64XX_GPNPUD                 (S3C64XX_GPN_BASE + 0x08)
35248 +
35249 +#define S3C64XX_GPN_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35250 +#define S3C64XX_GPN_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35251 +#define S3C64XX_GPN_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35252 +
35253 +#define S3C64XX_GPN0_EINT0             (0x02 << 0)
35254 +#define S3C64XX_GPN0_KP_ROW0           (0x03 << 0)
35255 +
35256 +#define S3C64XX_GPN1_EINT1             (0x02 << 2)
35257 +#define S3C64XX_GPN1_KP_ROW1           (0x03 << 2)
35258 +
35259 +#define S3C64XX_GPN2_EINT2             (0x02 << 4)
35260 +#define S3C64XX_GPN2_KP_ROW2           (0x03 << 4)
35261 +
35262 +#define S3C64XX_GPN3_EINT3             (0x02 << 6)
35263 +#define S3C64XX_GPN3_KP_ROW3           (0x03 << 6)
35264 +
35265 +#define S3C64XX_GPN4_EINT4             (0x02 << 8)
35266 +#define S3C64XX_GPN4_KP_ROW4           (0x03 << 8)
35267 +
35268 +#define S3C64XX_GPN5_EINT5             (0x02 << 10)
35269 +#define S3C64XX_GPN5_KP_ROW5           (0x03 << 10)
35270 +
35271 +#define S3C64XX_GPN6_EINT6             (0x02 << 12)
35272 +#define S3C64XX_GPN6_KP_ROW6           (0x03 << 12)
35273 +
35274 +#define S3C64XX_GPN7_EINT7             (0x02 << 14)
35275 +#define S3C64XX_GPN7_KP_ROW7           (0x03 << 14)
35276 +
35277 +#define S3C64XX_GPN8_EINT8             (0x02 << 16)
35278 +#define S3C64XX_GPN9_EINT9             (0x02 << 18)
35279 +#define S3C64XX_GPN10_EINT10           (0x02 << 20)
35280 +#define S3C64XX_GPN11_EINT11           (0x02 << 22)
35281 +#define S3C64XX_GPN12_EINT12           (0x02 << 24)
35282 +#define S3C64XX_GPN13_EINT13           (0x02 << 26)
35283 +#define S3C64XX_GPN14_EINT14           (0x02 << 28)
35284 +#define S3C64XX_GPN15_EINT15           (0x02 << 30)
35285 --- /dev/null
35286 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
35287 @@ -0,0 +1,70 @@
35288 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
35289 + *
35290 + * Copyright 2008 Openmoko, Inc.
35291 + * Copyright 2008 Simtec Electronics
35292 + *     Ben Dooks <ben@simtec.co.uk>
35293 + *     http://armlinux.simtec.co.uk/
35294 + *
35295 + * GPIO Bank O register and configuration definitions
35296 + *
35297 + * This program is free software; you can redistribute it and/or modify
35298 + * it under the terms of the GNU General Public License version 2 as
35299 + * published by the Free Software Foundation.
35300 +*/
35301 +
35302 +#define S3C64XX_GPOCON                 (S3C64XX_GPO_BASE + 0x00)
35303 +#define S3C64XX_GPODAT                 (S3C64XX_GPO_BASE + 0x04)
35304 +#define S3C64XX_GPOPUD                 (S3C64XX_GPO_BASE + 0x08)
35305 +#define S3C64XX_GPOCONSLP              (S3C64XX_GPO_BASE + 0x0c)
35306 +#define S3C64XX_GPOPUDSLP              (S3C64XX_GPO_BASE + 0x10)
35307 +
35308 +#define S3C64XX_GPO_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35309 +#define S3C64XX_GPO_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35310 +#define S3C64XX_GPO_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35311 +
35312 +#define S3C64XX_GPO0_MEM0_nCS2         (0x02 << 0)
35313 +#define S3C64XX_GPO0_EINT_G7_0         (0x03 << 0)
35314 +
35315 +#define S3C64XX_GPO1_MEM0_nCS3         (0x02 << 2)
35316 +#define S3C64XX_GPO1_EINT_G7_1         (0x03 << 2)
35317 +
35318 +#define S3C64XX_GPO2_MEM0_nCS4         (0x02 << 4)
35319 +#define S3C64XX_GPO2_EINT_G7_2         (0x03 << 4)
35320 +
35321 +#define S3C64XX_GPO3_MEM0_nCS5         (0x02 << 6)
35322 +#define S3C64XX_GPO3_EINT_G7_3         (0x03 << 6)
35323 +
35324 +#define S3C64XX_GPO4_EINT_G7_4         (0x03 << 8)
35325 +
35326 +#define S3C64XX_GPO5_EINT_G7_5         (0x03 << 10)
35327 +
35328 +#define S3C64XX_GPO6_MEM0_ADDR6                (0x02 << 12)
35329 +#define S3C64XX_GPO6_EINT_G7_6         (0x03 << 12)
35330 +
35331 +#define S3C64XX_GPO7_MEM0_ADDR7                (0x02 << 14)
35332 +#define S3C64XX_GPO7_EINT_G7_7         (0x03 << 14)
35333 +
35334 +#define S3C64XX_GPO8_MEM0_ADDR8                (0x02 << 16)
35335 +#define S3C64XX_GPO8_EINT_G7_8         (0x03 << 16)
35336 +
35337 +#define S3C64XX_GPO9_MEM0_ADDR9                (0x02 << 18)
35338 +#define S3C64XX_GPO9_EINT_G7_9         (0x03 << 18)
35339 +
35340 +#define S3C64XX_GPO10_MEM0_ADDR10      (0x02 << 20)
35341 +#define S3C64XX_GPO10_EINT_G7_10       (0x03 << 20)
35342 +
35343 +#define S3C64XX_GPO11_MEM0_ADDR11      (0x02 << 22)
35344 +#define S3C64XX_GPO11_EINT_G7_11       (0x03 << 22)
35345 +
35346 +#define S3C64XX_GPO12_MEM0_ADDR12      (0x02 << 24)
35347 +#define S3C64XX_GPO12_EINT_G7_12       (0x03 << 24)
35348 +
35349 +#define S3C64XX_GPO13_MEM0_ADDR13      (0x02 << 26)
35350 +#define S3C64XX_GPO13_EINT_G7_13       (0x03 << 26)
35351 +
35352 +#define S3C64XX_GPO14_MEM0_ADDR14      (0x02 << 28)
35353 +#define S3C64XX_GPO14_EINT_G7_14       (0x03 << 28)
35354 +
35355 +#define S3C64XX_GPO15_MEM0_ADDR15      (0x02 << 30)
35356 +#define S3C64XX_GPO15_EINT_G7_15       (0x03 << 30)
35357 +
35358 --- /dev/null
35359 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
35360 @@ -0,0 +1,69 @@
35361 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
35362 + *
35363 + * Copyright 2008 Openmoko, Inc.
35364 + * Copyright 2008 Simtec Electronics
35365 + *     Ben Dooks <ben@simtec.co.uk>
35366 + *     http://armlinux.simtec.co.uk/
35367 + *
35368 + * GPIO Bank P register and configuration definitions
35369 + *
35370 + * This program is free software; you can redistribute it and/or modify
35371 + * it under the terms of the GNU General Public License version 2 as
35372 + * published by the Free Software Foundation.
35373 +*/
35374 +
35375 +#define S3C64XX_GPPCON                 (S3C64XX_GPP_BASE + 0x00)
35376 +#define S3C64XX_GPPDAT                 (S3C64XX_GPP_BASE + 0x04)
35377 +#define S3C64XX_GPPPUD                 (S3C64XX_GPP_BASE + 0x08)
35378 +#define S3C64XX_GPPCONSLP              (S3C64XX_GPP_BASE + 0x0c)
35379 +#define S3C64XX_GPPPUDSLP              (S3C64XX_GPP_BASE + 0x10)
35380 +
35381 +#define S3C64XX_GPP_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35382 +#define S3C64XX_GPP_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35383 +#define S3C64XX_GPP_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35384 +
35385 +#define S3C64XX_GPP0_MEM0_ADDRV                (0x02 << 0)
35386 +#define S3C64XX_GPP0_EINT_G8_0         (0x03 << 0)
35387 +
35388 +#define S3C64XX_GPP1_MEM0_SMCLK                (0x02 << 2)
35389 +#define S3C64XX_GPP1_EINT_G8_1         (0x03 << 2)
35390 +
35391 +#define S3C64XX_GPP2_MEM0_nWAIT                (0x02 << 4)
35392 +#define S3C64XX_GPP2_EINT_G8_2         (0x03 << 4)
35393 +
35394 +#define S3C64XX_GPP3_MEM0_RDY0_ALE     (0x02 << 6)
35395 +#define S3C64XX_GPP3_EINT_G8_3         (0x03 << 6)
35396 +
35397 +#define S3C64XX_GPP4_MEM0_RDY1_CLE     (0x02 << 8)
35398 +#define S3C64XX_GPP4_EINT_G8_4         (0x03 << 8)
35399 +
35400 +#define S3C64XX_GPP5_MEM0_INTsm0_FWE   (0x02 << 10)
35401 +#define S3C64XX_GPP5_EINT_G8_5         (0x03 << 10)
35402 +
35403 +#define S3C64XX_GPP6_MEM0_(null)       (0x02 << 12)
35404 +#define S3C64XX_GPP6_EINT_G8_6         (0x03 << 12)
35405 +
35406 +#define S3C64XX_GPP7_MEM0_INTsm1_FRE   (0x02 << 14)
35407 +#define S3C64XX_GPP7_EINT_G8_7         (0x03 << 14)
35408 +
35409 +#define S3C64XX_GPP8_MEM0_RPn_RnB      (0x02 << 16)
35410 +#define S3C64XX_GPP8_EINT_G8_8         (0x03 << 16)
35411 +
35412 +#define S3C64XX_GPP9_MEM0_ATA_RESET    (0x02 << 18)
35413 +#define S3C64XX_GPP9_EINT_G8_9         (0x03 << 18)
35414 +
35415 +#define S3C64XX_GPP10_MEM0_ATA_INPACK  (0x02 << 20)
35416 +#define S3C64XX_GPP10_EINT_G8_10       (0x03 << 20)
35417 +
35418 +#define S3C64XX_GPP11_MEM0_ATA_REG     (0x02 << 22)
35419 +#define S3C64XX_GPP11_EINT_G8_11       (0x03 << 22)
35420 +
35421 +#define S3C64XX_GPP12_MEM0_ATA_WE      (0x02 << 24)
35422 +#define S3C64XX_GPP12_EINT_G8_12       (0x03 << 24)
35423 +
35424 +#define S3C64XX_GPP13_MEM0_ATA_OE      (0x02 << 26)
35425 +#define S3C64XX_GPP13_EINT_G8_13       (0x03 << 26)
35426 +
35427 +#define S3C64XX_GPP14_MEM0_ATA_CD      (0x02 << 28)
35428 +#define S3C64XX_GPP14_EINT_G8_14       (0x03 << 28)
35429 +
35430 --- /dev/null
35431 +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
35432 @@ -0,0 +1,46 @@
35433 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
35434 + *
35435 + * Copyright 2008 Openmoko, Inc.
35436 + * Copyright 2008 Simtec Electronics
35437 + *     Ben Dooks <ben@simtec.co.uk>
35438 + *     http://armlinux.simtec.co.uk/
35439 + *
35440 + * GPIO Bank Q register and configuration definitions
35441 + *
35442 + * This program is free software; you can redistribute it and/or modify
35443 + * it under the terms of the GNU General Public License version 2 as
35444 + * published by the Free Software Foundation.
35445 +*/
35446 +
35447 +#define S3C64XX_GPQCON                 (S3C64XX_GPQ_BASE + 0x00)
35448 +#define S3C64XX_GPQDAT                 (S3C64XX_GPQ_BASE + 0x04)
35449 +#define S3C64XX_GPQPUD                 (S3C64XX_GPQ_BASE + 0x08)
35450 +#define S3C64XX_GPQCONSLP              (S3C64XX_GPQ_BASE + 0x0c)
35451 +#define S3C64XX_GPQPUDSLP              (S3C64XX_GPQ_BASE + 0x10)
35452 +
35453 +#define S3C64XX_GPQ_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35454 +#define S3C64XX_GPQ_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35455 +#define S3C64XX_GPQ_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35456 +
35457 +#define S3C64XX_GPQ0_MEM0_ADDR18_RAS   (0x02 << 0)
35458 +#define S3C64XX_GPQ0_EINT_G9_0         (0x03 << 0)
35459 +
35460 +#define S3C64XX_GPQ1_MEM0_ADDR19_CAS   (0x02 << 2)
35461 +#define S3C64XX_GPQ1_EINT_G9_1         (0x03 << 2)
35462 +
35463 +#define S3C64XX_GPQ2_EINT_G9_2         (0x03 << 4)
35464 +
35465 +#define S3C64XX_GPQ3_EINT_G9_3         (0x03 << 6)
35466 +
35467 +#define S3C64XX_GPQ4_EINT_G9_4         (0x03 << 8)
35468 +
35469 +#define S3C64XX_GPQ5_EINT_G9_5         (0x03 << 10)
35470 +
35471 +#define S3C64XX_GPQ6_EINT_G9_6         (0x03 << 12)
35472 +
35473 +#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC        (0x02 << 14)
35474 +#define S3C64XX_GPQ7_EINT_G9_7         (0x03 << 14)
35475 +
35476 +#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16)
35477 +#define S3C64XX_GPQ8_EINT_G9_8         (0x03 << 16)
35478 +
35479 --- /dev/null
35480 +++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h
35481 @@ -0,0 +1,202 @@
35482 +/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h
35483 + *
35484 + * Copyright 2008 Openmoko, Inc.
35485 + * Copyright 2008 Simtec Electronics
35486 + *      Ben Dooks <ben@simtec.co.uk>
35487 + *      http://armlinux.simtec.co.uk/
35488 + *
35489 + * S3C64XX - Common IRQ support
35490 + */
35491 +
35492 +#ifndef __ASM_PLAT_S3C64XX_IRQS_H
35493 +#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__
35494 +
35495 +/* we keep the first set of CPU IRQs out of the range of
35496 + * the ISA space, so that the PC104 has them to itself
35497 + * and we don't end up having to do horrible things to the
35498 + * standard ISA drivers....
35499 + *
35500 + * note, since we're using the VICs, our start must be a
35501 + * mulitple of 32 to allow the common code to work
35502 + */
35503 +
35504 +#define S3C_IRQ_OFFSET (32)
35505 +
35506 +#define S3C_IRQ(x)     ((x) + S3C_IRQ_OFFSET)
35507 +
35508 +#define S3C_VIC0_BASE  S3C_IRQ(0)
35509 +#define S3C_VIC1_BASE  S3C_IRQ(32)
35510 +
35511 +/* UART interrupts, each UART has 4 intterupts per channel so
35512 + * use the space between the ISA and S3C main interrupts. Note, these
35513 + * are not in the same order as the S3C24XX series! */
35514 +
35515 +#define IRQ_S3CUART_BASE0      (16)
35516 +#define IRQ_S3CUART_BASE1      (20)
35517 +#define IRQ_S3CUART_BASE2      (24)
35518 +#define IRQ_S3CUART_BASE3      (28)
35519 +
35520 +#define UART_IRQ_RXD           (0)
35521 +#define UART_IRQ_ERR           (1)
35522 +#define UART_IRQ_TXD           (2)
35523 +#define UART_IRQ_MODEM         (3)
35524 +
35525 +#define IRQ_S3CUART_RX0                (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
35526 +#define IRQ_S3CUART_TX0                (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
35527 +#define IRQ_S3CUART_ERR0       (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
35528 +
35529 +#define IRQ_S3CUART_RX1                (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
35530 +#define IRQ_S3CUART_TX1                (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
35531 +#define IRQ_S3CUART_ERR1       (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
35532 +
35533 +#define IRQ_S3CUART_RX2                (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
35534 +#define IRQ_S3CUART_TX2                (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
35535 +#define IRQ_S3CUART_ERR2       (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
35536 +
35537 +#define IRQ_S3CUART_RX3                (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
35538 +#define IRQ_S3CUART_TX3                (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
35539 +#define IRQ_S3CUART_ERR3       (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
35540 +
35541 +/* VIC based IRQs */
35542 +
35543 +#define S3C64XX_IRQ_VIC0(x)    (S3C_VIC0_BASE + (x))
35544 +#define S3C64XX_IRQ_VIC1(x)    (S3C_VIC1_BASE + (x))
35545 +
35546 +/* VIC0 */
35547 +
35548 +#define IRQ_EINT0_3            S3C64XX_IRQ_VIC0(0)
35549 +#define IRQ_EINT4_11           S3C64XX_IRQ_VIC0(1)
35550 +#define IRQ_RTC_TIC            S3C64XX_IRQ_VIC0(2)
35551 +#define IRQ_CAMIF_C            S3C64XX_IRQ_VIC0(3)
35552 +#define IRQ_CAMIF_P            S3C64XX_IRQ_VIC0(4)
35553 +#define IRQ_CAMIF_MC           S3C64XX_IRQ_VIC0(5)
35554 +#define IRQ_S3C6410_IIC1       S3C64XX_IRQ_VIC0(5)
35555 +#define IRQ_S3C6410_IIS                S3C64XX_IRQ_VIC0(6)
35556 +#define IRQ_S3C6400_CAMIF_MP   S3C64XX_IRQ_VIC0(6)
35557 +#define IRQ_CAMIF_WE_C         S3C64XX_IRQ_VIC0(7)
35558 +#define IRQ_S3C6410_G3D                S3C64XX_IRQ_VIC0(8)
35559 +#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
35560 +#define IRQ_POST0              S3C64XX_IRQ_VIC0(9)
35561 +#define IRQ_ROTATOR            S3C64XX_IRQ_VIC0(10)
35562 +#define IRQ_2D                 S3C64XX_IRQ_VIC0(11)
35563 +#define IRQ_TVENC              S3C64XX_IRQ_VIC0(12)
35564 +#define IRQ_SCALER             S3C64XX_IRQ_VIC0(13)
35565 +#define IRQ_BATF               S3C64XX_IRQ_VIC0(14)
35566 +#define IRQ_JPEG               S3C64XX_IRQ_VIC0(15)
35567 +#define IRQ_MFC                        S3C64XX_IRQ_VIC0(16)
35568 +#define IRQ_SDMA0              S3C64XX_IRQ_VIC0(17)
35569 +#define IRQ_SDMA1              S3C64XX_IRQ_VIC0(18)
35570 +#define IRQ_ARM_DMAERR         S3C64XX_IRQ_VIC0(19)
35571 +#define IRQ_ARM_DMA            S3C64XX_IRQ_VIC0(20)
35572 +#define IRQ_ARM_DMAS           S3C64XX_IRQ_VIC0(21)
35573 +#define IRQ_KEYPAD             S3C64XX_IRQ_VIC0(22)
35574 +#define IRQ_TIMER0_VIC         S3C64XX_IRQ_VIC0(23)
35575 +#define IRQ_TIMER1_VIC         S3C64XX_IRQ_VIC0(24)
35576 +#define IRQ_TIMER2_VIC         S3C64XX_IRQ_VIC0(25)
35577 +#define IRQ_WDT                        S3C64XX_IRQ_VIC0(26)
35578 +#define IRQ_TIMER3_VIC         S3C64XX_IRQ_VIC0(27)
35579 +#define IRQ_TIMER4_VIC         S3C64XX_IRQ_VIC0(28)
35580 +#define IRQ_LCD_FIFO           S3C64XX_IRQ_VIC0(29)
35581 +#define IRQ_LCD_VSYNC          S3C64XX_IRQ_VIC0(30)
35582 +#define IRQ_LCD_SYSTEM         S3C64XX_IRQ_VIC0(31)
35583 +
35584 +/* VIC1 */
35585 +
35586 +#define IRQ_EINT12_19          S3C64XX_IRQ_VIC1(0)
35587 +#define IRQ_EINT20_27          S3C64XX_IRQ_VIC1(1)
35588 +#define IRQ_PCM0               S3C64XX_IRQ_VIC1(2)
35589 +#define IRQ_PCM1               S3C64XX_IRQ_VIC1(3)
35590 +#define IRQ_AC97               S3C64XX_IRQ_VIC1(4)
35591 +#define IRQ_UART0              S3C64XX_IRQ_VIC1(5)
35592 +#define IRQ_UART1              S3C64XX_IRQ_VIC1(6)
35593 +#define IRQ_UART2              S3C64XX_IRQ_VIC1(7)
35594 +#define IRQ_UART3              S3C64XX_IRQ_VIC1(8)
35595 +#define IRQ_DMA0               S3C64XX_IRQ_VIC1(9)
35596 +#define IRQ_DMA1               S3C64XX_IRQ_VIC1(10)
35597 +#define IRQ_ONENAND0           S3C64XX_IRQ_VIC1(11)
35598 +#define IRQ_ONENAND1           S3C64XX_IRQ_VIC1(12)
35599 +#define IRQ_NFC                        S3C64XX_IRQ_VIC1(13)
35600 +#define IRQ_CFCON              S3C64XX_IRQ_VIC1(14)
35601 +#define IRQ_UHOST              S3C64XX_IRQ_VIC1(15)
35602 +#define IRQ_SPI0               S3C64XX_IRQ_VIC1(16)
35603 +#define IRQ_SPI1               S3C64XX_IRQ_VIC1(17)
35604 +#define IRQ_IIC                        S3C64XX_IRQ_VIC1(18)
35605 +#define IRQ_HSItx              S3C64XX_IRQ_VIC1(19)
35606 +#define IRQ_HSIrx              S3C64XX_IRQ_VIC1(20)
35607 +#define IRQ_RESERVED           S3C64XX_IRQ_VIC1(21)
35608 +#define IRQ_MSM                        S3C64XX_IRQ_VIC1(22)
35609 +#define IRQ_HOSTIF             S3C64XX_IRQ_VIC1(23)
35610 +#define IRQ_HSMMC0             S3C64XX_IRQ_VIC1(24)
35611 +#define IRQ_HSMMC1             S3C64XX_IRQ_VIC1(25)
35612 +#define IRQ_HSMMC2             IRQ_SPI1        /* shared with SPI1 */
35613 +#define IRQ_OTG                        S3C64XX_IRQ_VIC1(26)
35614 +#define IRQ_IRDA               S3C64XX_IRQ_VIC1(27)
35615 +#define IRQ_RTC_ALARM          S3C64XX_IRQ_VIC1(28)
35616 +#define IRQ_SEC                        S3C64XX_IRQ_VIC1(29)
35617 +#define IRQ_PENDN              S3C64XX_IRQ_VIC1(30)
35618 +#define IRQ_TC                 IRQ_PENDN
35619 +#define IRQ_ADC                        S3C64XX_IRQ_VIC1(31)
35620 +
35621 +#define S3C64XX_TIMER_IRQ(x)   S3C_IRQ(64 + (x))
35622 +
35623 +#define IRQ_TIMER0             S3C64XX_TIMER_IRQ(0)
35624 +#define IRQ_TIMER1             S3C64XX_TIMER_IRQ(1)
35625 +#define IRQ_TIMER2             S3C64XX_TIMER_IRQ(2)
35626 +#define IRQ_TIMER3             S3C64XX_TIMER_IRQ(3)
35627 +#define IRQ_TIMER4             S3C64XX_TIMER_IRQ(4)
35628 +
35629 +/* compatibility for device defines */
35630 +
35631 +#define IRQ_IIC1               IRQ_S3C6410_IIC1
35632 +
35633 +/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
35634 + * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
35635 + * which we place after the pair of VICs. */
35636 +
35637 +#define S3C_IRQ_EINT_BASE      S3C_IRQ(64+5)
35638 +
35639 +#define S3C_EINT(x)            ((x) + S3C_IRQ_EINT_BASE)
35640 +#define IRQ_EINT(x)            S3C_EINT(x)
35641 +#define IRQ_EINT_BIT(x)                ((x) - S3C_EINT(0))
35642 +
35643 +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
35644 + * that they are sourced from the GPIO pins but with a different scheme for
35645 + * priority and source indication.
35646 + *
35647 + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
35648 + * interrupts, but for historical reasons they are kept apart from these
35649 + * next interrupts.
35650 + *
35651 + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
35652 + * machine specific support files.
35653 + */
35654 +
35655 +#define IRQ_EINT_GROUP1_NR     (15)
35656 +#define IRQ_EINT_GROUP2_NR     (8)
35657 +#define IRQ_EINT_GROUP3_NR     (5)
35658 +#define IRQ_EINT_GROUP4_NR     (14)
35659 +#define IRQ_EINT_GROUP5_NR     (7)
35660 +#define IRQ_EINT_GROUP6_NR     (10)
35661 +#define IRQ_EINT_GROUP7_NR     (16)
35662 +#define IRQ_EINT_GROUP8_NR     (15)
35663 +#define IRQ_EINT_GROUP9_NR     (9)
35664 +
35665 +#define IRQ_EINT_GROUP_BASE    S3C_EINT(28)
35666 +#define IRQ_EINT_GROUP1_BASE   (IRQ_EINT_GROUP_BASE + 0x00)
35667 +#define IRQ_EINT_GROUP2_BASE   (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
35668 +#define IRQ_EINT_GROUP3_BASE   (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
35669 +#define IRQ_EINT_GROUP4_BASE   (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
35670 +#define IRQ_EINT_GROUP5_BASE   (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
35671 +#define IRQ_EINT_GROUP6_BASE   (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
35672 +#define IRQ_EINT_GROUP7_BASE   (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
35673 +#define IRQ_EINT_GROUP8_BASE   (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
35674 +#define IRQ_EINT_GROUP9_BASE   (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
35675 +
35676 +#define IRQ_EINT_GROUP(group, no)      (IRQ_EINT_GROUP##group##__BASE + (x))
35677 +
35678 +/* Set the default NR_IRQS */
35679 +
35680 +#define NR_IRQS        (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
35681 +
35682 +#endif /* __ASM_PLAT_S3C64XX_IRQS_H */
35683 +
35684 --- /dev/null
35685 +++ b/arch/arm/plat-s3c64xx/include/plat/pll.h
35686 @@ -0,0 +1,74 @@
35687 +/* arch/arm/plat-s3c64xx/include/plat/pll.h
35688 + *
35689 + * Copyright 2008 Openmoko, Inc.
35690 + * Copyright 2008 Simtec Electronics
35691 + *     Ben Dooks <ben@simtec.co.uk>
35692 + *     http://armlinux.simtec.co.uk/
35693 + *
35694 + * S3C64XX PLL code
35695 + *
35696 + * This program is free software; you can redistribute it and/or modify
35697 + * it under the terms of the GNU General Public License version 2 as
35698 + * published by the Free Software Foundation.
35699 +*/
35700 +
35701 +#define S3C6400_PLL_MDIV_MASK  ((1 << (25-16+1)) - 1)
35702 +#define S3C6400_PLL_PDIV_MASK  ((1 << (13-8+1)) - 1)
35703 +#define S3C6400_PLL_SDIV_MASK  ((1 << (2-0+1)) - 1)
35704 +#define S3C6400_PLL_MDIV_SHIFT (16)
35705 +#define S3C6400_PLL_PDIV_SHIFT (8)
35706 +#define S3C6400_PLL_SDIV_SHIFT (0)
35707 +
35708 +#include <asm/div64.h>
35709 +
35710 +static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
35711 +                                           u32 pllcon)
35712 +{
35713 +       u32 mdiv, pdiv, sdiv;
35714 +       u64 fvco = baseclk;
35715 +
35716 +       mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
35717 +       pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
35718 +       sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
35719 +
35720 +       fvco *= mdiv;
35721 +       do_div(fvco, (pdiv << sdiv));
35722 +
35723 +       return (unsigned long)fvco;
35724 +}
35725 +
35726 +#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1)
35727 +#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1)
35728 +#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1)
35729 +#define S3C6400_EPLL_MDIV_SHIFT        (16)
35730 +#define S3C6400_EPLL_PDIV_SHIFT        (8)
35731 +#define S3C6400_EPLL_SDIV_SHIFT        (0)
35732 +#define S3C6400_EPLL_KDIV_MASK  (0xffff)
35733 +
35734 +static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
35735 +{
35736 +       unsigned long result;
35737 +       u32 epll0 = __raw_readl(S3C_EPLL_CON0);
35738 +       u32 epll1 = __raw_readl(S3C_EPLL_CON1);
35739 +       u32 mdiv, pdiv, sdiv, kdiv;
35740 +       u64 tmp;
35741 +
35742 +       mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
35743 +       pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
35744 +       sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
35745 +       kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
35746 +
35747 +       /* We need to multiple baseclk by mdiv (the integer part) and kdiv
35748 +        * which is in 2^16ths, so shift mdiv up (does not overflow) and
35749 +        * add kdiv before multiplying. The use of tmp is to avoid any
35750 +        * overflows before shifting bac down into result when multipling
35751 +        * by the mdiv and kdiv pair.
35752 +        */
35753 +
35754 +       tmp = baseclk;
35755 +       tmp *= (mdiv << 16) + kdiv;
35756 +       do_div(tmp, (pdiv << sdiv));
35757 +       result = tmp >> 16;
35758 +
35759 +       return result;
35760 +}
35761 --- /dev/null
35762 +++ b/arch/arm/plat-s3c64xx/include/plat/pm-core.h
35763 @@ -0,0 +1,106 @@
35764 +/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h
35765 + *
35766 + * Copyright 2008 Openmoko, Inc.
35767 + * Copyright 2008 Simtec Electronics
35768 + *      Ben Dooks <ben@simtec.co.uk>
35769 + *      http://armlinux.simtec.co.uk/
35770 + *
35771 + * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
35772 + *
35773 + * This program is free software; you can redistribute it and/or modify
35774 + * it under the terms of the GNU General Public License version 2 as
35775 + * published by the Free Software Foundation.
35776 + */
35777 +
35778 +#include <plat/regs-gpio.h>
35779 +
35780 +static inline void s3c_pm_debug_init_uart(void)
35781 +{
35782 +       u32 tmp = __raw_readl(S3C_PCLK_GATE);
35783 +
35784 +       /* As a note, since the S3C64XX UARTs generally have multiple
35785 +        * clock sources, we simply enable PCLK at the moment and hope
35786 +        * that the resume settings for the UART are suitable for the
35787 +        * use with PCLK.
35788 +        */
35789 +
35790 +       tmp |= S3C_CLKCON_PCLK_UART0;
35791 +       tmp |= S3C_CLKCON_PCLK_UART1;
35792 +       tmp |= S3C_CLKCON_PCLK_UART2;
35793 +       tmp |= S3C_CLKCON_PCLK_UART3;
35794 +
35795 +       __raw_writel(tmp, S3C_PCLK_GATE);
35796 +       udelay(10);
35797 +}
35798 +
35799 +static inline void s3c_pm_arch_clear_vic(void __iomem *base)
35800 +{
35801 +       __raw_writel(~0, base + VIC_INT_ENABLE_CLEAR);
35802 +       __raw_writel(~0, base + VIC_INT_SOFT_CLEAR);
35803 +}
35804 +
35805 +static inline void s3c_pm_arch_prepare_irqs(void)
35806 +{
35807 +       /* shutdown the VICs */
35808 +       s3c_pm_arch_clear_vic(S3C_VA_VIC0);
35809 +       s3c_pm_arch_clear_vic(S3C_VA_VIC1);
35810 +
35811 +       /* clear any pending EINT0 interrupts */
35812 +       __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
35813 +}
35814 +
35815 +static inline void s3c_pm_arch_stop_clocks(void)
35816 +{
35817 +}
35818 +
35819 +static inline void s3c_pm_arch_show_resume_irqs(void)
35820 +{
35821 +}
35822 +
35823 +/* make these defines, we currently do not have any need to change
35824 + * the IRQ wake controls depending on the CPU we are running on */
35825 +
35826 +#define s3c_irqwake_eintallow  ((1 << 28) - 1)
35827 +#define s3c_irqwake_intallow   (0)
35828 +
35829 +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
35830 +                                          struct pm_uart_save *save)
35831 +{
35832 +       u32 ucon = __raw_readl(regs + S3C2410_UCON);
35833 +       u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
35834 +       u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
35835 +       u32 new_ucon;
35836 +       u32 delta;
35837 +
35838 +       /* S3C64XX UART blocks only support level interrupts, so ensure that
35839 +        * when we restore unused UART blocks we force the level interrupt
35840 +        * settigs. */
35841 +       save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
35842 +
35843 +       /* We have a constraint on changing the clock type of the UART
35844 +        * between UCLKx and PCLK, so ensure that when we restore UCON
35845 +        * that the CLK field is correctly modified if the bootloader
35846 +        * has changed anything.
35847 +        */
35848 +       if (ucon_clk != save_clk) {
35849 +               new_ucon = save->ucon;
35850 +               delta = ucon_clk ^ save_clk;
35851 +
35852 +               /* change from UCLKx => wrong PCLK,
35853 +                * either UCLK can be tested for by a bit-test
35854 +                * with UCLK0 */
35855 +               if (ucon_clk & S3C6400_UCON_UCLK0 &&
35856 +                   !(save_clk & S3C6400_UCON_UCLK0) &&
35857 +                   delta & S3C6400_UCON_PCLK2) {
35858 +                       new_ucon &= ~S3C6400_UCON_UCLK0;
35859 +               } else if (delta == S3C6400_UCON_PCLK2) {
35860 +                       /* as an precaution, don't change from
35861 +                        * PCLK2 => PCLK or vice-versa */
35862 +                       new_ucon ^= S3C6400_UCON_PCLK2;
35863 +               }
35864 +
35865 +               S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
35866 +                         ucon, new_ucon, save->ucon);
35867 +               save->ucon = new_ucon;
35868 +       }
35869 +}
35870 --- /dev/null
35871 +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
35872 @@ -0,0 +1,225 @@
35873 +/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
35874 + *
35875 + * Copyright 2008 Openmoko, Inc.
35876 + * Copyright 2008 Simtec Electronics
35877 + *     Ben Dooks <ben@simtec.co.uk>
35878 + *     http://armlinux.simtec.co.uk/
35879 + *
35880 + * S3C64XX clock register definitions
35881 + *
35882 + * This program is free software; you can redistribute it and/or modify
35883 + * it under the terms of the GNU General Public License version 2 as
35884 + * published by the Free Software Foundation.
35885 +*/
35886 +
35887 +#ifndef __PLAT_REGS_CLOCK_H
35888 +#define __PLAT_REGS_CLOCK_H __FILE__
35889 +
35890 +#define S3C_CLKREG(x)          (S3C_VA_SYS + (x))
35891 +
35892 +#define S3C_APLL_LOCK          S3C_CLKREG(0x00)
35893 +#define S3C_MPLL_LOCK          S3C_CLKREG(0x04)
35894 +#define S3C_EPLL_LOCK          S3C_CLKREG(0x08)
35895 +#define S3C_APLL_CON           S3C_CLKREG(0x0C)
35896 +#define S3C_MPLL_CON           S3C_CLKREG(0x10)
35897 +#define S3C_EPLL_CON0          S3C_CLKREG(0x14)
35898 +#define S3C_EPLL_CON1          S3C_CLKREG(0x18)
35899 +#define S3C_CLK_SRC            S3C_CLKREG(0x1C)
35900 +#define S3C_CLK_DIV0           S3C_CLKREG(0x20)
35901 +#define S3C_CLK_DIV1           S3C_CLKREG(0x24)
35902 +#define S3C_CLK_DIV2           S3C_CLKREG(0x28)
35903 +#define S3C_CLK_OUT            S3C_CLKREG(0x2C)
35904 +#define S3C_HCLK_GATE          S3C_CLKREG(0x30)
35905 +#define S3C_PCLK_GATE          S3C_CLKREG(0x34)
35906 +#define S3C_SCLK_GATE          S3C_CLKREG(0x38)
35907 +#define S3C_MEM0_GATE          S3C_CLKREG(0x3C)
35908 +
35909 +/* CLKDIV0 */
35910 +#define S3C6400_CLKDIV0_MFC_MASK       (0xf << 28)
35911 +#define S3C6400_CLKDIV0_MFC_SHIFT      (28)
35912 +#define S3C6400_CLKDIV0_JPEG_MASK      (0xf << 24)
35913 +#define S3C6400_CLKDIV0_JPEG_SHIFT     (24)
35914 +#define S3C6400_CLKDIV0_CAM_MASK       (0xf << 20)
35915 +#define S3C6400_CLKDIV0_CAM_SHIFT      (20)
35916 +#define S3C6400_CLKDIV0_SECURITY_MASK  (0x3 << 18)
35917 +#define S3C6400_CLKDIV0_SECURITY_SHIFT (18)
35918 +#define S3C6400_CLKDIV0_PCLK_MASK      (0xf << 12)
35919 +#define S3C6400_CLKDIV0_PCLK_SHIFT     (12)
35920 +#define S3C6400_CLKDIV0_HCLK2_MASK     (0x7 << 9)
35921 +#define S3C6400_CLKDIV0_HCLK2_SHIFT    (9)
35922 +#define S3C6400_CLKDIV0_HCLK_MASK      (0x1 << 8)
35923 +#define S3C6400_CLKDIV0_HCLK_SHIFT     (8)
35924 +#define S3C6400_CLKDIV0_MPLL_MASK      (0x1 << 4)
35925 +#define S3C6400_CLKDIV0_MPLL_SHIFT     (4)
35926 +#define S3C6400_CLKDIV0_ARM_MASK       (0x3 << 0)
35927 +#define S3C6410_CLKDIV0_ARM_MASK       (0x7 << 0)
35928 +#define S3C6400_CLKDIV0_ARM_SHIFT      (0)
35929 +
35930 +/* CLKDIV1 */
35931 +#define S3C6410_CLKDIV1_FIMC_MASK      (0xf << 24)
35932 +#define S3C6410_CLKDIV1_FIMC_SHIFT     (24)
35933 +#define S3C6400_CLKDIV1_UHOST_MASK     (0xf << 20)
35934 +#define S3C6400_CLKDIV1_UHOST_SHIFT    (20)
35935 +#define S3C6400_CLKDIV1_SCALER_MASK    (0xf << 16)
35936 +#define S3C6400_CLKDIV1_SCALER_SHIFT   (16)
35937 +#define S3C6400_CLKDIV1_LCD_MASK       (0xf << 12)
35938 +#define S3C6400_CLKDIV1_LCD_SHIFT      (12)
35939 +#define S3C6400_CLKDIV1_MMC2_MASK      (0xf << 8)
35940 +#define S3C6400_CLKDIV1_MMC2_SHIFT     (8)
35941 +#define S3C6400_CLKDIV1_MMC1_MASK      (0xf << 4)
35942 +#define S3C6400_CLKDIV1_MMC1_SHIFT     (4)
35943 +#define S3C6400_CLKDIV1_MMC0_MASK      (0xf << 0)
35944 +#define S3C6400_CLKDIV1_MMC0_SHIFT     (0)
35945 +
35946 +/* CLKDIV2 */
35947 +#define S3C6410_CLKDIV2_AUDIO2_MASK    (0xf << 24)
35948 +#define S3C6410_CLKDIV2_AUDIO2_SHIFT   (24)
35949 +#define S3C6400_CLKDIV2_IRDA_MASK      (0xf << 20)
35950 +#define S3C6400_CLKDIV2_IRDA_SHIFT     (20)
35951 +#define S3C6400_CLKDIV2_UART_MASK      (0xf << 16)
35952 +#define S3C6400_CLKDIV2_UART_SHIFT     (16)
35953 +#define S3C6400_CLKDIV2_AUDIO1_MASK    (0xf << 12)
35954 +#define S3C6400_CLKDIV2_AUDIO1_SHIFT   (12)
35955 +#define S3C6400_CLKDIV2_AUDIO0_MASK    (0xf << 8)
35956 +#define S3C6400_CLKDIV2_AUDIO0_SHIFT   (8)
35957 +#define S3C6400_CLKDIV2_SPI1_MASK      (0xf << 4)
35958 +#define S3C6400_CLKDIV2_SPI1_SHIFT     (4)
35959 +#define S3C6400_CLKDIV2_SPI0_MASK      (0xf << 0)
35960 +#define S3C6400_CLKDIV2_SPI0_SHIFT     (0)
35961 +
35962 +/* HCLK GATE Registers */
35963 +#define S3C_CLKCON_HCLK_BUS    (1<<30)
35964 +#define S3C_CLKCON_HCLK_SECUR  (1<<29)
35965 +#define S3C_CLKCON_HCLK_SDMA1  (1<<28)
35966 +#define S3C_CLKCON_HCLK_SDMA2  (1<<27)
35967 +#define S3C_CLKCON_HCLK_UHOST  (1<<26)
35968 +#define S3C_CLKCON_HCLK_IROM   (1<<25)
35969 +#define S3C_CLKCON_HCLK_DDR1   (1<<24)
35970 +#define S3C_CLKCON_HCLK_DDR0   (1<<23)
35971 +#define S3C_CLKCON_HCLK_MEM1   (1<<22)
35972 +#define S3C_CLKCON_HCLK_MEM0   (1<<21)
35973 +#define S3C_CLKCON_HCLK_USB    (1<<20)
35974 +#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
35975 +#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
35976 +#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
35977 +#define S3C_CLKCON_HCLK_MDP    (1<<16)
35978 +#define S3C_CLKCON_HCLK_DHOST  (1<<15)
35979 +#define S3C_CLKCON_HCLK_IHOST  (1<<14)
35980 +#define S3C_CLKCON_HCLK_DMA1   (1<<13)
35981 +#define S3C_CLKCON_HCLK_DMA0   (1<<12)
35982 +#define S3C_CLKCON_HCLK_JPEG   (1<<11)
35983 +#define S3C_CLKCON_HCLK_CAMIF  (1<<10)
35984 +#define S3C_CLKCON_HCLK_SCALER (1<<9)
35985 +#define S3C_CLKCON_HCLK_2D     (1<<8)
35986 +#define S3C_CLKCON_HCLK_TV     (1<<7)
35987 +#define S3C_CLKCON_HCLK_POST0  (1<<5)
35988 +#define S3C_CLKCON_HCLK_ROT    (1<<4)
35989 +#define S3C_CLKCON_HCLK_LCD    (1<<3)
35990 +#define S3C_CLKCON_HCLK_TZIC   (1<<2)
35991 +#define S3C_CLKCON_HCLK_INTC   (1<<1)
35992 +#define S3C_CLKCON_HCLK_MFC    (1<<0)
35993 +
35994 +/* PCLK GATE Registers */
35995 +#define S3C6410_CLKCON_PCLK_I2C1       (1<<27)
35996 +#define S3C6410_CLKCON_PCLK_IIS2       (1<<26)
35997 +#define S3C_CLKCON_PCLK_SKEY           (1<<24)
35998 +#define S3C_CLKCON_PCLK_CHIPID         (1<<23)
35999 +#define S3C_CLKCON_PCLK_SPI1           (1<<22)
36000 +#define S3C_CLKCON_PCLK_SPI0           (1<<21)
36001 +#define S3C_CLKCON_PCLK_HSIRX          (1<<20)
36002 +#define S3C_CLKCON_PCLK_HSITX          (1<<19)
36003 +#define S3C_CLKCON_PCLK_GPIO           (1<<18)
36004 +#define S3C_CLKCON_PCLK_IIC            (1<<17)
36005 +#define S3C_CLKCON_PCLK_IIS1           (1<<16)
36006 +#define S3C_CLKCON_PCLK_IIS0           (1<<15)
36007 +#define S3C_CLKCON_PCLK_AC97           (1<<14)
36008 +#define S3C_CLKCON_PCLK_TZPC           (1<<13)
36009 +#define S3C_CLKCON_PCLK_TSADC          (1<<12)
36010 +#define S3C_CLKCON_PCLK_KEYPAD         (1<<11)
36011 +#define S3C_CLKCON_PCLK_IRDA           (1<<10)
36012 +#define S3C_CLKCON_PCLK_PCM1           (1<<9)
36013 +#define S3C_CLKCON_PCLK_PCM0           (1<<8)
36014 +#define S3C_CLKCON_PCLK_PWM            (1<<7)
36015 +#define S3C_CLKCON_PCLK_RTC            (1<<6)
36016 +#define S3C_CLKCON_PCLK_WDT            (1<<5)
36017 +#define S3C_CLKCON_PCLK_UART3          (1<<4)
36018 +#define S3C_CLKCON_PCLK_UART2          (1<<3)
36019 +#define S3C_CLKCON_PCLK_UART1          (1<<2)
36020 +#define S3C_CLKCON_PCLK_UART0          (1<<1)
36021 +#define S3C_CLKCON_PCLK_MFC            (1<<0)
36022 +
36023 +/* SCLK GATE Registers */
36024 +#define S3C_CLKCON_SCLK_UHOST          (1<<30)
36025 +#define S3C_CLKCON_SCLK_MMC2_48                (1<<29)
36026 +#define S3C_CLKCON_SCLK_MMC1_48                (1<<28)
36027 +#define S3C_CLKCON_SCLK_MMC0_48                (1<<27)
36028 +#define S3C_CLKCON_SCLK_MMC2           (1<<26)
36029 +#define S3C_CLKCON_SCLK_MMC1           (1<<25)
36030 +#define S3C_CLKCON_SCLK_MMC0           (1<<24)
36031 +#define S3C_CLKCON_SCLK_SPI1_48        (1<<23)
36032 +#define S3C_CLKCON_SCLK_SPI0_48        (1<<22)
36033 +#define S3C_CLKCON_SCLK_SPI1           (1<<21)
36034 +#define S3C_CLKCON_SCLK_SPI0           (1<<20)
36035 +#define S3C_CLKCON_SCLK_DAC27          (1<<19)
36036 +#define S3C_CLKCON_SCLK_TV27           (1<<18)
36037 +#define S3C_CLKCON_SCLK_SCALER27       (1<<17)
36038 +#define S3C_CLKCON_SCLK_SCALER         (1<<16)
36039 +#define S3C_CLKCON_SCLK_LCD27          (1<<15)
36040 +#define S3C_CLKCON_SCLK_LCD            (1<<14)
36041 +#define S3C6400_CLKCON_SCLK_POST1_27   (1<<13)
36042 +#define S3C6410_CLKCON_FIMC            (1<<13)
36043 +#define S3C_CLKCON_SCLK_POST0_27       (1<<12)
36044 +#define S3C6400_CLKCON_SCLK_POST1      (1<<11)
36045 +#define S3C6410_CLKCON_SCLK_AUDIO2     (1<<11)
36046 +#define S3C_CLKCON_SCLK_POST0          (1<<10)
36047 +#define S3C_CLKCON_SCLK_AUDIO1         (1<<9)
36048 +#define S3C_CLKCON_SCLK_AUDIO0         (1<<8)
36049 +#define S3C_CLKCON_SCLK_SECUR          (1<<7)
36050 +#define S3C_CLKCON_SCLK_IRDA           (1<<6)
36051 +#define S3C_CLKCON_SCLK_UART           (1<<5)
36052 +#define S3C_CLKCON_SCLK_ONENAND        (1<<4)
36053 +#define S3C_CLKCON_SCLK_MFC            (1<<3)
36054 +#define S3C_CLKCON_SCLK_CAM            (1<<2)
36055 +#define S3C_CLKCON_SCLK_JPEG           (1<<1)
36056 +
36057 +/* CLKSRC */
36058 +
36059 +#define S3C6400_CLKSRC_APLL_MOUT       (1 << 0)
36060 +#define S3C6400_CLKSRC_MPLL_MOUT       (1 << 1)
36061 +#define S3C6400_CLKSRC_EPLL_MOUT       (1 << 2)
36062 +#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
36063 +#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
36064 +#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
36065 +#define S3C6400_CLKSRC_MFC             (1 << 4)
36066 +
36067 +#define S3C6410_CLKSRC_TV27_MASK       (0x1 << 31)
36068 +#define S3C6410_CLKSRC_TV27_SHIFT      (31)
36069 +#define S3C6410_CLKSRC_DAC27_MASK      (0x1 << 30)
36070 +#define S3C6410_CLKSRC_DAC27_SHIFT     (30)
36071 +#define S3C6400_CLKSRC_SCALER_MASK     (0x3 << 28)
36072 +#define S3C6400_CLKSRC_SCALER_SHIFT    (28)
36073 +#define S3C6400_CLKSRC_LCD_MASK                (0x3 << 26)
36074 +#define S3C6400_CLKSRC_LCD_SHIFT       (26)
36075 +#define S3C6400_CLKSRC_IRDA_MASK       (0x3 << 24)
36076 +#define S3C6400_CLKSRC_IRDA_SHIFT      (24)
36077 +#define S3C6400_CLKSRC_MMC2_MASK       (0x3 << 22)
36078 +#define S3C6400_CLKSRC_MMC2_SHIFT      (22)
36079 +#define S3C6400_CLKSRC_MMC1_MASK       (0x3 << 20)
36080 +#define S3C6400_CLKSRC_MMC1_SHIFT      (20)
36081 +#define S3C6400_CLKSRC_MMC0_MASK       (0x3 << 18)
36082 +#define S3C6400_CLKSRC_MMC0_SHIFT      (18)
36083 +#define S3C6400_CLKSRC_SPI1_MASK       (0x3 << 16)
36084 +#define S3C6400_CLKSRC_SPI1_SHIFT      (16)
36085 +#define S3C6400_CLKSRC_SPI0_MASK       (0x3 << 14)
36086 +#define S3C6400_CLKSRC_SPI0_SHIFT      (14)
36087 +#define S3C6400_CLKSRC_UART_MASK       (0x1 << 13)
36088 +#define S3C6400_CLKSRC_UART_SHIFT      (13)
36089 +#define S3C6400_CLKSRC_AUDIO1_MASK     (0x7 << 10)
36090 +#define S3C6400_CLKSRC_AUDIO1_SHIFT    (10)
36091 +#define S3C6400_CLKSRC_AUDIO0_MASK     (0x7 << 7)
36092 +#define S3C6400_CLKSRC_AUDIO0_SHIFT    (7)
36093 +#define S3C6400_CLKSRC_UHOST_MASK      (0x3 << 5)
36094 +#define S3C6400_CLKSRC_UHOST_SHIFT     (5)
36095 +
36096 +
36097 +#endif /* _PLAT_REGS_CLOCK_H */
36098 --- /dev/null
36099 +++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
36100 @@ -0,0 +1,187 @@
36101 +/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
36102 + *
36103 + * Copyright 2008 Openmoko, Inc.
36104 + * Copyright 2008 Simtec Electronics
36105 + *      Ben Dooks <ben@simtec.co.uk>
36106 + *      http://armlinux.simtec.co.uk/
36107 + *
36108 + * S3C64XX - GPIO register definitions
36109 + */
36110 +
36111 +#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
36112 +#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
36113 +
36114 +/* Base addresses for each of the banks */
36115 +
36116 +#define S3C64XX_GPIOREG(reg)   (S3C64XX_VA_GPIO + (reg))
36117 +
36118 +#define S3C64XX_GPA_BASE       S3C64XX_GPIOREG(0x0000)
36119 +#define S3C64XX_GPB_BASE       S3C64XX_GPIOREG(0x0020)
36120 +#define S3C64XX_GPC_BASE       S3C64XX_GPIOREG(0x0040)
36121 +#define S3C64XX_GPD_BASE       S3C64XX_GPIOREG(0x0060)
36122 +#define S3C64XX_GPE_BASE       S3C64XX_GPIOREG(0x0080)
36123 +#define S3C64XX_GPF_BASE       S3C64XX_GPIOREG(0x00A0)
36124 +#define S3C64XX_GPG_BASE       S3C64XX_GPIOREG(0x00C0)
36125 +#define S3C64XX_GPH_BASE       S3C64XX_GPIOREG(0x00E0)
36126 +#define S3C64XX_GPI_BASE       S3C64XX_GPIOREG(0x0100)
36127 +#define S3C64XX_GPJ_BASE       S3C64XX_GPIOREG(0x0120)
36128 +#define S3C64XX_GPK_BASE       S3C64XX_GPIOREG(0x0800)
36129 +#define S3C64XX_GPL_BASE       S3C64XX_GPIOREG(0x0810)
36130 +#define S3C64XX_GPM_BASE       S3C64XX_GPIOREG(0x0820)
36131 +#define S3C64XX_GPN_BASE       S3C64XX_GPIOREG(0x0830)
36132 +#define S3C64XX_GPO_BASE       S3C64XX_GPIOREG(0x0140)
36133 +#define S3C64XX_GPP_BASE       S3C64XX_GPIOREG(0x0160)
36134 +#define S3C64XX_GPQ_BASE       S3C64XX_GPIOREG(0x0180)
36135 +
36136 +/* SPCON */
36137 +
36138 +#define S3C64XX_SPCON          S3C64XX_GPIOREG(0x1A0)
36139 +
36140 +#define S3C64XX_SPCON_DRVCON_CAM_MASK          (0x3 << 30)
36141 +#define S3C64XX_SPCON_DRVCON_CAM_SHIFT         (30)
36142 +#define S3C64XX_SPCON_DRVCON_CAM_2mA           (0x0 << 30)
36143 +#define S3C64XX_SPCON_DRVCON_CAM_4mA           (0x1 << 30)
36144 +#define S3C64XX_SPCON_DRVCON_CAM_7mA           (0x2 << 30)
36145 +#define S3C64XX_SPCON_DRVCON_CAM_9mA           (0x3 << 30)
36146 +
36147 +#define S3C64XX_SPCON_DRVCON_HSSPI_MASK                (0x3 << 28)
36148 +#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT       (28)
36149 +#define S3C64XX_SPCON_DRVCON_HSSPI_2mA         (0x0 << 28)
36150 +#define S3C64XX_SPCON_DRVCON_HSSPI_4mA         (0x1 << 28)
36151 +#define S3C64XX_SPCON_DRVCON_HSSPI_7mA         (0x2 << 28)
36152 +#define S3C64XX_SPCON_DRVCON_HSSPI_9mA         (0x3 << 28)
36153 +
36154 +#define S3C64XX_SPCON_DRVCON_HSMMC_MASK                (0x3 << 26)
36155 +#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT       (26)
36156 +#define S3C64XX_SPCON_DRVCON_HSMMC_2mA         (0x0 << 26)
36157 +#define S3C64XX_SPCON_DRVCON_HSMMC_4mA         (0x1 << 26)
36158 +#define S3C64XX_SPCON_DRVCON_HSMMC_7mA         (0x2 << 26)
36159 +#define S3C64XX_SPCON_DRVCON_HSMMC_9mA         (0x3 << 26)
36160 +
36161 +#define S3C64XX_SPCON_DRVCON_LCD_MASK          (0x3 << 24)
36162 +#define S3C64XX_SPCON_DRVCON_LCD_SHIFT         (24)
36163 +#define S3C64XX_SPCON_DRVCON_LCD_2mA           (0x0 << 24)
36164 +#define S3C64XX_SPCON_DRVCON_LCD_4mA           (0x1 << 24)
36165 +#define S3C64XX_SPCON_DRVCON_LCD_7mA           (0x2 << 24)
36166 +#define S3C64XX_SPCON_DRVCON_LCD_9mA           (0x3 << 24)
36167 +
36168 +#define S3C64XX_SPCON_DRVCON_MODEM_MASK                (0x3 << 22)
36169 +#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT       (22)
36170 +#define S3C64XX_SPCON_DRVCON_MODEM_2mA         (0x0 << 22)
36171 +#define S3C64XX_SPCON_DRVCON_MODEM_4mA         (0x1 << 22)
36172 +#define S3C64XX_SPCON_DRVCON_MODEM_7mA         (0x2 << 22)
36173 +#define S3C64XX_SPCON_DRVCON_MODEM_9mA         (0x3 << 22)
36174 +
36175 +#define S3C64XX_SPCON_nRSTOUT_OEN              (1 << 21)
36176 +
36177 +#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK      (0x3 << 18)
36178 +#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT     (18)
36179 +#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA       (0x0 << 18)
36180 +#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA       (0x1 << 18)
36181 +#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA       (0x2 << 18)
36182 +#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA       (0x3 << 18)
36183 +
36184 +#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK                (0x3 << 16)
36185 +#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT       (16)
36186 +#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED    (0x0 << 16)
36187 +#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN                (0x1 << 16)
36188 +#define S3C64XX_SPCON_MEM1_DQS_PUD_UP          (0x2 << 16)
36189 +
36190 +#define S3C64XX_SPCON_MEM1_D_PUD1_MASK         (0x3 << 14)
36191 +#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT                (14)
36192 +#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED     (0x0 << 14)
36193 +#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN         (0x1 << 14)
36194 +#define S3C64XX_SPCON_MEM1_D_PUD1_UP           (0x2 << 14)
36195 +
36196 +#define S3C64XX_SPCON_MEM1_D_PUD0_MASK         (0x3 << 12)
36197 +#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT                (12)
36198 +#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED     (0x0 << 12)
36199 +#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN         (0x1 << 12)
36200 +#define S3C64XX_SPCON_MEM1_D_PUD0_UP           (0x2 << 12)
36201 +
36202 +#define S3C64XX_SPCON_MEM0_D_PUD_MASK          (0x3 << 8)
36203 +#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT         (8)
36204 +#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED      (0x0 << 8)
36205 +#define S3C64XX_SPCON_MEM0_D_PUD_DOWN          (0x1 << 8)
36206 +#define S3C64XX_SPCON_MEM0_D_PUD_UP            (0x2 << 8)
36207 +
36208 +#define S3C64XX_SPCON_USBH_DMPD                        (1 << 7)
36209 +#define S3C64XX_SPCON_USBH_DPPD                        (1 << 6)
36210 +#define S3C64XX_SPCON_USBH_PUSW2               (1 << 5)
36211 +#define S3C64XX_SPCON_USBH_PUSW1               (1 << 4)
36212 +#define S3C64XX_SPCON_USBH_SUSPND              (1 << 3)
36213 +
36214 +#define S3C64XX_SPCON_LCD_SEL_MASK             (0x3 << 0)
36215 +#define S3C64XX_SPCON_LCD_SEL_SHIFT            (0)
36216 +#define S3C64XX_SPCON_LCD_SEL_HOST             (0x0 << 0)
36217 +#define S3C64XX_SPCON_LCD_SEL_RGB              (0x1 << 0)
36218 +#define S3C64XX_SPCON_LCD_SEL_606_656          (0x2 << 0)
36219 +
36220 +
36221 +/* External interrupt registers */
36222 +
36223 +#define S3C64XX_EINT12CON      S3C64XX_GPIOREG(0x200)
36224 +#define S3C64XX_EINT34CON      S3C64XX_GPIOREG(0x204)
36225 +#define S3C64XX_EINT56CON      S3C64XX_GPIOREG(0x208)
36226 +#define S3C64XX_EINT78CON      S3C64XX_GPIOREG(0x20C)
36227 +#define S3C64XX_EINT9CON       S3C64XX_GPIOREG(0x210)
36228 +
36229 +#define S3C64XX_EINT12FLTCON   S3C64XX_GPIOREG(0x220)
36230 +#define S3C64XX_EINT34FLTCON   S3C64XX_GPIOREG(0x224)
36231 +#define S3C64XX_EINT56FLTCON   S3C64XX_GPIOREG(0x228)
36232 +#define S3C64XX_EINT78FLTCON   S3C64XX_GPIOREG(0x22C)
36233 +#define S3C64XX_EINT9FLTCON    S3C64XX_GPIOREG(0x230)
36234 +
36235 +#define S3C64XX_EINT12MASK     S3C64XX_GPIOREG(0x240)
36236 +#define S3C64XX_EINT34MASK     S3C64XX_GPIOREG(0x244)
36237 +#define S3C64XX_EINT56MASK     S3C64XX_GPIOREG(0x248)
36238 +#define S3C64XX_EINT78MASK     S3C64XX_GPIOREG(0x24C)
36239 +#define S3C64XX_EINT9MASK      S3C64XX_GPIOREG(0x250)
36240 +
36241 +#define S3C64XX_EINT12PEND     S3C64XX_GPIOREG(0x260)
36242 +#define S3C64XX_EINT34PEND     S3C64XX_GPIOREG(0x264)
36243 +#define S3C64XX_EINT56PEND     S3C64XX_GPIOREG(0x268)
36244 +#define S3C64XX_EINT78PEND     S3C64XX_GPIOREG(0x26C)
36245 +#define S3C64XX_EINT9PEND      S3C64XX_GPIOREG(0x270)
36246 +
36247 +#define S3C64XX_PRIORITY       S3C64XX_GPIOREG(0x280)
36248 +#define S3C64XX_PRIORITY_ARB(x)        (1 << (x))
36249 +
36250 +#define S3C64XX_SERVICE                S3C64XX_GPIOREG(0x284)
36251 +#define S3C64XX_SERVICEPEND    S3C64XX_GPIOREG(0x288)
36252 +
36253 +#define S3C64XX_EINT0CON0      S3C64XX_GPIOREG(0x900)
36254 +#define S3C64XX_EINT0CON1      S3C64XX_GPIOREG(0x904)
36255 +#define S3C64XX_EINT0FLTCON0   S3C64XX_GPIOREG(0x910)
36256 +#define S3C64XX_EINT0FLTCON1   S3C64XX_GPIOREG(0x914)
36257 +#define S3C64XX_EINT0FLTCON2   S3C64XX_GPIOREG(0x918)
36258 +#define S3C64XX_EINT0FLTCON3   S3C64XX_GPIOREG(0x91C)
36259 +
36260 +#define S3C64XX_EINT0MASK      S3C64XX_GPIOREG(0x920)
36261 +#define S3C64XX_EINT0PEND      S3C64XX_GPIOREG(0x924)
36262 +
36263 +/* GPIO sleep configuration */
36264 +
36265 +#define S3C64XX_SPCONSLP       S3C64XX_GPIOREG(0x880)
36266 +
36267 +#define S3C64XX_SPCONSLP_TDO_PULLDOWN  (1 << 14)
36268 +#define S3C64XX_SPCONSLP_CKE1INIT      (1 << 5)
36269 +
36270 +#define S3C64XX_SPCONSLP_RSTOUT_MASK   (0x3 << 12)
36271 +#define S3C64XX_SPCONSLP_RSTOUT_OUT0   (0x0 << 12)
36272 +#define S3C64XX_SPCONSLP_RSTOUT_OUT1   (0x1 << 12)
36273 +#define S3C64XX_SPCONSLP_RSTOUT_HIZ    (0x2 << 12)
36274 +
36275 +#define S3C64XX_SPCONSLP_KPCOL_MASK    (0x3 << 0)
36276 +#define S3C64XX_SPCONSLP_KPCOL_OUT0    (0x0 << 0)
36277 +#define S3C64XX_SPCONSLP_KPCOL_OUT1    (0x1 << 0)
36278 +#define S3C64XX_SPCONSLP_KPCOL_INP     (0x2 << 0)
36279 +
36280 +
36281 +#define S3C64XX_SLPEN          S3C64XX_GPIOREG(0x930)
36282 +
36283 +#define S3C64XX_SLPEN_USE_xSLP         (1 << 0)
36284 +#define S3C64XX_SLPEN_CFG_BYSLPEN      (1 << 1)
36285 +
36286 +#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
36287 +
36288 --- /dev/null
36289 +++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h
36290 @@ -0,0 +1,25 @@
36291 +/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
36292 + *
36293 + * Copyright 2008 Openmoko, Inc.
36294 + * Copyright 2008 Simtec Electronics
36295 + *      Ben Dooks <ben@simtec.co.uk>
36296 + *      http://armlinux.simtec.co.uk/
36297 + *
36298 + * S3C64XX - GPIO memory port register definitions
36299 + */
36300 +
36301 +#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
36302 +#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
36303 +
36304 +#define S3C64XX_MEM0CONSTOP    S3C64XX_GPIOREG(0x1B0)
36305 +#define S3C64XX_MEM1CONSTOP    S3C64XX_GPIOREG(0x1B4)
36306 +
36307 +#define S3C64XX_MEM0CONSLP0    S3C64XX_GPIOREG(0x1C0)
36308 +#define S3C64XX_MEM0CONSLP1    S3C64XX_GPIOREG(0x1C4)
36309 +#define S3C64XX_MEM1CONSLP     S3C64XX_GPIOREG(0x1C8)
36310 +
36311 +#define S3C64XX_MEM0DRVCON     S3C64XX_GPIOREG(0x1D0)
36312 +#define S3C64XX_MEM1DRVCON     S3C64XX_GPIOREG(0x1D4)
36313 +
36314 +#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
36315 +
36316 --- /dev/null
36317 +++ b/arch/arm/plat-s3c64xx/include/plat/regs-modem.h
36318 @@ -0,0 +1,31 @@
36319 +/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
36320 + *
36321 + * Copyright 2008 Openmoko, Inc.
36322 + * Copyright 2008 Simtec Electronics
36323 + *      http://armlinux.simtec.co.uk/
36324 + *      Ben Dooks <ben@simtec.co.uk>
36325 + *
36326 + * S3C64XX - modem block registers
36327 + *
36328 + * This program is free software; you can redistribute it and/or modify
36329 + * it under the terms of the GNU General Public License version 2 as
36330 + * published by the Free Software Foundation.
36331 +*/
36332 +
36333 +#ifndef __PLAT_S3C64XX_REGS_MODEM_H
36334 +#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
36335 +
36336 +#define S3C64XX_MODEMREG(x)    (S3C64XX_VA_MODEM + (x))
36337 +
36338 +#define S3C64XX_MODEM_INT2AP                   S3C64XX_MODEMREG(0x0)
36339 +#define S3C64XX_MODEM_INT2MODEM                        S3C64XX_MODEMREG(0x4)
36340 +#define S3C64XX_MODEM_MIFCON                   S3C64XX_MODEMREG(0x8)
36341 +#define S3C64XX_MODEM_MIFPCON                  S3C64XX_MODEMREG(0xC)
36342 +#define S3C64XX_MODEM_INTCLR                   S3C64XX_MODEMREG(0x10)
36343 +#define S3C64XX_MODEM_DMA_TXADDR               S3C64XX_MODEMREG(0x14)
36344 +#define S3C64XX_MODEM_DMA_RXADDR               S3C64XX_MODEMREG(0x18)
36345 +
36346 +#define MIFPCON_INT2M_LEVEL                    (1 << 4)
36347 +#define MIFPCON_LCD_BYPASS                     (1 << 3)
36348 +
36349 +#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
36350 --- /dev/null
36351 +++ b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
36352 @@ -0,0 +1,116 @@
36353 +/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
36354 + *
36355 + * Copyright 2008 Openmoko, Inc.
36356 + * Copyright 2008 Simtec Electronics
36357 + *      http://armlinux.simtec.co.uk/
36358 + *      Ben Dooks <ben@simtec.co.uk>
36359 + *
36360 + * S3C64XX - syscon power and sleep control registers
36361 + *
36362 + * This program is free software; you can redistribute it and/or modify
36363 + * it under the terms of the GNU General Public License version 2 as
36364 + * published by the Free Software Foundation.
36365 +*/
36366 +
36367 +#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
36368 +#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
36369 +
36370 +#define S3C64XX_PWR_CFG                                S3C_SYSREG(0x804)
36371 +
36372 +#define S3C64XX_PWRCFG_OSC_OTG_DISABLE         (1 << 17)
36373 +#define S3C64XX_PWRCFG_MMC2_DISABLE            (1 << 16)
36374 +#define S3C64XX_PWRCFG_MMC1_DISABLE            (1 << 15)
36375 +#define S3C64XX_PWRCFG_MMC0_DISABLE            (1 << 14)
36376 +#define S3C64XX_PWRCFG_HSI_DISABLE             (1 << 13)
36377 +#define S3C64XX_PWRCFG_TS_DISABLE              (1 << 12)
36378 +#define S3C64XX_PWRCFG_RTC_TICK_DISABLE                (1 << 11)
36379 +#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE       (1 << 10)
36380 +#define S3C64XX_PWRCFG_MSM_DISABLE             (1 << 9)
36381 +#define S3C64XX_PWRCFG_KEY_DISABLE             (1 << 8)
36382 +#define S3C64XX_PWRCFG_BATF_DISABLE            (1 << 7)
36383 +
36384 +#define S3C64XX_PWRCFG_CFG_WFI_MASK            (0x3 << 5)
36385 +#define S3C64XX_PWRCFG_CFG_WFI_SHIFT           (5)
36386 +#define S3C64XX_PWRCFG_CFG_WFI_IGNORE          (0x0 << 5)
36387 +#define S3C64XX_PWRCFG_CFG_WFI_IDLE            (0x1 << 5)
36388 +#define S3C64XX_PWRCFG_CFG_WFI_STOP            (0x2 << 5)
36389 +#define S3C64XX_PWRCFG_CFG_WFI_SLEEP           (0x3 << 5)
36390 +
36391 +#define S3C64XX_PWRCFG_CFG_BATFLT_MASK         (0x3 << 3)
36392 +#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT                (3)
36393 +#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE       (0x0 << 3)
36394 +#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ          (0x1 << 3)
36395 +#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP                (0x3 << 3)
36396 +
36397 +#define S3C64XX_PWRCFG_CFG_BAT_WAKE            (1 << 2)
36398 +#define S3C64XX_PWRCFG_OSC27_EN                        (1 << 0)
36399 +
36400 +#define S3C64XX_EINT_MASK                      S3C_SYSREG(0x808)
36401 +
36402 +#define S3C64XX_NORMAL_CFG                     S3C_SYSREG(0x810)
36403 +
36404 +#define S3C64XX_NORMALCFG_IROM_ON              (1 << 30)
36405 +#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON                (1 << 16)
36406 +#define S3C64XX_NORMALCFG_DOMAIN_S_ON          (1 << 15)
36407 +#define S3C64XX_NORMALCFG_DOMAIN_F_ON          (1 << 14)
36408 +#define S3C64XX_NORMALCFG_DOMAIN_P_ON          (1 << 13)
36409 +#define S3C64XX_NORMALCFG_DOMAIN_I_ON          (1 << 12)
36410 +#define S3C64XX_NORMALCFG_DOMAIN_G_ON          (1 << 10)
36411 +#define S3C64XX_NORMALCFG_DOMAIN_V_ON          (1 << 9)
36412 +
36413 +#define S3C64XX_STOP_CFG                       S3C_SYSREG(0x814)
36414 +
36415 +#define S3C64XX_STOPCFG_MEMORY_ARM_ON          (1 << 29)
36416 +#define S3C64XX_STOPCFG_TOP_MEMORY_ON          (1 << 20)
36417 +#define S3C64XX_STOPCFG_ARM_LOGIC_ON           (1 << 17)
36418 +#define S3C64XX_STOPCFG_TOP_LOGIC_ON           (1 << 8)
36419 +#define S3C64XX_STOPCFG_OSC_EN                 (1 << 0)
36420 +
36421 +#define S3C64XX_SLEEP_CFG                      S3C_SYSREG(0x818)
36422 +
36423 +#define S3C64XX_SLEEPCFG_OSC_EN                        (1 << 0)
36424 +
36425 +#define S3C64XX_STOP_MEM_CFG                   S3C_SYSREG(0x81c)
36426 +
36427 +#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN      (1 << 6)
36428 +#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN       (1 << 5)
36429 +#define S3C64XX_STOPMEMCFG_OTG_RETAIN          (1 << 4)
36430 +#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN                (1 << 3)
36431 +#define S3C64XX_STOPMEMCFG_IROM_RETAIN         (1 << 2)
36432 +#define S3C64XX_STOPMEMCFG_IRDA_RETAIN         (1 << 1)
36433 +#define S3C64XX_STOPMEMCFG_NFCON_RETAIN                (1 << 0)
36434 +
36435 +#define S3C64XX_OSC_STABLE                     S3C_SYSREG(0x824)
36436 +#define S3C64XX_PWR_STABLE                     S3C_SYSREG(0x828)
36437 +
36438 +#define S3C64XX_WAKEUP_STAT                    S3C_SYSREG(0x908)
36439 +
36440 +#define S3C64XX_WAKEUPSTAT_MMC2                        (1 << 11)
36441 +#define S3C64XX_WAKEUPSTAT_MMC1                        (1 << 10)
36442 +#define S3C64XX_WAKEUPSTAT_MMC0                        (1 << 9)
36443 +#define S3C64XX_WAKEUPSTAT_HSI                 (1 << 8)
36444 +#define S3C64XX_WAKEUPSTAT_BATFLT              (1 << 6)
36445 +#define S3C64XX_WAKEUPSTAT_MSM                 (1 << 5)
36446 +#define S3C64XX_WAKEUPSTAT_KEY                 (1 << 4)
36447 +#define S3C64XX_WAKEUPSTAT_TS                  (1 << 3)
36448 +#define S3C64XX_WAKEUPSTAT_RTC_TICK            (1 << 2)
36449 +#define S3C64XX_WAKEUPSTAT_RTC_ALARM           (1 << 1)
36450 +#define S3C64XX_WAKEUPSTAT_EINT                        (1 << 0)
36451 +
36452 +#define S3C64XX_BLK_PWR_STAT                   S3C_SYSREG(0x90c)
36453 +
36454 +#define S3C64XX_BLKPWRSTAT_G                   (1 << 7)
36455 +#define S3C64XX_BLKPWRSTAT_ETM                 (1 << 6)
36456 +#define S3C64XX_BLKPWRSTAT_S                   (1 << 5)
36457 +#define S3C64XX_BLKPWRSTAT_F                   (1 << 4)
36458 +#define S3C64XX_BLKPWRSTAT_P                   (1 << 3)
36459 +#define S3C64XX_BLKPWRSTAT_I                   (1 << 2)
36460 +#define S3C64XX_BLKPWRSTAT_V                   (1 << 1)
36461 +#define S3C64XX_BLKPWRSTAT_TOP                 (1 << 0)
36462 +
36463 +#define S3C64XX_INFORM0                                S3C_SYSREG(0xA00)
36464 +#define S3C64XX_INFORM1                                S3C_SYSREG(0xA04)
36465 +#define S3C64XX_INFORM2                                S3C_SYSREG(0xA08)
36466 +#define S3C64XX_INFORM3                                S3C_SYSREG(0xA0C)
36467 +
36468 +#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
36469 --- /dev/null
36470 +++ b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
36471 @@ -0,0 +1,28 @@
36472 +/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
36473 + *
36474 + * Copyright 2008 Openmoko, Inc.
36475 + * Copyright 2008 Simtec Electronics
36476 + *     Ben Dooks <ben@simtec.co.uk>
36477 + *     http://armlinux.simtec.co.uk/
36478 + *
36479 + * S3C64XX system register definitions
36480 + *
36481 + * This program is free software; you can redistribute it and/or modify
36482 + * it under the terms of the GNU General Public License version 2 as
36483 + * published by the Free Software Foundation.
36484 +*/
36485 +
36486 +#ifndef __PLAT_REGS_SYS_H
36487 +#define __PLAT_REGS_SYS_H __FILE__
36488 +
36489 +#define S3C_SYSREG(x)          (S3C_VA_SYS + (x))
36490 +
36491 +#define S3C64XX_AHB_CON0       S3C_SYSREG(0x100)
36492 +#define S3C64XX_AHB_CON1       S3C_SYSREG(0x104)
36493 +#define S3C64XX_AHB_CON2       S3C_SYSREG(0x108)
36494 +
36495 +#define S3C64XX_OTHERS         S3C_SYSREG(0x900)
36496 +
36497 +#define S3C64XX_OTHERS_USBMASK (1 << 16)
36498 +
36499 +#endif /* _PLAT_REGS_SYS_H */
36500 --- /dev/null
36501 +++ b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
36502 @@ -0,0 +1,35 @@
36503 +/* arch/arm/plat-s3c64xx/include/plat/s3c6400.h
36504 + *
36505 + * Copyright 2008 Openmoko, Inc.
36506 + * Copyright 2008 Simtec Electronics
36507 + *     Ben Dooks <ben@simtec.co.uk>
36508 + *     http://armlinux.simtec.co.uk/
36509 + *
36510 + * Header file for s3c6400 cpu support
36511 + *
36512 + * This program is free software; you can redistribute it and/or modify
36513 + * it under the terms of the GNU General Public License version 2 as
36514 + * published by the Free Software Foundation.
36515 +*/
36516 +
36517 +/* Common init code for S3C6400 related SoCs */
36518 +
36519 +extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
36520 +extern void s3c6400_register_clocks(void);
36521 +extern void s3c6400_setup_clocks(void);
36522 +
36523 +#ifdef CONFIG_CPU_S3C6400
36524 +
36525 +extern  int s3c6400_init(void);
36526 +extern void s3c6400_map_io(void);
36527 +extern void s3c6400_init_clocks(int xtal);
36528 +
36529 +#define s3c6400_init_uarts s3c6400_common_init_uarts
36530 +
36531 +#else
36532 +#define s3c6400_init_clocks NULL
36533 +#define s3c6400_init_uarts NULL
36534 +#define s3c6400_map_io NULL
36535 +#define s3c6400_init NULL
36536 +#endif
36537 +
36538 --- /dev/null
36539 +++ b/arch/arm/plat-s3c64xx/include/plat/s3c6410.h
36540 @@ -0,0 +1,29 @@
36541 +/* arch/arm/plat-s3c64xx/include/plat/s3c6410.h
36542 + *
36543 + * Copyright 2008 Openmoko,  Inc.
36544 + * Copyright 2008 Simtec Electronics
36545 + *     Ben Dooks <ben@simtec.co.uk>
36546 + *     http://armlinux.simtec.co.uk/
36547 + *
36548 + * Header file for s3c6410 cpu support
36549 + *
36550 + * This program is free software; you can redistribute it and/or modify
36551 + * it under the terms of the GNU General Public License version 2 as
36552 + * published by the Free Software Foundation.
36553 +*/
36554 +
36555 +#ifdef CONFIG_CPU_S3C6410
36556 +
36557 +extern  int s3c6410_init(void);
36558 +extern void s3c6410_init_irq(void);
36559 +extern void s3c6410_map_io(void);
36560 +extern void s3c6410_init_clocks(int xtal);
36561 +
36562 +#define s3c6410_init_uarts s3c6400_common_init_uarts
36563 +
36564 +#else
36565 +#define s3c6410_init_clocks NULL
36566 +#define s3c6410_init_uarts NULL
36567 +#define s3c6410_map_io NULL
36568 +#define s3c6410_init NULL
36569 +#endif
36570 --- /dev/null
36571 +++ b/arch/arm/plat-s3c64xx/irq.c
36572 @@ -0,0 +1,256 @@
36573 +/* arch/arm/plat-s3c64xx/irq.c
36574 + *
36575 + * Copyright 2008 Openmoko, Inc.
36576 + * Copyright 2008 Simtec Electronics
36577 + *      Ben Dooks <ben@simtec.co.uk>
36578 + *      http://armlinux.simtec.co.uk/
36579 + *
36580 + * S3C64XX - Interrupt handling
36581 + *
36582 + * This program is free software; you can redistribute it and/or modify
36583 + * it under the terms of the GNU General Public License version 2 as
36584 + * published by the Free Software Foundation.
36585 + */
36586 +
36587 +#include <linux/kernel.h>
36588 +#include <linux/interrupt.h>
36589 +#include <linux/serial_core.h>
36590 +#include <linux/irq.h>
36591 +#include <linux/io.h>
36592 +
36593 +#include <asm/hardware/vic.h>
36594 +
36595 +#include <mach/map.h>
36596 +#include <plat/regs-serial.h>
36597 +#include <plat/regs-timer.h>
36598 +#include <plat/cpu.h>
36599 +
36600 +/* Timer interrupt handling */
36601 +
36602 +static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
36603 +{
36604 +       generic_handle_irq(sub_irq);
36605 +}
36606 +
36607 +static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
36608 +{
36609 +       s3c_irq_demux_timer(irq, IRQ_TIMER0);
36610 +}
36611 +
36612 +static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
36613 +{
36614 +       s3c_irq_demux_timer(irq, IRQ_TIMER1);
36615 +}
36616 +
36617 +static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
36618 +{
36619 +       s3c_irq_demux_timer(irq, IRQ_TIMER2);
36620 +}
36621 +
36622 +static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
36623 +{
36624 +       s3c_irq_demux_timer(irq, IRQ_TIMER3);
36625 +}
36626 +
36627 +static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
36628 +{
36629 +       s3c_irq_demux_timer(irq, IRQ_TIMER4);
36630 +}
36631 +
36632 +/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
36633 +
36634 +static void s3c_irq_timer_mask(unsigned int irq)
36635 +{
36636 +       u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
36637 +
36638 +       reg &= 0x1f;  /* mask out pending interrupts */
36639 +       reg &= ~(1 << (irq - IRQ_TIMER0));
36640 +       __raw_writel(reg, S3C64XX_TINT_CSTAT);
36641 +}
36642 +
36643 +static void s3c_irq_timer_unmask(unsigned int irq)
36644 +{
36645 +       u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
36646 +
36647 +       reg &= 0x1f;  /* mask out pending interrupts */
36648 +       reg |= 1 << (irq - IRQ_TIMER0);
36649 +       __raw_writel(reg, S3C64XX_TINT_CSTAT);
36650 +}
36651 +
36652 +static void s3c_irq_timer_ack(unsigned int irq)
36653 +{
36654 +       u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
36655 +
36656 +       reg &= 0x1f;
36657 +       reg |= (1 << 5) << (irq - IRQ_TIMER0);
36658 +       __raw_writel(reg, S3C64XX_TINT_CSTAT);
36659 +}
36660 +
36661 +static struct irq_chip s3c_irq_timer = {
36662 +       .name           = "s3c-timer",
36663 +       .mask           = s3c_irq_timer_mask,
36664 +       .unmask         = s3c_irq_timer_unmask,
36665 +       .ack            = s3c_irq_timer_ack,
36666 +};
36667 +
36668 +struct uart_irq {
36669 +       void __iomem    *regs;
36670 +       unsigned int     base_irq;
36671 +       unsigned int     parent_irq;
36672 +};
36673 +
36674 +/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
36675 + * are consecutive when looking up the interrupt in the demux routines.
36676 + */
36677 +static struct uart_irq uart_irqs[] = {
36678 +       [0] = {
36679 +               .regs           = S3C_VA_UART0,
36680 +               .base_irq       = IRQ_S3CUART_BASE0,
36681 +               .parent_irq     = IRQ_UART0,
36682 +       },
36683 +       [1] = {
36684 +               .regs           = S3C_VA_UART1,
36685 +               .base_irq       = IRQ_S3CUART_BASE1,
36686 +               .parent_irq     = IRQ_UART1,
36687 +       },
36688 +       [2] = {
36689 +               .regs           = S3C_VA_UART2,
36690 +               .base_irq       = IRQ_S3CUART_BASE2,
36691 +               .parent_irq     = IRQ_UART2,
36692 +       },
36693 +       [3] = {
36694 +               .regs           = S3C_VA_UART3,
36695 +               .base_irq       = IRQ_S3CUART_BASE3,
36696 +               .parent_irq     = IRQ_UART3,
36697 +       },
36698 +};
36699 +
36700 +static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
36701 +{
36702 +       struct uart_irq *uirq = get_irq_chip_data(irq);
36703 +       return uirq->regs;
36704 +}
36705 +
36706 +static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
36707 +{
36708 +       return irq & 3;
36709 +}
36710 +
36711 +/* UART interrupt registers, not worth adding to seperate include header */
36712 +
36713 +static void s3c_irq_uart_mask(unsigned int irq)
36714 +{
36715 +       void __iomem *regs = s3c_irq_uart_base(irq);
36716 +       unsigned int bit = s3c_irq_uart_bit(irq);
36717 +       u32 reg;
36718 +
36719 +       reg = __raw_readl(regs + S3C64XX_UINTM);
36720 +       reg |= (1 << bit);
36721 +       __raw_writel(reg, regs + S3C64XX_UINTM);
36722 +}
36723 +
36724 +static void s3c_irq_uart_maskack(unsigned int irq)
36725 +{
36726 +       void __iomem *regs = s3c_irq_uart_base(irq);
36727 +       unsigned int bit = s3c_irq_uart_bit(irq);
36728 +       u32 reg;
36729 +
36730 +       reg = __raw_readl(regs + S3C64XX_UINTM);
36731 +       reg |= (1 << bit);
36732 +       __raw_writel(reg, regs + S3C64XX_UINTM);
36733 +       __raw_writel(1 << bit, regs + S3C64XX_UINTP);
36734 +}
36735 +
36736 +static void s3c_irq_uart_unmask(unsigned int irq)
36737 +{
36738 +       void __iomem *regs = s3c_irq_uart_base(irq);
36739 +       unsigned int bit = s3c_irq_uart_bit(irq);
36740 +       u32 reg;
36741 +
36742 +       reg = __raw_readl(regs + S3C64XX_UINTM);
36743 +       reg &= ~(1 << bit);
36744 +       __raw_writel(reg, regs + S3C64XX_UINTM);
36745 +}
36746 +
36747 +static void s3c_irq_uart_ack(unsigned int irq)
36748 +{
36749 +       void __iomem *regs = s3c_irq_uart_base(irq);
36750 +       unsigned int bit = s3c_irq_uart_bit(irq);
36751 +
36752 +       __raw_writel(1 << bit, regs + S3C64XX_UINTP);
36753 +}
36754 +
36755 +static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
36756 +{
36757 +       struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
36758 +       u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
36759 +       int base = uirq->base_irq;
36760 +
36761 +       if (pend & (1 << 0))
36762 +               generic_handle_irq(base);
36763 +       if (pend & (1 << 1))
36764 +               generic_handle_irq(base + 1);
36765 +       if (pend & (1 << 2))
36766 +               generic_handle_irq(base + 2);
36767 +       if (pend & (1 << 3))
36768 +               generic_handle_irq(base + 3);
36769 +}
36770 +
36771 +static struct irq_chip s3c_irq_uart = {
36772 +       .name           = "s3c-uart",
36773 +       .mask           = s3c_irq_uart_mask,
36774 +       .unmask         = s3c_irq_uart_unmask,
36775 +       .mask_ack       = s3c_irq_uart_maskack,
36776 +       .ack            = s3c_irq_uart_ack,
36777 +};
36778 +
36779 +static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
36780 +{
36781 +       void *reg_base = uirq->regs;
36782 +       unsigned int irq;
36783 +       int offs;
36784 +
36785 +       /* mask all interrupts at the start. */
36786 +       __raw_writel(0xf, reg_base + S3C64XX_UINTM);
36787 +
36788 +       for (offs = 0; offs < 3; offs++) {
36789 +               irq = uirq->base_irq + offs;
36790 +
36791 +               set_irq_chip(irq, &s3c_irq_uart);
36792 +               set_irq_chip_data(irq, uirq);
36793 +               set_irq_handler(irq, handle_level_irq);
36794 +               set_irq_flags(irq, IRQF_VALID);
36795 +       }
36796 +
36797 +       set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
36798 +}
36799 +
36800 +void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
36801 +{
36802 +       int uart, irq;
36803 +
36804 +       printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
36805 +
36806 +       /* initialise the pair of VICs */
36807 +       vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid);
36808 +       vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid);
36809 +
36810 +       /* add the timer sub-irqs */
36811 +
36812 +       set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0);
36813 +       set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1);
36814 +       set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2);
36815 +       set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3);
36816 +       set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4);
36817 +
36818 +       for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
36819 +               set_irq_chip(irq, &s3c_irq_timer);
36820 +               set_irq_handler(irq, handle_level_irq);
36821 +               set_irq_flags(irq, IRQF_VALID);
36822 +       }
36823 +
36824 +       for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
36825 +               s3c64xx_uart_irq(&uart_irqs[uart]);
36826 +}
36827 +
36828 +
36829 --- /dev/null
36830 +++ b/arch/arm/plat-s3c64xx/irq-eint.c
36831 @@ -0,0 +1,204 @@
36832 +/* arch/arm/plat-s3c64xx/irq-eint.c
36833 + *
36834 + * Copyright 2008 Openmoko, Inc.
36835 + * Copyright 2008 Simtec Electronics
36836 + *      Ben Dooks <ben@simtec.co.uk>
36837 + *      http://armlinux.simtec.co.uk/
36838 + *
36839 + * S3C64XX - Interrupt handling for IRQ_EINT(x)
36840 + *
36841 + * This program is free software; you can redistribute it and/or modify
36842 + * it under the terms of the GNU General Public License version 2 as
36843 + * published by the Free Software Foundation.
36844 + */
36845 +
36846 +#include <linux/kernel.h>
36847 +#include <linux/interrupt.h>
36848 +#include <linux/gpio.h>
36849 +#include <linux/irq.h>
36850 +#include <linux/io.h>
36851 +#include <linux/gpio.h>
36852 +
36853 +#include <asm/hardware/vic.h>
36854 +
36855 +#include <plat/regs-irqtype.h>
36856 +#include <plat/regs-gpio.h>
36857 +#include <plat/gpio-cfg.h>
36858 +
36859 +#include <mach/map.h>
36860 +#include <plat/cpu.h>
36861 +#include <plat/pm.h>
36862 +
36863 +#define eint_offset(irq)       ((irq) - IRQ_EINT(0))
36864 +#define eint_irq_to_bit(irq)   (1 << eint_offset(irq))
36865 +
36866 +static inline void s3c_irq_eint_mask(unsigned int irq)
36867 +{
36868 +       u32 mask;
36869 +
36870 +       mask = __raw_readl(S3C64XX_EINT0MASK);
36871 +       mask |= eint_irq_to_bit(irq);
36872 +       __raw_writel(mask, S3C64XX_EINT0MASK);
36873 +}
36874 +
36875 +static void s3c_irq_eint_unmask(unsigned int irq)
36876 +{
36877 +       u32 mask;
36878 +
36879 +       mask = __raw_readl(S3C64XX_EINT0MASK);
36880 +       mask &= ~eint_irq_to_bit(irq);
36881 +       __raw_writel(mask, S3C64XX_EINT0MASK);
36882 +}
36883 +
36884 +static inline void s3c_irq_eint_ack(unsigned int irq)
36885 +{
36886 +       __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
36887 +}
36888 +
36889 +static void s3c_irq_eint_maskack(unsigned int irq)
36890 +{
36891 +       /* compiler should in-line these */
36892 +       s3c_irq_eint_mask(irq);
36893 +       s3c_irq_eint_ack(irq);
36894 +}
36895 +
36896 +static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
36897 +{
36898 +       int offs = eint_offset(irq);
36899 +       int pin;
36900 +       int shift;
36901 +       u32 ctrl, mask;
36902 +       u32 newvalue = 0;
36903 +       void __iomem *reg;
36904 +
36905 +       if (offs > 27)
36906 +               return -EINVAL;
36907 +
36908 +       if (offs <= 15)
36909 +               reg = S3C64XX_EINT0CON0;
36910 +       else
36911 +               reg = S3C64XX_EINT0CON1;
36912 +
36913 +       switch (type) {
36914 +       case IRQ_TYPE_NONE:
36915 +               printk(KERN_WARNING "No edge setting!\n");
36916 +               break;
36917 +
36918 +       case IRQ_TYPE_EDGE_RISING:
36919 +               newvalue = S3C2410_EXTINT_RISEEDGE;
36920 +               break;
36921 +
36922 +       case IRQ_TYPE_EDGE_FALLING:
36923 +               newvalue = S3C2410_EXTINT_FALLEDGE;
36924 +               break;
36925 +
36926 +       case IRQ_TYPE_EDGE_BOTH:
36927 +               newvalue = S3C2410_EXTINT_BOTHEDGE;
36928 +               break;
36929 +
36930 +       case IRQ_TYPE_LEVEL_LOW:
36931 +               newvalue = S3C2410_EXTINT_LOWLEV;
36932 +               break;
36933 +
36934 +       case IRQ_TYPE_LEVEL_HIGH:
36935 +               newvalue = S3C2410_EXTINT_HILEV;
36936 +               break;
36937 +
36938 +       default:
36939 +               printk(KERN_ERR "No such irq type %d", type);
36940 +               return -1;
36941 +       }
36942 +
36943 +       shift = (offs / 2) * 4;
36944 +       mask = 0x7 << shift;
36945 +
36946 +       ctrl = __raw_readl(reg);
36947 +       ctrl &= ~mask;
36948 +       ctrl |= newvalue << shift;
36949 +       __raw_writel(ctrl, reg);
36950 +
36951 +       /* set the GPIO pin appropriately */
36952 +
36953 +       if (offs < 23)
36954 +               pin = S3C64XX_GPN(offs);
36955 +       else
36956 +               pin = S3C64XX_GPM(offs - 23);
36957 +
36958 +       s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
36959 +
36960 +       return 0;
36961 +}
36962 +
36963 +static struct irq_chip s3c_irq_eint = {
36964 +       .name           = "s3c-eint",
36965 +       .mask           = s3c_irq_eint_mask,
36966 +       .unmask         = s3c_irq_eint_unmask,
36967 +       .mask_ack       = s3c_irq_eint_maskack,
36968 +       .ack            = s3c_irq_eint_ack,
36969 +       .set_type       = s3c_irq_eint_set_type,
36970 +       .set_wake       = s3c_irqext_wake,
36971 +};
36972 +
36973 +/* s3c_irq_demux_eint
36974 + *
36975 + * This function demuxes the IRQ from the group0 external interrupts,
36976 + * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
36977 + * the specific handlers s3c_irq_demux_eintX_Y.
36978 + */
36979 +static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
36980 +{
36981 +       u32 status = __raw_readl(S3C64XX_EINT0PEND);
36982 +       u32 mask = __raw_readl(S3C64XX_EINT0MASK);
36983 +       unsigned int irq;
36984 +
36985 +       status &= ~mask;
36986 +       status >>= start;
36987 +       status &= (1 << (end - start + 1)) - 1;
36988 +
36989 +       for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
36990 +               if (status & 1)
36991 +                       generic_handle_irq(irq);
36992 +
36993 +               status >>= 1;
36994 +       }
36995 +}
36996 +
36997 +static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
36998 +{
36999 +       s3c_irq_demux_eint(0, 3);
37000 +}
37001 +
37002 +static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
37003 +{
37004 +       s3c_irq_demux_eint(4, 11);
37005 +}
37006 +
37007 +static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
37008 +{
37009 +       s3c_irq_demux_eint(12, 19);
37010 +}
37011 +
37012 +static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
37013 +{
37014 +       s3c_irq_demux_eint(20, 27);
37015 +}
37016 +
37017 +int __init s3c64xx_init_irq_eint(void)
37018 +{
37019 +       int irq;
37020 +
37021 +       for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
37022 +               set_irq_chip(irq, &s3c_irq_eint);
37023 +               set_irq_handler(irq, handle_level_irq);
37024 +               set_irq_flags(irq, IRQF_VALID);
37025 +       }
37026 +
37027 +       set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
37028 +       set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
37029 +       set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
37030 +       set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
37031 +
37032 +       return 0;
37033 +}
37034 +
37035 +arch_initcall(s3c64xx_init_irq_eint);
37036 --- /dev/null
37037 +++ b/arch/arm/plat-s3c64xx/irq-pm.c
37038 @@ -0,0 +1,173 @@
37039 +/* arch/arm/plat-s3c64xx/irq-pm.c
37040 + *
37041 + * Copyright 2008 Openmoko, Inc.
37042 + * Copyright 2008 Simtec Electronics
37043 + *      Ben Dooks <ben@simtec.co.uk>
37044 + *      http://armlinux.simtec.co.uk/
37045 + *
37046 + * S3C64XX - Interrupt handling Power Management
37047 + *
37048 + * This program is free software; you can redistribute it and/or modify
37049 + * it under the terms of the GNU General Public License version 2 as
37050 + * published by the Free Software Foundation.
37051 + */
37052 +
37053 +#include <linux/kernel.h>
37054 +#include <linux/sysdev.h>
37055 +#include <linux/interrupt.h>
37056 +#include <linux/serial_core.h>
37057 +#include <linux/irq.h>
37058 +#include <linux/io.h>
37059 +
37060 +#include <asm/hardware/vic.h>
37061 +
37062 +#include <mach/map.h>
37063 +
37064 +#include <plat/regs-serial.h>
37065 +#include <plat/regs-timer.h>
37066 +#include <plat/regs-gpio.h>
37067 +#include <plat/cpu.h>
37068 +#include <plat/pm.h>
37069 +
37070 +/* We handled all the IRQ types in this code, to save having to make several
37071 + * small files to handle each different type separately. Having the EINT_GRP
37072 + * code here shouldn't be as much bloat as the IRQ table space needed when
37073 + * they are enabled. The added benefit is we ensure that these registers are
37074 + * in the same state as we suspended.
37075 + */
37076 +
37077 +static struct sleep_save irq_save[] = {
37078 +       SAVE_ITEM(S3C64XX_PRIORITY),
37079 +       SAVE_ITEM(S3C64XX_EINT0CON0),
37080 +       SAVE_ITEM(S3C64XX_EINT0CON1),
37081 +       SAVE_ITEM(S3C64XX_EINT0FLTCON0),
37082 +       SAVE_ITEM(S3C64XX_EINT0FLTCON1),
37083 +       SAVE_ITEM(S3C64XX_EINT0FLTCON2),
37084 +       SAVE_ITEM(S3C64XX_EINT0FLTCON3),
37085 +       SAVE_ITEM(S3C64XX_EINT0MASK),
37086 +       SAVE_ITEM(S3C64XX_TINT_CSTAT),
37087 +};
37088 +
37089 +static struct irq_grp_save {
37090 +       u32     fltcon;
37091 +       u32     con;
37092 +       u32     mask;
37093 +} eint_grp_save[5];
37094 +
37095 +struct irq_vic_save {
37096 +       u32     int_select;
37097 +       u32     int_enable;
37098 +       u32     soft_int;
37099 +       u32     protect;
37100 +       u32     vect_addr[32];
37101 +       u32     vect_cntl[32];
37102 +};
37103 +
37104 +static struct irq_vic_save irq_pm_vic0_save;
37105 +static struct irq_vic_save irq_pm_vic1_save;
37106 +
37107 +static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
37108 +
37109 +static void s3c64xx_vic_save(void __iomem *base, struct irq_vic_save *save)
37110 +{
37111 +       int v;
37112 +
37113 +       save->int_select = readl(base + VIC_INT_SELECT);
37114 +       save->int_enable = readl(base + VIC_INT_ENABLE);
37115 +       save->soft_int = readl(base + VIC_INT_SOFT);
37116 +       save->protect = readl(base + VIC_PROTECT);
37117 +
37118 +       S3C_PMDBG("%s: select=%08x, enable=%08x, protect=%08x\n", __func__,
37119 +                 save->int_select, save->int_enable, save->protect);
37120 +
37121 +       for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) {
37122 +               save->vect_addr[v] = readl(base + VIC_VECT_ADDR0 + (v * 4));
37123 +               save->vect_cntl[v] = readl(base + VIC_VECT_CNTL0 + (v * 4));
37124 +       }
37125 +}
37126 +
37127 +static void s3c64xx_vic_restore(void __iomem *base, struct irq_vic_save *save)
37128 +{
37129 +       int v;
37130 +
37131 +       writel(save->int_select, base + VIC_INT_SELECT);
37132 +       writel(save->protect, base + VIC_PROTECT);
37133 +
37134 +       /* set the enabled ints and then clear the non-enabled */
37135 +       writel(save->int_enable, base + VIC_INT_ENABLE);
37136 +       writel(~save->int_enable, base + VIC_INT_ENABLE_CLEAR);
37137 +
37138 +       /* and the same for the soft-int register */
37139 +
37140 +       writel(save->soft_int, base + VIC_INT_SOFT);
37141 +       writel(~save->soft_int, base + VIC_INT_SOFT_CLEAR);
37142 +
37143 +       S3C_PMDBG("%s: vic int_enable=%08x\n", __func__, readl(base + VIC_INT_ENABLE));
37144 +
37145 +       for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) {
37146 +               writel(save->vect_addr[v], base + VIC_VECT_ADDR0 + (v * 4));
37147 +               writel(save->vect_cntl[v], base + VIC_VECT_CNTL0 + (v * 4));
37148 +       }
37149 +}
37150 +
37151 +static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state)
37152 +{
37153 +       struct irq_grp_save *grp = eint_grp_save;
37154 +       int i;
37155 +
37156 +       S3C_PMDBG("%s: suspending IRQs\n", __func__);
37157 +
37158 +       s3c64xx_vic_save(S3C_VA_VIC0, &irq_pm_vic0_save);
37159 +       s3c64xx_vic_save(S3C_VA_VIC1, &irq_pm_vic1_save);
37160 +
37161 +       s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
37162 +
37163 +       for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
37164 +               irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
37165 +
37166 +       for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
37167 +               grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
37168 +               grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
37169 +               grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
37170 +       }
37171 +
37172 +       return 0;
37173 +}
37174 +
37175 +static int s3c64xx_irq_pm_resume(struct sys_device *dev)
37176 +{
37177 +       struct irq_grp_save *grp = eint_grp_save;
37178 +       int i;
37179 +
37180 +       S3C_PMDBG("%s: resuming IRQs\n", __func__);
37181 +
37182 +       s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
37183 +
37184 +       s3c64xx_vic_restore(S3C_VA_VIC0, &irq_pm_vic0_save);
37185 +       s3c64xx_vic_restore(S3C_VA_VIC1, &irq_pm_vic1_save);
37186 +
37187 +       for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
37188 +               __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
37189 +
37190 +       for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
37191 +               __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
37192 +               __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
37193 +               __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
37194 +       }
37195 +
37196 +       S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
37197 +       return 0;
37198 +}
37199 +
37200 +static struct sysdev_driver s3c64xx_irq_driver = {
37201 +       .suspend = s3c64xx_irq_pm_suspend,
37202 +       .resume  = s3c64xx_irq_pm_resume,
37203 +};
37204 +
37205 +static int __init s3c64xx_irq_pm_init(void)
37206 +{
37207 +       return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver);
37208 +}
37209 +
37210 +arch_initcall(s3c64xx_irq_pm_init);
37211 +
37212 --- /dev/null
37213 +++ b/arch/arm/plat-s3c64xx/Kconfig
37214 @@ -0,0 +1,61 @@
37215 +# arch/arm/plat-s3c64xx/Kconfig
37216 +#
37217 +# Copyright 2008 Openmoko, Inc.
37218 +# Copyright 2008 Simtec Electronics
37219 +#      Ben Dooks <ben@simtec.co.uk>
37220 +#
37221 +# Licensed under GPLv2
37222 +
37223 +config PLAT_S3C64XX
37224 +       bool
37225 +       depends on ARCH_S3C64XX
37226 +       select PLAT_S3C
37227 +       select ARM_VIC
37228 +       default y
37229 +       select NO_IOPORT
37230 +       select ARCH_REQUIRE_GPIOLIB
37231 +       select S3C_GPIO_TRACK
37232 +       select S3C_GPIO_PULL_UPDOWN
37233 +       select S3C_GPIO_CFG_S3C24XX
37234 +       select S3C_GPIO_CFG_S3C64XX
37235 +       help
37236 +         Base platform code for any Samsung S3C64XX device
37237 +
37238 +if PLAT_S3C64XX
37239 +
37240 +# Configuration options shared by all S3C64XX implementations
37241 +
37242 +config CPU_S3C6400_INIT
37243 +       bool
37244 +       help
37245 +         Common initialisation code for the S3C6400 that is shared
37246 +         by other CPUs in the series, such as the S3C6410.
37247 +
37248 +config CPU_S3C6400_CLOCK
37249 +       bool
37250 +       help
37251 +         Common clock support code for the S3C6400 that is shared
37252 +         by other CPUs in the series, such as the S3C6410.
37253 +
37254 +# platform specific device setup
37255 +
37256 +config S3C64XX_SETUP_I2C0
37257 +       bool
37258 +       default y
37259 +       help
37260 +         Common setup code for i2c bus 0.
37261 +
37262 +         Note, currently since i2c0 is always compiled, this setup helper
37263 +         is always compiled with it.
37264 +
37265 +config S3C64XX_SETUP_I2C1
37266 +       bool
37267 +       help
37268 +         Common setup code for i2c bus 1.
37269 +
37270 +config S3C64XX_SETUP_FB_24BPP
37271 +       bool
37272 +       help
37273 +         Common setup code for S3C64XX with an 24bpp RGB display helper.
37274 +
37275 +endif
37276 --- /dev/null
37277 +++ b/arch/arm/plat-s3c64xx/Makefile
37278 @@ -0,0 +1,37 @@
37279 +# arch/arm/plat-s3c64xx/Makefile
37280 +#
37281 +# Copyright 2008 Openmoko, Inc.
37282 +# Copyright 2008 Simtec Electronics
37283 +#
37284 +# Licensed under GPLv2
37285 +
37286 +obj-y                          :=
37287 +obj-m                          :=
37288 +obj-n                          := dummy.o
37289 +obj-                           :=
37290 +
37291 +# Core files
37292 +
37293 +obj-y                          += dev-uart.o
37294 +obj-y                          += cpu.o
37295 +obj-y                          += irq.o
37296 +obj-y                          += irq-eint.o
37297 +obj-y                          += clock.o
37298 +obj-y                          += gpiolib.o
37299 +
37300 +# CPU support
37301 +
37302 +obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
37303 +obj-$(CONFIG_CPU_S3C6400_CLOCK)        += s3c6400-clock.o
37304 +
37305 +# PM support
37306 +
37307 +obj-$(CONFIG_PM)               += pm.o
37308 +obj-$(CONFIG_PM)               += sleep.o
37309 +obj-$(CONFIG_PM)               += irq-pm.o
37310 +
37311 +# Device setup
37312 +
37313 +obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
37314 +obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
37315 +obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
37316 --- /dev/null
37317 +++ b/arch/arm/plat-s3c64xx/pm.c
37318 @@ -0,0 +1,177 @@
37319 +/* linux/arch/arm/plat-s3c64xx/pm.c
37320 + *
37321 + * Copyright 2008 Openmoko, Inc.
37322 + * Copyright 2008 Simtec Electronics
37323 + *     Ben Dooks <ben@simtec.co.uk>
37324 + *     http://armlinux.simtec.co.uk/
37325 + *
37326 + * S3C64XX CPU PM support.
37327 + *
37328 + * This program is free software; you can redistribute it and/or modify
37329 + * it under the terms of the GNU General Public License version 2 as
37330 + * published by the Free Software Foundation.
37331 +*/
37332 +
37333 +#include <linux/init.h>
37334 +#include <linux/suspend.h>
37335 +#include <linux/serial_core.h>
37336 +#include <linux/io.h>
37337 +
37338 +#include <mach/map.h>
37339 +
37340 +#include <plat/pm.h>
37341 +#include <plat/regs-sys.h>
37342 +#include <plat/regs-gpio.h>
37343 +#include <plat/regs-clock.h>
37344 +#include <plat/regs-modem.h>
37345 +#include <plat/regs-syscon-power.h>
37346 +#include <plat/regs-gpio-memport.h>
37347 +
37348 +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
37349 +#include <plat/gpio-bank-n.h>
37350 +
37351 +void s3c_pm_debug_smdkled(u32 set, u32 clear)
37352 +{
37353 +       unsigned long flags;
37354 +       u32 reg;
37355 +
37356 +       local_irq_save(flags);
37357 +       reg = __raw_readl(S3C64XX_GPNCON);
37358 +       reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) |
37359 +                S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15));
37360 +       reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) |
37361 +              S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15);
37362 +       __raw_writel(reg, S3C64XX_GPNCON);
37363 +
37364 +       reg = __raw_readl(S3C64XX_GPNDAT);
37365 +       reg &= ~(clear << 12);
37366 +       reg |= set << 12;
37367 +       __raw_writel(reg, S3C64XX_GPNDAT);
37368 +
37369 +       local_irq_restore(flags);
37370 +}
37371 +#endif
37372 +
37373 +static struct sleep_save core_save[] = {
37374 +       SAVE_ITEM(S3C_APLL_LOCK),
37375 +       SAVE_ITEM(S3C_MPLL_LOCK),
37376 +       SAVE_ITEM(S3C_EPLL_LOCK),
37377 +       SAVE_ITEM(S3C_CLK_SRC),
37378 +       SAVE_ITEM(S3C_CLK_DIV0),
37379 +       SAVE_ITEM(S3C_CLK_DIV1),
37380 +       SAVE_ITEM(S3C_CLK_DIV2),
37381 +       SAVE_ITEM(S3C_CLK_OUT),
37382 +       SAVE_ITEM(S3C_HCLK_GATE),
37383 +       SAVE_ITEM(S3C_PCLK_GATE),
37384 +       SAVE_ITEM(S3C_SCLK_GATE),
37385 +       SAVE_ITEM(S3C_MEM0_GATE),
37386 +
37387 +       SAVE_ITEM(S3C_EPLL_CON1),
37388 +       SAVE_ITEM(S3C_EPLL_CON0),
37389 +
37390 +       SAVE_ITEM(S3C64XX_MEM0DRVCON),
37391 +       SAVE_ITEM(S3C64XX_MEM1DRVCON),
37392 +
37393 +#ifndef CONFIG_CPU_FREQ
37394 +       SAVE_ITEM(S3C_APLL_CON),
37395 +       SAVE_ITEM(S3C_MPLL_CON),
37396 +#endif
37397 +};
37398 +
37399 +static struct sleep_save misc_save[] = {
37400 +       SAVE_ITEM(S3C64XX_AHB_CON0),
37401 +       SAVE_ITEM(S3C64XX_AHB_CON1),
37402 +       SAVE_ITEM(S3C64XX_AHB_CON2),
37403 +
37404 +       SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
37405 +       SAVE_ITEM(S3C64XX_SPCON),
37406 +
37407 +       SAVE_ITEM(S3C64XX_MEM0CONSTOP),
37408 +       SAVE_ITEM(S3C64XX_MEM1CONSTOP),
37409 +       SAVE_ITEM(S3C64XX_MEM0CONSLP0),
37410 +       SAVE_ITEM(S3C64XX_MEM0CONSLP1),
37411 +       SAVE_ITEM(S3C64XX_MEM1CONSLP),
37412 +};
37413 +
37414 +void s3c_pm_configure_extint(void)
37415 +{
37416 +       __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
37417 +}
37418 +
37419 +void s3c_pm_restore_core(void)
37420 +{
37421 +       __raw_writel(0, S3C64XX_EINT_MASK);
37422 +
37423 +       s3c_pm_debug_smdkled(1 << 2, 0);
37424 +
37425 +       s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
37426 +       s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
37427 +}
37428 +
37429 +void s3c_pm_save_core(void)
37430 +{
37431 +       s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
37432 +       s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
37433 +}
37434 +
37435 +/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
37436 + * put the per-cpu code in here until any new cpu comes along and changes
37437 + * this.
37438 + */
37439 +
37440 +#include <plat/regs-gpio.h>
37441 +
37442 +static void s3c64xx_cpu_suspend(void)
37443 +{
37444 +       unsigned long tmp;
37445 +
37446 +       /* set our standby method to sleep */
37447 +
37448 +       tmp = __raw_readl(S3C64XX_PWR_CFG);
37449 +       tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
37450 +       tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
37451 +       __raw_writel(tmp, S3C64XX_PWR_CFG);
37452 +
37453 +       /* clear any old wakeup */
37454 +
37455 +       __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
37456 +                    S3C64XX_WAKEUP_STAT);
37457 +
37458 +       /* set the LED state to 0110 over sleep */
37459 +       s3c_pm_debug_smdkled(3 << 1, 0xf);
37460 +
37461 +       /* issue the standby signal into the pm unit. Note, we
37462 +        * issue a write-buffer drain just in case */
37463 +
37464 +       tmp = 0;
37465 +
37466 +       asm("b 1f\n\t"
37467 +           ".align 5\n\t"
37468 +           "1:\n\t"
37469 +           "mcr p15, 0, %0, c7, c10, 5\n\t"
37470 +           "mcr p15, 0, %0, c7, c10, 4\n\t"
37471 +           "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
37472 +
37473 +       /* we should never get past here */
37474 +
37475 +       panic("sleep resumed to originator?");
37476 +}
37477 +
37478 +static void s3c64xx_pm_prepare(void)
37479 +{
37480 +       /* store address of resume. */
37481 +       __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
37482 +
37483 +       /* ensure previous wakeup state is cleared before sleeping */
37484 +       __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
37485 +}
37486 +
37487 +static int s3c64xx_pm_init(void)
37488 +{
37489 +       pm_cpu_prep = s3c64xx_pm_prepare;
37490 +       pm_cpu_sleep = s3c64xx_cpu_suspend;
37491 +       pm_uart_udivslot = 1;
37492 +       return 0;
37493 +}
37494 +
37495 +arch_initcall(s3c64xx_pm_init);
37496 --- /dev/null
37497 +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
37498 @@ -0,0 +1,654 @@
37499 +/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
37500 + *
37501 + * Copyright 2008 Openmoko, Inc.
37502 + * Copyright 2008 Simtec Electronics
37503 + *     Ben Dooks <ben@simtec.co.uk>
37504 + *     http://armlinux.simtec.co.uk/
37505 + *
37506 + * S3C6400 based common clock support
37507 + *
37508 + * This program is free software; you can redistribute it and/or modify
37509 + * it under the terms of the GNU General Public License version 2 as
37510 + * published by the Free Software Foundation.
37511 +*/
37512 +
37513 +#include <linux/init.h>
37514 +#include <linux/module.h>
37515 +#include <linux/kernel.h>
37516 +#include <linux/list.h>
37517 +#include <linux/errno.h>
37518 +#include <linux/err.h>
37519 +#include <linux/clk.h>
37520 +#include <linux/sysdev.h>
37521 +#include <linux/io.h>
37522 +
37523 +#include <mach/hardware.h>
37524 +#include <mach/map.h>
37525 +
37526 +#include <plat/cpu-freq.h>
37527 +
37528 +#include <plat/regs-clock.h>
37529 +#include <plat/clock.h>
37530 +#include <plat/cpu.h>
37531 +#include <plat/pll.h>
37532 +
37533 +/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37534 + * ext_xtal_mux for want of an actual name from the manual.
37535 +*/
37536 +
37537 +struct clk clk_ext_xtal_mux = {
37538 +       .name           = "ext_xtal",
37539 +       .id             = -1,
37540 +};
37541 +
37542 +#define clk_fin_apll clk_ext_xtal_mux
37543 +#define clk_fin_mpll clk_ext_xtal_mux
37544 +#define clk_fin_epll clk_ext_xtal_mux
37545 +
37546 +#define clk_fout_mpll  clk_mpll
37547 +
37548 +struct clk_sources {
37549 +       unsigned int    nr_sources;
37550 +       struct clk      **sources;
37551 +};
37552 +
37553 +struct clksrc_clk {
37554 +       struct clk              clk;
37555 +       unsigned int            mask;
37556 +       unsigned int            shift;
37557 +
37558 +       struct clk_sources      *sources;
37559 +
37560 +       unsigned int            divider_shift;
37561 +       void __iomem            *reg_divider;
37562 +};
37563 +
37564 +struct clk clk_fout_apll = {
37565 +       .name           = "fout_apll",
37566 +       .id             = -1,
37567 +};
37568 +
37569 +static struct clk *clk_src_apll_list[] = {
37570 +       [0] = &clk_fin_apll,
37571 +       [1] = &clk_fout_apll,
37572 +};
37573 +
37574 +static struct clk_sources clk_src_apll = {
37575 +       .sources        = clk_src_apll_list,
37576 +       .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
37577 +};
37578 +
37579 +struct clksrc_clk clk_mout_apll = {
37580 +       .clk    = {
37581 +               .name           = "mout_apll",
37582 +               .id             = -1,
37583 +       },
37584 +       .shift          = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
37585 +       .mask           = S3C6400_CLKSRC_APLL_MOUT,
37586 +       .sources        = &clk_src_apll,
37587 +};
37588 +
37589 +struct clk clk_fout_epll = {
37590 +       .name           = "fout_epll",
37591 +       .id             = -1,
37592 +};
37593 +
37594 +static struct clk *clk_src_epll_list[] = {
37595 +       [0] = &clk_fin_epll,
37596 +       [1] = &clk_fout_epll,
37597 +};
37598 +
37599 +static struct clk_sources clk_src_epll = {
37600 +       .sources        = clk_src_epll_list,
37601 +       .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
37602 +};
37603 +
37604 +struct clksrc_clk clk_mout_epll = {
37605 +       .clk    = {
37606 +               .name           = "mout_epll",
37607 +               .id             = -1,
37608 +       },
37609 +       .shift          = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
37610 +       .mask           = S3C6400_CLKSRC_EPLL_MOUT,
37611 +       .sources        = &clk_src_epll,
37612 +};
37613 +
37614 +static struct clk *clk_src_mpll_list[] = {
37615 +       [0] = &clk_fin_mpll,
37616 +       [1] = &clk_fout_mpll,
37617 +};
37618 +
37619 +static struct clk_sources clk_src_mpll = {
37620 +       .sources        = clk_src_mpll_list,
37621 +       .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
37622 +};
37623 +
37624 +struct clksrc_clk clk_mout_mpll = {
37625 +       .clk = {
37626 +               .name           = "mout_mpll",
37627 +               .id             = -1,
37628 +       },
37629 +       .shift          = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
37630 +       .mask           = S3C6400_CLKSRC_MPLL_MOUT,
37631 +       .sources        = &clk_src_mpll,
37632 +};
37633 +
37634 +static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
37635 +{
37636 +       unsigned long rate = clk_get_rate(clk->parent);
37637 +
37638 +       printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
37639 +
37640 +       if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
37641 +               rate /= 2;
37642 +
37643 +       return rate;
37644 +}
37645 +
37646 +struct clk clk_dout_mpll = {
37647 +       .name           = "dout_mpll",
37648 +       .id             = -1,
37649 +       .parent         = &clk_mout_mpll.clk,
37650 +       .get_rate       = s3c64xx_clk_doutmpll_get_rate,
37651 +};
37652 +
37653 +static struct clk *clkset_spi_mmc_list[] = {
37654 +       &clk_mout_epll.clk,
37655 +       &clk_dout_mpll,
37656 +       &clk_fin_epll,
37657 +       &clk_27m,
37658 +};
37659 +
37660 +static struct clk_sources clkset_spi_mmc = {
37661 +       .sources        = clkset_spi_mmc_list,
37662 +       .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
37663 +};
37664 +
37665 +static struct clk *clkset_irda_list[] = {
37666 +       &clk_mout_epll.clk,
37667 +       &clk_dout_mpll,
37668 +       NULL,
37669 +       &clk_27m,
37670 +};
37671 +
37672 +static struct clk_sources clkset_irda = {
37673 +       .sources        = clkset_irda_list,
37674 +       .nr_sources     = ARRAY_SIZE(clkset_irda_list),
37675 +};
37676 +
37677 +static struct clk *clkset_uart_list[] = {
37678 +       &clk_mout_epll.clk,
37679 +       &clk_dout_mpll,
37680 +       NULL,
37681 +       NULL
37682 +};
37683 +
37684 +static struct clk_sources clkset_uart = {
37685 +       .sources        = clkset_uart_list,
37686 +       .nr_sources     = ARRAY_SIZE(clkset_uart_list),
37687 +};
37688 +
37689 +static struct clk *clkset_uhost_list[] = {
37690 +       &clk_mout_epll.clk,
37691 +       &clk_dout_mpll,
37692 +       &clk_fin_epll,
37693 +       &clk_48m,
37694 +};
37695 +
37696 +static struct clk_sources clkset_uhost = {
37697 +       .sources        = clkset_uhost_list,
37698 +       .nr_sources     = ARRAY_SIZE(clkset_uhost_list),
37699 +};
37700 +
37701 +
37702 +/* The peripheral clocks are all controlled via clocksource followed
37703 + * by an optional divider and gate stage. We currently roll this into
37704 + * one clock which hides the intermediate clock from the mux.
37705 + *
37706 + * Note, the JPEG clock can only be an even divider...
37707 + *
37708 + * The scaler and LCD clocks depend on the S3C64XX version, and also
37709 + * have a common parent divisor so are not included here.
37710 + */
37711 +
37712 +static inline struct clksrc_clk *to_clksrc(struct clk *clk)
37713 +{
37714 +       return container_of(clk, struct clksrc_clk, clk);
37715 +}
37716 +
37717 +static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
37718 +{
37719 +       struct clksrc_clk *sclk = to_clksrc(clk);
37720 +       unsigned long rate = clk_get_rate(clk->parent);
37721 +       u32 clkdiv = __raw_readl(sclk->reg_divider);
37722 +
37723 +       clkdiv >>= sclk->divider_shift;
37724 +       clkdiv &= 0xf;
37725 +       clkdiv++;
37726 +
37727 +       rate /= clkdiv;
37728 +       return rate;
37729 +}
37730 +
37731 +static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
37732 +{
37733 +       struct clksrc_clk *sclk = to_clksrc(clk);
37734 +       void __iomem *reg = sclk->reg_divider;
37735 +       unsigned int div;
37736 +       u32 val;
37737 +
37738 +       rate = clk_round_rate(clk, rate);
37739 +       div = clk_get_rate(clk->parent) / rate;
37740 +
37741 +       val = __raw_readl(reg);
37742 +       val &= ~sclk->mask;
37743 +       val |= (rate - 1) << sclk->shift;
37744 +       __raw_writel(val, reg);
37745 +
37746 +       return 0;
37747 +}
37748 +
37749 +static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
37750 +{
37751 +       struct clksrc_clk *sclk = to_clksrc(clk);
37752 +       struct clk_sources *srcs = sclk->sources;
37753 +       u32 clksrc = __raw_readl(S3C_CLK_SRC);
37754 +       int src_nr = -1;
37755 +       int ptr;
37756 +
37757 +       for (ptr = 0; ptr < srcs->nr_sources; ptr++)
37758 +               if (srcs->sources[ptr] == parent) {
37759 +                       src_nr = ptr;
37760 +                       break;
37761 +               }
37762 +
37763 +       if (src_nr >= 0) {
37764 +               clksrc &= ~sclk->mask;
37765 +               clksrc |= src_nr << sclk->shift;
37766 +
37767 +               __raw_writel(clksrc, S3C_CLK_SRC);
37768 +               return 0;
37769 +       }
37770 +
37771 +       return -EINVAL;
37772 +}
37773 +
37774 +static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
37775 +                                             unsigned long rate)
37776 +{
37777 +       unsigned long parent_rate = clk_get_rate(clk->parent);
37778 +       int div;
37779 +
37780 +       if (rate > parent_rate)
37781 +               rate = parent_rate;
37782 +       else {
37783 +               div = rate / parent_rate;
37784 +
37785 +               if (div == 0)
37786 +                       div = 1;
37787 +               if (div > 16)
37788 +                       div = 16;
37789 +
37790 +               rate = parent_rate / div;
37791 +       }
37792 +
37793 +       return rate;
37794 +}
37795 +
37796 +static struct clksrc_clk clk_mmc0 = {
37797 +       .clk    = {
37798 +               .name           = "mmc_bus",
37799 +               .id             = 0,
37800 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
37801 +               .enable         = s3c64xx_sclk_ctrl,
37802 +               .set_parent     = s3c64xx_setparent_clksrc,
37803 +               .get_rate       = s3c64xx_getrate_clksrc,
37804 +               .set_rate       = s3c64xx_setrate_clksrc,
37805 +               .round_rate     = s3c64xx_roundrate_clksrc,
37806 +       },
37807 +       .shift          = S3C6400_CLKSRC_MMC0_SHIFT,
37808 +       .mask           = S3C6400_CLKSRC_MMC0_MASK,
37809 +       .sources        = &clkset_spi_mmc,
37810 +       .divider_shift  = S3C6400_CLKDIV1_MMC0_SHIFT,
37811 +       .reg_divider    = S3C_CLK_DIV1,
37812 +};
37813 +
37814 +static struct clksrc_clk clk_mmc1 = {
37815 +       .clk    = {
37816 +               .name           = "mmc_bus",
37817 +               .id             = 1,
37818 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
37819 +               .enable         = s3c64xx_sclk_ctrl,
37820 +               .get_rate       = s3c64xx_getrate_clksrc,
37821 +               .set_rate       = s3c64xx_setrate_clksrc,
37822 +               .set_parent     = s3c64xx_setparent_clksrc,
37823 +               .round_rate     = s3c64xx_roundrate_clksrc,
37824 +       },
37825 +       .shift          = S3C6400_CLKSRC_MMC1_SHIFT,
37826 +       .mask           = S3C6400_CLKSRC_MMC1_MASK,
37827 +       .sources        = &clkset_spi_mmc,
37828 +       .divider_shift  = S3C6400_CLKDIV1_MMC1_SHIFT,
37829 +       .reg_divider    = S3C_CLK_DIV1,
37830 +};
37831 +
37832 +static struct clksrc_clk clk_mmc2 = {
37833 +       .clk    = {
37834 +               .name           = "mmc_bus",
37835 +               .id             = 2,
37836 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
37837 +               .enable         = s3c64xx_sclk_ctrl,
37838 +               .get_rate       = s3c64xx_getrate_clksrc,
37839 +               .set_rate       = s3c64xx_setrate_clksrc,
37840 +               .set_parent     = s3c64xx_setparent_clksrc,
37841 +               .round_rate     = s3c64xx_roundrate_clksrc,
37842 +       },
37843 +       .shift          = S3C6400_CLKSRC_MMC2_SHIFT,
37844 +       .mask           = S3C6400_CLKSRC_MMC2_MASK,
37845 +       .sources        = &clkset_spi_mmc,
37846 +       .divider_shift  = S3C6400_CLKDIV1_MMC2_SHIFT,
37847 +       .reg_divider    = S3C_CLK_DIV1,
37848 +};
37849 +
37850 +static struct clksrc_clk clk_usbhost = {
37851 +       .clk    = {
37852 +               .name           = "usb-host-bus",
37853 +               .id             = -1,
37854 +               .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
37855 +               .enable         = s3c64xx_sclk_ctrl,
37856 +               .set_parent     = s3c64xx_setparent_clksrc,
37857 +               .get_rate       = s3c64xx_getrate_clksrc,
37858 +               .set_rate       = s3c64xx_setrate_clksrc,
37859 +               .round_rate     = s3c64xx_roundrate_clksrc,
37860 +       },
37861 +       .shift          = S3C6400_CLKSRC_UHOST_SHIFT,
37862 +       .mask           = S3C6400_CLKSRC_UHOST_MASK,
37863 +       .sources        = &clkset_uhost,
37864 +       .divider_shift  = S3C6400_CLKDIV1_UHOST_SHIFT,
37865 +       .reg_divider    = S3C_CLK_DIV1,
37866 +};
37867 +
37868 +static struct clksrc_clk clk_uart_uclk1 = {
37869 +       .clk    = {
37870 +               .name           = "uclk1",
37871 +               .id             = -1,
37872 +               .ctrlbit        = S3C_CLKCON_SCLK_UART,
37873 +               .enable         = s3c64xx_sclk_ctrl,
37874 +               .set_parent     = s3c64xx_setparent_clksrc,
37875 +               .get_rate       = s3c64xx_getrate_clksrc,
37876 +               .set_rate       = s3c64xx_setrate_clksrc,
37877 +               .round_rate     = s3c64xx_roundrate_clksrc,
37878 +       },
37879 +       .shift          = S3C6400_CLKSRC_UART_SHIFT,
37880 +       .mask           = S3C6400_CLKSRC_UART_MASK,
37881 +       .sources        = &clkset_uart,
37882 +       .divider_shift  = S3C6400_CLKDIV2_UART_SHIFT,
37883 +       .reg_divider    = S3C_CLK_DIV2,
37884 +};
37885 +
37886 +/* Where does UCLK0 come from? */
37887 +
37888 +static struct clksrc_clk clk_spi0 = {
37889 +       .clk    = {
37890 +               .name           = "spi-bus",
37891 +               .id             = 0,
37892 +               .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
37893 +               .enable         = s3c64xx_sclk_ctrl,
37894 +               .set_parent     = s3c64xx_setparent_clksrc,
37895 +               .get_rate       = s3c64xx_getrate_clksrc,
37896 +               .set_rate       = s3c64xx_setrate_clksrc,
37897 +               .round_rate     = s3c64xx_roundrate_clksrc,
37898 +       },
37899 +       .shift          = S3C6400_CLKSRC_SPI0_SHIFT,
37900 +       .mask           = S3C6400_CLKSRC_SPI0_MASK,
37901 +       .sources        = &clkset_spi_mmc,
37902 +       .divider_shift  = S3C6400_CLKDIV2_SPI0_SHIFT,
37903 +       .reg_divider    = S3C_CLK_DIV2,
37904 +};
37905 +
37906 +static struct clksrc_clk clk_spi1 = {
37907 +       .clk    = {
37908 +               .name           = "spi-bus",
37909 +               .id             = 1,
37910 +               .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
37911 +               .enable         = s3c64xx_sclk_ctrl,
37912 +               .set_parent     = s3c64xx_setparent_clksrc,
37913 +               .get_rate       = s3c64xx_getrate_clksrc,
37914 +               .set_rate       = s3c64xx_setrate_clksrc,
37915 +               .round_rate     = s3c64xx_roundrate_clksrc,
37916 +       },
37917 +       .shift          = S3C6400_CLKSRC_SPI1_SHIFT,
37918 +       .mask           = S3C6400_CLKSRC_SPI1_MASK,
37919 +       .sources        = &clkset_spi_mmc,
37920 +       .divider_shift  = S3C6400_CLKDIV2_SPI1_SHIFT,
37921 +       .reg_divider    = S3C_CLK_DIV2,
37922 +};
37923 +
37924 +static struct clk clk_iis_cd0 = {
37925 +       .name           = "iis_cdclk0",
37926 +       .id             = -1,
37927 +};
37928 +
37929 +static struct clk clk_iis_cd1 = {
37930 +       .name           = "iis_cdclk1",
37931 +       .id             = -1,
37932 +};
37933 +
37934 +static struct clk clk_pcm_cd = {
37935 +       .name           = "pcm_cdclk",
37936 +       .id             = -1,
37937 +};
37938 +
37939 +static struct clk *clkset_audio0_list[] = {
37940 +       [0] = &clk_mout_epll.clk,
37941 +       [1] = &clk_dout_mpll,
37942 +       [2] = &clk_fin_epll,
37943 +       [3] = &clk_iis_cd0,
37944 +       [4] = &clk_pcm_cd,
37945 +};
37946 +
37947 +static struct clk_sources clkset_audio0 = {
37948 +       .sources        = clkset_audio0_list,
37949 +       .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
37950 +};
37951 +
37952 +static struct clksrc_clk clk_audio0 = {
37953 +       .clk    = {
37954 +               .name           = "audio-bus",
37955 +               .id             = 0,
37956 +               .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
37957 +               .enable         = s3c64xx_sclk_ctrl,
37958 +               .set_parent     = s3c64xx_setparent_clksrc,
37959 +               .get_rate       = s3c64xx_getrate_clksrc,
37960 +               .set_rate       = s3c64xx_setrate_clksrc,
37961 +               .round_rate     = s3c64xx_roundrate_clksrc,
37962 +       },
37963 +       .shift          = S3C6400_CLKSRC_AUDIO0_SHIFT,
37964 +       .mask           = S3C6400_CLKSRC_AUDIO0_MASK,
37965 +       .sources        = &clkset_audio0,
37966 +       .divider_shift  = S3C6400_CLKDIV2_AUDIO0_SHIFT,
37967 +       .reg_divider    = S3C_CLK_DIV2,
37968 +};
37969 +
37970 +static struct clk *clkset_audio1_list[] = {
37971 +       [0] = &clk_mout_epll.clk,
37972 +       [1] = &clk_dout_mpll,
37973 +       [2] = &clk_fin_epll,
37974 +       [3] = &clk_iis_cd1,
37975 +       [4] = &clk_pcm_cd,
37976 +};
37977 +
37978 +static struct clk_sources clkset_audio1 = {
37979 +       .sources        = clkset_audio1_list,
37980 +       .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
37981 +};
37982 +
37983 +static struct clksrc_clk clk_audio1 = {
37984 +       .clk    = {
37985 +               .name           = "audio-bus",
37986 +               .id             = 1,
37987 +               .ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,
37988 +               .enable         = s3c64xx_sclk_ctrl,
37989 +               .set_parent     = s3c64xx_setparent_clksrc,
37990 +               .get_rate       = s3c64xx_getrate_clksrc,
37991 +               .set_rate       = s3c64xx_setrate_clksrc,
37992 +               .round_rate     = s3c64xx_roundrate_clksrc,
37993 +       },
37994 +       .shift          = S3C6400_CLKSRC_AUDIO1_SHIFT,
37995 +       .mask           = S3C6400_CLKSRC_AUDIO1_MASK,
37996 +       .sources        = &clkset_audio1,
37997 +       .divider_shift  = S3C6400_CLKDIV2_AUDIO1_SHIFT,
37998 +       .reg_divider    = S3C_CLK_DIV2,
37999 +};
38000 +
38001 +static struct clksrc_clk clk_irda = {
38002 +       .clk    = {
38003 +               .name           = "irda-bus",
38004 +               .id             = 0,
38005 +               .ctrlbit        = S3C_CLKCON_SCLK_IRDA,
38006 +               .enable         = s3c64xx_sclk_ctrl,
38007 +               .set_parent     = s3c64xx_setparent_clksrc,
38008 +               .get_rate       = s3c64xx_getrate_clksrc,
38009 +               .set_rate       = s3c64xx_setrate_clksrc,
38010 +               .round_rate     = s3c64xx_roundrate_clksrc,
38011 +       },
38012 +       .shift          = S3C6400_CLKSRC_IRDA_SHIFT,
38013 +       .mask           = S3C6400_CLKSRC_IRDA_MASK,
38014 +       .sources        = &clkset_irda,
38015 +       .divider_shift  = S3C6400_CLKDIV2_IRDA_SHIFT,
38016 +       .reg_divider    = S3C_CLK_DIV2,
38017 +};
38018 +
38019 +/* Clock initialisation code */
38020 +
38021 +static struct clksrc_clk *init_parents[] = {
38022 +       &clk_mout_apll,
38023 +       &clk_mout_epll,
38024 +       &clk_mout_mpll,
38025 +       &clk_mmc0,
38026 +       &clk_mmc1,
38027 +       &clk_mmc2,
38028 +       &clk_usbhost,
38029 +       &clk_uart_uclk1,
38030 +       &clk_spi0,
38031 +       &clk_spi1,
38032 +       &clk_audio0,
38033 +       &clk_audio1,
38034 +       &clk_irda,
38035 +};
38036 +
38037 +static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
38038 +{
38039 +       struct clk_sources *srcs = clk->sources;
38040 +       u32 clksrc = __raw_readl(S3C_CLK_SRC);
38041 +
38042 +       clksrc &= clk->mask;
38043 +       clksrc >>= clk->shift;
38044 +
38045 +       if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
38046 +               printk(KERN_ERR "%s: bad source %d\n",
38047 +                      clk->clk.name, clksrc);
38048 +               return;
38049 +       }
38050 +
38051 +       clk->clk.parent = srcs->sources[clksrc];
38052 +
38053 +       printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
38054 +              clk->clk.name, clk->clk.parent->name, clksrc,
38055 +              clk_get_rate(&clk->clk));
38056 +}
38057 +
38058 +#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
38059 +
38060 +void __init_or_cpufreq s3c6400_setup_clocks(void)
38061 +{
38062 +       struct clk *xtal_clk;
38063 +       unsigned long xtal;
38064 +       unsigned long fclk;
38065 +       unsigned long hclk;
38066 +       unsigned long hclk2;
38067 +       unsigned long pclk;
38068 +       unsigned long epll;
38069 +       unsigned long apll;
38070 +       unsigned long mpll;
38071 +       unsigned int ptr;
38072 +       u32 clkdiv0;
38073 +
38074 +       printk(KERN_DEBUG "%s: registering clocks\n", __func__);
38075 +
38076 +       clkdiv0 = __raw_readl(S3C_CLK_DIV0);
38077 +       printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
38078 +
38079 +       xtal_clk = clk_get(NULL, "xtal");
38080 +       BUG_ON(IS_ERR(xtal_clk));
38081 +
38082 +       xtal = clk_get_rate(xtal_clk);
38083 +       clk_put(xtal_clk);
38084 +
38085 +       printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
38086 +
38087 +       epll = s3c6400_get_epll(xtal);
38088 +       mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
38089 +       apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
38090 +
38091 +       fclk = mpll;
38092 +
38093 +       printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
38094 +              apll, mpll, epll);
38095 +
38096 +       hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
38097 +       hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
38098 +       pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
38099 +
38100 +       printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
38101 +              hclk2, hclk, pclk);
38102 +
38103 +       clk_fout_mpll.rate = mpll;
38104 +       clk_fout_epll.rate = epll;
38105 +       clk_fout_apll.rate = apll;
38106 +
38107 +       clk_h.rate = hclk;
38108 +       clk_p.rate = pclk;
38109 +       clk_f.rate = fclk;
38110 +
38111 +       for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
38112 +               s3c6400_set_clksrc(init_parents[ptr]);
38113 +}
38114 +
38115 +static struct clk *clks[] __initdata = {
38116 +       &clk_ext_xtal_mux,
38117 +       &clk_iis_cd0,
38118 +       &clk_iis_cd1,
38119 +       &clk_pcm_cd,
38120 +       &clk_mout_epll.clk,
38121 +       &clk_fout_epll,
38122 +       &clk_mout_mpll.clk,
38123 +       &clk_dout_mpll,
38124 +       &clk_mmc0.clk,
38125 +       &clk_mmc1.clk,
38126 +       &clk_mmc2.clk,
38127 +       &clk_usbhost.clk,
38128 +       &clk_uart_uclk1.clk,
38129 +       &clk_spi0.clk,
38130 +       &clk_spi1.clk,
38131 +       &clk_audio0.clk,
38132 +       &clk_audio1.clk,
38133 +       &clk_irda.clk,
38134 +};
38135 +
38136 +void __init s3c6400_register_clocks(void)
38137 +{
38138 +       struct clk *clkp;
38139 +       int ret;
38140 +       int ptr;
38141 +
38142 +       for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
38143 +               clkp = clks[ptr];
38144 +               ret = s3c24xx_register_clock(clkp);
38145 +               if (ret < 0) {
38146 +                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
38147 +                              clkp->name, ret);
38148 +               }
38149 +       }
38150 +
38151 +       clk_epll.parent = &clk_mout_epll.clk;
38152 +}
38153 --- /dev/null
38154 +++ b/arch/arm/plat-s3c64xx/s3c6400-init.c
38155 @@ -0,0 +1,29 @@
38156 +/* linux/arch/arm/plat-s3c64xx/s3c6400-init.c
38157 + *
38158 + * Copyright 2008 Openmoko, Inc.
38159 + * Copyright 2008 Simtec Electronics
38160 + *      Ben Dooks <ben@simtec.co.uk>
38161 + *      http://armlinux.simtec.co.uk/
38162 + *
38163 + * S3C6400 - CPU initialisation (common with other S3C64XX chips)
38164 + *
38165 + * This program is free software; you can redistribute it and/or modify
38166 + * it under the terms of the GNU General Public License version 2 as
38167 + * published by the Free Software Foundation.
38168 + */
38169 +
38170 +#include <linux/kernel.h>
38171 +#include <linux/types.h>
38172 +#include <linux/init.h>
38173 +
38174 +#include <plat/cpu.h>
38175 +#include <plat/devs.h>
38176 +#include <plat/s3c6400.h>
38177 +#include <plat/s3c6410.h>
38178 +
38179 +/* uart registration process */
38180 +
38181 +void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
38182 +{
38183 +       s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
38184 +}
38185 --- /dev/null
38186 +++ b/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
38187 @@ -0,0 +1,37 @@
38188 +/* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
38189 + *
38190 + * Copyright 2008 Openmoko, Inc.
38191 + * Copyright 2008 Simtec Electronics
38192 + *     Ben Dooks <ben@simtec.co.uk>
38193 + *     http://armlinux.simtec.co.uk/
38194 + *
38195 + * Base S3C64XX setup information for 24bpp LCD framebuffer
38196 + *
38197 + * This program is free software; you can redistribute it and/or modify
38198 + * it under the terms of the GNU General Public License version 2 as
38199 + * published by the Free Software Foundation.
38200 +*/
38201 +
38202 +#include <linux/kernel.h>
38203 +#include <linux/types.h>
38204 +#include <linux/fb.h>
38205 +
38206 +#include <mach/regs-fb.h>
38207 +#include <mach/gpio.h>
38208 +#include <plat/fb.h>
38209 +#include <plat/gpio-cfg.h>
38210 +
38211 +extern void s3c64xx_fb_gpio_setup_24bpp(void)
38212 +{
38213 +       unsigned int gpio;
38214 +
38215 +       for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
38216 +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
38217 +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
38218 +       }
38219 +
38220 +       for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
38221 +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
38222 +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
38223 +       }
38224 +}
38225 --- /dev/null
38226 +++ b/arch/arm/plat-s3c64xx/setup-i2c0.c
38227 @@ -0,0 +1,31 @@
38228 +/* linux/arch/arm/plat-s3c64xx/setup-i2c0.c
38229 + *
38230 + * Copyright 2008 Openmoko, Inc.
38231 + * Copyright 2008 Simtec Electronics
38232 + *     Ben Dooks <ben@simtec.co.uk>
38233 + *     http://armlinux.simtec.co.uk/
38234 + *
38235 + * Base S3C64XX I2C bus 0 gpio configuration
38236 + *
38237 + * This program is free software; you can redistribute it and/or modify
38238 + * it under the terms of the GNU General Public License version 2 as
38239 + * published by the Free Software Foundation.
38240 +*/
38241 +
38242 +#include <linux/kernel.h>
38243 +#include <linux/types.h>
38244 +
38245 +struct platform_device; /* don't need the contents */
38246 +
38247 +#include <mach/gpio.h>
38248 +#include <plat/iic.h>
38249 +#include <plat/gpio-bank-b.h>
38250 +#include <plat/gpio-cfg.h>
38251 +
38252 +void s3c_i2c0_cfg_gpio(struct platform_device *dev)
38253 +{
38254 +       s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
38255 +       s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
38256 +       s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP);
38257 +       s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP);
38258 +}
38259 --- /dev/null
38260 +++ b/arch/arm/plat-s3c64xx/setup-i2c1.c
38261 @@ -0,0 +1,31 @@
38262 +/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c
38263 + *
38264 + * Copyright 2008 Openmoko, Inc.
38265 + * Copyright 2008 Simtec Electronics
38266 + *     Ben Dooks <ben@simtec.co.uk>
38267 + *     http://armlinux.simtec.co.uk/
38268 + *
38269 + * Base S3C64XX I2C bus 1 gpio configuration
38270 + *
38271 + * This program is free software; you can redistribute it and/or modify
38272 + * it under the terms of the GNU General Public License version 2 as
38273 + * published by the Free Software Foundation.
38274 +*/
38275 +
38276 +#include <linux/kernel.h>
38277 +#include <linux/types.h>
38278 +
38279 +struct platform_device; /* don't need the contents */
38280 +
38281 +#include <mach/gpio.h>
38282 +#include <plat/iic.h>
38283 +#include <plat/gpio-bank-b.h>
38284 +#include <plat/gpio-cfg.h>
38285 +
38286 +void s3c_i2c1_cfg_gpio(struct platform_device *dev)
38287 +{
38288 +       s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1);
38289 +       s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1);
38290 +       s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP);
38291 +       s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP);
38292 +}
38293 --- /dev/null
38294 +++ b/arch/arm/plat-s3c64xx/sleep.S
38295 @@ -0,0 +1,143 @@
38296 +/* linux/0arch/arm/plat-s3c64xx/sleep.S
38297 + *
38298 + * Copyright 2008 Openmoko, Inc.
38299 + * Copyright 2008 Simtec Electronics
38300 + *     Ben Dooks <ben@simtec.co.uk>
38301 + *     http://armlinux.simtec.co.uk/
38302 + *
38303 + * S3C64XX CPU sleep code
38304 + *
38305 + * This program is free software; you can redistribute it and/or modify
38306 + * it under the terms of the GNU General Public License version 2 as
38307 + * published by the Free Software Foundation.
38308 +*/
38309 +
38310 +#include <linux/linkage.h>
38311 +#include <asm/assembler.h>
38312 +#include <mach/map.h>
38313 +
38314 +#undef S3C64XX_VA_GPIO
38315 +#define S3C64XX_VA_GPIO (0x0)
38316 +
38317 +#include <plat/regs-gpio.h>
38318 +#include <plat/gpio-bank-n.h>
38319 +
38320 +#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
38321 +
38322 +       .text
38323 +
38324 +       /* s3c_cpu_save
38325 +        *
38326 +        * Save enough processor state to allow the restart of the pm.c
38327 +        * code after resume.
38328 +        *
38329 +        * entry:
38330 +        *      r0 = pointer to the save block
38331 +        * exit:
38332 +        *      r0 = exit code: 1 => stored data
38333 +        *                      0 => resumed from sleep
38334 +       */
38335 +
38336 +ENTRY(s3c_cpu_save)
38337 +       stmfd   sp!, { r4 - r12, lr }
38338 +
38339 +       mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
38340 +       mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
38341 +       mrc     p15, 0, r6, c2, c0, 0   @ Translation Table BASE0
38342 +       mrc     p15, 0, r7, c2, c0, 1   @ Translation Table BASE1
38343 +       mrc     p15, 0, r8, c2, c0, 2   @ Translation Table Control
38344 +       mrc     p15, 0, r9, c1, c0, 0   @ Control register
38345 +       mrc     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
38346 +       mrc     p15, 0, r11, c1, c0, 2  @ Co-processor access controls
38347 +
38348 +       stmia   r0, { r4 - r13 }        @ Save CP registers and SP
38349 +       mov     r0, #0
38350 +       ldmfd   sp, { r4 - r12, pc }    @ return, not disturbing SP
38351 +
38352 +       @@ return to the caller, after the MMU is turned on.
38353 +       @@ restore the last bits of the stack and return.
38354 +resume_with_mmu:
38355 +       mov     r0, #1
38356 +       ldmfd   sp!, { r4 - r12, pc }   @ return, from sp from s3c_cpu_save
38357 +
38358 +       .data
38359 +
38360 +       /* the next bit is code, but it requires easy access to the
38361 +        * s3c_sleep_save_phys data before the MMU is switched on, so
38362 +        * we store the code that needs this variable in the .data where
38363 +        * the value can be written to (the .text segment is RO).
38364 +       */
38365 +
38366 +       .global s3c_sleep_save_phys
38367 +s3c_sleep_save_phys:
38368 +       .word   0
38369 +
38370 +       /* Sleep magic, the word before the resume entry point so that the
38371 +        * bootloader can check for a resumeable image. */
38372 +
38373 +       .word   0x2bedf00d
38374 +
38375 +       /* s3c_cpu_reusme
38376 +        *
38377 +        * This is the entry point, stored by whatever method the bootloader
38378 +        * requires to get the kernel runnign again. This code expects to be
38379 +        * entered with no caches live and the MMU disabled. It will then
38380 +        * restore the MMU and other basic CP registers saved and restart
38381 +        * the kernel C code to finish the resume code.
38382 +       */
38383 +
38384 +ENTRY(s3c_cpu_resume)
38385 +       msr     cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
38386 +       ldr     r2, =LL_UART            /* for debug */
38387 +
38388 +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
38389 +       /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
38390 +        * as the uboot version supplied resets these to inputs during the
38391 +        * resume checks.
38392 +       */
38393 +
38394 +       ldr     r3, =S3C64XX_PA_GPIO
38395 +       ldr     r0, [ r3, #S3C64XX_GPNCON ]
38396 +       bic     r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
38397 +                         S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
38398 +       orr     r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
38399 +                         S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
38400 +       str     r0, [ r3, #S3C64XX_GPNCON ]
38401 +
38402 +       ldr     r0, [ r3, #S3C64XX_GPNDAT ]
38403 +       bic     r0, r0, #0xf << 12                      @ GPN12..15
38404 +       orr     r0, r0, #1 << 15                        @ GPN15
38405 +       str     r0, [ r3, #S3C64XX_GPNDAT ]
38406 +#endif
38407 +
38408 +       /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
38409 +        * are thoroughly cleaned just in case the bootloader didn't do it
38410 +        * for us. */
38411 +       mov     r0, #0
38412 +       mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
38413 +       mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
38414 +       mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
38415 +       mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
38416 +       @@mcr   p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
38417 +       @@mcr   p15, 0, r0, c7, c7, 0           @ Invalidate I + D caches
38418 +
38419 +       ldr     r0, s3c_sleep_save_phys
38420 +       ldmia   r0, { r4 - r13 }
38421 +
38422 +       mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
38423 +       mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
38424 +       mcr     p15, 0, r6, c2, c0, 0   @ Translation Table BASE0
38425 +       mcr     p15, 0, r7, c2, c0, 1   @ Translation Table BASE1
38426 +       mcr     p15, 0, r8, c2, c0, 2   @ Translation Table Control
38427 +       mcr     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
38428 +
38429 +       mov     r0, #0                  @ restore copro access controls
38430 +       mcr     p15, 0, r11, c1, c0, 2  @ Co-processor access controls
38431 +       mcr     p15, 0, r0, c7, c5, 4
38432 +
38433 +       ldr     r2, =resume_with_mmu
38434 +       mcr     p15, 0, r9, c1, c0, 0           /* turn mmu back on */
38435 +       nop
38436 +       mov     pc, r2                          /* jump back */
38437 +
38438 +       .end
38439 --- /dev/null
38440 +++ b/dfu-kern
38441 @@ -0,0 +1,14 @@
38442 +#!/bin/bash
38443 +
38444 +if [ -z "$1" ] ; then
38445 +       echo "Usage: $0 <DEVICE>    eg, $0 GTA02"
38446 +       exit 1
38447 +fi
38448 +
38449 +../../dfu-util/src/dfu-util -a 3 -d 0x1d50:0x5119 -D uImage-$1.bin
38450 +if [ $? -eq 1 ] ; then
38451 +../../dfu-util/src/dfu-util -a 3 -d 0x1d50:0x5120 -D uImage-$1.bin
38452 +../../dfu-util/src/dfu-util -a 3 -d 0x1d50:0x5119 -D uImage-$1.bin
38453 +fi
38454 +
38455 +
38456 --- a/Documentation/arm/Samsung-S3C24XX/Suspend.txt
38457 +++ b/Documentation/arm/Samsung-S3C24XX/Suspend.txt
38458 @@ -40,13 +40,13 @@ Resuming
38459  Machine Support
38460  ---------------
38461
38462 -  The machine specific functions must call the s3c2410_pm_init() function
38463 +  The machine specific functions must call the s3c_pm_init() function
38464    to say that its bootloader is capable of resuming. This can be as
38465    simple as adding the following to the machine's definition:
38466
38467 -  INITMACHINE(s3c2410_pm_init)
38468 +  INITMACHINE(s3c_pm_init)
38469
38470 -  A board can do its own setup before calling s3c2410_pm_init, if it
38471 +  A board can do its own setup before calling s3c_pm_init, if it
38472    needs to setup anything else for power management support.
38473
38474    There is currently no support for over-riding the default method of
38475 @@ -74,7 +74,7 @@ statuc void __init machine_init(void)
38476
38477         enable_irq_wake(IRQ_EINT0);
38478
38479 -       s3c2410_pm_init();
38480 +       s3c_pm_init();
38481  }
38482
38483
38484 --- /dev/null
38485 +++ b/drivers/android/alarm.c
38486 @@ -0,0 +1,542 @@
38487 +/* drivers/android/alarm.c
38488 + *
38489 + * Copyright (C) 2007 Google, Inc.
38490 + *
38491 + * This software is licensed under the terms of the GNU General Public
38492 + * License version 2, as published by the Free Software Foundation, and
38493 + * may be copied, distributed, and modified under those terms.
38494 + *
38495 + * This program is distributed in the hope that it will be useful,
38496 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
38497 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
38498 + * GNU General Public License for more details.
38499 + *
38500 + */
38501 +
38502 +#include <asm/mach/time.h>
38503 +#include <linux/android_alarm.h>
38504 +#include <linux/android_power.h>
38505 +#include <linux/device.h>
38506 +#include <linux/miscdevice.h>
38507 +#include <linux/platform_device.h>
38508 +#include <linux/rtc.h>
38509 +#include <linux/spinlock.h>
38510 +#include <linux/sysdev.h>
38511 +
38512 +#define ANDROID_ALARM_PRINT_ERRORS (1U << 0)
38513 +#define ANDROID_ALARM_PRINT_INIT_STATUS (1U << 1)
38514 +#define ANDROID_ALARM_PRINT_INFO (1U << 2)
38515 +#define ANDROID_ALARM_PRINT_IO (1U << 3)
38516 +#define ANDROID_ALARM_PRINT_INT (1U << 4)
38517 +#define ANDROID_ALARM_PRINT_FLOW (1U << 5)
38518 +
38519 +#if 0
38520 +#define ANDROID_ALARM_DPRINTF_MASK (~0)
38521 +#define ANDROID_ALARM_DPRINTF(debug_level_mask, args...) \
38522 +       do { \
38523 +               if(ANDROID_ALARM_DPRINTF_MASK & debug_level_mask) { \
38524 +                       printk(args); \
38525 +               } \
38526 +       } while(0)
38527 +#else
38528 +#define ANDROID_ALARM_DPRINTF(args...)
38529 +#endif
38530 +
38531 +// support old usespace code
38532 +#define ANDROID_ALARM_SET_OLD               _IOW('a', 2, time_t) // set alarm
38533 +#define ANDROID_ALARM_SET_AND_WAIT_OLD      _IOW('a', 3, time_t)
38534 +
38535 +static struct rtc_device *alarm_rtc_dev;
38536 +static int alarm_opened;
38537 +static DEFINE_SPINLOCK(alarm_slock);
38538 +static DEFINE_MUTEX(alarm_setrtc_mutex);
38539 +static android_suspend_lock_t alarm_suspend_lock = {
38540 +       .name = "android_alarm"
38541 +};
38542 +static android_suspend_lock_t alarm_rtc_suspend_lock = {
38543 +       .name = "android_alarm_rtc"
38544 +};
38545 +static DECLARE_WAIT_QUEUE_HEAD(alarm_wait_queue);
38546 +static uint32_t alarm_pending;
38547 +static uint32_t alarm_enabled;
38548 +static uint32_t wait_pending;
38549 +static struct platform_device *alarm_platform_dev;
38550 +static struct hrtimer alarm_timer[ANDROID_ALARM_TYPE_COUNT];
38551 +static struct timespec alarm_time[ANDROID_ALARM_TYPE_COUNT];
38552 +static struct timespec elapsed_rtc_delta;
38553 +
38554 +static void alarm_start_hrtimer(android_alarm_type_t alarm_type)
38555 +{
38556 +       struct timespec hr_alarm_time;
38557 +       if(!(alarm_enabled & (1U << alarm_type)))
38558 +               return;
38559 +       hr_alarm_time = alarm_time[alarm_type];
38560 +       if(alarm_type == ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP || alarm_type == ANDROID_ALARM_ELAPSED_REALTIME)
38561 +               set_normalized_timespec(&hr_alarm_time, hr_alarm_time.tv_sec + elapsed_rtc_delta.tv_sec,
38562 +                                       hr_alarm_time.tv_nsec + elapsed_rtc_delta.tv_nsec);
38563 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, "alarm start hrtimer %d at %ld.%09ld\n", alarm_type, hr_alarm_time.tv_sec, hr_alarm_time.tv_nsec);
38564 +       hrtimer_start(&alarm_timer[alarm_type], timespec_to_ktime(hr_alarm_time), HRTIMER_MODE_ABS);
38565 +}
38566 +
38567 +static long alarm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
38568 +{
38569 +       int rv = 0;
38570 +       unsigned long flags;
38571 +       int i;
38572 +       struct timespec new_alarm_time;
38573 +       struct timespec new_rtc_time;
38574 +       struct timespec tmp_time;
38575 +       struct rtc_time rtc_new_rtc_time;
38576 +       android_alarm_type_t alarm_type = ANDROID_ALARM_IOCTL_TO_TYPE(cmd);
38577 +       uint32_t alarm_type_mask = 1U << alarm_type;
38578 +
38579 +       if(alarm_type >= ANDROID_ALARM_TYPE_COUNT)
38580 +               return -EINVAL;
38581 +
38582 +       if(ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_GET_TIME(0)) {
38583 +               if ((file->f_flags & O_ACCMODE) == O_RDONLY)
38584 +                       return -EPERM;
38585 +               if(file->private_data == NULL && cmd != ANDROID_ALARM_SET_RTC) {
38586 +                       spin_lock_irqsave(&alarm_slock, flags);
38587 +                       if(alarm_opened) {
38588 +                               spin_unlock_irqrestore(&alarm_slock, flags);
38589 +                               return -EBUSY;
38590 +                       }
38591 +                       alarm_opened = 1;
38592 +                       file->private_data = (void *)1;
38593 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38594 +               }
38595 +       }
38596 +
38597 +       switch(ANDROID_ALARM_BASE_CMD(cmd)) {
38598 +               //case ANDROID_ALARM_CLEAR_OLD: // same as ANDROID_ALARM_CLEAR(0)
38599 +               case ANDROID_ALARM_CLEAR(0):
38600 +                       spin_lock_irqsave(&alarm_slock, flags);
38601 +                       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, "alarm %d clear\n", alarm_type);
38602 +                       hrtimer_try_to_cancel(&alarm_timer[alarm_type]);
38603 +                       if(alarm_pending) {
38604 +                               alarm_pending &= ~alarm_type_mask;
38605 +                               if(!alarm_pending && !wait_pending) {
38606 +                                       android_unlock_suspend(&alarm_suspend_lock);
38607 +                               }
38608 +                       }
38609 +                       alarm_enabled &= ~alarm_type_mask;
38610 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38611 +                       break;
38612 +
38613 +               case ANDROID_ALARM_SET_OLD:
38614 +               case ANDROID_ALARM_SET_AND_WAIT_OLD:
38615 +                       if(get_user(new_alarm_time.tv_sec, (int __user *)arg)) {
38616 +                               rv = -EFAULT;
38617 +                               goto err1;
38618 +                       }
38619 +                       new_alarm_time.tv_nsec = 0;
38620 +                       goto from_old_alarm_set;
38621 +
38622 +               case ANDROID_ALARM_SET_AND_WAIT(0):
38623 +               case ANDROID_ALARM_SET(0):
38624 +                       if(copy_from_user(&new_alarm_time, (void __user *)arg, sizeof(new_alarm_time))) {
38625 +                               rv = -EFAULT;
38626 +                               goto err1;
38627 +                       }
38628 +from_old_alarm_set:
38629 +                       spin_lock_irqsave(&alarm_slock, flags);
38630 +                       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, "alarm %d set %ld.%09ld\n", alarm_type, new_alarm_time.tv_sec, new_alarm_time.tv_nsec);
38631 +                       alarm_time[alarm_type] = new_alarm_time;
38632 +                       alarm_enabled |= alarm_type_mask;
38633 +                       alarm_start_hrtimer(alarm_type);
38634 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38635 +                       if(ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_SET_AND_WAIT(0) && cmd != ANDROID_ALARM_SET_AND_WAIT_OLD)
38636 +                               break;
38637 +                       // fall though
38638 +               case ANDROID_ALARM_WAIT:
38639 +                       spin_lock_irqsave(&alarm_slock, flags);
38640 +                       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, "alarm wait\n");
38641 +                       if(!alarm_pending && wait_pending) {
38642 +                               android_unlock_suspend(&alarm_suspend_lock);
38643 +                               wait_pending = 0;
38644 +                       }
38645 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38646 +                       rv = wait_event_interruptible(alarm_wait_queue, alarm_pending);
38647 +                       if(rv)
38648 +                               goto err1;
38649 +                       spin_lock_irqsave(&alarm_slock, flags);
38650 +                       rv = alarm_pending;
38651 +                       wait_pending = 1;
38652 +                       alarm_pending = 0;
38653 +                       if(rv & (ANDROID_ALARM_RTC_WAKEUP_MASK | ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)) {
38654 +                               android_unlock_suspend(&alarm_rtc_suspend_lock);
38655 +                       }
38656 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38657 +                       break;
38658 +               case ANDROID_ALARM_SET_RTC:
38659 +                       if(copy_from_user(&new_rtc_time, (void __user *)arg, sizeof(new_rtc_time))) {
38660 +                               rv = -EFAULT;
38661 +                               goto err1;
38662 +                       }
38663 +                       rtc_time_to_tm(new_rtc_time.tv_sec, &rtc_new_rtc_time);
38664 +
38665 +                       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO,
38666 +                               "set rtc %ld %ld - rtc %02d:%02d:%02d %02d/%02d/%04d\n",
38667 +                               new_rtc_time.tv_sec, new_rtc_time.tv_nsec,
38668 +                               rtc_new_rtc_time.tm_hour, rtc_new_rtc_time.tm_min,
38669 +                               rtc_new_rtc_time.tm_sec, rtc_new_rtc_time.tm_mon + 1,
38670 +                               rtc_new_rtc_time.tm_mday, rtc_new_rtc_time.tm_year + 1900);
38671 +
38672 +                       mutex_lock(&alarm_setrtc_mutex);
38673 +                       spin_lock_irqsave(&alarm_slock, flags);
38674 +                       for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++)
38675 +                               hrtimer_try_to_cancel(&alarm_timer[i]);
38676 +                       getnstimeofday(&tmp_time);
38677 +                       elapsed_rtc_delta = timespec_sub(elapsed_rtc_delta, timespec_sub(tmp_time, new_rtc_time));
38678 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38679 +                       rv = do_settimeofday(&new_rtc_time);
38680 +                       spin_lock_irqsave(&alarm_slock, flags);
38681 +                       for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++)
38682 +                               alarm_start_hrtimer(i);
38683 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38684 +                       if(rv < 0) {
38685 +                               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_ERRORS, "Failed to set time\n");
38686 +                               mutex_unlock(&alarm_setrtc_mutex);
38687 +                               goto err1;
38688 +                       }
38689 +                       rv = rtc_set_time(alarm_rtc_dev, &rtc_new_rtc_time);
38690 +                       spin_lock_irqsave(&alarm_slock, flags);
38691 +                       alarm_pending |= ANDROID_ALARM_TIME_CHANGE_MASK;
38692 +                       wake_up(&alarm_wait_queue);
38693 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38694 +                       mutex_unlock(&alarm_setrtc_mutex);
38695 +                       if(rv < 0) {
38696 +                               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_ERRORS, "Failed to set RTC, time will be lost on reboot\n");
38697 +                               goto err1;
38698 +                       }
38699 +                       break;
38700 +               case ANDROID_ALARM_GET_TIME(0):
38701 +                       mutex_lock(&alarm_setrtc_mutex);
38702 +                       spin_lock_irqsave(&alarm_slock, flags);
38703 +                       if(alarm_type != ANDROID_ALARM_SYSTEMTIME) {
38704 +                               getnstimeofday(&tmp_time);
38705 +                               if(alarm_type >= ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP) {
38706 +                                       tmp_time = timespec_sub(tmp_time, elapsed_rtc_delta);
38707 +                               }
38708 +                       }
38709 +                       else
38710 +                               ktime_get_ts(&tmp_time);
38711 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38712 +                       mutex_unlock(&alarm_setrtc_mutex);
38713 +                       if(copy_to_user((void __user *)arg, &tmp_time, sizeof(tmp_time))) {
38714 +                               rv = -EFAULT;
38715 +                               goto err1;
38716 +                       }
38717 +                       break;
38718 +
38719 +               default:
38720 +                       rv = -EINVAL;
38721 +                       goto err1;
38722 +       }
38723 +err1:
38724 +       return rv;
38725 +}
38726 +
38727 +static int alarm_open(struct inode *inode, struct file *file)
38728 +{
38729 +       file->private_data = NULL;
38730 +       return 0;
38731 +}
38732 +
38733 +static int alarm_release(struct inode *inode, struct file *file)
38734 +{
38735 +       int i;
38736 +       unsigned long flags;
38737 +
38738 +       spin_lock_irqsave(&alarm_slock, flags);
38739 +       if(file->private_data != 0) {
38740 +               for(i = 0; i < ANDROID_ALARM_TYPE_COUNT; i++) {
38741 +                       uint32_t alarm_type_mask = 1U << i;
38742 +                       if(alarm_enabled & alarm_type_mask) {
38743 +                               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm_release: clear alarm, pending %d\n", !!(alarm_pending & alarm_type_mask));
38744 +                               alarm_enabled &= ~alarm_type_mask;
38745 +                       }
38746 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38747 +                       hrtimer_cancel(&alarm_timer[i]);
38748 +                       spin_lock_irqsave(&alarm_slock, flags);
38749 +               }
38750 +               if(alarm_pending | wait_pending) {
38751 +                       if(alarm_pending)
38752 +                               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm_release: clear pending alarms %x\n", alarm_pending);
38753 +                       android_unlock_suspend(&alarm_suspend_lock);
38754 +                       wait_pending = 0;
38755 +                       alarm_pending = 0;
38756 +               }
38757 +               alarm_opened = 0;
38758 +       }
38759 +       spin_unlock_irqrestore(&alarm_slock, flags);
38760 +       return 0;
38761 +}
38762 +
38763 +static enum hrtimer_restart alarm_timer_triggered(struct hrtimer *timer)
38764 +{
38765 +       unsigned long flags;
38766 +       android_alarm_type_t alarm_type = (timer - alarm_timer);
38767 +       uint32_t alarm_type_mask = 1U << alarm_type;
38768 +
38769 +
38770 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INT, "alarm_timer_triggered type %d\n", alarm_type);
38771 +       spin_lock_irqsave(&alarm_slock, flags);
38772 +       if (alarm_enabled & alarm_type_mask) {
38773 +               android_lock_suspend_auto_expire(&alarm_suspend_lock, 5 * HZ);
38774 +               alarm_enabled &= ~alarm_type_mask;
38775 +               alarm_pending |= alarm_type_mask;
38776 +               wake_up(&alarm_wait_queue);
38777 +       }
38778 +       spin_unlock_irqrestore(&alarm_slock, flags);
38779 +       return HRTIMER_NORESTART;
38780 +}
38781 +
38782 +static void alarm_triggered_func(void *p)
38783 +{
38784 +//     unsigned long flags;
38785 +
38786 +       struct rtc_device *rtc = alarm_rtc_dev;
38787 +       if(rtc->irq_data & RTC_AF) {
38788 +               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INT, "alarm_triggered_func:\n");
38789 +               android_lock_suspend_auto_expire(&alarm_rtc_suspend_lock, 1 * HZ);
38790 +       }
38791 +}
38792 +
38793 +int alarm_suspend(struct platform_device *pdev, pm_message_t state)
38794 +{
38795 +       int                 err = 0;
38796 +       unsigned long       flags;
38797 +       struct rtc_wkalrm   rtc_alarm;
38798 +       struct rtc_time     rtc_current_rtc_time;
38799 +       unsigned long       rtc_current_time;
38800 +       unsigned long       rtc_alarm_time;
38801 +       struct timespec     rtc_current_timespec;
38802 +       struct timespec     rtc_delta;
38803 +       struct timespec     elapsed_realtime_alarm_time;
38804 +
38805 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, "alarm_suspend(%p, %d)\n", pdev, state.event);
38806 +       spin_lock_irqsave(&alarm_slock, flags);
38807 +       if(alarm_pending && (alarm_suspend_lock.flags & ANDROID_SUSPEND_LOCK_AUTO_EXPIRE)) {
38808 +               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm pending\n");
38809 +               err = -EBUSY;
38810 +               goto err1;
38811 +       }
38812 +       if(alarm_enabled & (ANDROID_ALARM_RTC_WAKEUP_MASK | ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)) {
38813 +               spin_unlock_irqrestore(&alarm_slock, flags);
38814 +               if(alarm_enabled & ANDROID_ALARM_RTC_WAKEUP_MASK)
38815 +                       hrtimer_cancel(&alarm_timer[ANDROID_ALARM_RTC_WAKEUP]);
38816 +               if(alarm_enabled & ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)
38817 +                       hrtimer_cancel(&alarm_timer[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP]);
38818 +
38819 +               rtc_read_time(alarm_rtc_dev, &rtc_current_rtc_time);
38820 +               rtc_current_timespec.tv_nsec = 0;
38821 +               rtc_tm_to_time(&rtc_current_rtc_time, &rtc_current_timespec.tv_sec);
38822 +               save_time_delta(&rtc_delta, &rtc_current_timespec);
38823 +               set_normalized_timespec(&elapsed_realtime_alarm_time,
38824 +                       alarm_time[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP].tv_sec + elapsed_rtc_delta.tv_sec,
38825 +                       alarm_time[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP].tv_nsec + elapsed_rtc_delta.tv_nsec);
38826 +               if((alarm_enabled & ANDROID_ALARM_RTC_WAKEUP_MASK) &&
38827 +                  (!(alarm_enabled & ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)
38828 +                  || timespec_compare(&alarm_time[ANDROID_ALARM_RTC_WAKEUP], &elapsed_realtime_alarm_time) < 0))
38829 +                       rtc_alarm_time = timespec_sub(alarm_time[ANDROID_ALARM_RTC_WAKEUP], rtc_delta).tv_sec;
38830 +               else {
38831 +                       rtc_alarm_time = timespec_sub(elapsed_realtime_alarm_time, rtc_delta).tv_sec;
38832 +               }
38833 +               rtc_time_to_tm(rtc_alarm_time, &rtc_alarm.time);
38834 +               rtc_alarm.enabled = 1;
38835 +               rtc_set_alarm(alarm_rtc_dev, &rtc_alarm);
38836 +               rtc_read_time(alarm_rtc_dev, &rtc_current_rtc_time);
38837 +               rtc_tm_to_time(&rtc_current_rtc_time, &rtc_current_time);
38838 +               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO,
38839 +                       "rtc alarm set at %ld, now %ld, rtc delta %ld.%09ld\n",
38840 +                       rtc_alarm_time, rtc_current_time,
38841 +                       rtc_delta.tv_sec, rtc_delta.tv_nsec);
38842 +               if(rtc_current_time + 1 >= rtc_alarm_time) {
38843 +                       //spin_lock_irqsave(&alarm_slock, flags);
38844 +                       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm about to go off\n");
38845 +                       memset(&rtc_alarm, 0, sizeof(rtc_alarm));
38846 +                       rtc_alarm.enabled = 0;
38847 +                       rtc_set_alarm(alarm_rtc_dev, &rtc_alarm);
38848 +
38849 +                       spin_lock_irqsave(&alarm_slock, flags);
38850 +                       android_lock_suspend_auto_expire(&alarm_rtc_suspend_lock, 2 * HZ); // trigger a wakeup
38851 +                       alarm_start_hrtimer(ANDROID_ALARM_RTC_WAKEUP);
38852 +                       alarm_start_hrtimer(ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP);
38853 +                       err = -EBUSY;
38854 +                       spin_unlock_irqrestore(&alarm_slock, flags);
38855 +               }
38856 +       }
38857 +       else {
38858 +err1:
38859 +               spin_unlock_irqrestore(&alarm_slock, flags);
38860 +       }
38861 +       return err;
38862 +}
38863 +
38864 +int alarm_resume(struct platform_device *pdev)
38865 +{
38866 +       struct rtc_wkalrm alarm;
38867 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, "alarm_resume(%p)\n", pdev);
38868 +       if(alarm_enabled & (ANDROID_ALARM_RTC_WAKEUP_MASK | ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)) {
38869 +               memset(&alarm, 0, sizeof(alarm));
38870 +               alarm.enabled = 0;
38871 +               rtc_set_alarm(alarm_rtc_dev, &alarm);
38872 +               alarm_start_hrtimer(ANDROID_ALARM_RTC_WAKEUP);
38873 +               alarm_start_hrtimer(ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP);
38874 +       }
38875 +       return 0;
38876 +}
38877 +
38878 +static struct rtc_task alarm_rtc_task = {
38879 +       .func = alarm_triggered_func
38880 +};
38881 +
38882 +static struct file_operations alarm_fops = {
38883 +       .owner = THIS_MODULE,
38884 +       .unlocked_ioctl = alarm_ioctl,
38885 +       .open = alarm_open,
38886 +       .release = alarm_release,
38887 +};
38888 +
38889 +static struct miscdevice alarm_device = {
38890 +       .minor = MISC_DYNAMIC_MINOR,
38891 +       .name = "alarm",
38892 +       .fops = &alarm_fops,
38893 +};
38894 +
38895 +static int rtc_alarm_add_device(struct device *dev,
38896 +                               struct class_interface *class_intf)
38897 +{
38898 +       int err;
38899 +       struct rtc_device *rtc = to_rtc_device(dev);
38900 +
38901 +       mutex_lock(&alarm_setrtc_mutex);
38902 +
38903 +       if(alarm_rtc_dev) {
38904 +               err = -EBUSY;
38905 +               goto err1;
38906 +       }
38907 +
38908 +       err = misc_register(&alarm_device);
38909 +       if(err)
38910 +               goto err1;
38911 +       alarm_platform_dev = platform_device_register_simple("alarm", -1, NULL, 0);
38912 +       if(IS_ERR(alarm_platform_dev)) {
38913 +               err = PTR_ERR(alarm_platform_dev);
38914 +               goto err2;
38915 +       }
38916 +       err = rtc_irq_register(rtc, &alarm_rtc_task);
38917 +       if(err)
38918 +               goto err3;
38919 +       alarm_rtc_dev = rtc;
38920 +       mutex_unlock(&alarm_setrtc_mutex);
38921 +
38922 +       //device_pm_set_parent(&alarm_platform_dev->dev, dev); // currently useless, drivers are suspended in reverse creation order
38923 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm: parent %p\n", alarm_platform_dev->dev.power.pm_parent);
38924 +       return 0;
38925 +
38926 +err3:
38927 +       platform_device_unregister(alarm_platform_dev);
38928 +err2:
38929 +       misc_deregister(&alarm_device);
38930 +err1:
38931 +       mutex_unlock(&alarm_setrtc_mutex);
38932 +       return err;
38933 +}
38934 +
38935 +static void rtc_alarm_remove_device(struct device *dev,
38936 +                                    struct class_interface *class_intf)
38937 +{
38938 +       if(dev == &alarm_rtc_dev->dev) {
38939 +               rtc_irq_unregister(alarm_rtc_dev, &alarm_rtc_task);
38940 +               platform_device_unregister(alarm_platform_dev);
38941 +               misc_deregister(&alarm_device);
38942 +               alarm_rtc_dev = NULL;
38943 +       }
38944 +}
38945 +
38946 +static struct class_interface rtc_alarm_interface = {
38947 +       .add_dev = &rtc_alarm_add_device,
38948 +       .remove_dev = &rtc_alarm_remove_device,
38949 +};
38950 +
38951 +static struct platform_driver alarm_driver = {
38952 +       .suspend = alarm_suspend,
38953 +       .resume = alarm_resume,
38954 +       .driver = {
38955 +               .name = "alarm"
38956 +       }
38957 +};
38958 +
38959 +static int __init alarm_late_init(void)
38960 +{
38961 +       unsigned long   flags;
38962 +       struct timespec system_time;
38963 +
38964 +       // this needs to run after the rtc is read at boot
38965 +       spin_lock_irqsave(&alarm_slock, flags);
38966 +       // We read the current rtc and system time so we can later calulate
38967 +       // elasped realtime to be (boot_systemtime + rtc - boot_rtc) ==
38968 +       // (rtc - (boot_rtc - boot_systemtime))
38969 +       getnstimeofday(&elapsed_rtc_delta);
38970 +       ktime_get_ts(&system_time);
38971 +       elapsed_rtc_delta = timespec_sub(elapsed_rtc_delta, system_time);
38972 +       spin_unlock_irqrestore(&alarm_slock, flags);
38973 +
38974 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO,
38975 +               "alarm_late_init: rtc to elapsed realtime delta %ld.%09ld\n",
38976 +               elapsed_rtc_delta.tv_sec, elapsed_rtc_delta.tv_nsec);
38977 +       return 0;
38978 +}
38979 +
38980 +static int __init alarm_init(void)
38981 +{
38982 +       int err;
38983 +       int i;
38984 +
38985 +       for(i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++) {
38986 +               hrtimer_init(&alarm_timer[i], CLOCK_REALTIME, HRTIMER_MODE_ABS);
38987 +               alarm_timer[i].function = alarm_timer_triggered;
38988 +       }
38989 +       hrtimer_init(&alarm_timer[ANDROID_ALARM_SYSTEMTIME], CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
38990 +       alarm_timer[ANDROID_ALARM_SYSTEMTIME].function = alarm_timer_triggered;
38991 +       err = platform_driver_register(&alarm_driver);
38992 +       if(err < 0)
38993 +               goto err1;
38994 +       err = android_init_suspend_lock(&alarm_suspend_lock);
38995 +       if(err < 0)
38996 +               goto err2;
38997 +       err = android_init_suspend_lock(&alarm_rtc_suspend_lock);
38998 +       if(err < 0)
38999 +               goto err3;
39000 +       rtc_alarm_interface.class = rtc_class;
39001 +       err = class_interface_register(&rtc_alarm_interface);
39002 +       if(err < 0)
39003 +               goto err4;
39004 +
39005 +       return 0;
39006 +
39007 +err4:
39008 +       android_uninit_suspend_lock(&alarm_rtc_suspend_lock);
39009 +err3:
39010 +       android_uninit_suspend_lock(&alarm_suspend_lock);
39011 +err2:
39012 +       platform_driver_unregister(&alarm_driver);
39013 +err1:
39014 +       return err;
39015 +}
39016 +
39017 +static void  __exit alarm_exit(void)
39018 +{
39019 +       class_interface_unregister(&rtc_alarm_interface);
39020 +       android_uninit_suspend_lock(&alarm_rtc_suspend_lock);
39021 +       android_uninit_suspend_lock(&alarm_suspend_lock);
39022 +       platform_driver_unregister(&alarm_driver);
39023 +}
39024 +
39025 +late_initcall(alarm_late_init);
39026 +module_init(alarm_init);
39027 +module_exit(alarm_exit);
39028 +
39029 --- /dev/null
39030 +++ b/drivers/android/binder.c
39031 @@ -0,0 +1,3495 @@
39032 +/* drivers/android/binder.c
39033 + *
39034 + * Android IPC Subsystem
39035 + *
39036 + * Copyright (C) 2007-2008 Google, Inc.
39037 + *
39038 + * This software is licensed under the terms of the GNU General Public
39039 + * License version 2, as published by the Free Software Foundation, and
39040 + * may be copied, distributed, and modified under those terms.
39041 + *
39042 + * This program is distributed in the hope that it will be useful,
39043 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
39044 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
39045 + * GNU General Public License for more details.
39046 + *
39047 + */
39048 +
39049 +#include <asm/cacheflush.h>
39050 +#include <linux/binder.h>
39051 +#include <linux/fdtable.h>
39052 +#include <linux/file.h>
39053 +#include <linux/fs.h>
39054 +#include <linux/list.h>
39055 +#include <linux/miscdevice.h>
39056 +#include <linux/mm.h>
39057 +#include <linux/module.h>
39058 +#include <linux/mutex.h>
39059 +#include <linux/nsproxy.h>
39060 +#include <linux/poll.h>
39061 +#include <linux/proc_fs.h>
39062 +#include <linux/rbtree.h>
39063 +#include <linux/sched.h>
39064 +#include <linux/uaccess.h>
39065 +#include <linux/vmalloc.h>
39066 +
39067 +static DEFINE_MUTEX(binder_lock);
39068 +static HLIST_HEAD(binder_procs);
39069 +static struct binder_node *binder_context_mgr_node;
39070 +static uid_t binder_context_mgr_uid = -1;
39071 +static int binder_last_id;
39072 +static struct proc_dir_entry *binder_proc_dir_entry_root;
39073 +static struct proc_dir_entry *binder_proc_dir_entry_proc;
39074 +static struct hlist_head binder_dead_nodes;
39075 +
39076 +static int binder_read_proc_proc(
39077 +       char *page, char **start, off_t off, int count, int *eof, void *data);
39078 +
39079 +/* This is only defined in include/asm-arm/sizes.h */
39080 +#ifndef SZ_1K
39081 +#define SZ_1K                               0x400
39082 +#endif
39083 +
39084 +#ifndef SZ_4M
39085 +#define SZ_4M                               0x400000
39086 +#endif
39087 +
39088 +#define FORBIDDEN_MMAP_FLAGS                (VM_WRITE)
39089 +
39090 +#define BINDER_SMALL_BUF_SIZE (PAGE_SIZE * 64)
39091 +
39092 +enum {
39093 +       BINDER_DEBUG_USER_ERROR             = 1U << 0,
39094 +       BINDER_DEBUG_FAILED_TRANSACTION     = 1U << 1,
39095 +       BINDER_DEBUG_DEAD_TRANSACTION       = 1U << 2,
39096 +       BINDER_DEBUG_OPEN_CLOSE             = 1U << 3,
39097 +       BINDER_DEBUG_DEAD_BINDER            = 1U << 4,
39098 +       BINDER_DEBUG_DEATH_NOTIFICATION     = 1U << 5,
39099 +       BINDER_DEBUG_READ_WRITE             = 1U << 6,
39100 +       BINDER_DEBUG_USER_REFS              = 1U << 7,
39101 +       BINDER_DEBUG_THREADS                = 1U << 8,
39102 +       BINDER_DEBUG_TRANSACTION            = 1U << 9,
39103 +       BINDER_DEBUG_TRANSACTION_COMPLETE   = 1U << 10,
39104 +       BINDER_DEBUG_FREE_BUFFER            = 1U << 11,
39105 +       BINDER_DEBUG_INTERNAL_REFS          = 1U << 12,
39106 +       BINDER_DEBUG_BUFFER_ALLOC           = 1U << 13,
39107 +       BINDER_DEBUG_PRIORITY_CAP           = 1U << 14,
39108 +       BINDER_DEBUG_BUFFER_ALLOC_ASYNC     = 1U << 15,
39109 +};
39110 +static uint32_t binder_debug_mask = BINDER_DEBUG_USER_ERROR |
39111 +       BINDER_DEBUG_FAILED_TRANSACTION | BINDER_DEBUG_DEAD_TRANSACTION;
39112 +module_param_named(debug_mask, binder_debug_mask, uint, S_IWUSR | S_IRUGO)
39113 +static int binder_debug_no_lock;
39114 +module_param_named(proc_no_lock, binder_debug_no_lock, bool, S_IWUSR | S_IRUGO)
39115 +static DECLARE_WAIT_QUEUE_HEAD(binder_user_error_wait);
39116 +static int binder_stop_on_user_error;
39117 +static int binder_set_stop_on_user_error(
39118 +       const char *val, struct kernel_param *kp)
39119 +{
39120 +       int ret;
39121 +       ret = param_set_int(val, kp);
39122 +       if (binder_stop_on_user_error < 2)
39123 +               wake_up(&binder_user_error_wait);
39124 +       return ret;
39125 +}
39126 +module_param_call(stop_on_user_error, binder_set_stop_on_user_error,
39127 +       param_get_int, &binder_stop_on_user_error, S_IWUSR | S_IRUGO);
39128 +
39129 +#define binder_user_error(x...) \
39130 +       do { \
39131 +               if (binder_debug_mask & BINDER_DEBUG_USER_ERROR) \
39132 +                       printk(KERN_INFO x); \
39133 +               if (binder_stop_on_user_error) \
39134 +                       binder_stop_on_user_error = 2; \
39135 +       } while (0)
39136 +
39137 +enum {
39138 +       BINDER_STAT_PROC,
39139 +       BINDER_STAT_THREAD,
39140 +       BINDER_STAT_NODE,
39141 +       BINDER_STAT_REF,
39142 +       BINDER_STAT_DEATH,
39143 +       BINDER_STAT_TRANSACTION,
39144 +       BINDER_STAT_TRANSACTION_COMPLETE,
39145 +       BINDER_STAT_COUNT
39146 +};
39147 +
39148 +struct binder_stats {
39149 +       int br[_IOC_NR(BR_FAILED_REPLY) + 1];
39150 +       int bc[_IOC_NR(BC_DEAD_BINDER_DONE) + 1];
39151 +       int obj_created[BINDER_STAT_COUNT];
39152 +       int obj_deleted[BINDER_STAT_COUNT];
39153 +};
39154 +
39155 +static struct binder_stats binder_stats;
39156 +
39157 +struct binder_transaction_log_entry {
39158 +       int debug_id;
39159 +       int call_type;
39160 +       int from_proc;
39161 +       int from_thread;
39162 +       int target_handle;
39163 +       int to_proc;
39164 +       int to_thread;
39165 +       int to_node;
39166 +       int data_size;
39167 +       int offsets_size;
39168 +};
39169 +struct binder_transaction_log {
39170 +       int next;
39171 +       int full;
39172 +       struct binder_transaction_log_entry entry[32];
39173 +};
39174 +struct binder_transaction_log binder_transaction_log;
39175 +struct binder_transaction_log binder_transaction_log_failed;
39176 +
39177 +static struct binder_transaction_log_entry *binder_transaction_log_add(
39178 +       struct binder_transaction_log *log)
39179 +{
39180 +       struct binder_transaction_log_entry *e;
39181 +       e = &log->entry[log->next];
39182 +       memset(e, 0, sizeof(*e));
39183 +       log->next++;
39184 +       if (log->next == ARRAY_SIZE(log->entry)) {
39185 +               log->next = 0;
39186 +               log->full = 1;
39187 +       }
39188 +       return e;
39189 +}
39190 +
39191 +struct binder_work {
39192 +       struct list_head entry;
39193 +       enum {
39194 +               BINDER_WORK_TRANSACTION = 1,
39195 +               BINDER_WORK_TRANSACTION_COMPLETE,
39196 +               BINDER_WORK_NODE,
39197 +               BINDER_WORK_DEAD_BINDER,
39198 +               BINDER_WORK_DEAD_BINDER_AND_CLEAR,
39199 +               BINDER_WORK_CLEAR_DEATH_NOTIFICATION,
39200 +       } type;
39201 +};
39202 +
39203 +struct binder_node {
39204 +       int debug_id;
39205 +       struct binder_work work;
39206 +       union {
39207 +               struct rb_node rb_node;
39208 +               struct hlist_node dead_node;
39209 +       };
39210 +       struct binder_proc *proc;
39211 +       struct hlist_head refs;
39212 +       int internal_strong_refs;
39213 +       int local_weak_refs;
39214 +       int local_strong_refs;
39215 +       void __user *ptr;
39216 +       void __user *cookie;
39217 +       unsigned has_strong_ref : 1;
39218 +       unsigned pending_strong_ref : 1;
39219 +       unsigned has_weak_ref : 1;
39220 +       unsigned pending_weak_ref : 1;
39221 +       unsigned has_async_transaction : 1;
39222 +       unsigned accept_fds : 1;
39223 +       int min_priority : 8;
39224 +       struct list_head async_todo;
39225 +};
39226 +
39227 +struct binder_ref_death {
39228 +       struct binder_work work;
39229 +       void __user *cookie;
39230 +};
39231 +
39232 +struct binder_ref {
39233 +       /* Lookups needed: */
39234 +       /*   node + proc => ref (transaction) */
39235 +       /*   desc + proc => ref (transaction, inc/dec ref) */
39236 +       /*   node => refs + procs (proc exit) */
39237 +       int debug_id;
39238 +       struct rb_node rb_node_desc;
39239 +       struct rb_node rb_node_node;
39240 +       struct hlist_node node_entry;
39241 +       struct binder_proc *proc;
39242 +       struct binder_node *node;
39243 +       uint32_t desc;
39244 +       int strong;
39245 +       int weak;
39246 +       struct binder_ref_death *death;
39247 +};
39248 +
39249 +struct binder_buffer {
39250 +       struct list_head entry; /* free and allocated entries by addesss */
39251 +       struct rb_node rb_node; /* free entry by size or allocated entry */
39252 +                               /* by address */
39253 +       unsigned free : 1;
39254 +       unsigned allow_user_free : 1;
39255 +       unsigned async_transaction : 1;
39256 +       unsigned debug_id : 29;
39257 +
39258 +       struct binder_transaction *transaction;
39259 +
39260 +       struct binder_node *target_node;
39261 +       size_t data_size;
39262 +       size_t offsets_size;
39263 +       uint8_t data[0];
39264 +};
39265 +
39266 +struct binder_proc {
39267 +       struct hlist_node proc_node;
39268 +       struct rb_root threads;
39269 +       struct rb_root nodes;
39270 +       struct rb_root refs_by_desc;
39271 +       struct rb_root refs_by_node;
39272 +       int pid;
39273 +       struct vm_area_struct *vma;
39274 +       struct task_struct *tsk;
39275 +       void *buffer;
39276 +       size_t user_buffer_offset;
39277 +
39278 +       struct list_head buffers;
39279 +       struct rb_root free_buffers;
39280 +       struct rb_root allocated_buffers;
39281 +       size_t free_async_space;
39282 +
39283 +       struct page **pages;
39284 +       size_t buffer_size;
39285 +       uint32_t buffer_free;
39286 +       struct list_head todo;
39287 +       wait_queue_head_t wait;
39288 +       struct binder_stats stats;
39289 +       struct list_head delivered_death;
39290 +       int max_threads;
39291 +       int requested_threads;
39292 +       int requested_threads_started;
39293 +       int ready_threads;
39294 +       long default_priority;
39295 +};
39296 +
39297 +enum {
39298 +       BINDER_LOOPER_STATE_REGISTERED  = 0x01,
39299 +       BINDER_LOOPER_STATE_ENTERED     = 0x02,
39300 +       BINDER_LOOPER_STATE_EXITED      = 0x04,
39301 +       BINDER_LOOPER_STATE_INVALID     = 0x08,
39302 +       BINDER_LOOPER_STATE_WAITING     = 0x10,
39303 +       BINDER_LOOPER_STATE_NEED_RETURN = 0x20
39304 +};
39305 +
39306 +struct binder_thread {
39307 +       struct binder_proc *proc;
39308 +       struct rb_node rb_node;
39309 +       int pid;
39310 +       int looper;
39311 +       struct binder_transaction *transaction_stack;
39312 +       struct list_head todo;
39313 +       uint32_t return_error; /* Write failed, return error code in read buf */
39314 +       uint32_t return_error2; /* Write failed, return error code in read */
39315 +               /* buffer. Used when sending a reply to a dead process that */
39316 +               /* we are also waiting on */
39317 +       wait_queue_head_t wait;
39318 +       struct binder_stats stats;
39319 +};
39320 +
39321 +struct binder_transaction {
39322 +       int debug_id;
39323 +       struct binder_work work;
39324 +       struct binder_thread *from;
39325 +       struct binder_transaction *from_parent;
39326 +       struct binder_proc *to_proc;
39327 +       struct binder_thread *to_thread;
39328 +       struct binder_transaction *to_parent;
39329 +       unsigned need_reply : 1;
39330 +       /*unsigned is_dead : 1;*/ /* not used at the moment */
39331 +
39332 +       struct binder_buffer *buffer;
39333 +       unsigned int    code;
39334 +       unsigned int    flags;
39335 +       long    priority;
39336 +       long    saved_priority;
39337 +       uid_t   sender_euid;
39338 +};
39339 +
39340 +/*
39341 + * copied from get_unused_fd_flags
39342 + */
39343 +int task_get_unused_fd_flags(struct task_struct *tsk, int flags)
39344 +{
39345 +       struct files_struct *files = get_files_struct(tsk);
39346 +       int fd, error;
39347 +       struct fdtable *fdt;
39348 +       unsigned long rlim_cur;
39349 +
39350 +       if (files == NULL)
39351 +               return -ESRCH;
39352 +
39353 +       error = -EMFILE;
39354 +       spin_lock(&files->file_lock);
39355 +
39356 +repeat:
39357 +       fdt = files_fdtable(files);
39358 +       fd = find_next_zero_bit(fdt->open_fds->fds_bits, fdt->max_fds,
39359 +                               files->next_fd);
39360 +
39361 +       /*
39362 +        * N.B. For clone tasks sharing a files structure, this test
39363 +        * will limit the total number of files that can be opened.
39364 +        */
39365 +       rcu_read_lock();
39366 +       if (tsk->signal)
39367 +               rlim_cur = tsk->signal->rlim[RLIMIT_NOFILE].rlim_cur;
39368 +       else
39369 +               rlim_cur = 0;
39370 +       rcu_read_unlock();
39371 +       if (fd >= rlim_cur)
39372 +               goto out;
39373 +
39374 +       /* Do we need to expand the fd array or fd set?  */
39375 +       error = expand_files(files, fd);
39376 +       if (error < 0)
39377 +               goto out;
39378 +
39379 +       if (error) {
39380 +               /*
39381 +                * If we needed to expand the fs array we
39382 +                * might have blocked - try again.
39383 +                */
39384 +               error = -EMFILE;
39385 +               goto repeat;
39386 +       }
39387 +
39388 +       FD_SET(fd, fdt->open_fds);
39389 +       if (flags & O_CLOEXEC)
39390 +               FD_SET(fd, fdt->close_on_exec);
39391 +       else
39392 +               FD_CLR(fd, fdt->close_on_exec);
39393 +       files->next_fd = fd + 1;
39394 +#if 1
39395 +       /* Sanity check */
39396 +       if (fdt->fd[fd] != NULL) {
39397 +               printk(KERN_WARNING "get_unused_fd: slot %d not NULL!\n", fd);
39398 +               fdt->fd[fd] = NULL;
39399 +       }
39400 +#endif
39401 +       error = fd;
39402 +
39403 +out:
39404 +       spin_unlock(&files->file_lock);
39405 +       put_files_struct(files);
39406 +       return error;
39407 +}
39408 +
39409 +/*
39410 + * copied from fd_install
39411 + */
39412 +static void task_fd_install(
39413 +       struct task_struct *tsk, unsigned int fd, struct file *file)
39414 +{
39415 +       struct files_struct *files = get_files_struct(tsk);
39416 +       struct fdtable *fdt;
39417 +
39418 +       if (files == NULL)
39419 +               return;
39420 +
39421 +       spin_lock(&files->file_lock);
39422 +       fdt = files_fdtable(files);
39423 +       BUG_ON(fdt->fd[fd] != NULL);
39424 +       rcu_assign_pointer(fdt->fd[fd], file);
39425 +       spin_unlock(&files->file_lock);
39426 +       put_files_struct(files);
39427 +}
39428 +
39429 +/*
39430 + * copied from __put_unused_fd in open.c
39431 + */
39432 +static void __put_unused_fd(struct files_struct *files, unsigned int fd)
39433 +{
39434 +       struct fdtable *fdt = files_fdtable(files);
39435 +       __FD_CLR(fd, fdt->open_fds);
39436 +       if (fd < files->next_fd)
39437 +               files->next_fd = fd;
39438 +}
39439 +
39440 +/*
39441 + * copied from sys_close
39442 + */
39443 +static long task_close_fd(struct task_struct *tsk, unsigned int fd)
39444 +{
39445 +       struct file *filp;
39446 +       struct files_struct *files = get_files_struct(tsk);
39447 +       struct fdtable *fdt;
39448 +       int retval;
39449 +
39450 +       if (files == NULL)
39451 +               return -ESRCH;
39452 +
39453 +       spin_lock(&files->file_lock);
39454 +       fdt = files_fdtable(files);
39455 +       if (fd >= fdt->max_fds)
39456 +               goto out_unlock;
39457 +       filp = fdt->fd[fd];
39458 +       if (!filp)
39459 +               goto out_unlock;
39460 +       rcu_assign_pointer(fdt->fd[fd], NULL);
39461 +       FD_CLR(fd, fdt->close_on_exec);
39462 +       __put_unused_fd(files, fd);
39463 +       spin_unlock(&files->file_lock);
39464 +       retval = filp_close(filp, files);
39465 +
39466 +       /* can't restart close syscall because file table entry was cleared */
39467 +       if (unlikely(retval == -ERESTARTSYS ||
39468 +                    retval == -ERESTARTNOINTR ||
39469 +                    retval == -ERESTARTNOHAND ||
39470 +                    retval == -ERESTART_RESTARTBLOCK))
39471 +               retval = -EINTR;
39472 +
39473 +       put_files_struct(files);
39474 +       return retval;
39475 +
39476 +out_unlock:
39477 +       spin_unlock(&files->file_lock);
39478 +       put_files_struct(files);
39479 +       return -EBADF;
39480 +}
39481 +
39482 +static void binder_set_nice(long nice)
39483 +{
39484 +       long min_nice;
39485 +       if (can_nice(current, nice)) {
39486 +               set_user_nice(current, nice);
39487 +               return;
39488 +       }
39489 +       min_nice = 20 - current->signal->rlim[RLIMIT_NICE].rlim_cur;
39490 +       if (binder_debug_mask & BINDER_DEBUG_PRIORITY_CAP)
39491 +               printk(KERN_INFO "binder: %d: nice value %ld not allowed use "
39492 +                      "%ld instead\n", current->pid, nice, min_nice);
39493 +       set_user_nice(current, min_nice);
39494 +       if (min_nice < 20)
39495 +               return;
39496 +       binder_user_error("binder: %d RLIMIT_NICE not set\n", current->pid);
39497 +}
39498 +
39499 +static size_t binder_buffer_size(
39500 +       struct binder_proc *proc, struct binder_buffer *buffer)
39501 +{
39502 +       if (list_is_last(&buffer->entry, &proc->buffers))
39503 +               return proc->buffer + proc->buffer_size - (void *)buffer->data;
39504 +       else
39505 +               return (size_t)list_entry(buffer->entry.next,
39506 +                       struct binder_buffer, entry) - (size_t)buffer->data;
39507 +}
39508 +
39509 +static void binder_insert_free_buffer(
39510 +       struct binder_proc *proc, struct binder_buffer *new_buffer)
39511 +{
39512 +       struct rb_node **p = &proc->free_buffers.rb_node;
39513 +       struct rb_node *parent = NULL;
39514 +       struct binder_buffer *buffer;
39515 +       size_t buffer_size;
39516 +       size_t new_buffer_size;
39517 +
39518 +       BUG_ON(!new_buffer->free);
39519 +
39520 +       new_buffer_size = binder_buffer_size(proc, new_buffer);
39521 +
39522 +       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
39523 +               printk(KERN_INFO "binder: %d: add free buffer, size %d, "
39524 +                      "at %p\n", proc->pid, new_buffer_size, new_buffer);
39525 +
39526 +       while (*p) {
39527 +               parent = *p;
39528 +               buffer = rb_entry(parent, struct binder_buffer, rb_node);
39529 +               BUG_ON(!buffer->free);
39530 +
39531 +               buffer_size = binder_buffer_size(proc, buffer);
39532 +
39533 +               if (new_buffer_size < buffer_size)
39534 +                       p = &parent->rb_left;
39535 +               else
39536 +                       p = &parent->rb_right;
39537 +       }
39538 +       rb_link_node(&new_buffer->rb_node, parent, p);
39539 +       rb_insert_color(&new_buffer->rb_node, &proc->free_buffers);
39540 +}
39541 +
39542 +static void binder_insert_allocated_buffer(
39543 +       struct binder_proc *proc, struct binder_buffer *new_buffer)
39544 +{
39545 +       struct rb_node **p = &proc->allocated_buffers.rb_node;
39546 +       struct rb_node *parent = NULL;
39547 +       struct binder_buffer *buffer;
39548 +
39549 +       BUG_ON(new_buffer->free);
39550 +
39551 +       while (*p) {
39552 +               parent = *p;
39553 +               buffer = rb_entry(parent, struct binder_buffer, rb_node);
39554 +               BUG_ON(buffer->free);
39555 +
39556 +               if (new_buffer < buffer)
39557 +                       p = &parent->rb_left;
39558 +               else if (new_buffer > buffer)
39559 +                       p = &parent->rb_right;
39560 +               else
39561 +                       BUG();
39562 +       }
39563 +       rb_link_node(&new_buffer->rb_node, parent, p);
39564 +       rb_insert_color(&new_buffer->rb_node, &proc->allocated_buffers);
39565 +}
39566 +
39567 +static struct binder_buffer *binder_buffer_lookup(
39568 +       struct binder_proc *proc, void __user *user_ptr)
39569 +{
39570 +       struct rb_node *n = proc->allocated_buffers.rb_node;
39571 +       struct binder_buffer *buffer;
39572 +       struct binder_buffer *kern_ptr;
39573 +
39574 +       kern_ptr = user_ptr - proc->user_buffer_offset
39575 +               - offsetof(struct binder_buffer, data);
39576 +
39577 +       while (n) {
39578 +               buffer = rb_entry(n, struct binder_buffer, rb_node);
39579 +               BUG_ON(buffer->free);
39580 +
39581 +               if (kern_ptr < buffer)
39582 +                       n = n->rb_left;
39583 +               else if (kern_ptr > buffer)
39584 +                       n = n->rb_right;
39585 +               else
39586 +                       return buffer;
39587 +       }
39588 +       return NULL;
39589 +}
39590 +
39591 +static int binder_update_page_range(struct binder_proc *proc, int allocate,
39592 +       void *start, void *end, struct vm_area_struct *vma)
39593 +{
39594 +       void *page_addr;
39595 +       unsigned long user_page_addr;
39596 +       struct vm_struct tmp_area;
39597 +       struct page **page;
39598 +       struct mm_struct *mm;
39599 +
39600 +       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
39601 +               printk(KERN_INFO "binder: %d: %s pages %p-%p\n",
39602 +                      proc->pid, allocate ? "allocate" : "free", start, end);
39603 +
39604 +       if (end <= start)
39605 +               return 0;
39606 +
39607 +       if (vma)
39608 +               mm = NULL;
39609 +       else
39610 +               mm = get_task_mm(proc->tsk);
39611 +
39612 +       if (mm) {
39613 +               down_write(&mm->mmap_sem);
39614 +               vma = proc->vma;
39615 +       }
39616 +
39617 +       if (allocate == 0)
39618 +               goto free_range;
39619 +
39620 +       if (vma == NULL) {
39621 +               printk(KERN_ERR "binder: %d: binder_alloc_buf failed to "
39622 +                      "map pages in userspace, no vma\n", proc->pid);
39623 +               goto err_no_vma;
39624 +       }
39625 +
39626 +       for (page_addr = start; page_addr < end; page_addr += PAGE_SIZE) {
39627 +               int ret;
39628 +               struct page **page_array_ptr;
39629 +               page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE];
39630 +
39631 +               BUG_ON(*page);
39632 +               *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
39633 +               if (*page == NULL) {
39634 +                       printk(KERN_ERR "binder: %d: binder_alloc_buf failed "
39635 +                              "for page at %p\n", proc->pid, page_addr);
39636 +                       goto err_alloc_page_failed;
39637 +               }
39638 +               tmp_area.addr = page_addr;
39639 +               tmp_area.size = PAGE_SIZE + PAGE_SIZE /* guard page? */;
39640 +               page_array_ptr = page;
39641 +               ret = map_vm_area(&tmp_area, PAGE_KERNEL, &page_array_ptr);
39642 +               if (ret) {
39643 +                       printk(KERN_ERR "binder: %d: binder_alloc_buf failed "
39644 +                              "to map page at %p in kernel\n",
39645 +                              proc->pid, page_addr);
39646 +                       goto err_map_kernel_failed;
39647 +               }
39648 +               user_page_addr = (size_t)page_addr + proc->user_buffer_offset;
39649 +               ret = vm_insert_page(vma, user_page_addr, page[0]);
39650 +               if (ret) {
39651 +                       printk(KERN_ERR "binder: %d: binder_alloc_buf failed "
39652 +                              "to map page at %lx in userspace\n",
39653 +                              proc->pid, user_page_addr);
39654 +                       goto err_vm_insert_page_failed;
39655 +               }
39656 +               /* vm_insert_page does not seem to increment the refcount */
39657 +       }
39658 +       if (mm) {
39659 +               up_write(&mm->mmap_sem);
39660 +               mmput(mm);
39661 +       }
39662 +       return 0;
39663 +
39664 +free_range:
39665 +       for (page_addr = end - PAGE_SIZE; page_addr >= start;
39666 +            page_addr -= PAGE_SIZE) {
39667 +               page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE];
39668 +               if (vma)
39669 +                       zap_page_range(vma, (size_t)page_addr +
39670 +                               proc->user_buffer_offset, PAGE_SIZE, NULL);
39671 +err_vm_insert_page_failed:
39672 +               unmap_kernel_range((unsigned long)page_addr, PAGE_SIZE);
39673 +err_map_kernel_failed:
39674 +               __free_page(*page);
39675 +               *page = NULL;
39676 +err_alloc_page_failed:
39677 +               ;
39678 +       }
39679 +err_no_vma:
39680 +       if (mm) {
39681 +               up_write(&mm->mmap_sem);
39682 +               mmput(mm);
39683 +       }
39684 +       return -ENOMEM;
39685 +}
39686 +
39687 +static struct binder_buffer *binder_alloc_buf(struct binder_proc *proc,
39688 +       size_t data_size, size_t offsets_size, int is_async)
39689 +{
39690 +       struct rb_node *n = proc->free_buffers.rb_node;
39691 +       struct binder_buffer *buffer;
39692 +       size_t buffer_size;
39693 +       struct rb_node *best_fit = NULL;
39694 +       void *has_page_addr;
39695 +       void *end_page_addr;
39696 +       size_t size;
39697 +
39698 +       if (proc->vma == NULL) {
39699 +               printk(KERN_ERR "binder: %d: binder_alloc_buf, no vma\n",
39700 +                      proc->pid);
39701 +               return NULL;
39702 +       }
39703 +
39704 +       size = ALIGN(data_size, sizeof(void *)) +
39705 +               ALIGN(offsets_size, sizeof(void *));
39706 +
39707 +       if (size < data_size || size < offsets_size) {
39708 +               binder_user_error("binder: %d: got transaction with invalid "
39709 +                       "size %d-%d\n", proc->pid, data_size, offsets_size);
39710 +               return NULL;
39711 +       }
39712 +
39713 +       if (is_async &&
39714 +           proc->free_async_space < size + sizeof(struct binder_buffer)) {
39715 +               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
39716 +                       printk(KERN_ERR "binder: %d: binder_alloc_buf size %d f"
39717 +                              "ailed, no async space left\n", proc->pid, size);
39718 +               return NULL;
39719 +       }
39720 +
39721 +       while (n) {
39722 +               buffer = rb_entry(n, struct binder_buffer, rb_node);
39723 +               BUG_ON(!buffer->free);
39724 +               buffer_size = binder_buffer_size(proc, buffer);
39725 +
39726 +               if (size < buffer_size) {
39727 +                       best_fit = n;
39728 +                       n = n->rb_left;
39729 +               } else if (size > buffer_size)
39730 +                       n = n->rb_right;
39731 +               else {
39732 +                       best_fit = n;
39733 +                       break;
39734 +               }
39735 +       }
39736 +       if (best_fit == NULL) {
39737 +               printk(KERN_ERR "binder: %d: binder_alloc_buf size %d failed, "
39738 +                      "no address space\n", proc->pid, size);
39739 +               return NULL;
39740 +       }
39741 +       if (n == NULL) {
39742 +               buffer = rb_entry(best_fit, struct binder_buffer, rb_node);
39743 +               buffer_size = binder_buffer_size(proc, buffer);
39744 +       }
39745 +       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
39746 +               printk(KERN_INFO "binder: %d: binder_alloc_buf size %d got buff"
39747 +                      "er %p size %d\n", proc->pid, size, buffer, buffer_size);
39748 +
39749 +       has_page_addr =
39750 +               (void *)(((size_t)buffer->data + buffer_size) & PAGE_MASK);
39751 +       if (n == NULL) {
39752 +               if (size + sizeof(struct binder_buffer) + 4 >= buffer_size)
39753 +                       buffer_size = size; /* no room for other buffers */
39754 +               else
39755 +                       buffer_size = size + sizeof(struct binder_buffer);
39756 +       }
39757 +       end_page_addr = (void *)PAGE_ALIGN((size_t)buffer->data + buffer_size);
39758 +       if (end_page_addr > has_page_addr)
39759 +               end_page_addr = has_page_addr;
39760 +       if (binder_update_page_range(proc, 1,
39761 +           (void *)PAGE_ALIGN((size_t)buffer->data), end_page_addr, NULL))
39762 +               return NULL;
39763 +
39764 +       rb_erase(best_fit, &proc->free_buffers);
39765 +       buffer->free = 0;
39766 +       binder_insert_allocated_buffer(proc, buffer);
39767 +       if (buffer_size != size) {
39768 +               struct binder_buffer *new_buffer = (void *)buffer->data + size;
39769 +               list_add(&new_buffer->entry, &buffer->entry);
39770 +               new_buffer->free = 1;
39771 +               binder_insert_free_buffer(proc, new_buffer);
39772 +       }
39773 +       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
39774 +               printk(KERN_INFO "binder: %d: binder_alloc_buf size %d got "
39775 +                      "%p\n", proc->pid, size, buffer);
39776 +       buffer->data_size = data_size;
39777 +       buffer->offsets_size = offsets_size;
39778 +       buffer->async_transaction = is_async;
39779 +       if (is_async) {
39780 +               proc->free_async_space -= size + sizeof(struct binder_buffer);
39781 +               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC_ASYNC)
39782 +                       printk(KERN_INFO "binder: %d: binder_alloc_buf size %d "
39783 +                              "async free %d\n", proc->pid, size,
39784 +                              proc->free_async_space);
39785 +       }
39786 +
39787 +       return buffer;
39788 +}
39789 +
39790 +static void *buffer_start_page(struct binder_buffer *buffer)
39791 +{
39792 +       return (void *)((size_t)buffer & PAGE_MASK);
39793 +}
39794 +
39795 +static void *buffer_end_page(struct binder_buffer *buffer)
39796 +{
39797 +       return (void *)(((size_t)(buffer + 1) - 1) & PAGE_MASK);
39798 +}
39799 +
39800 +static void binder_delete_free_buffer(
39801 +       struct binder_proc *proc, struct binder_buffer *buffer)
39802 +{
39803 +       struct binder_buffer *prev, *next = NULL;
39804 +       int free_page_end = 1;
39805 +       int free_page_start = 1;
39806 +
39807 +       BUG_ON(proc->buffers.next == &buffer->entry);
39808 +       prev = list_entry(buffer->entry.prev, struct binder_buffer, entry);
39809 +       BUG_ON(!prev->free);
39810 +       if (buffer_end_page(prev) == buffer_start_page(buffer)) {
39811 +               free_page_start = 0;
39812 +               if (buffer_end_page(prev) == buffer_end_page(buffer))
39813 +                       free_page_end = 0;
39814 +               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
39815 +                       printk(KERN_INFO "binder: %d: merge free, buffer %p "
39816 +                              "share page with %p\n", proc->pid, buffer, prev);
39817 +       }
39818 +
39819 +       if (!list_is_last(&buffer->entry, &proc->buffers)) {
39820 +               next = list_entry(buffer->entry.next,
39821 +                                 struct binder_buffer, entry);
39822 +               if (buffer_start_page(next) == buffer_end_page(buffer)) {
39823 +                       free_page_end = 0;
39824 +                       if (buffer_start_page(next) ==
39825 +                           buffer_start_page(buffer))
39826 +                               free_page_start = 0;
39827 +                       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
39828 +                               printk(KERN_INFO "binder: %d: merge free, "
39829 +                                      "buffer %p share page with %p\n",
39830 +                                      proc->pid, buffer, prev);
39831 +               }
39832 +       }
39833 +       list_del(&buffer->entry);
39834 +       if (free_page_start || free_page_end) {
39835 +               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
39836 +                       printk(KERN_INFO "binder: %d: merge free, buffer %p do "
39837 +                              "not share page%s%s with with %p or %p\n",
39838 +                              proc->pid, buffer, free_page_start ? "" : " end",
39839 +                              free_page_end ? "" : " start", prev, next);
39840 +               binder_update_page_range(proc, 0, free_page_start ?
39841 +                       buffer_start_page(buffer) : buffer_end_page(buffer),
39842 +                       (free_page_end ? buffer_end_page(buffer) :
39843 +                       buffer_start_page(buffer)) + PAGE_SIZE, NULL);
39844 +       }
39845 +}
39846 +
39847 +static void binder_free_buf(
39848 +       struct binder_proc *proc, struct binder_buffer *buffer)
39849 +{
39850 +       size_t size, buffer_size;
39851 +
39852 +       buffer_size = binder_buffer_size(proc, buffer);
39853 +
39854 +       size = ALIGN(buffer->data_size, sizeof(void *)) +
39855 +               ALIGN(buffer->offsets_size, sizeof(void *));
39856 +       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
39857 +               printk(KERN_INFO "binder: %d: binder_free_buf %p size %d buffer"
39858 +                      "_size %d\n", proc->pid, buffer, size, buffer_size);
39859 +
39860 +       BUG_ON(buffer->free);
39861 +       BUG_ON(size > buffer_size);
39862 +       BUG_ON(buffer->transaction != NULL);
39863 +       BUG_ON((void *)buffer < proc->buffer);
39864 +       BUG_ON((void *)buffer > proc->buffer + proc->buffer_size);
39865 +
39866 +       if (buffer->async_transaction) {
39867 +               proc->free_async_space += size + sizeof(struct binder_buffer);
39868 +               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC_ASYNC)
39869 +                       printk(KERN_INFO "binder: %d: binder_free_buf size %d "
39870 +                              "async free %d\n", proc->pid, size,
39871 +                              proc->free_async_space);
39872 +       }
39873 +
39874 +       binder_update_page_range(proc, 0,
39875 +               (void *)PAGE_ALIGN((size_t)buffer->data),
39876 +               (void *)(((size_t)buffer->data + buffer_size) & PAGE_MASK),
39877 +               NULL);
39878 +       rb_erase(&buffer->rb_node, &proc->allocated_buffers);
39879 +       buffer->free = 1;
39880 +       if (!list_is_last(&buffer->entry, &proc->buffers)) {
39881 +               struct binder_buffer *next = list_entry(buffer->entry.next,
39882 +                                               struct binder_buffer, entry);
39883 +               if (next->free) {
39884 +                       rb_erase(&next->rb_node, &proc->free_buffers);
39885 +                       binder_delete_free_buffer(proc, next);
39886 +               }
39887 +       }
39888 +       if (proc->buffers.next != &buffer->entry) {
39889 +               struct binder_buffer *prev = list_entry(buffer->entry.prev,
39890 +                                               struct binder_buffer, entry);
39891 +               if (prev->free) {
39892 +                       binder_delete_free_buffer(proc, buffer);
39893 +                       rb_erase(&prev->rb_node, &proc->free_buffers);
39894 +                       buffer = prev;
39895 +               }
39896 +       }
39897 +       binder_insert_free_buffer(proc, buffer);
39898 +}
39899 +
39900 +static struct binder_node *
39901 +binder_get_node(struct binder_proc *proc, void __user *ptr)
39902 +{
39903 +       struct rb_node *n = proc->nodes.rb_node;
39904 +       struct binder_node *node;
39905 +
39906 +       while (n) {
39907 +               node = rb_entry(n, struct binder_node, rb_node);
39908 +
39909 +               if (ptr < node->ptr)
39910 +                       n = n->rb_left;
39911 +               else if (ptr > node->ptr)
39912 +                       n = n->rb_right;
39913 +               else
39914 +                       return node;
39915 +       }
39916 +       return NULL;
39917 +}
39918 +
39919 +static struct binder_node *
39920 +binder_new_node(struct binder_proc *proc, void __user *ptr, void __user *cookie)
39921 +{
39922 +       struct rb_node **p = &proc->nodes.rb_node;
39923 +       struct rb_node *parent = NULL;
39924 +       struct binder_node *node;
39925 +
39926 +       while (*p) {
39927 +               parent = *p;
39928 +               node = rb_entry(parent, struct binder_node, rb_node);
39929 +
39930 +               if (ptr < node->ptr)
39931 +                       p = &(*p)->rb_left;
39932 +               else if (ptr > node->ptr)
39933 +                       p = &(*p)->rb_right;
39934 +               else
39935 +                       return NULL;
39936 +       }
39937 +
39938 +       node = kzalloc(sizeof(*node), GFP_KERNEL);
39939 +       if (node == NULL)
39940 +               return NULL;
39941 +       binder_stats.obj_created[BINDER_STAT_NODE]++;
39942 +       rb_link_node(&node->rb_node, parent, p);
39943 +       rb_insert_color(&node->rb_node, &proc->nodes);
39944 +       node->debug_id = ++binder_last_id;
39945 +       node->proc = proc;
39946 +       node->ptr = ptr;
39947 +       node->cookie = cookie;
39948 +       node->work.type = BINDER_WORK_NODE;
39949 +       INIT_LIST_HEAD(&node->work.entry);
39950 +       INIT_LIST_HEAD(&node->async_todo);
39951 +       if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
39952 +               printk(KERN_INFO "binder: %d:%d node %d u%p c%p created\n",
39953 +                      proc->pid, current->pid, node->debug_id,
39954 +                      node->ptr, node->cookie);
39955 +       return node;
39956 +}
39957 +
39958 +static int
39959 +binder_inc_node(struct binder_node *node, int strong, int internal,
39960 +               struct list_head *target_list)
39961 +{
39962 +       if (strong) {
39963 +               if (internal) {
39964 +                       if (target_list == NULL &&
39965 +                           node->internal_strong_refs == 0 &&
39966 +                           !(node == binder_context_mgr_node &&
39967 +                           node->has_strong_ref)) {
39968 +                               printk(KERN_ERR "binder: invalid inc strong "
39969 +                                       "node for %d\n", node->debug_id);
39970 +                               return -EINVAL;
39971 +                       }
39972 +                       node->internal_strong_refs++;
39973 +               } else
39974 +                       node->local_strong_refs++;
39975 +               if (!node->has_strong_ref && target_list) {
39976 +                       list_del_init(&node->work.entry);
39977 +                       list_add_tail(&node->work.entry, target_list);
39978 +               }
39979 +       } else {
39980 +               if (!internal)
39981 +                       node->local_weak_refs++;
39982 +               if (!node->has_weak_ref && list_empty(&node->work.entry)) {
39983 +                       if (target_list == NULL) {
39984 +                               printk(KERN_ERR "binder: invalid inc weak node "
39985 +                                       "for %d\n", node->debug_id);
39986 +                               return -EINVAL;
39987 +                       }
39988 +                       list_add_tail(&node->work.entry, target_list);
39989 +               }
39990 +       }
39991 +       return 0;
39992 +}
39993 +
39994 +static int
39995 +binder_dec_node(struct binder_node *node, int strong, int internal)
39996 +{
39997 +       if (strong) {
39998 +               if (internal)
39999 +                       node->internal_strong_refs--;
40000 +               else
40001 +                       node->local_strong_refs--;
40002 +               if (node->local_strong_refs || node->internal_strong_refs)
40003 +                       return 0;
40004 +       } else {
40005 +               if (!internal)
40006 +                       node->local_weak_refs--;
40007 +               if (node->local_weak_refs || !hlist_empty(&node->refs))
40008 +                       return 0;
40009 +       }
40010 +       if (node->proc && (node->has_strong_ref || node->has_weak_ref)) {
40011 +               if (list_empty(&node->work.entry)) {
40012 +                       list_add_tail(&node->work.entry, &node->proc->todo);
40013 +                       wake_up_interruptible(&node->proc->wait);
40014 +               }
40015 +       } else {
40016 +               if (hlist_empty(&node->refs) && !node->local_strong_refs &&
40017 +                   !node->local_weak_refs) {
40018 +                       list_del_init(&node->work.entry);
40019 +                       if (node->proc) {
40020 +                               rb_erase(&node->rb_node, &node->proc->nodes);
40021 +                               if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40022 +                                       printk(KERN_INFO "binder: refless node %d deleted\n", node->debug_id);
40023 +                       } else {
40024 +                               hlist_del(&node->dead_node);
40025 +                               if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40026 +                                       printk(KERN_INFO "binder: dead node %d deleted\n", node->debug_id);
40027 +                       }
40028 +                       kfree(node);
40029 +                       binder_stats.obj_deleted[BINDER_STAT_NODE]++;
40030 +               }
40031 +       }
40032 +
40033 +       return 0;
40034 +}
40035 +
40036 +
40037 +static struct binder_ref *
40038 +binder_get_ref(struct binder_proc *proc, uint32_t desc)
40039 +{
40040 +       struct rb_node *n = proc->refs_by_desc.rb_node;
40041 +       struct binder_ref *ref;
40042 +
40043 +       while (n) {
40044 +               ref = rb_entry(n, struct binder_ref, rb_node_desc);
40045 +
40046 +               if (desc < ref->desc)
40047 +                       n = n->rb_left;
40048 +               else if (desc > ref->desc)
40049 +                       n = n->rb_right;
40050 +               else
40051 +                       return ref;
40052 +       }
40053 +       return NULL;
40054 +}
40055 +
40056 +static struct binder_ref *
40057 +binder_get_ref_for_node(struct binder_proc *proc, struct binder_node *node)
40058 +{
40059 +       struct rb_node *n;
40060 +       struct rb_node **p = &proc->refs_by_node.rb_node;
40061 +       struct rb_node *parent = NULL;
40062 +       struct binder_ref *ref, *new_ref;
40063 +
40064 +       while (*p) {
40065 +               parent = *p;
40066 +               ref = rb_entry(parent, struct binder_ref, rb_node_node);
40067 +
40068 +               if (node < ref->node)
40069 +                       p = &(*p)->rb_left;
40070 +               else if (node > ref->node)
40071 +                       p = &(*p)->rb_right;
40072 +               else
40073 +                       return ref;
40074 +       }
40075 +       new_ref = kzalloc(sizeof(*ref), GFP_KERNEL);
40076 +       if (new_ref == NULL)
40077 +               return NULL;
40078 +       binder_stats.obj_created[BINDER_STAT_REF]++;
40079 +       new_ref->debug_id = ++binder_last_id;
40080 +       new_ref->proc = proc;
40081 +       new_ref->node = node;
40082 +       rb_link_node(&new_ref->rb_node_node, parent, p);
40083 +       rb_insert_color(&new_ref->rb_node_node, &proc->refs_by_node);
40084 +
40085 +       new_ref->desc = (node == binder_context_mgr_node) ? 0 : 1;
40086 +       for (n = rb_first(&proc->refs_by_desc); n != NULL; n = rb_next(n)) {
40087 +               ref = rb_entry(n, struct binder_ref, rb_node_desc);
40088 +               if (ref->desc > new_ref->desc)
40089 +                       break;
40090 +               new_ref->desc = ref->desc + 1;
40091 +       }
40092 +
40093 +       p = &proc->refs_by_desc.rb_node;
40094 +       while (*p) {
40095 +               parent = *p;
40096 +               ref = rb_entry(parent, struct binder_ref, rb_node_desc);
40097 +
40098 +               if (new_ref->desc < ref->desc)
40099 +                       p = &(*p)->rb_left;
40100 +               else if (new_ref->desc > ref->desc)
40101 +                       p = &(*p)->rb_right;
40102 +               else
40103 +                       BUG();
40104 +       }
40105 +       rb_link_node(&new_ref->rb_node_desc, parent, p);
40106 +       rb_insert_color(&new_ref->rb_node_desc, &proc->refs_by_desc);
40107 +       if (node) {
40108 +               hlist_add_head(&new_ref->node_entry, &node->refs);
40109 +               if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40110 +                       printk(KERN_INFO "binder: %d new ref %d desc %d for "
40111 +                               "node %d\n", proc->pid, new_ref->debug_id,
40112 +                               new_ref->desc, node->debug_id);
40113 +       } else {
40114 +               if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40115 +                       printk(KERN_INFO "binder: %d new ref %d desc %d for "
40116 +                               "dead node\n", proc->pid, new_ref->debug_id,
40117 +                               new_ref->desc);
40118 +       }
40119 +       return new_ref;
40120 +}
40121 +
40122 +static void
40123 +binder_delete_ref(struct binder_ref *ref)
40124 +{
40125 +       if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40126 +               printk(KERN_INFO "binder: %d delete ref %d desc %d for "
40127 +                       "node %d\n", ref->proc->pid, ref->debug_id,
40128 +                       ref->desc, ref->node->debug_id);
40129 +       rb_erase(&ref->rb_node_desc, &ref->proc->refs_by_desc);
40130 +       rb_erase(&ref->rb_node_node, &ref->proc->refs_by_node);
40131 +       if (ref->strong)
40132 +               binder_dec_node(ref->node, 1, 1);
40133 +       hlist_del(&ref->node_entry);
40134 +       binder_dec_node(ref->node, 0, 1);
40135 +       if (ref->death) {
40136 +               if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
40137 +                       printk(KERN_INFO "binder: %d delete ref %d desc %d "
40138 +                               "has death notification\n", ref->proc->pid,
40139 +                               ref->debug_id, ref->desc);
40140 +               list_del(&ref->death->work.entry);
40141 +               kfree(ref->death);
40142 +               binder_stats.obj_deleted[BINDER_STAT_DEATH]++;
40143 +       }
40144 +       kfree(ref);
40145 +       binder_stats.obj_deleted[BINDER_STAT_REF]++;
40146 +}
40147 +
40148 +static int
40149 +binder_inc_ref(
40150 +       struct binder_ref *ref, int strong, struct list_head *target_list)
40151 +{
40152 +       int ret;
40153 +       if (strong) {
40154 +               if (ref->strong == 0) {
40155 +                       ret = binder_inc_node(ref->node, 1, 1, target_list);
40156 +                       if (ret)
40157 +                               return ret;
40158 +               }
40159 +               ref->strong++;
40160 +       } else {
40161 +               if (ref->weak == 0) {
40162 +                       ret = binder_inc_node(ref->node, 0, 1, target_list);
40163 +                       if (ret)
40164 +                               return ret;
40165 +               }
40166 +               ref->weak++;
40167 +       }
40168 +       return 0;
40169 +}
40170 +
40171 +
40172 +static int
40173 +binder_dec_ref(struct binder_ref *ref, int strong)
40174 +{
40175 +       if (strong) {
40176 +               if (ref->strong == 0) {
40177 +                       binder_user_error("binder: %d invalid dec strong, "
40178 +                                         "ref %d desc %d s %d w %d\n",
40179 +                                         ref->proc->pid, ref->debug_id,
40180 +                                         ref->desc, ref->strong, ref->weak);
40181 +                       return -EINVAL;
40182 +               }
40183 +               ref->strong--;
40184 +               if (ref->strong == 0) {
40185 +                       int ret;
40186 +                       ret = binder_dec_node(ref->node, strong, 1);
40187 +                       if (ret)
40188 +                               return ret;
40189 +               }
40190 +       } else {
40191 +               if (ref->weak == 0) {
40192 +                       binder_user_error("binder: %d invalid dec weak, "
40193 +                                         "ref %d desc %d s %d w %d\n",
40194 +                                         ref->proc->pid, ref->debug_id,
40195 +                                         ref->desc, ref->strong, ref->weak);
40196 +                       return -EINVAL;
40197 +               }
40198 +               ref->weak--;
40199 +       }
40200 +       if (ref->strong == 0 && ref->weak == 0)
40201 +               binder_delete_ref(ref);
40202 +       return 0;
40203 +}
40204 +
40205 +static void
40206 +binder_pop_transaction(
40207 +       struct binder_thread *target_thread, struct binder_transaction *t)
40208 +{
40209 +       if (target_thread) {
40210 +               BUG_ON(target_thread->transaction_stack != t);
40211 +               BUG_ON(target_thread->transaction_stack->from != target_thread);
40212 +               target_thread->transaction_stack =
40213 +                       target_thread->transaction_stack->from_parent;
40214 +               t->from = NULL;
40215 +       }
40216 +       t->need_reply = 0;
40217 +       if (t->buffer)
40218 +               t->buffer->transaction = NULL;
40219 +       kfree(t);
40220 +       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION]++;
40221 +}
40222 +
40223 +static void
40224 +binder_send_failed_reply(struct binder_transaction *t, uint32_t error_code)
40225 +{
40226 +       struct binder_thread *target_thread;
40227 +       BUG_ON(t->flags & TF_ONE_WAY);
40228 +       while (1) {
40229 +               target_thread = t->from;
40230 +               if (target_thread) {
40231 +                       if (target_thread->return_error != BR_OK &&
40232 +                          target_thread->return_error2 == BR_OK) {
40233 +                               target_thread->return_error2 =
40234 +                                       target_thread->return_error;
40235 +                               target_thread->return_error = BR_OK;
40236 +                       }
40237 +                       if (target_thread->return_error == BR_OK) {
40238 +                               if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
40239 +                                       printk(KERN_INFO "binder: send failed reply for transaction %d to %d:%d\n",
40240 +                                              t->debug_id, target_thread->proc->pid, target_thread->pid);
40241 +
40242 +                               binder_pop_transaction(target_thread, t);
40243 +                               target_thread->return_error = error_code;
40244 +                               wake_up_interruptible(&target_thread->wait);
40245 +                       } else {
40246 +                               printk(KERN_ERR "binder: reply failed, target "
40247 +                                       "thread, %d:%d, has error code %d "
40248 +                                       "already\n", target_thread->proc->pid,
40249 +                                       target_thread->pid,
40250 +                                       target_thread->return_error);
40251 +                       }
40252 +                       return;
40253 +               } else {
40254 +                       struct binder_transaction *next = t->from_parent;
40255 +
40256 +                       if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
40257 +                               printk(KERN_INFO "binder: send failed reply "
40258 +                                       "for transaction %d, target dead\n",
40259 +                                       t->debug_id);
40260 +
40261 +                       binder_pop_transaction(target_thread, t);
40262 +                       if (next == NULL) {
40263 +                               if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
40264 +                                       printk(KERN_INFO "binder: reply failed,"
40265 +                                               " no target thread at root\n");
40266 +                               return;
40267 +                       }
40268 +                       t = next;
40269 +                       if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
40270 +                               printk(KERN_INFO "binder: reply failed, no targ"
40271 +                                       "et thread -- retry %d\n", t->debug_id);
40272 +               }
40273 +       }
40274 +}
40275 +
40276 +static void
40277 +binder_transaction_buffer_release(struct binder_proc *proc,
40278 +                       struct binder_buffer *buffer, size_t *failed_at);
40279 +
40280 +static void
40281 +binder_transaction(struct binder_proc *proc, struct binder_thread *thread,
40282 +       struct binder_transaction_data *tr, int reply)
40283 +{
40284 +       struct binder_transaction *t;
40285 +       struct binder_work *tcomplete;
40286 +       size_t *offp, *off_end;
40287 +       struct binder_proc *target_proc;
40288 +       struct binder_thread *target_thread = NULL;
40289 +       struct binder_node *target_node = NULL;
40290 +       struct list_head *target_list;
40291 +       wait_queue_head_t *target_wait;
40292 +       struct binder_transaction *in_reply_to = NULL;
40293 +       struct binder_transaction_log_entry *e;
40294 +       uint32_t return_error;
40295 +
40296 +       e = binder_transaction_log_add(&binder_transaction_log);
40297 +       e->call_type = reply ? 2 : !!(tr->flags & TF_ONE_WAY);
40298 +       e->from_proc = proc->pid;
40299 +       e->from_thread = thread->pid;
40300 +       e->target_handle = tr->target.handle;
40301 +       e->data_size = tr->data_size;
40302 +       e->offsets_size = tr->offsets_size;
40303 +
40304 +       if (reply) {
40305 +               in_reply_to = thread->transaction_stack;
40306 +               if (in_reply_to == NULL) {
40307 +                       binder_user_error("binder: %d:%d got reply transaction "
40308 +                                         "with no transaction stack\n",
40309 +                                         proc->pid, thread->pid);
40310 +                       return_error = BR_FAILED_REPLY;
40311 +                       goto err_empty_call_stack;
40312 +               }
40313 +               binder_set_nice(in_reply_to->saved_priority);
40314 +               if (in_reply_to->to_thread != thread) {
40315 +                       binder_user_error("binder: %d:%d got reply transaction "
40316 +                               "with bad transaction stack,"
40317 +                               " transaction %d has target %d:%d\n",
40318 +                               proc->pid, thread->pid, in_reply_to->debug_id,
40319 +                               in_reply_to->to_proc ?
40320 +                               in_reply_to->to_proc->pid : 0,
40321 +                               in_reply_to->to_thread ?
40322 +                               in_reply_to->to_thread->pid : 0);
40323 +                       return_error = BR_FAILED_REPLY;
40324 +                       in_reply_to = NULL;
40325 +                       goto err_bad_call_stack;
40326 +               }
40327 +               thread->transaction_stack = in_reply_to->to_parent;
40328 +               target_thread = in_reply_to->from;
40329 +               if (target_thread == NULL) {
40330 +                       return_error = BR_DEAD_REPLY;
40331 +                       goto err_dead_binder;
40332 +               }
40333 +               if (target_thread->transaction_stack != in_reply_to) {
40334 +                       binder_user_error("binder: %d:%d got reply transaction "
40335 +                               "with bad target transaction stack %d, "
40336 +                               "expected %d\n",
40337 +                               proc->pid, thread->pid,
40338 +                               target_thread->transaction_stack ?
40339 +                               target_thread->transaction_stack->debug_id : 0,
40340 +                               in_reply_to->debug_id);
40341 +                       return_error = BR_FAILED_REPLY;
40342 +                       in_reply_to = NULL;
40343 +                       target_thread = NULL;
40344 +                       goto err_dead_binder;
40345 +               }
40346 +               target_proc = target_thread->proc;
40347 +       } else {
40348 +               if (tr->target.handle) {
40349 +                       struct binder_ref *ref;
40350 +                       ref = binder_get_ref(proc, tr->target.handle);
40351 +                       if (ref == NULL) {
40352 +                               binder_user_error("binder: %d:%d got "
40353 +                                       "transaction to invalid handle\n",
40354 +                                       proc->pid, thread->pid);
40355 +                               return_error = BR_FAILED_REPLY;
40356 +                               goto err_invalid_target_handle;
40357 +                       }
40358 +                       target_node = ref->node;
40359 +               } else {
40360 +                       target_node = binder_context_mgr_node;
40361 +                       if (target_node == NULL) {
40362 +                               return_error = BR_DEAD_REPLY;
40363 +                               goto err_no_context_mgr_node;
40364 +                       }
40365 +               }
40366 +               e->to_node = target_node->debug_id;
40367 +               target_proc = target_node->proc;
40368 +               if (target_proc == NULL) {
40369 +                       return_error = BR_DEAD_REPLY;
40370 +                       goto err_dead_binder;
40371 +               }
40372 +               if (!(tr->flags & TF_ONE_WAY) && thread->transaction_stack) {
40373 +                       struct binder_transaction *tmp;
40374 +                       tmp = thread->transaction_stack;
40375 +                       while (tmp) {
40376 +                               if (tmp->from && tmp->from->proc == target_proc)
40377 +                                       target_thread = tmp->from;
40378 +                               tmp = tmp->from_parent;
40379 +                       }
40380 +               }
40381 +       }
40382 +       if (target_thread) {
40383 +               e->to_thread = target_thread->pid;
40384 +               target_list = &target_thread->todo;
40385 +               target_wait = &target_thread->wait;
40386 +       } else {
40387 +               target_list = &target_proc->todo;
40388 +               target_wait = &target_proc->wait;
40389 +       }
40390 +       e->to_proc = target_proc->pid;
40391 +
40392 +       /* TODO: reuse incoming transaction for reply */
40393 +       t = kzalloc(sizeof(*t), GFP_KERNEL);
40394 +       if (t == NULL) {
40395 +               return_error = BR_FAILED_REPLY;
40396 +               goto err_alloc_t_failed;
40397 +       }
40398 +       binder_stats.obj_created[BINDER_STAT_TRANSACTION]++;
40399 +
40400 +       tcomplete = kzalloc(sizeof(*tcomplete), GFP_KERNEL);
40401 +       if (tcomplete == NULL) {
40402 +               return_error = BR_FAILED_REPLY;
40403 +               goto err_alloc_tcomplete_failed;
40404 +       }
40405 +       binder_stats.obj_created[BINDER_STAT_TRANSACTION_COMPLETE]++;
40406 +
40407 +       t->debug_id = ++binder_last_id;
40408 +       e->debug_id = t->debug_id;
40409 +
40410 +       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION) {
40411 +               if (reply)
40412 +                       printk(KERN_INFO "binder: %d:%d BC_REPLY %d -> %d:%d, "
40413 +                              "data %p-%p size %d-%d\n",
40414 +                              proc->pid, thread->pid, t->debug_id,
40415 +                              target_proc->pid, target_thread->pid,
40416 +                              tr->data.ptr.buffer, tr->data.ptr.offsets,
40417 +                              tr->data_size, tr->offsets_size);
40418 +               else
40419 +                       printk(KERN_INFO "binder: %d:%d BC_TRANSACTION %d -> "
40420 +                              "%d - node %d, data %p-%p size %d-%d\n",
40421 +                              proc->pid, thread->pid, t->debug_id,
40422 +                              target_proc->pid, target_node->debug_id,
40423 +                              tr->data.ptr.buffer, tr->data.ptr.offsets,
40424 +                              tr->data_size, tr->offsets_size);
40425 +       }
40426 +
40427 +       if (!reply && !(tr->flags & TF_ONE_WAY))
40428 +               t->from = thread;
40429 +       else
40430 +               t->from = NULL;
40431 +       t->sender_euid = proc->tsk->euid;
40432 +       t->to_proc = target_proc;
40433 +       t->to_thread = target_thread;
40434 +       t->code = tr->code;
40435 +       t->flags = tr->flags;
40436 +       t->priority = task_nice(current);
40437 +       t->buffer = binder_alloc_buf(target_proc, tr->data_size,
40438 +               tr->offsets_size, !reply && (t->flags & TF_ONE_WAY));
40439 +       if (t->buffer == NULL) {
40440 +               return_error = BR_FAILED_REPLY;
40441 +               goto err_binder_alloc_buf_failed;
40442 +       }
40443 +       t->buffer->allow_user_free = 0;
40444 +       t->buffer->debug_id = t->debug_id;
40445 +       t->buffer->transaction = t;
40446 +       t->buffer->target_node = target_node;
40447 +       if (target_node)
40448 +               binder_inc_node(target_node, 1, 0, NULL);
40449 +
40450 +       offp = (size_t *)(t->buffer->data + ALIGN(tr->data_size, sizeof(void *)));
40451 +
40452 +       if (copy_from_user(t->buffer->data, tr->data.ptr.buffer, tr->data_size)) {
40453 +               binder_user_error("binder: %d:%d got transaction with invalid "
40454 +                       "data ptr\n", proc->pid, thread->pid);
40455 +               return_error = BR_FAILED_REPLY;
40456 +               goto err_copy_data_failed;
40457 +       }
40458 +       if (copy_from_user(offp, tr->data.ptr.offsets, tr->offsets_size)) {
40459 +               binder_user_error("binder: %d:%d got transaction with invalid "
40460 +                       "offsets ptr\n", proc->pid, thread->pid);
40461 +               return_error = BR_FAILED_REPLY;
40462 +               goto err_copy_data_failed;
40463 +       }
40464 +       off_end = (void *)offp + tr->offsets_size;
40465 +       for (; offp < off_end; offp++) {
40466 +               struct flat_binder_object *fp;
40467 +               if (*offp > t->buffer->data_size - sizeof(*fp)) {
40468 +                       binder_user_error("binder: %d:%d got transaction with "
40469 +                               "invalid offset, %d\n",
40470 +                               proc->pid, thread->pid, *offp);
40471 +                       return_error = BR_FAILED_REPLY;
40472 +                       goto err_bad_offset;
40473 +               }
40474 +               fp = (struct flat_binder_object *)(t->buffer->data + *offp);
40475 +               switch (fp->type) {
40476 +               case BINDER_TYPE_BINDER:
40477 +               case BINDER_TYPE_WEAK_BINDER: {
40478 +                       struct binder_ref *ref;
40479 +                       struct binder_node *node = binder_get_node(proc, fp->binder);
40480 +                       if (node == NULL) {
40481 +                               node = binder_new_node(proc, fp->binder, fp->cookie);
40482 +                               if (node == NULL) {
40483 +                                       return_error = BR_FAILED_REPLY;
40484 +                                       goto err_binder_new_node_failed;
40485 +                               }
40486 +                               node->min_priority = fp->flags & FLAT_BINDER_FLAG_PRIORITY_MASK;
40487 +                               node->accept_fds = !!(fp->flags & FLAT_BINDER_FLAG_ACCEPTS_FDS);
40488 +                       }
40489 +                       if (fp->cookie != node->cookie) {
40490 +                               binder_user_error("binder: %d:%d sending u%p "
40491 +                                       "node %d, cookie mismatch %p != %p\n",
40492 +                                       proc->pid, thread->pid,
40493 +                                       fp->binder, node->debug_id,
40494 +                                       fp->cookie, node->cookie);
40495 +                               goto err_binder_get_ref_for_node_failed;
40496 +                       }
40497 +                       ref = binder_get_ref_for_node(target_proc, node);
40498 +                       if (ref == NULL) {
40499 +                               return_error = BR_FAILED_REPLY;
40500 +                               goto err_binder_get_ref_for_node_failed;
40501 +                       }
40502 +                       if (fp->type == BINDER_TYPE_BINDER)
40503 +                               fp->type = BINDER_TYPE_HANDLE;
40504 +                       else
40505 +                               fp->type = BINDER_TYPE_WEAK_HANDLE;
40506 +                       fp->handle = ref->desc;
40507 +                       binder_inc_ref(ref, fp->type == BINDER_TYPE_HANDLE, &thread->todo);
40508 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
40509 +                               printk(KERN_INFO "        node %d u%p -> ref %d desc %d\n",
40510 +                                      node->debug_id, node->ptr, ref->debug_id, ref->desc);
40511 +               } break;
40512 +               case BINDER_TYPE_HANDLE:
40513 +               case BINDER_TYPE_WEAK_HANDLE: {
40514 +                       struct binder_ref *ref = binder_get_ref(proc, fp->handle);
40515 +                       if (ref == NULL) {
40516 +                               binder_user_error("binder: %d:%d got "
40517 +                                       "transaction with invalid "
40518 +                                       "handle, %ld\n", proc->pid,
40519 +                                       thread->pid, fp->handle);
40520 +                               return_error = BR_FAILED_REPLY;
40521 +                               goto err_binder_get_ref_failed;
40522 +                       }
40523 +                       if (ref->node->proc == target_proc) {
40524 +                               if (fp->type == BINDER_TYPE_HANDLE)
40525 +                                       fp->type = BINDER_TYPE_BINDER;
40526 +                               else
40527 +                                       fp->type = BINDER_TYPE_WEAK_BINDER;
40528 +                               fp->binder = ref->node->ptr;
40529 +                               fp->cookie = ref->node->cookie;
40530 +                               binder_inc_node(ref->node, fp->type == BINDER_TYPE_BINDER, 0, NULL);
40531 +                               if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
40532 +                                       printk(KERN_INFO "        ref %d desc %d -> node %d u%p\n",
40533 +                                              ref->debug_id, ref->desc, ref->node->debug_id, ref->node->ptr);
40534 +                       } else {
40535 +                               struct binder_ref *new_ref;
40536 +                               new_ref = binder_get_ref_for_node(target_proc, ref->node);
40537 +                               if (new_ref == NULL) {
40538 +                                       return_error = BR_FAILED_REPLY;
40539 +                                       goto err_binder_get_ref_for_node_failed;
40540 +                               }
40541 +                               fp->handle = new_ref->desc;
40542 +                               binder_inc_ref(new_ref, fp->type == BINDER_TYPE_HANDLE, NULL);
40543 +                               if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
40544 +                                       printk(KERN_INFO "        ref %d desc %d -> ref %d desc %d (node %d)\n",
40545 +                                              ref->debug_id, ref->desc, new_ref->debug_id, new_ref->desc, ref->node->debug_id);
40546 +                       }
40547 +               } break;
40548 +
40549 +               case BINDER_TYPE_FD: {
40550 +                       int target_fd;
40551 +                       struct file *file;
40552 +
40553 +                       if (reply) {
40554 +                               if (!(in_reply_to->flags & TF_ACCEPT_FDS)) {
40555 +                                       binder_user_error("binder: %d:%d got reply with fd, %ld, but target does not allow fds\n",
40556 +                                               proc->pid, thread->pid, fp->handle);
40557 +                                       return_error = BR_FAILED_REPLY;
40558 +                                       goto err_fd_not_allowed;
40559 +                               }
40560 +                       } else if (!target_node->accept_fds) {
40561 +                               binder_user_error("binder: %d:%d got transaction with fd, %ld, but target does not allow fds\n",
40562 +                                       proc->pid, thread->pid, fp->handle);
40563 +                               return_error = BR_FAILED_REPLY;
40564 +                               goto err_fd_not_allowed;
40565 +                       }
40566 +
40567 +                       file = fget(fp->handle);
40568 +                       if (file == NULL) {
40569 +                               binder_user_error("binder: %d:%d got transaction with invalid fd, %ld\n",
40570 +                                       proc->pid, thread->pid, fp->handle);
40571 +                               return_error = BR_FAILED_REPLY;
40572 +                               goto err_fget_failed;
40573 +                       }
40574 +                       target_fd = task_get_unused_fd_flags(target_proc->tsk, O_CLOEXEC);
40575 +                       if (target_fd < 0) {
40576 +                               fput(file);
40577 +                               return_error = BR_FAILED_REPLY;
40578 +                               goto err_get_unused_fd_failed;
40579 +                       }
40580 +                       task_fd_install(target_proc->tsk, target_fd, file);
40581 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
40582 +                               printk(KERN_INFO "        fd %ld -> %d\n", fp->handle, target_fd);
40583 +                       /* TODO: fput? */
40584 +                       fp->handle = target_fd;
40585 +               } break;
40586 +
40587 +               default:
40588 +                       binder_user_error("binder: %d:%d got transactio"
40589 +                               "n with invalid object type, %lx\n",
40590 +                               proc->pid, thread->pid, fp->type);
40591 +                       return_error = BR_FAILED_REPLY;
40592 +                       goto err_bad_object_type;
40593 +               }
40594 +       }
40595 +       if (reply) {
40596 +               BUG_ON(t->buffer->async_transaction != 0);
40597 +               binder_pop_transaction(target_thread, in_reply_to);
40598 +       } else if (!(t->flags & TF_ONE_WAY)) {
40599 +               BUG_ON(t->buffer->async_transaction != 0);
40600 +               t->need_reply = 1;
40601 +               t->from_parent = thread->transaction_stack;
40602 +               thread->transaction_stack = t;
40603 +       } else {
40604 +               BUG_ON(target_node == NULL);
40605 +               BUG_ON(t->buffer->async_transaction != 1);
40606 +               if (target_node->has_async_transaction) {
40607 +                       target_list = &target_node->async_todo;
40608 +                       target_wait = NULL;
40609 +               } else
40610 +                       target_node->has_async_transaction = 1;
40611 +       }
40612 +       t->work.type = BINDER_WORK_TRANSACTION;
40613 +       list_add_tail(&t->work.entry, target_list);
40614 +       tcomplete->type = BINDER_WORK_TRANSACTION_COMPLETE;
40615 +       list_add_tail(&tcomplete->entry, &thread->todo);
40616 +       if (target_wait)
40617 +               wake_up_interruptible(target_wait);
40618 +       return;
40619 +
40620 +err_get_unused_fd_failed:
40621 +err_fget_failed:
40622 +err_fd_not_allowed:
40623 +err_binder_get_ref_for_node_failed:
40624 +err_binder_get_ref_failed:
40625 +err_binder_new_node_failed:
40626 +err_bad_object_type:
40627 +err_bad_offset:
40628 +err_copy_data_failed:
40629 +       binder_transaction_buffer_release(target_proc, t->buffer, offp);
40630 +       t->buffer->transaction = NULL;
40631 +       binder_free_buf(target_proc, t->buffer);
40632 +err_binder_alloc_buf_failed:
40633 +       kfree(tcomplete);
40634 +       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION_COMPLETE]++;
40635 +err_alloc_tcomplete_failed:
40636 +       kfree(t);
40637 +       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION]++;
40638 +err_alloc_t_failed:
40639 +err_bad_call_stack:
40640 +err_empty_call_stack:
40641 +err_dead_binder:
40642 +err_invalid_target_handle:
40643 +err_no_context_mgr_node:
40644 +       if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
40645 +               printk(KERN_INFO "binder: %d:%d transaction failed %d, size %d-%d\n",
40646 +                          proc->pid, thread->pid, return_error,
40647 +                          tr->data_size, tr->offsets_size);
40648 +
40649 +       {
40650 +               struct binder_transaction_log_entry *fe;
40651 +               fe = binder_transaction_log_add(&binder_transaction_log_failed);
40652 +               *fe = *e;
40653 +       }
40654 +
40655 +       BUG_ON(thread->return_error != BR_OK);
40656 +       if (in_reply_to) {
40657 +               thread->return_error = BR_TRANSACTION_COMPLETE;
40658 +               binder_send_failed_reply(in_reply_to, return_error);
40659 +       } else
40660 +               thread->return_error = return_error;
40661 +}
40662 +
40663 +static void
40664 +binder_transaction_buffer_release(struct binder_proc *proc, struct binder_buffer *buffer, size_t *failed_at)
40665 +{
40666 +       size_t *offp, *off_end;
40667 +       int debug_id = buffer->debug_id;
40668 +
40669 +       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
40670 +               printk(KERN_INFO "binder: %d buffer release %d, size %d-%d, failed at %p\n",
40671 +                          proc->pid, buffer->debug_id,
40672 +                          buffer->data_size, buffer->offsets_size, failed_at);
40673 +
40674 +       if (buffer->target_node)
40675 +               binder_dec_node(buffer->target_node, 1, 0);
40676 +
40677 +       offp = (size_t *)(buffer->data + ALIGN(buffer->data_size, sizeof(void *)));
40678 +       if (failed_at)
40679 +               off_end = failed_at;
40680 +       else
40681 +               off_end = (void *)offp + buffer->offsets_size;
40682 +       for (; offp < off_end; offp++) {
40683 +               struct flat_binder_object *fp;
40684 +               if (*offp > buffer->data_size - sizeof(*fp)) {
40685 +                       printk(KERN_ERR "binder: transaction release %d bad offset %d, size %d\n", debug_id, *offp, buffer->data_size);
40686 +                       continue;
40687 +               }
40688 +               fp = (struct flat_binder_object *)(buffer->data + *offp);
40689 +               switch (fp->type) {
40690 +               case BINDER_TYPE_BINDER:
40691 +               case BINDER_TYPE_WEAK_BINDER: {
40692 +                       struct binder_node *node = binder_get_node(proc, fp->binder);
40693 +                       if (node == NULL) {
40694 +                               printk(KERN_ERR "binder: transaction release %d bad node %p\n", debug_id, fp->binder);
40695 +                               break;
40696 +                       }
40697 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
40698 +                               printk(KERN_INFO "        node %d u%p\n",
40699 +                                      node->debug_id, node->ptr);
40700 +                       binder_dec_node(node, fp->type == BINDER_TYPE_BINDER, 0);
40701 +               } break;
40702 +               case BINDER_TYPE_HANDLE:
40703 +               case BINDER_TYPE_WEAK_HANDLE: {
40704 +                       struct binder_ref *ref = binder_get_ref(proc, fp->handle);
40705 +                       if (ref == NULL) {
40706 +                               printk(KERN_ERR "binder: transaction release %d bad handle %ld\n", debug_id, fp->handle);
40707 +                               break;
40708 +                       }
40709 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
40710 +                               printk(KERN_INFO "        ref %d desc %d (node %d)\n",
40711 +                                      ref->debug_id, ref->desc, ref->node->debug_id);
40712 +                       binder_dec_ref(ref, fp->type == BINDER_TYPE_HANDLE);
40713 +               } break;
40714 +
40715 +               case BINDER_TYPE_FD:
40716 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
40717 +                               printk(KERN_INFO "        fd %ld\n", fp->handle);
40718 +                       if (failed_at)
40719 +                               task_close_fd(proc->tsk, fp->handle);
40720 +                       break;
40721 +
40722 +               default:
40723 +                       printk(KERN_ERR "binder: transaction release %d bad object type %lx\n", debug_id, fp->type);
40724 +                       break;
40725 +               }
40726 +       }
40727 +}
40728 +
40729 +int
40730 +binder_thread_write(struct binder_proc *proc, struct binder_thread *thread,
40731 +                   void __user *buffer, int size, signed long *consumed)
40732 +{
40733 +       uint32_t cmd;
40734 +       void __user *ptr = buffer + *consumed;
40735 +       void __user *end = buffer + size;
40736 +
40737 +       while (ptr < end && thread->return_error == BR_OK) {
40738 +               if (get_user(cmd, (uint32_t __user *)ptr))
40739 +                       return -EFAULT;
40740 +               ptr += sizeof(uint32_t);
40741 +               if (_IOC_NR(cmd) < ARRAY_SIZE(binder_stats.bc)) {
40742 +                       binder_stats.bc[_IOC_NR(cmd)]++;
40743 +                       proc->stats.bc[_IOC_NR(cmd)]++;
40744 +                       thread->stats.bc[_IOC_NR(cmd)]++;
40745 +               }
40746 +               switch (cmd) {
40747 +               case BC_INCREFS:
40748 +               case BC_ACQUIRE:
40749 +               case BC_RELEASE:
40750 +               case BC_DECREFS: {
40751 +                       uint32_t target;
40752 +                       struct binder_ref *ref;
40753 +                       const char *debug_string;
40754 +
40755 +                       if (get_user(target, (uint32_t __user *)ptr))
40756 +                               return -EFAULT;
40757 +                       ptr += sizeof(uint32_t);
40758 +                       if (target == 0 && binder_context_mgr_node &&
40759 +                           (cmd == BC_INCREFS || cmd == BC_ACQUIRE)) {
40760 +                               ref = binder_get_ref_for_node(proc,
40761 +                                              binder_context_mgr_node);
40762 +                               if (ref->desc != target) {
40763 +                                       binder_user_error("binder: %d:"
40764 +                                               "%d tried to acquire "
40765 +                                               "reference to desc 0, "
40766 +                                               "got %d instead\n",
40767 +                                               proc->pid, thread->pid,
40768 +                                               ref->desc);
40769 +                               }
40770 +                       } else
40771 +                               ref = binder_get_ref(proc, target);
40772 +                       if (ref == NULL) {
40773 +                               binder_user_error("binder: %d:%d refcou"
40774 +                                       "nt change on invalid ref %d\n",
40775 +                                       proc->pid, thread->pid, target);
40776 +                               break;
40777 +                       }
40778 +                       switch (cmd) {
40779 +                       case BC_INCREFS:
40780 +                               debug_string = "IncRefs";
40781 +                               binder_inc_ref(ref, 0, NULL);
40782 +                               break;
40783 +                       case BC_ACQUIRE:
40784 +                               debug_string = "Acquire";
40785 +                               binder_inc_ref(ref, 1, NULL);
40786 +                               break;
40787 +                       case BC_RELEASE:
40788 +                               debug_string = "Release";
40789 +                               binder_dec_ref(ref, 1);
40790 +                               break;
40791 +                       case BC_DECREFS:
40792 +                       default:
40793 +                               debug_string = "DecRefs";
40794 +                               binder_dec_ref(ref, 0);
40795 +                               break;
40796 +                       }
40797 +                       if (binder_debug_mask & BINDER_DEBUG_USER_REFS)
40798 +                               printk(KERN_INFO "binder: %d:%d %s ref %d desc %d s %d w %d for node %d\n",
40799 +                                      proc->pid, thread->pid, debug_string, ref->debug_id, ref->desc, ref->strong, ref->weak, ref->node->debug_id);
40800 +                       break;
40801 +               }
40802 +               case BC_INCREFS_DONE:
40803 +               case BC_ACQUIRE_DONE: {
40804 +                       void __user *node_ptr;
40805 +                       void *cookie;
40806 +                       struct binder_node *node;
40807 +
40808 +                       if (get_user(node_ptr, (void * __user *)ptr))
40809 +                               return -EFAULT;
40810 +                       ptr += sizeof(void *);
40811 +                       if (get_user(cookie, (void * __user *)ptr))
40812 +                               return -EFAULT;
40813 +                       ptr += sizeof(void *);
40814 +                       node = binder_get_node(proc, node_ptr);
40815 +                       if (node == NULL) {
40816 +                               binder_user_error("binder: %d:%d "
40817 +                                       "%s u%p no match\n",
40818 +                                       proc->pid, thread->pid,
40819 +                                       cmd == BC_INCREFS_DONE ?
40820 +                                       "BC_INCREFS_DONE" :
40821 +                                       "BC_ACQUIRE_DONE",
40822 +                                       node_ptr);
40823 +                               break;
40824 +                       }
40825 +                       if (cookie != node->cookie) {
40826 +                               binder_user_error("binder: %d:%d %s u%p node %d"
40827 +                                       " cookie mismatch %p != %p\n",
40828 +                                       proc->pid, thread->pid,
40829 +                                       cmd == BC_INCREFS_DONE ?
40830 +                                       "BC_INCREFS_DONE" : "BC_ACQUIRE_DONE",
40831 +                                       node_ptr, node->debug_id,
40832 +                                       cookie, node->cookie);
40833 +                               break;
40834 +                       }
40835 +                       if (cmd == BC_ACQUIRE_DONE) {
40836 +                               if (node->pending_strong_ref == 0) {
40837 +                                       binder_user_error("binder: %d:%d "
40838 +                                               "BC_ACQUIRE_DONE node %d has "
40839 +                                               "no pending acquire request\n",
40840 +                                               proc->pid, thread->pid,
40841 +                                               node->debug_id);
40842 +                                       break;
40843 +                               }
40844 +                               node->pending_strong_ref = 0;
40845 +                       } else {
40846 +                               if (node->pending_weak_ref == 0) {
40847 +                                       binder_user_error("binder: %d:%d "
40848 +                                               "BC_INCREFS_DONE node %d has "
40849 +                                               "no pending increfs request\n",
40850 +                                               proc->pid, thread->pid,
40851 +                                               node->debug_id);
40852 +                                       break;
40853 +                               }
40854 +                               node->pending_weak_ref = 0;
40855 +                       }
40856 +                       binder_dec_node(node, cmd == BC_ACQUIRE_DONE, 0);
40857 +                       if (binder_debug_mask & BINDER_DEBUG_USER_REFS)
40858 +                               printk(KERN_INFO "binder: %d:%d %s node %d ls %d lw %d\n",
40859 +                                      proc->pid, thread->pid, cmd == BC_INCREFS_DONE ? "BC_INCREFS_DONE" : "BC_ACQUIRE_DONE", node->debug_id, node->local_strong_refs, node->local_weak_refs);
40860 +                       break;
40861 +               }
40862 +               case BC_ATTEMPT_ACQUIRE:
40863 +                       printk(KERN_ERR "binder: BC_ATTEMPT_ACQUIRE not supported\n");
40864 +                       return -EINVAL;
40865 +               case BC_ACQUIRE_RESULT:
40866 +                       printk(KERN_ERR "binder: BC_ACQUIRE_RESULT not supported\n");
40867 +                       return -EINVAL;
40868 +
40869 +               case BC_FREE_BUFFER: {
40870 +                       void __user *data_ptr;
40871 +                       struct binder_buffer *buffer;
40872 +
40873 +                       if (get_user(data_ptr, (void * __user *)ptr))
40874 +                               return -EFAULT;
40875 +                       ptr += sizeof(void *);
40876 +
40877 +                       buffer = binder_buffer_lookup(proc, data_ptr);
40878 +                       if (buffer == NULL) {
40879 +                               binder_user_error("binder: %d:%d "
40880 +                                       "BC_FREE_BUFFER u%p no match\n",
40881 +                                       proc->pid, thread->pid, data_ptr);
40882 +                               break;
40883 +                       }
40884 +                       if (!buffer->allow_user_free) {
40885 +                               binder_user_error("binder: %d:%d "
40886 +                                       "BC_FREE_BUFFER u%p matched "
40887 +                                       "unreturned buffer\n",
40888 +                                       proc->pid, thread->pid, data_ptr);
40889 +                               break;
40890 +                       }
40891 +                       if (binder_debug_mask & BINDER_DEBUG_FREE_BUFFER)
40892 +                               printk(KERN_INFO "binder: %d:%d BC_FREE_BUFFER u%p found buffer %d for %s transaction\n",
40893 +                                      proc->pid, thread->pid, data_ptr, buffer->debug_id,
40894 +                                      buffer->transaction ? "active" : "finished");
40895 +
40896 +                       if (buffer->transaction) {
40897 +                               buffer->transaction->buffer = NULL;
40898 +                               buffer->transaction = NULL;
40899 +                       }
40900 +                       if (buffer->async_transaction && buffer->target_node) {
40901 +                               BUG_ON(!buffer->target_node->has_async_transaction);
40902 +                               if (list_empty(&buffer->target_node->async_todo))
40903 +                                       buffer->target_node->has_async_transaction = 0;
40904 +                               else
40905 +                                       list_move_tail(buffer->target_node->async_todo.next, &thread->todo);
40906 +                       }
40907 +                       binder_transaction_buffer_release(proc, buffer, NULL);
40908 +                       binder_free_buf(proc, buffer);
40909 +                       break;
40910 +               }
40911 +
40912 +               case BC_TRANSACTION:
40913 +               case BC_REPLY: {
40914 +                       struct binder_transaction_data tr;
40915 +
40916 +                       if (copy_from_user(&tr, ptr, sizeof(tr)))
40917 +                               return -EFAULT;
40918 +                       ptr += sizeof(tr);
40919 +                       binder_transaction(proc, thread, &tr, cmd == BC_REPLY);
40920 +                       break;
40921 +               }
40922 +
40923 +               case BC_REGISTER_LOOPER:
40924 +                       if (binder_debug_mask & BINDER_DEBUG_THREADS)
40925 +                               printk(KERN_INFO "binder: %d:%d BC_REGISTER_LOOPER\n",
40926 +                                      proc->pid, thread->pid);
40927 +                       if (thread->looper & BINDER_LOOPER_STATE_ENTERED) {
40928 +                               thread->looper |= BINDER_LOOPER_STATE_INVALID;
40929 +                               binder_user_error("binder: %d:%d ERROR:"
40930 +                                       " BC_REGISTER_LOOPER called "
40931 +                                       "after BC_ENTER_LOOPER\n",
40932 +                                       proc->pid, thread->pid);
40933 +                       } else if (proc->requested_threads == 0) {
40934 +                               thread->looper |= BINDER_LOOPER_STATE_INVALID;
40935 +                               binder_user_error("binder: %d:%d ERROR:"
40936 +                                       " BC_REGISTER_LOOPER called "
40937 +                                       "without request\n",
40938 +                                       proc->pid, thread->pid);
40939 +                       } else {
40940 +                               proc->requested_threads--;
40941 +                               proc->requested_threads_started++;
40942 +                       }
40943 +                       thread->looper |= BINDER_LOOPER_STATE_REGISTERED;
40944 +                       break;
40945 +               case BC_ENTER_LOOPER:
40946 +                       if (binder_debug_mask & BINDER_DEBUG_THREADS)
40947 +                               printk(KERN_INFO "binder: %d:%d BC_ENTER_LOOPER\n",
40948 +                                      proc->pid, thread->pid);
40949 +                       if (thread->looper & BINDER_LOOPER_STATE_REGISTERED) {
40950 +                               thread->looper |= BINDER_LOOPER_STATE_INVALID;
40951 +                               binder_user_error("binder: %d:%d ERROR:"
40952 +                                       " BC_ENTER_LOOPER called after "
40953 +                                       "BC_REGISTER_LOOPER\n",
40954 +                                       proc->pid, thread->pid);
40955 +                       }
40956 +                       thread->looper |= BINDER_LOOPER_STATE_ENTERED;
40957 +                       break;
40958 +               case BC_EXIT_LOOPER:
40959 +                       if (binder_debug_mask & BINDER_DEBUG_THREADS)
40960 +                               printk(KERN_INFO "binder: %d:%d BC_EXIT_LOOPER\n",
40961 +                                      proc->pid, thread->pid);
40962 +                       thread->looper |= BINDER_LOOPER_STATE_EXITED;
40963 +                       break;
40964 +
40965 +               case BC_REQUEST_DEATH_NOTIFICATION:
40966 +               case BC_CLEAR_DEATH_NOTIFICATION: {
40967 +                       uint32_t target;
40968 +                       void __user *cookie;
40969 +                       struct binder_ref *ref;
40970 +                       struct binder_ref_death *death;
40971 +
40972 +                       if (get_user(target, (uint32_t __user *)ptr))
40973 +                               return -EFAULT;
40974 +                       ptr += sizeof(uint32_t);
40975 +                       if (get_user(cookie, (void __user * __user *)ptr))
40976 +                               return -EFAULT;
40977 +                       ptr += sizeof(void *);
40978 +                       ref = binder_get_ref(proc, target);
40979 +                       if (ref == NULL) {
40980 +                               binder_user_error("binder: %d:%d %s "
40981 +                                       "invalid ref %d\n",
40982 +                                       proc->pid, thread->pid,
40983 +                                       cmd == BC_REQUEST_DEATH_NOTIFICATION ?
40984 +                                       "BC_REQUEST_DEATH_NOTIFICATION" :
40985 +                                       "BC_CLEAR_DEATH_NOTIFICATION",
40986 +                                       target);
40987 +                               break;
40988 +                       }
40989 +
40990 +                       if (binder_debug_mask & BINDER_DEBUG_DEATH_NOTIFICATION)
40991 +                               printk(KERN_INFO "binder: %d:%d %s %p ref %d desc %d s %d w %d for node %d\n",
40992 +                                      proc->pid, thread->pid,
40993 +                                      cmd == BC_REQUEST_DEATH_NOTIFICATION ?
40994 +                                      "BC_REQUEST_DEATH_NOTIFICATION" :
40995 +                                      "BC_CLEAR_DEATH_NOTIFICATION",
40996 +                                      cookie, ref->debug_id, ref->desc,
40997 +                                      ref->strong, ref->weak, ref->node->debug_id);
40998 +
40999 +                       if (cmd == BC_REQUEST_DEATH_NOTIFICATION) {
41000 +                               if (ref->death) {
41001 +                                       binder_user_error("binder: %d:%"
41002 +                                               "d BC_REQUEST_DEATH_NOTI"
41003 +                                               "FICATION death notific"
41004 +                                               "ation already set\n",
41005 +                                               proc->pid, thread->pid);
41006 +                                       break;
41007 +                               }
41008 +                               death = kzalloc(sizeof(*death), GFP_KERNEL);
41009 +                               if (death == NULL) {
41010 +                                       thread->return_error = BR_ERROR;
41011 +                                       if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
41012 +                                               printk(KERN_INFO "binder: %d:%d "
41013 +                                                       "BC_REQUEST_DEATH_NOTIFICATION failed\n",
41014 +                                                       proc->pid, thread->pid);
41015 +                                       break;
41016 +                               }
41017 +                               binder_stats.obj_created[BINDER_STAT_DEATH]++;
41018 +                               INIT_LIST_HEAD(&death->work.entry);
41019 +                               death->cookie = cookie;
41020 +                               ref->death = death;
41021 +                               if (ref->node->proc == NULL) {
41022 +                                       ref->death->work.type = BINDER_WORK_DEAD_BINDER;
41023 +                                       if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) {
41024 +                                               list_add_tail(&ref->death->work.entry, &thread->todo);
41025 +                                       } else {
41026 +                                               list_add_tail(&ref->death->work.entry, &proc->todo);
41027 +                                               wake_up_interruptible(&proc->wait);
41028 +                                       }
41029 +                               }
41030 +                       } else {
41031 +                               if (ref->death == NULL) {
41032 +                                       binder_user_error("binder: %d:%"
41033 +                                               "d BC_CLEAR_DEATH_NOTIFI"
41034 +                                               "CATION death notificat"
41035 +                                               "ion not active\n",
41036 +                                               proc->pid, thread->pid);
41037 +                                       break;
41038 +                               }
41039 +                               death = ref->death;
41040 +                               if (death->cookie != cookie) {
41041 +                                       binder_user_error("binder: %d:%"
41042 +                                               "d BC_CLEAR_DEATH_NOTIFI"
41043 +                                               "CATION death notificat"
41044 +                                               "ion cookie mismatch "
41045 +                                               "%p != %p\n",
41046 +                                               proc->pid, thread->pid,
41047 +                                               death->cookie, cookie);
41048 +                                       break;
41049 +                               }
41050 +                               ref->death = NULL;
41051 +                               if (list_empty(&death->work.entry)) {
41052 +                                       death->work.type = BINDER_WORK_CLEAR_DEATH_NOTIFICATION;
41053 +                                       if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) {
41054 +                                               list_add_tail(&death->work.entry, &thread->todo);
41055 +                                       } else {
41056 +                                               list_add_tail(&death->work.entry, &proc->todo);
41057 +                                               wake_up_interruptible(&proc->wait);
41058 +                                       }
41059 +                               } else {
41060 +                                       BUG_ON(death->work.type != BINDER_WORK_DEAD_BINDER);
41061 +                                       death->work.type = BINDER_WORK_DEAD_BINDER_AND_CLEAR;
41062 +                               }
41063 +                       }
41064 +               } break;
41065 +               case BC_DEAD_BINDER_DONE: {
41066 +                       struct binder_work *w;
41067 +                       void __user *cookie;
41068 +                       struct binder_ref_death *death = NULL;
41069 +                       if (get_user(cookie, (void __user * __user *)ptr))
41070 +                               return -EFAULT;
41071 +
41072 +                       ptr += sizeof(void *);
41073 +                       list_for_each_entry(w, &proc->delivered_death, entry) {
41074 +                               struct binder_ref_death *tmp_death = container_of(w, struct binder_ref_death, work);
41075 +                               if (tmp_death->cookie == cookie) {
41076 +                                       death = tmp_death;
41077 +                                       break;
41078 +                               }
41079 +                       }
41080 +                       if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
41081 +                               printk(KERN_INFO "binder: %d:%d BC_DEAD_BINDER_DONE %p found %p\n",
41082 +                                      proc->pid, thread->pid, cookie, death);
41083 +                       if (death == NULL) {
41084 +                               binder_user_error("binder: %d:%d BC_DEAD"
41085 +                                       "_BINDER_DONE %p not found\n",
41086 +                                       proc->pid, thread->pid, cookie);
41087 +                               break;
41088 +                       }
41089 +
41090 +                       list_del_init(&death->work.entry);
41091 +                       if (death->work.type == BINDER_WORK_DEAD_BINDER_AND_CLEAR) {
41092 +                               death->work.type = BINDER_WORK_CLEAR_DEATH_NOTIFICATION;
41093 +                               if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) {
41094 +                                       list_add_tail(&death->work.entry, &thread->todo);
41095 +                               } else {
41096 +                                       list_add_tail(&death->work.entry, &proc->todo);
41097 +                                       wake_up_interruptible(&proc->wait);
41098 +                               }
41099 +                       }
41100 +               } break;
41101 +
41102 +               default:
41103 +                       printk(KERN_ERR "binder: %d:%d unknown command %d\n", proc->pid, thread->pid, cmd);
41104 +                       return -EINVAL;
41105 +               }
41106 +               *consumed = ptr - buffer;
41107 +       }
41108 +       return 0;
41109 +}
41110 +
41111 +void
41112 +binder_stat_br(struct binder_proc *proc, struct binder_thread *thread, uint32_t cmd)
41113 +{
41114 +       if (_IOC_NR(cmd) < ARRAY_SIZE(binder_stats.br)) {
41115 +               binder_stats.br[_IOC_NR(cmd)]++;
41116 +               proc->stats.br[_IOC_NR(cmd)]++;
41117 +               thread->stats.br[_IOC_NR(cmd)]++;
41118 +       }
41119 +}
41120 +
41121 +static int
41122 +binder_has_proc_work(struct binder_proc *proc, struct binder_thread *thread)
41123 +{
41124 +       return !list_empty(&proc->todo) || (thread->looper & BINDER_LOOPER_STATE_NEED_RETURN);
41125 +}
41126 +
41127 +static int
41128 +binder_has_thread_work(struct binder_thread *thread)
41129 +{
41130 +       return !list_empty(&thread->todo) || thread->return_error != BR_OK ||
41131 +               (thread->looper & BINDER_LOOPER_STATE_NEED_RETURN);
41132 +}
41133 +
41134 +static int
41135 +binder_thread_read(struct binder_proc *proc, struct binder_thread *thread,
41136 +       void  __user *buffer, int size, signed long *consumed, int non_block)
41137 +{
41138 +       void __user *ptr = buffer + *consumed;
41139 +       void __user *end = buffer + size;
41140 +
41141 +       int ret = 0;
41142 +       int wait_for_proc_work;
41143 +
41144 +       if (*consumed == 0) {
41145 +               if (put_user(BR_NOOP, (uint32_t __user *)ptr))
41146 +                       return -EFAULT;
41147 +               ptr += sizeof(uint32_t);
41148 +       }
41149 +
41150 +retry:
41151 +       wait_for_proc_work = thread->transaction_stack == NULL && list_empty(&thread->todo);
41152 +
41153 +       if (thread->return_error != BR_OK && ptr < end) {
41154 +               if (thread->return_error2 != BR_OK) {
41155 +                       if (put_user(thread->return_error2, (uint32_t __user *)ptr))
41156 +                               return -EFAULT;
41157 +                       ptr += sizeof(uint32_t);
41158 +                       if (ptr == end)
41159 +                               goto done;
41160 +                       thread->return_error2 = BR_OK;
41161 +               }
41162 +               if (put_user(thread->return_error, (uint32_t __user *)ptr))
41163 +                       return -EFAULT;
41164 +               ptr += sizeof(uint32_t);
41165 +               thread->return_error = BR_OK;
41166 +               goto done;
41167 +       }
41168 +
41169 +
41170 +       thread->looper |= BINDER_LOOPER_STATE_WAITING;
41171 +       if (wait_for_proc_work)
41172 +               proc->ready_threads++;
41173 +       mutex_unlock(&binder_lock);
41174 +       if (wait_for_proc_work) {
41175 +               if (!(thread->looper & (BINDER_LOOPER_STATE_REGISTERED |
41176 +                                       BINDER_LOOPER_STATE_ENTERED))) {
41177 +                       binder_user_error("binder: %d:%d ERROR: Thread waiting "
41178 +                               "for process work before calling BC_REGISTER_"
41179 +                               "LOOPER or BC_ENTER_LOOPER (state %x)\n",
41180 +                               proc->pid, thread->pid, thread->looper);
41181 +                       wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
41182 +               }
41183 +               binder_set_nice(proc->default_priority);
41184 +               if (non_block) {
41185 +                       if (!binder_has_proc_work(proc, thread))
41186 +                               ret = -EAGAIN;
41187 +               } else
41188 +                       ret = wait_event_interruptible_exclusive(proc->wait, binder_has_proc_work(proc, thread));
41189 +       } else {
41190 +               if (non_block) {
41191 +                       if (!binder_has_thread_work(thread))
41192 +                               ret = -EAGAIN;
41193 +               } else
41194 +                       ret = wait_event_interruptible(thread->wait, binder_has_thread_work(thread));
41195 +       }
41196 +       mutex_lock(&binder_lock);
41197 +       if (wait_for_proc_work)
41198 +               proc->ready_threads--;
41199 +       thread->looper &= ~BINDER_LOOPER_STATE_WAITING;
41200 +
41201 +       if (ret)
41202 +               return ret;
41203 +
41204 +       while (1) {
41205 +               uint32_t cmd;
41206 +               struct binder_transaction_data tr;
41207 +               struct binder_work *w;
41208 +               struct binder_transaction *t = NULL;
41209 +
41210 +               if (!list_empty(&thread->todo))
41211 +                       w = list_first_entry(&thread->todo, struct binder_work, entry);
41212 +               else if (!list_empty(&proc->todo) && wait_for_proc_work)
41213 +                       w = list_first_entry(&proc->todo, struct binder_work, entry);
41214 +               else {
41215 +                       if (ptr - buffer == 4 && !(thread->looper & BINDER_LOOPER_STATE_NEED_RETURN)) /* no data added */
41216 +                               goto retry;
41217 +                       break;
41218 +               }
41219 +
41220 +               if (end - ptr < sizeof(tr) + 4)
41221 +                       break;
41222 +
41223 +               switch (w->type) {
41224 +               case BINDER_WORK_TRANSACTION: {
41225 +                       t = container_of(w, struct binder_transaction, work);
41226 +               } break;
41227 +               case BINDER_WORK_TRANSACTION_COMPLETE: {
41228 +                       cmd = BR_TRANSACTION_COMPLETE;
41229 +                       if (put_user(cmd, (uint32_t __user *)ptr))
41230 +                               return -EFAULT;
41231 +                       ptr += sizeof(uint32_t);
41232 +
41233 +                       binder_stat_br(proc, thread, cmd);
41234 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION_COMPLETE)
41235 +                               printk(KERN_INFO "binder: %d:%d BR_TRANSACTION_COMPLETE\n",
41236 +                                      proc->pid, thread->pid);
41237 +
41238 +                       list_del(&w->entry);
41239 +                       kfree(w);
41240 +                       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION_COMPLETE]++;
41241 +               } break;
41242 +               case BINDER_WORK_NODE: {
41243 +                       struct binder_node *node = container_of(w, struct binder_node, work);
41244 +                       uint32_t cmd = BR_NOOP;
41245 +                       const char *cmd_name;
41246 +                       int strong = node->internal_strong_refs || node->local_strong_refs;
41247 +                       int weak = !hlist_empty(&node->refs) || node->local_weak_refs || strong;
41248 +                       if (weak && !node->has_weak_ref) {
41249 +                               cmd = BR_INCREFS;
41250 +                               cmd_name = "BR_INCREFS";
41251 +                               node->has_weak_ref = 1;
41252 +                               node->pending_weak_ref = 1;
41253 +                               node->local_weak_refs++;
41254 +                       } else if (strong && !node->has_strong_ref) {
41255 +                               cmd = BR_ACQUIRE;
41256 +                               cmd_name = "BR_ACQUIRE";
41257 +                               node->has_strong_ref = 1;
41258 +                               node->pending_strong_ref = 1;
41259 +                               node->local_strong_refs++;
41260 +                       } else if (!strong && node->has_strong_ref) {
41261 +                               cmd = BR_RELEASE;
41262 +                               cmd_name = "BR_RELEASE";
41263 +                               node->has_strong_ref = 0;
41264 +                       } else if (!weak && node->has_weak_ref) {
41265 +                               cmd = BR_DECREFS;
41266 +                               cmd_name = "BR_DECREFS";
41267 +                               node->has_weak_ref = 0;
41268 +                       }
41269 +                       if (cmd != BR_NOOP) {
41270 +                               if (put_user(cmd, (uint32_t __user *)ptr))
41271 +                                       return -EFAULT;
41272 +                               ptr += sizeof(uint32_t);
41273 +                               if (put_user(node->ptr, (void * __user *)ptr))
41274 +                                       return -EFAULT;
41275 +                               ptr += sizeof(void *);
41276 +                               if (put_user(node->cookie, (void * __user *)ptr))
41277 +                                       return -EFAULT;
41278 +                               ptr += sizeof(void *);
41279 +
41280 +                               binder_stat_br(proc, thread, cmd);
41281 +                               if (binder_debug_mask & BINDER_DEBUG_USER_REFS)
41282 +                                       printk(KERN_INFO "binder: %d:%d %s %d u%p c%p\n",
41283 +                                              proc->pid, thread->pid, cmd_name, node->debug_id, node->ptr, node->cookie);
41284 +                       } else {
41285 +                               list_del_init(&w->entry);
41286 +                               if (!weak && !strong) {
41287 +                                       if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
41288 +                                               printk(KERN_INFO "binder: %d:%d node %d u%p c%p deleted\n",
41289 +                                                      proc->pid, thread->pid, node->debug_id, node->ptr, node->cookie);
41290 +                                       rb_erase(&node->rb_node, &proc->nodes);
41291 +                                       kfree(node);
41292 +                                       binder_stats.obj_deleted[BINDER_STAT_NODE]++;
41293 +                               } else {
41294 +                                       if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
41295 +                                               printk(KERN_INFO "binder: %d:%d node %d u%p c%p state unchanged\n",
41296 +                                                      proc->pid, thread->pid, node->debug_id, node->ptr, node->cookie);
41297 +                               }
41298 +                       }
41299 +               } break;
41300 +               case BINDER_WORK_DEAD_BINDER:
41301 +               case BINDER_WORK_DEAD_BINDER_AND_CLEAR:
41302 +               case BINDER_WORK_CLEAR_DEATH_NOTIFICATION: {
41303 +                       struct binder_ref_death *death = container_of(w, struct binder_ref_death, work);
41304 +                       uint32_t cmd;
41305 +                       if (w->type == BINDER_WORK_CLEAR_DEATH_NOTIFICATION)
41306 +                               cmd = BR_CLEAR_DEATH_NOTIFICATION_DONE;
41307 +                       else
41308 +                               cmd = BR_DEAD_BINDER;
41309 +                       if (put_user(cmd, (uint32_t __user *)ptr))
41310 +                               return -EFAULT;
41311 +                       ptr += sizeof(uint32_t);
41312 +                       if (put_user(death->cookie, (void * __user *)ptr))
41313 +                               return -EFAULT;
41314 +                       ptr += sizeof(void *);
41315 +                       if (binder_debug_mask & BINDER_DEBUG_DEATH_NOTIFICATION)
41316 +                               printk(KERN_INFO "binder: %d:%d %s %p\n",
41317 +                                      proc->pid, thread->pid,
41318 +                                      cmd == BR_DEAD_BINDER ?
41319 +                                      "BR_DEAD_BINDER" :
41320 +                                      "BR_CLEAR_DEATH_NOTIFICATION_DONE",
41321 +                                      death->cookie);
41322 +
41323 +                       if (w->type == BINDER_WORK_CLEAR_DEATH_NOTIFICATION) {
41324 +                               list_del(&w->entry);
41325 +                               kfree(death);
41326 +                               binder_stats.obj_deleted[BINDER_STAT_DEATH]++;
41327 +                       } else
41328 +                               list_move(&w->entry, &proc->delivered_death);
41329 +                       if (cmd == BR_DEAD_BINDER)
41330 +                               goto done; /* DEAD_BINDER notifications can cause transactions */
41331 +               } break;
41332 +               }
41333 +
41334 +               if (!t)
41335 +                       continue;
41336 +
41337 +               BUG_ON(t->buffer == NULL);
41338 +               if (t->buffer->target_node) {
41339 +                       struct binder_node *target_node = t->buffer->target_node;
41340 +                       tr.target.ptr = target_node->ptr;
41341 +                       tr.cookie =  target_node->cookie;
41342 +                       t->saved_priority = task_nice(current);
41343 +                       if (t->priority < target_node->min_priority &&
41344 +                           !(t->flags & TF_ONE_WAY))
41345 +                               binder_set_nice(t->priority);
41346 +                       else if (!(t->flags & TF_ONE_WAY) ||
41347 +                                t->saved_priority > target_node->min_priority)
41348 +                               binder_set_nice(target_node->min_priority);
41349 +                       cmd = BR_TRANSACTION;
41350 +               } else {
41351 +                       tr.target.ptr = NULL;
41352 +                       tr.cookie = NULL;
41353 +                       cmd = BR_REPLY;
41354 +               }
41355 +               tr.code = t->code;
41356 +               tr.flags = t->flags;
41357 +               tr.sender_euid = t->sender_euid;
41358 +
41359 +               if (t->from) {
41360 +                       struct task_struct *sender = t->from->proc->tsk;
41361 +                       tr.sender_pid = task_tgid_nr_ns(sender, current->nsproxy->pid_ns);
41362 +               } else {
41363 +                       tr.sender_pid = 0;
41364 +               }
41365 +
41366 +               tr.data_size = t->buffer->data_size;
41367 +               tr.offsets_size = t->buffer->offsets_size;
41368 +               tr.data.ptr.buffer = (void *)((void *)t->buffer->data + proc->user_buffer_offset);
41369 +               tr.data.ptr.offsets = tr.data.ptr.buffer + ALIGN(t->buffer->data_size, sizeof(void *));
41370 +
41371 +               if (put_user(cmd, (uint32_t __user *)ptr))
41372 +                       return -EFAULT;
41373 +               ptr += sizeof(uint32_t);
41374 +               if (copy_to_user(ptr, &tr, sizeof(tr)))
41375 +                       return -EFAULT;
41376 +               ptr += sizeof(tr);
41377 +
41378 +               binder_stat_br(proc, thread, cmd);
41379 +               if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
41380 +                       printk(KERN_INFO "binder: %d:%d %s %d %d:%d, cmd %d size %d-%d ptr %p-%p\n",
41381 +                              proc->pid, thread->pid,
41382 +                              (cmd == BR_TRANSACTION) ? "BR_TRANSACTION" : "BR_REPLY",
41383 +                              t->debug_id, t->from ? t->from->proc->pid : 0,
41384 +                              t->from ? t->from->pid : 0, cmd,
41385 +                              t->buffer->data_size, t->buffer->offsets_size,
41386 +                              tr.data.ptr.buffer, tr.data.ptr.offsets);
41387 +
41388 +               list_del(&t->work.entry);
41389 +               t->buffer->allow_user_free = 1;
41390 +               if (cmd == BR_TRANSACTION && !(t->flags & TF_ONE_WAY)) {
41391 +                       t->to_parent = thread->transaction_stack;
41392 +                       t->to_thread = thread;
41393 +                       thread->transaction_stack = t;
41394 +               } else {
41395 +                       t->buffer->transaction = NULL;
41396 +                       kfree(t);
41397 +                       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION]++;
41398 +               }
41399 +               break;
41400 +       }
41401 +
41402 +done:
41403 +
41404 +       *consumed = ptr - buffer;
41405 +       if (proc->requested_threads + proc->ready_threads == 0 &&
41406 +           proc->requested_threads_started < proc->max_threads &&
41407 +           (thread->looper & (BINDER_LOOPER_STATE_REGISTERED |
41408 +            BINDER_LOOPER_STATE_ENTERED)) /* the user-space code fails to */
41409 +            /*spawn a new thread if we leave this out */) {
41410 +               proc->requested_threads++;
41411 +               if (binder_debug_mask & BINDER_DEBUG_THREADS)
41412 +                       printk(KERN_INFO "binder: %d:%d BR_SPAWN_LOOPER\n",
41413 +                              proc->pid, thread->pid);
41414 +               if (put_user(BR_SPAWN_LOOPER, (uint32_t __user *)buffer))
41415 +                       return -EFAULT;
41416 +       }
41417 +       return 0;
41418 +}
41419 +
41420 +static void binder_release_work(struct list_head *list)
41421 +{
41422 +       struct binder_work *w;
41423 +       while (!list_empty(list)) {
41424 +               w = list_first_entry(list, struct binder_work, entry);
41425 +               list_del_init(&w->entry);
41426 +               switch (w->type) {
41427 +               case BINDER_WORK_TRANSACTION: {
41428 +                       struct binder_transaction *t = container_of(w, struct binder_transaction, work);
41429 +                       if (t->buffer->target_node && !(t->flags & TF_ONE_WAY))
41430 +                               binder_send_failed_reply(t, BR_DEAD_REPLY);
41431 +               } break;
41432 +               case BINDER_WORK_TRANSACTION_COMPLETE: {
41433 +                       kfree(w);
41434 +                       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION_COMPLETE]++;
41435 +               } break;
41436 +               default:
41437 +                       break;
41438 +               }
41439 +       }
41440 +
41441 +}
41442 +
41443 +static struct binder_thread *binder_get_thread(struct binder_proc *proc)
41444 +{
41445 +       struct binder_thread *thread = NULL;
41446 +       struct rb_node *parent = NULL;
41447 +       struct rb_node **p = &proc->threads.rb_node;
41448 +
41449 +       while (*p) {
41450 +               parent = *p;
41451 +               thread = rb_entry(parent, struct binder_thread, rb_node);
41452 +
41453 +               if (current->pid < thread->pid)
41454 +                       p = &(*p)->rb_left;
41455 +               else if (current->pid > thread->pid)
41456 +                       p = &(*p)->rb_right;
41457 +               else
41458 +                       break;
41459 +       }
41460 +       if (*p == NULL) {
41461 +               thread = kzalloc(sizeof(*thread), GFP_KERNEL);
41462 +               if (thread == NULL)
41463 +                       return NULL;
41464 +               binder_stats.obj_created[BINDER_STAT_THREAD]++;
41465 +               thread->proc = proc;
41466 +               thread->pid = current->pid;
41467 +               init_waitqueue_head(&thread->wait);
41468 +               INIT_LIST_HEAD(&thread->todo);
41469 +               rb_link_node(&thread->rb_node, parent, p);
41470 +               rb_insert_color(&thread->rb_node, &proc->threads);
41471 +               thread->looper |= BINDER_LOOPER_STATE_NEED_RETURN;
41472 +               thread->return_error = BR_OK;
41473 +               thread->return_error2 = BR_OK;
41474 +       }
41475 +       return thread;
41476 +}
41477 +
41478 +static int binder_free_thread(struct binder_proc *proc, struct binder_thread *thread)
41479 +{
41480 +       struct binder_transaction *t;
41481 +       struct binder_transaction *send_reply = NULL;
41482 +       int active_transactions = 0;
41483 +
41484 +       rb_erase(&thread->rb_node, &proc->threads);
41485 +       t = thread->transaction_stack;
41486 +       if (t && t->to_thread == thread)
41487 +               send_reply = t;
41488 +       while (t) {
41489 +               active_transactions++;
41490 +               if (binder_debug_mask & BINDER_DEBUG_DEAD_TRANSACTION)
41491 +                       printk(KERN_INFO "binder: release %d:%d transaction %d %s, still active\n",
41492 +                              proc->pid, thread->pid, t->debug_id, (t->to_thread == thread) ? "in" : "out");
41493 +               if (t->to_thread == thread) {
41494 +                       t->to_proc = NULL;
41495 +                       t->to_thread = NULL;
41496 +                       if (t->buffer) {
41497 +                               t->buffer->transaction = NULL;
41498 +                               t->buffer = NULL;
41499 +                       }
41500 +                       t = t->to_parent;
41501 +               } else if (t->from == thread) {
41502 +                       t->from = NULL;
41503 +                       t = t->from_parent;
41504 +               } else
41505 +                       BUG();
41506 +       }
41507 +       if (send_reply)
41508 +               binder_send_failed_reply(send_reply, BR_DEAD_REPLY);
41509 +       binder_release_work(&thread->todo);
41510 +       kfree(thread);
41511 +       binder_stats.obj_deleted[BINDER_STAT_THREAD]++;
41512 +       return active_transactions;
41513 +}
41514 +
41515 +static unsigned int binder_poll(struct file *filp, struct poll_table_struct *wait)
41516 +{
41517 +       struct binder_proc *proc = filp->private_data;
41518 +       struct binder_thread *thread = NULL;
41519 +       int wait_for_proc_work;
41520 +
41521 +       mutex_lock(&binder_lock);
41522 +       thread = binder_get_thread(proc);
41523 +
41524 +       wait_for_proc_work = thread->transaction_stack == NULL &&
41525 +               list_empty(&thread->todo) && thread->return_error == BR_OK;
41526 +       mutex_unlock(&binder_lock);
41527 +
41528 +       if (wait_for_proc_work) {
41529 +               if (binder_has_proc_work(proc, thread))
41530 +                       return POLLIN;
41531 +               poll_wait(filp, &proc->wait, wait);
41532 +               if (binder_has_proc_work(proc, thread))
41533 +                       return POLLIN;
41534 +       } else {
41535 +               if (binder_has_thread_work(thread))
41536 +                       return POLLIN;
41537 +               poll_wait(filp, &thread->wait, wait);
41538 +               if (binder_has_thread_work(thread))
41539 +                       return POLLIN;
41540 +       }
41541 +       return 0;
41542 +}
41543 +
41544 +static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
41545 +{
41546 +       int ret;
41547 +       struct binder_proc *proc = filp->private_data;
41548 +       struct binder_thread *thread;
41549 +       unsigned int size = _IOC_SIZE(cmd);
41550 +       void __user *ubuf = (void __user *)arg;
41551 +
41552 +       /*printk(KERN_INFO "binder_ioctl: %d:%d %x %lx\n", proc->pid, current->pid, cmd, arg);*/
41553 +
41554 +       ret = wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
41555 +       if (ret)
41556 +               return ret;
41557 +
41558 +       mutex_lock(&binder_lock);
41559 +       thread = binder_get_thread(proc);
41560 +       if (thread == NULL) {
41561 +               ret = -ENOMEM;
41562 +               goto err;
41563 +       }
41564 +
41565 +       switch (cmd) {
41566 +       case BINDER_WRITE_READ: {
41567 +               struct binder_write_read bwr;
41568 +               if (size != sizeof(struct binder_write_read)) {
41569 +                       ret = -EINVAL;
41570 +                       goto err;
41571 +               }
41572 +               if (copy_from_user(&bwr, ubuf, sizeof(bwr))) {
41573 +                       ret = -EFAULT;
41574 +                       goto err;
41575 +               }
41576 +               if (binder_debug_mask & BINDER_DEBUG_READ_WRITE)
41577 +                       printk(KERN_INFO "binder: %d:%d write %ld at %08lx, read %ld at %08lx\n",
41578 +                              proc->pid, thread->pid, bwr.write_size, bwr.write_buffer, bwr.read_size, bwr.read_buffer);
41579 +               if (bwr.write_size > 0) {
41580 +                       ret = binder_thread_write(proc, thread, (void __user *)bwr.write_buffer, bwr.write_size, &bwr.write_consumed);
41581 +                       if (ret < 0) {
41582 +                               bwr.read_consumed = 0;
41583 +                               if (copy_to_user(ubuf, &bwr, sizeof(bwr)))
41584 +                                       ret = -EFAULT;
41585 +                               goto err;
41586 +                       }
41587 +               }
41588 +               if (bwr.read_size > 0) {
41589 +                       ret = binder_thread_read(proc, thread, (void __user *)bwr.read_buffer, bwr.read_size, &bwr.read_consumed, filp->f_flags & O_NONBLOCK);
41590 +                       if (!list_empty(&proc->todo))
41591 +                               wake_up_interruptible(&proc->wait);
41592 +                       if (ret < 0) {
41593 +                               if (copy_to_user(ubuf, &bwr, sizeof(bwr)))
41594 +                                       ret = -EFAULT;
41595 +                               goto err;
41596 +                       }
41597 +               }
41598 +               if (binder_debug_mask & BINDER_DEBUG_READ_WRITE)
41599 +                       printk(KERN_INFO "binder: %d:%d wrote %ld of %ld, read return %ld of %ld\n",
41600 +                              proc->pid, thread->pid, bwr.write_consumed, bwr.write_size, bwr.read_consumed, bwr.read_size);
41601 +               if (copy_to_user(ubuf, &bwr, sizeof(bwr))) {
41602 +                       ret = -EFAULT;
41603 +                       goto err;
41604 +               }
41605 +               break;
41606 +       }
41607 +       case BINDER_SET_MAX_THREADS:
41608 +               if (copy_from_user(&proc->max_threads, ubuf, sizeof(proc->max_threads))) {
41609 +                       ret = -EINVAL;
41610 +                       goto err;
41611 +               }
41612 +               break;
41613 +       case BINDER_SET_CONTEXT_MGR:
41614 +               if (binder_context_mgr_node != NULL) {
41615 +                       printk(KERN_ERR "binder: BINDER_SET_CONTEXT_MGR already set\n");
41616 +                       ret = -EBUSY;
41617 +                       goto err;
41618 +               }
41619 +               if (binder_context_mgr_uid != -1) {
41620 +                       if (binder_context_mgr_uid != current->euid) {
41621 +                               printk(KERN_ERR "binder: BINDER_SET_"
41622 +                                      "CONTEXT_MGR bad uid %d != %d\n",
41623 +                                      current->euid,
41624 +                                      binder_context_mgr_uid);
41625 +                               ret = -EPERM;
41626 +                               goto err;
41627 +                       }
41628 +               } else
41629 +                       binder_context_mgr_uid = current->euid;
41630 +               binder_context_mgr_node = binder_new_node(proc, NULL, NULL);
41631 +               if (binder_context_mgr_node == NULL) {
41632 +                       ret = -ENOMEM;
41633 +                       goto err;
41634 +               }
41635 +               binder_context_mgr_node->local_weak_refs++;
41636 +               binder_context_mgr_node->local_strong_refs++;
41637 +               binder_context_mgr_node->has_strong_ref = 1;
41638 +               binder_context_mgr_node->has_weak_ref = 1;
41639 +               break;
41640 +       case BINDER_THREAD_EXIT:
41641 +               if (binder_debug_mask & BINDER_DEBUG_THREADS)
41642 +                       printk(KERN_INFO "binder: %d:%d exit\n",
41643 +                              proc->pid, thread->pid);
41644 +               binder_free_thread(proc, thread);
41645 +               thread = NULL;
41646 +               break;
41647 +       case BINDER_VERSION:
41648 +               if (size != sizeof(struct binder_version)) {
41649 +                       ret = -EINVAL;
41650 +                       goto err;
41651 +               }
41652 +               if (put_user(BINDER_CURRENT_PROTOCOL_VERSION, &((struct binder_version *)ubuf)->protocol_version)) {
41653 +                       ret = -EINVAL;
41654 +                       goto err;
41655 +               }
41656 +               break;
41657 +       default:
41658 +               ret = -EINVAL;
41659 +               goto err;
41660 +       }
41661 +       ret = 0;
41662 +err:
41663 +       if (thread)
41664 +               thread->looper &= ~BINDER_LOOPER_STATE_NEED_RETURN;
41665 +       mutex_unlock(&binder_lock);
41666 +       wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
41667 +       if (ret && ret != -ERESTARTSYS)
41668 +               printk(KERN_INFO "binder: %d:%d ioctl %x %lx returned %d\n", proc->pid, current->pid, cmd, arg, ret);
41669 +       return ret;
41670 +}
41671 +
41672 +static void binder_vma_open(struct vm_area_struct *vma)
41673 +{
41674 +       struct binder_proc *proc = vma->vm_private_data;
41675 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
41676 +               printk(KERN_INFO "binder: %d open vm area %lx-%lx (%ld K) vma %lx pagep %lx\n", proc->pid, vma->vm_start, vma->vm_end, (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, vma->vm_page_prot);
41677 +       dump_stack();
41678 +}
41679 +static void binder_vma_close(struct vm_area_struct *vma)
41680 +{
41681 +       struct binder_proc *proc = vma->vm_private_data;
41682 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
41683 +               printk(KERN_INFO "binder: %d close vm area %lx-%lx (%ld K) vma %lx pagep %lx\n", proc->pid, vma->vm_start, vma->vm_end, (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, vma->vm_page_prot);
41684 +       proc->vma = NULL;
41685 +}
41686 +
41687 +static struct vm_operations_struct binder_vm_ops = {
41688 +       .open = binder_vma_open,
41689 +       .close = binder_vma_close,
41690 +};
41691 +
41692 +static int binder_mmap(struct file *filp, struct vm_area_struct *vma)
41693 +{
41694 +       int ret;
41695 +       struct vm_struct *area;
41696 +       struct binder_proc *proc = filp->private_data;
41697 +       const char *failure_string;
41698 +       struct binder_buffer *buffer;
41699 +
41700 +       if ((vma->vm_end - vma->vm_start) > SZ_4M)
41701 +               vma->vm_end = vma->vm_start + SZ_4M;
41702 +
41703 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
41704 +               printk(KERN_INFO "binder_mmap: %d %lx-%lx (%ld K) vma %lx pagep %lx\n", proc->pid, vma->vm_start, vma->vm_end, (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, vma->vm_page_prot);
41705 +
41706 +       if (vma->vm_flags & FORBIDDEN_MMAP_FLAGS) {
41707 +               ret = -EPERM;
41708 +               failure_string = "bad vm_flags";
41709 +               goto err_bad_arg;
41710 +       }
41711 +       vma->vm_flags = (vma->vm_flags | VM_DONTCOPY) & ~VM_MAYWRITE;
41712 +
41713 +       area = get_vm_area(vma->vm_end - vma->vm_start, VM_IOREMAP);
41714 +       if (area == NULL) {
41715 +               ret = -ENOMEM;
41716 +               failure_string = "get_vm_area";
41717 +               goto err_get_vm_area_failed;
41718 +       }
41719 +       proc->buffer = area->addr;
41720 +       proc->user_buffer_offset = vma->vm_start - (size_t)proc->buffer;
41721 +
41722 +#if defined(CONFIG_CPU_CACHE_VIPT) && !defined(CONFIG_CPU_S3C6410)
41723 +       if (cache_is_vipt_aliasing()) {
41724 +               while (CACHE_COLOUR((vma->vm_start ^ (uint32_t)proc->buffer))) {
41725 +                       printk(KERN_INFO "binder_mmap: %d %lx-%lx maps %p bad alignment\n", proc->pid, vma->vm_start, vma->vm_end, proc->buffer);
41726 +                       vma->vm_start += PAGE_SIZE;
41727 +               }
41728 +       }
41729 +#endif
41730 +       proc->pages = kzalloc(sizeof(proc->pages[0]) * ((vma->vm_end - vma->vm_start) / PAGE_SIZE), GFP_KERNEL);
41731 +       if (proc->pages == NULL) {
41732 +               ret = -ENOMEM;
41733 +               failure_string = "alloc page array";
41734 +               goto err_alloc_pages_failed;
41735 +       }
41736 +       proc->buffer_size = vma->vm_end - vma->vm_start;
41737 +
41738 +       vma->vm_ops = &binder_vm_ops;
41739 +       vma->vm_private_data = proc;
41740 +
41741 +       if (binder_update_page_range(proc, 1, proc->buffer, proc->buffer + PAGE_SIZE, vma)) {
41742 +               ret = -ENOMEM;
41743 +               failure_string = "alloc small buf";
41744 +               goto err_alloc_small_buf_failed;
41745 +       }
41746 +       buffer = proc->buffer;
41747 +       INIT_LIST_HEAD(&proc->buffers);
41748 +       list_add(&buffer->entry, &proc->buffers);
41749 +       buffer->free = 1;
41750 +       binder_insert_free_buffer(proc, buffer);
41751 +       proc->free_async_space = proc->buffer_size / 2;
41752 +       barrier();
41753 +       proc->vma = vma;
41754 +
41755 +       /*printk(KERN_INFO "binder_mmap: %d %lx-%lx maps %p\n", proc->pid, vma->vm_start, vma->vm_end, proc->buffer);*/
41756 +       return 0;
41757 +
41758 +err_alloc_small_buf_failed:
41759 +       kfree(proc->pages);
41760 +err_alloc_pages_failed:
41761 +       vfree(proc->buffer);
41762 +err_get_vm_area_failed:
41763 +       mutex_unlock(&binder_lock);
41764 +err_bad_arg:
41765 +       printk(KERN_ERR "binder_mmap: %d %lx-%lx %s failed %d\n", proc->pid, vma->vm_start, vma->vm_end, failure_string, ret);
41766 +       return ret;
41767 +}
41768 +
41769 +static int binder_open(struct inode *nodp, struct file *filp)
41770 +{
41771 +       struct binder_proc *proc;
41772 +
41773 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
41774 +               printk(KERN_INFO "binder_open: %d:%d\n", current->group_leader->pid, current->pid);
41775 +
41776 +       proc = kzalloc(sizeof(*proc), GFP_KERNEL);
41777 +       if (proc == NULL)
41778 +               return -ENOMEM;
41779 +       get_task_struct(current);
41780 +       proc->tsk = current;
41781 +       INIT_LIST_HEAD(&proc->todo);
41782 +       init_waitqueue_head(&proc->wait);
41783 +       proc->default_priority = task_nice(current);
41784 +       mutex_lock(&binder_lock);
41785 +       binder_stats.obj_created[BINDER_STAT_PROC]++;
41786 +       hlist_add_head(&proc->proc_node, &binder_procs);
41787 +       proc->pid = current->group_leader->pid;
41788 +       INIT_LIST_HEAD(&proc->delivered_death);
41789 +       filp->private_data = proc;
41790 +       mutex_unlock(&binder_lock);
41791 +
41792 +       if (binder_proc_dir_entry_proc) {
41793 +               char strbuf[11];
41794 +               snprintf(strbuf, sizeof(strbuf), "%u", proc->pid);
41795 +               create_proc_read_entry(strbuf, S_IRUGO, binder_proc_dir_entry_proc, binder_read_proc_proc, proc);
41796 +       }
41797 +
41798 +       return 0;
41799 +}
41800 +
41801 +static int binder_flush(struct file *filp, fl_owner_t id)
41802 +{
41803 +       struct rb_node *n;
41804 +       struct binder_proc *proc = filp->private_data;
41805 +       int wake_count = 0;
41806 +
41807 +       mutex_lock(&binder_lock);
41808 +       for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n)) {
41809 +               struct binder_thread *thread = rb_entry(n, struct binder_thread, rb_node);
41810 +               thread->looper |= BINDER_LOOPER_STATE_NEED_RETURN;
41811 +               if (thread->looper & BINDER_LOOPER_STATE_WAITING) {
41812 +                       wake_up_interruptible(&thread->wait);
41813 +                       wake_count++;
41814 +               }
41815 +       }
41816 +       wake_up_interruptible_all(&proc->wait);
41817 +       mutex_unlock(&binder_lock);
41818 +
41819 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
41820 +               printk(KERN_INFO "binder_flush: %d woke %d threads\n", proc->pid, wake_count);
41821 +
41822 +       return 0;
41823 +}
41824 +
41825 +static int binder_release(struct inode *nodp, struct file *filp)
41826 +{
41827 +       struct hlist_node *pos;
41828 +       struct binder_transaction *t;
41829 +       struct rb_node *n;
41830 +       struct binder_proc *proc = filp->private_data;
41831 +       int threads, nodes, incoming_refs, outgoing_refs, buffers, active_transactions, page_count;
41832 +
41833 +       if (binder_proc_dir_entry_proc) {
41834 +               char strbuf[11];
41835 +               snprintf(strbuf, sizeof(strbuf), "%u", proc->pid);
41836 +               remove_proc_entry(strbuf, binder_proc_dir_entry_proc);
41837 +       }
41838 +       mutex_lock(&binder_lock);
41839 +       hlist_del(&proc->proc_node);
41840 +       if (binder_context_mgr_node && binder_context_mgr_node->proc == proc) {
41841 +               if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
41842 +                       printk(KERN_INFO "binder_release: %d context_mgr_node gone\n", proc->pid);
41843 +               binder_context_mgr_node = NULL;
41844 +       }
41845 +
41846 +       threads = 0;
41847 +       active_transactions = 0;
41848 +       while ((n = rb_first(&proc->threads))) {
41849 +               struct binder_thread *thread = rb_entry(n, struct binder_thread, rb_node);
41850 +               threads++;
41851 +               active_transactions += binder_free_thread(proc, thread);
41852 +       }
41853 +       nodes = 0;
41854 +       incoming_refs = 0;
41855 +       while ((n = rb_first(&proc->nodes))) {
41856 +               struct binder_node *node = rb_entry(n, struct binder_node, rb_node);
41857 +
41858 +               nodes++;
41859 +               rb_erase(&node->rb_node, &proc->nodes);
41860 +               list_del_init(&node->work.entry);
41861 +               if (hlist_empty(&node->refs)) {
41862 +                       kfree(node);
41863 +                       binder_stats.obj_deleted[BINDER_STAT_NODE]++;
41864 +               } else {
41865 +                       struct binder_ref *ref;
41866 +                       int death = 0;
41867 +
41868 +                       node->proc = NULL;
41869 +                       node->local_strong_refs = 0;
41870 +                       node->local_weak_refs = 0;
41871 +                       hlist_add_head(&node->dead_node, &binder_dead_nodes);
41872 +
41873 +                       hlist_for_each_entry(ref, pos, &node->refs, node_entry) {
41874 +                               incoming_refs++;
41875 +                               if (ref->death) {
41876 +                                       death++;
41877 +                                       if (list_empty(&ref->death->work.entry)) {
41878 +                                               ref->death->work.type = BINDER_WORK_DEAD_BINDER;
41879 +                                               list_add_tail(&ref->death->work.entry, &ref->proc->todo);
41880 +                                               wake_up_interruptible(&ref->proc->wait);
41881 +                                       } else
41882 +                                               BUG();
41883 +                               }
41884 +                       }
41885 +                       if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
41886 +                               printk(KERN_INFO "binder: node %d now dead, refs %d, death %d\n", node->debug_id, incoming_refs, death);
41887 +               }
41888 +       }
41889 +       outgoing_refs = 0;
41890 +       while ((n = rb_first(&proc->refs_by_desc))) {
41891 +               struct binder_ref *ref = rb_entry(n, struct binder_ref, rb_node_desc);
41892 +               outgoing_refs++;
41893 +               binder_delete_ref(ref);
41894 +       }
41895 +       binder_release_work(&proc->todo);
41896 +       buffers = 0;
41897 +
41898 +       while ((n = rb_first(&proc->allocated_buffers))) {
41899 +               struct binder_buffer *buffer = rb_entry(n, struct binder_buffer, rb_node);
41900 +               t = buffer->transaction;
41901 +               if (t) {
41902 +                       t->buffer = NULL;
41903 +                       buffer->transaction = NULL;
41904 +                       printk(KERN_ERR "binder: release proc %d, transaction %d, not freed\n", proc->pid, t->debug_id);
41905 +                       /*BUG();*/
41906 +               }
41907 +               binder_free_buf(proc, buffer);
41908 +               buffers++;
41909 +       }
41910 +
41911 +       binder_stats.obj_deleted[BINDER_STAT_PROC]++;
41912 +       mutex_unlock(&binder_lock);
41913 +
41914 +       page_count = 0;
41915 +       if (proc->pages) {
41916 +               int i;
41917 +               for (i = 0; i < proc->buffer_size / PAGE_SIZE; i++) {
41918 +                       if (proc->pages[i]) {
41919 +                               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
41920 +                                       printk(KERN_INFO "binder_release: %d: page %d at %p not freed\n", proc->pid, i, proc->buffer + i * PAGE_SIZE);
41921 +                               __free_page(proc->pages[i]);
41922 +                               page_count++;
41923 +                       }
41924 +               }
41925 +               kfree(proc->pages);
41926 +               vfree(proc->buffer);
41927 +       }
41928 +
41929 +       put_task_struct(proc->tsk);
41930 +
41931 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
41932 +               printk(KERN_INFO "binder_release: %d threads %d, nodes %d (ref %d), refs %d, active transactions %d, buffers %d, pages %d\n",
41933 +                      proc->pid, threads, nodes, incoming_refs, outgoing_refs, active_transactions, buffers, page_count);
41934 +
41935 +       kfree(proc);
41936 +       return 0;
41937 +}
41938 +
41939 +static char *print_binder_transaction(char *buf, char *end, const char *prefix, struct binder_transaction *t)
41940 +{
41941 +       buf += snprintf(buf, end - buf, "%s %d: %p from %d:%d to %d:%d code %x flags %x pri %ld r%d",
41942 +                       prefix, t->debug_id, t, t->from ? t->from->proc->pid : 0,
41943 +                       t->from ? t->from->pid : 0,
41944 +                       t->to_proc ? t->to_proc->pid : 0,
41945 +                       t->to_thread ? t->to_thread->pid : 0,
41946 +                       t->code, t->flags, t->priority, t->need_reply);
41947 +       if (buf >= end)
41948 +               return buf;
41949 +       if (t->buffer == NULL) {
41950 +               buf += snprintf(buf, end - buf, " buffer free\n");
41951 +               return buf;
41952 +       }
41953 +       if (t->buffer->target_node) {
41954 +               buf += snprintf(buf, end - buf, " node %d",
41955 +                               t->buffer->target_node->debug_id);
41956 +               if (buf >= end)
41957 +                       return buf;
41958 +       }
41959 +       buf += snprintf(buf, end - buf, " size %d:%d data %p\n",
41960 +                       t->buffer->data_size, t->buffer->offsets_size,
41961 +                       t->buffer->data);
41962 +       return buf;
41963 +}
41964 +
41965 +static char *print_binder_buffer(char *buf, char *end, const char *prefix, struct binder_buffer *buffer)
41966 +{
41967 +       buf += snprintf(buf, end - buf, "%s %d: %p size %d:%d %s\n",
41968 +                       prefix, buffer->debug_id, buffer->data,
41969 +                       buffer->data_size, buffer->offsets_size,
41970 +                       buffer->transaction ? "active" : "delivered");
41971 +       return buf;
41972 +}
41973 +
41974 +static char *print_binder_work(char *buf, char *end, const char *prefix,
41975 +       const char *transaction_prefix, struct binder_work *w)
41976 +{
41977 +       struct binder_node *node;
41978 +       struct binder_transaction *t;
41979 +
41980 +       switch (w->type) {
41981 +       case BINDER_WORK_TRANSACTION:
41982 +               t = container_of(w, struct binder_transaction, work);
41983 +               buf = print_binder_transaction(buf, end, transaction_prefix, t);
41984 +               break;
41985 +       case BINDER_WORK_TRANSACTION_COMPLETE:
41986 +               buf += snprintf(buf, end - buf,
41987 +                               "%stransaction complete\n", prefix);
41988 +               break;
41989 +       case BINDER_WORK_NODE:
41990 +               node = container_of(w, struct binder_node, work);
41991 +               buf += snprintf(buf, end - buf, "%snode work %d: u%p c%p\n",
41992 +                               prefix, node->debug_id, node->ptr, node->cookie);
41993 +               break;
41994 +       case BINDER_WORK_DEAD_BINDER:
41995 +               buf += snprintf(buf, end - buf, "%shas dead binder\n", prefix);
41996 +               break;
41997 +       case BINDER_WORK_DEAD_BINDER_AND_CLEAR:
41998 +               buf += snprintf(buf, end - buf,
41999 +                               "%shas cleared dead binder\n", prefix);
42000 +               break;
42001 +       case BINDER_WORK_CLEAR_DEATH_NOTIFICATION:
42002 +               buf += snprintf(buf, end - buf,
42003 +                               "%shas cleared death notification\n", prefix);
42004 +               break;
42005 +       default:
42006 +               buf += snprintf(buf, end - buf, "%sunknown work: type %d\n",
42007 +                               prefix, w->type);
42008 +               break;
42009 +       }
42010 +       return buf;
42011 +}
42012 +
42013 +static char *print_binder_thread(char *buf, char *end, struct binder_thread *thread, int print_always)
42014 +{
42015 +       struct binder_transaction *t;
42016 +       struct binder_work *w;
42017 +       char *start_buf = buf;
42018 +       char *header_buf;
42019 +
42020 +       buf += snprintf(buf, end - buf, "  thread %d: l %02x\n", thread->pid, thread->looper);
42021 +       header_buf = buf;
42022 +       t = thread->transaction_stack;
42023 +       while (t) {
42024 +               if (buf >= end)
42025 +                       break;
42026 +               if (t->from == thread) {
42027 +                       buf = print_binder_transaction(buf, end, "    outgoing transaction", t);
42028 +                       t = t->from_parent;
42029 +               } else if (t->to_thread == thread) {
42030 +                       buf = print_binder_transaction(buf, end, "    incoming transaction", t);
42031 +                       t = t->to_parent;
42032 +               } else {
42033 +                       buf = print_binder_transaction(buf, end, "    bad transaction", t);
42034 +                       t = NULL;
42035 +               }
42036 +       }
42037 +       list_for_each_entry(w, &thread->todo, entry) {
42038 +               if (buf >= end)
42039 +                       break;
42040 +               buf = print_binder_work(buf, end, "    ",
42041 +                                       "    pending transaction", w);
42042 +       }
42043 +       if (!print_always && buf == header_buf)
42044 +               buf = start_buf;
42045 +       return buf;
42046 +}
42047 +
42048 +static char *print_binder_node(char *buf, char *end, struct binder_node *node)
42049 +{
42050 +       struct binder_ref *ref;
42051 +       struct hlist_node *pos;
42052 +       struct binder_work *w;
42053 +       int count;
42054 +       count = 0;
42055 +       hlist_for_each_entry(ref, pos, &node->refs, node_entry)
42056 +               count++;
42057 +
42058 +       buf += snprintf(buf, end - buf, "  node %d: u%p c%p hs %d hw %d ls %d lw %d is %d iw %d",
42059 +                       node->debug_id, node->ptr, node->cookie,
42060 +                       node->has_strong_ref, node->has_weak_ref,
42061 +                       node->local_strong_refs, node->local_weak_refs,
42062 +                       node->internal_strong_refs, count);
42063 +       if (buf >= end)
42064 +               return buf;
42065 +       if (count) {
42066 +               buf += snprintf(buf, end - buf, " proc");
42067 +               if (buf >= end)
42068 +                       return buf;
42069 +               hlist_for_each_entry(ref, pos, &node->refs, node_entry) {
42070 +                       buf += snprintf(buf, end - buf, " %d", ref->proc->pid);
42071 +                       if (buf >= end)
42072 +                               return buf;
42073 +               }
42074 +       }
42075 +       buf += snprintf(buf, end - buf, "\n");
42076 +       list_for_each_entry(w, &node->async_todo, entry) {
42077 +               if (buf >= end)
42078 +                       break;
42079 +               buf = print_binder_work(buf, end, "    ",
42080 +                                       "    pending async transaction", w);
42081 +       }
42082 +       return buf;
42083 +}
42084 +
42085 +static char *print_binder_ref(char *buf, char *end, struct binder_ref *ref)
42086 +{
42087 +       buf += snprintf(buf, end - buf, "  ref %d: desc %d %snode %d s %d w %d d %p\n",
42088 +                       ref->debug_id, ref->desc, ref->node->proc ? "" : "dead ",
42089 +                       ref->node->debug_id, ref->strong, ref->weak, ref->death);
42090 +       return buf;
42091 +}
42092 +
42093 +static char *print_binder_proc(char *buf, char *end, struct binder_proc *proc, int print_all)
42094 +{
42095 +       struct binder_work *w;
42096 +       struct rb_node *n;
42097 +       char *start_buf = buf;
42098 +       char *header_buf;
42099 +
42100 +       buf += snprintf(buf, end - buf, "proc %d\n", proc->pid);
42101 +       header_buf = buf;
42102 +
42103 +       for (n = rb_first(&proc->threads); n != NULL && buf < end; n = rb_next(n))
42104 +               buf = print_binder_thread(buf, end, rb_entry(n, struct binder_thread, rb_node), print_all);
42105 +       for (n = rb_first(&proc->nodes); n != NULL && buf < end; n = rb_next(n)) {
42106 +               struct binder_node *node = rb_entry(n, struct binder_node, rb_node);
42107 +               if (print_all || node->has_async_transaction)
42108 +                       buf = print_binder_node(buf, end, node);
42109 +       }
42110 +       if (print_all) {
42111 +               for (n = rb_first(&proc->refs_by_desc); n != NULL && buf < end; n = rb_next(n))
42112 +                       buf = print_binder_ref(buf, end, rb_entry(n, struct binder_ref, rb_node_desc));
42113 +       }
42114 +       for (n = rb_first(&proc->allocated_buffers); n != NULL && buf < end; n = rb_next(n))
42115 +               buf = print_binder_buffer(buf, end, "  buffer", rb_entry(n, struct binder_buffer, rb_node));
42116 +       list_for_each_entry(w, &proc->todo, entry) {
42117 +               if (buf >= end)
42118 +                       break;
42119 +               buf = print_binder_work(buf, end, "  ",
42120 +                                       "  pending transaction", w);
42121 +       }
42122 +       list_for_each_entry(w, &proc->delivered_death, entry) {
42123 +               if (buf >= end)
42124 +                       break;
42125 +               buf += snprintf(buf, end - buf, "  has delivered dead binder\n");
42126 +               break;
42127 +       }
42128 +       if (!print_all && buf == header_buf)
42129 +               buf = start_buf;
42130 +       return buf;
42131 +}
42132 +
42133 +static const char *binder_return_strings[] = {
42134 +       "BR_ERROR",
42135 +       "BR_OK",
42136 +       "BR_TRANSACTION",
42137 +       "BR_REPLY",
42138 +       "BR_ACQUIRE_RESULT",
42139 +       "BR_DEAD_REPLY",
42140 +       "BR_TRANSACTION_COMPLETE",
42141 +       "BR_INCREFS",
42142 +       "BR_ACQUIRE",
42143 +       "BR_RELEASE",
42144 +       "BR_DECREFS",
42145 +       "BR_ATTEMPT_ACQUIRE",
42146 +       "BR_NOOP",
42147 +       "BR_SPAWN_LOOPER",
42148 +       "BR_FINISHED",
42149 +       "BR_DEAD_BINDER",
42150 +       "BR_CLEAR_DEATH_NOTIFICATION_DONE",
42151 +       "BR_FAILED_REPLY"
42152 +};
42153 +
42154 +static const char *binder_command_strings[] = {
42155 +       "BC_TRANSACTION",
42156 +       "BC_REPLY",
42157 +       "BC_ACQUIRE_RESULT",
42158 +       "BC_FREE_BUFFER",
42159 +       "BC_INCREFS",
42160 +       "BC_ACQUIRE",
42161 +       "BC_RELEASE",
42162 +       "BC_DECREFS",
42163 +       "BC_INCREFS_DONE",
42164 +       "BC_ACQUIRE_DONE",
42165 +       "BC_ATTEMPT_ACQUIRE",
42166 +       "BC_REGISTER_LOOPER",
42167 +       "BC_ENTER_LOOPER",
42168 +       "BC_EXIT_LOOPER",
42169 +       "BC_REQUEST_DEATH_NOTIFICATION",
42170 +       "BC_CLEAR_DEATH_NOTIFICATION",
42171 +       "BC_DEAD_BINDER_DONE"
42172 +};
42173 +
42174 +static const char *binder_objstat_strings[] = {
42175 +       "proc",
42176 +       "thread",
42177 +       "node",
42178 +       "ref",
42179 +       "death",
42180 +       "transaction",
42181 +       "transaction_complete"
42182 +};
42183 +
42184 +static char *print_binder_stats(char *buf, char *end, const char *prefix, struct binder_stats *stats)
42185 +{
42186 +       int i;
42187 +
42188 +       BUILD_BUG_ON(ARRAY_SIZE(stats->bc) != ARRAY_SIZE(binder_command_strings));
42189 +       for (i = 0; i < ARRAY_SIZE(stats->bc); i++) {
42190 +               if (stats->bc[i])
42191 +                       buf += snprintf(buf, end - buf, "%s%s: %d\n", prefix,
42192 +                                       binder_command_strings[i], stats->bc[i]);
42193 +               if (buf >= end)
42194 +                       return buf;
42195 +       }
42196 +
42197 +       BUILD_BUG_ON(ARRAY_SIZE(stats->br) != ARRAY_SIZE(binder_return_strings));
42198 +       for (i = 0; i < ARRAY_SIZE(stats->br); i++) {
42199 +               if (stats->br[i])
42200 +                       buf += snprintf(buf, end - buf, "%s%s: %d\n", prefix,
42201 +                                       binder_return_strings[i], stats->br[i]);
42202 +               if (buf >= end)
42203 +                       return buf;
42204 +       }
42205 +
42206 +       BUILD_BUG_ON(ARRAY_SIZE(stats->obj_created) != ARRAY_SIZE(binder_objstat_strings));
42207 +       BUILD_BUG_ON(ARRAY_SIZE(stats->obj_created) != ARRAY_SIZE(stats->obj_deleted));
42208 +       for (i = 0; i < ARRAY_SIZE(stats->obj_created); i++) {
42209 +               if (stats->obj_created[i] || stats->obj_deleted[i])
42210 +                       buf += snprintf(buf, end - buf, "%s%s: active %d total %d\n", prefix,
42211 +                                       binder_objstat_strings[i],
42212 +                                       stats->obj_created[i] - stats->obj_deleted[i],
42213 +                                       stats->obj_created[i]);
42214 +               if (buf >= end)
42215 +                       return buf;
42216 +       }
42217 +       return buf;
42218 +}
42219 +
42220 +static char *print_binder_proc_stats(char *buf, char *end, struct binder_proc *proc)
42221 +{
42222 +       struct binder_work *w;
42223 +       struct rb_node *n;
42224 +       int count, strong, weak;
42225 +
42226 +       buf += snprintf(buf, end - buf, "proc %d\n", proc->pid);
42227 +       if (buf >= end)
42228 +               return buf;
42229 +       count = 0;
42230 +       for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n))
42231 +               count++;
42232 +       buf += snprintf(buf, end - buf, "  threads: %d\n", count);
42233 +       if (buf >= end)
42234 +               return buf;
42235 +       buf += snprintf(buf, end - buf, "  requested threads: %d+%d/%d\n"
42236 +                       "  ready threads %d\n"
42237 +                       "  free async space %d\n", proc->requested_threads,
42238 +                       proc->requested_threads_started, proc->max_threads,
42239 +                       proc->ready_threads, proc->free_async_space);
42240 +       if (buf >= end)
42241 +               return buf;
42242 +       count = 0;
42243 +       for (n = rb_first(&proc->nodes); n != NULL; n = rb_next(n))
42244 +               count++;
42245 +       buf += snprintf(buf, end - buf, "  nodes: %d\n", count);
42246 +       if (buf >= end)
42247 +               return buf;
42248 +       count = 0;
42249 +       strong = 0;
42250 +       weak = 0;
42251 +       for (n = rb_first(&proc->refs_by_desc); n != NULL; n = rb_next(n)) {
42252 +               struct binder_ref *ref = rb_entry(n, struct binder_ref, rb_node_desc);
42253 +               count++;
42254 +               strong += ref->strong;
42255 +               weak += ref->weak;
42256 +       }
42257 +       buf += snprintf(buf, end - buf, "  refs: %d s %d w %d\n", count, strong, weak);
42258 +       if (buf >= end)
42259 +               return buf;
42260 +
42261 +       count = 0;
42262 +       for (n = rb_first(&proc->allocated_buffers); n != NULL; n = rb_next(n))
42263 +               count++;
42264 +       buf += snprintf(buf, end - buf, "  buffers: %d\n", count);
42265 +       if (buf >= end)
42266 +               return buf;
42267 +
42268 +       count = 0;
42269 +       list_for_each_entry(w, &proc->todo, entry) {
42270 +               switch (w->type) {
42271 +               case BINDER_WORK_TRANSACTION:
42272 +                       count++;
42273 +                       break;
42274 +               default:
42275 +                       break;
42276 +               }
42277 +       }
42278 +       buf += snprintf(buf, end - buf, "  pending transactions: %d\n", count);
42279 +       if (buf >= end)
42280 +               return buf;
42281 +
42282 +       buf = print_binder_stats(buf, end, "  ", &proc->stats);
42283 +
42284 +       return buf;
42285 +}
42286 +
42287 +
42288 +static int binder_read_proc_state(
42289 +       char *page, char **start, off_t off, int count, int *eof, void *data)
42290 +{
42291 +       struct binder_proc *proc;
42292 +       struct hlist_node *pos;
42293 +       struct binder_node *node;
42294 +       int len = 0;
42295 +       char *buf = page;
42296 +       char *end = page + PAGE_SIZE;
42297 +       int do_lock = !binder_debug_no_lock;
42298 +
42299 +       if (off)
42300 +               return 0;
42301 +
42302 +       if (do_lock)
42303 +               mutex_lock(&binder_lock);
42304 +
42305 +       buf += snprintf(buf, end - buf, "binder state:\n");
42306 +
42307 +       if (!hlist_empty(&binder_dead_nodes))
42308 +               buf += snprintf(buf, end - buf, "dead nodes:\n");
42309 +       hlist_for_each_entry(node, pos, &binder_dead_nodes, dead_node) {
42310 +               if (buf >= end)
42311 +                       break;
42312 +               buf = print_binder_node(buf, end, node);
42313 +       }
42314 +
42315 +       hlist_for_each_entry(proc, pos, &binder_procs, proc_node) {
42316 +               if (buf >= end)
42317 +                       break;
42318 +               buf = print_binder_proc(buf, end, proc, 1);
42319 +       }
42320 +       if (do_lock)
42321 +               mutex_unlock(&binder_lock);
42322 +       if (buf > page + PAGE_SIZE)
42323 +               buf = page + PAGE_SIZE;
42324 +
42325 +       *start = page + off;
42326 +
42327 +       len = buf - page;
42328 +       if (len > off)
42329 +               len -= off;
42330 +       else
42331 +               len = 0;
42332 +
42333 +       return len < count ? len  : count;
42334 +}
42335 +
42336 +static int binder_read_proc_stats(
42337 +       char *page, char **start, off_t off, int count, int *eof, void *data)
42338 +{
42339 +       struct binder_proc *proc;
42340 +       struct hlist_node *pos;
42341 +       int len = 0;
42342 +       char *p = page;
42343 +       int do_lock = !binder_debug_no_lock;
42344 +
42345 +       if (off)
42346 +               return 0;
42347 +
42348 +       if (do_lock)
42349 +               mutex_lock(&binder_lock);
42350 +
42351 +       p += snprintf(p, PAGE_SIZE, "binder stats:\n");
42352 +
42353 +       p = print_binder_stats(p, page + PAGE_SIZE, "", &binder_stats);
42354 +
42355 +       hlist_for_each_entry(proc, pos, &binder_procs, proc_node) {
42356 +               if (p >= page + PAGE_SIZE)
42357 +                       break;
42358 +               p = print_binder_proc_stats(p, page + PAGE_SIZE, proc);
42359 +       }
42360 +       if (do_lock)
42361 +               mutex_unlock(&binder_lock);
42362 +       if (p > page + PAGE_SIZE)
42363 +               p = page + PAGE_SIZE;
42364 +
42365 +       *start = page + off;
42366 +
42367 +       len = p - page;
42368 +       if (len > off)
42369 +               len -= off;
42370 +       else
42371 +               len = 0;
42372 +
42373 +       return len < count ? len  : count;
42374 +}
42375 +
42376 +static int binder_read_proc_transactions(
42377 +       char *page, char **start, off_t off, int count, int *eof, void *data)
42378 +{
42379 +       struct binder_proc *proc;
42380 +       struct hlist_node *pos;
42381 +       int len = 0;
42382 +       char *buf = page;
42383 +       char *end = page + PAGE_SIZE;
42384 +       int do_lock = !binder_debug_no_lock;
42385 +
42386 +       if (off)
42387 +               return 0;
42388 +
42389 +       if (do_lock)
42390 +               mutex_lock(&binder_lock);
42391 +
42392 +       buf += snprintf(buf, end - buf, "binder transactions:\n");
42393 +       hlist_for_each_entry(proc, pos, &binder_procs, proc_node) {
42394 +               if (buf >= end)
42395 +                       break;
42396 +               buf = print_binder_proc(buf, end, proc, 0);
42397 +       }
42398 +       if (do_lock)
42399 +               mutex_unlock(&binder_lock);
42400 +       if (buf > page + PAGE_SIZE)
42401 +               buf = page + PAGE_SIZE;
42402 +
42403 +       *start = page + off;
42404 +
42405 +       len = buf - page;
42406 +       if (len > off)
42407 +               len -= off;
42408 +       else
42409 +               len = 0;
42410 +
42411 +       return len < count ? len  : count;
42412 +}
42413 +
42414 +static int binder_read_proc_proc(
42415 +       char *page, char **start, off_t off, int count, int *eof, void *data)
42416 +{
42417 +       struct binder_proc *proc = data;
42418 +       int len = 0;
42419 +       char *p = page;
42420 +       int do_lock = !binder_debug_no_lock;
42421 +
42422 +       if (off)
42423 +               return 0;
42424 +
42425 +       if (do_lock)
42426 +               mutex_lock(&binder_lock);
42427 +       p += snprintf(p, PAGE_SIZE, "binder proc state:\n");
42428 +       p = print_binder_proc(p, page + PAGE_SIZE, proc, 1);
42429 +       if (do_lock)
42430 +               mutex_unlock(&binder_lock);
42431 +
42432 +       if (p > page + PAGE_SIZE)
42433 +               p = page + PAGE_SIZE;
42434 +       *start = page + off;
42435 +
42436 +       len = p - page;
42437 +       if (len > off)
42438 +               len -= off;
42439 +       else
42440 +               len = 0;
42441 +
42442 +       return len < count ? len  : count;
42443 +}
42444 +
42445 +static char *print_binder_transaction_log_entry(char *buf, char *end, struct binder_transaction_log_entry *e)
42446 +{
42447 +       buf += snprintf(buf, end - buf, "%d: %s from %d:%d to %d:%d node %d handle %d size %d:%d\n",
42448 +                       e->debug_id, (e->call_type == 2) ? "reply" :
42449 +                       ((e->call_type == 1) ? "async" : "call "), e->from_proc,
42450 +                       e->from_thread, e->to_proc, e->to_thread, e->to_node,
42451 +                       e->target_handle, e->data_size, e->offsets_size);
42452 +       return buf;
42453 +}
42454 +
42455 +static int binder_read_proc_transaction_log(
42456 +       char *page, char **start, off_t off, int count, int *eof, void *data)
42457 +{
42458 +       struct binder_transaction_log *log = data;
42459 +       int len = 0;
42460 +       int i;
42461 +       char *buf = page;
42462 +       char *end = page + PAGE_SIZE;
42463 +
42464 +       if (off)
42465 +               return 0;
42466 +
42467 +       if (log->full) {
42468 +               for (i = log->next; i < ARRAY_SIZE(log->entry); i++) {
42469 +                       if (buf >= end)
42470 +                               break;
42471 +                       buf = print_binder_transaction_log_entry(buf, end, &log->entry[i]);
42472 +               }
42473 +       }
42474 +       for (i = 0; i < log->next; i++) {
42475 +               if (buf >= end)
42476 +                       break;
42477 +               buf = print_binder_transaction_log_entry(buf, end, &log->entry[i]);
42478 +       }
42479 +
42480 +       *start = page + off;
42481 +
42482 +       len = buf - page;
42483 +       if (len > off)
42484 +               len -= off;
42485 +       else
42486 +               len = 0;
42487 +
42488 +       return len < count ? len  : count;
42489 +}
42490 +
42491 +static struct file_operations binder_fops = {
42492 +       .owner = THIS_MODULE,
42493 +       .poll = binder_poll,
42494 +       .unlocked_ioctl = binder_ioctl,
42495 +       .mmap = binder_mmap,
42496 +       .open = binder_open,
42497 +       .flush = binder_flush,
42498 +       .release = binder_release,
42499 +};
42500 +
42501 +static struct miscdevice binder_miscdev = {
42502 +       .minor = MISC_DYNAMIC_MINOR,
42503 +       .name = "binder",
42504 +       .fops = &binder_fops
42505 +};
42506 +
42507 +static int __init binder_init(void)
42508 +{
42509 +       int ret;
42510 +
42511 +       binder_proc_dir_entry_root = proc_mkdir("binder", NULL);
42512 +       if (binder_proc_dir_entry_root)
42513 +               binder_proc_dir_entry_proc = proc_mkdir("proc", binder_proc_dir_entry_root);
42514 +       ret = misc_register(&binder_miscdev);
42515 +       if (binder_proc_dir_entry_root) {
42516 +               create_proc_read_entry("state", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_state, NULL);
42517 +               create_proc_read_entry("stats", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_stats, NULL);
42518 +               create_proc_read_entry("transactions", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_transactions, NULL);
42519 +               create_proc_read_entry("transaction_log", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_transaction_log, &binder_transaction_log);
42520 +               create_proc_read_entry("failed_transaction_log", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_transaction_log, &binder_transaction_log_failed);
42521 +       }
42522 +       return ret;
42523 +}
42524 +
42525 +device_initcall(binder_init);
42526 +
42527 --- /dev/null
42528 +++ b/drivers/android/Kconfig
42529 @@ -0,0 +1,93 @@
42530 +menu "Android"
42531 +
42532 +config ANDROID_BINDER_IPC
42533 +       tristate "Binder IPC Driver"
42534 +       default y
42535 +
42536 +config ANDROID_POWER
42537 +       bool "Android power driver"
42538 +       depends on PM && RTC_CLASS
42539 +       default n
42540 +
42541 +config ANDROID_POWER_STAT
42542 +       bool "Android power driver lock stats"
42543 +       depends on ANDROID_POWER
42544 +       default y
42545 +
42546 +config ANDROID_POWER_ALARM
42547 +       bool "Android alarm driver"
42548 +       depends on ANDROID_POWER
42549 +       default y
42550 +
42551 +config ANDROID_LOGGER
42552 +       bool "Android log driver"
42553 +       default y
42554 +
42555 +config ANDROID_RAM_CONSOLE
42556 +       bool "RAM buffer console"
42557 +       default n
42558 +
42559 +config ANDROID_RAM_CONSOLE_ENABLE_VERBOSE
42560 +       bool "Enable verbose console messages"
42561 +       default y
42562 +       depends on ANDROID_RAM_CONSOLE
42563 +
42564 +menuconfig ANDROID_RAM_CONSOLE_ERROR_CORRECTION
42565 +       bool "Enable error correction"
42566 +       default n
42567 +       depends on ANDROID_RAM_CONSOLE
42568 +       select REED_SOLOMON
42569 +       select REED_SOLOMON_ENC8
42570 +       select REED_SOLOMON_DEC8
42571 +
42572 +if ANDROID_RAM_CONSOLE_ERROR_CORRECTION
42573 +
42574 +config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE
42575 +       int "Data data size"
42576 +       default 128
42577 +       help
42578 +         Must be a power of 2.
42579 +
42580 +config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE
42581 +       int "ECC size"
42582 +       default 16
42583 +
42584 +config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE
42585 +       int "Symbol size"
42586 +       default 8
42587 +
42588 +config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL
42589 +       hex "Polynomial"
42590 +       default 0x19 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 4)
42591 +       default 0x29 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 5)
42592 +       default 0x61 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 6)
42593 +       default 0x89 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 7)
42594 +       default 0x11d if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 8)
42595 +
42596 +endif #ANDROID_RAM_CONSOLE_ERROR_CORRECTION
42597 +
42598 +config ANDROID_RAM_CONSOLE_EARLY_INIT
42599 +       bool "Start ram console early"
42600 +       default n
42601 +       depends on ANDROID_RAM_CONSOLE
42602 +
42603 +config ANDROID_RAM_CONSOLE_EARLY_ADDR
42604 +       hex "RAM console virtual address"
42605 +       default 0
42606 +       depends on ANDROID_RAM_CONSOLE_EARLY_INIT
42607 +
42608 +config ANDROID_RAM_CONSOLE_EARLY_SIZE
42609 +       hex "RAM console buffer size"
42610 +       default 0
42611 +       depends on ANDROID_RAM_CONSOLE_EARLY_INIT
42612 +
42613 +config ANDROID_TIMED_GPIO
42614 +       bool "Android timed gpio driver"
42615 +       depends on GENERIC_GPIO
42616 +       default y
42617 +
42618 +config ANDROID_PARANOID_NETWORK
42619 +       bool "Only allow certain groups to create sockets"
42620 +       default y
42621 +
42622 +endmenu
42623 --- /dev/null
42624 +++ b/drivers/android/logger.c
42625 @@ -0,0 +1,607 @@
42626 +/*
42627 + * drivers/android/logger.c
42628 + *
42629 + * Android Logging Subsystem
42630 + *
42631 + * Copyright (C) 2007-2008 Google, Inc.
42632 + *
42633 + * Robert Love <rlove@google.com>
42634 + *
42635 + * This software is licensed under the terms of the GNU General Public
42636 + * License version 2, as published by the Free Software Foundation, and
42637 + * may be copied, distributed, and modified under those terms.
42638 + *
42639 + * This program is distributed in the hope that it will be useful,
42640 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
42641 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
42642 + * GNU General Public License for more details.
42643 + */
42644 +
42645 +#include <linux/module.h>
42646 +#include <linux/fs.h>
42647 +#include <linux/miscdevice.h>
42648 +#include <linux/uaccess.h>
42649 +#include <linux/poll.h>
42650 +#include <linux/time.h>
42651 +#include <linux/logger.h>
42652 +
42653 +#include <asm/ioctls.h>
42654 +
42655 +/*
42656 + * struct logger_log - represents a specific log, such as 'main' or 'radio'
42657 + *
42658 + * This structure lives from module insertion until module removal, so it does
42659 + * not need additional reference counting. The structure is protected by the
42660 + * mutex 'mutex'.
42661 + */
42662 +struct logger_log {
42663 +       unsigned char *         buffer; /* the ring buffer itself */
42664 +       struct miscdevice       misc;   /* misc device representing the log */
42665 +       wait_queue_head_t       wq;     /* wait queue for readers */
42666 +       struct list_head        readers; /* this log's readers */
42667 +       struct mutex            mutex;  /* mutex protecting buffer */
42668 +       size_t                  w_off;  /* current write head offset */
42669 +       size_t                  head;   /* new readers start here */
42670 +       size_t                  size;   /* size of the log */
42671 +};
42672 +
42673 +/*
42674 + * struct logger_reader - a logging device open for reading
42675 + *
42676 + * This object lives from open to release, so we don't need additional
42677 + * reference counting. The structure is protected by log->mutex.
42678 + */
42679 +struct logger_reader {
42680 +       struct logger_log *     log;    /* associated log */
42681 +       struct list_head        list;   /* entry in logger_log's list */
42682 +       size_t                  r_off;  /* current read head offset */
42683 +};
42684 +
42685 +/* logger_offset - returns index 'n' into the log via (optimized) modulus */
42686 +#define logger_offset(n)       ((n) & (log->size - 1))
42687 +
42688 +/*
42689 + * file_get_log - Given a file structure, return the associated log
42690 + *
42691 + * This isn't aesthetic. We have several goals:
42692 + *
42693 + *     1) Need to quickly obtain the associated log during an I/O operation
42694 + *     2) Readers need to maintain state (logger_reader)
42695 + *     3) Writers need to be very fast (open() should be a near no-op)
42696 + *
42697 + * In the reader case, we can trivially go file->logger_reader->logger_log.
42698 + * For a writer, we don't want to maintain a logger_reader, so we just go
42699 + * file->logger_log. Thus what file->private_data points at depends on whether
42700 + * or not the file was opened for reading. This function hides that dirtiness.
42701 + */
42702 +static inline struct logger_log * file_get_log(struct file *file)
42703 +{
42704 +       if (file->f_mode & FMODE_READ) {
42705 +               struct logger_reader *reader = file->private_data;
42706 +               return reader->log;
42707 +       } else
42708 +               return file->private_data;
42709 +}
42710 +
42711 +/*
42712 + * get_entry_len - Grabs the length of the payload of the next entry starting
42713 + * from 'off'.
42714 + *
42715 + * Caller needs to hold log->mutex.
42716 + */
42717 +static __u32 get_entry_len(struct logger_log *log, size_t off)
42718 +{
42719 +       __u16 val;
42720 +
42721 +       switch (log->size - off) {
42722 +       case 1:
42723 +               memcpy(&val, log->buffer + off, 1);
42724 +               memcpy(((char *) &val) + 1, log->buffer, 1);
42725 +               break;
42726 +       default:
42727 +               memcpy(&val, log->buffer + off, 2);
42728 +       }
42729 +
42730 +       return sizeof(struct logger_entry) + val;
42731 +}
42732 +
42733 +/*
42734 + * do_read_log_to_user - reads exactly 'count' bytes from 'log' into the
42735 + * user-space buffer 'buf'. Returns 'count' on success.
42736 + *
42737 + * Caller must hold log->mutex.
42738 + */
42739 +static ssize_t do_read_log_to_user(struct logger_log *log,
42740 +                                  struct logger_reader *reader,
42741 +                                  char __user *buf,
42742 +                                  size_t count)
42743 +{
42744 +       size_t len;
42745 +
42746 +       /*
42747 +        * We read from the log in two disjoint operations. First, we read from
42748 +        * the current read head offset up to 'count' bytes or to the end of
42749 +        * the log, whichever comes first.
42750 +        */
42751 +       len = min(count, log->size - reader->r_off);
42752 +       if (copy_to_user(buf, log->buffer + reader->r_off, len))
42753 +               return -EFAULT;
42754 +
42755 +       /*
42756 +        * Second, we read any remaining bytes, starting back at the head of
42757 +        * the log.
42758 +        */
42759 +       if (count != len)
42760 +               if (copy_to_user(buf + len, log->buffer, count - len))
42761 +                       return -EFAULT;
42762 +
42763 +       reader->r_off = logger_offset(reader->r_off + count);
42764 +
42765 +       return count;
42766 +}
42767 +
42768 +/*
42769 + * logger_read - our log's read() method
42770 + *
42771 + * Behavior:
42772 + *
42773 + *     - O_NONBLOCK works
42774 + *     - If there are no log entries to read, blocks until log is written to
42775 + *     - Atomically reads exactly one log entry
42776 + *
42777 + * Optimal read size is LOGGER_ENTRY_MAX_LEN. Will set errno to EINVAL if read
42778 + * buffer is insufficient to hold next entry.
42779 + */
42780 +static ssize_t logger_read(struct file *file, char __user *buf,
42781 +                          size_t count, loff_t *pos)
42782 +{
42783 +       struct logger_reader *reader = file->private_data;
42784 +       struct logger_log *log = reader->log;
42785 +       ssize_t ret;
42786 +       DEFINE_WAIT(wait);
42787 +
42788 +start:
42789 +       while (1) {
42790 +               prepare_to_wait(&log->wq, &wait, TASK_INTERRUPTIBLE);
42791 +
42792 +               mutex_lock(&log->mutex);
42793 +               ret = (log->w_off == reader->r_off);
42794 +               mutex_unlock(&log->mutex);
42795 +               if (!ret)
42796 +                       break;
42797 +
42798 +               if (file->f_flags & O_NONBLOCK) {
42799 +                       ret = -EAGAIN;
42800 +                       break;
42801 +               }
42802 +
42803 +               if (signal_pending(current)) {
42804 +                       ret = -EINTR;
42805 +                       break;
42806 +               }
42807 +
42808 +               schedule();
42809 +       }
42810 +
42811 +       finish_wait(&log->wq, &wait);
42812 +       if (ret)
42813 +               return ret;
42814 +
42815 +       mutex_lock(&log->mutex);
42816 +
42817 +       /* is there still something to read or did we race? */
42818 +       if (unlikely(log->w_off == reader->r_off)) {
42819 +               mutex_unlock(&log->mutex);
42820 +               goto start;
42821 +       }
42822 +
42823 +       /* get the size of the next entry */
42824 +       ret = get_entry_len(log, reader->r_off);
42825 +       if (count < ret) {
42826 +               ret = -EINVAL;
42827 +               goto out;
42828 +       }
42829 +
42830 +       /* get exactly one entry from the log */
42831 +       ret = do_read_log_to_user(log, reader, buf, ret);
42832 +
42833 +out:
42834 +       mutex_unlock(&log->mutex);
42835 +
42836 +       return ret;
42837 +}
42838 +
42839 +/*
42840 + * get_next_entry - return the offset of the first valid entry at least 'len'
42841 + * bytes after 'off'.
42842 + *
42843 + * Caller must hold log->mutex.
42844 + */
42845 +static size_t get_next_entry(struct logger_log *log, size_t off, size_t len)
42846 +{
42847 +       size_t count = 0;
42848 +
42849 +       do {
42850 +               size_t nr = get_entry_len(log, off);
42851 +               off = logger_offset(off + nr);
42852 +               count += nr;
42853 +       } while (count < len);
42854 +
42855 +       return off;
42856 +}
42857 +
42858 +/*
42859 + * clock_interval - is a < c < b in mod-space? Put another way, does the line
42860 + * from a to b cross c?
42861 + */
42862 +static inline int clock_interval(size_t a, size_t b, size_t c)
42863 +{
42864 +       if (b < a) {
42865 +               if (a < c || b >= c)
42866 +                       return 1;
42867 +       } else {
42868 +               if (a < c && b >= c)
42869 +                       return 1;
42870 +       }
42871 +
42872 +       return 0;
42873 +}
42874 +
42875 +/*
42876 + * fix_up_readers - walk the list of all readers and "fix up" any who were
42877 + * lapped by the writer; also do the same for the default "start head".
42878 + * We do this by "pulling forward" the readers and start head to the first
42879 + * entry after the new write head.
42880 + *
42881 + * The caller needs to hold log->mutex.
42882 + */
42883 +static void fix_up_readers(struct logger_log *log, size_t len)
42884 +{
42885 +       size_t old = log->w_off;
42886 +       size_t new = logger_offset(old + len);
42887 +       struct logger_reader *reader;
42888 +
42889 +       if (clock_interval(old, new, log->head))
42890 +               log->head = get_next_entry(log, log->head, len);
42891 +
42892 +       list_for_each_entry(reader, &log->readers, list)
42893 +               if (clock_interval(old, new, reader->r_off))
42894 +                       reader->r_off = get_next_entry(log, reader->r_off, len);
42895 +}
42896 +
42897 +/*
42898 + * do_write_log - writes 'len' bytes from 'buf' to 'log'
42899 + *
42900 + * The caller needs to hold log->mutex.
42901 + */
42902 +static void do_write_log(struct logger_log *log, const void *buf, size_t count)
42903 +{
42904 +       size_t len;
42905 +
42906 +       len = min(count, log->size - log->w_off);
42907 +       memcpy(log->buffer + log->w_off, buf, len);
42908 +
42909 +       if (count != len)
42910 +               memcpy(log->buffer, buf + len, count - len);
42911 +
42912 +       log->w_off = logger_offset(log->w_off + count);
42913 +
42914 +}
42915 +
42916 +/*
42917 + * do_write_log_user - writes 'len' bytes from the user-space buffer 'buf' to
42918 + * the log 'log'
42919 + *
42920 + * The caller needs to hold log->mutex.
42921 + *
42922 + * Returns 'count' on success, negative error code on failure.
42923 + */
42924 +static ssize_t do_write_log_from_user(struct logger_log *log,
42925 +                                     const void __user *buf, size_t count)
42926 +{
42927 +       size_t len;
42928 +
42929 +       len = min(count, log->size - log->w_off);
42930 +       if (len && copy_from_user(log->buffer + log->w_off, buf, len))
42931 +               return -EFAULT;
42932 +
42933 +       if (count != len)
42934 +               if (copy_from_user(log->buffer, buf + len, count - len))
42935 +                       return -EFAULT;
42936 +
42937 +       log->w_off = logger_offset(log->w_off + count);
42938 +
42939 +       return count;
42940 +}
42941 +
42942 +/*
42943 + * logger_aio_write - our write method, implementing support for write(),
42944 + * writev(), and aio_write(). Writes are our fast path, and we try to optimize
42945 + * them above all else.
42946 + */
42947 +ssize_t logger_aio_write(struct kiocb *iocb, const struct iovec *iov,
42948 +                        unsigned long nr_segs, loff_t ppos)
42949 +{
42950 +       struct logger_log *log = file_get_log(iocb->ki_filp);
42951 +       size_t orig = log->w_off;
42952 +       struct logger_entry header;
42953 +       struct timespec now;
42954 +       ssize_t ret = 0;
42955 +
42956 +       now = current_kernel_time();
42957 +
42958 +       header.pid = current->tgid;
42959 +       header.tid = current->pid;
42960 +       header.sec = now.tv_sec;
42961 +       header.nsec = now.tv_nsec;
42962 +       header.len = min_t(size_t, iocb->ki_left, LOGGER_ENTRY_MAX_PAYLOAD);
42963 +
42964 +       /* null writes succeed, return zero */
42965 +       if (unlikely(!header.len))
42966 +               return 0;
42967 +
42968 +       mutex_lock(&log->mutex);
42969 +
42970 +       /*
42971 +        * Fix up any readers, pulling them forward to the first readable
42972 +        * entry after (what will be) the new write offset. We do this now
42973 +        * because if we partially fail, we can end up with clobbered log
42974 +        * entries that encroach on readable buffer.
42975 +        */
42976 +       fix_up_readers(log, sizeof(struct logger_entry) + header.len);
42977 +
42978 +       do_write_log(log, &header, sizeof(struct logger_entry));
42979 +
42980 +       while (nr_segs-- > 0) {
42981 +               size_t len;
42982 +               ssize_t nr;
42983 +
42984 +               /* figure out how much of this vector we can keep */
42985 +               len = min_t(size_t, iov->iov_len, header.len - ret);
42986 +
42987 +               /* write out this segment's payload */
42988 +               nr = do_write_log_from_user(log, iov->iov_base, len);
42989 +               if (unlikely(nr < 0)) {
42990 +                       log->w_off = orig;
42991 +                       mutex_unlock(&log->mutex);
42992 +                       return nr;
42993 +               }
42994 +
42995 +               iov++;
42996 +               ret += nr;
42997 +       }
42998 +
42999 +       mutex_unlock(&log->mutex);
43000 +
43001 +       /* wake up any blocked readers */
43002 +       wake_up_interruptible(&log->wq);
43003 +
43004 +       return ret;
43005 +}
43006 +
43007 +static struct logger_log * get_log_from_minor(int);
43008 +
43009 +/*
43010 + * logger_open - the log's open() file operation
43011 + *
43012 + * Note how near a no-op this is in the write-only case. Keep it that way!
43013 + */
43014 +static int logger_open(struct inode *inode, struct file *file)
43015 +{
43016 +       struct logger_log *log;
43017 +       int ret;
43018 +
43019 +       ret = nonseekable_open(inode, file);
43020 +       if (ret)
43021 +               return ret;
43022 +
43023 +       log = get_log_from_minor(MINOR(inode->i_rdev));
43024 +       if (!log)
43025 +               return -ENODEV;
43026 +
43027 +       if (file->f_mode & FMODE_READ) {
43028 +               struct logger_reader *reader;
43029 +
43030 +               reader = kmalloc(sizeof(struct logger_reader), GFP_KERNEL);
43031 +               if (!reader)
43032 +                       return -ENOMEM;
43033 +
43034 +               reader->log = log;
43035 +               INIT_LIST_HEAD(&reader->list);
43036 +
43037 +               mutex_lock(&log->mutex);
43038 +               reader->r_off = log->head;
43039 +               list_add_tail(&reader->list, &log->readers);
43040 +               mutex_unlock(&log->mutex);
43041 +
43042 +               file->private_data = reader;
43043 +       } else
43044 +               file->private_data = log;
43045 +
43046 +       return 0;
43047 +}
43048 +
43049 +/*
43050 + * logger_release - the log's release file operation
43051 + *
43052 + * Note this is a total no-op in the write-only case. Keep it that way!
43053 + */
43054 +static int logger_release(struct inode *ignored, struct file *file)
43055 +{
43056 +       if (file->f_mode & FMODE_READ) {
43057 +               struct logger_reader *reader = file->private_data;
43058 +               list_del(&reader->list);
43059 +               kfree(reader);
43060 +       }
43061 +
43062 +       return 0;
43063 +}
43064 +
43065 +/*
43066 + * logger_poll - the log's poll file operation, for poll/select/epoll
43067 + *
43068 + * Note we always return POLLOUT, because you can always write() to the log.
43069 + * Note also that, strictly speaking, a return value of POLLIN does not
43070 + * guarantee that the log is readable without blocking, as there is a small
43071 + * chance that the writer can lap the reader in the interim between poll()
43072 + * returning and the read() request.
43073 + */
43074 +static unsigned int logger_poll(struct file *file, poll_table *wait)
43075 +{
43076 +       struct logger_reader *reader;
43077 +       struct logger_log *log;
43078 +       unsigned int ret = POLLOUT | POLLWRNORM;
43079 +
43080 +       if (!(file->f_mode & FMODE_READ))
43081 +               return ret;
43082 +
43083 +       reader = file->private_data;
43084 +       log = reader->log;
43085 +
43086 +       poll_wait(file, &log->wq, wait);
43087 +
43088 +       mutex_lock(&log->mutex);
43089 +       if (log->w_off != reader->r_off)
43090 +               ret |= POLLIN | POLLRDNORM;
43091 +       mutex_unlock(&log->mutex);
43092 +
43093 +       return ret;
43094 +}
43095 +
43096 +static long logger_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
43097 +{
43098 +       struct logger_log *log = file_get_log(file);
43099 +       struct logger_reader *reader;
43100 +       long ret = -ENOTTY;
43101 +
43102 +       mutex_lock(&log->mutex);
43103 +
43104 +       switch (cmd) {
43105 +       case LOGGER_GET_LOG_BUF_SIZE:
43106 +               ret = log->size;
43107 +               break;
43108 +       case LOGGER_GET_LOG_LEN:
43109 +               if (!(file->f_mode & FMODE_READ)) {
43110 +                       ret = -EBADF;
43111 +                       break;
43112 +               }
43113 +               reader = file->private_data;
43114 +               if (log->w_off >= reader->r_off)
43115 +                       ret = log->w_off - reader->r_off;
43116 +               else
43117 +                       ret = (log->size - reader->r_off) + log->w_off;
43118 +               break;
43119 +       case LOGGER_GET_NEXT_ENTRY_LEN:
43120 +               if (!(file->f_mode & FMODE_READ)) {
43121 +                       ret = -EBADF;
43122 +                       break;
43123 +               }
43124 +               reader = file->private_data;
43125 +               if (log->w_off != reader->r_off)
43126 +                       ret = get_entry_len(log, reader->r_off);
43127 +               else
43128 +                       ret = 0;
43129 +               break;
43130 +       case LOGGER_FLUSH_LOG:
43131 +               if (!(file->f_mode & FMODE_WRITE)) {
43132 +                       ret = -EBADF;
43133 +                       break;
43134 +               }
43135 +               list_for_each_entry(reader, &log->readers, list)
43136 +                       reader->r_off = log->w_off;
43137 +               log->head = log->w_off;
43138 +               ret = 0;
43139 +               break;
43140 +       }
43141 +
43142 +       mutex_unlock(&log->mutex);
43143 +
43144 +       return ret;
43145 +}
43146 +
43147 +static struct file_operations logger_fops = {
43148 +       .owner = THIS_MODULE,
43149 +       .read = logger_read,
43150 +       .aio_write = logger_aio_write,
43151 +       .poll = logger_poll,
43152 +       .unlocked_ioctl = logger_ioctl,
43153 +       .compat_ioctl = logger_ioctl,
43154 +       .open = logger_open,
43155 +       .release = logger_release,
43156 +};
43157 +
43158 +/*
43159 + * Defines a log structure with name 'NAME' and a size of 'SIZE' bytes, which
43160 + * must be a power of two, greater than LOGGER_ENTRY_MAX_LEN, and less than
43161 + * LONG_MAX minus LOGGER_ENTRY_MAX_LEN.
43162 + */
43163 +#define DEFINE_LOGGER_DEVICE(VAR, NAME, SIZE) \
43164 +static unsigned char _buf_ ## VAR[SIZE]; \
43165 +static struct logger_log VAR = { \
43166 +       .buffer = _buf_ ## VAR, \
43167 +       .misc = { \
43168 +               .minor = MISC_DYNAMIC_MINOR, \
43169 +               .name = NAME, \
43170 +               .fops = &logger_fops, \
43171 +               .parent = NULL, \
43172 +       }, \
43173 +       .wq = __WAIT_QUEUE_HEAD_INITIALIZER(VAR .wq), \
43174 +       .readers = LIST_HEAD_INIT(VAR .readers), \
43175 +       .mutex = __MUTEX_INITIALIZER(VAR .mutex), \
43176 +       .w_off = 0, \
43177 +       .head = 0, \
43178 +       .size = SIZE, \
43179 +};
43180 +
43181 +DEFINE_LOGGER_DEVICE(log_main, LOGGER_LOG_MAIN, 64*1024)
43182 +DEFINE_LOGGER_DEVICE(log_events, LOGGER_LOG_EVENTS, 256*1024)
43183 +DEFINE_LOGGER_DEVICE(log_radio, LOGGER_LOG_RADIO, 64*1024)
43184 +
43185 +static struct logger_log * get_log_from_minor(int minor)
43186 +{
43187 +       if (log_main.misc.minor == minor)
43188 +               return &log_main;
43189 +       if (log_events.misc.minor == minor)
43190 +               return &log_events;
43191 +       if (log_radio.misc.minor == minor)
43192 +               return &log_radio;
43193 +       return NULL;
43194 +}
43195 +
43196 +static int __init init_log(struct logger_log *log)
43197 +{
43198 +       int ret;
43199 +
43200 +       ret = misc_register(&log->misc);
43201 +       if (unlikely(ret)) {
43202 +               printk(KERN_ERR "logger: failed to register misc "
43203 +                      "device for log '%s'!\n", log->misc.name);
43204 +               return ret;
43205 +       }
43206 +
43207 +       printk(KERN_INFO "logger: created %luK log '%s'\n",
43208 +              (unsigned long) log->size >> 10, log->misc.name);
43209 +
43210 +       return 0;
43211 +}
43212 +
43213 +static int __init logger_init(void)
43214 +{
43215 +       int ret;
43216 +
43217 +       ret = init_log(&log_main);
43218 +       if (unlikely(ret))
43219 +               goto out;
43220 +
43221 +       ret = init_log(&log_events);
43222 +       if (unlikely(ret))
43223 +               goto out;
43224 +
43225 +       ret = init_log(&log_radio);
43226 +       if (unlikely(ret))
43227 +               goto out;
43228 +
43229 +out:
43230 +       return ret;
43231 +}
43232 +device_initcall(logger_init);
43233 --- /dev/null
43234 +++ b/drivers/android/Makefile
43235 @@ -0,0 +1,6 @@
43236 +obj-$(CONFIG_ANDROID_BINDER_IPC)       += binder.o
43237 +obj-$(CONFIG_ANDROID_POWER)            += power.o
43238 +obj-$(CONFIG_ANDROID_POWER_ALARM)              += alarm.o
43239 +obj-$(CONFIG_ANDROID_LOGGER)           += logger.o
43240 +obj-$(CONFIG_ANDROID_RAM_CONSOLE)      += ram_console.o
43241 +obj-$(CONFIG_ANDROID_TIMED_GPIO)       += timed_gpio.o
43242 --- /dev/null
43243 +++ b/drivers/android/power.c
43244 @@ -0,0 +1,1336 @@
43245 +/* drivers/android/power.c
43246 + *
43247 + * Copyright (C) 2005-2008 Google, Inc.
43248 + *
43249 + * This software is licensed under the terms of the GNU General Public
43250 + * License version 2, as published by the Free Software Foundation, and
43251 + * may be copied, distributed, and modified under those terms.
43252 + *
43253 + * This program is distributed in the hope that it will be useful,
43254 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
43255 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
43256 + * GNU General Public License for more details.
43257 + *
43258 + */
43259 +
43260 +#include <linux/list.h>
43261 +#include <linux/module.h>
43262 +#include <linux/miscdevice.h>
43263 +//#include <linux/platform_device.h>
43264 +#include <linux/sysdev.h>
43265 +#include <linux/fs.h>
43266 +#include <linux/poll.h>
43267 +#include <linux/interrupt.h>
43268 +#include <linux/delay.h>
43269 +#include <linux/clk.h>
43270 +#include <linux/rtc.h>
43271 +#include <linux/wait.h>
43272 +#include <linux/android_power.h>
43273 +#include <linux/suspend.h>
43274 +#include <linux/syscalls.h> // sys_sync
43275 +#include <linux/console.h>
43276 +#include <linux/kbd_kern.h>
43277 +#include <linux/vt_kern.h>
43278 +#include <linux/freezer.h>
43279 +#ifdef CONFIG_ANDROID_POWER_STAT
43280 +#include <linux/proc_fs.h>
43281 +#endif
43282 +
43283 +enum {
43284 +       ANDROID_POWER_DEBUG_USER_STATE = 1U << 0,
43285 +       ANDROID_POWER_DEBUG_EXIT_SUSPEND = 1U << 1,
43286 +       ANDROID_POWER_DEBUG_SUSPEND = 1U << 2,
43287 +       ANDROID_POWER_DEBUG_USER_WAKE_LOCK = 1U << 3,
43288 +       ANDROID_POWER_DEBUG_WAKE_LOCK = 1U << 4,
43289 +};
43290 +static int android_power_debug_mask =
43291 +       ANDROID_POWER_DEBUG_USER_STATE | ANDROID_POWER_DEBUG_EXIT_SUSPEND;
43292 +module_param_named(debug_mask, android_power_debug_mask,
43293 +                       int, S_IRUGO | S_IWUSR | S_IWGRP);
43294 +
43295 +#define ANDROID_POWER_TEST_EARLY_SUSPEND 0
43296 +
43297 +MODULE_DESCRIPTION("OMAP CSMI Driver");
43298 +MODULE_LICENSE("GPL");
43299 +MODULE_VERSION("1.0");
43300 +
43301 +#define ANDROID_SUSPEND_CONSOLE        (MAX_NR_CONSOLES-2)
43302 +
43303 +static spinlock_t g_list_lock = SPIN_LOCK_UNLOCKED;
43304 +static DEFINE_MUTEX(g_early_suspend_lock);
43305 +
43306 +wait_queue_head_t g_wait_queue;
43307 +
43308 +static LIST_HEAD(g_inactive_locks);
43309 +static LIST_HEAD(g_active_idle_wake_locks);
43310 +static LIST_HEAD(g_active_partial_wake_locks);
43311 +static LIST_HEAD(g_active_full_wake_locks);
43312 +static LIST_HEAD(g_early_suspend_handlers);
43313 +static enum {
43314 +       USER_AWAKE,
43315 +       USER_NOTIFICATION,
43316 +       USER_SLEEP
43317 +} g_user_suspend_state;
43318 +static int g_current_event_num;
43319 +static struct workqueue_struct *g_suspend_work_queue;
43320 +static void android_power_suspend(struct work_struct *work);
43321 +static void android_power_wakeup_locked(int notification, ktime_t time);
43322 +static DECLARE_WORK(g_suspend_work, android_power_suspend);
43323 +static int g_max_user_lockouts = 16;
43324 +
43325 +//static const char g_free_user_lockout_name[] = "free_user";
43326 +static struct {
43327 +       enum {
43328 +               USER_WAKE_LOCK_INACTIVE,
43329 +               USER_WAKE_LOCK_PARTIAL,
43330 +               USER_WAKE_LOCK_FULL
43331 +       }                       state;
43332 +       android_suspend_lock_t  suspend_lock;
43333 +       char                    name_buffer[32];
43334 +} *g_user_wake_locks;
43335 +#ifdef CONFIG_ANDROID_POWER_STAT
43336 +android_suspend_lock_t g_deleted_wake_locks;
43337 +android_suspend_lock_t g_no_wake_locks;
43338 +#endif
43339 +static struct kobject *android_power_kobj;
43340 +#ifndef CONFIG_FRAMEBUFFER_CONSOLE
43341 +static wait_queue_head_t fb_state_wq;
43342 +static spinlock_t fb_state_lock = SPIN_LOCK_UNLOCKED;
43343 +int fb_state;
43344 +#endif
43345 +
43346 +#if 0
43347 +android_suspend_lock_t *android_allocate_suspend_lock(const char *debug_name)
43348 +{
43349 +       unsigned long irqflags;
43350 +       struct android_power *e;
43351 +
43352 +       e = kzalloc(sizeof(*e), GFP_KERNEL);
43353 +       if(e == NULL) {
43354 +               printk("android_power_allocate: kzalloc failed\n");
43355 +               return NULL;
43356 +       }
43357 +       e->name = debug_name;
43358 +       spin_lock_irqsave(&g_list_lock, irqflags);
43359 +       list_add(&e->link, &g_allocated);
43360 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43361 +       return e;
43362 +}
43363 +#endif
43364 +
43365 +static int android_init_suspend_lock_internal(
43366 +       android_suspend_lock_t *lock, int has_spin_lock)
43367 +{
43368 +       unsigned long irqflags;
43369 +
43370 +       if(lock->name == NULL) {
43371 +               printk(KERN_ERR "android_init_suspend_lock: error name=NULL, "
43372 +                       "lock=%p\n", lock);
43373 +               dump_stack();
43374 +               return -EINVAL;
43375 +       }
43376 +
43377 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43378 +               printk(KERN_INFO "android_init_suspend_lock name=%s\n",
43379 +                       lock->name);
43380 +#ifdef CONFIG_ANDROID_POWER_STAT
43381 +       lock->stat.count = 0;
43382 +       lock->stat.expire_count = 0;
43383 +       lock->stat.total_time = ktime_set(0, 0);
43384 +       lock->stat.max_time = ktime_set(0, 0);
43385 +       lock->stat.last_time = ktime_set(0, 0);
43386 +#endif
43387 +       lock->flags = 0;
43388 +
43389 +       INIT_LIST_HEAD(&lock->link);
43390 +       if (!has_spin_lock)
43391 +               spin_lock_irqsave(&g_list_lock, irqflags);
43392 +       list_add(&lock->link, &g_inactive_locks);
43393 +       if (!has_spin_lock)
43394 +               spin_unlock_irqrestore(&g_list_lock, irqflags);
43395 +//     if(lock->flags & ANDROID_SUSPEND_LOCK_FLAG_USER_VISIBLE_MASK) {
43396 +//             sysfs_create_file(struct kobject * k, const struct attribute * a)
43397 +//     }
43398 +       return 0;
43399 +}
43400 +
43401 +int android_init_suspend_lock(android_suspend_lock_t *lock)
43402 +{
43403 +       return android_init_suspend_lock_internal(lock, 0);
43404 +}
43405 +
43406 +void android_uninit_suspend_lock(android_suspend_lock_t *lock)
43407 +{
43408 +       unsigned long irqflags;
43409 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43410 +               printk(KERN_INFO "android_uninit_suspend_lock name=%s\n",
43411 +                       lock->name);
43412 +       spin_lock_irqsave(&g_list_lock, irqflags);
43413 +#ifdef CONFIG_ANDROID_POWER_STAT
43414 +       if(lock->stat.count) {
43415 +               if(g_deleted_wake_locks.stat.count == 0) {
43416 +                       g_deleted_wake_locks.name = "deleted_wake_locks";
43417 +                       android_init_suspend_lock_internal(
43418 +                               &g_deleted_wake_locks, 1);
43419 +               }
43420 +               g_deleted_wake_locks.stat.count += lock->stat.count;
43421 +               g_deleted_wake_locks.stat.expire_count += lock->stat.expire_count;
43422 +               g_deleted_wake_locks.stat.total_time = ktime_add(g_deleted_wake_locks.stat.total_time, lock->stat.total_time);
43423 +               g_deleted_wake_locks.stat.max_time = ktime_add(g_deleted_wake_locks.stat.max_time, lock->stat.max_time);
43424 +       }
43425 +#endif
43426 +       list_del(&lock->link);
43427 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43428 +}
43429 +
43430 +void android_lock_idle(android_suspend_lock_t *lock)
43431 +{
43432 +       unsigned long irqflags;
43433 +       spin_lock_irqsave(&g_list_lock, irqflags);
43434 +#ifdef CONFIG_ANDROID_POWER_STAT
43435 +       if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
43436 +               lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
43437 +               lock->stat.last_time = ktime_get();
43438 +       }
43439 +#endif
43440 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43441 +               printk(KERN_INFO "android_power: acquire idle wake lock: %s\n",
43442 +                       lock->name);
43443 +       lock->expires = INT_MAX;
43444 +       lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
43445 +       list_del(&lock->link);
43446 +       list_add(&lock->link, &g_active_idle_wake_locks);
43447 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43448 +}
43449 +
43450 +void android_lock_idle_auto_expire(android_suspend_lock_t *lock, int timeout)
43451 +{
43452 +       unsigned long irqflags;
43453 +       spin_lock_irqsave(&g_list_lock, irqflags);
43454 +#ifdef CONFIG_ANDROID_POWER_STAT
43455 +       if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
43456 +               lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
43457 +               lock->stat.last_time = ktime_get();
43458 +       }
43459 +#endif
43460 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43461 +               printk(KERN_INFO "android_power: acquire idle wake lock: %s, "
43462 +                       "timeout %d.%03lu\n", lock->name, timeout / HZ,
43463 +                       (timeout % HZ) * MSEC_PER_SEC / HZ);
43464 +       lock->expires = jiffies + timeout;
43465 +       lock->flags |= ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
43466 +       list_del(&lock->link);
43467 +       list_add(&lock->link, &g_active_idle_wake_locks);
43468 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43469 +}
43470 +
43471 +void android_lock_suspend(android_suspend_lock_t *lock)
43472 +{
43473 +       unsigned long irqflags;
43474 +       spin_lock_irqsave(&g_list_lock, irqflags);
43475 +#ifdef CONFIG_ANDROID_POWER_STAT
43476 +       if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
43477 +               lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
43478 +               lock->stat.last_time = ktime_get();
43479 +       }
43480 +#endif
43481 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43482 +               printk(KERN_INFO "android_power: acquire wake lock: %s\n",
43483 +                       lock->name);
43484 +       lock->expires = INT_MAX;
43485 +       lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
43486 +       list_del(&lock->link);
43487 +       list_add(&lock->link, &g_active_partial_wake_locks);
43488 +       g_current_event_num++;
43489 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43490 +}
43491 +
43492 +void android_lock_suspend_auto_expire(android_suspend_lock_t *lock, int timeout)
43493 +{
43494 +       unsigned long irqflags;
43495 +       spin_lock_irqsave(&g_list_lock, irqflags);
43496 +#ifdef CONFIG_ANDROID_POWER_STAT
43497 +       if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
43498 +               lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
43499 +               lock->stat.last_time = ktime_get();
43500 +       }
43501 +#endif
43502 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43503 +               printk(KERN_INFO "android_power: acquire wake lock: %s, "
43504 +                       "timeout %d.%03lu\n", lock->name, timeout / HZ,
43505 +                       (timeout % HZ) * MSEC_PER_SEC / HZ);
43506 +       lock->expires = jiffies + timeout;
43507 +       lock->flags |= ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
43508 +       list_del(&lock->link);
43509 +       list_add(&lock->link, &g_active_partial_wake_locks);
43510 +       g_current_event_num++;
43511 +       wake_up(&g_wait_queue);
43512 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43513 +}
43514 +
43515 +void android_lock_partial_suspend_auto_expire(android_suspend_lock_t *lock, int timeout)
43516 +{
43517 +       unsigned long irqflags;
43518 +       spin_lock_irqsave(&g_list_lock, irqflags);
43519 +#ifdef CONFIG_ANDROID_POWER_STAT
43520 +       if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
43521 +               lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
43522 +               lock->stat.last_time = ktime_get();
43523 +       }
43524 +#endif
43525 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43526 +               printk(KERN_INFO "android_power: acquire full wake lock: %s, "
43527 +                       "timeout %d.%03lu\n", lock->name, timeout / HZ,
43528 +                       (timeout % HZ) * MSEC_PER_SEC / HZ);
43529 +       lock->expires = jiffies + timeout;
43530 +       lock->flags |= ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
43531 +       list_del(&lock->link);
43532 +       list_add(&lock->link, &g_active_full_wake_locks);
43533 +       g_current_event_num++;
43534 +       wake_up(&g_wait_queue);
43535 +       android_power_wakeup_locked(1, ktime_get());
43536 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43537 +}
43538 +
43539 +#ifdef CONFIG_ANDROID_POWER_STAT
43540 +static int print_lock_stat(char *buf, android_suspend_lock_t *lock)
43541 +{
43542 +       ktime_t active_time;
43543 +       if(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)
43544 +               active_time = ktime_sub(ktime_get(), lock->stat.last_time);
43545 +       else
43546 +               active_time = ktime_set(0, 0);
43547 +       return sprintf(buf, "\"%s\"\t%d\t%d\t%lld\t%lld\t%lld\t%lld\n",
43548 +                      lock->name,
43549 +                      lock->stat.count, lock->stat.expire_count,
43550 +                      ktime_to_ns(active_time),
43551 +                      ktime_to_ns(lock->stat.total_time),
43552 +                      ktime_to_ns(lock->stat.max_time),
43553 +                      ktime_to_ns(lock->stat.last_time));
43554 +}
43555 +
43556 +
43557 +static int wakelocks_read_proc(char *page, char **start, off_t off,
43558 +                               int count, int *eof, void *data)
43559 +{
43560 +       unsigned long irqflags;
43561 +       android_suspend_lock_t *lock;
43562 +       int len = 0;
43563 +       char *p = page;
43564 +
43565 +       spin_lock_irqsave(&g_list_lock, irqflags);
43566 +
43567 +       p += sprintf(p, "name\tcount\texpire_count\tactive_since\ttotal_time\tmax_time\tlast_change\n");
43568 +       list_for_each_entry(lock, &g_inactive_locks, link) {
43569 +               p += print_lock_stat(p, lock);
43570 +       }
43571 +       list_for_each_entry(lock, &g_active_partial_wake_locks, link) {
43572 +               p += print_lock_stat(p, lock);
43573 +       }
43574 +       list_for_each_entry(lock, &g_active_full_wake_locks, link) {
43575 +               p += print_lock_stat(p, lock);
43576 +       }
43577 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43578 +
43579 +
43580 +       *start = page + off;
43581 +
43582 +       len = p - page;
43583 +       if (len > off)
43584 +               len -= off;
43585 +       else
43586 +               len = 0;
43587 +
43588 +       return len < count ? len  : count;
43589 +}
43590 +
43591 +static void android_unlock_suspend_stat_locked(android_suspend_lock_t *lock)
43592 +{
43593 +       if(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE) {
43594 +               ktime_t duration;
43595 +               lock->flags &= ~ANDROID_SUSPEND_LOCK_ACTIVE;
43596 +               lock->stat.count++;
43597 +               duration = ktime_sub(ktime_get(), lock->stat.last_time);
43598 +               lock->stat.total_time = ktime_add(lock->stat.total_time, duration);
43599 +               if(ktime_to_ns(duration) > ktime_to_ns(lock->stat.max_time))
43600 +                       lock->stat.max_time = duration;
43601 +               lock->stat.last_time = ktime_get();
43602 +       }
43603 +}
43604 +#endif
43605 +
43606 +void android_unlock_suspend(android_suspend_lock_t *lock)
43607 +{
43608 +       int had_full_wake_locks;
43609 +       unsigned long irqflags;
43610 +       spin_lock_irqsave(&g_list_lock, irqflags);
43611 +#ifdef CONFIG_ANDROID_POWER_STAT
43612 +       android_unlock_suspend_stat_locked(lock);
43613 +#endif
43614 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43615 +               printk(KERN_INFO "android_power: release wake lock: %s\n",
43616 +                       lock->name);
43617 +       lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
43618 +       had_full_wake_locks = !list_empty(&g_active_full_wake_locks);
43619 +       list_del(&lock->link);
43620 +       list_add(&lock->link, &g_inactive_locks);
43621 +       wake_up(&g_wait_queue);
43622 +       if(had_full_wake_locks && list_empty(&g_active_full_wake_locks)) {
43623 +               printk("android_unlock_suspend: released at %lld\n", ktime_to_ns(ktime_get()));
43624 +               if(g_user_suspend_state == USER_NOTIFICATION) {
43625 +                       printk("android sleep state %d->%d at %lld\n", g_user_suspend_state, USER_SLEEP, ktime_to_ns(ktime_get()));
43626 +                       g_user_suspend_state = USER_SLEEP;
43627 +                       queue_work(g_suspend_work_queue, &g_suspend_work);
43628 +               }
43629 +       }
43630 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43631 +}
43632 +
43633 +static void android_power_wakeup_locked(int notification, ktime_t time)
43634 +{
43635 +       int new_state = (notification == 0) ? USER_AWAKE : USER_NOTIFICATION;
43636 +
43637 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_STATE) {
43638 +               struct timespec ts;
43639 +               struct rtc_time tm;
43640 +               getnstimeofday(&ts);
43641 +               rtc_time_to_tm(ts.tv_sec, &tm);
43642 +               printk(KERN_INFO "android_power: wakeup (%d->%d) at %lld "
43643 +                       "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n",
43644 +                       g_user_suspend_state, new_state, ktime_to_ns(time),
43645 +                       tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
43646 +                       tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
43647 +       }
43648 +
43649 +       if(new_state >= g_user_suspend_state) {
43650 +               return;
43651 +       }
43652 +       g_user_suspend_state = new_state;
43653 +       g_current_event_num++;
43654 +       wake_up(&g_wait_queue);
43655 +}
43656 +
43657 +static void android_power_wakeup(void)
43658 +{
43659 +       unsigned long irqflags;
43660 +
43661 +       ktime_t ktime_now;
43662 +
43663 +       spin_lock_irqsave(&g_list_lock, irqflags);
43664 +       ktime_now = ktime_get();
43665 +       android_power_wakeup_locked(0, ktime_now);
43666 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43667 +}
43668 +
43669 +static void android_power_request_sleep(void)
43670 +{
43671 +       unsigned long irqflags;
43672 +       int already_suspended;
43673 +       android_suspend_lock_t *lock, *next_lock;
43674 +
43675 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_STATE) {
43676 +               ktime_t ktime_now;
43677 +               struct timespec ts;
43678 +               struct rtc_time tm;
43679 +               ktime_now = ktime_get();
43680 +               getnstimeofday(&ts);
43681 +               rtc_time_to_tm(ts.tv_sec, &tm);
43682 +               printk(KERN_INFO "android_power: sleep (%d->%d) at %lld "
43683 +                      "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n",
43684 +                      g_user_suspend_state, USER_SLEEP, ktime_to_ns(ktime_now),
43685 +                      tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
43686 +                      tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
43687 +       }
43688 +
43689 +       spin_lock_irqsave(&g_list_lock, irqflags);
43690 +       already_suspended = g_user_suspend_state == USER_SLEEP;
43691 +       if(!already_suspended) {
43692 +               g_user_suspend_state = USER_SLEEP;
43693 +       }
43694 +
43695 +       list_for_each_entry_safe(lock, next_lock, &g_active_full_wake_locks, link) {
43696 +#ifdef CONFIG_ANDROID_POWER_STAT
43697 +               android_unlock_suspend_stat_locked(lock);
43698 +#endif
43699 +               list_del(&lock->link);
43700 +               list_add(&lock->link, &g_inactive_locks);
43701 +               printk("android_power_suspend: aborted full wake lock %s\n", lock->name);
43702 +       }
43703 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43704 +       queue_work(g_suspend_work_queue, &g_suspend_work);
43705 +}
43706 +
43707 +void android_register_early_suspend(android_early_suspend_t *handler)
43708 +{
43709 +       struct list_head *pos;
43710 +
43711 +       mutex_lock(&g_early_suspend_lock);
43712 +       list_for_each(pos, &g_early_suspend_handlers) {
43713 +               android_early_suspend_t *e = list_entry(pos, android_early_suspend_t, link);
43714 +               if(e->level > handler->level)
43715 +                       break;
43716 +       }
43717 +       list_add_tail(&handler->link, pos);
43718 +       mutex_unlock(&g_early_suspend_lock);
43719 +}
43720 +
43721 +void android_unregister_early_suspend(android_early_suspend_t *handler)
43722 +{
43723 +       mutex_lock(&g_early_suspend_lock);
43724 +       list_del(&handler->link);
43725 +       mutex_unlock(&g_early_suspend_lock);
43726 +}
43727 +
43728 +#ifdef CONFIG_FRAMEBUFFER_CONSOLE
43729 +static int orig_fgconsole;
43730 +static void console_early_suspend(android_early_suspend_t *h)
43731 +{
43732 +       acquire_console_sem();
43733 +       orig_fgconsole = fg_console;
43734 +       if (vc_allocate(ANDROID_SUSPEND_CONSOLE))
43735 +               goto err;
43736 +       if (set_console(ANDROID_SUSPEND_CONSOLE))
43737 +               goto err;
43738 +       release_console_sem();
43739 +
43740 +       if (vt_waitactive(ANDROID_SUSPEND_CONSOLE))
43741 +               pr_warning("console_early_suspend: Can't switch VCs.\n");
43742 +       return;
43743 +err:
43744 +       pr_warning("console_early_suspend: Can't set console\n");
43745 +       release_console_sem();
43746 +}
43747 +
43748 +static void console_late_resume(android_early_suspend_t *h)
43749 +{
43750 +       int ret;
43751 +       acquire_console_sem();
43752 +       ret = set_console(orig_fgconsole);
43753 +       release_console_sem();
43754 +       if (ret) {
43755 +               pr_warning("console_late_resume: Can't set console.\n");
43756 +               return;
43757 +       }
43758 +
43759 +       if (vt_waitactive(orig_fgconsole))
43760 +               pr_warning("console_late_resume: Can't switch VCs.\n");
43761 +}
43762 +
43763 +static android_early_suspend_t console_early_suspend_desc = {
43764 +       .level = ANDROID_EARLY_SUSPEND_LEVEL_CONSOLE_SWITCH,
43765 +       .suspend = console_early_suspend,
43766 +       .resume = console_late_resume,
43767 +};
43768 +#else
43769 +/* tell userspace to stop drawing, wait for it to stop */
43770 +static void stop_drawing_early_suspend(android_early_suspend_t *h)
43771 +{
43772 +       int ret;
43773 +       unsigned long irq_flags;
43774 +
43775 +       spin_lock_irqsave(&fb_state_lock, irq_flags);
43776 +       fb_state = ANDROID_REQUEST_STOP_DRAWING;
43777 +       spin_unlock_irqrestore(&fb_state_lock, irq_flags);
43778 +
43779 +       wake_up_all(&fb_state_wq);
43780 +       ret = wait_event_timeout(fb_state_wq,
43781 +                                fb_state == ANDROID_STOPPED_DRAWING,
43782 +                                HZ);
43783 +       if (unlikely(fb_state != ANDROID_STOPPED_DRAWING))
43784 +               printk(KERN_WARNING "android_power: timeout waiting for "
43785 +                      "userspace to stop drawing\n");
43786 +}
43787 +
43788 +/* tell userspace to start drawing */
43789 +static void start_drawing_late_resume(android_early_suspend_t *h)
43790 +{
43791 +       unsigned long irq_flags;
43792 +
43793 +       spin_lock_irqsave(&fb_state_lock, irq_flags);
43794 +       fb_state = ANDROID_DRAWING_OK;
43795 +       spin_unlock_irqrestore(&fb_state_lock, irq_flags);
43796 +       wake_up(&fb_state_wq);
43797 +}
43798 +
43799 +static android_early_suspend_t stop_drawing_early_suspend_desc = {
43800 +       .level = ANDROID_EARLY_SUSPEND_LEVEL_CONSOLE_SWITCH,
43801 +       .suspend = stop_drawing_early_suspend,
43802 +       .resume = start_drawing_late_resume,
43803 +};
43804 +#endif
43805 +
43806 +#if ANDROID_POWER_TEST_EARLY_SUSPEND
43807 +
43808 +typedef struct
43809 +{
43810 +       android_early_suspend_t h;
43811 +       const char *string;
43812 +} early_suspend_test_t;
43813 +
43814 +static void early_suspend_test(android_early_suspend_t *h)
43815 +{
43816 +       early_suspend_test_t *est = container_of(h, early_suspend_test_t, h);
43817 +       printk("early suspend %s (l %d)\n", est->string, h->level);
43818 +}
43819 +
43820 +static void late_resume_test(android_early_suspend_t *h)
43821 +{
43822 +       early_suspend_test_t *est = container_of(h, early_suspend_test_t, h);
43823 +       printk("late resume %s (l %d)\n", est->string, h->level);
43824 +}
43825 +
43826 +#define EARLY_SUSPEND_TEST_ENTRY(ilevel, istring) \
43827 +{ \
43828 +       .h = { \
43829 +               .level = ilevel, \
43830 +               .suspend = early_suspend_test, \
43831 +               .resume = late_resume_test \
43832 +       }, \
43833 +       .string = istring \
43834 +}
43835 +static early_suspend_test_t early_suspend_tests[] = {
43836 +       EARLY_SUSPEND_TEST_ENTRY(10, "1"),
43837 +       EARLY_SUSPEND_TEST_ENTRY(5, "2"),
43838 +       EARLY_SUSPEND_TEST_ENTRY(10, "3"),
43839 +       EARLY_SUSPEND_TEST_ENTRY(15, "4"),
43840 +       EARLY_SUSPEND_TEST_ENTRY(8, "5")
43841 +};
43842 +
43843 +#endif
43844 +
43845 +static int get_wait_timeout(int print_locks, int state, struct list_head *list_head)
43846 +{
43847 +       unsigned long irqflags;
43848 +       android_suspend_lock_t *lock, *next;
43849 +       int max_timeout = 0;
43850 +
43851 +       spin_lock_irqsave(&g_list_lock, irqflags);
43852 +       list_for_each_entry_safe(lock, next, list_head, link) {
43853 +               if(lock->flags & ANDROID_SUSPEND_LOCK_AUTO_EXPIRE) {
43854 +                       int timeout = lock->expires - (int)jiffies;
43855 +                       if(timeout <= 0) {
43856 +                               lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
43857 +#ifdef CONFIG_ANDROID_POWER_STAT
43858 +                               lock->stat.expire_count++;
43859 +                               android_unlock_suspend_stat_locked(lock);
43860 +#endif
43861 +                               list_del(&lock->link);
43862 +                               list_add(&lock->link, &g_inactive_locks);
43863 +                               if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43864 +                                       printk("expired wake lock %s\n", lock->name);
43865 +                       }
43866 +                       else {
43867 +                               if(timeout > max_timeout)
43868 +                                       max_timeout = timeout;
43869 +                               if(print_locks)
43870 +                                       printk("active wake lock %s, time left %d\n", lock->name, timeout);
43871 +                       }
43872 +               }
43873 +               else {
43874 +                       if(print_locks)
43875 +                               printk("active wake lock %s\n", lock->name);
43876 +               }
43877 +       }
43878 +       if(g_user_suspend_state != state || list_empty(list_head))
43879 +               max_timeout = -1;
43880 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43881 +       return max_timeout;
43882 +}
43883 +
43884 +#ifdef CONFIG_FRAMEBUFFER_CONSOLE
43885 +static int android_power_class_suspend(struct sys_device *sdev, pm_message_t state)
43886 +{
43887 +       int rv = 0;
43888 +       unsigned long irqflags;
43889 +
43890 +       printk("android_power_suspend: enter\n");
43891 +       spin_lock_irqsave(&g_list_lock, irqflags);
43892 +       if(!list_empty(&g_active_partial_wake_locks)) {
43893 +               printk("android_power_suspend: abort for partial wakeup\n");
43894 +               rv = -EAGAIN;
43895 +       }
43896 +       if(g_user_suspend_state != USER_SLEEP) {
43897 +               printk("android_power_suspend: abort for full wakeup\n");
43898 +               rv = -EAGAIN;
43899 +       }
43900 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43901 +       return rv;
43902 +}
43903 +
43904 +static int android_power_device_suspend(struct sys_device *sdev, pm_message_t state)
43905 +{
43906 +       int rv = 0;
43907 +       unsigned long irqflags;
43908 +
43909 +       printk("android_power_device_suspend: enter\n");
43910 +       spin_lock_irqsave(&g_list_lock, irqflags);
43911 +       if(!list_empty(&g_active_partial_wake_locks)) {
43912 +               printk("android_power_device_suspend: abort for partial wakeup\n");
43913 +               rv = -EAGAIN;
43914 +       }
43915 +       if(g_user_suspend_state != USER_SLEEP) {
43916 +               printk("android_power_device_suspend: abort for full wakeup\n");
43917 +               rv = -EAGAIN;
43918 +       }
43919 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43920 +       return rv;
43921 +}
43922 +#endif
43923 +
43924 +int android_power_is_driver_suspended(void)
43925 +{
43926 +       return (get_wait_timeout(0, USER_SLEEP, &g_active_partial_wake_locks) < 0) && (g_user_suspend_state == USER_SLEEP);
43927 +}
43928 +
43929 +int android_power_is_low_power_idle_ok(void)
43930 +{
43931 +       get_wait_timeout(0, USER_SLEEP, &g_active_idle_wake_locks);
43932 +       return list_empty(&g_active_idle_wake_locks);
43933 +}
43934 +
43935 +static void android_power_suspend(struct work_struct *work)
43936 +{
43937 +       int entry_event_num;
43938 +       int ret;
43939 +       int wait = 0;
43940 +       android_early_suspend_t *pos;
43941 +       int print_locks = 0;
43942 +       unsigned long irqflags;
43943 +
43944 +       while(g_user_suspend_state != USER_AWAKE) {
43945 +               while(g_user_suspend_state == USER_NOTIFICATION) {
43946 +                       wait = get_wait_timeout(print_locks, USER_NOTIFICATION, &g_active_full_wake_locks);
43947 +                       if(wait < 0)
43948 +                               break;
43949 +                       if(wait)
43950 +                               wait_event_interruptible_timeout(g_wait_queue, get_wait_timeout(0, USER_NOTIFICATION, &g_active_full_wake_locks) != wait, wait);
43951 +               }
43952 +               spin_lock_irqsave(&g_list_lock, irqflags);
43953 +               if(g_user_suspend_state == USER_NOTIFICATION && list_empty(&g_active_full_wake_locks)) {
43954 +                       printk("android sleep state %d->%d at %lld\n", g_user_suspend_state, USER_SLEEP, ktime_to_ns(ktime_get()));
43955 +                       g_user_suspend_state = USER_SLEEP;
43956 +               }
43957 +               spin_unlock_irqrestore(&g_list_lock, irqflags);
43958 +               wait = 0;
43959 +               if(g_user_suspend_state == USER_AWAKE) {
43960 +                       printk("android_power_suspend: suspend aborted\n");
43961 +                       return;
43962 +               }
43963 +
43964 +               mutex_lock(&g_early_suspend_lock);
43965 +               //printk("android_power_suspend: call early suspend handlers\n");
43966 +               list_for_each_entry(pos, &g_early_suspend_handlers, link) {
43967 +                       if(pos->suspend != NULL)
43968 +                               pos->suspend(pos);
43969 +               }
43970 +               //printk("android_power_suspend: call early suspend handlers\n");
43971 +
43972 +               //printk("android_power_suspend: enter\n");
43973 +
43974 +               sys_sync();
43975 +
43976 +               while(g_user_suspend_state == USER_SLEEP) {
43977 +                       //printk("android_power_suspend: enter wait (%d)\n", wait);
43978 +                       if(wait) {
43979 +                               wait_event_interruptible_timeout(g_wait_queue, g_user_suspend_state != USER_SLEEP, wait);
43980 +                               wait = 0;
43981 +                       }
43982 +                       if (android_power_debug_mask & ANDROID_POWER_DEBUG_SUSPEND)
43983 +                               print_locks = 1;
43984 +                       while(1) {
43985 +                               wait = get_wait_timeout(print_locks, USER_SLEEP, &g_active_partial_wake_locks);
43986 +                               print_locks = 0;
43987 +                               if(wait < 0)
43988 +                                       break;
43989 +                               if(wait)
43990 +                                       wait_event_interruptible_timeout(g_wait_queue, get_wait_timeout(0, USER_SLEEP, &g_active_partial_wake_locks) != wait, wait);
43991 +                               else
43992 +                                       wait_event_interruptible(g_wait_queue, get_wait_timeout(0, USER_SLEEP, &g_active_partial_wake_locks) != wait);
43993 +                       }
43994 +                       wait = 0;
43995 +                       //printk("android_power_suspend: exit wait\n");
43996 +                       entry_event_num = g_current_event_num;
43997 +                       if(g_user_suspend_state != USER_SLEEP)
43998 +                               break;
43999 +                       sys_sync();
44000 +                       if (android_power_debug_mask & ANDROID_POWER_DEBUG_SUSPEND)
44001 +                               printk(KERN_INFO "android_power_suspend: enter suspend\n");
44002 +                       ret = pm_suspend(PM_SUSPEND_MEM);
44003 +                       if (android_power_debug_mask & ANDROID_POWER_DEBUG_EXIT_SUSPEND) {
44004 +                               struct timespec ts;
44005 +                               struct rtc_time tm;
44006 +                               getnstimeofday(&ts);
44007 +                               rtc_time_to_tm(ts.tv_sec, &tm);
44008 +                               printk("android_power_suspend: exit suspend, ret = %d "
44009 +                                       "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n", ret,
44010 +                                       tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
44011 +                                       tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
44012 +                       }
44013 +                       if(g_current_event_num == entry_event_num) {
44014 +                               if (android_power_debug_mask & ANDROID_POWER_DEBUG_SUSPEND)
44015 +                                       printk(KERN_INFO "android_power_suspend: pm_suspend returned with no event\n");
44016 +                               wait = HZ / 2;
44017 +#ifdef CONFIG_ANDROID_POWER_STAT
44018 +                               if(g_no_wake_locks.stat.count == 0) {
44019 +                                       g_no_wake_locks.name = "unknown_wakeups";
44020 +                                       android_init_suspend_lock(&g_no_wake_locks);
44021 +                               }
44022 +                               g_no_wake_locks.stat.count++;
44023 +                               g_no_wake_locks.stat.total_time = ktime_add(
44024 +                                       g_no_wake_locks.stat.total_time,
44025 +                                       ktime_set(0, 500 * NSEC_PER_MSEC));
44026 +                               g_no_wake_locks.stat.max_time =
44027 +                                       ktime_set(0, 500 * NSEC_PER_MSEC);
44028 +#endif
44029 +                       }
44030 +               }
44031 +               if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_STATE)
44032 +                       printk("android_power_suspend: done\n");
44033 +               //printk("android_power_suspend: call late resume handlers\n");
44034 +               list_for_each_entry_reverse(pos, &g_early_suspend_handlers, link) {
44035 +                       if(pos->resume != NULL)
44036 +                               pos->resume(pos);
44037 +               }
44038 +               //printk("android_power_suspend: call late resume handlers\n");
44039 +               mutex_unlock(&g_early_suspend_lock);
44040 +       }
44041 +}
44042 +
44043 +#if 0
44044 +struct sysdev_class android_power_sysclass = {
44045 +       set_kset_name("android_power"),
44046 +       .suspend = android_power_class_suspend
44047 +};
44048 +static struct sysdev_class *g_android_power_sysclass = NULL;
44049 +
44050 +static struct {
44051 +       struct sys_device sysdev;
44052 +//     omap_csmi_gsm_image_info_t *pdata;
44053 +} android_power_device = {
44054 +       .sysdev = {
44055 +               .id             = 0,
44056 +               .cls            = &android_power_sysclass,
44057 +//             .suspend = android_power_device_suspend
44058 +       },
44059 +//     .pdata = &g_gsm_image_info
44060 +};
44061 +
44062 +struct sysdev_class *android_power_get_sysclass(void)
44063 +{
44064 +       return g_android_power_sysclass;
44065 +}
44066 +#endif
44067 +
44068 +static ssize_t state_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
44069 +{
44070 +       char * s = buf;
44071 +       unsigned long irqflags;
44072 +
44073 +       spin_lock_irqsave(&g_list_lock, irqflags);
44074 +       s += sprintf(s, "%d-%d-%d\n", g_user_suspend_state, list_empty(&g_active_full_wake_locks), list_empty(&g_active_partial_wake_locks));
44075 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44076 +       return (s - buf);
44077 +}
44078 +
44079 +static ssize_t state_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
44080 +{
44081 +       if(n >= strlen("standby") &&
44082 +          strncmp(buf, "standby", strlen("standby")) == 0) {
44083 +               android_power_request_sleep();
44084 +               wait_event_interruptible(g_wait_queue, g_user_suspend_state == USER_AWAKE);
44085 +               return n;
44086 +       }
44087 +       if(n >= strlen("wake") &&
44088 +          strncmp(buf, "wake", strlen("wake")) == 0) {
44089 +               android_power_wakeup();
44090 +               return n;
44091 +       }
44092 +       printk("android_power state_store: invalid argument\n");
44093 +       return -EINVAL;
44094 +}
44095 +
44096 +static ssize_t request_state_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
44097 +{
44098 +       char * s = buf;
44099 +       unsigned long irqflags;
44100 +
44101 +       spin_lock_irqsave(&g_list_lock, irqflags);
44102 +       if(g_user_suspend_state == USER_AWAKE)
44103 +               s += sprintf(s, "wake\n");
44104 +       else if(g_user_suspend_state == USER_NOTIFICATION)
44105 +               s += sprintf(s, "standby (w/full wake lock)\n");
44106 +       else
44107 +               s += sprintf(s, "standby\n");
44108 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44109 +       return (s - buf);
44110 +}
44111 +
44112 +static ssize_t request_state_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
44113 +{
44114 +       if(n >= strlen("standby") &&
44115 +          strncmp(buf, "standby", strlen("standby")) == 0) {
44116 +               android_power_request_sleep();
44117 +               return n;
44118 +       }
44119 +       if(n >= strlen("wake") &&
44120 +          strncmp(buf, "wake", strlen("wake")) == 0) {
44121 +               android_power_wakeup();
44122 +               return n;
44123 +       }
44124 +       printk("android_power state_store: invalid argument\n");
44125 +       return -EINVAL;
44126 +}
44127 +
44128 +
44129 +static int lookup_wake_lock_name(const char *buf, size_t n, int allocate, int *timeout)
44130 +{
44131 +       int i;
44132 +       int free_index = -1;
44133 +       int inactive_index = -1;
44134 +       int expires_index = -1;
44135 +       int expires_time = INT_MAX;
44136 +       char *tmp_buf[64];
44137 +       char name[32];
44138 +       u64 nanoseconds;
44139 +       int num_arg;
44140 +
44141 +       if(n <= 0)
44142 +               return -EINVAL;
44143 +       if(n >= sizeof(tmp_buf))
44144 +               return -EOVERFLOW;
44145 +       if(n == sizeof(tmp_buf) - 1 && buf[n - 1] != '\0')
44146 +               return -EOVERFLOW;
44147 +
44148 +       memcpy(tmp_buf, buf, n);
44149 +       if(tmp_buf[n - 1] != '\0')
44150 +               tmp_buf[n] = '\0';
44151 +
44152 +       num_arg = sscanf(buf, "%31s %llu", name, &nanoseconds);
44153 +       if(num_arg < 1)
44154 +               return -EINVAL;
44155 +
44156 +       if(strlen(name) >= sizeof(g_user_wake_locks[i].name_buffer))
44157 +               return -EOVERFLOW;
44158 +
44159 +       if(timeout != NULL) {
44160 +               if(num_arg > 1) {
44161 +                       do_div(nanoseconds, (NSEC_PER_SEC / HZ));
44162 +                       if(nanoseconds <= 0)
44163 +                               nanoseconds = 1;
44164 +                       *timeout = nanoseconds;
44165 +               }
44166 +               else
44167 +                       *timeout = 0;
44168 +       }
44169 +
44170 +       for(i = 0; i < g_max_user_lockouts; i++) {
44171 +               if(strcmp(g_user_wake_locks[i].name_buffer, name) == 0)
44172 +                       return i;
44173 +               if(g_user_wake_locks[i].name_buffer[0] == '\0')
44174 +                       free_index = i;
44175 +               else if(g_user_wake_locks[i].state == USER_WAKE_LOCK_INACTIVE)
44176 +                       inactive_index = i;
44177 +               else if(g_user_wake_locks[i].suspend_lock.expires < expires_time)
44178 +                       expires_index = i;
44179 +       }
44180 +       if(allocate) {
44181 +               if(free_index >= 0)
44182 +                       i = free_index;
44183 +               else if(inactive_index >= 0)
44184 +                       i = inactive_index;
44185 +               else if(expires_index >= 0) {
44186 +                       i = expires_index;
44187 +                       printk("lookup_wake_lock_name: overwriting expired lock, %s\n", g_user_wake_locks[i].name_buffer);
44188 +               }
44189 +               else {
44190 +                       i = 0;
44191 +                       printk("lookup_wake_lock_name: overwriting active lock, %s\n", g_user_wake_locks[i].name_buffer);
44192 +               }
44193 +               strcpy(g_user_wake_locks[i].name_buffer, name);
44194 +               return i;
44195 +       }
44196 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
44197 +               printk(KERN_INFO "lookup_wake_lock_name: %s not found\n", name);
44198 +       return -EINVAL;
44199 +}
44200 +
44201 +static ssize_t acquire_full_wake_lock_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
44202 +{
44203 +       int i;
44204 +       char * s = buf;
44205 +       unsigned long irqflags;
44206 +
44207 +       spin_lock_irqsave(&g_list_lock, irqflags);
44208 +       for(i = 0; i < g_max_user_lockouts; i++) {
44209 +               if(g_user_wake_locks[i].name_buffer[0] != '\0' && g_user_wake_locks[i].state == USER_WAKE_LOCK_FULL)
44210 +                       s += sprintf(s, "%s ", g_user_wake_locks[i].name_buffer);
44211 +       }
44212 +       s += sprintf(s, "\n");
44213 +
44214 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44215 +       return (s - buf);
44216 +}
44217 +
44218 +static ssize_t acquire_full_wake_lock_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
44219 +{
44220 +       int i;
44221 +       unsigned long irqflags;
44222 +       int timeout;
44223 +
44224 +       spin_lock_irqsave(&g_list_lock, irqflags);
44225 +       i = lookup_wake_lock_name(buf, n, 1, &timeout);
44226 +       if(i >= 0)
44227 +               g_user_wake_locks[i].state = USER_WAKE_LOCK_FULL;
44228 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44229 +       if(i < 0)
44230 +               return i;
44231 +
44232 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
44233 +               printk(KERN_INFO "acquire_full_wake_lock_store: %s, size %d\n",
44234 +                       g_user_wake_locks[i].name_buffer, n);
44235 +
44236 +       //android_lock_partial_suspend_auto_expire(&g_user_wake_locks[i].suspend_lock, ktime_to_timespec(g_auto_off_timeout).tv_sec * HZ);
44237 +       if(timeout == 0)
44238 +               timeout = INT_MAX;
44239 +       android_lock_partial_suspend_auto_expire(&g_user_wake_locks[i].suspend_lock, timeout);
44240 +
44241 +       return n;
44242 +}
44243 +
44244 +static ssize_t acquire_partial_wake_lock_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
44245 +{
44246 +       int i;
44247 +       char * s = buf;
44248 +       unsigned long irqflags;
44249 +
44250 +       spin_lock_irqsave(&g_list_lock, irqflags);
44251 +       for(i = 0; i < g_max_user_lockouts; i++) {
44252 +               if(g_user_wake_locks[i].name_buffer[0] != '\0' && g_user_wake_locks[i].state == USER_WAKE_LOCK_PARTIAL)
44253 +                       s += sprintf(s, "%s ", g_user_wake_locks[i].name_buffer);
44254 +       }
44255 +       s += sprintf(s, "\n");
44256 +
44257 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44258 +       return (s - buf);
44259 +}
44260 +
44261 +static ssize_t acquire_partial_wake_lock_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
44262 +{
44263 +       int i;
44264 +       unsigned long irqflags;
44265 +       int timeout;
44266 +
44267 +       spin_lock_irqsave(&g_list_lock, irqflags);
44268 +       i = lookup_wake_lock_name(buf, n, 1, &timeout);
44269 +       if(i >= 0)
44270 +               g_user_wake_locks[i].state = USER_WAKE_LOCK_PARTIAL;
44271 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44272 +       if(i < 0)
44273 +               return 0;
44274 +
44275 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
44276 +               printk(KERN_INFO "acquire_partial_wake_lock_store: %s, "
44277 +                       "size %d\n", g_user_wake_locks[i].name_buffer, n);
44278 +
44279 +       if(timeout)
44280 +               android_lock_suspend_auto_expire(&g_user_wake_locks[i].suspend_lock, timeout);
44281 +       else
44282 +               android_lock_suspend(&g_user_wake_locks[i].suspend_lock);
44283 +
44284 +       return n;
44285 +}
44286 +
44287 +
44288 +static ssize_t release_wake_lock_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
44289 +{
44290 +       int i;
44291 +       char * s = buf;
44292 +       unsigned long irqflags;
44293 +
44294 +       spin_lock_irqsave(&g_list_lock, irqflags);
44295 +       for(i = 0; i < g_max_user_lockouts; i++) {
44296 +               if(g_user_wake_locks[i].name_buffer[0] != '\0' && g_user_wake_locks[i].state == USER_WAKE_LOCK_INACTIVE)
44297 +                       s += sprintf(s, "%s ", g_user_wake_locks[i].name_buffer);
44298 +       }
44299 +       s += sprintf(s, "\n");
44300 +
44301 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44302 +       return (s - buf);
44303 +}
44304 +
44305 +static ssize_t release_wake_lock_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
44306 +{
44307 +       int i;
44308 +       unsigned long irqflags;
44309 +
44310 +       spin_lock_irqsave(&g_list_lock, irqflags);
44311 +       i = lookup_wake_lock_name(buf, n, 1, NULL);
44312 +       if(i >= 0) {
44313 +               g_user_wake_locks[i].state = USER_WAKE_LOCK_INACTIVE;
44314 +       }
44315 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44316 +
44317 +       if(i < 0)
44318 +               return i;
44319 +
44320 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
44321 +               printk(KERN_INFO "release_wake_lock_store: %s, size %d\n",
44322 +                       g_user_wake_locks[i].name_buffer, n);
44323 +
44324 +       android_unlock_suspend(&g_user_wake_locks[i].suspend_lock);
44325 +       return n;
44326 +}
44327 +
44328 +
44329 +#ifndef CONFIG_FRAMEBUFFER_CONSOLE
44330 +static ssize_t wait_for_fb_sleep_show(struct kobject *kobj,
44331 +                                     struct kobj_attribute *attr, char *buf)
44332 +{
44333 +       char * s = buf;
44334 +       int ret;
44335 +
44336 +       ret = wait_event_interruptible(fb_state_wq,
44337 +                                      fb_state != ANDROID_DRAWING_OK);
44338 +       if (ret && fb_state == ANDROID_DRAWING_OK)
44339 +               return ret;
44340 +       else
44341 +               s += sprintf(buf, "sleeping");
44342 +       return (s - buf);
44343 +}
44344 +
44345 +static ssize_t wait_for_fb_wake_show(struct kobject *kobj,
44346 +                                    struct kobj_attribute *attr, char *buf)
44347 +{
44348 +       char * s = buf;
44349 +       int ret;
44350 +       unsigned long irq_flags;
44351 +
44352 +       spin_lock_irqsave(&fb_state_lock, irq_flags);
44353 +       if (fb_state == ANDROID_REQUEST_STOP_DRAWING) {
44354 +               fb_state = ANDROID_STOPPED_DRAWING;
44355 +               wake_up(&fb_state_wq);
44356 +       }
44357 +       spin_unlock_irqrestore(&fb_state_lock, irq_flags);
44358 +
44359 +       ret = wait_event_interruptible(fb_state_wq,
44360 +                                      fb_state == ANDROID_DRAWING_OK);
44361 +       if (ret && fb_state != ANDROID_DRAWING_OK)
44362 +               return ret;
44363 +       else
44364 +               s += sprintf(buf, "awake");
44365 +
44366 +       return (s - buf);
44367 +}
44368 +#endif
44369 +
44370 +#define android_power_attr(_name) \
44371 +static struct kobj_attribute _name##_attr = {  \
44372 +       .attr   = {                             \
44373 +               .name = __stringify(_name),     \
44374 +               .mode = 0664,                   \
44375 +       },                                      \
44376 +       .show   = _name##_show,                 \
44377 +       .store  = _name##_store,                \
44378 +}
44379 +
44380 +#define android_power_ro_attr(_name) \
44381 +static struct kobj_attribute _name##_attr = {  \
44382 +       .attr   = {                             \
44383 +               .name = __stringify(_name),     \
44384 +               .mode = 0444,                   \
44385 +       },                                      \
44386 +       .show   = _name##_show,                 \
44387 +       .store  = NULL,         \
44388 +}
44389 +
44390 +android_power_attr(state);
44391 +android_power_attr(request_state);
44392 +android_power_attr(acquire_full_wake_lock);
44393 +android_power_attr(acquire_partial_wake_lock);
44394 +android_power_attr(release_wake_lock);
44395 +#ifndef CONFIG_FRAMEBUFFER_CONSOLE
44396 +android_power_ro_attr(wait_for_fb_sleep);
44397 +android_power_ro_attr(wait_for_fb_wake);
44398 +#endif
44399 +
44400 +static struct attribute * g[] = {
44401 +       &state_attr.attr,
44402 +       &request_state_attr.attr,
44403 +       &acquire_full_wake_lock_attr.attr,
44404 +       &acquire_partial_wake_lock_attr.attr,
44405 +       &release_wake_lock_attr.attr,
44406 +#ifndef CONFIG_FRAMEBUFFER_CONSOLE
44407 +       &wait_for_fb_sleep_attr.attr,
44408 +       &wait_for_fb_wake_attr.attr,
44409 +#endif
44410 +       NULL,
44411 +};
44412 +
44413 +static struct attribute_group attr_group = {
44414 +       .attrs = g,
44415 +};
44416 +
44417 +#if 0
44418 +// test code when there is no platform suspend
44419 +
44420 +static android_suspend_lock_t test_pm_ops_suspend_lock = {
44421 +       .name = "test_pm_ops"
44422 +};
44423 +
44424 +int test_pm_op_enter(suspend_state_t state)
44425 +{
44426 +       printk("test_pm_op_enter reached\n");
44427 +       android_lock_suspend(&test_pm_ops_suspend_lock);
44428 +       printk("test_pm_op_enter returned\n");
44429 +       return 0;
44430 +}
44431 +
44432 +void test_pm_ops_late_resume_handler(android_early_suspend_t *h)
44433 +{
44434 +       printk("test_pm_ops_late_resume_handler reached\n");
44435 +       android_unlock_suspend(&test_pm_ops_suspend_lock);
44436 +       printk("test_pm_ops_late_resume_handler returned\n");
44437 +}
44438 +
44439 +static struct pm_ops test_pm_ops = {
44440 +       .enter = test_pm_op_enter
44441 +};
44442 +
44443 +static android_early_suspend_t test_pm_ops_early_suspend_handler = {
44444 +       .resume = test_pm_ops_late_resume_handler
44445 +};
44446 +#endif
44447 +
44448 +static int __init android_power_init(void)
44449 +{
44450 +       int ret;
44451 +       int i;
44452 +
44453 +#if 0
44454 +       if(pm_ops == NULL) {
44455 +               printk("android_power_init no pm_ops, installing test code\n");
44456 +               pm_set_ops(&test_pm_ops);
44457 +               android_init_suspend_lock(&test_pm_ops_suspend_lock);
44458 +               android_register_early_suspend(&test_pm_ops_early_suspend_handler);
44459 +       }
44460 +#endif
44461 +
44462 +#ifdef CONFIG_ANDROID_POWER_STAT
44463 +       g_deleted_wake_locks.stat.count = 0;
44464 +#endif
44465 +       init_waitqueue_head(&g_wait_queue);
44466 +#ifndef CONFIG_FRAMEBUFFER_CONSOLE
44467 +       init_waitqueue_head(&fb_state_wq);
44468 +       fb_state = ANDROID_DRAWING_OK;
44469 +#endif
44470 +
44471 +       g_user_wake_locks = kzalloc(sizeof(*g_user_wake_locks) * g_max_user_lockouts, GFP_KERNEL);
44472 +       if(g_user_wake_locks == NULL) {
44473 +               ret = -ENOMEM;
44474 +               goto err1;
44475 +       }
44476 +       for(i = 0; i < g_max_user_lockouts; i++) {
44477 +               g_user_wake_locks[i].suspend_lock.name = g_user_wake_locks[i].name_buffer;
44478 +               android_init_suspend_lock(&g_user_wake_locks[i].suspend_lock);
44479 +       }
44480 +
44481 +       g_suspend_work_queue = create_workqueue("suspend");
44482 +       if(g_suspend_work_queue == NULL) {
44483 +               ret = -ENOMEM;
44484 +               goto err2;
44485 +       }
44486 +
44487 +       android_power_kobj = kobject_create_and_add("android_power", NULL);
44488 +       if (android_power_kobj == NULL) {
44489 +               printk("android_power_init: subsystem_register failed\n");
44490 +               ret = -ENOMEM;
44491 +               goto err3;
44492 +       }
44493 +       ret = sysfs_create_group(android_power_kobj, &attr_group);
44494 +       if(ret) {
44495 +               printk("android_power_init: sysfs_create_group failed\n");
44496 +               goto err4;
44497 +       }
44498 +#ifdef CONFIG_ANDROID_POWER_STAT
44499 +       create_proc_read_entry("wakelocks", S_IRUGO, NULL, wakelocks_read_proc, NULL);
44500 +#endif
44501 +
44502 +#if ANDROID_POWER_TEST_EARLY_SUSPEND
44503 +       {
44504 +               int i;
44505 +               for(i = 0; i < sizeof(early_suspend_tests) / sizeof(early_suspend_tests[0]); i++)
44506 +                       android_register_early_suspend(&early_suspend_tests[i].h);
44507 +       }
44508 +#endif
44509 +#ifdef CONFIG_FRAMEBUFFER_CONSOLE
44510 +       android_register_early_suspend(&console_early_suspend_desc);
44511 +#else
44512 +       android_register_early_suspend(&stop_drawing_early_suspend_desc);
44513 +#endif
44514 +
44515 +#if 0
44516 +       ret = sysdev_class_register(&android_power_sysclass);
44517 +       if(ret) {
44518 +               printk("android_power_init: sysdev_class_register failed\n");
44519 +               goto err1;
44520 +       }
44521 +       ret = sysdev_register(&android_power_device.sysdev);
44522 +       if(ret < 0)
44523 +               goto err2;
44524 +
44525 +       g_android_power_sysclass = &android_power_sysclass;
44526 +#endif
44527 +       return 0;
44528 +
44529 +//err2:
44530 +//     sysdev_class_unregister(&android_power_sysclass);
44531 +err4:
44532 +       kobject_del(android_power_kobj);
44533 +err3:
44534 +       destroy_workqueue(g_suspend_work_queue);
44535 +err2:
44536 +       for(i = 0; i < g_max_user_lockouts; i++) {
44537 +               android_uninit_suspend_lock(&g_user_wake_locks[i].suspend_lock);
44538 +       }
44539 +       kfree(g_user_wake_locks);
44540 +err1:
44541 +       return ret;
44542 +}
44543 +
44544 +static void  __exit android_power_exit(void)
44545 +{
44546 +       int i;
44547 +//     g_android_power_sysclass = NULL;
44548 +//     sysdev_unregister(&android_power_device.sysdev);
44549 +//     sysdev_class_unregister(&android_power_sysclass);
44550 +#ifdef CONFIG_FRAMEBUFFER_CONSOLE
44551 +       android_unregister_early_suspend(&console_early_suspend_desc);
44552 +#else
44553 +       android_unregister_early_suspend(&stop_drawing_early_suspend_desc);
44554 +#endif
44555 +#ifdef CONFIG_ANDROID_POWER_STAT
44556 +       remove_proc_entry("wakelocks", NULL);
44557 +#endif
44558 +       sysfs_remove_group(android_power_kobj, &attr_group);
44559 +       kobject_del(android_power_kobj);
44560 +       destroy_workqueue(g_suspend_work_queue);
44561 +       for(i = 0; i < g_max_user_lockouts; i++) {
44562 +               android_uninit_suspend_lock(&g_user_wake_locks[i].suspend_lock);
44563 +       }
44564 +       kfree(g_user_wake_locks);
44565 +}
44566 +
44567 +core_initcall(android_power_init);
44568 +module_exit(android_power_exit);
44569 +
44570 +//EXPORT_SYMBOL(android_power_get_sysclass);
44571 +EXPORT_SYMBOL(android_init_suspend_lock);
44572 +EXPORT_SYMBOL(android_uninit_suspend_lock);
44573 +EXPORT_SYMBOL(android_lock_suspend);
44574 +EXPORT_SYMBOL(android_lock_suspend_auto_expire);
44575 +EXPORT_SYMBOL(android_unlock_suspend);
44576 +EXPORT_SYMBOL(android_power_wakeup);
44577 +EXPORT_SYMBOL(android_register_early_suspend);
44578 +EXPORT_SYMBOL(android_unregister_early_suspend);
44579 +
44580 +
44581 --- /dev/null
44582 +++ b/drivers/android/ram_console.c
44583 @@ -0,0 +1,395 @@
44584 +/* drivers/android/ram_console.c
44585 + *
44586 + * Copyright (C) 2007-2008 Google, Inc.
44587 + *
44588 + * This software is licensed under the terms of the GNU General Public
44589 + * License version 2, as published by the Free Software Foundation, and
44590 + * may be copied, distributed, and modified under those terms.
44591 + *
44592 + * This program is distributed in the hope that it will be useful,
44593 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
44594 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
44595 + * GNU General Public License for more details.
44596 + *
44597 + */
44598 +
44599 +#include <linux/console.h>
44600 +#include <linux/init.h>
44601 +#include <linux/module.h>
44602 +#include <linux/platform_device.h>
44603 +#include <linux/proc_fs.h>
44604 +#include <linux/string.h>
44605 +#include <linux/uaccess.h>
44606 +#include <asm/io.h>
44607 +
44608 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
44609 +#include <linux/rslib.h>
44610 +#endif
44611 +
44612 +struct ram_console_buffer {
44613 +       uint32_t    sig;
44614 +       uint32_t    start;
44615 +       uint32_t    size;
44616 +       uint8_t     data[0];
44617 +};
44618 +
44619 +#define RAM_CONSOLE_SIG (0x43474244) /* DBGC */
44620 +
44621 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
44622 +static char __initdata
44623 +       ram_console_old_log_init_buffer[CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE];
44624 +#endif
44625 +static char *ram_console_old_log;
44626 +static size_t ram_console_old_log_size;
44627 +
44628 +static struct ram_console_buffer *ram_console_buffer;
44629 +static size_t ram_console_buffer_size;
44630 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
44631 +static char *ram_console_par_buffer;
44632 +static struct rs_control *ram_console_rs_decoder;
44633 +static int ram_console_corrected_bytes;
44634 +static int ram_console_bad_blocks;
44635 +#define ECC_BLOCK_SIZE CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE
44636 +#define ECC_SIZE CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE
44637 +#define ECC_SYMSIZE CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE
44638 +#define ECC_POLY CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL
44639 +#endif
44640 +
44641 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
44642 +static void ram_console_encode_rs8(uint8_t *data, size_t len, uint8_t *ecc)
44643 +{
44644 +       int i;
44645 +       uint16_t par[ECC_SIZE];
44646 +       /* Initialize the parity buffer */
44647 +       memset(par, 0, sizeof(par));
44648 +       encode_rs8(ram_console_rs_decoder, data, len, par, 0);
44649 +       for (i = 0; i < ECC_SIZE; i++)
44650 +               ecc[i] = par[i];
44651 +}
44652 +
44653 +static int ram_console_decode_rs8(void *data, size_t len, uint8_t *ecc)
44654 +{
44655 +       int i;
44656 +       uint16_t par[ECC_SIZE];
44657 +       for (i = 0; i < ECC_SIZE; i++)
44658 +               par[i] = ecc[i];
44659 +       return decode_rs8(ram_console_rs_decoder, data, par, len,
44660 +                               NULL, 0, NULL, 0, NULL);
44661 +}
44662 +#endif
44663 +
44664 +static void ram_console_update(const char *s, unsigned int count)
44665 +{
44666 +       struct ram_console_buffer *buffer = ram_console_buffer;
44667 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
44668 +       uint8_t *buffer_end = buffer->data + ram_console_buffer_size;
44669 +       uint8_t *block;
44670 +       uint8_t *par;
44671 +       int size = ECC_BLOCK_SIZE;
44672 +#endif
44673 +       memcpy(buffer->data + buffer->start, s, count);
44674 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
44675 +       block = buffer->data + (buffer->start & ~(ECC_BLOCK_SIZE - 1));
44676 +       par = ram_console_par_buffer +
44677 +             (buffer->start / ECC_BLOCK_SIZE) * ECC_SIZE;
44678 +       do {
44679 +               if (block + ECC_BLOCK_SIZE > buffer_end)
44680 +                       size = buffer_end - block;
44681 +               ram_console_encode_rs8(block, size, par);
44682 +               block += ECC_BLOCK_SIZE;
44683 +               par += ECC_SIZE;
44684 +       } while (block < buffer->data + buffer->start + count);
44685 +#endif
44686 +}
44687 +
44688 +static void ram_console_update_header(void)
44689 +{
44690 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
44691 +       struct ram_console_buffer *buffer = ram_console_buffer;
44692 +       uint8_t *par;
44693 +       par = ram_console_par_buffer +
44694 +             DIV_ROUND_UP(ram_console_buffer_size, ECC_BLOCK_SIZE) * ECC_SIZE;
44695 +       ram_console_encode_rs8((uint8_t *)buffer, sizeof(*buffer), par);
44696 +#endif
44697 +}
44698 +
44699 +static void
44700 +ram_console_write(struct console *console, const char *s, unsigned int count)
44701 +{
44702 +       int rem;
44703 +       struct ram_console_buffer *buffer = ram_console_buffer;
44704 +
44705 +       if (count > ram_console_buffer_size) {
44706 +               s += count - ram_console_buffer_size;
44707 +               count = ram_console_buffer_size;
44708 +       }
44709 +       rem = ram_console_buffer_size - buffer->start;
44710 +       if (rem < count) {
44711 +               ram_console_update(s, rem);
44712 +               s += rem;
44713 +               count -= rem;
44714 +               buffer->start = 0;
44715 +               buffer->size = ram_console_buffer_size;
44716 +       }
44717 +       ram_console_update(s, count);
44718 +
44719 +       buffer->start += count;
44720 +       if (buffer->size < ram_console_buffer_size)
44721 +               buffer->size += count;
44722 +       ram_console_update_header();
44723 +}
44724 +
44725 +static struct console ram_console = {
44726 +       .name   = "ram",
44727 +       .write  = ram_console_write,
44728 +       .flags  = CON_PRINTBUFFER | CON_ENABLED,
44729 +       .index  = -1,
44730 +};
44731 +
44732 +static void __init
44733 +ram_console_save_old(struct ram_console_buffer *buffer, char *dest)
44734 +{
44735 +       size_t old_log_size = buffer->size;
44736 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
44737 +       uint8_t *block;
44738 +       uint8_t *par;
44739 +       char strbuf[80];
44740 +       int strbuf_len;
44741 +
44742 +       block = buffer->data;
44743 +       par = ram_console_par_buffer;
44744 +       while (block < buffer->data + buffer->size) {
44745 +               int numerr;
44746 +               int size = ECC_BLOCK_SIZE;
44747 +               if (block + size > buffer->data + ram_console_buffer_size)
44748 +                       size = buffer->data + ram_console_buffer_size - block;
44749 +               numerr = ram_console_decode_rs8(block, size, par);
44750 +               if (numerr > 0) {
44751 +#if 0
44752 +                       printk(KERN_INFO "ram_console: error in block %p, %d\n",
44753 +                              block, numerr);
44754 +#endif
44755 +                       ram_console_corrected_bytes += numerr;
44756 +               } else if (numerr < 0) {
44757 +#if 0
44758 +                       printk(KERN_INFO "ram_console: uncorrectable error in "
44759 +                              "block %p\n", block);
44760 +#endif
44761 +                       ram_console_bad_blocks++;
44762 +               }
44763 +               block += ECC_BLOCK_SIZE;
44764 +               par += ECC_SIZE;
44765 +       }
44766 +       if (ram_console_corrected_bytes || ram_console_bad_blocks)
44767 +               strbuf_len = snprintf(strbuf, sizeof(strbuf),
44768 +                       "\n%d Corrected bytes, %d unrecoverable blocks\n",
44769 +                       ram_console_corrected_bytes, ram_console_bad_blocks);
44770 +       else
44771 +               strbuf_len = snprintf(strbuf, sizeof(strbuf),
44772 +                                     "\nNo errors detected\n");
44773 +       if (strbuf_len >= sizeof(strbuf))
44774 +               strbuf_len = sizeof(strbuf) - 1;
44775 +       old_log_size += strbuf_len;
44776 +#endif
44777 +
44778 +       if (dest == NULL) {
44779 +               dest = kmalloc(old_log_size, GFP_KERNEL);
44780 +               if (dest == NULL) {
44781 +                       printk(KERN_ERR
44782 +                              "ram_console: failed to allocate buffer\n");
44783 +                       return;
44784 +               }
44785 +       }
44786 +
44787 +       ram_console_old_log = dest;
44788 +       ram_console_old_log_size = old_log_size;
44789 +       memcpy(ram_console_old_log,
44790 +              &buffer->data[buffer->start], buffer->size - buffer->start);
44791 +       memcpy(ram_console_old_log + buffer->size - buffer->start,
44792 +              &buffer->data[0], buffer->start);
44793 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
44794 +       memcpy(ram_console_old_log + old_log_size - strbuf_len,
44795 +              strbuf, strbuf_len);
44796 +#endif
44797 +}
44798 +
44799 +static int __init ram_console_init(struct ram_console_buffer *buffer,
44800 +                                  size_t buffer_size, char *old_buf)
44801 +{
44802 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
44803 +       int numerr;
44804 +       uint8_t *par;
44805 +#endif
44806 +       ram_console_buffer = buffer;
44807 +       ram_console_buffer_size =
44808 +               buffer_size - sizeof(struct ram_console_buffer);
44809 +
44810 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
44811 +       ram_console_buffer_size -= (DIV_ROUND_UP(ram_console_buffer_size,
44812 +                                               ECC_BLOCK_SIZE) + 1) * ECC_SIZE;
44813 +       ram_console_par_buffer = buffer->data + ram_console_buffer_size;
44814 +
44815 +
44816 +       /* first consecutive root is 0
44817 +        * primitive element to generate roots = 1
44818 +        */
44819 +       ram_console_rs_decoder = init_rs(ECC_SYMSIZE, ECC_POLY, 0, 1, ECC_SIZE);
44820 +       if (ram_console_rs_decoder == NULL) {
44821 +               printk(KERN_INFO "ram_console: init_rs failed\n");
44822 +               return 0;
44823 +       }
44824 +
44825 +       ram_console_corrected_bytes = 0;
44826 +       ram_console_bad_blocks = 0;
44827 +
44828 +       par = ram_console_par_buffer +
44829 +             DIV_ROUND_UP(ram_console_buffer_size, ECC_BLOCK_SIZE) * ECC_SIZE;
44830 +
44831 +       numerr = ram_console_decode_rs8(buffer, sizeof(*buffer), par);
44832 +       if (numerr > 0) {
44833 +               printk(KERN_INFO "ram_console: error in header, %d\n", numerr);
44834 +               ram_console_corrected_bytes += numerr;
44835 +       } else if (numerr < 0) {
44836 +               printk(KERN_INFO
44837 +                      "ram_console: uncorrectable error in header\n");
44838 +               ram_console_bad_blocks++;
44839 +       }
44840 +#endif
44841 +
44842 +       if (buffer->sig == RAM_CONSOLE_SIG) {
44843 +               if (buffer->size > ram_console_buffer_size
44844 +                   || buffer->start > buffer->size)
44845 +                       printk(KERN_INFO "ram_console: found existing invalid "
44846 +                              "buffer, size %d, start %d\n",
44847 +                              buffer->size, buffer->start);
44848 +               else {
44849 +                       printk(KERN_INFO "ram_console: found existing buffer, "
44850 +                              "size %d, start %d\n",
44851 +                              buffer->size, buffer->start);
44852 +                       ram_console_save_old(buffer, old_buf);
44853 +               }
44854 +       } else {
44855 +               printk(KERN_INFO "ram_console: no valid data in buffer "
44856 +                      "(sig = 0x%08x)\n", buffer->sig);
44857 +       }
44858 +
44859 +       buffer->sig = RAM_CONSOLE_SIG;
44860 +       buffer->start = 0;
44861 +       buffer->size = 0;
44862 +
44863 +       register_console(&ram_console);
44864 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE
44865 +       console_verbose();
44866 +#endif
44867 +       return 0;
44868 +}
44869 +
44870 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
44871 +static int __init ram_console_early_init(void)
44872 +{
44873 +       return ram_console_init((struct ram_console_buffer *)
44874 +               CONFIG_ANDROID_RAM_CONSOLE_EARLY_ADDR,
44875 +               CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE,
44876 +               ram_console_old_log_init_buffer);
44877 +}
44878 +#else
44879 +static int ram_console_driver_probe(struct platform_device *pdev)
44880 +{
44881 +       struct resource *res = pdev->resource;
44882 +       size_t start;
44883 +       size_t buffer_size;
44884 +       void *buffer;
44885 +
44886 +       if (res == NULL || pdev->num_resources != 1 ||
44887 +           !(res->flags & IORESOURCE_MEM)) {
44888 +               printk(KERN_ERR "ram_console: invalid resource, %p %d flags "
44889 +                      "%lx\n", res, pdev->num_resources, res ? res->flags : 0);
44890 +               return -ENXIO;
44891 +       }
44892 +       buffer_size = res->end - res->start + 1;
44893 +       start = res->start;
44894 +       printk(KERN_INFO "ram_console: got buffer at %x, size %x\n",
44895 +              start, buffer_size);
44896 +       buffer = ioremap(res->start, buffer_size);
44897 +       if (buffer == NULL) {
44898 +               printk(KERN_ERR "ram_console: failed to map memory\n");
44899 +               return -ENOMEM;
44900 +       }
44901 +
44902 +       return ram_console_init(buffer, buffer_size, NULL/* allocate */);
44903 +}
44904 +
44905 +static struct platform_driver ram_console_driver = {
44906 +       .probe = ram_console_driver_probe,
44907 +       .driver         = {
44908 +               .name   = "ram_console",
44909 +       },
44910 +};
44911 +
44912 +static int __init ram_console_module_init(void)
44913 +{
44914 +       int err;
44915 +       err = platform_driver_register(&ram_console_driver);
44916 +       return err;
44917 +}
44918 +#endif
44919 +
44920 +static ssize_t ram_console_read_old(struct file *file, char __user *buf,
44921 +                                   size_t len, loff_t *offset)
44922 +{
44923 +       loff_t pos = *offset;
44924 +       ssize_t count;
44925 +
44926 +       if (pos >= ram_console_old_log_size)
44927 +               return 0;
44928 +
44929 +       count = min(len, (size_t)(ram_console_old_log_size - pos));
44930 +       if (copy_to_user(buf, ram_console_old_log + pos, count))
44931 +               return -EFAULT;
44932 +
44933 +       *offset += count;
44934 +       return count;
44935 +}
44936 +
44937 +static struct file_operations ram_console_file_ops = {
44938 +       .owner = THIS_MODULE,
44939 +       .read = ram_console_read_old,
44940 +};
44941 +
44942 +static int __init ram_console_late_init(void)
44943 +{
44944 +       struct proc_dir_entry *entry;
44945 +
44946 +       if (ram_console_old_log == NULL)
44947 +               return 0;
44948 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
44949 +       ram_console_old_log = kmalloc(ram_console_old_log_size, GFP_KERNEL);
44950 +       if (ram_console_old_log == NULL) {
44951 +               printk(KERN_ERR
44952 +                      "ram_console: failed to allocate buffer for old log\n");
44953 +               ram_console_old_log_size = 0;
44954 +               return 0;
44955 +       }
44956 +       memcpy(ram_console_old_log,
44957 +              ram_console_old_log_init_buffer, ram_console_old_log_size);
44958 +#endif
44959 +       entry = create_proc_entry("last_kmsg", S_IFREG | S_IRUGO, NULL);
44960 +       if (!entry) {
44961 +               printk(KERN_ERR "ram_console: failed to create proc entry\n");
44962 +               kfree(ram_console_old_log);
44963 +               ram_console_old_log = NULL;
44964 +               return 0;
44965 +       }
44966 +
44967 +       entry->proc_fops = &ram_console_file_ops;
44968 +       entry->size = ram_console_old_log_size;
44969 +       return 0;
44970 +}
44971 +
44972 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
44973 +console_initcall(ram_console_early_init);
44974 +#else
44975 +module_init(ram_console_module_init);
44976 +#endif
44977 +late_initcall(ram_console_late_init);
44978 +
44979 --- /dev/null
44980 +++ b/drivers/android/timed_gpio.c
44981 @@ -0,0 +1,177 @@
44982 +/* drivers/android/timed_gpio.c
44983 + *
44984 + * Copyright (C) 2008 Google, Inc.
44985 + * Author: Mike Lockwood <lockwood@android.com>
44986 + *
44987 + * This software is licensed under the terms of the GNU General Public
44988 + * License version 2, as published by the Free Software Foundation, and
44989 + * may be copied, distributed, and modified under those terms.
44990 + *
44991 + * This program is distributed in the hope that it will be useful,
44992 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
44993 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
44994 + * GNU General Public License for more details.
44995 + *
44996 + */
44997 +
44998 +#include <linux/module.h>
44999 +#include <linux/platform_device.h>
45000 +#include <linux/hrtimer.h>
45001 +#include <linux/err.h>
45002 +#include <mach/gpio.h>
45003 +
45004 +#include <linux/android_timed_gpio.h>
45005 +
45006 +
45007 +static struct class *timed_gpio_class;
45008 +
45009 +struct timed_gpio_data {
45010 +       struct device *dev;
45011 +       struct hrtimer timer;
45012 +       spinlock_t lock;
45013 +       unsigned        gpio;
45014 +       int             max_timeout;
45015 +       u8              active_low;
45016 +};
45017 +
45018 +static enum hrtimer_restart gpio_timer_func(struct hrtimer *timer)
45019 +{
45020 +       struct timed_gpio_data *gpio_data = container_of(timer, struct timed_gpio_data, timer);
45021 +
45022 +       gpio_direction_output(gpio_data->gpio, gpio_data->active_low ? 1 : 0);
45023 +       return HRTIMER_NORESTART;
45024 +}
45025 +
45026 +static ssize_t gpio_enable_show(struct device *dev, struct device_attribute *attr, char *buf)
45027 +{
45028 +       struct timed_gpio_data *gpio_data = dev_get_drvdata(dev);
45029 +       int remaining;
45030 +
45031 +       if (hrtimer_active(&gpio_data->timer)) {
45032 +               ktime_t r = hrtimer_get_remaining(&gpio_data->timer);
45033 +               remaining = r.tv.sec * 1000 + r.tv.nsec / 1000000;
45034 +       } else
45035 +               remaining = 0;
45036 +
45037 +       return sprintf(buf, "%d\n", remaining);
45038 +}
45039 +
45040 +static ssize_t gpio_enable_store(
45041 +               struct device *dev, struct device_attribute *attr,
45042 +               const char *buf, size_t size)
45043 +{
45044 +       struct timed_gpio_data *gpio_data = dev_get_drvdata(dev);
45045 +       int value;
45046 +       unsigned long   flags;
45047 +
45048 +       sscanf(buf, "%d", &value);
45049 +
45050 +       spin_lock_irqsave(&gpio_data->lock, flags);
45051 +
45052 +       /* cancel previous timer and set GPIO according to value */
45053 +       hrtimer_cancel(&gpio_data->timer);
45054 +       gpio_direction_output(gpio_data->gpio, gpio_data->active_low ? !value : !!value);
45055 +
45056 +       if (value > 0) {
45057 +               if (value > gpio_data->max_timeout)
45058 +                       value = gpio_data->max_timeout;
45059 +
45060 +               hrtimer_start(&gpio_data->timer,
45061 +                                               ktime_set(value / 1000, (value % 1000) * 1000000),
45062 +                                               HRTIMER_MODE_REL);
45063 +       }
45064 +
45065 +       spin_unlock_irqrestore(&gpio_data->lock, flags);
45066 +
45067 +       return size;
45068 +}
45069 +
45070 +static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, gpio_enable_show, gpio_enable_store);
45071 +
45072 +static int android_timed_gpio_probe(struct platform_device *pdev)
45073 +{
45074 +       struct timed_gpio_platform_data *pdata = pdev->dev.platform_data;
45075 +       struct timed_gpio *cur_gpio;
45076 +       struct timed_gpio_data *gpio_data, *gpio_dat;
45077 +       int i, ret = 0;
45078 +
45079 +       if (!pdata)
45080 +               return -EBUSY;
45081 +
45082 +       gpio_data = kzalloc(sizeof(struct timed_gpio_data) * pdata->num_gpios, GFP_KERNEL);
45083 +       if (!gpio_data)
45084 +               return -ENOMEM;
45085 +
45086 +       for (i = 0; i < pdata->num_gpios; i++) {
45087 +               cur_gpio = &pdata->gpios[i];
45088 +               gpio_dat = &gpio_data[i];
45089 +
45090 +               hrtimer_init(&gpio_dat->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
45091 +               gpio_dat->timer.function = gpio_timer_func;
45092 +               spin_lock_init(&gpio_dat->lock);
45093 +
45094 +               gpio_dat->gpio = cur_gpio->gpio;
45095 +               gpio_dat->max_timeout = cur_gpio->max_timeout;
45096 +               gpio_dat->active_low = cur_gpio->active_low;
45097 +               gpio_direction_output(gpio_dat->gpio, gpio_dat->active_low);
45098 +
45099 +               gpio_dat->dev = device_create(timed_gpio_class, &pdev->dev, 0, "%s", cur_gpio->name);
45100 +               if (unlikely(IS_ERR(gpio_dat->dev)))
45101 +                       return PTR_ERR(gpio_dat->dev);
45102 +
45103 +               dev_set_drvdata(gpio_dat->dev, gpio_dat);
45104 +               ret = device_create_file(gpio_dat->dev, &dev_attr_enable);
45105 +               if (ret)
45106 +                       return ret;
45107 +       }
45108 +
45109 +       platform_set_drvdata(pdev, gpio_data);
45110 +
45111 +       return 0;
45112 +}
45113 +
45114 +static int android_timed_gpio_remove(struct platform_device *pdev)
45115 +{
45116 +       struct timed_gpio_platform_data *pdata = pdev->dev.platform_data;
45117 +       struct timed_gpio_data *gpio_data = platform_get_drvdata(pdev);
45118 +       int i;
45119 +
45120 +       for (i = 0; i < pdata->num_gpios; i++) {
45121 +               device_remove_file(gpio_data[i].dev, &dev_attr_enable);
45122 +               device_unregister(gpio_data[i].dev);
45123 +       }
45124 +
45125 +       kfree(gpio_data);
45126 +
45127 +       return 0;
45128 +}
45129 +
45130 +static struct platform_driver android_timed_gpio_driver = {
45131 +       .probe          = android_timed_gpio_probe,
45132 +       .remove         = android_timed_gpio_remove,
45133 +       .driver         = {
45134 +               .name           = "android-timed-gpio",
45135 +               .owner          = THIS_MODULE,
45136 +       },
45137 +};
45138 +
45139 +static int __init android_timed_gpio_init(void)
45140 +{
45141 +       timed_gpio_class = class_create(THIS_MODULE, "timed_output");
45142 +       if (IS_ERR(timed_gpio_class))
45143 +               return PTR_ERR(timed_gpio_class);
45144 +       return platform_driver_register(&android_timed_gpio_driver);
45145 +}
45146 +
45147 +static void __exit android_timed_gpio_exit(void)
45148 +{
45149 +       class_destroy(timed_gpio_class);
45150 +       platform_driver_unregister(&android_timed_gpio_driver);
45151 +}
45152 +
45153 +module_init(android_timed_gpio_init);
45154 +module_exit(android_timed_gpio_exit);
45155 +
45156 +MODULE_AUTHOR("Mike Lockwood <lockwood@android.com>");
45157 +MODULE_DESCRIPTION("Android timed gpio driver");
45158 +MODULE_LICENSE("GPL");
45159 --- /dev/null
45160 +++ b/drivers/ar6000/ar6000/ar6000_drv.c
45161 @@ -0,0 +1,3124 @@
45162 +/*
45163 + *
45164 + * Copyright (c) 2004-2007 Atheros Communications Inc.
45165 + * All rights reserved.
45166 + *
45167 + *
45168 + *  This program is free software; you can redistribute it and/or modify
45169 + *  it under the terms of the GNU General Public License version 2 as
45170 + *  published by the Free Software Foundation;
45171 + *
45172 + *  Software distributed under the License is distributed on an "AS
45173 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
45174 + *  implied. See the License for the specific language governing
45175 + *  rights and limitations under the License.
45176 + *
45177 + *
45178 + *
45179 + */
45180 +
45181 +/*
45182 + * This driver is a pseudo ethernet driver to access the Atheros AR6000
45183 + * WLAN Device
45184 + */
45185 +static const char athId[] __attribute__ ((unused)) = "$Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/ar6000_drv.c#2 $";
45186 +
45187 +#include "ar6000_drv.h"
45188 +#include "htc.h"
45189 +
45190 +MODULE_LICENSE("GPL and additional rights");
45191 +
45192 +#ifndef REORG_APTC_HEURISTICS
45193 +#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45194 +#endif /* REORG_APTC_HEURISTICS */
45195 +
45196 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45197 +#define APTC_TRAFFIC_SAMPLING_INTERVAL     100  /* msec */
45198 +#define APTC_UPPER_THROUGHPUT_THRESHOLD    3000 /* Kbps */
45199 +#define APTC_LOWER_THROUGHPUT_THRESHOLD    2000 /* Kbps */
45200 +
45201 +typedef struct aptc_traffic_record {
45202 +    A_BOOL timerScheduled;
45203 +    struct timeval samplingTS;
45204 +    unsigned long bytesReceived;
45205 +    unsigned long bytesTransmitted;
45206 +} APTC_TRAFFIC_RECORD;
45207 +
45208 +A_TIMER aptcTimer;
45209 +APTC_TRAFFIC_RECORD aptcTR;
45210 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45211 +
45212 +int bmienable = 0;
45213 +unsigned int bypasswmi = 0;
45214 +unsigned int debuglevel = 0;
45215 +int tspecCompliance = 1;
45216 +unsigned int busspeedlow = 0;
45217 +unsigned int onebitmode = 0;
45218 +unsigned int skipflash = 0;
45219 +unsigned int wmitimeout = 2;
45220 +unsigned int wlanNodeCaching = 1;
45221 +unsigned int enableuartprint = 0;
45222 +unsigned int logWmiRawMsgs = 0;
45223 +unsigned int enabletimerwar = 0;
45224 +unsigned int mbox_yield_limit = 99;
45225 +int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF;
45226 +int allow_trace_signal = 0;
45227 +#ifdef CONFIG_HOST_TCMD_SUPPORT
45228 +unsigned int testmode =0;
45229 +#endif
45230 +
45231 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
45232 +module_param(bmienable, int, 0644);
45233 +module_param(bypasswmi, int, 0644);
45234 +module_param(debuglevel, int, 0644);
45235 +module_param(tspecCompliance, int, 0644);
45236 +module_param(onebitmode, int, 0644);
45237 +module_param(busspeedlow, int, 0644);
45238 +module_param(skipflash, int, 0644);
45239 +module_param(wmitimeout, int, 0644);
45240 +module_param(wlanNodeCaching, int, 0644);
45241 +module_param(logWmiRawMsgs, int, 0644);
45242 +module_param(enableuartprint, int, 0644);
45243 +module_param(enabletimerwar, int, 0644);
45244 +module_param(mbox_yield_limit, int, 0644);
45245 +module_param(reduce_credit_dribble, int, 0644);
45246 +module_param(allow_trace_signal, int, 0644);
45247 +#ifdef CONFIG_HOST_TCMD_SUPPORT
45248 +module_param(testmode, int, 0644);
45249 +#endif
45250 +#else
45251 +
45252 +#define __user
45253 +/* for linux 2.4 and lower */
45254 +MODULE_PARM(bmienable,"i");
45255 +MODULE_PARM(bypasswmi,"i");
45256 +MODULE_PARM(debuglevel, "i");
45257 +MODULE_PARM(onebitmode,"i");
45258 +MODULE_PARM(busspeedlow, "i");
45259 +MODULE_PARM(skipflash, "i");
45260 +MODULE_PARM(wmitimeout, "i");
45261 +MODULE_PARM(wlanNodeCaching, "i");
45262 +MODULE_PARM(enableuartprint,"i");
45263 +MODULE_PARM(logWmiRawMsgs, "i");
45264 +MODULE_PARM(enabletimerwar,"i");
45265 +MODULE_PARM(mbox_yield_limit,"i");
45266 +MODULE_PARM(reduce_credit_dribble,"i");
45267 +MODULE_PARM(allow_trace_signal,"i");
45268 +#ifdef CONFIG_HOST_TCMD_SUPPORT
45269 +MODULE_PARM(testmode, "i");
45270 +#endif
45271 +#endif
45272 +
45273 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10)
45274 +/* in 2.6.10 and later this is now a pointer to a uint */
45275 +unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX;
45276 +#define mboxnum &_mboxnum
45277 +#else
45278 +unsigned int mboxnum = HTC_MAILBOX_NUM_MAX;
45279 +#endif
45280 +
45281 +#ifdef DEBUG
45282 +A_UINT32 g_dbg_flags = DBG_DEFAULTS;
45283 +unsigned int debugflags = 0;
45284 +int debugdriver = 1;
45285 +unsigned int debughtc = 128;
45286 +unsigned int debugbmi = 1;
45287 +unsigned int debughif = 2;
45288 +unsigned int resetok = 1;
45289 +unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0};
45290 +unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0};
45291 +unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0};
45292 +unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0};
45293 +
45294 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
45295 +module_param(debugflags, int, 0644);
45296 +module_param(debugdriver, int, 0644);
45297 +module_param(debughtc, int, 0644);
45298 +module_param(debugbmi, int, 0644);
45299 +module_param(debughif, int, 0644);
45300 +module_param(resetok, int, 0644);
45301 +module_param_array(txcreditsavailable, int, mboxnum, 0644);
45302 +module_param_array(txcreditsconsumed, int, mboxnum, 0644);
45303 +module_param_array(txcreditintrenable, int, mboxnum, 0644);
45304 +module_param_array(txcreditintrenableaggregate, int, mboxnum, 0644);
45305 +#else
45306 +/* linux 2.4 and lower */
45307 +MODULE_PARM(debugflags,"i");
45308 +MODULE_PARM(debugdriver, "i");
45309 +MODULE_PARM(debughtc, "i");
45310 +MODULE_PARM(debugbmi, "i");
45311 +MODULE_PARM(debughif, "i");
45312 +MODULE_PARM(resetok, "i");
45313 +MODULE_PARM(txcreditsavailable, "0-3i");
45314 +MODULE_PARM(txcreditsconsumed, "0-3i");
45315 +MODULE_PARM(txcreditintrenable, "0-3i");
45316 +MODULE_PARM(txcreditintrenableaggregate, "0-3i");
45317 +#endif
45318 +
45319 +#else
45320 +unsigned int resetok = 1;
45321 +
45322 +#endif /* DEBUG */
45323 +
45324 +unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0};
45325 +unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0};
45326 +unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0};
45327 +unsigned int hifBusRequestNumMax = 40;
45328 +unsigned int war23838_disabled = 0;
45329 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45330 +unsigned int enableAPTCHeuristics = 1;
45331 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45332 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
45333 +module_param_array(tx_attempt, int, mboxnum, 0644);
45334 +module_param_array(tx_post, int, mboxnum, 0644);
45335 +module_param_array(tx_complete, int, mboxnum, 0644);
45336 +module_param(hifBusRequestNumMax, int, 0644);
45337 +module_param(war23838_disabled, int, 0644);
45338 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45339 +module_param(enableAPTCHeuristics, int, 0644);
45340 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45341 +#else
45342 +MODULE_PARM(tx_attempt, "0-3i");
45343 +MODULE_PARM(tx_post, "0-3i");
45344 +MODULE_PARM(tx_complete, "0-3i");
45345 +MODULE_PARM(hifBusRequestNumMax, "i");
45346 +MODULE_PARM(war23838_disabled, "i");
45347 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45348 +MODULE_PARM(enableAPTCHeuristics, "i");
45349 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45350 +#endif
45351 +
45352 +#ifdef BLOCK_TX_PATH_FLAG
45353 +int blocktx = 0;
45354 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
45355 +module_param(blocktx, int, 0644);
45356 +#else
45357 +MODULE_PARM(blocktx, "i");
45358 +#endif
45359 +#endif /* BLOCK_TX_PATH_FLAG */
45360 +
45361 +// TODO move to arsoft_c
45362 +USER_RSSI_THOLD rssi_map[12];
45363 +
45364 +int reconnect_flag = 0;
45365 +
45366 +DECLARE_WAIT_QUEUE_HEAD(ar6000_scan_queue);
45367 +
45368 +/* Function declarations */
45369 +static int ar6000_init_module(void);
45370 +static void ar6000_cleanup_module(void);
45371 +
45372 +int ar6000_init(struct net_device *dev);
45373 +static int ar6000_open(struct net_device *dev);
45374 +static int ar6000_close(struct net_device *dev);
45375 +static void ar6000_init_control_info(AR_SOFTC_T *ar);
45376 +static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev);
45377 +
45378 +static void ar6000_destroy(struct net_device *dev, unsigned int unregister);
45379 +static void ar6000_detect_error(unsigned long ptr);
45380 +static struct net_device_stats *ar6000_get_stats(struct net_device *dev);
45381 +static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev);
45382 +
45383 +/*
45384 + * HTC service connection handlers
45385 + */
45386 +static void ar6000_avail_ev(HTC_HANDLE HTCHandle);
45387 +
45388 +static void ar6000_unavail_ev(void *Instance);
45389 +
45390 +static void ar6000_target_failure(void *Instance, A_STATUS Status);
45391 +
45392 +static void ar6000_rx(void *Context, HTC_PACKET *pPacket);
45393 +
45394 +static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint);
45395 +
45396 +static void ar6000_tx_complete(void *Context, HTC_PACKET *pPacket);
45397 +
45398 +static void ar6000_tx_queue_full(void *Context, HTC_ENDPOINT_ID Endpoint);
45399 +
45400 +/*
45401 + * Static variables
45402 + */
45403 +
45404 +static struct net_device *ar6000_devices[MAX_AR6000];
45405 +extern struct iw_handler_def ath_iw_handler_def;
45406 +DECLARE_WAIT_QUEUE_HEAD(arEvent);
45407 +static void ar6000_cookie_init(AR_SOFTC_T *ar);
45408 +static void ar6000_cookie_cleanup(AR_SOFTC_T *ar);
45409 +static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie);
45410 +static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar);
45411 +static void ar6000_TxDataCleanup(AR_SOFTC_T *ar);
45412 +
45413 +#ifdef USER_KEYS
45414 +static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl);
45415 +#endif
45416 +
45417 +
45418 +static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM];
45419 +
45420 +#define HOST_INTEREST_ITEM_ADDRESS(ar, item)    \
45421 +((ar->arTargetType == TARGET_TYPE_AR6001) ?     \
45422 +   AR6001_HOST_INTEREST_ITEM_ADDRESS(item) :    \
45423 +   AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
45424 +
45425 +
45426 +/* Debug log support */
45427 +
45428 +/*
45429 + * Flag to govern whether the debug logs should be parsed in the kernel
45430 + * or reported to the application.
45431 + */
45432 +#ifdef DEBUG
45433 +#define REPORT_DEBUG_LOGS_TO_APP
45434 +#endif
45435 +
45436 +A_STATUS
45437 +ar6000_set_host_app_area(AR_SOFTC_T *ar)
45438 +{
45439 +    A_UINT32 address, data;
45440 +    struct host_app_area_s host_app_area;
45441 +
45442 +    /* Fetch the address of the host_app_area_s instance in the host interest area */
45443 +    address = HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest);
45444 +    if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) {
45445 +        return A_ERROR;
45446 +    }
45447 +    address = data;
45448 +    host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION;
45449 +    if (ar6000_WriteDataDiag(ar->arHifDevice, address,
45450 +                             (A_UCHAR *)&host_app_area,
45451 +                             sizeof(struct host_app_area_s)) != A_OK)
45452 +    {
45453 +        return A_ERROR;
45454 +    }
45455 +
45456 +    return A_OK;
45457 +}
45458 +
45459 +A_UINT32
45460 +dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar)
45461 +{
45462 +    A_UINT32 param;
45463 +    A_UINT32 address;
45464 +    A_STATUS status;
45465 +
45466 +    address = HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr);
45467 +    if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address,
45468 +                                      (A_UCHAR *)&param, 4)) != A_OK)
45469 +    {
45470 +        param = 0;
45471 +    }
45472 +
45473 +    return param;
45474 +}
45475 +
45476 +/*
45477 + * The dbglog module has been initialized. Its ok to access the relevant
45478 + * data stuctures over the diagnostic window.
45479 + */
45480 +void
45481 +ar6000_dbglog_init_done(AR_SOFTC_T *ar)
45482 +{
45483 +    ar->dbglog_init_done = TRUE;
45484 +}
45485 +
45486 +A_UINT32
45487 +dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit)
45488 +{
45489 +    A_INT32 *buffer;
45490 +    A_UINT32 count;
45491 +    A_UINT32 numargs;
45492 +    A_UINT32 length;
45493 +    A_UINT32 fraglen;
45494 +
45495 +    count = fraglen = 0;
45496 +    buffer = (A_INT32 *)datap;
45497 +    length = (limit >> 2);
45498 +
45499 +    if (len <= limit) {
45500 +        fraglen = len;
45501 +    } else {
45502 +        while (count < length) {
45503 +            numargs = DBGLOG_GET_NUMARGS(buffer[count]);
45504 +            fraglen = (count << 2);
45505 +            count += numargs + 1;
45506 +        }
45507 +    }
45508 +
45509 +    return fraglen;
45510 +}
45511 +
45512 +void
45513 +dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len)
45514 +{
45515 +    A_INT32 *buffer;
45516 +    A_UINT32 count;
45517 +    A_UINT32 timestamp;
45518 +    A_UINT32 debugid;
45519 +    A_UINT32 moduleid;
45520 +    A_UINT32 numargs;
45521 +    A_UINT32 length;
45522 +
45523 +    count = 0;
45524 +    buffer = (A_INT32 *)datap;
45525 +    length = (len >> 2);
45526 +    while (count < length) {
45527 +        debugid = DBGLOG_GET_DBGID(buffer[count]);
45528 +        moduleid = DBGLOG_GET_MODULEID(buffer[count]);
45529 +        numargs = DBGLOG_GET_NUMARGS(buffer[count]);
45530 +        timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]);
45531 +        switch (numargs) {
45532 +            case 0:
45533 +            AR_DEBUG_PRINTF("%d %d (%d)\n", moduleid, debugid, timestamp);
45534 +            break;
45535 +
45536 +            case 1:
45537 +            AR_DEBUG_PRINTF("%d %d (%d): 0x%x\n", moduleid, debugid,
45538 +                            timestamp, buffer[count+1]);
45539 +            break;
45540 +
45541 +            case 2:
45542 +            AR_DEBUG_PRINTF("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid,
45543 +                            timestamp, buffer[count+1], buffer[count+2]);
45544 +            break;
45545 +
45546 +            default:
45547 +            AR_DEBUG_PRINTF("Invalid args: %d\n", numargs);
45548 +        }
45549 +        count += numargs + 1;
45550 +    }
45551 +}
45552 +
45553 +int
45554 +ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar)
45555 +{
45556 +    struct dbglog_hdr_s debug_hdr;
45557 +    struct dbglog_buf_s debug_buf;
45558 +    A_UINT32 address;
45559 +    A_UINT32 length;
45560 +    A_UINT32 dropped;
45561 +    A_UINT32 firstbuf;
45562 +    A_UINT32 debug_hdr_ptr;
45563 +
45564 +    if (!ar->dbglog_init_done) return A_ERROR;
45565 +
45566 +
45567 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
45568 +
45569 +    if (ar->dbgLogFetchInProgress) {
45570 +        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
45571 +        return A_EBUSY;
45572 +    }
45573 +
45574 +        /* block out others */
45575 +    ar->dbgLogFetchInProgress = TRUE;
45576 +
45577 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
45578 +
45579 +    debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar);
45580 +    printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr);
45581 +
45582 +    /* Get the contents of the ring buffer */
45583 +    if (debug_hdr_ptr) {
45584 +        address = debug_hdr_ptr;
45585 +        length = sizeof(struct dbglog_hdr_s);
45586 +        ar6000_ReadDataDiag(ar->arHifDevice, address,
45587 +                            (A_UCHAR *)&debug_hdr, length);
45588 +        address = (A_UINT32)debug_hdr.dbuf;
45589 +        firstbuf = address;
45590 +        dropped = debug_hdr.dropped;
45591 +        length = sizeof(struct dbglog_buf_s);
45592 +        ar6000_ReadDataDiag(ar->arHifDevice, address,
45593 +                            (A_UCHAR *)&debug_buf, length);
45594 +
45595 +        do {
45596 +            address = (A_UINT32)debug_buf.buffer;
45597 +            length = debug_buf.length;
45598 +            if ((length) && (debug_buf.length <= debug_buf.bufsize)) {
45599 +                /* Rewind the index if it is about to overrun the buffer */
45600 +                if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) {
45601 +                    ar->log_cnt = 0;
45602 +                }
45603 +                if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
45604 +                                    (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length))
45605 +                {
45606 +                    break;
45607 +                }
45608 +                ar6000_dbglog_event(ar, dropped, &ar->log_buffer[ar->log_cnt], length);
45609 +                ar->log_cnt += length;
45610 +            } else {
45611 +                AR_DEBUG_PRINTF("Length: %d (Total size: %d)\n",
45612 +                                debug_buf.length, debug_buf.bufsize);
45613 +            }
45614 +
45615 +            address = (A_UINT32)debug_buf.next;
45616 +            length = sizeof(struct dbglog_buf_s);
45617 +            if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
45618 +                                (A_UCHAR *)&debug_buf, length))
45619 +            {
45620 +                break;
45621 +            }
45622 +
45623 +        } while (address != firstbuf);
45624 +    }
45625 +
45626 +    ar->dbgLogFetchInProgress = FALSE;
45627 +
45628 +    return A_OK;
45629 +}
45630 +
45631 +void
45632 +ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped,
45633 +                    A_INT8 *buffer, A_UINT32 length)
45634 +{
45635 +#ifdef REPORT_DEBUG_LOGS_TO_APP
45636 +    #define MAX_WIRELESS_EVENT_SIZE 252
45637 +    /*
45638 +     * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages.
45639 +     * There seems to be a limitation on the length of message that could be
45640 +     * transmitted to the user app via this mechanism.
45641 +     */
45642 +    A_UINT32 send, sent;
45643 +
45644 +    sent = 0;
45645 +    send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
45646 +                                     MAX_WIRELESS_EVENT_SIZE);
45647 +    while (send) {
45648 +        ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, &buffer[sent], send);
45649 +        sent += send;
45650 +        send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
45651 +                                         MAX_WIRELESS_EVENT_SIZE);
45652 +    }
45653 +#else
45654 +    AR_DEBUG_PRINTF("Dropped logs: 0x%x\nDebug info length: %d\n",
45655 +                    dropped, length);
45656 +
45657 +    /* Interpret the debug logs */
45658 +    dbglog_parse_debug_logs(buffer, length);
45659 +#endif /* REPORT_DEBUG_LOGS_TO_APP */
45660 +}
45661 +
45662 +
45663 +
45664 +static int __init
45665 +ar6000_init_module(void)
45666 +{
45667 +    static int probed = 0;
45668 +    A_STATUS status;
45669 +    HTC_INIT_INFO initInfo;
45670 +
45671 +    A_MEMZERO(&initInfo,sizeof(initInfo));
45672 +    initInfo.AddInstance = ar6000_avail_ev;
45673 +    initInfo.DeleteInstance = ar6000_unavail_ev;
45674 +    initInfo.TargetFailure = ar6000_target_failure;
45675 +
45676 +
45677 +#ifdef DEBUG
45678 +    /* Set the debug flags if specified at load time */
45679 +    if(debugflags != 0)
45680 +    {
45681 +        g_dbg_flags = debugflags;
45682 +    }
45683 +#endif
45684 +
45685 +    if (probed) {
45686 +        return -ENODEV;
45687 +    }
45688 +    probed++;
45689 +
45690 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45691 +    memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD));
45692 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45693 +
45694 +#ifdef CONFIG_HOST_GPIO_SUPPORT
45695 +    ar6000_gpio_init();
45696 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
45697 +
45698 +    status = HTCInit(&initInfo);
45699 +    if(status != A_OK)
45700 +        return -ENODEV;
45701 +
45702 +    return 0;
45703 +}
45704 +
45705 +static void __exit
45706 +ar6000_cleanup_module(void)
45707 +{
45708 +    int i = 0;
45709 +    struct net_device *ar6000_netdev;
45710 +
45711 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45712 +    /* Delete the Adaptive Power Control timer */
45713 +    if (timer_pending(&aptcTimer)) {
45714 +        del_timer_sync(&aptcTimer);
45715 +    }
45716 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45717 +
45718 +    for (i=0; i < MAX_AR6000; i++) {
45719 +        if (ar6000_devices[i] != NULL) {
45720 +            ar6000_netdev = ar6000_devices[i];
45721 +            ar6000_devices[i] = NULL;
45722 +            ar6000_destroy(ar6000_netdev, 1);
45723 +        }
45724 +    }
45725 +
45726 +        /* shutting down HTC will cause the HIF layer to detach from the
45727 +         * underlying bus driver which will cause the subsequent deletion of
45728 +         * all HIF and HTC instances */
45729 +    HTCShutDown();
45730 +
45731 +    AR_DEBUG_PRINTF("ar6000_cleanup: success\n");
45732 +}
45733 +
45734 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45735 +void
45736 +aptcTimerHandler(unsigned long arg)
45737 +{
45738 +    A_UINT32 numbytes;
45739 +    A_UINT32 throughput;
45740 +    AR_SOFTC_T *ar;
45741 +    A_STATUS status;
45742 +
45743 +    ar = (AR_SOFTC_T *)arg;
45744 +    A_ASSERT(ar != NULL);
45745 +    A_ASSERT(!timer_pending(&aptcTimer));
45746 +
45747 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
45748 +
45749 +    /* Get the number of bytes transferred */
45750 +    numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
45751 +    aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
45752 +
45753 +    /* Calculate and decide based on throughput thresholds */
45754 +    throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */
45755 +    if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) {
45756 +        /* Enable Sleep and delete the timer */
45757 +        A_ASSERT(ar->arWmiReady == TRUE);
45758 +        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
45759 +        status = wmi_powermode_cmd(ar->arWmi, REC_POWER);
45760 +        AR6000_SPIN_LOCK(&ar->arLock, 0);
45761 +        A_ASSERT(status == A_OK);
45762 +        aptcTR.timerScheduled = FALSE;
45763 +    } else {
45764 +        A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
45765 +    }
45766 +
45767 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
45768 +}
45769 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45770 +
45771 +
45772 +
45773 +/* set HTC block size, assume BMI is already initialized */
45774 +A_STATUS ar6000_SetHTCBlockSize(AR_SOFTC_T *ar)
45775 +{
45776 +    A_STATUS status;
45777 +    A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
45778 +
45779 +    do {
45780 +            /* get the block sizes */
45781 +        status = HIFConfigureDevice(ar->arHifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
45782 +                                    blocksizes, sizeof(blocksizes));
45783 +
45784 +        if (A_FAILED(status)) {
45785 +            AR_DEBUG_PRINTF("Failed to get block size info from HIF layer...\n");
45786 +            break;
45787 +        }
45788 +            /* note: we actually get the block size for mailbox 1, for SDIO the block
45789 +             * size on mailbox 0 is artificially set to 1 */
45790 +            /* must be a power of 2 */
45791 +        A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0);
45792 +
45793 +            /* set the host interest area for the block size */
45794 +        status = BMIWriteMemory(ar->arHifDevice,
45795 +                                HOST_INTEREST_ITEM_ADDRESS(ar, hi_mbox_io_block_sz),
45796 +                                (A_UCHAR *)&blocksizes[1],
45797 +                                4);
45798 +
45799 +        if (A_FAILED(status)) {
45800 +            AR_DEBUG_PRINTF("BMIWriteMemory for IO block size failed \n");
45801 +            break;
45802 +        }
45803 +
45804 +        AR_DEBUG_PRINTF("Block Size Set: %d (target address:0x%X)\n",
45805 +                blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(ar, hi_mbox_io_block_sz));
45806 +
45807 +            /* set the host interest area for the mbox ISR yield limit */
45808 +        status = BMIWriteMemory(ar->arHifDevice,
45809 +                                HOST_INTEREST_ITEM_ADDRESS(ar, hi_mbox_isr_yield_limit),
45810 +                                (A_UCHAR *)&mbox_yield_limit,
45811 +                                4);
45812 +
45813 +        if (A_FAILED(status)) {
45814 +            AR_DEBUG_PRINTF("BMIWriteMemory for yield limit failed \n");
45815 +            break;
45816 +        }
45817 +
45818 +    } while (FALSE);
45819 +
45820 +    return status;
45821 +}
45822 +
45823 +static void free_raw_buffers(AR_SOFTC_T *ar)
45824 +{
45825 +    int i, j;
45826 +
45827 +    for (i = 0; i != HTC_RAW_STREAM_NUM_MAX; i++) {
45828 +       for (j = 0; j != RAW_HTC_READ_BUFFERS_NUM; j++)
45829 +           kfree(ar->raw_htc_read_buffer[i][j]);
45830 +       for (j = 0; j != RAW_HTC_WRITE_BUFFERS_NUM; j++)
45831 +           kfree(ar->raw_htc_write_buffer[i][j]);
45832 +    }
45833 +}
45834 +
45835 +static int alloc_raw_buffers(AR_SOFTC_T *ar)
45836 +{
45837 +    int i, j;
45838 +    raw_htc_buffer *b;
45839 +
45840 +    for (i = 0; i != HTC_RAW_STREAM_NUM_MAX; i++) {
45841 +       for (j = 0; j != RAW_HTC_READ_BUFFERS_NUM; j++) {
45842 +           b = kzalloc(sizeof(*b), GFP_KERNEL);
45843 +           if (!b)
45844 +               return -ENOMEM;
45845 +           ar->raw_htc_read_buffer[i][j] = b;
45846 +       }
45847 +       for (j = 0; j != RAW_HTC_WRITE_BUFFERS_NUM; j++) {
45848 +           b = kzalloc(sizeof(*b), GFP_KERNEL);
45849 +           if (!b)
45850 +               return -ENOMEM;
45851 +           ar->raw_htc_write_buffer[i][j] = b;
45852 +       }
45853 +    }
45854 +    return 0;
45855 +}
45856 +
45857 +/*
45858 + * HTC Event handlers
45859 + */
45860 +static void
45861 +ar6000_avail_ev(HTC_HANDLE HTCHandle)
45862 +{
45863 +    int i;
45864 +    struct net_device *dev;
45865 +    AR_SOFTC_T *ar;
45866 +    int device_index = 0;
45867 +
45868 +    AR_DEBUG_PRINTF("ar6000_available\n");
45869 +
45870 +    for (i=0; i < MAX_AR6000; i++) {
45871 +        if (ar6000_devices[i] == NULL) {
45872 +            break;
45873 +        }
45874 +    }
45875 +
45876 +    if (i == MAX_AR6000) {
45877 +        AR_DEBUG_PRINTF("ar6000_available: max devices reached\n");
45878 +        return;
45879 +    }
45880 +
45881 +    /* Save this. It gives a bit better readability especially since */
45882 +    /* we use another local "i" variable below.                      */
45883 +    device_index = i;
45884 +
45885 +    A_ASSERT(HTCHandle != NULL);
45886 +
45887 +    dev = alloc_etherdev(sizeof(AR_SOFTC_T));
45888 +    if (dev == NULL) {
45889 +        AR_DEBUG_PRINTF("ar6000_available: can't alloc etherdev\n");
45890 +        return;
45891 +    }
45892 +
45893 +    ether_setup(dev);
45894 +
45895 +    if (dev->priv == NULL) {
45896 +        printk(KERN_CRIT "ar6000_available: Could not allocate memory\n");
45897 +        return;
45898 +    }
45899 +
45900 +    A_MEMZERO(dev->priv, sizeof(AR_SOFTC_T));
45901 +
45902 +    ar                       = (AR_SOFTC_T *)dev->priv;
45903 +    ar->arNetDev             = dev;
45904 +    ar->arHtcTarget          = HTCHandle;
45905 +    ar->arHifDevice          = HTCGetHifDevice(HTCHandle);
45906 +    ar->arWlanState          = WLAN_ENABLED;
45907 +    ar->arRadioSwitch        = WLAN_ENABLED;
45908 +    ar->arDeviceIndex        = device_index;
45909 +
45910 +    A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev);
45911 +    ar->arHBChallengeResp.seqNum = 0;
45912 +    ar->arHBChallengeResp.outstanding = FALSE;
45913 +    ar->arHBChallengeResp.missCnt = 0;
45914 +    ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT;
45915 +    ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT;
45916 +
45917 +    ar6000_init_control_info(ar);
45918 +    init_waitqueue_head(&arEvent);
45919 +    sema_init(&ar->arSem, 1);
45920 +
45921 +    if (alloc_raw_buffers(ar)) {
45922 +       free_raw_buffers(ar);
45923 +       /*
45924 +        * @@@ Clean up our own mess, but for anything else, cheerfully mimick
45925 +        * the beautiful error non-handling of the rest of this function.
45926 +        */
45927 +       return;
45928 +    }
45929 +
45930 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45931 +    A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar);
45932 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45933 +
45934 +    /*
45935 +     * If requested, perform some magic which requires no cooperation from
45936 +     * the Target.  It causes the Target to ignore flash and execute to the
45937 +     * OS from ROM.
45938 +     *
45939 +     * This is intended to support recovery from a corrupted flash on Targets
45940 +     * that support flash.
45941 +     */
45942 +    if (skipflash)
45943 +    {
45944 +        ar6000_reset_device_skipflash(ar->arHifDevice);
45945 +            }
45946 +
45947 +    BMIInit();
45948 +    {
45949 +        struct bmi_target_info targ_info;
45950 +
45951 +        if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) {
45952 +            return;
45953 +        }
45954 +
45955 +        ar->arVersion.target_ver = targ_info.target_ver;
45956 +        ar->arTargetType = targ_info.target_type;
45957 +    }
45958 +
45959 +    if (enableuartprint) {
45960 +        A_UINT32 param;
45961 +        param = 1;
45962 +        if (BMIWriteMemory(ar->arHifDevice,
45963 +                           HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable),
45964 +                           (A_UCHAR *)&param,
45965 +                           4)!= A_OK)
45966 +        {
45967 +             AR_DEBUG_PRINTF("BMIWriteMemory for enableuartprint failed \n");
45968 +             return ;
45969 +        }
45970 +        AR_DEBUG_PRINTF("Serial console prints enabled\n");
45971 +    }
45972 +#ifdef CONFIG_HOST_TCMD_SUPPORT
45973 +    if(testmode) {
45974 +        ar->arTargetMode = AR6000_TCMD_MODE;
45975 +    }else {
45976 +        ar->arTargetMode = AR6000_WLAN_MODE;
45977 +    }
45978 +#endif
45979 +    if (enabletimerwar) {
45980 +        A_UINT32 param;
45981 +
45982 +        if (BMIReadMemory(ar->arHifDevice,
45983 +            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
45984 +            (A_UCHAR *)&param,
45985 +            4)!= A_OK)
45986 +        {
45987 +            AR_DEBUG_PRINTF("BMIReadMemory for enabletimerwar failed \n");
45988 +            return;
45989 +        }
45990 +
45991 +        param |= HI_OPTION_TIMER_WAR;
45992 +
45993 +        if (BMIWriteMemory(ar->arHifDevice,
45994 +            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
45995 +            (A_UCHAR *)&param,
45996 +            4) != A_OK)
45997 +        {
45998 +            AR_DEBUG_PRINTF("BMIWriteMemory for enabletimerwar failed \n");
45999 +            return;
46000 +        }
46001 +        AR_DEBUG_PRINTF("Timer WAR enabled\n");
46002 +    }
46003 +
46004 +
46005 +        /* since BMIInit is called in the driver layer, we have to set the block
46006 +         * size here for the target */
46007 +
46008 +    if (A_FAILED(ar6000_SetHTCBlockSize(ar))) {
46009 +        return;
46010 +    }
46011 +
46012 +    spin_lock_init(&ar->arLock);
46013 +
46014 +    /* Don't install the init function if BMI is requested */
46015 +    if(!bmienable)
46016 +    {
46017 +        dev->init = ar6000_init;
46018 +    } else {
46019 +        AR_DEBUG_PRINTF(" BMI enabled \n");
46020 +    }
46021 +
46022 +    dev->open = &ar6000_open;
46023 +    dev->stop = &ar6000_close;
46024 +    dev->hard_start_xmit = &ar6000_data_tx;
46025 +    dev->get_stats = &ar6000_get_stats;
46026 +
46027 +    /* dev->tx_timeout = ar6000_tx_timeout; */
46028 +    dev->do_ioctl = &ar6000_ioctl;
46029 +    dev->watchdog_timeo = AR6000_TX_TIMEOUT;
46030 +    ar6000_ioctl_iwsetup(&ath_iw_handler_def);
46031 +    dev->wireless_handlers = &ath_iw_handler_def;
46032 +    ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */
46033 +
46034 +    /*
46035 +     * We need the OS to provide us with more headroom in order to
46036 +     * perform dix to 802.3, WMI header encap, and the HTC header
46037 +     */
46038 +    dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) +
46039 +        sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN;
46040 +
46041 +    /* This runs the init function */
46042 +    SET_NETDEV_DEV(dev, HIFGetOSDevice(ar->arHifDevice));
46043 +    if (register_netdev(dev)) {
46044 +        AR_DEBUG_PRINTF("ar6000_avail: register_netdev failed\n");
46045 +        ar6000_destroy(dev, 0);
46046 +        return;
46047 +    }
46048 +
46049 +    HTCSetInstance(ar->arHtcTarget, ar);
46050 +
46051 +    /* We only register the device in the global list if we succeed. */
46052 +    /* If the device is in the global list, it will be destroyed     */
46053 +    /* when the module is unloaded.                                  */
46054 +    ar6000_devices[device_index] = dev;
46055 +
46056 +    AR_DEBUG_PRINTF("ar6000_avail: name=%s htcTarget=0x%x, dev=0x%x (%d), ar=0x%x\n",
46057 +                    dev->name, (A_UINT32)HTCHandle, (A_UINT32)dev, device_index,
46058 +                    (A_UINT32)ar);
46059 +}
46060 +
46061 +static void ar6000_target_failure(void *Instance, A_STATUS Status)
46062 +{
46063 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance;
46064 +    WMI_TARGET_ERROR_REPORT_EVENT errEvent;
46065 +    static A_BOOL sip = FALSE;
46066 +
46067 +    if (Status != A_OK) {
46068 +        if (timer_pending(&ar->arHBChallengeResp.timer)) {
46069 +            A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
46070 +        }
46071 +
46072 +        /* try dumping target assertion information (if any) */
46073 +        ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType);
46074 +
46075 +        /*
46076 +         * Fetch the logs from the target via the diagnostic
46077 +         * window.
46078 +         */
46079 +        ar6000_dbglog_get_debug_logs(ar);
46080 +
46081 +        /* Report the error only once */
46082 +        if (!sip) {
46083 +            sip = TRUE;
46084 +            errEvent.errorVal = WMI_TARGET_COM_ERR |
46085 +                                WMI_TARGET_FATAL_ERR;
46086 +#ifdef SEND_EVENT_TO_APP
46087 +            ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
46088 +                                     (A_UINT8 *)&errEvent,
46089 +                                     sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
46090 +#endif
46091 +        }
46092 +    }
46093 +}
46094 +
46095 +static void
46096 +ar6000_unavail_ev(void *Instance)
46097 +{
46098 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance;
46099 +        /* NULL out it's entry in the global list */
46100 +    ar6000_devices[ar->arDeviceIndex] = NULL;
46101 +    ar6000_destroy(ar->arNetDev, 1);
46102 +}
46103 +
46104 +/*
46105 + * We need to differentiate between the surprise and planned removal of the
46106 + * device because of the following consideration:
46107 + * - In case of surprise removal, the hcd already frees up the pending
46108 + *   for the device and hence there is no need to unregister the function
46109 + *   driver inorder to get these requests. For planned removal, the function
46110 + *   driver has to explictly unregister itself to have the hcd return all the
46111 + *   pending requests before the data structures for the devices are freed up.
46112 + *   Note that as per the current implementation, the function driver will
46113 + *   end up releasing all the devices since there is no API to selectively
46114 + *   release a particular device.
46115 + * - Certain commands issued to the target can be skipped for surprise
46116 + *   removal since they will anyway not go through.
46117 + */
46118 +static void
46119 +ar6000_destroy(struct net_device *dev, unsigned int unregister)
46120 +{
46121 +    AR_SOFTC_T *ar;
46122 +
46123 +    AR_DEBUG_PRINTF("+ar6000_destroy \n");
46124 +
46125 +    if((dev == NULL) || ((ar = netdev_priv(dev)) == NULL))
46126 +    {
46127 +        AR_DEBUG_PRINTF("%s(): Failed to get device structure.\n", __func__);
46128 +        return;
46129 +    }
46130 +
46131 +    /* Stop the transmit queues */
46132 +    netif_stop_queue(dev);
46133 +
46134 +    /* Disable the target and the interrupts associated with it */
46135 +    if (ar->arWmiReady == TRUE)
46136 +    {
46137 +        if (!bypasswmi)
46138 +        {
46139 +            if (ar->arConnected == TRUE || ar->arConnectPending == TRUE)
46140 +            {
46141 +                AR_DEBUG_PRINTF("%s(): Disconnect\n", __func__);
46142 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
46143 +                ar6000_init_profile_info(ar);
46144 +                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46145 +                wmi_disconnect_cmd(ar->arWmi);
46146 +            }
46147 +
46148 +            ar6000_dbglog_get_debug_logs(ar);
46149 +            ar->arWmiReady  = FALSE;
46150 +            ar->arConnected = FALSE;
46151 +            ar->arConnectPending = FALSE;
46152 +            wmi_shutdown(ar->arWmi);
46153 +            ar->arWmiEnabled = FALSE;
46154 +            ar->arWmi = NULL;
46155 +            ar->arWlanState = WLAN_ENABLED;
46156 +#ifdef USER_KEYS
46157 +            ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
46158 +            ar->user_key_ctrl      = 0;
46159 +#endif
46160 +        }
46161 +
46162 +         AR_DEBUG_PRINTF("%s(): WMI stopped\n", __func__);
46163 +    }
46164 +    else
46165 +    {
46166 +        AR_DEBUG_PRINTF("%s(): WMI not ready 0x%08x 0x%08x\n",
46167 +            __func__, (unsigned int) ar, (unsigned int) ar->arWmi);
46168 +
46169 +        /* Shut down WMI if we have started it */
46170 +        if(ar->arWmiEnabled == TRUE)
46171 +        {
46172 +            AR_DEBUG_PRINTF("%s(): Shut down WMI\n", __func__);
46173 +            wmi_shutdown(ar->arWmi);
46174 +            ar->arWmiEnabled = FALSE;
46175 +            ar->arWmi = NULL;
46176 +        }
46177 +    }
46178 +
46179 +    /* stop HTC */
46180 +    HTCStop(ar->arHtcTarget);
46181 +
46182 +    /* set the instance to NULL so we do not get called back on remove incase we
46183 +     * we're explicity destroyed by module unload */
46184 +    HTCSetInstance(ar->arHtcTarget, NULL);
46185 +
46186 +    if (resetok) {
46187 +        /* try to reset the device if we can
46188 +         * The driver may have been configure NOT to reset the target during
46189 +         * a debug session */
46190 +        AR_DEBUG_PRINTF(" Attempting to reset target on instance destroy.... \n");
46191 +        ar6000_reset_device(ar->arHifDevice, ar->arTargetType);
46192 +    } else {
46193 +        AR_DEBUG_PRINTF(" Host does not want target reset. \n");
46194 +    }
46195 +
46196 +       /* Done with cookies */
46197 +    ar6000_cookie_cleanup(ar);
46198 +
46199 +    /* Cleanup BMI */
46200 +    BMIInit();
46201 +
46202 +    /* Clear the tx counters */
46203 +    memset(tx_attempt, 0, sizeof(tx_attempt));
46204 +    memset(tx_post, 0, sizeof(tx_post));
46205 +    memset(tx_complete, 0, sizeof(tx_complete));
46206 +
46207 +
46208 +    /* Free up the device data structure */
46209 +    if (unregister)
46210 +           unregister_netdev(dev);
46211 +
46212 +    free_raw_buffers(ar);
46213 +
46214 +#ifndef free_netdev
46215 +    kfree(dev);
46216 +#else
46217 +    free_netdev(dev);
46218 +#endif
46219 +
46220 +    AR_DEBUG_PRINTF("-ar6000_destroy \n");
46221 +}
46222 +
46223 +static void ar6000_detect_error(unsigned long ptr)
46224 +{
46225 +    struct net_device *dev = (struct net_device *)ptr;
46226 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
46227 +    WMI_TARGET_ERROR_REPORT_EVENT errEvent;
46228 +
46229 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
46230 +
46231 +    if (ar->arHBChallengeResp.outstanding) {
46232 +        ar->arHBChallengeResp.missCnt++;
46233 +    } else {
46234 +        ar->arHBChallengeResp.missCnt = 0;
46235 +    }
46236 +
46237 +    if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) {
46238 +        /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */
46239 +        ar->arHBChallengeResp.missCnt = 0;
46240 +        ar->arHBChallengeResp.seqNum = 0;
46241 +        errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR;
46242 +        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46243 +#ifdef SEND_EVENT_TO_APP
46244 +        ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
46245 +                                 (A_UINT8 *)&errEvent,
46246 +                                 sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
46247 +#endif
46248 +        return;
46249 +    }
46250 +
46251 +    /* Generate the sequence number for the next challenge */
46252 +    ar->arHBChallengeResp.seqNum++;
46253 +    ar->arHBChallengeResp.outstanding = TRUE;
46254 +
46255 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46256 +
46257 +    /* Send the challenge on the control channel */
46258 +    if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) {
46259 +        AR_DEBUG_PRINTF("Unable to send heart beat challenge\n");
46260 +    }
46261 +
46262 +
46263 +    /* Reschedule the timer for the next challenge */
46264 +    A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
46265 +}
46266 +
46267 +void ar6000_init_profile_info(AR_SOFTC_T *ar)
46268 +{
46269 +    ar->arSsidLen            = 0;
46270 +    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
46271 +    ar->arNetworkType        = INFRA_NETWORK;
46272 +    ar->arDot11AuthMode      = OPEN_AUTH;
46273 +    ar->arAuthMode           = NONE_AUTH;
46274 +    ar->arPairwiseCrypto     = NONE_CRYPT;
46275 +    ar->arPairwiseCryptoLen  = 0;
46276 +    ar->arGroupCrypto        = NONE_CRYPT;
46277 +    ar->arGroupCryptoLen     = 0;
46278 +    A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
46279 +    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
46280 +    A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
46281 +    ar->arBssChannel = 0;
46282 +}
46283 +
46284 +static void
46285 +ar6000_init_control_info(AR_SOFTC_T *ar)
46286 +{
46287 +    ar->arWmiEnabled         = FALSE;
46288 +    ar6000_init_profile_info(ar);
46289 +    ar->arDefTxKeyIndex      = 0;
46290 +    A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
46291 +    ar->arChannelHint        = 0;
46292 +    ar->arListenInterval     = MAX_LISTEN_INTERVAL;
46293 +    ar->arVersion.host_ver   = AR6K_SW_VERSION;
46294 +    ar->arRssi               = 0;
46295 +    ar->arTxPwr              = 0;
46296 +    ar->arTxPwrSet           = FALSE;
46297 +    ar->arSkipScan           = 0;
46298 +    ar->arBeaconInterval     = 0;
46299 +    ar->arBitRate            = 0;
46300 +    ar->arMaxRetries         = 0;
46301 +    ar->arWmmEnabled         = TRUE;
46302 +}
46303 +
46304 +static int
46305 +ar6000_open(struct net_device *dev)
46306 +{
46307 +    /* Wake up the queues */
46308 +    netif_wake_queue(dev);
46309 +
46310 +    return 0;
46311 +}
46312 +
46313 +static int
46314 +ar6000_close(struct net_device *dev)
46315 +{
46316 +    netif_stop_queue(dev);
46317 +
46318 +    return 0;
46319 +}
46320 +
46321 +/* connect to a service */
46322 +static A_STATUS ar6000_connectservice(AR_SOFTC_T               *ar,
46323 +                                      HTC_SERVICE_CONNECT_REQ  *pConnect,
46324 +                                      WMI_PRI_STREAM_ID        WmiStreamID,
46325 +                                      char                     *pDesc)
46326 +{
46327 +    A_STATUS                 status;
46328 +    HTC_SERVICE_CONNECT_RESP response;
46329 +
46330 +    do {
46331 +
46332 +        A_MEMZERO(&response,sizeof(response));
46333 +
46334 +        status = HTCConnectService(ar->arHtcTarget,
46335 +                                   pConnect,
46336 +                                   &response);
46337 +
46338 +        if (A_FAILED(status)) {
46339 +            AR_DEBUG_PRINTF(" Failed to connect to %s service status:%d \n", pDesc, status);
46340 +            break;
46341 +        }
46342 +
46343 +        if (WmiStreamID == WMI_NOT_MAPPED) {
46344 +                /* done */
46345 +            break;
46346 +        }
46347 +
46348 +            /* set endpoint mapping for the WMI stream in the driver layer */
46349 +        arSetWMIStream2EndpointIDMap(ar,WmiStreamID,response.Endpoint);
46350 +
46351 +    } while (FALSE);
46352 +
46353 +    return status;
46354 +}
46355 +
46356 +static void ar6000_TxDataCleanup(AR_SOFTC_T *ar)
46357 +{
46358 +        /* flush all the data (non-control) streams
46359 +         * we only flush packets that are tagged as data, we leave any control packets that
46360 +         * were in the TX queues alone */
46361 +    HTCFlushEndpoint(ar->arHtcTarget,
46362 +                     arWMIStream2EndpointID(ar,WMI_BEST_EFFORT_PRI),
46363 +                     AR6K_DATA_PKT_TAG);
46364 +    HTCFlushEndpoint(ar->arHtcTarget,
46365 +                     arWMIStream2EndpointID(ar,WMI_LOW_PRI),
46366 +                     AR6K_DATA_PKT_TAG);
46367 +    HTCFlushEndpoint(ar->arHtcTarget,
46368 +                     arWMIStream2EndpointID(ar,WMI_HIGH_PRI),
46369 +                     AR6K_DATA_PKT_TAG);
46370 +    HTCFlushEndpoint(ar->arHtcTarget,
46371 +                     arWMIStream2EndpointID(ar,WMI_HIGHEST_PRI),
46372 +                     AR6K_DATA_PKT_TAG);
46373 +}
46374 +
46375 +/* This function does one time initialization for the lifetime of the device */
46376 +int ar6000_init(struct net_device *dev)
46377 +{
46378 +    AR_SOFTC_T *ar;
46379 +    A_STATUS    status;
46380 +    A_INT32     timeleft;
46381 +
46382 +    if((ar = netdev_priv(dev)) == NULL)
46383 +    {
46384 +        return(-EIO);
46385 +    }
46386 +
46387 +    /* Do we need to finish the BMI phase */
46388 +    if(BMIDone(ar->arHifDevice) != A_OK)
46389 +    {
46390 +        return -EIO;
46391 +    }
46392 +
46393 +    if (!bypasswmi)
46394 +    {
46395 +#if 0 /* TBDXXX */
46396 +        if (ar->arVersion.host_ver != ar->arVersion.target_ver) {
46397 +            A_PRINTF("WARNING: Host version 0x%x does not match Target "
46398 +                    " version 0x%x!\n",
46399 +                    ar->arVersion.host_ver, ar->arVersion.target_ver);
46400 +        }
46401 +#endif
46402 +
46403 +        /* Indicate that WMI is enabled (although not ready yet) */
46404 +        ar->arWmiEnabled = TRUE;
46405 +        if ((ar->arWmi = wmi_init((void *) ar)) == NULL)
46406 +        {
46407 +            AR_DEBUG_PRINTF("%s() Failed to initialize WMI.\n", __func__);
46408 +            return(-EIO);
46409 +        }
46410 +
46411 +        AR_DEBUG_PRINTF("%s() Got WMI @ 0x%08x.\n", __func__,
46412 +            (unsigned int) ar->arWmi);
46413 +    }
46414 +
46415 +    do {
46416 +        HTC_SERVICE_CONNECT_REQ connect;
46417 +
46418 +            /* the reason we have to wait for the target here is that the driver layer
46419 +             * has to init BMI in order to set the host block size,
46420 +             */
46421 +        status = HTCWaitTarget(ar->arHtcTarget);
46422 +
46423 +        if (A_FAILED(status)) {
46424 +            break;
46425 +        }
46426 +
46427 +        A_MEMZERO(&connect,sizeof(connect));
46428 +            /* meta data is unused for now */
46429 +        connect.pMetaData = NULL;
46430 +        connect.MetaDataLength = 0;
46431 +            /* these fields are the same for all service endpoints */
46432 +        connect.EpCallbacks.pContext = ar;
46433 +        connect.EpCallbacks.EpTxComplete = ar6000_tx_complete;
46434 +        connect.EpCallbacks.EpRecv = ar6000_rx;
46435 +        connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill;
46436 +        connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full;
46437 +            /* set the max queue depth so that our ar6000_tx_queue_full handler gets called.
46438 +             * Linux has the peculiarity of not providing flow control between the
46439 +             * NIC and the network stack. There is no API to indicate that a TX packet
46440 +             * was sent which could provide some back pressure to the network stack.
46441 +             * Under linux you would have to wait till the network stack consumed all sk_buffs
46442 +             * before any back-flow kicked in. Which isn't very friendly.
46443 +             * So we have to manage this ourselves */
46444 +        connect.MaxSendQueueDepth = 32;
46445 +
46446 +            /* connect to control service */
46447 +        connect.ServiceID = WMI_CONTROL_SVC;
46448 +        status = ar6000_connectservice(ar,
46449 +                                       &connect,
46450 +                                       WMI_CONTROL_PRI,
46451 +                                       "WMI CONTROL");
46452 +        if (A_FAILED(status)) {
46453 +            break;
46454 +        }
46455 +
46456 +            /* for the remaining data services set the connection flag to reduce dribbling,
46457 +             * if configured to do so */
46458 +        if (reduce_credit_dribble) {
46459 +            connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE;
46460 +            /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value
46461 +             * of 0-3 */
46462 +            connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
46463 +            connect.ConnectionFlags |=
46464 +                        ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
46465 +        }
46466 +            /* connect to best-effort service */
46467 +        connect.ServiceID = WMI_DATA_BE_SVC;
46468 +
46469 +        status = ar6000_connectservice(ar,
46470 +                                       &connect,
46471 +                                       WMI_BEST_EFFORT_PRI,
46472 +                                       "WMI DATA BE");
46473 +        if (A_FAILED(status)) {
46474 +            break;
46475 +        }
46476 +
46477 +            /* connect to back-ground
46478 +             * map this to WMI LOW_PRI */
46479 +        connect.ServiceID = WMI_DATA_BK_SVC;
46480 +        status = ar6000_connectservice(ar,
46481 +                                       &connect,
46482 +                                       WMI_LOW_PRI,
46483 +                                       "WMI DATA BK");
46484 +        if (A_FAILED(status)) {
46485 +            break;
46486 +        }
46487 +
46488 +            /* connect to Video service, map this to
46489 +             * to HI PRI */
46490 +        connect.ServiceID = WMI_DATA_VI_SVC;
46491 +        status = ar6000_connectservice(ar,
46492 +                                       &connect,
46493 +                                       WMI_HIGH_PRI,
46494 +                                       "WMI DATA VI");
46495 +        if (A_FAILED(status)) {
46496 +            break;
46497 +        }
46498 +
46499 +            /* connect to VO service, this is currently not
46500 +             * mapped to a WMI priority stream due to historical reasons.
46501 +             * WMI originally defined 3 priorities over 3 mailboxes
46502 +             * We can change this when WMI is reworked so that priorities are not
46503 +             * dependent on mailboxes */
46504 +        connect.ServiceID = WMI_DATA_VO_SVC;
46505 +        status = ar6000_connectservice(ar,
46506 +                                       &connect,
46507 +                                       WMI_HIGHEST_PRI,
46508 +                                       "WMI DATA VO");
46509 +        if (A_FAILED(status)) {
46510 +            break;
46511 +        }
46512 +
46513 +        A_ASSERT(arWMIStream2EndpointID(ar,WMI_CONTROL_PRI) != 0);
46514 +        A_ASSERT(arWMIStream2EndpointID(ar,WMI_BEST_EFFORT_PRI) != 0);
46515 +        A_ASSERT(arWMIStream2EndpointID(ar,WMI_LOW_PRI) != 0);
46516 +        A_ASSERT(arWMIStream2EndpointID(ar,WMI_HIGH_PRI) != 0);
46517 +        A_ASSERT(arWMIStream2EndpointID(ar,WMI_HIGHEST_PRI) != 0);
46518 +    } while (FALSE);
46519 +
46520 +    if (A_FAILED(status)) {
46521 +        return (-EIO);
46522 +    }
46523 +
46524 +    /*
46525 +     * give our connected endpoints some buffers
46526 +     */
46527 +    ar6000_rx_refill(ar, arWMIStream2EndpointID(ar,WMI_CONTROL_PRI));
46528 +
46529 +    ar6000_rx_refill(ar, arWMIStream2EndpointID(ar,WMI_BEST_EFFORT_PRI));
46530 +
46531 +    /*
46532 +     * We will post the receive buffers only for SPE testing and so we are
46533 +     * making it conditional on the 'bypasswmi' flag.
46534 +     */
46535 +    if (bypasswmi) {
46536 +        ar6000_rx_refill(ar,arWMIStream2EndpointID(ar,WMI_LOW_PRI));
46537 +        ar6000_rx_refill(ar,arWMIStream2EndpointID(ar,WMI_HIGH_PRI));
46538 +    }
46539 +
46540 +        /* setup credit distribution */
46541 +    ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo);
46542 +
46543 +    /* Since cookies are used for HTC transports, they should be */
46544 +    /* initialized prior to enabling HTC.                        */
46545 +    ar6000_cookie_init(ar);
46546 +
46547 +    /* start HTC */
46548 +    status = HTCStart(ar->arHtcTarget);
46549 +
46550 +    if (status != A_OK) {
46551 +        if (ar->arWmiEnabled == TRUE) {
46552 +            wmi_shutdown(ar->arWmi);
46553 +            ar->arWmiEnabled = FALSE;
46554 +            ar->arWmi = NULL;
46555 +        }
46556 +        ar6000_cookie_cleanup(ar);
46557 +        return -EIO;
46558 +    }
46559 +
46560 +    if (!bypasswmi) {
46561 +        /* Wait for Wmi event to be ready */
46562 +        timeleft = wait_event_interruptible_timeout(arEvent,
46563 +            (ar->arWmiReady == TRUE), wmitimeout * HZ);
46564 +
46565 +        if(!timeleft || signal_pending(current))
46566 +        {
46567 +            AR_DEBUG_PRINTF("WMI is not ready or wait was interrupted\n");
46568 +#if defined(DWSIM) /* TBDXXX */
46569 +            AR_DEBUG_PRINTF(".....but proceed anyway.\n");
46570 +#else
46571 +            return -EIO;
46572 +#endif
46573 +        }
46574 +
46575 +        AR_DEBUG_PRINTF("%s() WMI is ready\n", __func__);
46576 +
46577 +        /* Communicate the wmi protocol verision to the target */
46578 +        if ((ar6000_set_host_app_area(ar)) != A_OK) {
46579 +            AR_DEBUG_PRINTF("Unable to set the host app area\n");
46580 +        }
46581 +    }
46582 +
46583 +    ar->arNumDataEndPts = 1;
46584 +
46585 +    return(0);
46586 +}
46587 +
46588 +
46589 +void
46590 +ar6000_bitrate_rx(void *devt, A_INT32 rateKbps)
46591 +{
46592 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
46593 +
46594 +    ar->arBitRate = rateKbps;
46595 +    wake_up(&arEvent);
46596 +}
46597 +
46598 +void
46599 +ar6000_ratemask_rx(void *devt, A_UINT16 ratemask)
46600 +{
46601 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
46602 +
46603 +    ar->arRateMask = ratemask;
46604 +    wake_up(&arEvent);
46605 +}
46606 +
46607 +void
46608 +ar6000_txPwr_rx(void *devt, A_UINT8 txPwr)
46609 +{
46610 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
46611 +
46612 +    ar->arTxPwr = txPwr;
46613 +    wake_up(&arEvent);
46614 +}
46615 +
46616 +
46617 +void
46618 +ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList)
46619 +{
46620 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
46621 +
46622 +    A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16));
46623 +    ar->arNumChannels = numChan;
46624 +
46625 +    wake_up(&arEvent);
46626 +}
46627 +
46628 +A_UINT8
46629 +ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo)
46630 +{
46631 +    AR_SOFTC_T      *ar = (AR_SOFTC_T *)dev->priv;
46632 +    A_UINT8         *datap;
46633 +    ATH_MAC_HDR     *macHdr;
46634 +    A_UINT32         i, eptMap;
46635 +
46636 +    (*mapNo) = 0;
46637 +    datap = A_NETBUF_DATA(skb);
46638 +    macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR));
46639 +    if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) {
46640 +        return ENDPOINT_2;
46641 +    }
46642 +
46643 +    eptMap = -1;
46644 +    for (i = 0; i < ar->arNodeNum; i ++) {
46645 +        if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) {
46646 +            (*mapNo) = i + 1;
46647 +            ar->arNodeMap[i].txPending ++;
46648 +            return ar->arNodeMap[i].epId;
46649 +        }
46650 +
46651 +        if ((eptMap == -1) && !ar->arNodeMap[i].txPending) {
46652 +            eptMap = i;
46653 +        }
46654 +    }
46655 +
46656 +    if (eptMap == -1) {
46657 +        eptMap = ar->arNodeNum;
46658 +        ar->arNodeNum ++;
46659 +        A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM);
46660 +    }
46661 +
46662 +    A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN);
46663 +
46664 +    for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) {
46665 +        if (!ar->arTxPending[i]) {
46666 +            ar->arNodeMap[eptMap].epId = i;
46667 +            break;
46668 +        }
46669 +        // No free endpoint is available, start redistribution on the inuse endpoints.
46670 +        if (i == ENDPOINT_5) {
46671 +            ar->arNodeMap[eptMap].epId = ar->arNexEpId;
46672 +            ar->arNexEpId ++;
46673 +            if (ar->arNexEpId > ENDPOINT_5) {
46674 +                ar->arNexEpId = ENDPOINT_2;
46675 +            }
46676 +        }
46677 +    }
46678 +
46679 +    (*mapNo) = eptMap + 1;
46680 +    ar->arNodeMap[eptMap].txPending ++;
46681 +
46682 +    return ar->arNodeMap[eptMap].epId;
46683 +}
46684 +
46685 +#ifdef DEBUG
46686 +static void ar6000_dump_skb(struct sk_buff *skb)
46687 +{
46688 +   u_char *ch;
46689 +   for (ch = A_NETBUF_DATA(skb);
46690 +        (A_UINT32)ch < ((A_UINT32)A_NETBUF_DATA(skb) +
46691 +        A_NETBUF_LEN(skb)); ch++)
46692 +    {
46693 +         AR_DEBUG_PRINTF("%2.2x ", *ch);
46694 +    }
46695 +    AR_DEBUG_PRINTF("\n");
46696 +}
46697 +#endif
46698 +
46699 +static int
46700 +ar6000_data_tx(struct sk_buff *skb, struct net_device *dev)
46701 +{
46702 +    AR_SOFTC_T        *ar = (AR_SOFTC_T *)dev->priv;
46703 +    WMI_PRI_STREAM_ID streamID = WMI_NOT_MAPPED;
46704 +    A_UINT32          mapNo = 0;
46705 +    int               len;
46706 +    struct ar_cookie *cookie;
46707 +    A_BOOL            checkAdHocPsMapping = FALSE;
46708 +
46709 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13)
46710 +    skb->list = NULL;
46711 +#endif
46712 +
46713 +    AR_DEBUG2_PRINTF("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n",
46714 +                     (A_UINT32)skb, (A_UINT32)A_NETBUF_DATA(skb),
46715 +                     A_NETBUF_LEN(skb));
46716 +#ifdef CONFIG_HOST_TCMD_SUPPORT
46717 +     /* TCMD doesnt support any data, free the buf and return */
46718 +    if(ar->arTargetMode == AR6000_TCMD_MODE) {
46719 +        A_NETBUF_FREE(skb);
46720 +        return 0;
46721 +    }
46722 +#endif
46723 +    do {
46724 +
46725 +        if (ar->arWmiReady == FALSE && bypasswmi == 0) {
46726 +            break;
46727 +        }
46728 +
46729 +#ifdef BLOCK_TX_PATH_FLAG
46730 +        if (blocktx) {
46731 +            break;
46732 +        }
46733 +#endif /* BLOCK_TX_PATH_FLAG */
46734 +
46735 +        if (ar->arWmiEnabled) {
46736 +            if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len) {
46737 +                struct sk_buff  *newbuf;
46738 +                /*
46739 +                 * We really should have gotten enough headroom but sometimes
46740 +                 * we still get packets with not enough headroom.  Copy the packet.
46741 +                 */
46742 +                len = A_NETBUF_LEN(skb);
46743 +                newbuf = A_NETBUF_ALLOC(len);
46744 +                if (newbuf == NULL) {
46745 +                    break;
46746 +                }
46747 +                A_NETBUF_PUT(newbuf, len);
46748 +                A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len);
46749 +                A_NETBUF_FREE(skb);
46750 +                skb = newbuf;
46751 +                /* fall through and assemble header */
46752 +            }
46753 +
46754 +            if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) {
46755 +                AR_DEBUG_PRINTF("ar6000_data_tx - wmi_dix_2_dot3 failed\n");
46756 +                break;
46757 +            }
46758 +
46759 +            if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE) != A_OK) {
46760 +                AR_DEBUG_PRINTF("ar6000_data_tx - wmi_data_hdr_add failed\n");
46761 +                break;
46762 +            }
46763 +
46764 +            if ((ar->arNetworkType == ADHOC_NETWORK) &&
46765 +                ar->arIbssPsEnable && ar->arConnected) {
46766 +                    /* flag to check adhoc mapping once we take the lock below: */
46767 +                checkAdHocPsMapping = TRUE;
46768 +
46769 +            } else {
46770 +                    /* get the stream mapping */
46771 +                if (ar->arWmmEnabled) {
46772 +                    streamID = wmi_get_stream_id(ar->arWmi,
46773 +                                    wmi_implicit_create_pstream(ar->arWmi, skb, UPLINK_TRAFFIC, UNDEFINED_PRI));
46774 +                } else {
46775 +                    streamID = WMI_BEST_EFFORT_PRI;
46776 +                }
46777 +            }
46778 +
46779 +        } else {
46780 +            struct iphdr    *ipHdr;
46781 +            /*
46782 +             * the endpoint is directly based on the TOS field in the IP
46783 +             * header **** only for testing ******
46784 +             */
46785 +            ipHdr = A_NETBUF_DATA(skb) + sizeof(ATH_MAC_HDR);
46786 +                /* here we map the TOS field to an endpoint number, this is for
46787 +                 * the endpointping test application */
46788 +            streamID = IP_TOS_TO_WMI_PRI(ipHdr->tos);
46789 +        }
46790 +
46791 +    } while (FALSE);
46792 +
46793 +        /* did we succeed ? */
46794 +    if ((streamID == WMI_NOT_MAPPED) && !checkAdHocPsMapping) {
46795 +            /* cleanup and exit */
46796 +        A_NETBUF_FREE(skb);
46797 +        AR6000_STAT_INC(ar, tx_dropped);
46798 +        AR6000_STAT_INC(ar, tx_aborted_errors);
46799 +        return 0;
46800 +    }
46801 +
46802 +    cookie = NULL;
46803 +
46804 +        /* take the lock to protect driver data */
46805 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
46806 +
46807 +    do {
46808 +
46809 +        if (checkAdHocPsMapping) {
46810 +            streamID = ar6000_ibss_map_epid(skb, dev, &mapNo);
46811 +        }
46812 +
46813 +        A_ASSERT(streamID != WMI_NOT_MAPPED);
46814 +
46815 +            /* validate that the endpoint is connected */
46816 +        if (arWMIStream2EndpointID(ar,streamID) == 0) {
46817 +            AR_DEBUG_PRINTF("Stream %d is NOT mapped!\n",streamID);
46818 +            break;
46819 +        }
46820 +            /* allocate resource for this packet */
46821 +        cookie = ar6000_alloc_cookie(ar);
46822 +
46823 +        if (cookie != NULL) {
46824 +                /* update counts while the lock is held */
46825 +            ar->arTxPending[streamID]++;
46826 +            ar->arTotalTxDataPending++;
46827 +        }
46828 +
46829 +    } while (FALSE);
46830 +
46831 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46832 +
46833 +    if (cookie != NULL) {
46834 +        cookie->arc_bp[0] = (A_UINT32)skb;
46835 +        cookie->arc_bp[1] = mapNo;
46836 +        SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
46837 +                               cookie,
46838 +                               A_NETBUF_DATA(skb),
46839 +                               A_NETBUF_LEN(skb),
46840 +                               arWMIStream2EndpointID(ar,streamID),
46841 +                               AR6K_DATA_PKT_TAG);
46842 +
46843 +#ifdef DEBUG
46844 +        if (debugdriver >= 3) {
46845 +            ar6000_dump_skb(skb);
46846 +        }
46847 +#endif
46848 +            /* HTC interface is asynchronous, if this fails, cleanup will happen in
46849 +             * the ar6000_tx_complete callback */
46850 +        HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
46851 +    } else {
46852 +            /* no packet to send, cleanup */
46853 +        A_NETBUF_FREE(skb);
46854 +        AR6000_STAT_INC(ar, tx_dropped);
46855 +        AR6000_STAT_INC(ar, tx_aborted_errors);
46856 +    }
46857 +
46858 +    return 0;
46859 +}
46860 +
46861 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
46862 +static void
46863 +tvsub(register struct timeval *out, register struct timeval *in)
46864 +{
46865 +    if((out->tv_usec -= in->tv_usec) < 0) {
46866 +        out->tv_sec--;
46867 +        out->tv_usec += 1000000;
46868 +    }
46869 +    out->tv_sec -= in->tv_sec;
46870 +}
46871 +
46872 +void
46873 +applyAPTCHeuristics(AR_SOFTC_T *ar)
46874 +{
46875 +    A_UINT32 duration;
46876 +    A_UINT32 numbytes;
46877 +    A_UINT32 throughput;
46878 +    struct timeval ts;
46879 +    A_STATUS status;
46880 +
46881 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
46882 +
46883 +    if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) {
46884 +        do_gettimeofday(&ts);
46885 +        tvsub(&ts, &aptcTR.samplingTS);
46886 +        duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */
46887 +        numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
46888 +
46889 +        if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) {
46890 +            /* Initialize the time stamp and byte count */
46891 +            aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
46892 +            do_gettimeofday(&aptcTR.samplingTS);
46893 +
46894 +            /* Calculate and decide based on throughput thresholds */
46895 +            throughput = ((numbytes * 8) / duration);
46896 +            if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) {
46897 +                /* Disable Sleep and schedule a timer */
46898 +                A_ASSERT(ar->arWmiReady == TRUE);
46899 +                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46900 +                status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER);
46901 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
46902 +                A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
46903 +                aptcTR.timerScheduled = TRUE;
46904 +            }
46905 +        }
46906 +    }
46907 +
46908 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46909 +}
46910 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
46911 +
46912 +static void ar6000_tx_queue_full(void *Context, HTC_ENDPOINT_ID Endpoint)
46913 +{
46914 +    AR_SOFTC_T     *ar = (AR_SOFTC_T *)Context;
46915 +
46916 +
46917 +    if (Endpoint == arWMIStream2EndpointID(ar,WMI_CONTROL_PRI)) {
46918 +        if (!bypasswmi) {
46919 +                /* under normal WMI if this is getting full, then something is running rampant
46920 +                 * the host should not be exhausting the WMI queue with too many commands
46921 +                 * the only exception to this is during testing using endpointping */
46922 +
46923 +            AR6000_SPIN_LOCK(&ar->arLock, 0);
46924 +                /* set flag to handle subsequent messages */
46925 +            ar->arWMIControlEpFull = TRUE;
46926 +            AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46927 +            AR_DEBUG_PRINTF("WMI Control Endpoint is FULL!!! \n");
46928 +        }
46929 +    } else {
46930 +
46931 +        AR6000_SPIN_LOCK(&ar->arLock, 0);
46932 +        ar->arNetQueueStopped = TRUE;
46933 +        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46934 +        /* one of the data endpoints queues is getting full..need to stop network stack
46935 +         * the queue will resume in ar6000_tx_complete() */
46936 +        netif_stop_queue(ar->arNetDev);
46937 +    }
46938 +
46939 +
46940 +}
46941 +
46942 +
46943 +static void
46944 +ar6000_tx_complete(void *Context, HTC_PACKET *pPacket)
46945 +{
46946 +    AR_SOFTC_T     *ar = (AR_SOFTC_T *)Context;
46947 +    void           *cookie = (void *)pPacket->pPktContext;
46948 +    struct sk_buff *skb = NULL;
46949 +    A_UINT32        mapNo = 0;
46950 +    A_STATUS        status;
46951 +    struct ar_cookie * ar_cookie;
46952 +    WMI_PRI_STREAM_ID streamID;
46953 +    A_BOOL          wakeEvent = FALSE;
46954 +
46955 +    status = pPacket->Status;
46956 +    ar_cookie = (struct ar_cookie *)cookie;
46957 +    skb = (struct sk_buff *)ar_cookie->arc_bp[0];
46958 +    streamID = arEndpoint2WMIStreamID(ar,pPacket->Endpoint);
46959 +    mapNo = ar_cookie->arc_bp[1];
46960 +
46961 +    A_ASSERT(skb);
46962 +    A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(skb));
46963 +
46964 +    if (A_SUCCESS(status)) {
46965 +        A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(skb));
46966 +    }
46967 +
46968 +    AR_DEBUG2_PRINTF("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x sid=%d ",
46969 +                     (A_UINT32)skb, (A_UINT32)pPacket->pBuffer,
46970 +                     pPacket->ActualLength,
46971 +                     streamID);
46972 +
46973 +        /* lock the driver as we update internal state */
46974 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
46975 +
46976 +    ar->arTxPending[streamID]--;
46977 +
46978 +    if ((streamID != WMI_CONTROL_PRI) || bypasswmi) {
46979 +        ar->arTotalTxDataPending--;
46980 +    }
46981 +
46982 +    if (streamID == WMI_CONTROL_PRI)
46983 +    {
46984 +        if (ar->arWMIControlEpFull) {
46985 +                /* since this packet completed, the WMI EP is no longer full */
46986 +            ar->arWMIControlEpFull = FALSE;
46987 +        }
46988 +
46989 +        if (ar->arTxPending[streamID] == 0) {
46990 +            wakeEvent = TRUE;
46991 +        }
46992 +    }
46993 +
46994 +    if (A_FAILED(status)) {
46995 +        AR_DEBUG_PRINTF("%s() -TX ERROR, status: 0x%x\n", __func__,
46996 +                        status);
46997 +        AR6000_STAT_INC(ar, tx_errors);
46998 +    } else {
46999 +        AR_DEBUG2_PRINTF("OK\n");
47000 +        AR6000_STAT_INC(ar, tx_packets);
47001 +        ar->arNetStats.tx_bytes += A_NETBUF_LEN(skb);
47002 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
47003 +        aptcTR.bytesTransmitted += a_netbuf_to_len(skb);
47004 +        applyAPTCHeuristics(ar);
47005 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
47006 +    }
47007 +
47008 +    // TODO this needs to be looked at
47009 +    if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable
47010 +        && (streamID != WMI_CONTROL_PRI) && mapNo)
47011 +    {
47012 +        mapNo --;
47013 +        ar->arNodeMap[mapNo].txPending --;
47014 +
47015 +        if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) {
47016 +            A_UINT32 i;
47017 +            for (i = ar->arNodeNum; i > 0; i --) {
47018 +                if (!ar->arNodeMap[i - 1].txPending) {
47019 +                    A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping));
47020 +                    ar->arNodeNum --;
47021 +                } else {
47022 +                    break;
47023 +                }
47024 +            }
47025 +        }
47026 +    }
47027 +
47028 +    /* Freeing a cookie should not be contingent on either of */
47029 +    /* these flags, just if we have a cookie or not.           */
47030 +    /* Can we even get here without a cookie? Fix later.       */
47031 +    if (ar->arWmiReady == TRUE || (bypasswmi))
47032 +    {
47033 +        ar6000_free_cookie(ar, cookie);
47034 +    }
47035 +
47036 +    if (ar->arNetQueueStopped) {
47037 +        ar->arNetQueueStopped = FALSE;
47038 +    }
47039 +
47040 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47041 +
47042 +    /* lock is released, we can freely call other kernel APIs */
47043 +
47044 +        /* this indirectly frees the HTC_PACKET */
47045 +    A_NETBUF_FREE(skb);
47046 +
47047 +    if ((ar->arConnected == TRUE) || (bypasswmi)) {
47048 +        if (status != A_ECANCELED) {
47049 +                /* don't wake the queue if we are flushing, other wise it will just
47050 +                 * keep queueing packets, which will keep failing */
47051 +            netif_wake_queue(ar->arNetDev);
47052 +        }
47053 +    }
47054 +
47055 +    if (wakeEvent) {
47056 +        wake_up(&arEvent);
47057 +    }
47058 +
47059 +}
47060 +
47061 +/*
47062 + * Receive event handler.  This is called by HTC when a packet is received
47063 + */
47064 +int pktcount;
47065 +static void
47066 +ar6000_rx(void *Context, HTC_PACKET *pPacket)
47067 +{
47068 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
47069 +    struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext;
47070 +    int minHdrLen;
47071 +    A_STATUS        status = pPacket->Status;
47072 +    WMI_PRI_STREAM_ID streamID = arEndpoint2WMIStreamID(ar,pPacket->Endpoint);
47073 +    HTC_ENDPOINT_ID   ept = pPacket->Endpoint;
47074 +
47075 +    A_ASSERT((status != A_OK) || (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN)));
47076 +
47077 +    AR_DEBUG2_PRINTF("ar6000_rx ar=0x%x sid=%d, skb=0x%x, data=0x%x, len=0x%x ",
47078 +                    (A_UINT32)ar, streamID, (A_UINT32)skb, (A_UINT32)pPacket->pBuffer,
47079 +                    pPacket->ActualLength);
47080 +    if (status != A_OK) {
47081 +        AR_DEBUG2_PRINTF("ERR\n");
47082 +    } else {
47083 +        AR_DEBUG2_PRINTF("OK\n");
47084 +    }
47085 +
47086 +        /* take lock to protect buffer counts
47087 +         * and adaptive power throughput state */
47088 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
47089 +
47090 +    ar->arRxBuffers[streamID]--;
47091 +
47092 +    if (A_SUCCESS(status)) {
47093 +        AR6000_STAT_INC(ar, rx_packets);
47094 +        ar->arNetStats.rx_bytes += pPacket->ActualLength;
47095 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
47096 +        aptcTR.bytesReceived += a_netbuf_to_len(skb);
47097 +        applyAPTCHeuristics(ar);
47098 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
47099 +
47100 +        A_NETBUF_PUT(skb, pPacket->ActualLength +  HTC_HEADER_LEN);
47101 +        A_NETBUF_PULL(skb, HTC_HEADER_LEN);
47102 +
47103 +#ifdef DEBUG
47104 +        if (debugdriver >= 2) {
47105 +            ar6000_dump_skb(skb);
47106 +        }
47107 +#endif /* DEBUG */
47108 +    }
47109 +
47110 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47111 +
47112 +    if (status != A_OK) {
47113 +        AR6000_STAT_INC(ar, rx_errors);
47114 +        A_NETBUF_FREE(skb);
47115 +    } else if (ar->arWmiEnabled == TRUE) {
47116 +        if (streamID == WMI_CONTROL_PRI) {
47117 +           /*
47118 +            * this is a wmi control msg
47119 +            */
47120 +            wmi_control_rx(ar->arWmi, skb);
47121 +        } else {
47122 +            WMI_DATA_HDR *dhdr = (WMI_DATA_HDR *)A_NETBUF_DATA(skb);
47123 +            if (WMI_DATA_HDR_IS_MSG_TYPE(dhdr, CNTL_MSGTYPE)) {
47124 +                /*
47125 +                 * this is a wmi control msg
47126 +                 */
47127 +                /* strip off WMI hdr */
47128 +                wmi_data_hdr_remove(ar->arWmi, skb);
47129 +                wmi_control_rx(ar->arWmi, skb);
47130 +            } else {
47131 +                /*
47132 +                 * this is a wmi data packet
47133 +                 */
47134 +                minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) +
47135 +                            sizeof(ATH_LLC_SNAP_HDR);
47136 +
47137 +                if ((pPacket->ActualLength < minHdrLen) ||
47138 +                    (pPacket->ActualLength > AR6000_BUFFER_SIZE))
47139 +                {
47140 +                    /*
47141 +                     * packet is too short or too long
47142 +                     */
47143 +                    AR_DEBUG_PRINTF("TOO SHORT or TOO LONG\n");
47144 +                    AR6000_STAT_INC(ar, rx_errors);
47145 +                    AR6000_STAT_INC(ar, rx_length_errors);
47146 +                    A_NETBUF_FREE(skb);
47147 +                } else {
47148 +                    if (ar->arWmmEnabled) {
47149 +                        wmi_implicit_create_pstream(ar->arWmi, skb,
47150 +                            DNLINK_TRAFFIC, UNDEFINED_PRI);
47151 +                    }
47152 +#if 0
47153 +                    /* Access RSSI values here */
47154 +                    AR_DEBUG_PRINTF("RSSI %d\n",
47155 +                        ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi);
47156 +#endif
47157 +                    wmi_data_hdr_remove(ar->arWmi, skb);
47158 +                    wmi_dot3_2_dix(ar->arWmi, skb);
47159 +
47160 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
47161 +                    /*
47162 +                     * extra push and memcpy, for eth_type_trans() of 2.4 kernel
47163 +                     * will pull out hard_header_len bytes of the skb.
47164 +                     */
47165 +                    A_NETBUF_PUSH(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN);
47166 +                    A_MEMCPY(A_NETBUF_DATA(skb), A_NETBUF_DATA(skb) + sizeof(WMI_DATA_HDR) +
47167 +                             sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR));
47168 +#endif
47169 +                    if ((ar->arNetDev->flags & IFF_UP) == IFF_UP)
47170 +                    {
47171 +                        skb->dev = ar->arNetDev;
47172 +                        skb->protocol = eth_type_trans(skb, ar->arNetDev);
47173 +                        netif_rx(skb);
47174 +                    }
47175 +                    else
47176 +                    {
47177 +                        A_NETBUF_FREE(skb);
47178 +                    }
47179 +                }
47180 +            }
47181 +        }
47182 +    } else {
47183 +        if ((ar->arNetDev->flags & IFF_UP) == IFF_UP)
47184 +        {
47185 +            skb->dev = ar->arNetDev;
47186 +            skb->protocol = eth_type_trans(skb, ar->arNetDev);
47187 +            netif_rx(skb);
47188 +        }
47189 +        else
47190 +        {
47191 +            A_NETBUF_FREE(skb);
47192 +        }
47193 +    }
47194 +
47195 +    if (status != A_ECANCELED) {
47196 +        /*
47197 +         * HTC provides A_ECANCELED status when it doesn't want to be refilled
47198 +         * (probably due to a shutdown)
47199 +         */
47200 +        ar6000_rx_refill(Context, ept);
47201 +    }
47202 +
47203 +
47204 +}
47205 +
47206 +static void
47207 +ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint)
47208 +{
47209 +    AR_SOFTC_T  *ar = (AR_SOFTC_T *)Context;
47210 +    void        *osBuf;
47211 +    int         RxBuffers;
47212 +    int         buffersToRefill;
47213 +    HTC_PACKET  *pPacket;
47214 +    WMI_PRI_STREAM_ID streamId = arEndpoint2WMIStreamID(ar,Endpoint);
47215 +
47216 +    buffersToRefill = (int)AR6000_MAX_RX_BUFFERS -
47217 +                                    (int)ar->arRxBuffers[streamId];
47218 +
47219 +    if (buffersToRefill <= 0) {
47220 +            /* fast return, nothing to fill */
47221 +        return;
47222 +    }
47223 +
47224 +    AR_DEBUG2_PRINTF("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n",
47225 +                    buffersToRefill, Endpoint);
47226 +
47227 +    for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) {
47228 +        osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE);
47229 +        if (NULL == osBuf) {
47230 +            break;
47231 +        }
47232 +            /* the HTC packet wrapper is at the head of the reserved area
47233 +             * in the skb */
47234 +        pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf));
47235 +            /* set re-fill info */
47236 +        SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint);
47237 +            /* add this packet */
47238 +        HTCAddReceivePkt(ar->arHtcTarget, pPacket);
47239 +    }
47240 +
47241 +        /* update count */
47242 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
47243 +    ar->arRxBuffers[streamId] += RxBuffers;
47244 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47245 +}
47246 +
47247 +static struct net_device_stats *
47248 +ar6000_get_stats(struct net_device *dev)
47249 +{
47250 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
47251 +    return &ar->arNetStats;
47252 +}
47253 +
47254 +static struct iw_statistics *
47255 +ar6000_get_iwstats(struct net_device * dev)
47256 +{
47257 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
47258 +    TARGET_STATS *pStats = &ar->arTargetStats;
47259 +    struct iw_statistics * pIwStats = &ar->arIwStats;
47260 +
47261 +    if ((ar->arWmiReady == FALSE)
47262 +    /*
47263 +     * The in_atomic function is used to determine if the scheduling is
47264 +     * allowed in the current context or not. This was introduced in 2.6
47265 +     * From what I have read on the differences between 2.4 and 2.6, the
47266 +     * 2.4 kernel did not support preemption and so this check might not
47267 +     * be required for 2.4 kernels.
47268 +     */
47269 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
47270 +        || (in_atomic())
47271 +#endif
47272 +       )
47273 +    {
47274 +        pIwStats->status = 0;
47275 +        pIwStats->qual.qual = 0;
47276 +        pIwStats->qual.level =0;
47277 +        pIwStats->qual.noise = 0;
47278 +        pIwStats->discard.code =0;
47279 +        pIwStats->discard.retries=0;
47280 +        pIwStats->miss.beacon =0;
47281 +        return pIwStats;
47282 +    }
47283 +    if (down_interruptible(&ar->arSem)) {
47284 +        pIwStats->status = 0;
47285 +        return pIwStats;
47286 +    }
47287 +
47288 +
47289 +    ar->statsUpdatePending = TRUE;
47290 +
47291 +    if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
47292 +        up(&ar->arSem);
47293 +        pIwStats->status = 0;
47294 +        return pIwStats;
47295 +    }
47296 +
47297 +    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
47298 +
47299 +    if (signal_pending(current)) {
47300 +        AR_DEBUG_PRINTF("ar6000 : WMI get stats timeout \n");
47301 +        up(&ar->arSem);
47302 +        pIwStats->status = 0;
47303 +        return pIwStats;
47304 +    }
47305 +    pIwStats->status = 1 ;
47306 +    pIwStats->qual.qual = pStats->cs_aveBeacon_rssi;
47307 +    pIwStats->qual.level =pStats->cs_aveBeacon_rssi + 161;  /* noise is -95 dBm */
47308 +    pIwStats->qual.noise = pStats->noise_floor_calibation;
47309 +    pIwStats->discard.code = pStats->rx_decrypt_err;
47310 +    pIwStats->discard.retries = pStats->tx_retry_cnt;
47311 +    pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
47312 +    up(&ar->arSem);
47313 +    return pIwStats;
47314 +}
47315 +
47316 +void
47317 +ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap)
47318 +{
47319 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
47320 +    struct net_device *dev = ar->arNetDev;
47321 +
47322 +    ar->arWmiReady = TRUE;
47323 +    wake_up(&arEvent);
47324 +    A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN);
47325 +    AR_DEBUG_PRINTF("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
47326 +        dev->dev_addr[0], dev->dev_addr[1],
47327 +        dev->dev_addr[2], dev->dev_addr[3],
47328 +        dev->dev_addr[4], dev->dev_addr[5]);
47329 +
47330 +    ar->arPhyCapability = phyCap;
47331 +}
47332 +
47333 +A_UINT8
47334 +ar6000_iptos_to_userPriority(A_UINT8 *pkt)
47335 +{
47336 +    struct iphdr *ipHdr = (struct iphdr *)pkt;
47337 +    A_UINT8 userPriority;
47338 +
47339 +    /*
47340 +     * IP Tos format :
47341 +     *      (Refer Pg 57 WMM-test-plan-v1.2)
47342 +     * IP-TOS - 8bits
47343 +     *          : DSCP(6-bits) ECN(2-bits)
47344 +     *          : DSCP - P2 P1 P0 X X X
47345 +     *              where (P2 P1 P0) form 802.1D
47346 +     */
47347 +    userPriority = ipHdr->tos >> 5;
47348 +    return (userPriority & 0x7);
47349 +}
47350 +
47351 +void
47352 +ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid,
47353 +                     A_UINT16 listenInterval, A_UINT16 beaconInterval,
47354 +                     NETWORK_TYPE networkType, A_UINT8 beaconIeLen,
47355 +                     A_UINT8 assocReqLen, A_UINT8 assocRespLen,
47356 +                     A_UINT8 *assocInfo)
47357 +{
47358 +    union iwreq_data wrqu;
47359 +    int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos;
47360 +    static const char *tag1 = "ASSOCINFO(ReqIEs=";
47361 +    static const char *tag2 = "ASSOCRESPIE=";
47362 +    static const char *beaconIetag = "BEACONIE=";
47363 +    char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + sizeof(tag1)];
47364 +    char *pos;
47365 +    A_UINT8 key_op_ctrl;
47366 +
47367 +    A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid));
47368 +    ar->arBssChannel = channel;
47369 +
47370 +    A_PRINTF("AR6000 connected event on freq %d ", channel);
47371 +    A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
47372 +            " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d"
47373 +            " assocRespLen =%d\n",
47374 +             bssid[0], bssid[1], bssid[2],
47375 +             bssid[3], bssid[4], bssid[5],
47376 +             listenInterval, beaconInterval,
47377 +             beaconIeLen, assocReqLen, assocRespLen);
47378 +    if (networkType & ADHOC_NETWORK) {
47379 +        if (networkType & ADHOC_CREATOR) {
47380 +            A_PRINTF("Network: Adhoc (Creator)\n");
47381 +        } else {
47382 +            A_PRINTF("Network: Adhoc (Joiner)\n");
47383 +        }
47384 +    } else {
47385 +        A_PRINTF("Network: Infrastructure\n");
47386 +    }
47387 +
47388 +    if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) {
47389 +        AR_DEBUG_PRINTF("\nBeaconIEs= ");
47390 +
47391 +        beacon_ie_pos = 0;
47392 +        A_MEMZERO(buf, sizeof(buf));
47393 +        sprintf(buf, "%s", beaconIetag);
47394 +        pos = buf + 9;
47395 +        for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) {
47396 +            AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
47397 +            sprintf(pos, "%2.2x", assocInfo[i]);
47398 +            pos += 2;
47399 +        }
47400 +        AR_DEBUG_PRINTF("\n");
47401 +
47402 +        A_MEMZERO(&wrqu, sizeof(wrqu));
47403 +        wrqu.data.length = strlen(buf);
47404 +        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
47405 +    }
47406 +
47407 +    if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2))))
47408 +    {
47409 +        assoc_resp_ie_pos = beaconIeLen + assocReqLen +
47410 +                            sizeof(A_UINT16)  +  /* capinfo*/
47411 +                            sizeof(A_UINT16)  +  /* status Code */
47412 +                            sizeof(A_UINT16)  ;  /* associd */
47413 +        A_MEMZERO(buf, sizeof(buf));
47414 +        sprintf(buf, "%s", tag2);
47415 +        pos = buf + 12;
47416 +        AR_DEBUG_PRINTF("\nAssocRespIEs= ");
47417 +        /*
47418 +         * The Association Response Frame w.o. the WLAN header is delivered to
47419 +         * the host, so skip over to the IEs
47420 +         */
47421 +        for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++)
47422 +        {
47423 +            AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
47424 +            sprintf(pos, "%2.2x", assocInfo[i]);
47425 +            pos += 2;
47426 +        }
47427 +        AR_DEBUG_PRINTF("\n");
47428 +
47429 +        A_MEMZERO(&wrqu, sizeof(wrqu));
47430 +        wrqu.data.length = strlen(buf);
47431 +        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
47432 +    }
47433 +
47434 +    if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) {
47435 +        /*
47436 +         * assoc Request includes capability and listen interval. Skip these.
47437 +         */
47438 +        assoc_req_ie_pos =  beaconIeLen +
47439 +                            sizeof(A_UINT16)  +  /* capinfo*/
47440 +                            sizeof(A_UINT16);    /* listen interval */
47441 +
47442 +        A_MEMZERO(buf, sizeof(buf));
47443 +        sprintf(buf, "%s", tag1);
47444 +        pos = buf + 17;
47445 +        AR_DEBUG_PRINTF("AssocReqIEs= ");
47446 +        for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) {
47447 +            AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
47448 +            sprintf(pos, "%2.2x", assocInfo[i]);
47449 +            pos += 2;;
47450 +        }
47451 +        AR_DEBUG_PRINTF("\n");
47452 +
47453 +        A_MEMZERO(&wrqu, sizeof(wrqu));
47454 +        wrqu.data.length = strlen(buf);
47455 +        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
47456 +    }
47457 +
47458 +#ifdef USER_KEYS
47459 +    if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN &&
47460 +        ar->user_saved_keys.keyOk == TRUE)
47461 +    {
47462 +
47463 +        key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC;
47464 +        if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) {
47465 +            key_op_ctrl &= ~KEY_OP_INIT_RSC;
47466 +        } else {
47467 +            key_op_ctrl |= KEY_OP_INIT_RSC;
47468 +        }
47469 +        ar6000_reinstall_keys(ar, key_op_ctrl);
47470 +    }
47471 +#endif /* USER_KEYS */
47472 +
47473 +        /* flush data queues */
47474 +    ar6000_TxDataCleanup(ar);
47475 +
47476 +    netif_wake_queue(ar->arNetDev);
47477 +
47478 +    if ((OPEN_AUTH == ar->arDot11AuthMode) &&
47479 +        (NONE_AUTH == ar->arAuthMode)      &&
47480 +        (WEP_CRYPT == ar->arPairwiseCrypto))
47481 +    {
47482 +        if (!ar->arConnected) {
47483 +            ar6000_install_static_wep_keys(ar);
47484 +        }
47485 +    }
47486 +
47487 +    ar->arConnected  = TRUE;
47488 +    ar->arConnectPending = FALSE;
47489 +
47490 +    reconnect_flag = 0;
47491 +
47492 +    A_MEMZERO(&wrqu, sizeof(wrqu));
47493 +    A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN);
47494 +    wrqu.addr.sa_family = ARPHRD_ETHER;
47495 +    wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
47496 +    if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) {
47497 +        A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap));
47498 +        ar->arNodeNum = 0;
47499 +        ar->arNexEpId = ENDPOINT_2;
47500 +    }
47501 +
47502 +}
47503 +
47504 +void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num)
47505 +{
47506 +    A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1));
47507 +    ar->arNumDataEndPts = num;
47508 +}
47509 +
47510 +void
47511 +ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid,
47512 +                        A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus)
47513 +{
47514 +    A_UINT8 i;
47515 +
47516 +    A_PRINTF("AR6000 disconnected");
47517 +    if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) {
47518 +        A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
47519 +                 bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
47520 +    }
47521 +    A_PRINTF("\n");
47522 +
47523 +    AR_DEBUG_PRINTF("\nDisconnect Reason is %d", reason);
47524 +    AR_DEBUG_PRINTF("\nProtocol Reason/Status Code is %d", protocolReasonStatus);
47525 +    AR_DEBUG_PRINTF("\nAssocResp Frame = %s",
47526 +                    assocRespLen ? " " : "NULL");
47527 +    for (i = 0; i < assocRespLen; i++) {
47528 +        if (!(i % 0x10)) {
47529 +            AR_DEBUG_PRINTF("\n");
47530 +        }
47531 +        AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
47532 +    }
47533 +    AR_DEBUG_PRINTF("\n");
47534 +    /*
47535 +     * If the event is due to disconnect cmd from the host, only they the target
47536 +     * would stop trying to connect. Under any other condition, target would
47537 +     * keep trying to connect.
47538 +     *
47539 +     */
47540 +    if( reason == DISCONNECT_CMD)
47541 +    {
47542 +        ar->arConnectPending = FALSE;
47543 +    } else {
47544 +        ar->arConnectPending = TRUE;
47545 +        if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) ||
47546 +            ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) {
47547 +            ar->arConnected = TRUE;
47548 +            return;
47549 +        }
47550 +    }
47551 +    ar->arConnected = FALSE;
47552 +
47553 +    if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) {
47554 +        reconnect_flag = 0;
47555 +    }
47556 +
47557 +#ifdef USER_KEYS
47558 +    if (reason != CSERV_DISCONNECT)
47559 +    {
47560 +        ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
47561 +        ar->user_key_ctrl      = 0;
47562 +    }
47563 +#endif /* USER_KEYS */
47564 +
47565 +    netif_stop_queue(ar->arNetDev);
47566 +    A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
47567 +    ar->arBssChannel = 0;
47568 +    ar->arBeaconInterval = 0;
47569 +
47570 +    ar6000_TxDataCleanup(ar);
47571 +}
47572 +
47573 +void
47574 +ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode)
47575 +{
47576 +    A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode);
47577 +    ar->arRegCode = regCode;
47578 +}
47579 +
47580 +void
47581 +ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info)
47582 +{
47583 +    static const char *tag = "PRE-AUTH";
47584 +    char buf[128];
47585 +    union iwreq_data wrqu;
47586 +    int i;
47587 +
47588 +    AR_DEBUG_PRINTF("AR6000 Neighbor Report Event\n");
47589 +    for (i=0; i < numAps; info++, i++) {
47590 +        AR_DEBUG_PRINTF("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
47591 +            info->bssid[0], info->bssid[1], info->bssid[2],
47592 +            info->bssid[3], info->bssid[4], info->bssid[5]);
47593 +        if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) {
47594 +            AR_DEBUG_PRINTF("preauth-cap");
47595 +        }
47596 +        if (info->bssFlags & WMI_PMKID_VALID_BSS) {
47597 +            AR_DEBUG_PRINTF(" pmkid-valid\n");
47598 +            continue;           /* we skip bss if the pmkid is already valid */
47599 +        }
47600 +        AR_DEBUG_PRINTF("\n");
47601 +        snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x",
47602 +                 tag,
47603 +                 info->bssid[0], info->bssid[1], info->bssid[2],
47604 +                 info->bssid[3], info->bssid[4], info->bssid[5],
47605 +                 i, info->bssFlags);
47606 +        A_MEMZERO(&wrqu, sizeof(wrqu));
47607 +        wrqu.data.length = strlen(buf);
47608 +        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
47609 +    }
47610 +}
47611 +
47612 +void
47613 +ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast)
47614 +{
47615 +    static const char *tag = "MLME-MICHAELMICFAILURE.indication";
47616 +    char buf[128];
47617 +    union iwreq_data wrqu;
47618 +
47619 +    A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n",
47620 +             keyid, ismcast ? "multi": "uni");
47621 +    snprintf(buf, sizeof(buf), "%s(keyid=%d %scat)", tag, keyid,
47622 +             ismcast ? "multi" : "uni");
47623 +    memset(&wrqu, 0, sizeof(wrqu));
47624 +    wrqu.data.length = strlen(buf);
47625 +    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
47626 +}
47627 +
47628 +void
47629 +ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status)
47630 +{
47631 +       AR_DEBUG_PRINTF("AR6000 scan complete: %d\n", status);
47632 +
47633 +       ar->scan_complete = 1;
47634 +       wake_up_interruptible(&ar6000_scan_queue);
47635 +}
47636 +
47637 +void
47638 +ar6000_targetStats_event(AR_SOFTC_T *ar,  WMI_TARGET_STATS *pTarget)
47639 +{
47640 +    TARGET_STATS *pStats = &ar->arTargetStats;
47641 +    A_UINT8 ac;
47642 +
47643 +    /*A_PRINTF("AR6000 updating target stats\n");*/
47644 +    pStats->tx_packets          += pTarget->txrxStats.tx_stats.tx_packets;
47645 +    pStats->tx_bytes            += pTarget->txrxStats.tx_stats.tx_bytes;
47646 +    pStats->tx_unicast_pkts     += pTarget->txrxStats.tx_stats.tx_unicast_pkts;
47647 +    pStats->tx_unicast_bytes    += pTarget->txrxStats.tx_stats.tx_unicast_bytes;
47648 +    pStats->tx_multicast_pkts   += pTarget->txrxStats.tx_stats.tx_multicast_pkts;
47649 +    pStats->tx_multicast_bytes  += pTarget->txrxStats.tx_stats.tx_multicast_bytes;
47650 +    pStats->tx_broadcast_pkts   += pTarget->txrxStats.tx_stats.tx_broadcast_pkts;
47651 +    pStats->tx_broadcast_bytes  += pTarget->txrxStats.tx_stats.tx_broadcast_bytes;
47652 +    pStats->tx_rts_success_cnt  += pTarget->txrxStats.tx_stats.tx_rts_success_cnt;
47653 +    for(ac = 0; ac < WMM_NUM_AC; ac++)
47654 +        pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac];
47655 +    pStats->tx_errors           += pTarget->txrxStats.tx_stats.tx_errors;
47656 +    pStats->tx_failed_cnt       += pTarget->txrxStats.tx_stats.tx_failed_cnt;
47657 +    pStats->tx_retry_cnt        += pTarget->txrxStats.tx_stats.tx_retry_cnt;
47658 +    pStats->tx_rts_fail_cnt     += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt;
47659 +    pStats->tx_unicast_rate      = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate);
47660 +
47661 +    pStats->rx_packets          += pTarget->txrxStats.rx_stats.rx_packets;
47662 +    pStats->rx_bytes            += pTarget->txrxStats.rx_stats.rx_bytes;
47663 +    pStats->rx_unicast_pkts     += pTarget->txrxStats.rx_stats.rx_unicast_pkts;
47664 +    pStats->rx_unicast_bytes    += pTarget->txrxStats.rx_stats.rx_unicast_bytes;
47665 +    pStats->rx_multicast_pkts   += pTarget->txrxStats.rx_stats.rx_multicast_pkts;
47666 +    pStats->rx_multicast_bytes  += pTarget->txrxStats.rx_stats.rx_multicast_bytes;
47667 +    pStats->rx_broadcast_pkts   += pTarget->txrxStats.rx_stats.rx_broadcast_pkts;
47668 +    pStats->rx_broadcast_bytes  += pTarget->txrxStats.rx_stats.rx_broadcast_bytes;
47669 +    pStats->rx_fragment_pkt     += pTarget->txrxStats.rx_stats.rx_fragment_pkt;
47670 +    pStats->rx_errors           += pTarget->txrxStats.rx_stats.rx_errors;
47671 +    pStats->rx_crcerr           += pTarget->txrxStats.rx_stats.rx_crcerr;
47672 +    pStats->rx_key_cache_miss   += pTarget->txrxStats.rx_stats.rx_key_cache_miss;
47673 +    pStats->rx_decrypt_err      += pTarget->txrxStats.rx_stats.rx_decrypt_err;
47674 +    pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames;
47675 +    pStats->rx_unicast_rate      = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate);
47676 +
47677 +
47678 +    pStats->tkip_local_mic_failure
47679 +                                += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure;
47680 +    pStats->tkip_counter_measures_invoked
47681 +                                += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked;
47682 +    pStats->tkip_replays        += pTarget->txrxStats.tkipCcmpStats.tkip_replays;
47683 +    pStats->tkip_format_errors  += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors;
47684 +    pStats->ccmp_format_errors  += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors;
47685 +    pStats->ccmp_replays        += pTarget->txrxStats.tkipCcmpStats.ccmp_replays;
47686 +
47687 +
47688 +    pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt;
47689 +    pStats->noise_floor_calibation = pTarget->noise_floor_calibation;
47690 +
47691 +    pStats->cs_bmiss_cnt        += pTarget->cservStats.cs_bmiss_cnt;
47692 +    pStats->cs_lowRssi_cnt      += pTarget->cservStats.cs_lowRssi_cnt;
47693 +    pStats->cs_connect_cnt      += pTarget->cservStats.cs_connect_cnt;
47694 +    pStats->cs_disconnect_cnt   += pTarget->cservStats.cs_disconnect_cnt;
47695 +    pStats->cs_aveBeacon_snr    = pTarget->cservStats.cs_aveBeacon_snr;
47696 +    pStats->cs_aveBeacon_rssi   = pTarget->cservStats.cs_aveBeacon_rssi;
47697 +    pStats->cs_lastRoam_msec    = pTarget->cservStats.cs_lastRoam_msec;
47698 +    pStats->cs_snr              = pTarget->cservStats.cs_snr;
47699 +    pStats->cs_rssi             = pTarget->cservStats.cs_rssi;
47700 +
47701 +    pStats->lq_val              = pTarget->lqVal;
47702 +
47703 +    pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped;
47704 +    pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups;
47705 +    pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups;
47706 +    pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded;
47707 +
47708 +    ar->statsUpdatePending = FALSE;
47709 +    wake_up(&arEvent);
47710 +}
47711 +
47712 +void
47713 +ar6000_rssiThreshold_event(AR_SOFTC_T *ar,  WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi)
47714 +{
47715 +    USER_RSSI_THOLD userRssiThold;
47716 +
47717 +    userRssiThold.tag = rssi_map[newThreshold].tag;
47718 +    userRssiThold.rssi = rssi;
47719 +    AR_DEBUG2_PRINTF("rssi Threshold range = %d tag = %d  rssi = %d\n", newThreshold, userRssiThold.tag, rssi);
47720 +#ifdef SEND_EVENT_TO_APP
47721 +    ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD));
47722 +#endif
47723 +}
47724 +
47725 +
47726 +void
47727 +ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source)
47728 +{
47729 +    if (source == APP_HB_CHALLENGE) {
47730 +        /* Report it to the app in case it wants a positive acknowledgement */
47731 +#ifdef SEND_EVENT_TO_APP
47732 +        ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID,
47733 +                                 (A_UINT8 *)&cookie, sizeof(cookie));
47734 +#endif
47735 +    } else {
47736 +        /* This would ignore the replys that come in after their due time */
47737 +        if (cookie == ar->arHBChallengeResp.seqNum) {
47738 +            ar->arHBChallengeResp.outstanding = FALSE;
47739 +        }
47740 +    }
47741 +}
47742 +
47743 +
47744 +void
47745 +ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal)
47746 +{
47747 +    char    *errString[] = {
47748 +                [WMI_TARGET_PM_ERR_FAIL]    "WMI_TARGET_PM_ERR_FAIL",
47749 +                [WMI_TARGET_KEY_NOT_FOUND]  "WMI_TARGET_KEY_NOT_FOUND",
47750 +                [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR",
47751 +                [WMI_TARGET_BMISS]          "WMI_TARGET_BMISS",
47752 +                [WMI_PSDISABLE_NODE_JOIN]   "WMI_PSDISABLE_NODE_JOIN"
47753 +                };
47754 +
47755 +    A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal);
47756 +
47757 +    /* One error is reported at a time, and errorval is a bitmask */
47758 +    if(errorVal & (errorVal - 1))
47759 +       return;
47760 +
47761 +    A_PRINTF("AR6000 Error type = ");
47762 +    switch(errorVal)
47763 +    {
47764 +        case WMI_TARGET_PM_ERR_FAIL:
47765 +        case WMI_TARGET_KEY_NOT_FOUND:
47766 +        case WMI_TARGET_DECRYPTION_ERR:
47767 +        case WMI_TARGET_BMISS:
47768 +        case WMI_PSDISABLE_NODE_JOIN:
47769 +            A_PRINTF("%s\n", errString[errorVal]);
47770 +            break;
47771 +        default:
47772 +            A_PRINTF("INVALID\n");
47773 +            break;
47774 +    }
47775 +
47776 +}
47777 +
47778 +
47779 +void
47780 +ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication,
47781 +                 A_UINT8 statusCode, A_UINT8 *tspecSuggestion)
47782 +{
47783 +    WMM_TSPEC_IE    *tspecIe;
47784 +
47785 +    /*
47786 +     * This is the TSPEC IE suggestion from AP.
47787 +     * Suggestion provided by AP under some error
47788 +     * cases, could be helpful for the host app.
47789 +     * Check documentation.
47790 +     */
47791 +    tspecIe = (WMM_TSPEC_IE *)tspecSuggestion;
47792 +
47793 +    /*
47794 +     * What do we do, if we get TSPEC rejection? One thought
47795 +     * that comes to mind is implictly delete the pstream...
47796 +     */
47797 +    A_PRINTF("AR6000 CAC notification. "
47798 +                "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n",
47799 +                 ac, cacIndication, statusCode);
47800 +}
47801 +
47802 +#define AR6000_PRINT_BSSID(_pBss)  do {     \
47803 +        A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\
47804 +                 (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\
47805 +                 (_pBss)[4],(_pBss)[5]);  \
47806 +} while(0)
47807 +
47808 +void
47809 +ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl)
47810 +{
47811 +    A_UINT8 i;
47812 +
47813 +    A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n",
47814 +              pTbl->numEntries, pTbl->roamMode);
47815 +    for (i= 0; i < pTbl->numEntries; i++) {
47816 +        A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i,
47817 +            pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1],
47818 +            pTbl->bssRoamInfo[i].bssid[2],
47819 +            pTbl->bssRoamInfo[i].bssid[3],
47820 +            pTbl->bssRoamInfo[i].bssid[4],
47821 +            pTbl->bssRoamInfo[i].bssid[5]);
47822 +        A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d"
47823 +                 " BIAS %d\n",
47824 +            pTbl->bssRoamInfo[i].rssi,
47825 +            pTbl->bssRoamInfo[i].rssidt,
47826 +            pTbl->bssRoamInfo[i].last_rssi,
47827 +            pTbl->bssRoamInfo[i].util,
47828 +            pTbl->bssRoamInfo[i].roam_util,
47829 +            pTbl->bssRoamInfo[i].bias);
47830 +    }
47831 +}
47832 +
47833 +void
47834 +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply)
47835 +{
47836 +    A_UINT8 i,j;
47837 +
47838 +    /*Each event now contains exactly one filter, see bug 26613*/
47839 +    A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num,                 wow_reply->num_filters);
47840 +    A_PRINTF("wow mode = %s host mode = %s\n",
47841 +            (wow_reply->wow_mode == 0? "disabled":"enabled"),
47842 +            (wow_reply->host_mode == 1 ? "awake":"asleep"));
47843 +
47844 +
47845 +    /*If there are no patterns, the reply will only contain generic
47846 +      WoW information. Pattern information will exist only if there are
47847 +      patterns present. Bug 26716*/
47848 +
47849 +   /* If this event contains pattern information, display it*/
47850 +    if (wow_reply->this_filter_num) {
47851 +        i=0;
47852 +        A_PRINTF("id=%d size=%d offset=%d\n",
47853 +                    wow_reply->wow_filters[i].wow_filter_id,
47854 +                    wow_reply->wow_filters[i].wow_filter_size,
47855 +                    wow_reply->wow_filters[i].wow_filter_offset);
47856 +       A_PRINTF("wow pattern = ");
47857 +       for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
47858 +             A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]);
47859 +        }
47860 +
47861 +        A_PRINTF("\nwow mask = ");
47862 +        for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
47863 +            A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]);
47864 +        }
47865 +        A_PRINTF("\n");
47866 +    }
47867 +}
47868 +
47869 +/*
47870 + * Report the Roaming related data collected on the target
47871 + */
47872 +void
47873 +ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p)
47874 +{
47875 +    A_PRINTF("Disconnect Data : BSSID: ");
47876 +    AR6000_PRINT_BSSID(p->disassoc_bssid);
47877 +    A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n",
47878 +             p->disassoc_bss_rssi,p->disassoc_time,
47879 +             p->no_txrx_time);
47880 +    A_PRINTF("Connect Data: BSSID: ");
47881 +    AR6000_PRINT_BSSID(p->assoc_bssid);
47882 +    A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n",
47883 +             p->assoc_bss_rssi,p->assoc_time,
47884 +             p->allow_txrx_time);
47885 +    A_PRINTF("Last Data Tx Time (b4 Disassoc) %d "\
47886 +             "First Data Tx Time (after Assoc) %d\n",
47887 +             p->last_data_txrx_time, p->first_data_txrx_time);
47888 +}
47889 +
47890 +void
47891 +ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p)
47892 +{
47893 +    switch (p->roamDataType) {
47894 +        case ROAM_DATA_TIME:
47895 +            ar6000_display_roam_time(&p->u.roamTime);
47896 +            break;
47897 +        default:
47898 +            break;
47899 +    }
47900 +}
47901 +
47902 +void
47903 +ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len)
47904 +{
47905 +    struct sk_buff *skb;
47906 +    WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap;
47907 +
47908 +
47909 +    if (!ar->arMgmtFilter) {
47910 +        return;
47911 +    }
47912 +    if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) &&
47913 +        (bih->frameType != BEACON_FTYPE))  ||
47914 +        ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) &&
47915 +        (bih->frameType != PROBERESP_FTYPE)))
47916 +    {
47917 +        return;
47918 +    }
47919 +
47920 +    if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) {
47921 +
47922 +        A_NETBUF_PUT(skb, len);
47923 +        A_MEMCPY(A_NETBUF_DATA(skb), datap, len);
47924 +        skb->dev = ar->arNetDev;
47925 +       printk("MAC RAW...\n");
47926 +//        skb->mac.raw = A_NETBUF_DATA(skb);
47927 +        skb->ip_summed = CHECKSUM_NONE;
47928 +        skb->pkt_type = PACKET_OTHERHOST;
47929 +        skb->protocol = __constant_htons(0x0019);
47930 +        netif_rx(skb);
47931 +    }
47932 +}
47933 +
47934 +A_UINT32 wmiSendCmdNum;
47935 +
47936 +A_STATUS
47937 +ar6000_control_tx(void *devt, void *osbuf, WMI_PRI_STREAM_ID streamID)
47938 +{
47939 +    AR_SOFTC_T       *ar = (AR_SOFTC_T *)devt;
47940 +    A_STATUS         status = A_OK;
47941 +    struct ar_cookie *cookie = NULL;
47942 +    int i;
47943 +
47944 +        /* take lock to protect ar6000_alloc_cookie() */
47945 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
47946 +
47947 +    do {
47948 +
47949 +        AR_DEBUG2_PRINTF("ar_contrstatus = ol_tx: skb=0x%x, len=0x%x, sid=%d\n",
47950 +                         (A_UINT32)osbuf, A_NETBUF_LEN(osbuf), streamID);
47951 +
47952 +        if ((streamID == WMI_CONTROL_PRI) && (ar->arWMIControlEpFull)) {
47953 +                /* control endpoint is full, don't allocate resources, we
47954 +                 * are just going to drop this packet */
47955 +            cookie = NULL;
47956 +            AR_DEBUG_PRINTF(" WMI Control EP full, dropping packet : 0x%X, len:%d \n",
47957 +                    (A_UINT32)osbuf, A_NETBUF_LEN(osbuf));
47958 +        } else {
47959 +            cookie = ar6000_alloc_cookie(ar);
47960 +        }
47961 +
47962 +        if (cookie == NULL) {
47963 +            status = A_NO_MEMORY;
47964 +            break;
47965 +        }
47966 +
47967 +        if(logWmiRawMsgs) {
47968 +            A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum);
47969 +            for(i = 0; i < a_netbuf_to_len(osbuf); i++)
47970 +                A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]);
47971 +            A_PRINTF("\n");
47972 +        }
47973 +
47974 +        wmiSendCmdNum++;
47975 +
47976 +    } while (FALSE);
47977 +
47978 +    if (cookie != NULL) {
47979 +            /* got a structure to send it out on */
47980 +        ar->arTxPending[streamID]++;
47981 +
47982 +        if (streamID != WMI_CONTROL_PRI) {
47983 +            ar->arTotalTxDataPending++;
47984 +        }
47985 +    }
47986 +
47987 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47988 +
47989 +    if (cookie != NULL) {
47990 +        cookie->arc_bp[0] = (A_UINT32)osbuf;
47991 +        cookie->arc_bp[1] = 0;
47992 +        SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
47993 +                               cookie,
47994 +                               A_NETBUF_DATA(osbuf),
47995 +                               A_NETBUF_LEN(osbuf),
47996 +                               arWMIStream2EndpointID(ar,streamID),
47997 +                               AR6K_CONTROL_PKT_TAG);
47998 +            /* this interface is asynchronous, if there is an error, cleanup will happen in the
47999 +             * TX completion callback */
48000 +        HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
48001 +        status = A_OK;
48002 +    }
48003 +
48004 +    return status;
48005 +}
48006 +
48007 +/* indicate tx activity or inactivity on a WMI stream */
48008 +void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active)
48009 +{
48010 +    AR_SOFTC_T  *ar = (AR_SOFTC_T *)devt;
48011 +    WMI_PRI_STREAM_ID streamid;
48012 +
48013 +    if (ar->arWmiEnabled) {
48014 +        streamid = wmi_get_stream_id(ar->arWmi, TrafficClass);
48015 +    } else {
48016 +            /* for mbox ping testing, the traffic class is mapped directly as a stream ID,
48017 +             * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c */
48018 +        streamid = (WMI_PRI_STREAM_ID)TrafficClass;
48019 +    }
48020 +
48021 +        /* notify HTC, this may cause credit distribution changes */
48022 +
48023 +    HTCIndicateActivityChange(ar->arHtcTarget,
48024 +                              arWMIStream2EndpointID(ar,streamid),
48025 +                              Active);
48026 +
48027 +}
48028 +
48029 +module_init(ar6000_init_module);
48030 +module_exit(ar6000_cleanup_module);
48031 +
48032 +/* Init cookie queue */
48033 +static void
48034 +ar6000_cookie_init(AR_SOFTC_T *ar)
48035 +{
48036 +    A_UINT32    i;
48037 +
48038 +    ar->arCookieList = NULL;
48039 +    A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem));
48040 +
48041 +    for (i = 0; i < MAX_COOKIE_NUM; i++) {
48042 +        ar6000_free_cookie(ar, &s_ar_cookie_mem[i]);
48043 +    }
48044 +}
48045 +
48046 +/* cleanup cookie queue */
48047 +static void
48048 +ar6000_cookie_cleanup(AR_SOFTC_T *ar)
48049 +{
48050 +    /* It is gone .... */
48051 +    ar->arCookieList = NULL;
48052 +}
48053 +
48054 +/* Init cookie queue */
48055 +static void
48056 +ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie)
48057 +{
48058 +    /* Insert first */
48059 +    A_ASSERT(ar != NULL);
48060 +    A_ASSERT(cookie != NULL);
48061 +    cookie->arc_list_next = ar->arCookieList;
48062 +    ar->arCookieList = cookie;
48063 +}
48064 +
48065 +/* cleanup cookie queue */
48066 +static struct ar_cookie *
48067 +ar6000_alloc_cookie(AR_SOFTC_T  *ar)
48068 +{
48069 +    struct ar_cookie   *cookie;
48070 +
48071 +    cookie = ar->arCookieList;
48072 +    if(cookie != NULL)
48073 +    {
48074 +        ar->arCookieList = cookie->arc_list_next;
48075 +    }
48076 +
48077 +    return cookie;
48078 +}
48079 +
48080 +#ifdef SEND_EVENT_TO_APP
48081 +/*
48082 + * This function is used to send event which come from taget to
48083 + * the application. The buf which send to application is include
48084 + * the event ID and event content.
48085 + */
48086 +#define EVENT_ID_LEN   2
48087 +void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId,
48088 +                              A_UINT8 *datap, int len)
48089 +{
48090 +
48091 +#if (WIRELESS_EXT >= 15)
48092 +
48093 +/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */
48094 +
48095 +    char *buf;
48096 +    A_UINT16 size;
48097 +    union iwreq_data wrqu;
48098 +
48099 +    size = len + EVENT_ID_LEN;
48100 +
48101 +    if (size > IW_CUSTOM_MAX) {
48102 +        AR_DEBUG_PRINTF("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n",
48103 +                eventId, size, IW_CUSTOM_MAX);
48104 +        return;
48105 +    }
48106 +
48107 +    buf = A_MALLOC_NOWAIT(size);
48108 +    A_MEMZERO(buf, size);
48109 +    A_MEMCPY(buf, &eventId, EVENT_ID_LEN);
48110 +    A_MEMCPY(buf+EVENT_ID_LEN, datap, len);
48111 +
48112 +    //AR_DEBUG_PRINTF("event ID = %d,len = %d\n",*(A_UINT16*)buf, size);
48113 +    A_MEMZERO(&wrqu, sizeof(wrqu));
48114 +    wrqu.data.length = size;
48115 +    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
48116 +
48117 +    A_FREE(buf);
48118 +#endif
48119 +
48120 +
48121 +}
48122 +#endif
48123 +
48124 +
48125 +void
48126 +ar6000_tx_retry_err_event(void *devt)
48127 +{
48128 +    AR_DEBUG2_PRINTF("Tx retries reach maximum!\n");
48129 +}
48130 +
48131 +void
48132 +ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr)
48133 +{
48134 +    AR_DEBUG2_PRINTF("snr threshold range %d, snr %d\n", newThreshold, snr);
48135 +}
48136 +
48137 +void
48138 +ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq)
48139 +{
48140 +    AR_DEBUG2_PRINTF("lq threshold range %d, lq %d\n", newThreshold, lq);
48141 +}
48142 +
48143 +
48144 +
48145 +A_UINT32
48146 +a_copy_to_user(void *to, const void *from, A_UINT32 n)
48147 +{
48148 +    return(copy_to_user(to, from, n));
48149 +}
48150 +
48151 +A_UINT32
48152 +a_copy_from_user(void *to, const void *from, A_UINT32 n)
48153 +{
48154 +    return(copy_from_user(to, from, n));
48155 +}
48156 +
48157 +
48158 +A_STATUS
48159 +ar6000_get_driver_cfg(struct net_device *dev,
48160 +                        A_UINT16 cfgParam,
48161 +                        void *result)
48162 +{
48163 +
48164 +    A_STATUS    ret = 0;
48165 +
48166 +    switch(cfgParam)
48167 +    {
48168 +        case AR6000_DRIVER_CFG_GET_WLANNODECACHING:
48169 +           *((A_UINT32 *)result) = wlanNodeCaching;
48170 +           break;
48171 +        case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS:
48172 +           *((A_UINT32 *)result) = logWmiRawMsgs;
48173 +            break;
48174 +        default:
48175 +           ret = EINVAL;
48176 +           break;
48177 +    }
48178 +
48179 +    return ret;
48180 +}
48181 +
48182 +void
48183 +ar6000_keepalive_rx(void *devt, A_UINT8 configured)
48184 +{
48185 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
48186 +
48187 +    ar->arKeepaliveConfigured = configured;
48188 +    wake_up(&arEvent);
48189 +}
48190 +
48191 +void
48192 +ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList)
48193 +{
48194 +    A_UINT8 i, j;
48195 +
48196 +    A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID);
48197 +
48198 +    for (i = 0; i < numPMKID; i++) {
48199 +        A_PRINTF("\nPMKID %d ", i);
48200 +            for (j = 0; j < WMI_PMKID_LEN; j++) {
48201 +                A_PRINTF("%2.2x", pmkidList->pmkid[j]);
48202 +            }
48203 +        pmkidList++;
48204 +    }
48205 +}
48206 +
48207 +#ifdef USER_KEYS
48208 +static A_STATUS
48209 +
48210 +ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl)
48211 +{
48212 +    A_STATUS status = A_OK;
48213 +    struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik;
48214 +    struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik;
48215 +    CRYPTO_TYPE  keyType = ar->user_saved_keys.keyType;
48216 +
48217 +    if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) {
48218 +        if (NONE_CRYPT == keyType) {
48219 +            goto _reinstall_keys_out;
48220 +        }
48221 +
48222 +        if (uik->ik_keylen) {
48223 +            status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix,
48224 +                    ar->user_saved_keys.keyType, PAIRWISE_USAGE,
48225 +                    uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc,
48226 +                    uik->ik_keydata, key_op_ctrl, SYNC_BEFORE_WMIFLAG);
48227 +        }
48228 +
48229 +    } else {
48230 +        status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata);
48231 +    }
48232 +
48233 +    if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) {
48234 +        if (NONE_CRYPT == keyType) {
48235 +            goto _reinstall_keys_out;
48236 +        }
48237 +
48238 +        if (bik->ik_keylen) {
48239 +            status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix,
48240 +                    ar->user_saved_keys.keyType, GROUP_USAGE,
48241 +                    bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc,
48242 +                    bik->ik_keydata, key_op_ctrl, NO_SYNC_WMIFLAG);
48243 +        }
48244 +    } else {
48245 +        status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata);
48246 +    }
48247 +
48248 +_reinstall_keys_out:
48249 +    ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
48250 +    ar->user_key_ctrl      = 0;
48251 +
48252 +    return status;
48253 +}
48254 +#endif /* USER_KEYS */
48255 +
48256 +
48257 +void
48258 +ar6000_dset_open_req(
48259 +    void *context,
48260 +    A_UINT32 id,
48261 +    A_UINT32 targHandle,
48262 +    A_UINT32 targReplyFn,
48263 +    A_UINT32 targReplyArg)
48264 +{
48265 +}
48266 +
48267 +void
48268 +ar6000_dset_close(
48269 +    void *context,
48270 +    A_UINT32 access_cookie)
48271 +{
48272 +    return;
48273 +}
48274 +
48275 +void
48276 +ar6000_dset_data_req(
48277 +   void *context,
48278 +   A_UINT32 accessCookie,
48279 +   A_UINT32 offset,
48280 +   A_UINT32 length,
48281 +   A_UINT32 targBuf,
48282 +   A_UINT32 targReplyFn,
48283 +   A_UINT32 targReplyArg)
48284 +{
48285 +}
48286 --- /dev/null
48287 +++ b/drivers/ar6000/ar6000/ar6000_drv.h
48288 @@ -0,0 +1,361 @@
48289 +/*
48290 + *
48291 + * Copyright (c) 2004-2007 Atheros Communications Inc.
48292 + * All rights reserved.
48293 + *
48294 + *
48295 + *  This program is free software; you can redistribute it and/or modify
48296 + *  it under the terms of the GNU General Public License version 2 as
48297 + *  published by the Free Software Foundation;
48298 + *
48299 + *  Software distributed under the License is distributed on an "AS
48300 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
48301 + *  implied. See the License for the specific language governing
48302 + *  rights and limitations under the License.
48303 + *
48304 + *
48305 + *
48306 + */
48307 +
48308 +#ifndef _AR6000_H_
48309 +#define _AR6000_H_
48310 +
48311 +#include <linux/version.h>
48312 +
48313 +
48314 +#include <linux/autoconf.h>
48315 +#include <linux/init.h>
48316 +#include <linux/kernel.h>
48317 +#include <linux/spinlock.h>
48318 +#include <linux/skbuff.h>
48319 +#include <linux/if_ether.h>
48320 +#include <linux/netdevice.h>
48321 +#include <linux/etherdevice.h>
48322 +#include <net/iw_handler.h>
48323 +#include <linux/if_arp.h>
48324 +#include <linux/ip.h>
48325 +#include <linux/semaphore.h>
48326 +#include <linux/wireless.h>
48327 +#include <linux/module.h>
48328 +#include <asm/io.h>
48329 +
48330 +#include <a_config.h>
48331 +#include <athdefs.h>
48332 +#include "a_types.h"
48333 +#include "a_osapi.h"
48334 +#include "htc_api.h"
48335 +#include "wmi.h"
48336 +#include "a_drv.h"
48337 +#include "bmi.h"
48338 +#include <ieee80211.h>
48339 +#include <ieee80211_ioctl.h>
48340 +#include <wlan_api.h>
48341 +#include <wmi_api.h>
48342 +#include "gpio_api.h"
48343 +#include "gpio.h"
48344 +#include <host_version.h>
48345 +#include <linux/rtnetlink.h>
48346 +#include <linux/init.h>
48347 +#include <linux/moduleparam.h>
48348 +#include "AR6Khwreg.h"
48349 +#include "ar6000_api.h"
48350 +#ifdef CONFIG_HOST_TCMD_SUPPORT
48351 +#include <testcmd.h>
48352 +#endif
48353 +
48354 +#include "targaddrs.h"
48355 +#include "dbglog_api.h"
48356 +#include "ar6000_diag.h"
48357 +#include "common_drv.h"
48358 +
48359 +#ifndef  __dev_put
48360 +#define  __dev_put(dev) dev_put(dev)
48361 +#endif
48362 +
48363 +#ifdef USER_KEYS
48364 +
48365 +#define USER_SAVEDKEYS_STAT_INIT     0
48366 +#define USER_SAVEDKEYS_STAT_RUN      1
48367 +
48368 +// TODO this needs to move into the AR_SOFTC struct
48369 +struct USER_SAVEDKEYS {
48370 +    struct ieee80211req_key   ucast_ik;
48371 +    struct ieee80211req_key   bcast_ik;
48372 +    CRYPTO_TYPE               keyType;
48373 +    A_BOOL                    keyOk;
48374 +};
48375 +#endif
48376 +
48377 +#define DBG_INFO               0x00000001
48378 +#define DBG_ERROR              0x00000002
48379 +#define DBG_WARNING            0x00000004
48380 +#define DBG_SDIO               0x00000008
48381 +#define DBG_HIF                        0x00000010
48382 +#define DBG_HTC                        0x00000020
48383 +#define DBG_WMI                        0x00000040
48384 +#define DBG_WMI2               0x00000080
48385 +#define DBG_DRIVER             0x00000100
48386 +
48387 +#define DBG_DEFAULTS   (DBG_ERROR|DBG_WARNING)
48388 +
48389 +
48390 +#ifdef DEBUG
48391 +#define AR_DEBUG_PRINTF(args...)        if (debugdriver) A_PRINTF(args);
48392 +#define AR_DEBUG2_PRINTF(args...)        if (debugdriver >= 2) A_PRINTF(args);
48393 +extern int debugdriver;
48394 +#else
48395 +#define AR_DEBUG_PRINTF(args...)
48396 +#define AR_DEBUG2_PRINTF(args...)
48397 +#endif
48398 +
48399 +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
48400 +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
48401 +
48402 +#ifdef __cplusplus
48403 +extern "C" {
48404 +#endif
48405 +
48406 +#define        MAX_AR6000                        1
48407 +#define AR6000_MAX_RX_BUFFERS             16
48408 +#define AR6000_BUFFER_SIZE                1664
48409 +#define AR6000_TX_TIMEOUT                 10
48410 +#define        AR6000_ETH_ADDR_LEN               6
48411 +#define        AR6000_MAX_ENDPOINTS              4
48412 +#define MAX_NODE_NUM                      15
48413 +#define MAX_COOKIE_NUM                    150
48414 +#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT        1
48415 +#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT  1
48416 +
48417 +enum {
48418 +    DRV_HB_CHALLENGE = 0,
48419 +    APP_HB_CHALLENGE
48420 +};
48421 +
48422 +/* HTC RAW streams */
48423 +typedef enum _HTC_RAW_STREAM_ID {
48424 +    HTC_RAW_STREAM_NOT_MAPPED = -1,
48425 +    HTC_RAW_STREAM_0 = 0,
48426 +    HTC_RAW_STREAM_1 = 1,
48427 +    HTC_RAW_STREAM_2 = 2,
48428 +    HTC_RAW_STREAM_3 = 3,
48429 +    HTC_RAW_STREAM_NUM_MAX
48430 +} HTC_RAW_STREAM_ID;
48431 +
48432 +#define RAW_HTC_READ_BUFFERS_NUM    4
48433 +#define RAW_HTC_WRITE_BUFFERS_NUM   4
48434 +
48435 +typedef struct {
48436 +    int currPtr;
48437 +    int length;
48438 +    unsigned char data[AR6000_BUFFER_SIZE];
48439 +    HTC_PACKET    HTCPacket;
48440 +} raw_htc_buffer;
48441 +
48442 +#ifdef CONFIG_HOST_TCMD_SUPPORT
48443 +/*
48444 + *  add TCMD_MODE besides wmi and bypasswmi
48445 + *  in TCMD_MODE, only few TCMD releated wmi commands
48446 + *  counld be hanlder
48447 + */
48448 +enum {
48449 +    AR6000_WMI_MODE = 0,
48450 +    AR6000_BYPASS_MODE,
48451 +    AR6000_TCMD_MODE,
48452 +    AR6000_WLAN_MODE
48453 +};
48454 +#endif /* CONFIG_HOST_TCMD_SUPPORT */
48455 +
48456 +struct ar_wep_key {
48457 +    A_UINT8                 arKeyIndex;
48458 +    A_UINT8                 arKeyLen;
48459 +    A_UINT8                 arKey[64];
48460 +} ;
48461 +
48462 +struct ar_node_mapping {
48463 +    A_UINT8                 macAddress[6];
48464 +    A_UINT8                 epId;
48465 +    A_UINT8                 txPending;
48466 +};
48467 +
48468 +struct ar_cookie {
48469 +    A_UINT32               arc_bp[2];    /* Must be first field */
48470 +    HTC_PACKET             HtcPkt;       /* HTC packet wrapper */
48471 +    struct ar_cookie *arc_list_next;
48472 +};
48473 +
48474 +struct ar_hb_chlng_resp {
48475 +    A_TIMER                 timer;
48476 +    A_UINT32                frequency;
48477 +    A_UINT32                seqNum;
48478 +    A_BOOL                  outstanding;
48479 +    A_UINT8                 missCnt;
48480 +    A_UINT8                 missThres;
48481 +};
48482 +
48483 +typedef struct ar6_softc {
48484 +    struct net_device       *arNetDev;    /* net_device pointer */
48485 +    void                    *arWmi;
48486 +    int                     arTxPending[WMI_PRI_MAX_COUNT];
48487 +    int                     arTotalTxDataPending;
48488 +    A_UINT8                 arNumDataEndPts;
48489 +    A_BOOL                  arWmiEnabled;
48490 +    A_BOOL                  arWmiReady;
48491 +    A_BOOL                  arConnected;
48492 +    A_BOOL                  arRadioSwitch;
48493 +    HTC_HANDLE              arHtcTarget;
48494 +    void                    *arHifDevice;
48495 +    spinlock_t              arLock;
48496 +    struct semaphore        arSem;
48497 +    int                     arRxBuffers[WMI_PRI_MAX_COUNT];
48498 +    int                     arSsidLen;
48499 +    u_char                  arSsid[32];
48500 +    A_UINT8                 arNetworkType;
48501 +    A_UINT8                 arDot11AuthMode;
48502 +    A_UINT8                 arAuthMode;
48503 +    A_UINT8                 arPairwiseCrypto;
48504 +    A_UINT8                 arPairwiseCryptoLen;
48505 +    A_UINT8                 arGroupCrypto;
48506 +    A_UINT8                 arGroupCryptoLen;
48507 +    A_UINT8                 arDefTxKeyIndex;
48508 +    struct ar_wep_key       arWepKeyList[WMI_MAX_KEY_INDEX + 1];
48509 +    A_UINT8                 arBssid[6];
48510 +    A_UINT8                 arReqBssid[6];
48511 +    A_UINT16                arChannelHint;
48512 +    A_UINT16                arBssChannel;
48513 +    A_UINT16                arListenInterval;
48514 +    struct ar6000_version   arVersion;
48515 +    A_UINT32                arTargetType;
48516 +    A_INT8                  arRssi;
48517 +    A_UINT8                 arTxPwr;
48518 +    A_BOOL                  arTxPwrSet;
48519 +    A_INT32                 arBitRate;
48520 +    struct net_device_stats arNetStats;
48521 +    struct iw_statistics       arIwStats;
48522 +    A_INT8                  arNumChannels;
48523 +    A_UINT16                arChannelList[32];
48524 +    A_UINT32                arRegCode;
48525 +    A_BOOL                  statsUpdatePending;
48526 +    TARGET_STATS            arTargetStats;
48527 +    A_INT8                  arMaxRetries;
48528 +    A_UINT8                 arPhyCapability;
48529 +#ifdef CONFIG_HOST_TCMD_SUPPORT
48530 +    A_UINT8                 tcmdRxReport;
48531 +    A_UINT32                tcmdRxTotalPkt;
48532 +    A_INT32                 tcmdRxRssi;
48533 +    A_UINT32                tcmdPm;
48534 +   A_UINT32                 arTargetMode;
48535 +#endif
48536 +    AR6000_WLAN_STATE       arWlanState;
48537 +    struct ar_node_mapping  arNodeMap[MAX_NODE_NUM];
48538 +    A_UINT8                 arIbssPsEnable;
48539 +    A_UINT8                 arNodeNum;
48540 +    A_UINT8                 arNexEpId;
48541 +    struct ar_cookie        *arCookieList;
48542 +    A_UINT16                arRateMask;
48543 +    A_UINT8                 arSkipScan;
48544 +    A_UINT16                arBeaconInterval;
48545 +    A_BOOL                  arConnectPending;
48546 +    A_BOOL                  arWmmEnabled;
48547 +    struct ar_hb_chlng_resp arHBChallengeResp;
48548 +    A_UINT8                 arKeepaliveConfigured;
48549 +    A_UINT32                arMgmtFilter;
48550 +    HTC_ENDPOINT_ID         arWmi2EpMapping[WMI_PRI_MAX_COUNT];
48551 +    WMI_PRI_STREAM_ID       arEp2WmiMapping[ENDPOINT_MAX];
48552 +#ifdef HTC_RAW_INTERFACE
48553 +    HTC_ENDPOINT_ID         arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX];
48554 +    HTC_RAW_STREAM_ID       arEp2RawMapping[ENDPOINT_MAX];
48555 +    struct semaphore        raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX];
48556 +    struct semaphore        raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX];
48557 +    wait_queue_head_t       raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX];
48558 +    wait_queue_head_t       raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX];
48559 +    raw_htc_buffer          *raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM];
48560 +    raw_htc_buffer          *raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM];
48561 +    A_BOOL                  write_buffer_available[HTC_RAW_STREAM_NUM_MAX];
48562 +    A_BOOL                  read_buffer_available[HTC_RAW_STREAM_NUM_MAX];
48563 +#endif
48564 +    A_BOOL                  arNetQueueStopped;
48565 +    A_BOOL                  arRawIfInit;
48566 +    int                     arDeviceIndex;
48567 +    COMMON_CREDIT_STATE_INFO arCreditStateInfo;
48568 +    A_BOOL                  arWMIControlEpFull;
48569 +    A_BOOL                  dbgLogFetchInProgress;
48570 +    A_UCHAR                 log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE];
48571 +    A_UINT32                log_cnt;
48572 +    A_UINT32                dbglog_init_done;
48573 +    A_UINT32                arConnectCtrlFlags;
48574 +       A_UINT32                scan_complete;
48575 +#ifdef USER_KEYS
48576 +    A_INT32                 user_savedkeys_stat;
48577 +    A_UINT32                user_key_ctrl;
48578 +    struct USER_SAVEDKEYS   user_saved_keys;
48579 +#endif
48580 +} AR_SOFTC_T;
48581 +
48582 +
48583 +#define arWMIStream2EndpointID(ar,wmi)          (ar)->arWmi2EpMapping[(wmi)]
48584 +#define arSetWMIStream2EndpointIDMap(ar,wmi,ep)  \
48585 +{  (ar)->arWmi2EpMapping[(wmi)] = (ep); \
48586 +   (ar)->arEp2WmiMapping[(ep)] = (wmi); }
48587 +#define arEndpoint2WMIStreamID(ar,ep)           (ar)->arEp2WmiMapping[(ep)]
48588 +
48589 +#define arRawIfEnabled(ar) (ar)->arRawIfInit
48590 +#define arRawStream2EndpointID(ar,raw)          (ar)->arRaw2EpMapping[(raw)]
48591 +#define arSetRawStream2EndpointIDMap(ar,raw,ep)  \
48592 +{  (ar)->arRaw2EpMapping[(raw)] = (ep); \
48593 +   (ar)->arEp2RawMapping[(ep)] = (raw); }
48594 +#define arEndpoint2RawStreamID(ar,ep)           (ar)->arEp2RawMapping[(ep)]
48595 +
48596 +struct ar_giwscan_param {
48597 +    char    *current_ev;
48598 +    char    *end_buf;
48599 +    A_BOOL  firstPass;
48600 +};
48601 +
48602 +#define AR6000_STAT_INC(ar, stat)       (ar->arNetStats.stat++)
48603 +
48604 +#define AR6000_SPIN_LOCK(lock, param)   do {                            \
48605 +    if (irqs_disabled()) {                                              \
48606 +        AR_DEBUG_PRINTF("IRQs disabled:AR6000_LOCK\n");                 \
48607 +    }                                                                   \
48608 +    spin_lock_bh(lock);                                                 \
48609 +} while (0)
48610 +
48611 +#define AR6000_SPIN_UNLOCK(lock, param) do {                            \
48612 +    if (irqs_disabled()) {                                              \
48613 +        AR_DEBUG_PRINTF("IRQs disabled: AR6000_UNLOCK\n");              \
48614 +    }                                                                   \
48615 +    spin_unlock_bh(lock);                                               \
48616 +} while (0)
48617 +
48618 +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
48619 +int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd);
48620 +void ar6000_ioctl_iwsetup(struct iw_handler_def *def);
48621 +void ar6000_gpio_init(void);
48622 +void ar6000_init_profile_info(AR_SOFTC_T *ar);
48623 +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar);
48624 +int ar6000_init(struct net_device *dev);
48625 +int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar);
48626 +A_STATUS ar6000_SetHTCBlockSize(AR_SOFTC_T *ar);
48627 +
48628 +#ifdef HTC_RAW_INTERFACE
48629 +
48630 +#ifndef __user
48631 +#define __user
48632 +#endif
48633 +
48634 +int ar6000_htc_raw_open(AR_SOFTC_T *ar);
48635 +int ar6000_htc_raw_close(AR_SOFTC_T *ar);
48636 +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar,
48637 +                            HTC_RAW_STREAM_ID StreamID,
48638 +                            char __user *buffer, size_t count);
48639 +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar,
48640 +                             HTC_RAW_STREAM_ID StreamID,
48641 +                             char __user *buffer, size_t count);
48642 +
48643 +#endif /* HTC_RAW_INTERFACE */
48644 +
48645 +#ifdef __cplusplus
48646 +}
48647 +#endif
48648 +
48649 +#endif /* _AR6000_H_ */
48650 --- /dev/null
48651 +++ b/drivers/ar6000/ar6000/ar6000_raw_if.c
48652 @@ -0,0 +1,439 @@
48653 +/*
48654 + *
48655 + * Copyright (c) 2004-2007 Atheros Communications Inc.
48656 + * All rights reserved.
48657 + *
48658 + *
48659 + *  This program is free software; you can redistribute it and/or modify
48660 + *  it under the terms of the GNU General Public License version 2 as
48661 + *  published by the Free Software Foundation;
48662 + *
48663 + *  Software distributed under the License is distributed on an "AS
48664 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
48665 + *  implied. See the License for the specific language governing
48666 + *  rights and limitations under the License.
48667 + *
48668 + *
48669 + *
48670 + */
48671 +
48672 +#include "ar6000_drv.h"
48673 +
48674 +#ifdef HTC_RAW_INTERFACE
48675 +
48676 +static void
48677 +ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket)
48678 +{
48679 +    AR_SOFTC_T        *ar = (AR_SOFTC_T *)Context;
48680 +    raw_htc_buffer    *busy;
48681 +    HTC_RAW_STREAM_ID streamID;
48682 +
48683 +    busy = (raw_htc_buffer *)pPacket->pPktContext;
48684 +    A_ASSERT(busy != NULL);
48685 +
48686 +    if (pPacket->Status == A_ECANCELED) {
48687 +        /*
48688 +         * HTC provides A_ECANCELED status when it doesn't want to be refilled
48689 +         * (probably due to a shutdown)
48690 +         */
48691 +        return;
48692 +    }
48693 +
48694 +    streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
48695 +    A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
48696 +
48697 +#ifdef CF
48698 +   if (down_trylock(&ar->raw_htc_read_sem[streamID])) {
48699 +#else
48700 +    if (down_interruptible(&ar->raw_htc_read_sem[streamID])) {
48701 +#endif /* CF */
48702 +        AR_DEBUG2_PRINTF("Unable to down the semaphore\n");
48703 +    }
48704 +
48705 +    A_ASSERT((pPacket->Status != A_OK) ||
48706 +             (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN)));
48707 +
48708 +    busy->length = pPacket->ActualLength + HTC_HEADER_LEN;
48709 +    busy->currPtr = HTC_HEADER_LEN;
48710 +    ar->read_buffer_available[streamID] = TRUE;
48711 +    //AR_DEBUG_PRINTF("raw read cb:  0x%X 0x%X \n", busy->currPtr,busy->length);
48712 +    up(&ar->raw_htc_read_sem[streamID]);
48713 +
48714 +    /* Signal the waiting process */
48715 +    AR_DEBUG2_PRINTF("Waking up the StreamID(%d) read process\n", streamID);
48716 +    wake_up_interruptible(&ar->raw_htc_read_queue[streamID]);
48717 +}
48718 +
48719 +static void
48720 +ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket)
48721 +{
48722 +    AR_SOFTC_T          *ar = (AR_SOFTC_T  *)Context;
48723 +    raw_htc_buffer      *free;
48724 +    HTC_RAW_STREAM_ID   streamID;
48725 +
48726 +    free = (raw_htc_buffer *)pPacket->pPktContext;
48727 +    A_ASSERT(free != NULL);
48728 +
48729 +    if (pPacket->Status == A_ECANCELED) {
48730 +        /*
48731 +         * HTC provides A_ECANCELED status when it doesn't want to be refilled
48732 +         * (probably due to a shutdown)
48733 +         */
48734 +        return;
48735 +    }
48736 +
48737 +    streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
48738 +    A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
48739 +
48740 +#ifdef CF
48741 +    if (down_trylock(&ar->raw_htc_write_sem[streamID])) {
48742 +#else
48743 +    if (down_interruptible(&ar->raw_htc_write_sem[streamID])) {
48744 +#endif
48745 +        AR_DEBUG2_PRINTF("Unable to down the semaphore\n");
48746 +    }
48747 +
48748 +    A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN));
48749 +
48750 +    free->length = 0;
48751 +    ar->write_buffer_available[streamID] = TRUE;
48752 +    up(&ar->raw_htc_write_sem[streamID]);
48753 +
48754 +    /* Signal the waiting process */
48755 +    AR_DEBUG2_PRINTF("Waking up the StreamID(%d) write process\n", streamID);
48756 +    wake_up_interruptible(&ar->raw_htc_write_queue[streamID]);
48757 +}
48758 +
48759 +/* connect to a service */
48760 +static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T        *ar,
48761 +                                           HTC_RAW_STREAM_ID StreamID)
48762 +{
48763 +    A_STATUS                 status;
48764 +    HTC_SERVICE_CONNECT_RESP response;
48765 +    A_UINT8                  streamNo;
48766 +    HTC_SERVICE_CONNECT_REQ  connect;
48767 +
48768 +    do {
48769 +
48770 +        A_MEMZERO(&connect,sizeof(connect));
48771 +            /* pass the stream ID as meta data to the RAW streams service */
48772 +        streamNo = (A_UINT8)StreamID;
48773 +        connect.pMetaData = &streamNo;
48774 +        connect.MetaDataLength = sizeof(A_UINT8);
48775 +            /* these fields are the same for all endpoints */
48776 +        connect.EpCallbacks.pContext = ar;
48777 +        connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb;
48778 +        connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb;
48779 +            /* simple interface, we don't need these optional callbacks */
48780 +        connect.EpCallbacks.EpRecvRefill = NULL;
48781 +        connect.EpCallbacks.EpSendFull = NULL;
48782 +        connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM;
48783 +
48784 +            /* connect to the raw streams service, we may be able to get 1 or more
48785 +             * connections, depending on WHAT is running on the target */
48786 +        connect.ServiceID = HTC_RAW_STREAMS_SVC;
48787 +
48788 +        A_MEMZERO(&response,sizeof(response));
48789 +
48790 +            /* try to connect to the raw stream, it is okay if this fails with
48791 +             * status HTC_SERVICE_NO_MORE_EP */
48792 +        status = HTCConnectService(ar->arHtcTarget,
48793 +                                   &connect,
48794 +                                   &response);
48795 +
48796 +        if (A_FAILED(status)) {
48797 +            if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) {
48798 +                AR_DEBUG_PRINTF("HTC RAW , No more streams allowed \n");
48799 +                status = A_OK;
48800 +            }
48801 +            break;
48802 +        }
48803 +
48804 +            /* set endpoint mapping for the RAW HTC streams */
48805 +        arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint);
48806 +
48807 +        AR_DEBUG_PRINTF("HTC RAW : stream ID: %d, endpoint: %d\n",
48808 +                        StreamID, arRawStream2EndpointID(ar,StreamID));
48809 +
48810 +    } while (FALSE);
48811 +
48812 +    return status;
48813 +}
48814 +
48815 +int ar6000_htc_raw_open(AR_SOFTC_T *ar)
48816 +{
48817 +    A_STATUS status;
48818 +    int streamID, endPt, count2;
48819 +    raw_htc_buffer *buffer;
48820 +    HTC_SERVICE_ID servicepriority;
48821 +
48822 +    A_ASSERT(ar->arHtcTarget != NULL);
48823 +
48824 +        /* wait for target */
48825 +    status = HTCWaitTarget(ar->arHtcTarget);
48826 +
48827 +    if (A_FAILED(status)) {
48828 +        AR_DEBUG_PRINTF("HTCWaitTarget failed (%d)\n", status);
48829 +        return -ENODEV;
48830 +    }
48831 +
48832 +    for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) {
48833 +        ar->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED;
48834 +    }
48835 +
48836 +    for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) {
48837 +        /* Initialize the data structures */
48838 +        init_MUTEX(&ar->raw_htc_read_sem[streamID]);
48839 +        init_MUTEX(&ar->raw_htc_write_sem[streamID]);
48840 +        init_waitqueue_head(&ar->raw_htc_read_queue[streamID]);
48841 +        init_waitqueue_head(&ar->raw_htc_write_queue[streamID]);
48842 +
48843 +            /* try to connect to the raw service */
48844 +        status = ar6000_connect_raw_service(ar,streamID);
48845 +
48846 +        if (A_FAILED(status)) {
48847 +            break;
48848 +        }
48849 +
48850 +        if (arRawStream2EndpointID(ar,streamID) == 0) {
48851 +            break;
48852 +        }
48853 +
48854 +        for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) {
48855 +            /* Initialize the receive buffers */
48856 +            buffer = ar->raw_htc_write_buffer[streamID][count2];
48857 +            memset(buffer, 0, sizeof(raw_htc_buffer));
48858 +            buffer = ar->raw_htc_read_buffer[streamID][count2];
48859 +            memset(buffer, 0, sizeof(raw_htc_buffer));
48860 +
48861 +            SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket,
48862 +                                          buffer,
48863 +                                          buffer->data,
48864 +                                          AR6000_BUFFER_SIZE,
48865 +                                          arRawStream2EndpointID(ar,streamID));
48866 +
48867 +            /* Queue buffers to HTC for receive */
48868 +            if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK)
48869 +            {
48870 +                BMIInit();
48871 +                return -EIO;
48872 +            }
48873 +        }
48874 +
48875 +        for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) {
48876 +            /* Initialize the receive buffers */
48877 +            buffer = ar->raw_htc_write_buffer[streamID][count2];
48878 +            memset(buffer, 0, sizeof(raw_htc_buffer));
48879 +        }
48880 +
48881 +        ar->read_buffer_available[streamID] = FALSE;
48882 +        ar->write_buffer_available[streamID] = TRUE;
48883 +    }
48884 +
48885 +    if (A_FAILED(status)) {
48886 +        return -EIO;
48887 +    }
48888 +
48889 +    AR_DEBUG_PRINTF("HTC RAW, number of streams the target supports: %d \n", streamID);
48890 +
48891 +    servicepriority = HTC_RAW_STREAMS_SVC;  /* only 1 */
48892 +
48893 +        /* set callbacks and priority list */
48894 +    HTCSetCreditDistribution(ar->arHtcTarget,
48895 +                             ar,
48896 +                             NULL,  /* use default */
48897 +                             NULL,  /* use default */
48898 +                             &servicepriority,
48899 +                             1);
48900 +
48901 +    /* Start the HTC component */
48902 +    if ((status = HTCStart(ar->arHtcTarget)) != A_OK) {
48903 +        BMIInit();
48904 +        return -EIO;
48905 +    }
48906 +
48907 +    (ar)->arRawIfInit = TRUE;
48908 +
48909 +    return 0;
48910 +}
48911 +
48912 +int ar6000_htc_raw_close(AR_SOFTC_T *ar)
48913 +{
48914 +    A_PRINTF("ar6000_htc_raw_close called \n");
48915 +    HTCStop(ar->arHtcTarget);
48916 +
48917 +        /* reset the device */
48918 +    ar6000_reset_device(ar->arHifDevice, ar->arTargetType);
48919 +    /* Initialize the BMI component */
48920 +    BMIInit();
48921 +
48922 +    return 0;
48923 +}
48924 +
48925 +raw_htc_buffer *
48926 +get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID)
48927 +{
48928 +    int count;
48929 +    raw_htc_buffer *busy;
48930 +
48931 +    /* Check for data */
48932 +    for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) {
48933 +        busy = ar->raw_htc_read_buffer[StreamID][count];
48934 +        if (busy->length) {
48935 +            break;
48936 +        }
48937 +    }
48938 +    if (busy->length) {
48939 +        ar->read_buffer_available[StreamID] = TRUE;
48940 +    } else {
48941 +        ar->read_buffer_available[StreamID] = FALSE;
48942 +    }
48943 +
48944 +    return busy;
48945 +}
48946 +
48947 +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID,
48948 +                            char __user *buffer, size_t length)
48949 +{
48950 +    int readPtr;
48951 +    raw_htc_buffer *busy;
48952 +
48953 +    if (arRawStream2EndpointID(ar,StreamID) == 0) {
48954 +        AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID);
48955 +        return -EFAULT;
48956 +    }
48957 +
48958 +    if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) {
48959 +        return -ERESTARTSYS;
48960 +    }
48961 +
48962 +    busy = get_filled_buffer(ar,StreamID);
48963 +    while (!ar->read_buffer_available[StreamID]) {
48964 +        up(&ar->raw_htc_read_sem[StreamID]);
48965 +
48966 +        /* Wait for the data */
48967 +        AR_DEBUG2_PRINTF("Sleeping StreamID(%d) read process\n", StreamID);
48968 +        if (wait_event_interruptible(ar->raw_htc_read_queue[StreamID],
48969 +                                     ar->read_buffer_available[StreamID]))
48970 +        {
48971 +            return -EINTR;
48972 +        }
48973 +        if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) {
48974 +            return -ERESTARTSYS;
48975 +        }
48976 +        busy = get_filled_buffer(ar,StreamID);
48977 +    }
48978 +
48979 +    /* Read the data */
48980 +    readPtr = busy->currPtr;
48981 +    if (length > busy->length - HTC_HEADER_LEN) {
48982 +        length = busy->length - HTC_HEADER_LEN;
48983 +    }
48984 +    if (copy_to_user(buffer, &busy->data[readPtr], length)) {
48985 +        up(&ar->raw_htc_read_sem[StreamID]);
48986 +        return -EFAULT;
48987 +    }
48988 +
48989 +    busy->currPtr += length;
48990 +
48991 +    //AR_DEBUG_PRINTF("raw read ioctl:  currPTR : 0x%X 0x%X \n", busy->currPtr,busy->length);
48992 +
48993 +    if (busy->currPtr == busy->length)
48994 +    {
48995 +        busy->currPtr = 0;
48996 +        busy->length = 0;
48997 +        HTC_PACKET_RESET_RX(&busy->HTCPacket);
48998 +        //AR_DEBUG_PRINTF("raw read ioctl:  ep for packet:%d \n", busy->HTCPacket.Endpoint);
48999 +        HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket);
49000 +    }
49001 +    ar->read_buffer_available[StreamID] = FALSE;
49002 +    up(&ar->raw_htc_read_sem[StreamID]);
49003 +
49004 +    return length;
49005 +}
49006 +
49007 +static raw_htc_buffer *
49008 +get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID)
49009 +{
49010 +    int count;
49011 +    raw_htc_buffer *free;
49012 +
49013 +    free = NULL;
49014 +    for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) {
49015 +        free = ar->raw_htc_write_buffer[StreamID][count];
49016 +        if (free->length == 0) {
49017 +            break;
49018 +        }
49019 +    }
49020 +    if (!free->length) {
49021 +        ar->write_buffer_available[StreamID] = TRUE;
49022 +    } else {
49023 +        ar->write_buffer_available[StreamID] = FALSE;
49024 +    }
49025 +
49026 +    return free;
49027 +}
49028 +
49029 +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID,
49030 +                     char __user *buffer, size_t length)
49031 +{
49032 +    int writePtr;
49033 +    raw_htc_buffer *free;
49034 +
49035 +    if (arRawStream2EndpointID(ar,StreamID) == 0) {
49036 +        AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID);
49037 +        return -EFAULT;
49038 +    }
49039 +
49040 +    if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) {
49041 +        return -ERESTARTSYS;
49042 +    }
49043 +
49044 +    /* Search for a free buffer */
49045 +    free = get_free_buffer(ar,StreamID);
49046 +
49047 +    /* Check if there is space to write else wait */
49048 +    while (!ar->write_buffer_available[StreamID]) {
49049 +        up(&ar->raw_htc_write_sem[StreamID]);
49050 +
49051 +        /* Wait for buffer to become free */
49052 +        AR_DEBUG2_PRINTF("Sleeping StreamID(%d) write process\n", StreamID);
49053 +        if (wait_event_interruptible(ar->raw_htc_write_queue[StreamID],
49054 +                                     ar->write_buffer_available[StreamID]))
49055 +        {
49056 +            return -EINTR;
49057 +        }
49058 +        if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) {
49059 +            return -ERESTARTSYS;
49060 +        }
49061 +        free = get_free_buffer(ar,StreamID);
49062 +    }
49063 +
49064 +    /* Send the data */
49065 +    writePtr = HTC_HEADER_LEN;
49066 +    if (length > (AR6000_BUFFER_SIZE - HTC_HEADER_LEN)) {
49067 +        length = AR6000_BUFFER_SIZE - HTC_HEADER_LEN;
49068 +    }
49069 +
49070 +    if (copy_from_user(&free->data[writePtr], buffer, length)) {
49071 +        up(&ar->raw_htc_read_sem[StreamID]);
49072 +        return -EFAULT;
49073 +    }
49074 +
49075 +    free->length = length;
49076 +
49077 +    SET_HTC_PACKET_INFO_TX(&free->HTCPacket,
49078 +                           free,
49079 +                           &free->data[writePtr],
49080 +                           length,
49081 +                           arRawStream2EndpointID(ar,StreamID),
49082 +                           AR6K_DATA_PKT_TAG);
49083 +
49084 +    HTCSendPkt(ar->arHtcTarget,&free->HTCPacket);
49085 +
49086 +    ar->write_buffer_available[StreamID] = FALSE;
49087 +    up(&ar->raw_htc_write_sem[StreamID]);
49088 +
49089 +    return length;
49090 +}
49091 +#endif /* HTC_RAW_INTERFACE */
49092 --- /dev/null
49093 +++ b/drivers/ar6000/ar6000/ar6xapi_linux.h
49094 @@ -0,0 +1,128 @@
49095 +#ifndef _AR6XAPI_LINUX_H
49096 +#define _AR6XAPI_LINUX_H
49097 +/*
49098 + *
49099 + * Copyright (c) 2004-2007 Atheros Communications Inc.
49100 + * All rights reserved.
49101 + *
49102 + *
49103 + *  This program is free software; you can redistribute it and/or modify
49104 + *  it under the terms of the GNU General Public License version 2 as
49105 + *  published by the Free Software Foundation;
49106 + *
49107 + *  Software distributed under the License is distributed on an "AS
49108 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
49109 + *  implied. See the License for the specific language governing
49110 + *  rights and limitations under the License.
49111 + *
49112 + *
49113 + *
49114 + */
49115 +
49116 +#ifdef __cplusplus
49117 +extern "C" {
49118 +#endif
49119 +
49120 +struct ar6_softc;
49121 +
49122 +void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap);
49123 +A_UINT8 ar6000_iptos_to_userPriority(A_UINT8 *pkt);
49124 +A_STATUS ar6000_control_tx(void *devt, void *osbuf, WMI_PRI_STREAM_ID streamID);
49125 +void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel,
49126 +                          A_UINT8 *bssid, A_UINT16 listenInterval,
49127 +                          A_UINT16 beaconInterval, NETWORK_TYPE networkType,
49128 +                          A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
49129 +                          A_UINT8 assocRespLen,A_UINT8 *assocInfo);
49130 +void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason,
49131 +                             A_UINT8 *bssid, A_UINT8 assocRespLen,
49132 +                             A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus);
49133 +void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid,
49134 +                              A_BOOL ismcast);
49135 +void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps);
49136 +void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList);
49137 +void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode);
49138 +void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr);
49139 +void ar6000_keepalive_rx(void *devt, A_UINT8 configured);
49140 +void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps,
49141 +                                 WMI_NEIGHBOR_INFO *info);
49142 +void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num);
49143 +void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status);
49144 +void ar6000_targetStats_event(struct ar6_softc *ar,  WMI_TARGET_STATS *pStats);
49145 +void ar6000_rssiThreshold_event(struct ar6_softc *ar,
49146 +                                WMI_RSSI_THRESHOLD_VAL newThreshold,
49147 +                                A_INT16 rssi);
49148 +void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal);
49149 +void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication,
49150 +                                A_UINT8 statusCode, A_UINT8 *tspecSuggestion);
49151 +void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source);
49152 +void
49153 +ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl);
49154 +
49155 +void
49156 +ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p);
49157 +
49158 +void
49159 +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters,
49160 +                      WMI_GET_WOW_LIST_REPLY *wow_reply);
49161 +
49162 +void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID,
49163 +                             WMI_PMKID *pmkidList);
49164 +
49165 +void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values);
49166 +void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value);
49167 +void ar6000_gpio_ack_rx(void);
49168 +
49169 +void ar6000_dbglog_init_done(struct ar6_softc *ar);
49170 +
49171 +#ifdef SEND_EVENT_TO_APP
49172 +void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len);
49173 +#endif
49174 +
49175 +#ifdef CONFIG_HOST_TCMD_SUPPORT
49176 +void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len);
49177 +#endif
49178 +
49179 +void ar6000_tx_retry_err_event(void *devt);
49180 +
49181 +void ar6000_snrThresholdEvent_rx(void *devt,
49182 +                                 WMI_SNR_THRESHOLD_VAL newThreshold,
49183 +                                 A_UINT8 snr);
49184 +
49185 +void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal);
49186 +
49187 +
49188 +void ar6000_ratemask_rx(void *devt, A_UINT16 ratemask);
49189 +
49190 +A_STATUS ar6000_get_driver_cfg(struct net_device *dev,
49191 +                                A_UINT16 cfgParam,
49192 +                                void *result);
49193 +void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len);
49194 +
49195 +void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped,
49196 +                         A_INT8 *buffer, A_UINT32 length);
49197 +
49198 +int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar);
49199 +
49200 +void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active);
49201 +
49202 +void ar6000_dset_open_req(void *devt,
49203 +                          A_UINT32 id,
49204 +                          A_UINT32 targ_handle,
49205 +                          A_UINT32 targ_reply_fn,
49206 +                          A_UINT32 targ_reply_arg);
49207 +void ar6000_dset_close(void *devt, A_UINT32 access_cookie);
49208 +void ar6000_dset_data_req(void *devt,
49209 +                          A_UINT32 access_cookie,
49210 +                          A_UINT32 offset,
49211 +                          A_UINT32 length,
49212 +                          A_UINT32 targ_buf,
49213 +                          A_UINT32 targ_reply_fn,
49214 +                          A_UINT32 targ_reply_arg);
49215 +
49216 +
49217 +
49218 +#ifdef __cplusplus
49219 +}
49220 +#endif
49221 +
49222 +#endif
49223 --- /dev/null
49224 +++ b/drivers/ar6000/ar6000/athdrv_linux.h
49225 @@ -0,0 +1,993 @@
49226 +/*
49227 + * Copyright (c) 2004-2006 Atheros Communications Inc.
49228 + * All rights reserved.
49229 + *
49230 + *
49231 + *
49232 + *  This program is free software; you can redistribute it and/or modify
49233 + *  it under the terms of the GNU General Public License version 2 as
49234 + *  published by the Free Software Foundation;
49235 + *
49236 + *  Software distributed under the License is distributed on an "AS
49237 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
49238 + *  implied. See the License for the specific language governing
49239 + *  rights and limitations under the License.
49240 + *
49241 + *
49242 + *
49243 + */
49244 +
49245 +#ifndef _ATHDRV_LINUX_H
49246 +#define _ATHDRV_LINUX_H
49247 +
49248 +#ifdef __cplusplus
49249 +extern "C" {
49250 +#endif
49251 +
49252 +
49253 +/*
49254 + * There are two types of ioctl's here: Standard ioctls and
49255 + * eXtended ioctls.  All extended ioctls (XIOCTL) are multiplexed
49256 + * off of the single ioctl command, AR6000_IOCTL_EXTENDED.  The
49257 + * arguments for every XIOCTL starts with a 32-bit command word
49258 + * that is used to select which extended ioctl is in use.  After
49259 + * the command word are command-specific arguments.
49260 + */
49261 +
49262 +/* Linux standard Wireless Extensions, private ioctl interfaces */
49263 +#define IEEE80211_IOCTL_SETPARAM             (SIOCIWFIRSTPRIV+0)
49264 +#define IEEE80211_IOCTL_GETPARAM             (SIOCIWFIRSTPRIV+1)
49265 +#define IEEE80211_IOCTL_SETKEY               (SIOCIWFIRSTPRIV+2)
49266 +#define IEEE80211_IOCTL_SETWMMPARAMS         (SIOCIWFIRSTPRIV+3)
49267 +#define IEEE80211_IOCTL_DELKEY               (SIOCIWFIRSTPRIV+4)
49268 +#define IEEE80211_IOCTL_GETWMMPARAMS         (SIOCIWFIRSTPRIV+5)
49269 +#define IEEE80211_IOCTL_SETOPTIE             (SIOCIWFIRSTPRIV+6)
49270 +#define IEEE80211_IOCTL_SETMLME              (SIOCIWFIRSTPRIV+7)
49271 +//#define IEEE80211_IOCTL_GETOPTIE             (SIOCIWFIRSTPRIV+7)
49272 +#define IEEE80211_IOCTL_ADDPMKID             (SIOCIWFIRSTPRIV+8)
49273 +//#define IEEE80211_IOCTL_SETAUTHALG           (SIOCIWFIRSTPRIV+10)
49274 +#define IEEE80211_IOCTL_LASTONE              (SIOCIWFIRSTPRIV+9)
49275 +
49276 +
49277 +
49278 +/*                      ====WMI Ioctls====                                    */
49279 +/*
49280 + *
49281 + * Many ioctls simply provide WMI services to application code:
49282 + * an application makes such an ioctl call with a set of arguments
49283 + * that are packaged into the corresponding WMI message, and sent
49284 + * to the Target.
49285 + */
49286 +
49287 +#define AR6000_IOCTL_WMI_GETREV              (SIOCIWFIRSTPRIV+10)
49288 +/*
49289 + * arguments:
49290 + *   ar6000_version *revision
49291 + */
49292 +
49293 +#define AR6000_IOCTL_WMI_SETPWR              (SIOCIWFIRSTPRIV+11)
49294 +/*
49295 + * arguments:
49296 + *   WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h)
49297 + * uses: WMI_SET_POWER_MODE_CMDID
49298 + */
49299 +
49300 +#define AR6000_IOCTL_WMI_SETSCAN             (SIOCIWFIRSTPRIV+12)
49301 +/*
49302 + * arguments:
49303 + *   WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h)
49304 + * uses: WMI_SET_SCAN_PARAMS_CMDID
49305 + */
49306 +
49307 +#define AR6000_IOCTL_WMI_SETLISTENINT        (SIOCIWFIRSTPRIV+13)
49308 +/*
49309 + * arguments:
49310 + *   UINT32 listenInterval
49311 + * uses: WMI_SET_LISTEN_INT_CMDID
49312 + */
49313 +
49314 +#define AR6000_IOCTL_WMI_SETBSSFILTER        (SIOCIWFIRSTPRIV+14)
49315 +/*
49316 + * arguments:
49317 + *   WMI_BSS_FILTER filter (see include/wmi.h)
49318 + * uses: WMI_SET_BSS_FILTER_CMDID
49319 + */
49320 +
49321 +#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS   (SIOCIWFIRSTPRIV+16)
49322 +/*
49323 + * arguments:
49324 + *   WMI_CHANNEL_PARAMS_CMD chParams
49325 + * uses: WMI_SET_CHANNEL_PARAMS_CMDID
49326 + */
49327 +
49328 +#define AR6000_IOCTL_WMI_SET_PROBEDSSID      (SIOCIWFIRSTPRIV+17)
49329 +/*
49330 + * arguments:
49331 + *   WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h)
49332 + * uses: WMI_SETPROBED_SSID_CMDID
49333 + */
49334 +
49335 +#define AR6000_IOCTL_WMI_SET_PMPARAMS        (SIOCIWFIRSTPRIV+18)
49336 +/*
49337 + * arguments:
49338 + *   WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h)
49339 + * uses: WMI_SET_POWER_PARAMS_CMDID
49340 + */
49341 +
49342 +#define AR6000_IOCTL_WMI_SET_BADAP           (SIOCIWFIRSTPRIV+19)
49343 +/*
49344 + * arguments:
49345 + *   WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h)
49346 + * uses: WMI_ADD_BAD_AP_CMDID
49347 + */
49348 +
49349 +#define AR6000_IOCTL_WMI_GET_QOS_QUEUE       (SIOCIWFIRSTPRIV+20)
49350 +/*
49351 + * arguments:
49352 + *   ar6000_queuereq queueRequest (see below)
49353 + */
49354 +
49355 +#define AR6000_IOCTL_WMI_CREATE_QOS          (SIOCIWFIRSTPRIV+21)
49356 +/*
49357 + * arguments:
49358 + *   WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h)
49359 + * uses: WMI_CREATE_PSTREAM_CMDID
49360 + */
49361 +
49362 +#define AR6000_IOCTL_WMI_DELETE_QOS          (SIOCIWFIRSTPRIV+22)
49363 +/*
49364 + * arguments:
49365 + *   WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h)
49366 + * uses: WMI_DELETE_PSTREAM_CMDID
49367 + */
49368 +
49369 +#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD   (SIOCIWFIRSTPRIV+23)
49370 +/*
49371 + * arguments:
49372 + *   WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
49373 + * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID
49374 + */
49375 +
49376 +#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)
49377 +/*
49378 + * arguments:
49379 + *   WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h)
49380 + * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
49381 + */
49382 +
49383 +#define AR6000_IOCTL_WMI_GET_TARGET_STATS    (SIOCIWFIRSTPRIV+25)
49384 +/*
49385 + * arguments:
49386 + *   TARGET_STATS *targetStats (see below)
49387 + * uses: WMI_GET_STATISTICS_CMDID
49388 + */
49389 +
49390 +#define AR6000_IOCTL_WMI_SET_ASSOC_INFO      (SIOCIWFIRSTPRIV+26)
49391 +/*
49392 + * arguments:
49393 + *   WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd
49394 + * uses: WMI_SET_ASSOC_INFO_CMDID
49395 + */
49396 +
49397 +#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS   (SIOCIWFIRSTPRIV+27)
49398 +/*
49399 + * arguments:
49400 + *   WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h)
49401 + * uses: WMI_SET_ACCESS_PARAMS_CMDID
49402 + */
49403 +
49404 +#define AR6000_IOCTL_WMI_SET_BMISS_TIME      (SIOCIWFIRSTPRIV+28)
49405 +/*
49406 + * arguments:
49407 + *   UINT32 beaconMissTime
49408 + * uses: WMI_SET_BMISS_TIME_CMDID
49409 + */
49410 +
49411 +#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT    (SIOCIWFIRSTPRIV+29)
49412 +/*
49413 + * arguments:
49414 + *   WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h)
49415 + * uses: WMI_SET_DISC_TIMEOUT_CMDID
49416 + */
49417 +
49418 +#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS    (SIOCIWFIRSTPRIV+30)
49419 +/*
49420 + * arguments:
49421 + *   WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd
49422 + * uses: WMI_SET_IBSS_PM_CAPS_CMDID
49423 + */
49424 +
49425 +/*
49426 + * There is a very small space available for driver-private
49427 + * wireless ioctls.  In order to circumvent this limitation,
49428 + * we multiplex a bunch of ioctls (XIOCTLs) on top of a
49429 + * single AR6000_IOCTL_EXTENDED ioctl.
49430 + */
49431 +#define AR6000_IOCTL_EXTENDED                (SIOCIWFIRSTPRIV+31)
49432 +
49433 +
49434 +/*                         ====BMI Extended Ioctls====                        */
49435 +
49436 +#define AR6000_XIOCTL_BMI_DONE                                  1
49437 +/*
49438 + * arguments:
49439 + *   UINT32 cmd (AR6000_XIOCTL_BMI_DONE)
49440 + * uses: BMI_DONE
49441 + */
49442 +
49443 +#define AR6000_XIOCTL_BMI_READ_MEMORY                           2
49444 +/*
49445 + * arguments:
49446 + *   union {
49447 + *     struct {
49448 + *       UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY)
49449 + *       UINT32 address
49450 + *       UINT32 length
49451 + *     }
49452 + *     char results[length]
49453 + *   }
49454 + * uses: BMI_READ_MEMORY
49455 + */
49456 +
49457 +#define AR6000_XIOCTL_BMI_WRITE_MEMORY                          3
49458 +/*
49459 + * arguments:
49460 + *   UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY)
49461 + *   UINT32 address
49462 + *   UINT32 length
49463 + *   char data[length]
49464 + * uses: BMI_WRITE_MEMORY
49465 + */
49466 +
49467 +#define AR6000_XIOCTL_BMI_EXECUTE                               4
49468 +/*
49469 + * arguments:
49470 + *   UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE)
49471 + *   UINT32 TargetAddress
49472 + *   UINT32 parameter
49473 + * uses: BMI_EXECUTE
49474 + */
49475 +
49476 +#define AR6000_XIOCTL_BMI_SET_APP_START                         5
49477 +/*
49478 + * arguments:
49479 + *   UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START)
49480 + *   UINT32 TargetAddress
49481 + * uses: BMI_SET_APP_START
49482 + */
49483 +
49484 +#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER                     6
49485 +/*
49486 + * arguments:
49487 + *   union {
49488 + *     struct {
49489 + *       UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER)
49490 + *       UINT32 TargetAddress, 32-bit aligned
49491 + *     }
49492 + *     UINT32 result
49493 + *   }
49494 + * uses: BMI_READ_SOC_REGISTER
49495 + */
49496 +
49497 +#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER                    7
49498 +/*
49499 + * arguments:
49500 + *     struct {
49501 + *       UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER)
49502 + *       UINT32 TargetAddress, 32-bit aligned
49503 + *       UINT32 newValue
49504 + *     }
49505 + * uses: BMI_WRITE_SOC_REGISTER
49506 + */
49507 +
49508 +#define AR6000_XIOCTL_BMI_TEST                                  8
49509 +/*
49510 + * arguments:
49511 + *   UINT32 cmd (AR6000_XIOCTL_BMI_TEST)
49512 + *   UINT32 address
49513 + *   UINT32 length
49514 + *   UINT32 count
49515 + */
49516 +
49517 +
49518 +
49519 +/* Historical Host-side DataSet support */
49520 +#define AR6000_XIOCTL_UNUSED9                                   9
49521 +#define AR6000_XIOCTL_UNUSED10                                  10
49522 +#define AR6000_XIOCTL_UNUSED11                                  11
49523 +
49524 +/*                      ====Misc Extended Ioctls====                          */
49525 +
49526 +#define AR6000_XIOCTL_FORCE_TARGET_RESET                        12
49527 +/*
49528 + * arguments:
49529 + *   UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET)
49530 + */
49531 +
49532 +
49533 +#ifdef HTC_RAW_INTERFACE
49534 +/* HTC Raw Interface Ioctls */
49535 +#define AR6000_XIOCTL_HTC_RAW_OPEN                              13
49536 +/*
49537 + * arguments:
49538 + *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN)
49539 + */
49540 +
49541 +#define AR6000_XIOCTL_HTC_RAW_CLOSE                             14
49542 +/*
49543 + * arguments:
49544 + *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE)
49545 + */
49546 +
49547 +#define AR6000_XIOCTL_HTC_RAW_READ                              15
49548 +/*
49549 + * arguments:
49550 + *   union {
49551 + *     struct {
49552 + *       UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ)
49553 + *       UINT32 mailboxID
49554 + *       UINT32 length
49555 + *     }
49556 + *     results[length]
49557 + *   }
49558 + */
49559 +
49560 +#define AR6000_XIOCTL_HTC_RAW_WRITE                             16
49561 +/*
49562 + * arguments:
49563 + *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE)
49564 + *   UINT32 mailboxID
49565 + *   UINT32 length
49566 + *   char buffer[length]
49567 + */
49568 +#endif /* HTC_RAW_INTERFACE */
49569 +
49570 +#define AR6000_XIOCTL_CHECK_TARGET_READY                        17
49571 +/*
49572 + * arguments:
49573 + *   UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY)
49574 + */
49575 +
49576 +
49577 +
49578 +/*                ====GPIO (General Purpose I/O) Extended Ioctls====          */
49579 +
49580 +#define AR6000_XIOCTL_GPIO_OUTPUT_SET                           18
49581 +/*
49582 + * arguments:
49583 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET)
49584 + *   ar6000_gpio_output_set_cmd_s (see below)
49585 + * uses: WMIX_GPIO_OUTPUT_SET_CMDID
49586 + */
49587 +
49588 +#define AR6000_XIOCTL_GPIO_INPUT_GET                            19
49589 +/*
49590 + * arguments:
49591 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET)
49592 + * uses: WMIX_GPIO_INPUT_GET_CMDID
49593 + */
49594 +
49595 +#define AR6000_XIOCTL_GPIO_REGISTER_SET                         20
49596 +/*
49597 + * arguments:
49598 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET)
49599 + *   ar6000_gpio_register_cmd_s (see below)
49600 + * uses: WMIX_GPIO_REGISTER_SET_CMDID
49601 + */
49602 +
49603 +#define AR6000_XIOCTL_GPIO_REGISTER_GET                         21
49604 +/*
49605 + * arguments:
49606 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET)
49607 + *   ar6000_gpio_register_cmd_s (see below)
49608 + * uses: WMIX_GPIO_REGISTER_GET_CMDID
49609 + */
49610 +
49611 +#define AR6000_XIOCTL_GPIO_INTR_ACK                             22
49612 +/*
49613 + * arguments:
49614 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK)
49615 + *   ar6000_cpio_intr_ack_cmd_s (see below)
49616 + * uses: WMIX_GPIO_INTR_ACK_CMDID
49617 + */
49618 +
49619 +#define AR6000_XIOCTL_GPIO_INTR_WAIT                            23
49620 +/*
49621 + * arguments:
49622 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT)
49623 + */
49624 +
49625 +
49626 +
49627 +/*                    ====more wireless commands====                          */
49628 +
49629 +#define AR6000_XIOCTL_SET_ADHOC_BSSID                           24
49630 +/*
49631 + * arguments:
49632 + *   UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID)
49633 + *   WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h)
49634 + */
49635 +
49636 +#define AR6000_XIOCTL_SET_OPT_MODE                              25
49637 +/*
49638 + * arguments:
49639 + *   UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE)
49640 + *   WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h)
49641 + * uses: WMI_SET_OPT_MODE_CMDID
49642 + */
49643 +
49644 +#define AR6000_XIOCTL_OPT_SEND_FRAME                            26
49645 +/*
49646 + * arguments:
49647 + *   UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME)
49648 + *   WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h)
49649 + * uses: WMI_OPT_TX_FRAME_CMDID
49650 + */
49651 +
49652 +#define AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL                   27
49653 +/*
49654 + * arguments:
49655 + *   UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL)
49656 + *   WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h)
49657 + * uses: WMI_SET_BEACON_INT_CMDID
49658 + */
49659 +
49660 +
49661 +#define IEEE80211_IOCTL_SETAUTHALG                              28
49662 +
49663 +
49664 +#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE                        29
49665 +/*
49666 + * arguments:
49667 + *   UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE)
49668 + *   WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h)
49669 + * uses: WMI_SET_VOICE_PKT_SIZE_CMDID
49670 + */
49671 +
49672 +
49673 +#define AR6000_XIOCTL_SET_MAX_SP                                30
49674 +/*
49675 + * arguments:
49676 + *   UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP)
49677 + *   WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h)
49678 + * uses: WMI_SET_MAX_SP_LEN_CMDID
49679 + */
49680 +
49681 +#define AR6000_XIOCTL_WMI_GET_ROAM_TBL                          31
49682 +
49683 +#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL                         32
49684 +
49685 +#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS                 33
49686 +
49687 +
49688 +/*
49689 + * arguments:
49690 + *   UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS)
49691 + *   WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h)
49692 + *   WMI_SET_POWERSAVE_TIMERS_CMDID
49693 + */
49694 +
49695 +#define AR6000_XIOCTRL_WMI_GET_POWER_MODE                        34
49696 +/*
49697 + * arguments:
49698 + *   UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE)
49699 + */
49700 +
49701 +#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE                       35
49702 +typedef enum {
49703 +    WLAN_DISABLED,
49704 +    WLAN_ENABLED
49705 +} AR6000_WLAN_STATE;
49706 +/*
49707 + * arguments:
49708 + * enable/disable
49709 + */
49710 +
49711 +#define AR6000_XIOCTL_WMI_GET_ROAM_DATA                         36
49712 +
49713 +#define AR6000_XIOCTL_WMI_SETRETRYLIMITS                37
49714 +/*
49715 + * arguments:
49716 + *   WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd
49717 + * uses: WMI_SET_RETRY_LIMITS_CMDID
49718 + */
49719 +
49720 +#ifdef CONFIG_HOST_TCMD_SUPPORT
49721 +/*       ====extended commands for radio test ====                          */
49722 +
49723 +#define AR6000_XIOCTL_TCMD_CONT_TX                      38
49724 +/*
49725 + * arguments:
49726 + *   UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX)
49727 + *   WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h)
49728 + * uses: WMI_TCMD_CONT_TX_CMDID
49729 + */
49730 +
49731 +#define AR6000_XIOCTL_TCMD_CONT_RX                      39
49732 +/*
49733 + * arguments:
49734 + *   UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX)
49735 + *   WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h)
49736 + * uses: WMI_TCMD_CONT_RX_CMDID
49737 + */
49738 +
49739 +#define AR6000_XIOCTL_TCMD_PM                           40
49740 +/*
49741 + * arguments:
49742 + *   UINT32 cmd (AR6000_XIOCTL_TCMD_PM)
49743 + *   WMI_TCMD_PM_CMD pmCmd (see include/wmi.h)
49744 + * uses: WMI_TCMD_PM_CMDID
49745 + */
49746 +
49747 +#endif /* CONFIG_HOST_TCMD_SUPPORT */
49748 +
49749 +#define AR6000_XIOCTL_WMI_STARTSCAN                     41
49750 +/*
49751 + * arguments:
49752 + *   UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN)
49753 + *   UINT8  scanType
49754 + *   UINT8  scanConnected
49755 + *   A_BOOL forceFgScan
49756 + * uses: WMI_START_SCAN_CMDID
49757 + */
49758 +
49759 +#define AR6000_XIOCTL_WMI_SETFIXRATES                   42
49760 +
49761 +#define AR6000_XIOCTL_WMI_GETFIXRATES                   43
49762 +
49763 +
49764 +#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD             44
49765 +/*
49766 + * arguments:
49767 + *   WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
49768 + * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID
49769 + */
49770 +
49771 +#define AR6000_XIOCTL_WMI_CLR_RSSISNR                   45
49772 +/*
49773 + * arguments:
49774 + *   WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h)
49775 + * uses: WMI_CLR_RSSISNR_CMDID
49776 + */
49777 +
49778 +#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD               46
49779 +/*
49780 + * arguments:
49781 + *   WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
49782 + * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID
49783 + */
49784 +
49785 +#define AR6000_XIOCTL_WMI_SET_RTS                        47
49786 +/*
49787 + * arguments:
49788 + *   WMI_SET_RTS_MODE_CMD (see include/wmi.h)
49789 + * uses: WMI_SET_RTS_MODE_CMDID
49790 + */
49791 +
49792 +#define AR6000_XIOCTL_WMI_SET_LPREAMBLE                 48
49793 +
49794 +#define AR6000_XIOCTL_WMI_SET_AUTHMODE                  49
49795 +/*
49796 + * arguments:
49797 + *   UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE)
49798 + *   UINT8  mode
49799 + * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID
49800 + */
49801 +
49802 +#define AR6000_XIOCTL_WMI_SET_REASSOCMODE               50
49803 +
49804 +/*
49805 + * arguments:
49806 + *   UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM)
49807 + *   UINT8  mode
49808 + * uses: WMI_SET_WMM_CMDID
49809 + */
49810 +#define AR6000_XIOCTL_WMI_SET_WMM                       51
49811 +
49812 +/*
49813 + * arguments:
49814 + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS)
49815 + * UINT32 frequency
49816 + * UINT8  threshold
49817 + */
49818 +#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS  52
49819 +
49820 +/*
49821 + * arguments:
49822 + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP)
49823 + * UINT32 cookie
49824 + */
49825 +#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP         53
49826 +
49827 +/*
49828 + * arguments:
49829 + *   UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD)
49830 + *   UINT32 regDomain
49831 + */
49832 +#define AR6000_XIOCTL_WMI_GET_RD                        54
49833 +
49834 +#define AR6000_XIOCTL_DIAG_READ                         55
49835 +
49836 +#define AR6000_XIOCTL_DIAG_WRITE                        56
49837 +
49838 +/*
49839 + * arguments cmd (AR6000_XIOCTL_SET_TXOP)
49840 + * WMI_TXOP_CFG  txopEnable
49841 + */
49842 +#define AR6000_XIOCTL_WMI_SET_TXOP                      57
49843 +
49844 +#ifdef USER_KEYS
49845 +/*
49846 + * arguments:
49847 + * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS)
49848 + * UINT32 keyOpCtrl
49849 + * uses AR6000_USER_SETKEYS_INFO
49850 + */
49851 +#define AR6000_XIOCTL_USER_SETKEYS                      58
49852 +#endif /* USER_KEYS */
49853 +
49854 +#define AR6000_XIOCTL_WMI_SET_KEEPALIVE                 59
49855 +/*
49856 + * arguments:
49857 + *   UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE)
49858 + *   UINT8 keepaliveInterval
49859 + * uses: WMI_SET_KEEPALIVE_CMDID
49860 + */
49861 +
49862 +#define AR6000_XIOCTL_WMI_GET_KEEPALIVE                 60
49863 +/*
49864 + * arguments:
49865 + *   UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE)
49866 + *   UINT8 keepaliveInterval
49867 + *   A_BOOL configured
49868 + * uses: WMI_GET_KEEPALIVE_CMDID
49869 + */
49870 +
49871 +/*               ====ROM Patching Extended Ioctls====                       */
49872 +
49873 +#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL              61
49874 +/*
49875 + * arguments:
49876 + *     union {
49877 + *       struct {
49878 + *         UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL)
49879 + *         UINT32 ROM Address
49880 + *         UINT32 RAM Address
49881 + *         UINT32 number of bytes
49882 + *         UINT32 activate? (0 or 1)
49883 + *       }
49884 + *       A_UINT32 resulting rompatch ID
49885 + *     }
49886 + * uses: BMI_ROMPATCH_INSTALL
49887 + */
49888 +
49889 +#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL            62
49890 +/*
49891 + * arguments:
49892 + *     struct {
49893 + *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL)
49894 + *       UINT32 rompatch ID
49895 + *     }
49896 + * uses: BMI_ROMPATCH_UNINSTALL
49897 + */
49898 +
49899 +#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE             63
49900 +/*
49901 + * arguments:
49902 + *     struct {
49903 + *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE)
49904 + *       UINT32 rompatch count
49905 + *       UINT32 rompatch IDs[rompatch count]
49906 + *     }
49907 + * uses: BMI_ROMPATCH_ACTIVATE
49908 + */
49909 +
49910 +#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE           64
49911 +/*
49912 + * arguments:
49913 + *     struct {
49914 + *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE)
49915 + *       UINT32 rompatch count
49916 + *       UINT32 rompatch IDs[rompatch count]
49917 + *     }
49918 + * uses: BMI_ROMPATCH_DEACTIVATE
49919 + */
49920 +
49921 +#define AR6000_XIOCTL_WMI_SET_APPIE             65
49922 +/*
49923 + * arguments:
49924 + *      struct {
49925 + *          UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE)
49926 + *          UINT32  app_frmtype;
49927 + *          UINT32  app_buflen;
49928 + *          UINT8   app_buf[];
49929 + *      }
49930 + */
49931 +#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER    66
49932 +/*
49933 + * arguments:
49934 + *      A_UINT32 filter_type;
49935 + */
49936 +
49937 +#define AR6000_XIOCTL_DBGLOG_CFG_MODULE             67
49938 +
49939 +#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS         68
49940 +
49941 +#define AR6000_XIOCTL_WMI_SET_WSC_STATUS               70
49942 +/*
49943 + * arguments:
49944 + *      A_UINT32 wsc_status;
49945 + *            (WSC_REG_INACTIVE or WSC_REG_ACTIVE)
49946 + */
49947 +
49948 +/*
49949 + * arguments:
49950 + *      struct {
49951 + *          A_UINT8 streamType;
49952 + *          A_UINT8 status;
49953 + *      }
49954 + * uses: WMI_SET_BT_STATUS_CMDID
49955 + */
49956 +#define AR6000_XIOCTL_WMI_SET_BT_STATUS             71
49957 +
49958 +/*
49959 + * arguments:
49960 + *      struct {
49961 + *           A_UINT8 paramType;
49962 + *           union {
49963 + *               A_UINT8 noSCOPkts;
49964 + *               BT_PARAMS_A2DP a2dpParams;
49965 + *               BT_COEX_REGS regs;
49966 + *           };
49967 + *      }
49968 + * uses: WMI_SET_BT_PARAM_CMDID
49969 + */
49970 +#define AR6000_XIOCTL_WMI_SET_BT_PARAMS             72
49971 +
49972 +#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE       73
49973 +#define AR6000_XIOCTL_WMI_SET_WOW_MODE              74
49974 +#define AR6000_XIOCTL_WMI_GET_WOW_LIST              75
49975 +#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN           76
49976 +#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN           77
49977 +
49978 +
49979 +
49980 +#define AR6000_XIOCTL_TARGET_INFO                   78
49981 +/*
49982 + * arguments:
49983 + *   UINT32 cmd (AR6000_XIOCTL_TARGET_INFO)
49984 + *   A_UINT32 TargetVersion (returned)
49985 + *   A_UINT32 TargetType    (returned)
49986 + * (See also bmi_msg.h target_ver and target_type)
49987 + */
49988 +
49989 +#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE         79
49990 +/*
49991 + * arguments:
49992 + *      none
49993 + */
49994 +
49995 +#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE       80
49996 +/*
49997 + * This ioctl is used to emulate traffic activity
49998 + * timeouts.  Activity/inactivity will trigger the driver
49999 + * to re-balance credits.
50000 + *
50001 + * arguments:
50002 + *      ar6000_traffic_activity_change
50003 + */
50004 +
50005 +#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS    81
50006 +/*
50007 + * This ioctl is used to set the connect control flags
50008 + *
50009 + * arguments:
50010 + *      A_UINT32 connectCtrlFlags
50011 + */
50012 +
50013 +#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS              82
50014 +/*
50015 + * This IOCTL sets any Authentication,Key Management and Protection
50016 + * related parameters. This is used along with the information set in
50017 + * Connect Command.
50018 + * Currently this enables Multiple PMKIDs to an AP.
50019 + *
50020 + * arguments:
50021 + *      struct {
50022 + *          A_UINT32    akmpInfo;
50023 + *      }
50024 + * uses: WMI_SET_AKMP_PARAMS_CMD
50025 + */
50026 +
50027 +#define AR6000_XIOCTL_WMI_GET_PMKID_LIST            83
50028 +
50029 +#define AR6000_XIOCTL_WMI_SET_PMKID_LIST            84
50030 +/*
50031 + * This IOCTL is used to set a list of PMKIDs. This list of
50032 + * PMKIDs is used in the [Re]AssocReq Frame. This list is used
50033 + * only if the MultiPMKID option is enabled via the
50034 + * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS  IOCTL.
50035 + *
50036 + * arguments:
50037 + *      struct {
50038 + *          A_UINT32    numPMKID;
50039 + *          WMI_PMKID   pmkidList[WMI_MAX_PMKID_CACHE];
50040 + *      }
50041 + * uses: WMI_SET_PMKIDLIST_CMD
50042 + */
50043 +
50044 +/* Historical DSETPATCH support for INI patches */
50045 +#define AR6000_XIOCTL_UNUSED90                      90
50046 +
50047 +
50048 +
50049 +/* used by AR6000_IOCTL_WMI_GETREV */
50050 +struct ar6000_version {
50051 +    A_UINT32        host_ver;
50052 +    A_UINT32        target_ver;
50053 +};
50054 +
50055 +/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */
50056 +struct ar6000_queuereq {
50057 +    A_UINT8         trafficClass;
50058 +    A_UINT16        activeTsids;
50059 +};
50060 +
50061 +/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */
50062 +typedef struct targetStats_t {
50063 +    A_UINT64    tx_packets;
50064 +    A_UINT64    tx_bytes;
50065 +    A_UINT64    tx_unicast_pkts;
50066 +    A_UINT64    tx_unicast_bytes;
50067 +    A_UINT64    tx_multicast_pkts;
50068 +    A_UINT64    tx_multicast_bytes;
50069 +    A_UINT64    tx_broadcast_pkts;
50070 +    A_UINT64    tx_broadcast_bytes;
50071 +    A_UINT64    tx_rts_success_cnt;
50072 +    A_UINT64    tx_packet_per_ac[4];
50073 +
50074 +    A_UINT64    tx_errors;
50075 +    A_UINT64    tx_failed_cnt;
50076 +    A_UINT64    tx_retry_cnt;
50077 +    A_UINT64    tx_rts_fail_cnt;
50078 +    A_INT32     tx_unicast_rate;
50079 +    A_UINT64    rx_packets;
50080 +    A_UINT64    rx_bytes;
50081 +    A_UINT64    rx_unicast_pkts;
50082 +    A_UINT64    rx_unicast_bytes;
50083 +    A_UINT64    rx_multicast_pkts;
50084 +    A_UINT64    rx_multicast_bytes;
50085 +    A_UINT64    rx_broadcast_pkts;
50086 +    A_UINT64    rx_broadcast_bytes;
50087 +    A_UINT64    rx_fragment_pkt;
50088 +
50089 +    A_UINT64    rx_errors;
50090 +    A_UINT64    rx_crcerr;
50091 +    A_UINT64    rx_key_cache_miss;
50092 +    A_UINT64    rx_decrypt_err;
50093 +    A_UINT64    rx_duplicate_frames;
50094 +    A_INT32     rx_unicast_rate;
50095 +
50096 +    A_UINT64    tkip_local_mic_failure;
50097 +    A_UINT64    tkip_counter_measures_invoked;
50098 +    A_UINT64    tkip_replays;
50099 +    A_UINT64    tkip_format_errors;
50100 +    A_UINT64    ccmp_format_errors;
50101 +    A_UINT64    ccmp_replays;
50102 +
50103 +    A_UINT64    power_save_failure_cnt;
50104 +    A_INT16     noise_floor_calibation;
50105 +
50106 +    A_UINT64    cs_bmiss_cnt;
50107 +    A_UINT64    cs_lowRssi_cnt;
50108 +    A_UINT64    cs_connect_cnt;
50109 +    A_UINT64    cs_disconnect_cnt;
50110 +    A_UINT8     cs_aveBeacon_snr;
50111 +    A_INT16     cs_aveBeacon_rssi;
50112 +    A_UINT8     cs_lastRoam_msec;
50113 +    A_UINT8     cs_snr;
50114 +    A_INT16     cs_rssi;
50115 +
50116 +    A_UINT32    lq_val;
50117 +
50118 +    A_UINT32    wow_num_pkts_dropped;
50119 +    A_UINT8     wow_num_host_pkt_wakeups;
50120 +    A_UINT8     wow_num_host_event_wakeups;
50121 +    A_UINT16    wow_num_events_discarded;
50122 +
50123 +}TARGET_STATS;
50124 +
50125 +typedef struct targetStats_cmd_t {
50126 +    TARGET_STATS targetStats;
50127 +    int clearStats;
50128 +} TARGET_STATS_CMD;
50129 +
50130 +/* used by AR6000_XIOCTL_USER_SETKEYS */
50131 +
50132 +/*
50133 + * Setting this bit to 1 doesnot initialize the RSC on the firmware
50134 + */
50135 +#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL    1
50136 +#define AR6000_USER_SETKEYS_RSC_UNCHANGED     0x00000002
50137 +
50138 +typedef struct {
50139 +    A_UINT32  keyOpCtrl;  /* Bit Map of Key Mgmt Ctrl Flags */
50140 +} AR6000_USER_SETKEYS_INFO;
50141 +
50142 +
50143 +/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */
50144 +struct ar6000_gpio_output_set_cmd_s {
50145 +    A_UINT32 set_mask;
50146 +    A_UINT32 clear_mask;
50147 +    A_UINT32 enable_mask;
50148 +    A_UINT32 disable_mask;
50149 +};
50150 +
50151 +/*
50152 + * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET
50153 + */
50154 +struct ar6000_gpio_register_cmd_s {
50155 +    A_UINT32 gpioreg_id;
50156 +    A_UINT32 value;
50157 +};
50158 +
50159 +/* used by AR6000_XIOCTL_GPIO_INTR_ACK */
50160 +struct ar6000_gpio_intr_ack_cmd_s {
50161 +    A_UINT32 ack_mask;
50162 +};
50163 +
50164 +/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */
50165 +struct ar6000_gpio_intr_wait_cmd_s {
50166 +    A_UINT32 intr_mask;
50167 +    A_UINT32 input_values;
50168 +};
50169 +
50170 +/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */
50171 +typedef struct ar6000_dbglog_module_config_s {
50172 +    A_UINT32 valid;
50173 +    A_UINT16 mmask;
50174 +    A_UINT16 tsr;
50175 +    A_BOOL   rep;
50176 +    A_UINT16 size;
50177 +} DBGLOG_MODULE_CONFIG;
50178 +
50179 +typedef struct user_rssi_thold_t {
50180 +    A_INT16     tag;
50181 +    A_INT16     rssi;
50182 +} USER_RSSI_THOLD;
50183 +
50184 +typedef struct user_rssi_params_t {
50185 +    A_UINT8            weight;
50186 +    A_UINT32           pollTime;
50187 +    USER_RSSI_THOLD    tholds[12];
50188 +} USER_RSSI_PARAMS;
50189 +
50190 +/*
50191 + * Host driver may have some config parameters. Typically, these
50192 + * config params are one time config parameters. These could
50193 + * correspond to any of the underlying modules. Host driver exposes
50194 + * an api for the underlying modules to get this config.
50195 + */
50196 +#define AR6000_DRIVER_CFG_BASE                  0x8000
50197 +
50198 +/* Should driver perform wlan node caching? */
50199 +#define AR6000_DRIVER_CFG_GET_WLANNODECACHING   0x8001
50200 +/*Should we log raw WMI msgs */
50201 +#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS      0x8002
50202 +
50203 +/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */
50204 +struct ar6000_diag_window_cmd_s {
50205 +    unsigned int addr;
50206 +    unsigned int value;
50207 +};
50208 +
50209 +
50210 +struct ar6000_traffic_activity_change {
50211 +    A_UINT32    StreamID;   /* stream ID to indicate activity change */
50212 +    A_UINT32    Active;     /* active (1) or inactive (0) */
50213 +};
50214 +
50215 +#ifdef __cplusplus
50216 +}
50217 +#endif
50218 +#endif
50219 --- /dev/null
50220 +++ b/drivers/ar6000/ar6000/athtypes_linux.h
50221 @@ -0,0 +1,47 @@
50222 +/*
50223 + * $Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/include/athtypes_linux.h#1 $
50224 + *
50225 + * This file contains the definitions of the basic atheros data types.
50226 + * It is used to map the data types in atheros files to a platform specific
50227 + * type.
50228 + *
50229 + * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
50230 + *
50231 + *
50232 + *  This program is free software; you can redistribute it and/or modify
50233 + *  it under the terms of the GNU General Public License version 2 as
50234 + *  published by the Free Software Foundation;
50235 + *
50236 + *  Software distributed under the License is distributed on an "AS
50237 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
50238 + *  implied. See the License for the specific language governing
50239 + *  rights and limitations under the License.
50240 + *
50241 + *
50242 + *
50243 + */
50244 +
50245 +#ifndef _ATHTYPES_LINUX_H_
50246 +#define _ATHTYPES_LINUX_H_
50247 +
50248 +#ifdef __KERNEL__
50249 +#include <linux/types.h>
50250 +#endif
50251 +
50252 +typedef int8_t      A_INT8;
50253 +typedef int16_t     A_INT16;
50254 +typedef int32_t     A_INT32;
50255 +typedef int64_t     A_INT64;
50256 +
50257 +typedef u_int8_t     A_UINT8;
50258 +typedef u_int16_t    A_UINT16;
50259 +typedef u_int32_t    A_UINT32;
50260 +typedef u_int64_t    A_UINT64;
50261 +
50262 +typedef int             A_BOOL;
50263 +typedef char            A_CHAR;
50264 +typedef unsigned char   A_UCHAR;
50265 +typedef unsigned long   A_ATH_TIMER;
50266 +
50267 +
50268 +#endif /* _ATHTYPES_LINUX_H_ */
50269 --- /dev/null
50270 +++ b/drivers/ar6000/ar6000/config_linux.h
50271 @@ -0,0 +1,44 @@
50272 +/*
50273 + * Copyright (c) 2004-2007 Atheros Communications Inc.
50274 + * All rights reserved.
50275 + *
50276 + *
50277 + *  This program is free software; you can redistribute it and/or modify
50278 + *  it under the terms of the GNU General Public License version 2 as
50279 + *  published by the Free Software Foundation;
50280 + *
50281 + *  Software distributed under the License is distributed on an "AS
50282 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
50283 + *  implied. See the License for the specific language governing
50284 + *  rights and limitations under the License.
50285 + *
50286 + *
50287 + *
50288 + */
50289 +
50290 +#ifndef _CONFIG_LINUX_H_
50291 +#define _CONFIG_LINUX_H_
50292 +
50293 +#ifdef __cplusplus
50294 +extern "C" {
50295 +#endif
50296 +
50297 +/*
50298 + * Host-side GPIO support is optional.
50299 + * If run-time access to GPIO pins is not required, then
50300 + * this should be changed to #undef.
50301 + */
50302 +#define CONFIG_HOST_GPIO_SUPPORT
50303 +
50304 +/*
50305 + * Host side Test Command support
50306 + */
50307 +#define CONFIG_HOST_TCMD_SUPPORT
50308 +
50309 +#define USE_4BYTE_REGISTER_ACCESS
50310 +
50311 +#ifdef __cplusplus
50312 +}
50313 +#endif
50314 +
50315 +#endif
50316 --- /dev/null
50317 +++ b/drivers/ar6000/ar6000/debug_linux.h
50318 @@ -0,0 +1,86 @@
50319 +/*
50320 + * Copyright (c) 2004-2006 Atheros Communications Inc.
50321 + * All rights reserved.
50322 + *
50323 + *
50324 + *  This program is free software; you can redistribute it and/or modify
50325 + *  it under the terms of the GNU General Public License version 2 as
50326 + *  published by the Free Software Foundation;
50327 + *
50328 + *  Software distributed under the License is distributed on an "AS
50329 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
50330 + *  implied. See the License for the specific language governing
50331 + *  rights and limitations under the License.
50332 + *
50333 + *
50334 + *
50335 + */
50336 +
50337 +#ifndef _DEBUG_LINUX_H_
50338 +#define _DEBUG_LINUX_H_
50339 +
50340 +#define DBG_DEFAULTS   (DBG_ERROR|DBG_WARNING)
50341 +
50342 +extern A_UINT32 g_dbg_flags;
50343 +
50344 +#define DBGFMT  "%s() : "
50345 +#define DBGARG  __func__
50346 +#define DBGFN  A_PRINTF
50347 +
50348 +/* ------- Debug related stuff ------- */
50349 +enum {
50350 +    ATH_DEBUG_SEND = 0x0001,
50351 +    ATH_DEBUG_RECV = 0x0002,
50352 +    ATH_DEBUG_SYNC = 0x0004,
50353 +    ATH_DEBUG_DUMP = 0x0008,
50354 +    ATH_DEBUG_IRQ  = 0x0010,
50355 +    ATH_DEBUG_TRC  = 0x0020,
50356 +    ATH_DEBUG_WARN = 0x0040,
50357 +    ATH_DEBUG_ERR  = 0x0080,
50358 +    ATH_LOG_INF           = 0x0100,
50359 +    ATH_DEBUG_BMI  = 0x0110,
50360 +    ATH_DEBUG_WMI  = 0x0120,
50361 +    ATH_DEBUG_HIF  = 0x0140,
50362 +    ATH_DEBUG_HTC  = 0x0180,
50363 +    ATH_DEBUG_WLAN = 0x1000,
50364 +    ATH_LOG_ERR           = 0x1010,
50365 +    ATH_DEBUG_ANY  = 0xFFFF,
50366 +};
50367 +
50368 +#ifdef DEBUG
50369 +
50370 +#define A_DPRINTF(f, a) \
50371 +       if(g_dbg_flags & (f)) \
50372 +       {       \
50373 +               DBGFN a ; \
50374 +       }
50375 +
50376 +
50377 +// TODO FIX usage of A_PRINTF!
50378 +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl))
50379 +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do {   \
50380 +    if (debughtc & ATH_DEBUG_DUMP) {             \
50381 +        DebugDumpBytes(buffer, length,desc);               \
50382 +    }                                            \
50383 +} while(0)
50384 +#define PRINTX_ARG(arg...) arg
50385 +#define AR_DEBUG_PRINTF(flags, args) do {        \
50386 +    if (debughtc & (flags)) {                    \
50387 +        A_PRINTF(KERN_ALERT PRINTX_ARG args);    \
50388 +    }                                            \
50389 +} while (0)
50390 +#define AR_DEBUG_ASSERT(test) do {               \
50391 +    if (!(test)) {                               \
50392 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test));         \
50393 +    }                                            \
50394 +} while(0)
50395 +extern int debughtc;
50396 +#else
50397 +#define AR_DEBUG_PRINTF(flags, args)
50398 +#define AR_DEBUG_PRINTBUF(buffer, length, desc)
50399 +#define AR_DEBUG_ASSERT(test)
50400 +#define AR_DEBUG_LVL_CHECK(lvl) 0
50401 +#define A_DPRINTF(f, a)
50402 +#endif
50403 +
50404 +#endif /* _DEBUG_LINUX_H_ */
50405 --- /dev/null
50406 +++ b/drivers/ar6000/ar6000/ioctl.c
50407 @@ -0,0 +1,2540 @@
50408 +/*
50409 + *
50410 + * Copyright (c) 2004-2007 Atheros Communications Inc.
50411 + * All rights reserved.
50412 + *
50413 + *
50414 + *  This program is free software; you can redistribute it and/or modify
50415 + *  it under the terms of the GNU General Public License version 2 as
50416 + *  published by the Free Software Foundation;
50417 + *
50418 + *  Software distributed under the License is distributed on an "AS
50419 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
50420 + *  implied. See the License for the specific language governing
50421 + *  rights and limitations under the License.
50422 + *
50423 + *
50424 + *
50425 + */
50426 +
50427 +#include "ar6000_drv.h"
50428 +
50429 +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
50430 +static A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
50431 +extern USER_RSSI_THOLD rssi_map[12];
50432 +extern unsigned int wmitimeout;
50433 +extern A_WAITQUEUE_HEAD arEvent;
50434 +extern int tspecCompliance;
50435 +extern int bmienable;
50436 +extern int bypasswmi;
50437 +
50438 +static int
50439 +ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq)
50440 +{
50441 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50442 +
50443 +    if (ar->arWmiReady == FALSE) {
50444 +        return -EIO;
50445 +    }
50446 +
50447 +    if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) {
50448 +        return -EIO;
50449 +    }
50450 +
50451 +    return 0;
50452 +}
50453 +
50454 +static int
50455 +ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq)
50456 +{
50457 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50458 +
50459 +    if (ar->arWmiReady == FALSE) {
50460 +        return -EIO;
50461 +    }
50462 +
50463 +
50464 +    /* currently assume only roam times are required */
50465 +    if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) {
50466 +        return -EIO;
50467 +    }
50468 +
50469 +
50470 +    return 0;
50471 +}
50472 +
50473 +static int
50474 +ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata)
50475 +{
50476 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50477 +    WMI_SET_ROAM_CTRL_CMD cmd;
50478 +    A_UINT8 size = sizeof(cmd);
50479 +
50480 +    if (ar->arWmiReady == FALSE) {
50481 +        return -EIO;
50482 +    }
50483 +
50484 +
50485 +    if (copy_from_user(&cmd, userdata, size)) {
50486 +        return -EFAULT;
50487 +    }
50488 +
50489 +    if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) {
50490 +        if (cmd.info.bssBiasInfo.numBss > 1) {
50491 +            size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS);
50492 +        }
50493 +    }
50494 +
50495 +    if (copy_from_user(&cmd, userdata, size)) {
50496 +        return -EFAULT;
50497 +    }
50498 +
50499 +    if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) {
50500 +        return -EIO;
50501 +    }
50502 +
50503 +    return 0;
50504 +}
50505 +
50506 +static int
50507 +ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata)
50508 +{
50509 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50510 +    WMI_POWERSAVE_TIMERS_POLICY_CMD cmd;
50511 +    A_UINT8 size = sizeof(cmd);
50512 +
50513 +    if (ar->arWmiReady == FALSE) {
50514 +        return -EIO;
50515 +    }
50516 +
50517 +    if (copy_from_user(&cmd, userdata, size)) {
50518 +        return -EFAULT;
50519 +    }
50520 +
50521 +    if (copy_from_user(&cmd, userdata, size)) {
50522 +        return -EFAULT;
50523 +    }
50524 +
50525 +    if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) {
50526 +        return -EIO;
50527 +    }
50528 +
50529 +    return 0;
50530 +}
50531 +
50532 +static int
50533 +ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq)
50534 +{
50535 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50536 +    WMI_SET_WMM_CMD cmd;
50537 +    A_STATUS ret;
50538 +
50539 +    if ((dev->flags & IFF_UP) != IFF_UP) {
50540 +        return -EIO;
50541 +    }
50542 +    if (ar->arWmiReady == FALSE) {
50543 +        return -EIO;
50544 +    }
50545 +
50546 +    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
50547 +                                sizeof(cmd)))
50548 +    {
50549 +        return -EFAULT;
50550 +    }
50551 +
50552 +    if (cmd.status == WMI_WMM_ENABLED) {
50553 +        ar->arWmmEnabled = TRUE;
50554 +    } else {
50555 +        ar->arWmmEnabled = FALSE;
50556 +    }
50557 +
50558 +    ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status);
50559 +
50560 +    switch (ret) {
50561 +        case A_OK:
50562 +            return 0;
50563 +        case A_EBUSY :
50564 +            return -EBUSY;
50565 +        case A_NO_MEMORY:
50566 +            return -ENOMEM;
50567 +        case A_EINVAL:
50568 +        default:
50569 +            return -EFAULT;
50570 +    }
50571 +}
50572 +
50573 +static int
50574 +ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq)
50575 +{
50576 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50577 +    WMI_SET_WMM_TXOP_CMD cmd;
50578 +    A_STATUS ret;
50579 +
50580 +    if ((dev->flags & IFF_UP) != IFF_UP) {
50581 +        return -EIO;
50582 +    }
50583 +    if (ar->arWmiReady == FALSE) {
50584 +        return -EIO;
50585 +    }
50586 +
50587 +    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
50588 +                                sizeof(cmd)))
50589 +    {
50590 +        return -EFAULT;
50591 +    }
50592 +
50593 +    ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable);
50594 +
50595 +    switch (ret) {
50596 +        case A_OK:
50597 +            return 0;
50598 +        case A_EBUSY :
50599 +            return -EBUSY;
50600 +        case A_NO_MEMORY:
50601 +            return -ENOMEM;
50602 +        case A_EINVAL:
50603 +        default:
50604 +            return -EFAULT;
50605 +    }
50606 +}
50607 +
50608 +static int
50609 +ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq)
50610 +{
50611 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50612 +    A_STATUS ret = 0;
50613 +
50614 +    if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) {
50615 +        return -EIO;
50616 +    }
50617 +
50618 +    if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1),
50619 +                            &ar->arRegCode, sizeof(ar->arRegCode)))
50620 +        ret = -EFAULT;
50621 +
50622 +    return ret;
50623 +}
50624 +
50625 +
50626 +/* Get power mode command */
50627 +static int
50628 +ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq)
50629 +{
50630 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50631 +    WMI_POWER_MODE_CMD power_mode;
50632 +    int ret = 0;
50633 +
50634 +    if (ar->arWmiReady == FALSE) {
50635 +        return -EIO;
50636 +    }
50637 +
50638 +    power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi);
50639 +    if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) {
50640 +        ret = -EFAULT;
50641 +    }
50642 +
50643 +    return ret;
50644 +}
50645 +
50646 +
50647 +static int
50648 +ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq)
50649 +{
50650 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50651 +    WMI_CHANNEL_PARAMS_CMD cmd, *cmdp;
50652 +    int ret = 0;
50653 +
50654 +    if (ar->arWmiReady == FALSE) {
50655 +        return -EIO;
50656 +    }
50657 +
50658 +
50659 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
50660 +        return -EFAULT;
50661 +    }
50662 +
50663 +    if (cmd.numChannels > 1) {
50664 +        cmdp = A_MALLOC(130);
50665 +        if (copy_from_user(cmdp, rq->ifr_data,
50666 +                           sizeof (*cmdp) +
50667 +                           ((cmd.numChannels - 1) * sizeof(A_UINT16))))
50668 +        {
50669 +            kfree(cmdp);
50670 +            return -EFAULT;
50671 +        }
50672 +    } else {
50673 +        cmdp = &cmd;
50674 +    }
50675 +
50676 +    if ((ar->arPhyCapability == WMI_11G_CAPABILITY) &&
50677 +        ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE)))
50678 +    {
50679 +        ret = -EINVAL;
50680 +    }
50681 +
50682 +    if (!ret &&
50683 +        (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode,
50684 +                                   cmdp->numChannels, cmdp->channelList)
50685 +         != A_OK))
50686 +    {
50687 +        ret = -EIO;
50688 +    }
50689 +
50690 +    if (cmd.numChannels > 1) {
50691 +        kfree(cmdp);
50692 +    }
50693 +
50694 +    return ret;
50695 +}
50696 +
50697 +static int
50698 +ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq)
50699 +{
50700 +
50701 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50702 +    WMI_SNR_THRESHOLD_PARAMS_CMD cmd;
50703 +    int ret = 0;
50704 +
50705 +    if (ar->arWmiReady == FALSE) {
50706 +        return -EIO;
50707 +    }
50708 +
50709 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
50710 +        return -EFAULT;
50711 +    }
50712 +
50713 +    if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) {
50714 +        ret = -EIO;
50715 +    }
50716 +
50717 +    return ret;
50718 +}
50719 +
50720 +static int
50721 +ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq)
50722 +{
50723 +#define SWAP_THOLD(thold1, thold2) do { \
50724 +    USER_RSSI_THOLD tmpThold;           \
50725 +    tmpThold.tag = thold1.tag;          \
50726 +    tmpThold.rssi = thold1.rssi;        \
50727 +    thold1.tag = thold2.tag;            \
50728 +    thold1.rssi = thold2.rssi;          \
50729 +    thold2.tag = tmpThold.tag;          \
50730 +    thold2.rssi = tmpThold.rssi;        \
50731 +} while (0)
50732 +
50733 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50734 +    WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
50735 +    USER_RSSI_PARAMS rssiParams;
50736 +    A_INT32 i, j;
50737 +
50738 +    int ret = 0;
50739 +
50740 +    if (ar->arWmiReady == FALSE) {
50741 +        return -EIO;
50742 +    }
50743 +
50744 +    if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) {
50745 +        return -EFAULT;
50746 +    }
50747 +    cmd.weight = rssiParams.weight;
50748 +    cmd.pollTime = rssiParams.pollTime;
50749 +
50750 +    A_MEMCPY(rssi_map, &rssiParams.tholds, sizeof(rssi_map));
50751 +    /*
50752 +     *  only 6 elements, so use bubble sorting, in ascending order
50753 +     */
50754 +    for (i = 5; i > 0; i--) {
50755 +        for (j = 0; j < i; j++) { /* above tholds */
50756 +            if (rssi_map[j+1].rssi < rssi_map[j].rssi) {
50757 +                SWAP_THOLD(rssi_map[j+1], rssi_map[j]);
50758 +            } else if (rssi_map[j+1].rssi == rssi_map[j].rssi) {
50759 +                return EFAULT;
50760 +            }
50761 +        }
50762 +    }
50763 +    for (i = 11; i > 6; i--) {
50764 +        for (j = 6; j < i; j++) { /* below tholds */
50765 +            if (rssi_map[j+1].rssi < rssi_map[j].rssi) {
50766 +                SWAP_THOLD(rssi_map[j+1], rssi_map[j]);
50767 +            } else if (rssi_map[j+1].rssi == rssi_map[j].rssi) {
50768 +                return EFAULT;
50769 +            }
50770 +        }
50771 +    }
50772 +
50773 +#ifdef DEBUG
50774 +    for (i = 0; i < 12; i++) {
50775 +        AR_DEBUG2_PRINTF("thold[%d].tag: %d, thold[%d].rssi: %d \n",
50776 +                i, rssi_map[i].tag, i, rssi_map[i].rssi);
50777 +    }
50778 +#endif
50779 +    cmd.thresholdAbove1_Val = rssi_map[0].rssi;
50780 +    cmd.thresholdAbove2_Val = rssi_map[1].rssi;
50781 +    cmd.thresholdAbove3_Val = rssi_map[2].rssi;
50782 +    cmd.thresholdAbove4_Val = rssi_map[3].rssi;
50783 +    cmd.thresholdAbove5_Val = rssi_map[4].rssi;
50784 +    cmd.thresholdAbove6_Val = rssi_map[5].rssi;
50785 +    cmd.thresholdBelow1_Val = rssi_map[6].rssi;
50786 +    cmd.thresholdBelow2_Val = rssi_map[7].rssi;
50787 +    cmd.thresholdBelow3_Val = rssi_map[8].rssi;
50788 +    cmd.thresholdBelow4_Val = rssi_map[9].rssi;
50789 +    cmd.thresholdBelow5_Val = rssi_map[10].rssi;
50790 +    cmd.thresholdBelow6_Val = rssi_map[11].rssi;
50791 +
50792 +    if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) {
50793 +        ret = -EIO;
50794 +    }
50795 +
50796 +    return ret;
50797 +}
50798 +
50799 +static int
50800 +ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq)
50801 +{
50802 +
50803 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50804 +    WMI_LQ_THRESHOLD_PARAMS_CMD cmd;
50805 +    int ret = 0;
50806 +
50807 +    if (ar->arWmiReady == FALSE) {
50808 +        return -EIO;
50809 +    }
50810 +
50811 +    if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) {
50812 +        return -EFAULT;
50813 +    }
50814 +
50815 +    if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) {
50816 +        ret = -EIO;
50817 +    }
50818 +
50819 +    return ret;
50820 +}
50821 +
50822 +
50823 +static int
50824 +ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq)
50825 +{
50826 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50827 +    WMI_PROBED_SSID_CMD cmd;
50828 +    int ret = 0;
50829 +
50830 +    if (ar->arWmiReady == FALSE) {
50831 +        return -EIO;
50832 +    }
50833 +
50834 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
50835 +        return -EFAULT;
50836 +    }
50837 +
50838 +    if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength,
50839 +                                  cmd.ssid) != A_OK)
50840 +    {
50841 +        ret = -EIO;
50842 +    }
50843 +
50844 +    return ret;
50845 +}
50846 +
50847 +static int
50848 +ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq)
50849 +{
50850 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50851 +    WMI_ADD_BAD_AP_CMD cmd;
50852 +    int ret = 0;
50853 +
50854 +    if (ar->arWmiReady == FALSE) {
50855 +        return -EIO;
50856 +    }
50857 +
50858 +
50859 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
50860 +        return -EFAULT;
50861 +    }
50862 +
50863 +    if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) {
50864 +        return -EIO;
50865 +    }
50866 +
50867 +    if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) {
50868 +        /*
50869 +         * This is a delete badAP.
50870 +         */
50871 +        if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) {
50872 +            ret = -EIO;
50873 +        }
50874 +    } else {
50875 +        if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) {
50876 +            ret = -EIO;
50877 +        }
50878 +    }
50879 +
50880 +    return ret;
50881 +}
50882 +
50883 +static int
50884 +ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq)
50885 +{
50886 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50887 +    WMI_CREATE_PSTREAM_CMD cmd;
50888 +    A_STATUS ret;
50889 +
50890 +    if (ar->arWmiReady == FALSE) {
50891 +        return -EIO;
50892 +    }
50893 +
50894 +
50895 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
50896 +        return -EFAULT;
50897 +    }
50898 +
50899 +    ret = wmi_verify_tspec_params(&cmd, tspecCompliance);
50900 +    if (ret == A_OK)
50901 +        ret = wmi_create_pstream_cmd(ar->arWmi, &cmd);
50902 +
50903 +    switch (ret) {
50904 +        case A_OK:
50905 +            return 0;
50906 +        case A_EBUSY :
50907 +            return -EBUSY;
50908 +        case A_NO_MEMORY:
50909 +            return -ENOMEM;
50910 +        case A_EINVAL:
50911 +        default:
50912 +            return -EFAULT;
50913 +    }
50914 +}
50915 +
50916 +static int
50917 +ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq)
50918 +{
50919 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50920 +    WMI_DELETE_PSTREAM_CMD cmd;
50921 +    int ret = 0;
50922 +
50923 +    if (ar->arWmiReady == FALSE) {
50924 +        return -EIO;
50925 +    }
50926 +
50927 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
50928 +        return -EFAULT;
50929 +    }
50930 +
50931 +    ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid);
50932 +
50933 +    switch (ret) {
50934 +        case A_OK:
50935 +            return 0;
50936 +        case A_EBUSY :
50937 +            return -EBUSY;
50938 +        case A_NO_MEMORY:
50939 +            return -ENOMEM;
50940 +        case A_EINVAL:
50941 +        default:
50942 +            return -EFAULT;
50943 +    }
50944 +}
50945 +
50946 +static int
50947 +ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq)
50948 +{
50949 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50950 +    struct ar6000_queuereq qreq;
50951 +    int ret = 0;
50952 +
50953 +    if (ar->arWmiReady == FALSE) {
50954 +        return -EIO;
50955 +    }
50956 +
50957 +    if( copy_from_user(&qreq, rq->ifr_data,
50958 +                  sizeof(struct ar6000_queuereq)))
50959 +        return -EFAULT;
50960 +
50961 +    qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass);
50962 +
50963 +    if (copy_to_user(rq->ifr_data, &qreq,
50964 +                 sizeof(struct ar6000_queuereq)))
50965 +    {
50966 +        ret = -EFAULT;
50967 +    }
50968 +
50969 +    return ret;
50970 +}
50971 +
50972 +#ifdef CONFIG_HOST_TCMD_SUPPORT
50973 +static A_STATUS
50974 +ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev,
50975 +                                 struct ifreq *rq, A_UINT8 *data, A_UINT32 len)
50976 +{
50977 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
50978 +    A_UINT32    buf[2];
50979 +    int ret = 0;
50980 +
50981 +    if (ar->arWmiReady == FALSE) {
50982 +        return -EIO;
50983 +    }
50984 +
50985 +    if (down_interruptible(&ar->arSem)) {
50986 +        return -ERESTARTSYS;
50987 +    }
50988 +    ar->tcmdRxReport = 0;
50989 +    if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) {
50990 +        up(&ar->arSem);
50991 +        return -EIO;
50992 +    }
50993 +
50994 +    wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ);
50995 +
50996 +    if (signal_pending(current)) {
50997 +        ret = -EINTR;
50998 +    }
50999 +
51000 +    buf[0] = ar->tcmdRxTotalPkt;
51001 +    buf[1] = ar->tcmdRxRssi;
51002 +    if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) {
51003 +        ret = -EFAULT;
51004 +    }
51005 +
51006 +    up(&ar->arSem);
51007 +
51008 +    return ret;
51009 +}
51010 +
51011 +void
51012 +ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len)
51013 +{
51014 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
51015 +    TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results;
51016 +
51017 +    ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt;
51018 +    ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm;
51019 +    ar->tcmdRxReport = 1;
51020 +
51021 +    wake_up(&arEvent);
51022 +}
51023 +#endif /* CONFIG_HOST_TCMD_SUPPORT*/
51024 +
51025 +static int
51026 +ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq)
51027 +{
51028 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51029 +    WMI_TARGET_ERROR_REPORT_BITMASK cmd;
51030 +    int ret = 0;
51031 +
51032 +    if (ar->arWmiReady == FALSE) {
51033 +        return -EIO;
51034 +    }
51035 +
51036 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51037 +        return -EFAULT;
51038 +    }
51039 +
51040 +    ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask);
51041 +
51042 +    return  (ret==0 ? ret : -EINVAL);
51043 +}
51044 +
51045 +static int
51046 +ar6000_clear_target_stats(struct net_device *dev)
51047 +{
51048 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51049 +    TARGET_STATS *pStats = &ar->arTargetStats;
51050 +    int ret = 0;
51051 +
51052 +    if (ar->arWmiReady == FALSE) {
51053 +       return -EIO;
51054 +    }
51055 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
51056 +    A_MEMZERO(pStats, sizeof(TARGET_STATS));
51057 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
51058 +    return ret;
51059 +}
51060 +
51061 +static int
51062 +ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq)
51063 +{
51064 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51065 +    TARGET_STATS_CMD cmd;
51066 +    TARGET_STATS *pStats = &ar->arTargetStats;
51067 +    int ret = 0;
51068 +
51069 +    if (ar->arWmiReady == FALSE) {
51070 +        return -EIO;
51071 +    }
51072 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51073 +        return -EFAULT;
51074 +    }
51075 +    if (down_interruptible(&ar->arSem)) {
51076 +        return -ERESTARTSYS;
51077 +    }
51078 +
51079 +    ar->statsUpdatePending = TRUE;
51080 +
51081 +    if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
51082 +        up(&ar->arSem);
51083 +        return -EIO;
51084 +    }
51085 +
51086 +    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
51087 +
51088 +    if (signal_pending(current)) {
51089 +        ret = -EINTR;
51090 +    }
51091 +
51092 +    if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
51093 +        ret = -EFAULT;
51094 +    }
51095 +
51096 +    if (cmd.clearStats == 1) {
51097 +        ret = ar6000_clear_target_stats(dev);
51098 +    }
51099 +
51100 +    up(&ar->arSem);
51101 +
51102 +    return ret;
51103 +}
51104 +
51105 +static int
51106 +ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq)
51107 +{
51108 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51109 +    WMI_SET_ACCESS_PARAMS_CMD cmd;
51110 +    int ret = 0;
51111 +
51112 +    if (ar->arWmiReady == FALSE) {
51113 +        return -EIO;
51114 +    }
51115 +
51116 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51117 +        return -EFAULT;
51118 +    }
51119 +
51120 +    if (wmi_set_access_params_cmd(ar->arWmi, cmd.txop, cmd.eCWmin, cmd.eCWmax,
51121 +                                  cmd.aifsn) == A_OK)
51122 +    {
51123 +        ret = 0;
51124 +    } else {
51125 +        ret = -EINVAL;
51126 +    }
51127 +
51128 +    return (ret);
51129 +}
51130 +
51131 +static int
51132 +ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq)
51133 +{
51134 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51135 +    WMI_DISC_TIMEOUT_CMD cmd;
51136 +    int ret = 0;
51137 +
51138 +    if (ar->arWmiReady == FALSE) {
51139 +        return -EIO;
51140 +    }
51141 +
51142 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51143 +        return -EFAULT;
51144 +    }
51145 +
51146 +    if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK)
51147 +    {
51148 +        ret = 0;
51149 +    } else {
51150 +        ret = -EINVAL;
51151 +    }
51152 +
51153 +    return (ret);
51154 +}
51155 +
51156 +static int
51157 +ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata)
51158 +{
51159 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51160 +    WMI_SET_VOICE_PKT_SIZE_CMD cmd;
51161 +    int ret = 0;
51162 +
51163 +    if (ar->arWmiReady == FALSE) {
51164 +        return -EIO;
51165 +    }
51166 +
51167 +    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
51168 +        return -EFAULT;
51169 +    }
51170 +
51171 +    if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK)
51172 +    {
51173 +        ret = 0;
51174 +    } else {
51175 +        ret = -EINVAL;
51176 +    }
51177 +
51178 +
51179 +    return (ret);
51180 +}
51181 +
51182 +static int
51183 +ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata)
51184 +{
51185 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51186 +    WMI_SET_MAX_SP_LEN_CMD cmd;
51187 +    int ret = 0;
51188 +
51189 +    if (ar->arWmiReady == FALSE) {
51190 +        return -EIO;
51191 +    }
51192 +
51193 +    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
51194 +        return -EFAULT;
51195 +    }
51196 +
51197 +    if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK)
51198 +    {
51199 +        ret = 0;
51200 +    } else {
51201 +        ret = -EINVAL;
51202 +    }
51203 +
51204 +    return (ret);
51205 +}
51206 +
51207 +
51208 +static int
51209 +ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata)
51210 +{
51211 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51212 +    WMI_SET_BT_STATUS_CMD cmd;
51213 +    int ret = 0;
51214 +
51215 +    if (ar->arWmiReady == FALSE) {
51216 +        return -EIO;
51217 +    }
51218 +
51219 +    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
51220 +        return -EFAULT;
51221 +    }
51222 +
51223 +    if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK)
51224 +    {
51225 +        ret = 0;
51226 +    } else {
51227 +        ret = -EINVAL;
51228 +    }
51229 +
51230 +    return (ret);
51231 +}
51232 +
51233 +static int
51234 +ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata)
51235 +{
51236 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51237 +    WMI_SET_BT_PARAMS_CMD cmd;
51238 +    int ret = 0;
51239 +
51240 +    if (ar->arWmiReady == FALSE) {
51241 +        return -EIO;
51242 +    }
51243 +
51244 +    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
51245 +        return -EFAULT;
51246 +    }
51247 +
51248 +    if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK)
51249 +    {
51250 +        ret = 0;
51251 +    } else {
51252 +        ret = -EINVAL;
51253 +    }
51254 +
51255 +    return (ret);
51256 +}
51257 +
51258 +#ifdef CONFIG_HOST_GPIO_SUPPORT
51259 +struct ar6000_gpio_intr_wait_cmd_s  gpio_intr_results;
51260 +/* gpio_reg_results and gpio_data_available are protected by arSem */
51261 +static struct ar6000_gpio_register_cmd_s gpio_reg_results;
51262 +static A_BOOL gpio_data_available; /* Requested GPIO data available */
51263 +static A_BOOL gpio_intr_available; /* GPIO interrupt info available */
51264 +static A_BOOL gpio_ack_received;   /* GPIO ack was received */
51265 +
51266 +/* Host-side initialization for General Purpose I/O support */
51267 +void ar6000_gpio_init(void)
51268 +{
51269 +    gpio_intr_available = FALSE;
51270 +    gpio_data_available = FALSE;
51271 +    gpio_ack_received   = FALSE;
51272 +}
51273 +
51274 +/*
51275 + * Called when a GPIO interrupt is received from the Target.
51276 + * intr_values shows which GPIO pins have interrupted.
51277 + * input_values shows a recent value of GPIO pins.
51278 + */
51279 +void
51280 +ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values)
51281 +{
51282 +    gpio_intr_results.intr_mask = intr_mask;
51283 +    gpio_intr_results.input_values = input_values;
51284 +    *((volatile A_BOOL *)&gpio_intr_available) = TRUE;
51285 +    wake_up(&arEvent);
51286 +}
51287 +
51288 +/*
51289 + * This is called when a response is received from the Target
51290 + * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get
51291 + * call.
51292 + */
51293 +void
51294 +ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value)
51295 +{
51296 +    gpio_reg_results.gpioreg_id = reg_id;
51297 +    gpio_reg_results.value = value;
51298 +    *((volatile A_BOOL *)&gpio_data_available) = TRUE;
51299 +    wake_up(&arEvent);
51300 +}
51301 +
51302 +/*
51303 + * This is called when an acknowledgement is received from the Target
51304 + * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set
51305 + * call.
51306 + */
51307 +void
51308 +ar6000_gpio_ack_rx(void)
51309 +{
51310 +    gpio_ack_received = TRUE;
51311 +    wake_up(&arEvent);
51312 +}
51313 +
51314 +A_STATUS
51315 +ar6000_gpio_output_set(struct net_device *dev,
51316 +                       A_UINT32 set_mask,
51317 +                       A_UINT32 clear_mask,
51318 +                       A_UINT32 enable_mask,
51319 +                       A_UINT32 disable_mask)
51320 +{
51321 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51322 +
51323 +    gpio_ack_received = FALSE;
51324 +    return wmi_gpio_output_set(ar->arWmi,
51325 +                set_mask, clear_mask, enable_mask, disable_mask);
51326 +}
51327 +
51328 +static A_STATUS
51329 +ar6000_gpio_input_get(struct net_device *dev)
51330 +{
51331 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51332 +
51333 +    *((volatile A_BOOL *)&gpio_data_available) = FALSE;
51334 +    return wmi_gpio_input_get(ar->arWmi);
51335 +}
51336 +
51337 +static A_STATUS
51338 +ar6000_gpio_register_set(struct net_device *dev,
51339 +                         A_UINT32 gpioreg_id,
51340 +                         A_UINT32 value)
51341 +{
51342 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51343 +
51344 +    gpio_ack_received = FALSE;
51345 +    return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value);
51346 +}
51347 +
51348 +static A_STATUS
51349 +ar6000_gpio_register_get(struct net_device *dev,
51350 +                         A_UINT32 gpioreg_id)
51351 +{
51352 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51353 +
51354 +    *((volatile A_BOOL *)&gpio_data_available) = FALSE;
51355 +    return wmi_gpio_register_get(ar->arWmi, gpioreg_id);
51356 +}
51357 +
51358 +static A_STATUS
51359 +ar6000_gpio_intr_ack(struct net_device *dev,
51360 +                     A_UINT32 ack_mask)
51361 +{
51362 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51363 +
51364 +    gpio_intr_available = FALSE;
51365 +    return wmi_gpio_intr_ack(ar->arWmi, ack_mask);
51366 +}
51367 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
51368 +
51369 +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
51370 +{
51371 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51372 +    HIF_DEVICE *hifDevice = ar->arHifDevice;
51373 +    int ret, param, param2;
51374 +    unsigned int address = 0;
51375 +    unsigned int length = 0;
51376 +    unsigned char *buffer;
51377 +    char *userdata;
51378 +    A_UINT32 connectCtrlFlags;
51379 +
51380 +
51381 +    static WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0,
51382 +                                           WMI_SHORTSCANRATIO_DEFAULT,
51383 +                                           DEFAULT_SCAN_CTRL_FLAGS,
51384 +                                           0};
51385 +    WMI_SET_AKMP_PARAMS_CMD  akmpParams;
51386 +    WMI_SET_PMKID_LIST_CMD   pmkidInfo;
51387 +
51388 +    if (cmd == AR6000_IOCTL_EXTENDED)
51389 +    {
51390 +        /*
51391 +         * This allows for many more wireless ioctls than would otherwise
51392 +         * be available.  Applications embed the actual ioctl command in
51393 +         * the first word of the parameter block, and use the command
51394 +         * AR6000_IOCTL_EXTENDED_CMD on the ioctl call.
51395 +         */
51396 +        get_user(cmd, (int *)rq->ifr_data);
51397 +        userdata = (char *)(((unsigned int *)rq->ifr_data)+1);
51398 +    }
51399 +    else
51400 +    {
51401 +        userdata = (char *)rq->ifr_data;
51402 +    }
51403 +
51404 +    if ((ar->arWlanState == WLAN_DISABLED) &&
51405 +        ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) &&
51406 +         (cmd != AR6000_XIOCTL_DIAG_READ) &&
51407 +         (cmd != AR6000_XIOCTL_DIAG_WRITE)))
51408 +    {
51409 +        return -EIO;
51410 +    }
51411 +
51412 +    ret = 0;
51413 +    switch(cmd)
51414 +    {
51415 +#ifdef CONFIG_HOST_TCMD_SUPPORT
51416 +        case AR6000_XIOCTL_TCMD_CONT_TX:
51417 +            {
51418 +                TCMD_CONT_TX txCmd;
51419 +
51420 +                if (ar->tcmdPm == TCMD_PM_SLEEP) {
51421 +                    A_PRINTF("Can NOT send tx tcmd when target is asleep! \n");
51422 +                    return -EFAULT;
51423 +                }
51424 +
51425 +                if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX)))
51426 +                    return -EFAULT;
51427 +                wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX));
51428 +            }
51429 +            break;
51430 +        case AR6000_XIOCTL_TCMD_CONT_RX:
51431 +            {
51432 +                TCMD_CONT_RX rxCmd;
51433 +
51434 +                if (ar->tcmdPm == TCMD_PM_SLEEP) {
51435 +                    A_PRINTF("Can NOT send rx tcmd when target is asleep! \n");
51436 +                    return -EFAULT;
51437 +                }
51438 +                if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX)))
51439 +                    return -EFAULT;
51440 +                switch(rxCmd.act)
51441 +                {
51442 +                    case TCMD_CONT_RX_PROMIS:
51443 +                    case TCMD_CONT_RX_FILTER:
51444 +                    case TCMD_CONT_RX_SETMAC:
51445 +                         wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd,
51446 +                                                sizeof(TCMD_CONT_RX));
51447 +                         break;
51448 +                    case TCMD_CONT_RX_REPORT:
51449 +                         ar6000_ioctl_tcmd_get_rx_report(dev, rq,
51450 +                         (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX));
51451 +                         break;
51452 +                    default:
51453 +                         A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act);
51454 +                         return -EINVAL;
51455 +                }
51456 +            }
51457 +            break;
51458 +        case AR6000_XIOCTL_TCMD_PM:
51459 +            {
51460 +                TCMD_PM pmCmd;
51461 +
51462 +                if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM)))
51463 +                    return -EFAULT;
51464 +                ar->tcmdPm = pmCmd.mode;
51465 +                wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM));
51466 +            }
51467 +            break;
51468 +#endif /* CONFIG_HOST_TCMD_SUPPORT */
51469 +
51470 +        case AR6000_XIOCTL_BMI_DONE:
51471 +            if(bmienable)
51472 +            {
51473 +                ret = ar6000_init(dev);
51474 +            }
51475 +            else
51476 +            {
51477 +                ret = BMIDone(hifDevice);
51478 +            }
51479 +            break;
51480 +
51481 +        case AR6000_XIOCTL_BMI_READ_MEMORY:
51482 +            get_user(address, (unsigned int *)userdata);
51483 +            get_user(length, (unsigned int *)userdata + 1);
51484 +            AR_DEBUG_PRINTF("Read Memory (address: 0x%x, length: %d)\n",
51485 +                             address, length);
51486 +            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
51487 +                A_MEMZERO(buffer, length);
51488 +                ret = BMIReadMemory(hifDevice, address, buffer, length);
51489 +                if (copy_to_user(rq->ifr_data, buffer, length)) {
51490 +                    ret = -EFAULT;
51491 +                }
51492 +                A_FREE(buffer);
51493 +            } else {
51494 +                ret = -ENOMEM;
51495 +            }
51496 +            break;
51497 +
51498 +        case AR6000_XIOCTL_BMI_WRITE_MEMORY:
51499 +            get_user(address, (unsigned int *)userdata);
51500 +            get_user(length, (unsigned int *)userdata + 1);
51501 +            AR_DEBUG_PRINTF("Write Memory (address: 0x%x, length: %d)\n",
51502 +                             address, length);
51503 +            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
51504 +                A_MEMZERO(buffer, length);
51505 +                if (copy_from_user(buffer, &userdata[sizeof(address) +
51506 +                                   sizeof(length)], length))
51507 +                {
51508 +                    ret = -EFAULT;
51509 +                } else {
51510 +                    ret = BMIWriteMemory(hifDevice, address, buffer, length);
51511 +                }
51512 +                A_FREE(buffer);
51513 +            } else {
51514 +                ret = -ENOMEM;
51515 +            }
51516 +            break;
51517 +
51518 +        case AR6000_XIOCTL_BMI_TEST:
51519 +           AR_DEBUG_PRINTF("No longer supported\n");
51520 +           ret = -EOPNOTSUPP;
51521 +           break;
51522 +
51523 +        case AR6000_XIOCTL_BMI_EXECUTE:
51524 +            get_user(address, (unsigned int *)userdata);
51525 +            get_user(param, (unsigned int *)userdata + 1);
51526 +            AR_DEBUG_PRINTF("Execute (address: 0x%x, param: %d)\n",
51527 +                             address, param);
51528 +            ret = BMIExecute(hifDevice, address, &param);
51529 +            put_user(param, (unsigned int *)rq->ifr_data); /* return value */
51530 +            break;
51531 +
51532 +        case AR6000_XIOCTL_BMI_SET_APP_START:
51533 +            get_user(address, (unsigned int *)userdata);
51534 +            AR_DEBUG_PRINTF("Set App Start (address: 0x%x)\n", address);
51535 +            ret = BMISetAppStart(hifDevice, address);
51536 +            break;
51537 +
51538 +        case AR6000_XIOCTL_BMI_READ_SOC_REGISTER:
51539 +            get_user(address, (unsigned int *)userdata);
51540 +            ret = BMIReadSOCRegister(hifDevice, address, &param);
51541 +            put_user(param, (unsigned int *)rq->ifr_data); /* return value */
51542 +            break;
51543 +
51544 +        case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER:
51545 +            get_user(address, (unsigned int *)userdata);
51546 +            get_user(param, (unsigned int *)userdata + 1);
51547 +            ret = BMIWriteSOCRegister(hifDevice, address, param);
51548 +            break;
51549 +
51550 +#ifdef HTC_RAW_INTERFACE
51551 +        case AR6000_XIOCTL_HTC_RAW_OPEN:
51552 +            ret = A_OK;
51553 +            if (!arRawIfEnabled(ar)) {
51554 +                /* make sure block size is set in case the target was reset since last
51555 +                  * BMI phase (i.e. flashup downloads) */
51556 +                ret = ar6000_SetHTCBlockSize(ar);
51557 +                if (A_FAILED(ret)) {
51558 +                    break;
51559 +                }
51560 +                /* Terminate the BMI phase */
51561 +                ret = BMIDone(hifDevice);
51562 +                if (ret == A_OK) {
51563 +                    ret = ar6000_htc_raw_open(ar);
51564 +                }
51565 +            }
51566 +            break;
51567 +
51568 +        case AR6000_XIOCTL_HTC_RAW_CLOSE:
51569 +            if (arRawIfEnabled(ar)) {
51570 +                ret = ar6000_htc_raw_close(ar);
51571 +                arRawIfEnabled(ar) = FALSE;
51572 +            } else {
51573 +                ret = A_ERROR;
51574 +            }
51575 +            break;
51576 +
51577 +        case AR6000_XIOCTL_HTC_RAW_READ:
51578 +            if (arRawIfEnabled(ar)) {
51579 +                unsigned int streamID;
51580 +                get_user(streamID, (unsigned int *)userdata);
51581 +                get_user(length, (unsigned int *)userdata + 1);
51582 +                buffer = rq->ifr_data + sizeof(length);
51583 +                ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID,
51584 +                                          buffer, length);
51585 +                put_user(ret, (unsigned int *)rq->ifr_data);
51586 +            } else {
51587 +                ret = A_ERROR;
51588 +            }
51589 +            break;
51590 +
51591 +        case AR6000_XIOCTL_HTC_RAW_WRITE:
51592 +            if (arRawIfEnabled(ar)) {
51593 +                unsigned int streamID;
51594 +                get_user(streamID, (unsigned int *)userdata);
51595 +                get_user(length, (unsigned int *)userdata + 1);
51596 +                buffer = userdata + sizeof(streamID) + sizeof(length);
51597 +                ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID,
51598 +                                           buffer, length);
51599 +                put_user(ret, (unsigned int *)rq->ifr_data);
51600 +            } else {
51601 +                ret = A_ERROR;
51602 +            }
51603 +            break;
51604 +#endif /* HTC_RAW_INTERFACE */
51605 +
51606 +        case AR6000_IOCTL_WMI_GETREV:
51607 +        {
51608 +            if (copy_to_user(rq->ifr_data, &ar->arVersion,
51609 +                             sizeof(ar->arVersion)))
51610 +            {
51611 +                ret = -EFAULT;
51612 +            }
51613 +            break;
51614 +        }
51615 +        case AR6000_IOCTL_WMI_SETPWR:
51616 +        {
51617 +            WMI_POWER_MODE_CMD pwrModeCmd;
51618 +
51619 +            if (ar->arWmiReady == FALSE) {
51620 +                ret = -EIO;
51621 +            } else if (copy_from_user(&pwrModeCmd, userdata,
51622 +                                   sizeof(pwrModeCmd)))
51623 +            {
51624 +                ret = -EFAULT;
51625 +            } else {
51626 +                if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode)
51627 +                       != A_OK)
51628 +                {
51629 +                    ret = -EIO;
51630 +                }
51631 +            }
51632 +            break;
51633 +        }
51634 +        case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS:
51635 +        {
51636 +            WMI_IBSS_PM_CAPS_CMD ibssPmCaps;
51637 +
51638 +            if (ar->arWmiReady == FALSE) {
51639 +                ret = -EIO;
51640 +            } else if (copy_from_user(&ibssPmCaps, userdata,
51641 +                                   sizeof(ibssPmCaps)))
51642 +            {
51643 +                ret = -EFAULT;
51644 +            } else {
51645 +                if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl,
51646 +                    ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK)
51647 +                {
51648 +                    ret = -EIO;
51649 +                }
51650 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
51651 +                ar->arIbssPsEnable = ibssPmCaps.power_saving;
51652 +                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
51653 +            }
51654 +            break;
51655 +        }
51656 +        case AR6000_IOCTL_WMI_SET_PMPARAMS:
51657 +        {
51658 +            WMI_POWER_PARAMS_CMD pmParams;
51659 +
51660 +            if (ar->arWmiReady == FALSE) {
51661 +                ret = -EIO;
51662 +            } else if (copy_from_user(&pmParams, userdata,
51663 +                                      sizeof(pmParams)))
51664 +            {
51665 +                ret = -EFAULT;
51666 +            } else {
51667 +                if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period,
51668 +                                     pmParams.pspoll_number,
51669 +                                     pmParams.dtim_policy) != A_OK)
51670 +                {
51671 +                    ret = -EIO;
51672 +                }
51673 +            }
51674 +            break;
51675 +        }
51676 +        case AR6000_IOCTL_WMI_SETSCAN:
51677 +        {
51678 +            if (ar->arWmiReady == FALSE) {
51679 +                ret = -EIO;
51680 +            } else if (copy_from_user(&scParams, userdata,
51681 +                                      sizeof(scParams)))
51682 +            {
51683 +                ret = -EFAULT;
51684 +            } else {
51685 +                if (CAN_SCAN_IN_CONNECT(scParams.scanCtrlFlags)) {
51686 +                    ar->arSkipScan = FALSE;
51687 +                } else {
51688 +                    ar->arSkipScan = TRUE;
51689 +                }
51690 +
51691 +                if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period,
51692 +                                       scParams.fg_end_period,
51693 +                                       scParams.bg_period,
51694 +                                       scParams.minact_chdwell_time,
51695 +                                       scParams.maxact_chdwell_time,
51696 +                                       scParams.pas_chdwell_time,
51697 +                                       scParams.shortScanRatio,
51698 +                                       scParams.scanCtrlFlags,
51699 +                                       scParams.max_dfsch_act_time) != A_OK)
51700 +                {
51701 +                    ret = -EIO;
51702 +                }
51703 +            }
51704 +            break;
51705 +        }
51706 +        case AR6000_IOCTL_WMI_SETLISTENINT:
51707 +        {
51708 +            WMI_LISTEN_INT_CMD listenCmd;
51709 +
51710 +            if (ar->arWmiReady == FALSE) {
51711 +                ret = -EIO;
51712 +            } else if (copy_from_user(&listenCmd, userdata,
51713 +                                      sizeof(listenCmd)))
51714 +            {
51715 +                ret = -EFAULT;
51716 +            } else {
51717 +                    if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) {
51718 +                        ret = -EIO;
51719 +                    } else {
51720 +                        AR6000_SPIN_LOCK(&ar->arLock, 0);
51721 +                        ar->arListenInterval = param;
51722 +                        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
51723 +                    }
51724 +
51725 +                }
51726 +            break;
51727 +        }
51728 +        case AR6000_IOCTL_WMI_SET_BMISS_TIME:
51729 +        {
51730 +            WMI_BMISS_TIME_CMD bmissCmd;
51731 +
51732 +            if (ar->arWmiReady == FALSE) {
51733 +                ret = -EIO;
51734 +            } else if (copy_from_user(&bmissCmd, userdata,
51735 +                                      sizeof(bmissCmd)))
51736 +            {
51737 +                ret = -EFAULT;
51738 +            } else {
51739 +                if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) {
51740 +                    ret = -EIO;
51741 +                }
51742 +            }
51743 +            break;
51744 +        }
51745 +        case AR6000_IOCTL_WMI_SETBSSFILTER:
51746 +        {
51747 +            if (ar->arWmiReady == FALSE) {
51748 +                ret = -EIO;
51749 +            } else {
51750 +
51751 +                get_user(param, (unsigned char *)userdata);
51752 +                get_user(param2, (unsigned int *)(userdata + 1));
51753 +               printk("SETBSSFILTER: filter 0x%x, mask: 0x%x\n", param, param2);
51754 +                if (wmi_bssfilter_cmd(ar->arWmi, param, param2) != A_OK) {
51755 +                    ret = -EIO;
51756 +                }
51757 +            }
51758 +            break;
51759 +        }
51760 +        case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD:
51761 +        {
51762 +            ret = ar6000_ioctl_set_snr_threshold(dev, rq);
51763 +            break;
51764 +        }
51765 +        case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD:
51766 +        {
51767 +            ret = ar6000_ioctl_set_rssi_threshold(dev, rq);
51768 +            break;
51769 +        }
51770 +        case AR6000_XIOCTL_WMI_CLR_RSSISNR:
51771 +        {
51772 +            if (ar->arWmiReady == FALSE) {
51773 +                ret = -EIO;
51774 +            }
51775 +            ret = wmi_clr_rssi_snr(ar->arWmi);
51776 +            break;
51777 +        }
51778 +        case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD:
51779 +        {
51780 +            ret = ar6000_ioctl_set_lq_threshold(dev, rq);
51781 +            break;
51782 +        }
51783 +        case AR6000_XIOCTL_WMI_SET_LPREAMBLE:
51784 +        {
51785 +            WMI_SET_LPREAMBLE_CMD setLpreambleCmd;
51786 +
51787 +            if (ar->arWmiReady == FALSE) {
51788 +                ret = -EIO;
51789 +            } else if (copy_from_user(&setLpreambleCmd, userdata,
51790 +                                   sizeof(setLpreambleCmd)))
51791 +            {
51792 +                ret = -EFAULT;
51793 +            } else {
51794 +                if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status)
51795 +                       != A_OK)
51796 +                {
51797 +                    ret = -EIO;
51798 +                }
51799 +            }
51800 +
51801 +            break;
51802 +        }
51803 +        case AR6000_XIOCTL_WMI_SET_RTS:
51804 +        {
51805 +            WMI_SET_RTS_CMD rtsCmd;
51806 +
51807 +            if (ar->arWmiReady == FALSE) {
51808 +                ret = -EIO;
51809 +            } else if (copy_from_user(&rtsCmd, userdata,
51810 +                                   sizeof(rtsCmd)))
51811 +            {
51812 +                ret = -EFAULT;
51813 +            } else {
51814 +                if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold)
51815 +                       != A_OK)
51816 +                {
51817 +                    ret = -EIO;
51818 +                }
51819 +            }
51820 +
51821 +            break;
51822 +        }
51823 +        case AR6000_XIOCTL_WMI_SET_WMM:
51824 +        {
51825 +            ret = ar6000_ioctl_set_wmm(dev, rq);
51826 +            break;
51827 +        }
51828 +        case AR6000_XIOCTL_WMI_SET_TXOP:
51829 +        {
51830 +            ret = ar6000_ioctl_set_txop(dev, rq);
51831 +            break;
51832 +        }
51833 +        case AR6000_XIOCTL_WMI_GET_RD:
51834 +        {
51835 +            ret = ar6000_ioctl_get_rd(dev, rq);
51836 +            break;
51837 +        }
51838 +        case AR6000_IOCTL_WMI_SET_CHANNELPARAMS:
51839 +        {
51840 +            ret = ar6000_ioctl_set_channelParams(dev, rq);
51841 +            break;
51842 +        }
51843 +        case AR6000_IOCTL_WMI_SET_PROBEDSSID:
51844 +        {
51845 +            ret = ar6000_ioctl_set_probedSsid(dev, rq);
51846 +            break;
51847 +        }
51848 +        case AR6000_IOCTL_WMI_SET_BADAP:
51849 +        {
51850 +            ret = ar6000_ioctl_set_badAp(dev, rq);
51851 +            break;
51852 +        }
51853 +        case AR6000_IOCTL_WMI_CREATE_QOS:
51854 +        {
51855 +            ret = ar6000_ioctl_create_qos(dev, rq);
51856 +            break;
51857 +        }
51858 +        case AR6000_IOCTL_WMI_DELETE_QOS:
51859 +        {
51860 +            ret = ar6000_ioctl_delete_qos(dev, rq);
51861 +            break;
51862 +        }
51863 +        case AR6000_IOCTL_WMI_GET_QOS_QUEUE:
51864 +        {
51865 +            ret = ar6000_ioctl_get_qos_queue(dev, rq);
51866 +            break;
51867 +        }
51868 +        case AR6000_IOCTL_WMI_GET_TARGET_STATS:
51869 +        {
51870 +            ret = ar6000_ioctl_get_target_stats(dev, rq);
51871 +            break;
51872 +        }
51873 +        case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK:
51874 +        {
51875 +            ret = ar6000_ioctl_set_error_report_bitmask(dev, rq);
51876 +            break;
51877 +        }
51878 +        case AR6000_IOCTL_WMI_SET_ASSOC_INFO:
51879 +        {
51880 +            WMI_SET_ASSOC_INFO_CMD cmd;
51881 +            A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN];
51882 +
51883 +            if (ar->arWmiReady == FALSE) {
51884 +                ret = -EIO;
51885 +            } else {
51886 +                get_user(cmd.ieType, userdata);
51887 +                if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) {
51888 +                    ret = -EIO;
51889 +                } else {
51890 +                    get_user(cmd.bufferSize, userdata + 1);
51891 +                    if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) {
51892 +                        ret = -EFAULT;
51893 +                        break;
51894 +                    }
51895 +                    if (copy_from_user(assocInfo, userdata + 2,
51896 +                                       cmd.bufferSize))
51897 +                    {
51898 +                        ret = -EFAULT;
51899 +                    } else {
51900 +                        if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType,
51901 +                                                 cmd.bufferSize,
51902 +                                                 assocInfo) != A_OK)
51903 +                        {
51904 +                            ret = -EIO;
51905 +                        }
51906 +                    }
51907 +                }
51908 +            }
51909 +            break;
51910 +        }
51911 +        case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS:
51912 +        {
51913 +            ret = ar6000_ioctl_set_access_params(dev, rq);
51914 +            break;
51915 +        }
51916 +        case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT:
51917 +        {
51918 +            ret = ar6000_ioctl_set_disconnect_timeout(dev, rq);
51919 +            break;
51920 +        }
51921 +        case AR6000_XIOCTL_FORCE_TARGET_RESET:
51922 +        {
51923 +            if (ar->arHtcTarget)
51924 +            {
51925 +//                HTCForceReset(htcTarget);
51926 +            }
51927 +            else
51928 +            {
51929 +                AR_DEBUG_PRINTF("ar6000_ioctl cannot attempt reset.\n");
51930 +            }
51931 +            break;
51932 +        }
51933 +        case AR6000_XIOCTL_TARGET_INFO:
51934 +        case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */
51935 +        {
51936 +            /* If we made it to here, then the Target exists and is ready. */
51937 +
51938 +            if (cmd == AR6000_XIOCTL_TARGET_INFO) {
51939 +                if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver,
51940 +                                 sizeof(ar->arVersion.target_ver)))
51941 +                {
51942 +                    ret = -EFAULT;
51943 +                }
51944 +                if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType,
51945 +                                 sizeof(ar->arTargetType)))
51946 +                {
51947 +                    ret = -EFAULT;
51948 +                }
51949 +            }
51950 +            break;
51951 +        }
51952 +        case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS:
51953 +        {
51954 +            WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam;
51955 +
51956 +            if (copy_from_user(&hbparam, userdata, sizeof(hbparam)))
51957 +            {
51958 +                ret = -EFAULT;
51959 +            } else {
51960 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
51961 +                /* Start a cyclic timer with the parameters provided. */
51962 +                if (hbparam.frequency) {
51963 +                    ar->arHBChallengeResp.frequency = hbparam.frequency;
51964 +                }
51965 +                if (hbparam.threshold) {
51966 +                    ar->arHBChallengeResp.missThres = hbparam.threshold;
51967 +                }
51968 +
51969 +                /* Delete the pending timer and start a new one */
51970 +                if (timer_pending(&ar->arHBChallengeResp.timer)) {
51971 +                    A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
51972 +                }
51973 +                A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
51974 +                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
51975 +            }
51976 +            break;
51977 +        }
51978 +        case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP:
51979 +        {
51980 +            A_UINT32 cookie;
51981 +
51982 +            if (copy_from_user(&cookie, userdata, sizeof(cookie))) {
51983 +                return -EFAULT;
51984 +            }
51985 +
51986 +            /* Send the challenge on the control channel */
51987 +            if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) {
51988 +                return -EIO;
51989 +            }
51990 +            break;
51991 +        }
51992 +#ifdef USER_KEYS
51993 +        case AR6000_XIOCTL_USER_SETKEYS:
51994 +        {
51995 +
51996 +            ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN;
51997 +
51998 +            if (copy_from_user(&ar->user_key_ctrl, userdata,
51999 +                               sizeof(ar->user_key_ctrl)))
52000 +            {
52001 +                return -EFAULT;
52002 +            }
52003 +
52004 +            A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl);
52005 +            break;
52006 +        }
52007 +#endif /* USER_KEYS */
52008 +
52009 +#ifdef CONFIG_HOST_GPIO_SUPPORT
52010 +        case AR6000_XIOCTL_GPIO_OUTPUT_SET:
52011 +        {
52012 +            struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd;
52013 +
52014 +            if (ar->arWmiReady == FALSE) {
52015 +                return -EIO;
52016 +            }
52017 +            if (down_interruptible(&ar->arSem)) {
52018 +                return -ERESTARTSYS;
52019 +            }
52020 +
52021 +            if (copy_from_user(&gpio_output_set_cmd, userdata,
52022 +                                sizeof(gpio_output_set_cmd)))
52023 +            {
52024 +                ret = -EFAULT;
52025 +            } else {
52026 +                ret = ar6000_gpio_output_set(dev,
52027 +                                             gpio_output_set_cmd.set_mask,
52028 +                                             gpio_output_set_cmd.clear_mask,
52029 +                                             gpio_output_set_cmd.enable_mask,
52030 +                                             gpio_output_set_cmd.disable_mask);
52031 +                if (ret != A_OK) {
52032 +                    ret = EIO;
52033 +                }
52034 +            }
52035 +            up(&ar->arSem);
52036 +            break;
52037 +        }
52038 +        case AR6000_XIOCTL_GPIO_INPUT_GET:
52039 +        {
52040 +            if (ar->arWmiReady == FALSE) {
52041 +                return -EIO;
52042 +            }
52043 +            if (down_interruptible(&ar->arSem)) {
52044 +                return -ERESTARTSYS;
52045 +            }
52046 +
52047 +            ret = ar6000_gpio_input_get(dev);
52048 +            if (ret != A_OK) {
52049 +                up(&ar->arSem);
52050 +                return -EIO;
52051 +            }
52052 +
52053 +            /* Wait for Target to respond. */
52054 +            wait_event_interruptible(arEvent, gpio_data_available);
52055 +            if (signal_pending(current)) {
52056 +                ret = -EINTR;
52057 +            } else {
52058 +                A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE);
52059 +
52060 +                if (copy_to_user(userdata, &gpio_reg_results.value,
52061 +                                 sizeof(gpio_reg_results.value)))
52062 +                {
52063 +                    ret = -EFAULT;
52064 +                }
52065 +            }
52066 +            up(&ar->arSem);
52067 +            break;
52068 +        }
52069 +        case AR6000_XIOCTL_GPIO_REGISTER_SET:
52070 +        {
52071 +            struct ar6000_gpio_register_cmd_s gpio_register_cmd;
52072 +
52073 +            if (ar->arWmiReady == FALSE) {
52074 +                return -EIO;
52075 +            }
52076 +            if (down_interruptible(&ar->arSem)) {
52077 +                return -ERESTARTSYS;
52078 +            }
52079 +
52080 +            if (copy_from_user(&gpio_register_cmd, userdata,
52081 +                                sizeof(gpio_register_cmd)))
52082 +            {
52083 +                ret = -EFAULT;
52084 +            } else {
52085 +                ret = ar6000_gpio_register_set(dev,
52086 +                                               gpio_register_cmd.gpioreg_id,
52087 +                                               gpio_register_cmd.value);
52088 +                if (ret != A_OK) {
52089 +                    ret = EIO;
52090 +                }
52091 +
52092 +                /* Wait for acknowledgement from Target */
52093 +                wait_event_interruptible(arEvent, gpio_ack_received);
52094 +                if (signal_pending(current)) {
52095 +                    ret = -EINTR;
52096 +                }
52097 +            }
52098 +            up(&ar->arSem);
52099 +            break;
52100 +        }
52101 +        case AR6000_XIOCTL_GPIO_REGISTER_GET:
52102 +        {
52103 +            struct ar6000_gpio_register_cmd_s gpio_register_cmd;
52104 +
52105 +            if (ar->arWmiReady == FALSE) {
52106 +                return -EIO;
52107 +            }
52108 +            if (down_interruptible(&ar->arSem)) {
52109 +                return -ERESTARTSYS;
52110 +            }
52111 +
52112 +            if (copy_from_user(&gpio_register_cmd, userdata,
52113 +                                sizeof(gpio_register_cmd)))
52114 +            {
52115 +                ret = -EFAULT;
52116 +            } else {
52117 +                ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id);
52118 +                if (ret != A_OK) {
52119 +                    up(&ar->arSem);
52120 +                    return -EIO;
52121 +                }
52122 +
52123 +                /* Wait for Target to respond. */
52124 +                wait_event_interruptible(arEvent, gpio_data_available);
52125 +                if (signal_pending(current)) {
52126 +                    ret = -EINTR;
52127 +                } else {
52128 +                    A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id);
52129 +                    if (copy_to_user(userdata, &gpio_reg_results,
52130 +                                     sizeof(gpio_reg_results)))
52131 +                    {
52132 +                        ret = -EFAULT;
52133 +                    }
52134 +                }
52135 +            }
52136 +            up(&ar->arSem);
52137 +            break;
52138 +        }
52139 +        case AR6000_XIOCTL_GPIO_INTR_ACK:
52140 +        {
52141 +            struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd;
52142 +
52143 +            if (ar->arWmiReady == FALSE) {
52144 +                return -EIO;
52145 +            }
52146 +            if (down_interruptible(&ar->arSem)) {
52147 +                return -ERESTARTSYS;
52148 +            }
52149 +
52150 +            if (copy_from_user(&gpio_intr_ack_cmd, userdata,
52151 +                                sizeof(gpio_intr_ack_cmd)))
52152 +            {
52153 +                ret = -EFAULT;
52154 +            } else {
52155 +                ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask);
52156 +                if (ret != A_OK) {
52157 +                    ret = EIO;
52158 +                }
52159 +            }
52160 +            up(&ar->arSem);
52161 +            break;
52162 +        }
52163 +        case AR6000_XIOCTL_GPIO_INTR_WAIT:
52164 +        {
52165 +            /* Wait for Target to report an interrupt. */
52166 +            dev_hold(dev);
52167 +            rtnl_unlock();
52168 +            wait_event_interruptible(arEvent, gpio_intr_available);
52169 +            rtnl_lock();
52170 +            __dev_put(dev);
52171 +
52172 +            if (signal_pending(current)) {
52173 +                ret = -EINTR;
52174 +            } else {
52175 +                if (copy_to_user(userdata, &gpio_intr_results,
52176 +                                 sizeof(gpio_intr_results)))
52177 +                {
52178 +                    ret = -EFAULT;
52179 +                }
52180 +            }
52181 +            break;
52182 +        }
52183 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
52184 +
52185 +        case AR6000_XIOCTL_DBGLOG_CFG_MODULE:
52186 +        {
52187 +            struct ar6000_dbglog_module_config_s config;
52188 +
52189 +            if (copy_from_user(&config, userdata, sizeof(config))) {
52190 +                return -EFAULT;
52191 +            }
52192 +
52193 +            /* Send the challenge on the control channel */
52194 +            if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask,
52195 +                                            config.tsr, config.rep,
52196 +                                            config.size, config.valid) != A_OK)
52197 +            {
52198 +                return -EIO;
52199 +            }
52200 +            break;
52201 +        }
52202 +
52203 +        case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS:
52204 +        {
52205 +            /* Send the challenge on the control channel */
52206 +            if (ar6000_dbglog_get_debug_logs(ar) != A_OK)
52207 +            {
52208 +                return -EIO;
52209 +            }
52210 +            break;
52211 +        }
52212 +
52213 +        case AR6000_XIOCTL_SET_ADHOC_BSSID:
52214 +        {
52215 +            WMI_SET_ADHOC_BSSID_CMD adhocBssid;
52216 +
52217 +            if (ar->arWmiReady == FALSE) {
52218 +                ret = -EIO;
52219 +            } else if (copy_from_user(&adhocBssid, userdata,
52220 +                                      sizeof(adhocBssid)))
52221 +            {
52222 +                ret = -EFAULT;
52223 +            } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac,
52224 +                                AR6000_ETH_ADDR_LEN) == 0)
52225 +            {
52226 +                ret = -EFAULT;
52227 +            } else {
52228 +
52229 +                A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid));
52230 +        }
52231 +            break;
52232 +        }
52233 +
52234 +        case AR6000_XIOCTL_SET_OPT_MODE:
52235 +        {
52236 +        WMI_SET_OPT_MODE_CMD optModeCmd;
52237 +            AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
52238 +
52239 +            if (ar->arWmiReady == FALSE) {
52240 +                ret = -EIO;
52241 +            } else if (copy_from_user(&optModeCmd, userdata,
52242 +                                      sizeof(optModeCmd)))
52243 +            {
52244 +                ret = -EFAULT;
52245 +            } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) {
52246 +                ret = -EFAULT;
52247 +
52248 +            } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode)
52249 +                       != A_OK)
52250 +            {
52251 +                ret = -EIO;
52252 +            }
52253 +            break;
52254 +        }
52255 +
52256 +        case AR6000_XIOCTL_OPT_SEND_FRAME:
52257 +        {
52258 +        WMI_OPT_TX_FRAME_CMD optTxFrmCmd;
52259 +            A_UINT8 data[MAX_OPT_DATA_LEN];
52260 +
52261 +            if (ar->arWmiReady == FALSE) {
52262 +                ret = -EIO;
52263 +            } else if (copy_from_user(&optTxFrmCmd, userdata,
52264 +                                      sizeof(optTxFrmCmd)))
52265 +            {
52266 +                ret = -EFAULT;
52267 +            } else if (copy_from_user(data,
52268 +                                      userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1,
52269 +                                      optTxFrmCmd.optIEDataLen))
52270 +            {
52271 +                ret = -EFAULT;
52272 +            } else {
52273 +                ret = wmi_opt_tx_frame_cmd(ar->arWmi,
52274 +                                           optTxFrmCmd.frmType,
52275 +                                           optTxFrmCmd.dstAddr,
52276 +                                           optTxFrmCmd.bssid,
52277 +                                           optTxFrmCmd.optIEDataLen,
52278 +                                           data);
52279 +            }
52280 +
52281 +            break;
52282 +        }
52283 +        case AR6000_XIOCTL_WMI_SETRETRYLIMITS:
52284 +        {
52285 +            WMI_SET_RETRY_LIMITS_CMD setRetryParams;
52286 +
52287 +            if (ar->arWmiReady == FALSE) {
52288 +                ret = -EIO;
52289 +            } else if (copy_from_user(&setRetryParams, userdata,
52290 +                                      sizeof(setRetryParams)))
52291 +            {
52292 +                ret = -EFAULT;
52293 +            } else {
52294 +                if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType,
52295 +                                          setRetryParams.trafficClass,
52296 +                                          setRetryParams.maxRetries,
52297 +                                          setRetryParams.enableNotify) != A_OK)
52298 +                {
52299 +                    ret = -EIO;
52300 +                }
52301 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
52302 +                ar->arMaxRetries = setRetryParams.maxRetries;
52303 +                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
52304 +            }
52305 +            break;
52306 +        }
52307 +
52308 +        case AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL:
52309 +        {
52310 +            WMI_BEACON_INT_CMD bIntvlCmd;
52311 +
52312 +            if (ar->arWmiReady == FALSE) {
52313 +                ret = -EIO;
52314 +            } else if (copy_from_user(&bIntvlCmd, userdata,
52315 +                       sizeof(bIntvlCmd)))
52316 +            {
52317 +                ret = -EFAULT;
52318 +            } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval)
52319 +                        != A_OK)
52320 +            {
52321 +                ret = -EIO;
52322 +            }
52323 +            break;
52324 +        }
52325 +        case IEEE80211_IOCTL_SETAUTHALG:
52326 +        {
52327 +            AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
52328 +            struct ieee80211req_authalg req;
52329 +
52330 +            if (ar->arWmiReady == FALSE) {
52331 +                ret = -EIO;
52332 +            } else if (copy_from_user(&req, userdata,
52333 +                       sizeof(struct ieee80211req_authalg)))
52334 +            {
52335 +                ret = -EFAULT;
52336 +            } else if (req.auth_alg == AUTH_ALG_OPEN_SYSTEM) {
52337 +                ar->arDot11AuthMode  = OPEN_AUTH;
52338 +                ar->arPairwiseCrypto  = NONE_CRYPT;
52339 +                ar->arGroupCrypto     = NONE_CRYPT;
52340 +            } else if (req.auth_alg == AUTH_ALG_LEAP) {
52341 +                ar->arDot11AuthMode   = LEAP_AUTH;
52342 +            } else {
52343 +                ret = -EIO;
52344 +            }
52345 +            break;
52346 +        }
52347 +
52348 +        case AR6000_XIOCTL_SET_VOICE_PKT_SIZE:
52349 +            ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata);
52350 +            break;
52351 +
52352 +        case AR6000_XIOCTL_SET_MAX_SP:
52353 +            ret = ar6000_xioctl_set_max_sp_len(dev, userdata);
52354 +            break;
52355 +
52356 +        case AR6000_XIOCTL_WMI_GET_ROAM_TBL:
52357 +            ret = ar6000_ioctl_get_roam_tbl(dev, rq);
52358 +            break;
52359 +        case AR6000_XIOCTL_WMI_SET_ROAM_CTRL:
52360 +            ret = ar6000_ioctl_set_roam_ctrl(dev, userdata);
52361 +            break;
52362 +        case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS:
52363 +            ret = ar6000_ioctl_set_powersave_timers(dev, userdata);
52364 +            break;
52365 +        case AR6000_XIOCTRL_WMI_GET_POWER_MODE:
52366 +            ret = ar6000_ioctl_get_power_mode(dev, rq);
52367 +            break;
52368 +        case AR6000_XIOCTRL_WMI_SET_WLAN_STATE:
52369 +            get_user(ar->arWlanState, (unsigned int *)userdata);
52370 +            if (ar->arWmiReady == FALSE) {
52371 +                ret = -EIO;
52372 +                break;
52373 +            }
52374 +
52375 +            if (ar->arWlanState == WLAN_ENABLED) {
52376 +                /* Enable foreground scanning */
52377 +                if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period,
52378 +                                       scParams.fg_end_period,
52379 +                                       scParams.bg_period,
52380 +                                       scParams.minact_chdwell_time,
52381 +                                       scParams.maxact_chdwell_time,
52382 +                                       scParams.pas_chdwell_time,
52383 +                                       scParams.shortScanRatio,
52384 +                                       scParams.scanCtrlFlags,
52385 +                                       scParams.max_dfsch_act_time) != A_OK)
52386 +                {
52387 +                    ret = -EIO;
52388 +                }
52389 +                if (ar->arSsidLen) {
52390 +                    ar->arConnectPending = TRUE;
52391 +                    if (wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
52392 +                                        ar->arDot11AuthMode, ar->arAuthMode,
52393 +                                        ar->arPairwiseCrypto,
52394 +                                        ar->arPairwiseCryptoLen,
52395 +                                        ar->arGroupCrypto, ar->arGroupCryptoLen,
52396 +                                        ar->arSsidLen, ar->arSsid,
52397 +                                        ar->arReqBssid, ar->arChannelHint,
52398 +                                        ar->arConnectCtrlFlags) != A_OK)
52399 +                    {
52400 +                        ret = -EIO;
52401 +                        ar->arConnectPending = FALSE;
52402 +                    }
52403 +                }
52404 +            } else {
52405 +                /* Disconnect from the AP and disable foreground scanning */
52406 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
52407 +                if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
52408 +                    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
52409 +                    wmi_disconnect_cmd(ar->arWmi);
52410 +                } else {
52411 +                    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
52412 +                }
52413 +
52414 +                if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0xFF, 0) != A_OK)
52415 +                {
52416 +                    ret = -EIO;
52417 +                }
52418 +            }
52419 +            break;
52420 +        case AR6000_XIOCTL_WMI_GET_ROAM_DATA:
52421 +            ret = ar6000_ioctl_get_roam_data(dev, rq);
52422 +            break;
52423 +        case AR6000_XIOCTL_WMI_SET_BT_STATUS:
52424 +            ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata);
52425 +            break;
52426 +        case AR6000_XIOCTL_WMI_SET_BT_PARAMS:
52427 +            ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata);
52428 +            break;
52429 +        case AR6000_XIOCTL_WMI_STARTSCAN:
52430 +        {
52431 +            WMI_START_SCAN_CMD setStartScanCmd;
52432 +
52433 +            if (ar->arWmiReady == FALSE) {
52434 +                    ret = -EIO;
52435 +                } else if (copy_from_user(&setStartScanCmd, userdata,
52436 +                                          sizeof(setStartScanCmd)))
52437 +                {
52438 +                    ret = -EFAULT;
52439 +                } else {
52440 +                    if (wmi_startscan_cmd(ar->arWmi, setStartScanCmd.scanType,
52441 +                                    setStartScanCmd.forceFgScan,
52442 +                                    setStartScanCmd.isLegacy,
52443 +                                    setStartScanCmd.homeDwellTime,
52444 +                                    setStartScanCmd.forceScanInterval) != A_OK)
52445 +                    {
52446 +                        ret = -EIO;
52447 +                    }
52448 +                }
52449 +            break;
52450 +        }
52451 +        case AR6000_XIOCTL_WMI_SETFIXRATES:
52452 +        {
52453 +            WMI_FIX_RATES_CMD setFixRatesCmd;
52454 +            A_STATUS returnStatus;
52455 +
52456 +            if (ar->arWmiReady == FALSE) {
52457 +                    ret = -EIO;
52458 +                } else if (copy_from_user(&setFixRatesCmd, userdata,
52459 +                                          sizeof(setFixRatesCmd)))
52460 +                {
52461 +                    ret = -EFAULT;
52462 +                } else {
52463 +                    returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask);
52464 +                    if (returnStatus == A_EINVAL)
52465 +                    {
52466 +                        ret = -EINVAL;
52467 +                    }
52468 +                    else if(returnStatus != A_OK) {
52469 +                        ret = -EIO;
52470 +                    }
52471 +                }
52472 +            break;
52473 +        }
52474 +
52475 +        case AR6000_XIOCTL_WMI_GETFIXRATES:
52476 +        {
52477 +            WMI_FIX_RATES_CMD getFixRatesCmd;
52478 +            AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
52479 +            int ret = 0;
52480 +
52481 +            if (ar->arWmiReady == FALSE) {
52482 +                return -EIO;
52483 +            }
52484 +
52485 +            if (down_interruptible(&ar->arSem)) {
52486 +                return -ERESTARTSYS;
52487 +            }
52488 +            /* Used copy_from_user/copy_to_user to access user space data */
52489 +            if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) {
52490 +                ret = -EFAULT;
52491 +            } else {
52492 +                ar->arRateMask = 0xFFFF;
52493 +
52494 +                if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) {
52495 +                    up(&ar->arSem);
52496 +                    return -EIO;
52497 +                }
52498 +
52499 +                wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFF, wmitimeout * HZ);
52500 +
52501 +                if (signal_pending(current)) {
52502 +                    ret = -EINTR;
52503 +                }
52504 +
52505 +                if (!ret) {
52506 +                    getFixRatesCmd.fixRateMask = ar->arRateMask;
52507 +                }
52508 +
52509 +                if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) {
52510 +                   ret = -EFAULT;
52511 +                }
52512 +
52513 +                up(&ar->arSem);
52514 +            }
52515 +            break;
52516 +        }
52517 +        case AR6000_XIOCTL_WMI_SET_AUTHMODE:
52518 +        {
52519 +            WMI_SET_AUTH_MODE_CMD setAuthMode;
52520 +
52521 +            if (ar->arWmiReady == FALSE) {
52522 +                ret = -EIO;
52523 +            } else if (copy_from_user(&setAuthMode, userdata,
52524 +                                      sizeof(setAuthMode)))
52525 +            {
52526 +                ret = -EFAULT;
52527 +            } else {
52528 +                if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK)
52529 +                {
52530 +                    ret = -EIO;
52531 +                }
52532 +            }
52533 +            break;
52534 +        }
52535 +        case AR6000_XIOCTL_WMI_SET_REASSOCMODE:
52536 +        {
52537 +            WMI_SET_REASSOC_MODE_CMD setReassocMode;
52538 +
52539 +            if (ar->arWmiReady == FALSE) {
52540 +                ret = -EIO;
52541 +            } else if (copy_from_user(&setReassocMode, userdata,
52542 +                                      sizeof(setReassocMode)))
52543 +            {
52544 +                ret = -EFAULT;
52545 +            } else {
52546 +                if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK)
52547 +                {
52548 +                    ret = -EIO;
52549 +                }
52550 +            }
52551 +            break;
52552 +        }
52553 +        case AR6000_XIOCTL_DIAG_READ:
52554 +        {
52555 +            A_UINT32 addr, data;
52556 +            get_user(addr, (unsigned int *)userdata);
52557 +            if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
52558 +                ret = -EIO;
52559 +            }
52560 +            put_user(data, (unsigned int *)userdata + 1);
52561 +            break;
52562 +        }
52563 +        case AR6000_XIOCTL_DIAG_WRITE:
52564 +        {
52565 +            A_UINT32 addr, data;
52566 +            get_user(addr, (unsigned int *)userdata);
52567 +            get_user(data, (unsigned int *)userdata + 1);
52568 +            if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
52569 +                ret = -EIO;
52570 +            }
52571 +            break;
52572 +        }
52573 +        case AR6000_XIOCTL_WMI_SET_KEEPALIVE:
52574 +        {
52575 +             WMI_SET_KEEPALIVE_CMD setKeepAlive;
52576 +             if (ar->arWmiReady == FALSE) {
52577 +                 return -EIO;
52578 +             } else if (copy_from_user(&setKeepAlive, userdata,
52579 +                        sizeof(setKeepAlive))){
52580 +                 ret = -EFAULT;
52581 +             } else {
52582 +                 if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) {
52583 +                     ret = -EIO;
52584 +               }
52585 +             }
52586 +             break;
52587 +        }
52588 +        case AR6000_XIOCTL_WMI_GET_KEEPALIVE:
52589 +        {
52590 +            AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
52591 +            WMI_GET_KEEPALIVE_CMD getKeepAlive;
52592 +            int ret = 0;
52593 +            if (ar->arWmiReady == FALSE) {
52594 +               return -EIO;
52595 +            }
52596 +            if (down_interruptible(&ar->arSem)) {
52597 +                return -ERESTARTSYS;
52598 +            }
52599 +            if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) {
52600 +               ret = -EFAULT;
52601 +            } else {
52602 +            getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi);
52603 +            ar->arKeepaliveConfigured = 0xFF;
52604 +            if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){
52605 +                up(&ar->arSem);
52606 +                return -EIO;
52607 +            }
52608 +            wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ);
52609 +            if (signal_pending(current)) {
52610 +                ret = -EINTR;
52611 +            }
52612 +
52613 +            if (!ret) {
52614 +                getKeepAlive.configured = ar->arKeepaliveConfigured;
52615 +            }
52616 +            if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) {
52617 +               ret = -EFAULT;
52618 +            }
52619 +            up(&ar->arSem);
52620 +            }
52621 +            break;
52622 +        }
52623 +        case AR6000_XIOCTL_WMI_SET_APPIE:
52624 +        {
52625 +            WMI_SET_APPIE_CMD appIEcmd;
52626 +            A_UINT8           appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN];
52627 +            A_UINT32            fType,ieLen;
52628 +
52629 +           if (ar->arWmiReady == FALSE) {
52630 +                   return -EIO;
52631 +           }
52632 +           get_user(fType, (A_UINT32 *)userdata);
52633 +           appIEcmd.mgmtFrmType = fType;
52634 +           if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) {
52635 +                   ret = -EIO;
52636 +           } else {
52637 +                   get_user(ieLen, (A_UINT32 *)(userdata + 4));
52638 +                   appIEcmd.ieLen = ieLen;
52639 +                   if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) {
52640 +                           ret = -EIO;
52641 +                           break;
52642 +                   }
52643 +                   if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) {
52644 +                           ret = -EFAULT;
52645 +                   } else {
52646 +                           if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType,
52647 +                                                 appIEcmd.ieLen,  appIeInfo) != A_OK)
52648 +                           {
52649 +                                   ret = -EIO;
52650 +                           }
52651 +                   }
52652 +            }
52653 +            break;
52654 +        }
52655 +        case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER:
52656 +        {
52657 +            WMI_BSS_FILTER_CMD cmd;
52658 +            A_UINT32    filterType;
52659 +
52660 +            if (copy_from_user(&filterType, userdata, sizeof(A_UINT32)))
52661 +            {
52662 +                return -EFAULT;
52663 +            }
52664 +            if (filterType & (IEEE80211_FILTER_TYPE_BEACON |
52665 +                                    IEEE80211_FILTER_TYPE_PROBE_RESP))
52666 +            {
52667 +                cmd.bssFilter = ALL_BSS_FILTER;
52668 +            } else {
52669 +                cmd.bssFilter = NONE_BSS_FILTER;
52670 +            }
52671 +            if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) {
52672 +                ret = -EIO;
52673 +            }
52674 +
52675 +            AR6000_SPIN_LOCK(&ar->arLock, 0);
52676 +            ar->arMgmtFilter = filterType;
52677 +            AR6000_SPIN_UNLOCK(&ar->arLock, 0);
52678 +            break;
52679 +        }
52680 +        case AR6000_XIOCTL_WMI_SET_WSC_STATUS:
52681 +        {
52682 +            A_UINT32    wsc_status;
52683 +
52684 +            if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32)))
52685 +            {
52686 +                return -EFAULT;
52687 +            }
52688 +            if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) {
52689 +                ret = -EIO;
52690 +            }
52691 +            break;
52692 +        }
52693 +        case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL:
52694 +        {
52695 +            A_UINT32 ROM_addr;
52696 +            A_UINT32 RAM_addr;
52697 +            A_UINT32 nbytes;
52698 +            A_UINT32 do_activate;
52699 +            A_UINT32 rompatch_id;
52700 +
52701 +            get_user(ROM_addr, (A_UINT32 *)userdata);
52702 +            get_user(RAM_addr, (A_UINT32 *)userdata + 1);
52703 +            get_user(nbytes, (A_UINT32 *)userdata + 2);
52704 +            get_user(do_activate, (A_UINT32 *)userdata + 3);
52705 +            AR_DEBUG_PRINTF("Install rompatch from ROM: 0x%x to RAM: 0x%x  length: %d\n",
52706 +                             ROM_addr, RAM_addr, nbytes);
52707 +            ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr,
52708 +                                        nbytes, do_activate, &rompatch_id);
52709 +            if (ret == A_OK) {
52710 +                put_user(rompatch_id, (unsigned int *)rq->ifr_data); /* return value */
52711 +            }
52712 +            break;
52713 +        }
52714 +
52715 +        case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL:
52716 +        {
52717 +            A_UINT32 rompatch_id;
52718 +
52719 +            get_user(rompatch_id, (A_UINT32 *)userdata);
52720 +            AR_DEBUG_PRINTF("UNinstall rompatch_id %d\n", rompatch_id);
52721 +            ret = BMIrompatchUninstall(hifDevice, rompatch_id);
52722 +            break;
52723 +        }
52724 +
52725 +        case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE:
52726 +        case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE:
52727 +        {
52728 +            A_UINT32 rompatch_count;
52729 +
52730 +            get_user(rompatch_count, (A_UINT32 *)userdata);
52731 +            AR_DEBUG_PRINTF("Change rompatch activation count=%d\n", rompatch_count);
52732 +            length = sizeof(A_UINT32) * rompatch_count;
52733 +            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
52734 +                A_MEMZERO(buffer, length);
52735 +                if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length))
52736 +                {
52737 +                    ret = -EFAULT;
52738 +                } else {
52739 +                    if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) {
52740 +                        ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
52741 +                    } else {
52742 +                        ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
52743 +                    }
52744 +                }
52745 +                A_FREE(buffer);
52746 +            } else {
52747 +                ret = -ENOMEM;
52748 +            }
52749 +
52750 +            break;
52751 +        }
52752 +
52753 +        case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE:
52754 +        {
52755 +            WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode;
52756 +
52757 +            if (ar->arWmiReady == FALSE) {
52758 +                ret = -EIO;
52759 +            } else if (copy_from_user(&setHostSleepMode, userdata,
52760 +                                      sizeof(setHostSleepMode)))
52761 +            {
52762 +                ret = -EFAULT;
52763 +            } else {
52764 +                if (wmi_set_host_sleep_mode_cmd(ar->arWmi,
52765 +                                &setHostSleepMode) != A_OK)
52766 +                {
52767 +                    ret = -EIO;
52768 +                }
52769 +            }
52770 +            break;
52771 +        }
52772 +        case AR6000_XIOCTL_WMI_SET_WOW_MODE:
52773 +        {
52774 +            WMI_SET_WOW_MODE_CMD setWowMode;
52775 +
52776 +            if (ar->arWmiReady == FALSE) {
52777 +                ret = -EIO;
52778 +            } else if (copy_from_user(&setWowMode, userdata,
52779 +                                      sizeof(setWowMode)))
52780 +            {
52781 +                ret = -EFAULT;
52782 +            } else {
52783 +                if (wmi_set_wow_mode_cmd(ar->arWmi,
52784 +                                &setWowMode) != A_OK)
52785 +                {
52786 +                    ret = -EIO;
52787 +                }
52788 +            }
52789 +            break;
52790 +        }
52791 +        case AR6000_XIOCTL_WMI_GET_WOW_LIST:
52792 +        {
52793 +            WMI_GET_WOW_LIST_CMD getWowList;
52794 +
52795 +            if (ar->arWmiReady == FALSE) {
52796 +                ret = -EIO;
52797 +            } else if (copy_from_user(&getWowList, userdata,
52798 +                                      sizeof(getWowList)))
52799 +            {
52800 +                ret = -EFAULT;
52801 +            } else {
52802 +                if (wmi_get_wow_list_cmd(ar->arWmi,
52803 +                                &getWowList) != A_OK)
52804 +                {
52805 +                    ret = -EIO;
52806 +                }
52807 +            }
52808 +            break;
52809 +        }
52810 +        case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN:
52811 +        {
52812 +#define WOW_PATTERN_SIZE 64
52813 +#define WOW_MASK_SIZE 64
52814 +
52815 +            WMI_ADD_WOW_PATTERN_CMD cmd;
52816 +            A_UINT8 mask_data[WOW_PATTERN_SIZE]={0};
52817 +            A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0};
52818 +
52819 +            if (ar->arWmiReady == FALSE) {
52820 +                ret = -EIO;
52821 +            } else {
52822 +
52823 +                if(copy_from_user(&cmd, userdata,
52824 +                            sizeof(WMI_ADD_WOW_PATTERN_CMD)))
52825 +                      return -EFAULT;
52826 +                if (copy_from_user(pattern_data,
52827 +                                      userdata + 3,
52828 +                                      cmd.filter_size)){
52829 +                        ret = -EFAULT;
52830 +                        break;
52831 +                }
52832 +                if (copy_from_user(mask_data,
52833 +                                      (userdata + 3 + cmd.filter_size),
52834 +                                      cmd.filter_size)){
52835 +                        ret = -EFAULT;
52836 +                        break;
52837 +                } else {
52838 +                    if (wmi_add_wow_pattern_cmd(ar->arWmi,
52839 +                                &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK){
52840 +                        ret = -EIO;
52841 +                    }
52842 +                }
52843 +            }
52844 +#undef WOW_PATTERN_SIZE
52845 +#undef WOW_MASK_SIZE
52846 +            break;
52847 +        }
52848 +        case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN:
52849 +        {
52850 +            WMI_DEL_WOW_PATTERN_CMD delWowPattern;
52851 +
52852 +            if (ar->arWmiReady == FALSE) {
52853 +                ret = -EIO;
52854 +            } else if (copy_from_user(&delWowPattern, userdata,
52855 +                                      sizeof(delWowPattern)))
52856 +            {
52857 +                ret = -EFAULT;
52858 +            } else {
52859 +                if (wmi_del_wow_pattern_cmd(ar->arWmi,
52860 +                                &delWowPattern) != A_OK)
52861 +                {
52862 +                    ret = -EIO;
52863 +                }
52864 +            }
52865 +            break;
52866 +        }
52867 +        case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE:
52868 +            if (ar->arHtcTarget != NULL) {
52869 +                HTCDumpCreditStates(ar->arHtcTarget);
52870 +            }
52871 +            break;
52872 +        case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE:
52873 +            if (ar->arHtcTarget != NULL) {
52874 +                struct ar6000_traffic_activity_change data;
52875 +
52876 +                if (copy_from_user(&data, userdata, sizeof(data)))
52877 +                {
52878 +                    return -EFAULT;
52879 +                }
52880 +                    /* note, this is used for testing (mbox ping testing), indicate activity
52881 +                     * change using the stream ID as the traffic class */
52882 +                ar6000_indicate_tx_activity(ar,
52883 +                                            (A_UINT8)data.StreamID,
52884 +                                            data.Active ? TRUE : FALSE);
52885 +            }
52886 +            break;
52887 +        case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS:
52888 +            if (ar->arWmiReady == FALSE) {
52889 +                ret = -EIO;
52890 +            } else if (copy_from_user(&connectCtrlFlags, userdata,
52891 +                                      sizeof(connectCtrlFlags)))
52892 +            {
52893 +                ret = -EFAULT;
52894 +            } else {
52895 +                ar->arConnectCtrlFlags = connectCtrlFlags;
52896 +            }
52897 +            break;
52898 +        case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS:
52899 +            if (ar->arWmiReady == FALSE) {
52900 +                ret = -EIO;
52901 +            } else if (copy_from_user(&akmpParams, userdata,
52902 +                                      sizeof(WMI_SET_AKMP_PARAMS_CMD)))
52903 +            {
52904 +                ret = -EFAULT;
52905 +            } else {
52906 +                if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) {
52907 +                    ret = -EIO;
52908 +                }
52909 +            }
52910 +            break;
52911 +        case AR6000_XIOCTL_WMI_SET_PMKID_LIST:
52912 +            if (ar->arWmiReady == FALSE) {
52913 +                ret = -EIO;
52914 +            } else {
52915 +                if (copy_from_user(&pmkidInfo.numPMKID, userdata,
52916 +                                      sizeof(pmkidInfo.numPMKID)))
52917 +                {
52918 +                    ret = -EFAULT;
52919 +                    break;
52920 +                }
52921 +                if (copy_from_user(&pmkidInfo.pmkidList,
52922 +                                   userdata + sizeof(pmkidInfo.numPMKID),
52923 +                                   pmkidInfo.numPMKID * sizeof(WMI_PMKID)))
52924 +                {
52925 +                    ret = -EFAULT;
52926 +                    break;
52927 +                }
52928 +                if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) {
52929 +                    ret = -EIO;
52930 +                }
52931 +            }
52932 +            break;
52933 +        case AR6000_XIOCTL_WMI_GET_PMKID_LIST:
52934 +            if (ar->arWmiReady == FALSE) {
52935 +                ret = -EIO;
52936 +            } else  {
52937 +                if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) {
52938 +                    ret = -EIO;
52939 +                }
52940 +            }
52941 +            break;
52942 +        default:
52943 +            ret = -EOPNOTSUPP;
52944 +    }
52945 +    return ret;
52946 +}
52947 +
52948 --- /dev/null
52949 +++ b/drivers/ar6000/ar6000/netbuf.c
52950 @@ -0,0 +1,225 @@
52951 +
52952 +/*
52953 + *
52954 + * Copyright (c) 2004-2007 Atheros Communications Inc.
52955 + * All rights reserved.
52956 + *
52957 + *
52958 + *  This program is free software; you can redistribute it and/or modify
52959 + *  it under the terms of the GNU General Public License version 2 as
52960 + *  published by the Free Software Foundation;
52961 + *
52962 + *  Software distributed under the License is distributed on an "AS
52963 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
52964 + *  implied. See the License for the specific language governing
52965 + *  rights and limitations under the License.
52966 + *
52967 + *
52968 + *
52969 + */
52970 +#include <linux/kernel.h>
52971 +#include <linux/skbuff.h>
52972 +#include <a_config.h>
52973 +#include "athdefs.h"
52974 +#include "a_types.h"
52975 +#include "a_osapi.h"
52976 +#include "htc_packet.h"
52977 +
52978 +#define AR6000_DATA_OFFSET    64
52979 +
52980 +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt)
52981 +{
52982 +    skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt);
52983 +}
52984 +
52985 +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt)
52986 +{
52987 +    skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt);
52988 +}
52989 +
52990 +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q)
52991 +{
52992 +    return((void *) skb_dequeue((struct sk_buff_head *) q));
52993 +}
52994 +
52995 +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q)
52996 +{
52997 +    return(skb_queue_len((struct sk_buff_head *) q));
52998 +}
52999 +
53000 +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q)
53001 +{
53002 +    return(skb_queue_empty((struct sk_buff_head *) q));
53003 +}
53004 +
53005 +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q)
53006 +{
53007 +    skb_queue_head_init((struct sk_buff_head *) q);
53008 +}
53009 +
53010 +void *
53011 +a_netbuf_alloc(int size)
53012 +{
53013 +    struct sk_buff *skb;
53014 +    skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size);
53015 +    skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET));
53016 +    return ((void *)skb);
53017 +}
53018 +
53019 +/*
53020 + * Allocate an SKB w.o. any encapsulation requirement.
53021 + */
53022 +void *
53023 +a_netbuf_alloc_raw(int size)
53024 +{
53025 +    struct sk_buff *skb;
53026 +
53027 +    skb = dev_alloc_skb(size);
53028 +
53029 +    return ((void *)skb);
53030 +}
53031 +
53032 +void
53033 +a_netbuf_free(void *bufPtr)
53034 +{
53035 +    struct sk_buff *skb = (struct sk_buff *)bufPtr;
53036 +
53037 +    dev_kfree_skb(skb);
53038 +}
53039 +
53040 +A_UINT32
53041 +a_netbuf_to_len(void *bufPtr)
53042 +{
53043 +    return (((struct sk_buff *)bufPtr)->len);
53044 +}
53045 +
53046 +void *
53047 +a_netbuf_to_data(void *bufPtr)
53048 +{
53049 +    return (((struct sk_buff *)bufPtr)->data);
53050 +}
53051 +
53052 +/*
53053 + * Add len # of bytes to the beginning of the network buffer
53054 + * pointed to by bufPtr
53055 + */
53056 +A_STATUS
53057 +a_netbuf_push(void *bufPtr, A_INT32 len)
53058 +{
53059 +    skb_push((struct sk_buff *)bufPtr, len);
53060 +
53061 +    return A_OK;
53062 +}
53063 +
53064 +/*
53065 + * Add len # of bytes to the beginning of the network buffer
53066 + * pointed to by bufPtr and also fill with data
53067 + */
53068 +A_STATUS
53069 +a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len)
53070 +{
53071 +    skb_push((struct sk_buff *) bufPtr, len);
53072 +    A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len);
53073 +
53074 +    return A_OK;
53075 +}
53076 +
53077 +/*
53078 + * Add len # of bytes to the end of the network buffer
53079 + * pointed to by bufPtr
53080 + */
53081 +A_STATUS
53082 +a_netbuf_put(void *bufPtr, A_INT32 len)
53083 +{
53084 +    skb_put((struct sk_buff *)bufPtr, len);
53085 +
53086 +    return A_OK;
53087 +}
53088 +
53089 +/*
53090 + * Add len # of bytes to the end of the network buffer
53091 + * pointed to by bufPtr and also fill with data
53092 + */
53093 +A_STATUS
53094 +a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len)
53095 +{
53096 +    char *start = ((struct sk_buff *)bufPtr)->data +
53097 +        ((struct sk_buff *)bufPtr)->len;
53098 +    skb_put((struct sk_buff *)bufPtr, len);
53099 +    A_MEMCPY(start, srcPtr, len);
53100 +
53101 +    return A_OK;
53102 +}
53103 +
53104 +
53105 +/*
53106 + * Trim the network buffer pointed to by bufPtr to len # of bytes
53107 + */
53108 +A_STATUS
53109 +a_netbuf_setlen(void *bufPtr, A_INT32 len)
53110 +{
53111 +    skb_trim((struct sk_buff *)bufPtr, len);
53112 +
53113 +    return A_OK;
53114 +}
53115 +
53116 +/*
53117 + * Chop of len # of bytes from the end of the buffer.
53118 + */
53119 +A_STATUS
53120 +a_netbuf_trim(void *bufPtr, A_INT32 len)
53121 +{
53122 +    skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
53123 +
53124 +    return A_OK;
53125 +}
53126 +
53127 +/*
53128 + * Chop of len # of bytes from the end of the buffer and return the data.
53129 + */
53130 +A_STATUS
53131 +a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len)
53132 +{
53133 +    char *start = ((struct sk_buff *)bufPtr)->data +
53134 +        (((struct sk_buff *)bufPtr)->len - len);
53135 +
53136 +    A_MEMCPY(dstPtr, start, len);
53137 +    skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
53138 +
53139 +    return A_OK;
53140 +}
53141 +
53142 +
53143 +/*
53144 + * Returns the number of bytes available to a a_netbuf_push()
53145 + */
53146 +A_INT32
53147 +a_netbuf_headroom(void *bufPtr)
53148 +{
53149 +    return (skb_headroom((struct sk_buff *)bufPtr));
53150 +}
53151 +
53152 +/*
53153 + * Removes specified number of bytes from the beginning of the buffer
53154 + */
53155 +A_STATUS
53156 +a_netbuf_pull(void *bufPtr, A_INT32 len)
53157 +{
53158 +    skb_pull((struct sk_buff *)bufPtr, len);
53159 +
53160 +    return A_OK;
53161 +}
53162 +
53163 +/*
53164 + * Removes specified number of bytes from the beginning of the buffer
53165 + * and return the data
53166 + */
53167 +A_STATUS
53168 +a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len)
53169 +{
53170 +    A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len);
53171 +    skb_pull((struct sk_buff *)bufPtr, len);
53172 +
53173 +    return A_OK;
53174 +}
53175 +
53176 --- /dev/null
53177 +++ b/drivers/ar6000/ar6000/osapi_linux.h
53178 @@ -0,0 +1,319 @@
53179 +/*
53180 + * $Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/include/osapi_linux.h#1 $
53181 + *
53182 + * This file contains the definitions of the basic atheros data types.
53183 + * It is used to map the data types in atheros files to a platform specific
53184 + * type.
53185 + *
53186 + * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
53187 + *
53188 + *
53189 + *  This program is free software; you can redistribute it and/or modify
53190 + *  it under the terms of the GNU General Public License version 2 as
53191 + *  published by the Free Software Foundation;
53192 + *
53193 + *  Software distributed under the License is distributed on an "AS
53194 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
53195 + *  implied. See the License for the specific language governing
53196 + *  rights and limitations under the License.
53197 + *
53198 + *
53199 + *
53200 + */
53201 +
53202 +#ifndef _OSAPI_LINUX_H_
53203 +#define _OSAPI_LINUX_H_
53204 +
53205 +#ifdef __KERNEL__
53206 +
53207 +#include <linux/version.h>
53208 +#include <linux/types.h>
53209 +#include <linux/kernel.h>
53210 +#include <linux/string.h>
53211 +#include <linux/skbuff.h>
53212 +#include <linux/netdevice.h>
53213 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
53214 +#include <linux/jiffies.h>
53215 +#endif
53216 +#include <linux/timer.h>
53217 +#include <linux/delay.h>
53218 +#include <linux/wait.h>
53219 +#ifdef KERNEL_2_4
53220 +#include <asm/arch/irq.h>
53221 +#include <asm/irq.h>
53222 +#endif
53223 +
53224 +#ifdef __GNUC__
53225 +#define __ATTRIB_PACK           __attribute__ ((packed))
53226 +#define __ATTRIB_PRINTF         __attribute__ ((format (printf, 1, 2)))
53227 +#define __ATTRIB_NORETURN       __attribute__ ((noreturn))
53228 +#ifndef INLINE
53229 +#define INLINE                  __inline__
53230 +#endif
53231 +#else /* Not GCC */
53232 +#define __ATTRIB_PACK
53233 +#define __ATTRIB_PRINTF
53234 +#define __ATTRIB_NORETURN
53235 +#ifndef INLINE
53236 +#define INLINE                  __inline
53237 +#endif
53238 +#endif /* End __GNUC__ */
53239 +
53240 +#define PREPACK
53241 +#define POSTPACK                __ATTRIB_PACK
53242 +
53243 +/*
53244 + * Endianes macros
53245 + */
53246 +#define A_BE2CPU8(x)       ntohb(x)
53247 +#define A_BE2CPU16(x)      ntohs(x)
53248 +#define A_BE2CPU32(x)      ntohl(x)
53249 +
53250 +#define A_LE2CPU8(x)       (x)
53251 +#define A_LE2CPU16(x)      (x)
53252 +#define A_LE2CPU32(x)      (x)
53253 +
53254 +#define A_CPU2BE8(x)       htonb(x)
53255 +#define A_CPU2BE16(x)      htons(x)
53256 +#define A_CPU2BE32(x)      htonl(x)
53257 +
53258 +#define A_MEMCPY(dst, src, len)         memcpy((A_UINT8 *)(dst), (src), (len))
53259 +#define A_MEMZERO(addr, len)            memset(addr, 0, len)
53260 +#define A_MEMCMP(addr1, addr2, len)     memcmp((addr1), (addr2), (len))
53261 +#define A_MALLOC(size)                  kmalloc((size), GFP_KERNEL)
53262 +#define A_MALLOC_NOWAIT(size)           kmalloc((size), GFP_ATOMIC)
53263 +#define A_FREE(addr)                    kfree(addr)
53264 +#define A_PRINTF(args...)               printk(args)
53265 +
53266 +/* Mutual Exclusion */
53267 +typedef spinlock_t                      A_MUTEX_T;
53268 +#define A_MUTEX_INIT(mutex)             spin_lock_init(mutex)
53269 +#define A_MUTEX_LOCK(mutex)             spin_lock_bh(mutex)
53270 +#define A_MUTEX_UNLOCK(mutex)           spin_unlock_bh(mutex)
53271 +#define A_IS_MUTEX_VALID(mutex)         TRUE  /* okay to return true, since A_MUTEX_DELETE does nothing */
53272 +#define A_MUTEX_DELETE(mutex)           /* spin locks are not kernel resources so nothing to free.. */
53273 +
53274 +/* Get current time in ms adding a constant offset (in ms) */
53275 +#define A_GET_MS(offset)    \
53276 +       (jiffies + ((offset) / 1000) * HZ)
53277 +
53278 +/*
53279 + * Timer Functions
53280 + */
53281 +#define A_MDELAY(msecs)                 mdelay(msecs)
53282 +typedef struct timer_list               A_TIMER;
53283 +
53284 +#define A_INIT_TIMER(pTimer, pFunction, pArg) do {              \
53285 +    init_timer(pTimer);                                         \
53286 +    (pTimer)->function = (pFunction);                           \
53287 +    (pTimer)->data   = (unsigned long)(pArg);                   \
53288 +} while (0)
53289 +
53290 +/*
53291 + * Start a Timer that elapses after 'periodMSec' milli-seconds
53292 + * Support is provided for a one-shot timer. The 'repeatFlag' is
53293 + * ignored.
53294 + */
53295 +#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do {                   \
53296 +    if (repeatFlag) {                                                       \
53297 +        printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__);     \
53298 +        panic("Timer Repeat");                                              \
53299 +    }                                                                       \
53300 +    mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000);                \
53301 +} while (0)
53302 +
53303 +/*
53304 + * Cancel the Timer.
53305 + */
53306 +#define A_UNTIMEOUT(pTimer) do {                                \
53307 +    del_timer((pTimer));                                        \
53308 +} while (0)
53309 +
53310 +#define A_DELETE_TIMER(pTimer) do {                             \
53311 +} while (0)
53312 +
53313 +/*
53314 + * Wait Queue related functions
53315 + */
53316 +typedef wait_queue_head_t               A_WAITQUEUE_HEAD;
53317 +#define A_INIT_WAITQUEUE_HEAD(head)     init_waitqueue_head(head)
53318 +#ifndef wait_event_interruptible_timeout
53319 +#define __wait_event_interruptible_timeout(wq, condition, ret)          \
53320 +do {                                                                    \
53321 +        wait_queue_t __wait;                                            \
53322 +        init_waitqueue_entry(&__wait, current);                         \
53323 +                                                                        \
53324 +        add_wait_queue(&wq, &__wait);                                   \
53325 +        for (;;) {                                                      \
53326 +                set_current_state(TASK_INTERRUPTIBLE);                  \
53327 +                if (condition)                                          \
53328 +                        break;                                          \
53329 +                if (!signal_pending(current)) {                         \
53330 +                        ret = schedule_timeout(ret);                    \
53331 +                        if (!ret)                                       \
53332 +                                break;                                  \
53333 +                        continue;                                       \
53334 +                }                                                       \
53335 +                ret = -ERESTARTSYS;                                     \
53336 +                break;                                                  \
53337 +        }                                                               \
53338 +        current->state = TASK_RUNNING;                                  \
53339 +        remove_wait_queue(&wq, &__wait);                                \
53340 +} while (0)
53341 +
53342 +#define wait_event_interruptible_timeout(wq, condition, timeout)        \
53343 +({                                                                      \
53344 +        long __ret = timeout;                                           \
53345 +        if (!(condition))                                               \
53346 +                __wait_event_interruptible_timeout(wq, condition, __ret); \
53347 +        __ret;                                                          \
53348 +})
53349 +#endif /* wait_event_interruptible_timeout */
53350 +
53351 +#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \
53352 +    wait_event_interruptible_timeout(head, condition, timeout); \
53353 +} while (0)
53354 +
53355 +#define A_WAKE_UP(head)                 wake_up(head)
53356 +
53357 +#ifdef DEBUG
53358 +#define A_ASSERT(expr)  \
53359 +    if (!(expr)) {   \
53360 +        printk(KERN_ALERT "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
53361 +        panic(#expr); \
53362 +    }
53363 +
53364 +#else
53365 +#define A_ASSERT(expr)
53366 +#endif /* DEBUG */
53367 +
53368 +/*
53369 + * Initialization of the network buffer subsystem
53370 + */
53371 +#define A_NETBUF_INIT()
53372 +
53373 +/*
53374 + * Network buffer queue support
53375 + */
53376 +typedef struct sk_buff_head A_NETBUF_QUEUE_T;
53377 +
53378 +#define A_NETBUF_QUEUE_INIT(q)  \
53379 +    a_netbuf_queue_init(q)
53380 +
53381 +#define A_NETBUF_ENQUEUE(q, pkt) \
53382 +    a_netbuf_enqueue((q), (pkt))
53383 +#define A_NETBUF_PREQUEUE(q, pkt) \
53384 +    a_netbuf_prequeue((q), (pkt))
53385 +#define A_NETBUF_DEQUEUE(q) \
53386 +    (a_netbuf_dequeue(q))
53387 +#define A_NETBUF_QUEUE_SIZE(q)  \
53388 +    a_netbuf_queue_size(q)
53389 +#define A_NETBUF_QUEUE_EMPTY(q) \
53390 +    a_netbuf_queue_empty(q)
53391 +
53392 +/*
53393 + * Network buffer support
53394 + */
53395 +#define A_NETBUF_ALLOC(size) \
53396 +    a_netbuf_alloc(size)
53397 +#define A_NETBUF_ALLOC_RAW(size) \
53398 +    a_netbuf_alloc_raw(size)
53399 +#define A_NETBUF_FREE(bufPtr) \
53400 +    a_netbuf_free(bufPtr)
53401 +#define A_NETBUF_DATA(bufPtr) \
53402 +    a_netbuf_to_data(bufPtr)
53403 +#define A_NETBUF_LEN(bufPtr) \
53404 +    a_netbuf_to_len(bufPtr)
53405 +#define A_NETBUF_PUSH(bufPtr, len) \
53406 +    a_netbuf_push(bufPtr, len)
53407 +#define A_NETBUF_PUT(bufPtr, len) \
53408 +    a_netbuf_put(bufPtr, len)
53409 +#define A_NETBUF_TRIM(bufPtr,len) \
53410 +    a_netbuf_trim(bufPtr, len)
53411 +#define A_NETBUF_PULL(bufPtr, len) \
53412 +    a_netbuf_pull(bufPtr, len)
53413 +#define A_NETBUF_HEADROOM(bufPtr)\
53414 +    a_netbuf_headroom(bufPtr)
53415 +#define A_NETBUF_SETLEN(bufPtr,len) \
53416 +    a_netbuf_setlen(bufPtr, len)
53417 +
53418 +/* Add data to end of a buffer  */
53419 +#define A_NETBUF_PUT_DATA(bufPtr, srcPtr,  len) \
53420 +    a_netbuf_put_data(bufPtr, srcPtr, len)
53421 +
53422 +/* Add data to start of the  buffer */
53423 +#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr,  len) \
53424 +    a_netbuf_push_data(bufPtr, srcPtr, len)
53425 +
53426 +/* Remove data at start of the buffer */
53427 +#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \
53428 +    a_netbuf_pull_data(bufPtr, dstPtr, len)
53429 +
53430 +/* Remove data from the end of the buffer */
53431 +#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \
53432 +    a_netbuf_trim_data(bufPtr, dstPtr, len)
53433 +
53434 +/* View data as "size" contiguous bytes of type "t" */
53435 +#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \
53436 +    (t )( ((struct skbuf *)(bufPtr))->data)
53437 +
53438 +/* return the beginning of the headroom for the buffer */
53439 +#define A_NETBUF_HEAD(bufPtr) \
53440 +        ((((struct sk_buff *)(bufPtr))->head))
53441 +
53442 +/*
53443 + * OS specific network buffer access routines
53444 + */
53445 +void *a_netbuf_alloc(int size);
53446 +void *a_netbuf_alloc_raw(int size);
53447 +void a_netbuf_free(void *bufPtr);
53448 +void *a_netbuf_to_data(void *bufPtr);
53449 +A_UINT32 a_netbuf_to_len(void *bufPtr);
53450 +A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len);
53451 +A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len);
53452 +A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len);
53453 +A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len);
53454 +A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len);
53455 +A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len);
53456 +A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len);
53457 +A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len);
53458 +A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len);
53459 +A_INT32 a_netbuf_headroom(void *bufPtr);
53460 +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt);
53461 +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt);
53462 +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q);
53463 +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q);
53464 +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
53465 +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
53466 +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q);
53467 +
53468 +/*
53469 + * Kernel v.s User space functions
53470 + */
53471 +A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n);
53472 +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n);
53473 +
53474 +#else /* __KERNEL__ */
53475 +
53476 +#ifdef __GNUC__
53477 +#define __ATTRIB_PACK           __attribute__ ((packed))
53478 +#define __ATTRIB_PRINTF         __attribute__ ((format (printf, 1, 2)))
53479 +#define __ATTRIB_NORETURN       __attribute__ ((noreturn))
53480 +#ifndef INLINE
53481 +#define INLINE                  __inline__
53482 +#endif
53483 +#else /* Not GCC */
53484 +#define __ATTRIB_PACK
53485 +#define __ATTRIB_PRINTF
53486 +#define __ATTRIB_NORETURN
53487 +#ifndef INLINE
53488 +#define INLINE                  __inline
53489 +#endif
53490 +#endif /* End __GNUC__ */
53491 +
53492 +#define PREPACK
53493 +#define POSTPACK                __ATTRIB_PACK
53494 +
53495 +#endif /* __KERNEL__ */
53496 +
53497 +#endif /* _OSAPI_LINUX_H_ */
53498 --- /dev/null
53499 +++ b/drivers/ar6000/ar6000/wireless_ext.c
53500 @@ -0,0 +1,1972 @@
53501 +/*
53502 + *
53503 + * Copyright (c) 2004-2007 Atheros Communications Inc.
53504 + * All rights reserved.
53505 + *
53506 + *
53507 + *  This program is free software; you can redistribute it and/or modify
53508 + *  it under the terms of the GNU General Public License version 2 as
53509 + *  published by the Free Software Foundation;
53510 + *
53511 + *  Software distributed under the License is distributed on an "AS
53512 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
53513 + *  implied. See the License for the specific language governing
53514 + *  rights and limitations under the License.
53515 + *
53516 + *
53517 + *
53518 + */
53519 +
53520 +#include "ar6000_drv.h"
53521 +
53522 +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
53523 +static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi);
53524 +extern unsigned int wmitimeout;
53525 +extern A_WAITQUEUE_HEAD arEvent;
53526 +extern wait_queue_head_t ar6000_scan_queue;
53527 +
53528 +/*
53529 + * Encode a WPA or RSN information element as a custom
53530 + * element using the hostap format.
53531 + */
53532 +static u_int
53533 +encode_ie(void *buf, size_t bufsize,
53534 +    const u_int8_t *ie, size_t ielen,
53535 +    const char *leader, size_t leader_len)
53536 +{
53537 +    u_int8_t *p;
53538 +    int i;
53539 +
53540 +    if (bufsize < leader_len)
53541 +        return 0;
53542 +    p = buf;
53543 +    memcpy(p, leader, leader_len);
53544 +    bufsize -= leader_len;
53545 +    p += leader_len;
53546 +    for (i = 0; i < ielen && bufsize > 2; i++)
53547 +        p += sprintf(p, "%02x", ie[i]);
53548 +    return (i == ielen ? p - (u_int8_t *)buf : 0);
53549 +}
53550 +
53551 +void
53552 +ar6000_scan_node(void *arg, bss_t *ni)
53553 +{
53554 +    struct iw_event iwe;
53555 +#if WIRELESS_EXT > 14
53556 +    char buf[64*2 + 30];
53557 +#endif
53558 +    struct ar_giwscan_param *param;
53559 +    A_CHAR *current_ev;
53560 +    A_CHAR *end_buf;
53561 +    struct ieee80211_common_ie  *cie;
53562 +       struct iw_request_info info;
53563 +
53564 +       info.cmd = 0;
53565 +       info.flags = 0;
53566 +
53567 +    param = (struct ar_giwscan_param *)arg;
53568 +
53569 +    if (param->current_ev >= param->end_buf) {
53570 +        return;
53571 +    }
53572 +    if ((param->firstPass == TRUE) &&
53573 +        ((ni->ni_cie.ie_wpa == NULL) && (ni->ni_cie.ie_rsn == NULL))) {
53574 +        /*
53575 +         * Only forward wpa bss's in first pass
53576 +         */
53577 +        return;
53578 +    }
53579 +
53580 +     if ((param->firstPass == FALSE) &&
53581 +        ((ni->ni_cie.ie_wpa != NULL) || (ni->ni_cie.ie_rsn != NULL))) {
53582 +        /*
53583 +         * Only forward non-wpa bss's in 2nd pass
53584 +         */
53585 +        return;
53586 +    }
53587 +
53588 +    current_ev = param->current_ev;
53589 +    end_buf = param->end_buf;
53590 +
53591 +    cie = &ni->ni_cie;
53592 +
53593 +    A_MEMZERO(&iwe, sizeof(iwe));
53594 +    iwe.cmd = SIOCGIWAP;
53595 +    iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
53596 +    A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6);
53597 +    current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
53598 +                                      IW_EV_ADDR_LEN);
53599 +
53600 +    A_MEMZERO(&iwe, sizeof(iwe));
53601 +    iwe.cmd = SIOCGIWESSID;
53602 +    iwe.u.data.flags = 1;
53603 +    iwe.u.data.length = cie->ie_ssid[1];
53604 +    current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
53605 +                                      &cie->ie_ssid[2]);
53606 +
53607 +    if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) {
53608 +        A_MEMZERO(&iwe, sizeof(iwe));
53609 +        iwe.cmd = SIOCGIWMODE;
53610 +        iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ?
53611 +                IW_MODE_MASTER : IW_MODE_ADHOC;
53612 +        current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
53613 +                                          IW_EV_UINT_LEN);
53614 +    }
53615 +
53616 +    A_MEMZERO(&iwe, sizeof(iwe));
53617 +    iwe.cmd = SIOCGIWFREQ;
53618 +    iwe.u.freq.m = cie->ie_chan * 100000;
53619 +    iwe.u.freq.e = 1;
53620 +    current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
53621 +                                      IW_EV_FREQ_LEN);
53622 +
53623 +    A_MEMZERO(&iwe, sizeof(iwe));
53624 +    iwe.cmd = IWEVQUAL;
53625 +    ar6000_set_quality(&iwe.u.qual, ni->ni_snr);
53626 +    current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
53627 +                                      IW_EV_QUAL_LEN);
53628 +
53629 +    A_MEMZERO(&iwe, sizeof(iwe));
53630 +    iwe.cmd = SIOCGIWENCODE;
53631 +    if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) {
53632 +        iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
53633 +    } else {
53634 +        iwe.u.data.flags = IW_ENCODE_DISABLED;
53635 +    }
53636 +    iwe.u.data.length = 0;
53637 +    current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe, "");
53638 +
53639 +    A_MEMZERO(&iwe, sizeof(iwe));
53640 +    iwe.cmd = IWEVCUSTOM;
53641 +    snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt);
53642 +    iwe.u.data.length = strlen(buf);
53643 +    current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe, buf);
53644 +
53645 +    if (cie->ie_wpa != NULL) {
53646 +        static const char wpa_leader[] = "wpa_ie=";
53647 +
53648 +        A_MEMZERO(&iwe, sizeof(iwe));
53649 +        iwe.cmd = IWEVCUSTOM;
53650 +        iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
53651 +                                      cie->ie_wpa[1]+2,
53652 +                                      wpa_leader, sizeof(wpa_leader)-1);
53653 +
53654 +        if (iwe.u.data.length != 0) {
53655 +            current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
53656 +                                                                          buf);
53657 +        }
53658 +    }
53659 +
53660 +    if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
53661 +        static const char rsn_leader[] = "rsn_ie=";
53662 +
53663 +        A_MEMZERO(&iwe, sizeof(iwe));
53664 +        iwe.cmd = IWEVCUSTOM;
53665 +        iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn,
53666 +                                      cie->ie_rsn[1]+2,
53667 +                                      rsn_leader, sizeof(rsn_leader)-1);
53668 +
53669 +        if (iwe.u.data.length != 0) {
53670 +            current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
53671 +                                                                          buf);
53672 +        }
53673 +    }
53674 +
53675 +    if (cie->ie_wmm != NULL) {
53676 +        static const char wmm_leader[] = "wmm_ie=";
53677 +
53678 +        A_MEMZERO(&iwe, sizeof(iwe));
53679 +        iwe.cmd = IWEVCUSTOM;
53680 +        iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm,
53681 +                                      cie->ie_wmm[1]+2,
53682 +                                      wmm_leader, sizeof(wmm_leader)-1);
53683 +        if (iwe.u.data.length != 0) {
53684 +            current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
53685 +                                                                          buf);
53686 +        }
53687 +    }
53688 +
53689 +    if (cie->ie_ath != NULL) {
53690 +        static const char ath_leader[] = "ath_ie=";
53691 +
53692 +        A_MEMZERO(&iwe, sizeof(iwe));
53693 +        iwe.cmd = IWEVCUSTOM;
53694 +        iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath,
53695 +                                      cie->ie_ath[1]+2,
53696 +                                      ath_leader, sizeof(ath_leader)-1);
53697 +        if (iwe.u.data.length != 0) {
53698 +            current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
53699 +                                                                          buf);
53700 +        }
53701 +    }
53702 +
53703 +    param->current_ev = current_ev;
53704 +}
53705 +
53706 +int
53707 +ar6000_ioctl_giwscan(struct net_device *dev,
53708 +            struct iw_request_info *info,
53709 +            struct iw_point *data, char *extra)
53710 +{
53711 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
53712 +    struct ar_giwscan_param param;
53713 +    int i;
53714 +
53715 +    if (ar->arWlanState == WLAN_DISABLED) {
53716 +        return -EIO;
53717 +    }
53718 +
53719 +    if (ar->arWmiReady == FALSE) {
53720 +        return -EIO;
53721 +    }
53722 +
53723 +    param.current_ev = extra;
53724 +    param.end_buf = extra + IW_SCAN_MAX_DATA;
53725 +    param.firstPass = TRUE;
53726 +
53727 +    /*
53728 +     * Do two passes to insure WPA scan candidates
53729 +     * are sorted to the front.  This is a hack to deal with
53730 +     * the wireless extensions capping scan results at
53731 +     * IW_SCAN_MAX_DATA bytes.  In densely populated environments
53732 +     * it's easy to overflow this buffer (especially with WPA/RSN
53733 +     * information elements).  Note this sorting hack does not
53734 +     * guarantee we won't overflow anyway.
53735 +     */
53736 +    for (i = 0; i < 2; i++) {
53737 +        /*
53738 +         * Translate data to WE format.
53739 +         */
53740 +        wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, &param);
53741 +        param.firstPass = FALSE;
53742 +        if (param.current_ev >= param.end_buf) {
53743 +            data->length = param.current_ev - extra;
53744 +            return -E2BIG;
53745 +        }
53746 +    }
53747 +
53748 +    if(!(data->length = param.current_ev - extra)) {
53749 +           printk("%s(): data length %d\n", __FUNCTION__, data->length);
53750 +           return -EAGAIN;
53751 +    }
53752 +    return 0;
53753 +}
53754 +
53755 +extern int reconnect_flag;
53756 +/* SIOCSIWESSID */
53757 +static int
53758 +ar6000_ioctl_siwessid(struct net_device *dev,
53759 +                     struct iw_request_info *info,
53760 +                     struct iw_point *data, char *ssid)
53761 +{
53762 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
53763 +    A_STATUS status;
53764 +    A_UINT8     arNetworkType;
53765 +
53766 +    if (ar->arWlanState == WLAN_DISABLED) {
53767 +        return -EIO;
53768 +    }
53769 +
53770 +    if (ar->arWmiReady == FALSE) {
53771 +        return -EIO;
53772 +    }
53773 +
53774 +    /*
53775 +     * iwconfig passes a string with length excluding any trailing NUL.
53776 +     * FIXME: we should be able to set an ESSID of 32 bytes, yet things fall
53777 +     * over badly if we do. So we limit the ESSID to 31 bytes.
53778 +     */
53779 +    if (data->flags && (!data->length || data->length >= sizeof(ar->arSsid))) {
53780 +        /*
53781 +         * ssid is invalid
53782 +         */
53783 +        return -EINVAL;
53784 +    }
53785 +    /* Added for bug 25178, return an IOCTL error instead of target returning
53786 +       Illegal parameter error when either the BSSID or channel is missing
53787 +       and we cannot scan during connect.
53788 +     */
53789 +    if (data->flags) {
53790 +        if (ar->arSkipScan == TRUE &&
53791 +            (ar->arChannelHint == 0 ||
53792 +             (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] &&
53793 +              !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5])))
53794 +        {
53795 +            return -EINVAL;
53796 +        }
53797 +    }
53798 +
53799 +    if (down_interruptible(&ar->arSem)) {
53800 +        return -ERESTARTSYS;
53801 +    }
53802 +
53803 +    if (ar->arTxPending[WMI_CONTROL_PRI]) {
53804 +        /*
53805 +         * sleep until the command queue drains
53806 +         */
53807 +        wait_event_interruptible_timeout(arEvent,
53808 +            ar->arTxPending[WMI_CONTROL_PRI] == 0, wmitimeout * HZ);
53809 +        if (signal_pending(current)) {
53810 +            return -EINTR;
53811 +        }
53812 +    }
53813 +
53814 +    if (!data->flags) {
53815 +        arNetworkType = ar->arNetworkType;
53816 +        ar6000_init_profile_info(ar);
53817 +        ar->arNetworkType = arNetworkType;
53818 +    }
53819 +
53820 +    /*
53821 +     * The original logic here prevented a disconnect if issuing an "essid off"
53822 +     * if no ESSID was set, presumably to prevent sending multiple disconnects
53823 +     * to the WMI.
53824 +     *
53825 +     * Unfortunately, this also meant that no disconnect was sent when we were
53826 +     * already connected, but the profile has been changed since (which also
53827 +     * clears the ESSID as a reminder that the WMI needs updating.)
53828 +     *
53829 +     * The "1 ||" makes sure we always disconnect or reconnect. The WMI doesn't
53830 +     * seem to mind being sent multiple disconnects.
53831 +     */
53832 +    if (1 || (ar->arSsidLen) || (!data->flags))
53833 +    {
53834 +        if ((!data->flags) ||
53835 +            (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) ||
53836 +            (ar->arSsidLen != (data->length)))
53837 +        {
53838 +            /*
53839 +             * SSID set previously or essid off has been issued.
53840 +             *
53841 +             * Disconnect Command is issued in two cases after wmi is ready
53842 +             * (1) ssid is different from the previous setting
53843 +             * (2) essid off has been issued
53844 +             *
53845 +             */
53846 +            if (ar->arWmiReady == TRUE) {
53847 +                reconnect_flag = 0;
53848 +                status = wmi_disconnect_cmd(ar->arWmi);
53849 +                A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
53850 +                ar->arSsidLen = 0;
53851 +                if (ar->arSkipScan == FALSE) {
53852 +                    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
53853 +                }
53854 +                if (!data->flags) {
53855 +                    up(&ar->arSem);
53856 +                    return 0;
53857 +                }
53858 +            } else {
53859 +                 up(&ar->arSem);
53860 +            }
53861 +        }
53862 +        else
53863 +        {
53864 +            /*
53865 +             * SSID is same, so we assume profile hasn't changed.
53866 +             * If the interface is up and wmi is ready, we issue
53867 +             * a reconnect cmd. Issue a reconnect only we are already
53868 +             * connected.
53869 +             */
53870 +            if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE))
53871 +            {
53872 +                reconnect_flag = TRUE;
53873 +                status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid,
53874 +                                           ar->arChannelHint);
53875 +                up(&ar->arSem);
53876 +                if (status != A_OK) {
53877 +                    return -EIO;
53878 +                }
53879 +                return 0;
53880 +            }
53881 +            else{
53882 +                /*
53883 +                 * Dont return if connect is pending.
53884 +                 */
53885 +                if(!(ar->arConnectPending)) {
53886 +                    up(&ar->arSem);
53887 +                    return 0;
53888 +                }
53889 +            }
53890 +        }
53891 +    }
53892 +
53893 +    ar->arSsidLen = data->length;
53894 +    A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
53895 +
53896 +    /* The ssid length check prevents second "essid off" from the user,
53897 +       to be treated as a connect cmd. The second "essid off" is ignored.
53898 +    */
53899 +    if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) )
53900 +    {
53901 +        AR6000_SPIN_LOCK(&ar->arLock, 0);
53902 +        if (SHARED_AUTH == ar->arDot11AuthMode) {
53903 +            ar6000_install_static_wep_keys(ar);
53904 +        }
53905 +        AR_DEBUG_PRINTF("Connect called with authmode %d dot11 auth %d"\
53906 +                        " PW crypto %d PW crypto Len %d GRP crypto %d"\
53907 +                        " GRP crypto Len %d\n",
53908 +                        ar->arAuthMode, ar->arDot11AuthMode,
53909 +                        ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
53910 +                        ar->arGroupCrypto, ar->arGroupCryptoLen);
53911 +        reconnect_flag = 0;
53912 +        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
53913 +        status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
53914 +                                 ar->arDot11AuthMode, ar->arAuthMode,
53915 +                                 ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
53916 +                                 ar->arGroupCrypto,ar->arGroupCryptoLen,
53917 +                                 ar->arSsidLen, ar->arSsid,
53918 +                                 ar->arReqBssid, ar->arChannelHint,
53919 +                                 ar->arConnectCtrlFlags);
53920 +
53921 +
53922 +        up(&ar->arSem);
53923 +
53924 +        if (status != A_OK) {
53925 +            return -EIO;
53926 +        }
53927 +        ar->arConnectPending = TRUE;
53928 +    }else{
53929 +      up(&ar->arSem);
53930 +    }
53931 +    return 0;
53932 +}
53933 +
53934 +/* SIOCGIWESSID */
53935 +static int
53936 +ar6000_ioctl_giwessid(struct net_device *dev,
53937 +                     struct iw_request_info *info,
53938 +                     struct iw_point *data, char *essid)
53939 +{
53940 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
53941 +
53942 +    if (ar->arWlanState == WLAN_DISABLED) {
53943 +        return -EIO;
53944 +    }
53945 +
53946 +    data->flags = 1;
53947 +    data->length = ar->arSsidLen;
53948 +    A_MEMCPY(essid, ar->arSsid, ar->arSsidLen);
53949 +
53950 +    return 0;
53951 +}
53952 +
53953 +
53954 +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar)
53955 +{
53956 +    A_UINT8 index;
53957 +    A_UINT8 keyUsage;
53958 +
53959 +    for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) {
53960 +        if (ar->arWepKeyList[index].arKeyLen) {
53961 +            keyUsage = GROUP_USAGE;
53962 +            if (index == ar->arDefTxKeyIndex) {
53963 +                keyUsage |= TX_USAGE;
53964 +            }
53965 +            wmi_addKey_cmd(ar->arWmi,
53966 +                           index,
53967 +                           WEP_CRYPT,
53968 +                           keyUsage,
53969 +                           ar->arWepKeyList[index].arKeyLen,
53970 +                           NULL,
53971 +                           ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL,
53972 +                           NO_SYNC_WMIFLAG);
53973 +        }
53974 +    }
53975 +}
53976 +
53977 +int
53978 +ar6000_ioctl_delkey(struct net_device *dev, struct iw_request_info *info,
53979 +             void *w, char *extra)
53980 +{
53981 +    return 0;
53982 +}
53983 +
53984 +int
53985 +ar6000_ioctl_setmlme(struct net_device *dev, struct iw_request_info *info,
53986 +             void *w, char *extra)
53987 +{
53988 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
53989 +    struct ieee80211req_mlme *mlme = (struct ieee80211req_mlme *)extra;
53990 +
53991 +    if ((ar->arWmiReady == FALSE) || (ar->arConnected != TRUE))
53992 +               return -EIO;
53993 +
53994 +    switch (mlme->im_op) {
53995 +        case IEEE80211_MLME_DISASSOC:
53996 +        case IEEE80211_MLME_DEAUTH:
53997 +            /* Not Supported */
53998 +            break;
53999 +        default:
54000 +            break;
54001 +    }
54002 +    return 0;
54003 +}
54004 +
54005 +
54006 +int
54007 +ar6000_ioctl_setwmmparams(struct net_device *dev, struct iw_request_info *info,
54008 +             void *w, char *extra)
54009 +{
54010 +    return -EIO;            /* for now */
54011 +}
54012 +
54013 +int
54014 +ar6000_ioctl_getwmmparams(struct net_device *dev, struct iw_request_info *info,
54015 +             void *w, char *extra)
54016 +{
54017 +    return -EIO;            /* for now */
54018 +}
54019 +
54020 +int ar6000_ioctl_setoptie(struct net_device *dev, struct iw_request_info *info,
54021 +                         struct iw_point *data, char *extra)
54022 +{
54023 +       /* The target generates the WPA/RSN IE */
54024 +       return 0;
54025 +}
54026 +
54027 +int
54028 +ar6000_ioctl_setauthalg(struct net_device *dev, struct iw_request_info *info,
54029 +             void *w, char *extra)
54030 +{
54031 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54032 +    struct ieee80211req_authalg *req = (struct ieee80211req_authalg *)extra;
54033 +    int ret = 0;
54034 +
54035 +
54036 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
54037 +
54038 +    if (req->auth_alg == AUTH_ALG_OPEN_SYSTEM) {
54039 +        ar->arDot11AuthMode  = OPEN_AUTH;
54040 +    } else if (req->auth_alg == AUTH_ALG_LEAP) {
54041 +        ar->arDot11AuthMode   = LEAP_AUTH;
54042 +        ar->arPairwiseCrypto  = WEP_CRYPT;
54043 +        ar->arGroupCrypto     = WEP_CRYPT;
54044 +    } else {
54045 +        ret = -EIO;
54046 +    }
54047 +
54048 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
54049 +
54050 +    return ret;
54051 +}
54052 +static int
54053 +ar6000_ioctl_addpmkid(struct net_device *dev, struct iw_request_info *info,
54054 +             void *w, char *extra)
54055 +{
54056 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54057 +    struct ieee80211req_addpmkid  *req = (struct ieee80211req_addpmkid *)extra;
54058 +    A_STATUS status;
54059 +
54060 +    if (ar->arWlanState == WLAN_DISABLED) {
54061 +        return -EIO;
54062 +    }
54063 +
54064 +    AR_DEBUG_PRINTF("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n",
54065 +                    req->pi_bssid[0], req->pi_bssid[1], req->pi_bssid[2],
54066 +                    req->pi_bssid[3], req->pi_bssid[4], req->pi_bssid[5],
54067 +                    req->pi_enable);
54068 +
54069 +    status = wmi_setPmkid_cmd(ar->arWmi, req->pi_bssid, req->pi_pmkid,
54070 +                              req->pi_enable);
54071 +
54072 +    if (status != A_OK) {
54073 +        return -EIO;
54074 +    }
54075 +
54076 +    return 0;
54077 +}
54078 +
54079 +/*
54080 + * SIOCSIWRATE
54081 + */
54082 +int
54083 +ar6000_ioctl_siwrate(struct net_device *dev,
54084 +            struct iw_request_info *info,
54085 +            struct iw_param *rrq, char *extra)
54086 +{
54087 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54088 +    A_UINT32  kbps;
54089 +
54090 +    if (rrq->fixed) {
54091 +        kbps = rrq->value / 1000;           /* rrq->value is in bps */
54092 +    } else {
54093 +        kbps = -1;                          /* -1 indicates auto rate */
54094 +    }
54095 +    if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL)
54096 +    {
54097 +        AR_DEBUG_PRINTF("BitRate is not Valid %d\n", kbps);
54098 +        return -EINVAL;
54099 +    }
54100 +    ar->arBitRate = kbps;
54101 +    if(ar->arWmiReady == TRUE)
54102 +    {
54103 +        if (wmi_set_bitrate_cmd(ar->arWmi, kbps) != A_OK) {
54104 +            return -EINVAL;
54105 +        }
54106 +    }
54107 +    return 0;
54108 +}
54109 +
54110 +/*
54111 + * SIOCGIWRATE
54112 + */
54113 +int
54114 +ar6000_ioctl_giwrate(struct net_device *dev,
54115 +            struct iw_request_info *info,
54116 +            struct iw_param *rrq, char *extra)
54117 +{
54118 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54119 +    int ret = 0;
54120 +
54121 +    if (down_interruptible(&ar->arSem)) {
54122 +        return -ERESTARTSYS;
54123 +    }
54124 +    if(ar->arWmiReady == TRUE)
54125 +    {
54126 +        ar->arBitRate = 0xFFFF;
54127 +        if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) {
54128 +            up(&ar->arSem);
54129 +            return -EIO;
54130 +        }
54131 +        wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ);
54132 +        if (signal_pending(current)) {
54133 +            ret = -EINTR;
54134 +        }
54135 +    }
54136 +    /* If the interface is down or wmi is not ready or the target is not
54137 +       connected - return the value stored in the device structure */
54138 +    if (!ret) {
54139 +        if (ar->arBitRate == -1) {
54140 +            rrq->fixed = TRUE;
54141 +            rrq->value = 0;
54142 +        } else {
54143 +            rrq->value = ar->arBitRate * 1000;
54144 +        }
54145 +    }
54146 +
54147 +    up(&ar->arSem);
54148 +
54149 +    return ret;
54150 +}
54151 +
54152 +/*
54153 + * SIOCSIWTXPOW
54154 + */
54155 +static int
54156 +ar6000_ioctl_siwtxpow(struct net_device *dev,
54157 +             struct iw_request_info *info,
54158 +             struct iw_param *rrq, char *extra)
54159 +{
54160 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54161 +    A_UINT8 dbM;
54162 +
54163 +    if (ar->arWlanState == WLAN_DISABLED) {
54164 +        return -EIO;
54165 +    }
54166 +
54167 +    if (ar->arRadioSwitch == WLAN_ENABLED
54168 +       && rrq->disabled) {
54169 +           if (wmi_switch_radio(ar->arWmi, WLAN_DISABLED) < 0)
54170 +                   return -EIO;
54171 +           ar->arRadioSwitch = WLAN_DISABLED;
54172 +    } else if (ar->arRadioSwitch == WLAN_DISABLED
54173 +              && !rrq->disabled) {
54174 +           if (wmi_switch_radio(ar->arWmi, WLAN_ENABLED) < 0)
54175 +                   return -EIO;
54176 +           ar->arRadioSwitch = WLAN_ENABLED;
54177 +    }
54178 +
54179 +    if (rrq->fixed) {
54180 +        if (rrq->flags != IW_TXPOW_DBM) {
54181 +            return -EOPNOTSUPP;
54182 +        }
54183 +        ar->arTxPwr= dbM = rrq->value;
54184 +        ar->arTxPwrSet = TRUE;
54185 +    } else {
54186 +        ar->arTxPwr = dbM = 0;
54187 +        ar->arTxPwrSet = FALSE;
54188 +    }
54189 +    if(ar->arWmiReady == TRUE)
54190 +    {
54191 +        AR_DEBUG_PRINTF("Set tx pwr cmd %d dbM\n", dbM);
54192 +        wmi_set_txPwr_cmd(ar->arWmi, dbM);
54193 +    }
54194 +    return 0;
54195 +}
54196 +
54197 +/*
54198 + * SIOCGIWTXPOW
54199 + */
54200 +int
54201 +ar6000_ioctl_giwtxpow(struct net_device *dev,
54202 +            struct iw_request_info *info,
54203 +            struct iw_param *rrq, char *extra)
54204 +{
54205 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54206 +    int ret = 0;
54207 +
54208 +    if (ar->arWlanState == WLAN_DISABLED) {
54209 +        return -EIO;
54210 +    }
54211 +
54212 +    if (ar->arRadioSwitch == WLAN_DISABLED) {
54213 +           rrq->disabled = 1;
54214 +           return 0;
54215 +    }
54216 +
54217 +    if (down_interruptible(&ar->arSem)) {
54218 +        return -ERESTARTSYS;
54219 +    }
54220 +    if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE))
54221 +    {
54222 +        ar->arTxPwr = 0;
54223 +
54224 +        if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
54225 +            up(&ar->arSem);
54226 +            return -EIO;
54227 +        }
54228 +
54229 +        wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ);
54230 +
54231 +        if (signal_pending(current)) {
54232 +            ret = -EINTR;
54233 +         }
54234 +    }
54235 +   /* If the interace is down or wmi is not ready or target is not connected
54236 +      then return value stored in the device structure */
54237 +
54238 +    if (!ret) {
54239 +         if (ar->arTxPwrSet == TRUE) {
54240 +            rrq->fixed = TRUE;
54241 +        }
54242 +        rrq->value = ar->arTxPwr;
54243 +        rrq->flags = IW_TXPOW_DBM;
54244 +    }
54245 +
54246 +    up(&ar->arSem);
54247 +
54248 +    return ret;
54249 +}
54250 +
54251 +/*
54252 + * SIOCSIWRETRY
54253 + * since iwconfig only provides us with one max retry value, we use it
54254 + * to apply to data frames of the BE traffic class.
54255 + */
54256 +static int
54257 +ar6000_ioctl_siwretry(struct net_device *dev,
54258 +             struct iw_request_info *info,
54259 +             struct iw_param *rrq, char *extra)
54260 +{
54261 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54262 +
54263 +    if (ar->arWlanState == WLAN_DISABLED) {
54264 +        return -EIO;
54265 +    }
54266 +
54267 +    if (rrq->disabled) {
54268 +        return -EOPNOTSUPP;
54269 +    }
54270 +
54271 +    if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) {
54272 +        return -EOPNOTSUPP;
54273 +    }
54274 +
54275 +    if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) {
54276 +            return - EINVAL;
54277 +    }
54278 +    if(ar->arWmiReady == TRUE)
54279 +    {
54280 +        if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE,
54281 +                                     rrq->value, 0) != A_OK){
54282 +            return -EINVAL;
54283 +        }
54284 +    }
54285 +    ar->arMaxRetries = rrq->value;
54286 +    return 0;
54287 +}
54288 +
54289 +/*
54290 + * SIOCGIWRETRY
54291 + */
54292 +static int
54293 +ar6000_ioctl_giwretry(struct net_device *dev,
54294 +             struct iw_request_info *info,
54295 +             struct iw_param *rrq, char *extra)
54296 +{
54297 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54298 +
54299 +    if (ar->arWlanState == WLAN_DISABLED) {
54300 +        return -EIO;
54301 +    }
54302 +
54303 +    rrq->disabled = 0;
54304 +    switch (rrq->flags & IW_RETRY_TYPE) {
54305 +    case IW_RETRY_LIFETIME:
54306 +        return -EOPNOTSUPP;
54307 +        break;
54308 +    case IW_RETRY_LIMIT:
54309 +        rrq->flags = IW_RETRY_LIMIT;
54310 +        switch (rrq->flags & IW_RETRY_MODIFIER) {
54311 +        case IW_RETRY_MIN:
54312 +            rrq->flags |= IW_RETRY_MIN;
54313 +            rrq->value = WMI_MIN_RETRIES;
54314 +            break;
54315 +        case IW_RETRY_MAX:
54316 +            rrq->flags |= IW_RETRY_MAX;
54317 +            rrq->value = ar->arMaxRetries;
54318 +            break;
54319 +        }
54320 +        break;
54321 +    }
54322 +    return 0;
54323 +}
54324 +
54325 +/*
54326 + * SIOCSIWENCODE
54327 + */
54328 +static int
54329 +ar6000_ioctl_siwencode(struct net_device *dev,
54330 +              struct iw_request_info *info,
54331 +              struct iw_point *erq, char *keybuf)
54332 +{
54333 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54334 +    int index;
54335 +    A_INT32 auth = ar->arDot11AuthMode;
54336 +
54337 +    if (ar->arWlanState == WLAN_DISABLED) {
54338 +        return -EIO;
54339 +    }
54340 +
54341 +    index = erq->flags & IW_ENCODE_INDEX;
54342 +
54343 +    if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
54344 +                  ((index - 1) > WMI_MAX_KEY_INDEX)))
54345 +    {
54346 +        return -EIO;
54347 +    }
54348 +
54349 +    if (erq->flags & IW_ENCODE_DISABLED) {
54350 +        /*
54351 +         * Encryption disabled
54352 +         */
54353 +        if (index) {
54354 +            /*
54355 +             * If key index was specified then clear the specified key
54356 +             */
54357 +            index--;
54358 +            A_MEMZERO(ar->arWepKeyList[index].arKey,
54359 +                      sizeof(ar->arWepKeyList[index].arKey));
54360 +            ar->arWepKeyList[index].arKeyLen = 0;
54361 +        }
54362 +        ar->arDot11AuthMode       = OPEN_AUTH;
54363 +        ar->arPairwiseCrypto      = NONE_CRYPT;
54364 +        ar->arGroupCrypto         = NONE_CRYPT;
54365 +        ar->arAuthMode            = NONE_AUTH;
54366 +    } else {
54367 +        /*
54368 +         * Enabling WEP encryption
54369 +         */
54370 +        if (index) {
54371 +            index--;                /* keyindex is off base 1 in iwconfig */
54372 +        }
54373 +
54374 +        if (erq->flags & IW_ENCODE_OPEN) {
54375 +            auth = OPEN_AUTH;
54376 +        } else if (erq->flags & IW_ENCODE_RESTRICTED) {
54377 +            auth = SHARED_AUTH;
54378 +        }
54379 +
54380 +        if (erq->length) {
54381 +            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) {
54382 +                return -EIO;
54383 +            }
54384 +
54385 +            A_MEMZERO(ar->arWepKeyList[index].arKey,
54386 +                      sizeof(ar->arWepKeyList[index].arKey));
54387 +            A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length);
54388 +            ar->arWepKeyList[index].arKeyLen = erq->length;
54389 +        } else {
54390 +            if (ar->arWepKeyList[index].arKeyLen == 0) {
54391 +                return -EIO;
54392 +            }
54393 +            ar->arDefTxKeyIndex = index;
54394 +        }
54395 +
54396 +        ar->arPairwiseCrypto      = WEP_CRYPT;
54397 +        ar->arGroupCrypto         = WEP_CRYPT;
54398 +        ar->arDot11AuthMode       = auth;
54399 +        ar->arAuthMode            = NONE_AUTH;
54400 +    }
54401 +
54402 +    /*
54403 +     * profile has changed.  Erase ssid to signal change
54404 +     */
54405 +    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
54406 +    ar->arSsidLen = 0;
54407 +
54408 +    return 0;
54409 +}
54410 +
54411 +static int
54412 +ar6000_ioctl_giwencode(struct net_device *dev,
54413 +              struct iw_request_info *info,
54414 +              struct iw_point *erq, char *key)
54415 +{
54416 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
54417 +    A_UINT8 keyIndex;
54418 +    struct ar_wep_key *wk;
54419 +
54420 +    if (ar->arWlanState == WLAN_DISABLED) {
54421 +        return -EIO;
54422 +    }
54423 +
54424 +    if (ar->arPairwiseCrypto == NONE_CRYPT) {
54425 +        erq->length = 0;
54426 +        erq->flags = IW_ENCODE_DISABLED;
54427 +    } else {
54428 +        /* get the keyIndex */
54429 +        keyIndex = erq->flags & IW_ENCODE_INDEX;
54430 +        if (0 == keyIndex) {
54431 +            keyIndex = ar->arDefTxKeyIndex;
54432 +        } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) ||
54433 +                   (keyIndex - 1 > WMI_MAX_KEY_INDEX))
54434 +        {
54435 +            keyIndex = WMI_MIN_KEY_INDEX;
54436 +        } else {
54437 +            keyIndex--;
54438 +        }
54439 +        erq->flags = keyIndex + 1;
54440 +        erq->flags |= IW_ENCODE_ENABLED;
54441 +        wk = &ar->arWepKeyList[keyIndex];
54442 +        if (erq->length > wk->arKeyLen) {
54443 +            erq->length = wk->arKeyLen;
54444 +        }
54445 +        if (wk->arKeyLen) {
54446 +            A_MEMCPY(key, wk->arKey, erq->length);
54447 +        }
54448 +        if (ar->arDot11AuthMode == OPEN_AUTH) {
54449 +            erq->flags |= IW_ENCODE_OPEN;
54450 +        } else if (ar->arDot11AuthMode == SHARED_AUTH) {
54451 +            erq->flags |= IW_ENCODE_RESTRICTED;
54452 +        }
54453 +    }
54454 +
54455 +    return 0;
54456 +}
54457 +
54458 +static int ar6000_ioctl_siwpower(struct net_device *dev,
54459 +                                struct iw_request_info *info,
54460 +                                union iwreq_data *wrqu, char *extra)
54461 +{
54462 +       AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
54463 +       WMI_POWER_MODE power_mode;
54464 +
54465 +       if (wrqu->power.disabled)
54466 +               power_mode = MAX_PERF_POWER;
54467 +       else
54468 +               power_mode = REC_POWER;
54469 +
54470 +       if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0)
54471 +               return -EIO;
54472 +
54473 +       return 0;
54474 +}
54475 +
54476 +static int ar6000_ioctl_giwpower(struct net_device *dev,
54477 +                                struct iw_request_info *info,
54478 +                                union iwreq_data *wrqu, char *extra)
54479 +{
54480 +       AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
54481 +
54482 +       return wmi_get_power_mode_cmd(ar->arWmi);
54483 +}
54484 +
54485 +static int ar6000_ioctl_siwgenie(struct net_device *dev,
54486 +                                struct iw_request_info *info,
54487 +                                struct iw_point *dwrq,
54488 +                                char *extra)
54489 +{
54490 +       /* The target does that for us */
54491 +       return 0;
54492 +}
54493 +
54494 +static int ar6000_ioctl_giwgenie(struct net_device *dev,
54495 +                                struct iw_request_info *info,
54496 +                                struct iw_point *dwrq,
54497 +                                char *extra)
54498 +{
54499 +       return 0;
54500 +}
54501 +
54502 +static int ar6000_ioctl_siwauth(struct net_device *dev,
54503 +                               struct iw_request_info *info,
54504 +                               struct iw_param *param,
54505 +                               char *extra)
54506 +{
54507 +       AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
54508 +       int reset = 0;
54509 +
54510 +       switch (param->flags & IW_AUTH_INDEX) {
54511 +       case IW_AUTH_WPA_VERSION:
54512 +               if (param->value & IW_AUTH_WPA_VERSION_DISABLED) {
54513 +                       ar->arAuthMode = NONE_AUTH;
54514 +               }
54515 +               if (param->value & IW_AUTH_WPA_VERSION_WPA) {
54516 +                       ar->arAuthMode = WPA_AUTH;
54517 +               }
54518 +               if (param->value & IW_AUTH_WPA_VERSION_WPA2) {
54519 +                       ar->arAuthMode = WPA2_AUTH;
54520 +               }
54521 +
54522 +               reset = 1;
54523 +               break;
54524 +       case IW_AUTH_CIPHER_PAIRWISE:
54525 +               if (param->value & IW_AUTH_CIPHER_NONE) {
54526 +                       ar->arPairwiseCrypto = NONE_CRYPT;
54527 +               }
54528 +               if (param->value & IW_AUTH_CIPHER_WEP40) {
54529 +                       ar->arPairwiseCrypto = WEP_CRYPT;
54530 +               }
54531 +               if (param->value & IW_AUTH_CIPHER_TKIP) {
54532 +                       ar->arPairwiseCrypto = TKIP_CRYPT;
54533 +               }
54534 +               if (param->value & IW_AUTH_CIPHER_CCMP) {
54535 +                       ar->arPairwiseCrypto = AES_CRYPT;
54536 +               }
54537 +
54538 +               reset = 1;
54539 +               break;
54540 +       case IW_AUTH_CIPHER_GROUP:
54541 +               if (param->value & IW_AUTH_CIPHER_NONE) {
54542 +                       ar->arGroupCrypto = NONE_CRYPT;
54543 +               }
54544 +               if (param->value & IW_AUTH_CIPHER_WEP40) {
54545 +                       ar->arGroupCrypto = WEP_CRYPT;
54546 +               }
54547 +               if (param->value & IW_AUTH_CIPHER_TKIP) {
54548 +                       ar->arGroupCrypto = TKIP_CRYPT;
54549 +               }
54550 +               if (param->value & IW_AUTH_CIPHER_CCMP) {
54551 +                       ar->arGroupCrypto = AES_CRYPT;
54552 +               }
54553 +
54554 +               reset = 1;
54555 +               break;
54556 +       case IW_AUTH_KEY_MGMT:
54557 +               if (param->value & IW_AUTH_KEY_MGMT_PSK) {
54558 +                       if (ar->arAuthMode == WPA_AUTH) {
54559 +                               ar->arAuthMode = WPA_PSK_AUTH;
54560 +                       } else if (ar->arAuthMode == WPA2_AUTH) {
54561 +                               ar->arAuthMode = WPA2_PSK_AUTH;
54562 +                       }
54563 +
54564 +                       reset = 1;
54565 +               }
54566 +               break;
54567 +
54568 +       case IW_AUTH_TKIP_COUNTERMEASURES:
54569 +               if (ar->arWmiReady == FALSE) {
54570 +                       return -EIO;
54571 +               }
54572 +               wmi_set_tkip_countermeasures_cmd(ar->arWmi, param->value);
54573 +               break;
54574 +
54575 +       case IW_AUTH_DROP_UNENCRYPTED:
54576 +               break;
54577 +
54578 +       case IW_AUTH_80211_AUTH_ALG:
54579 +               if (param->value & IW_AUTH_ALG_OPEN_SYSTEM) {
54580 +                       ar->arDot11AuthMode  = OPEN_AUTH;
54581 +               }
54582 +               if (param->value & IW_AUTH_ALG_SHARED_KEY) {
54583 +                       ar->arDot11AuthMode  = SHARED_AUTH;
54584 +               }
54585 +               if (param->value & IW_AUTH_ALG_LEAP) {
54586 +                       ar->arDot11AuthMode   = LEAP_AUTH;
54587 +                       ar->arPairwiseCrypto  = WEP_CRYPT;
54588 +                       ar->arGroupCrypto     = WEP_CRYPT;
54589 +               }
54590 +
54591 +               reset = 1;
54592 +               break;
54593 +
54594 +       case IW_AUTH_WPA_ENABLED:
54595 +               reset = 1;
54596 +               break;
54597 +
54598 +       case IW_AUTH_RX_UNENCRYPTED_EAPOL:
54599 +               break;
54600 +
54601 +       case IW_AUTH_PRIVACY_INVOKED:
54602 +               break;
54603 +
54604 +       default:
54605 +               printk("%s(): Unknown flag 0x%x\n", __FUNCTION__, param->flags);
54606 +               return -EOPNOTSUPP;
54607 +       }
54608 +
54609 +       if (reset) {
54610 +               A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
54611 +               ar->arSsidLen = 0;
54612 +       }
54613 +
54614 +       return 0;
54615 +}
54616 +
54617 +static int ar6000_ioctl_giwauth(struct net_device *dev,
54618 +                               struct iw_request_info *info,
54619 +                               struct iw_param *dwrq,
54620 +                               char *extra)
54621 +{
54622 +       return 0;
54623 +}
54624 +
54625 +static int ar6000_ioctl_siwencodeext(struct net_device *dev,
54626 +                                    struct iw_request_info *info,
54627 +                                    union iwreq_data *wrqu,
54628 +                                    char *extra)
54629 +{
54630 +       AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
54631 +       struct iw_point *encoding = &wrqu->encoding;
54632 +       struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
54633 +       int alg = ext->alg, idx;
54634 +
54635 +       if (ar->arWlanState == WLAN_DISABLED) {
54636 +               return -EIO;
54637 +       }
54638 +
54639 +       /* Determine and validate the key index */
54640 +       idx = (encoding->flags & IW_ENCODE_INDEX) - 1;
54641 +       if (idx) {
54642 +               if (idx < 0 || idx > 3)
54643 +                       return -EINVAL;
54644 +       }
54645 +
54646 +       if ((alg == IW_ENCODE_ALG_TKIP) || (alg == IW_ENCODE_ALG_CCMP)) {
54647 +               struct ieee80211req_key ik;
54648 +               KEY_USAGE key_usage;
54649 +               CRYPTO_TYPE key_type = NONE_CRYPT;
54650 +               int status;
54651 +
54652 +               ar->user_saved_keys.keyOk = FALSE;
54653 +
54654 +               if (alg == IW_ENCODE_ALG_TKIP) {
54655 +                       key_type = TKIP_CRYPT;
54656 +                       ik.ik_type = IEEE80211_CIPHER_TKIP;
54657 +               } else {
54658 +                       key_type = AES_CRYPT;
54659 +                       ik.ik_type = IEEE80211_CIPHER_AES_CCM;
54660 +               }
54661 +
54662 +               ik.ik_keyix = idx;
54663 +               ik.ik_keylen = ext->key_len;
54664 +               ik.ik_flags = IEEE80211_KEY_RECV;
54665 +               if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
54666 +                       ik.ik_flags |= IEEE80211_KEY_XMIT
54667 +                               | IEEE80211_KEY_DEFAULT;
54668 +               }
54669 +
54670 +               if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
54671 +                       memcpy(&ik.ik_keyrsc, ext->rx_seq, 8);
54672 +               }
54673 +
54674 +               memcpy(ik.ik_keydata, ext->key, ext->key_len);
54675 +
54676 +               ar->user_saved_keys.keyType = key_type;
54677 +               if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
54678 +                       key_usage = GROUP_USAGE;
54679 +                       memset(ik.ik_macaddr, 0, ETH_ALEN);
54680 +                       memcpy(&ar->user_saved_keys.bcast_ik, &ik,
54681 +                              sizeof(struct ieee80211req_key));
54682 +               } else {
54683 +                       key_usage = PAIRWISE_USAGE;
54684 +                       memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN);
54685 +                       memcpy(&ar->user_saved_keys.ucast_ik, &ik,
54686 +                              sizeof(struct ieee80211req_key));
54687 +               }
54688 +
54689 +               status = wmi_addKey_cmd(ar->arWmi, ik.ik_keyix, key_type,
54690 +                                       key_usage, ik.ik_keylen,
54691 +                                       (A_UINT8 *)&ik.ik_keyrsc,
54692 +                                       ik.ik_keydata,
54693 +                                       KEY_OP_INIT_VAL, SYNC_BEFORE_WMIFLAG);
54694 +
54695 +               if (status < 0)
54696 +                       return -EIO;
54697 +
54698 +               ar->user_saved_keys.keyOk = TRUE;
54699 +
54700 +               return 0;
54701 +
54702 +       } else {
54703 +               /* WEP falls back to SIWENCODE */
54704 +               return -EOPNOTSUPP;
54705 +       }
54706 +
54707 +       return 0;
54708 +}
54709 +
54710 +
54711 +static int ar6000_ioctl_giwencodeext(struct net_device *dev,
54712 +                                    struct iw_request_info *info,
54713 +                                    struct iw_point *dwrq,
54714 +                                    char *extra)
54715 +{
54716 +       return 0;
54717 +}
54718 +
54719 +
54720 +static int
54721 +ar6000_ioctl_setparam(struct net_device *dev,
54722 +                      struct iw_request_info *info,
54723 +                      void *erq, char *extra)
54724 +{
54725 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54726 +    int *i = (int *)extra;
54727 +    int param = i[0];
54728 +    int value = i[1];
54729 +    int ret = 0;
54730 +    A_BOOL profChanged = FALSE;
54731 +
54732 +    if (ar->arWlanState == WLAN_DISABLED) {
54733 +        return -EIO;
54734 +    }
54735 +
54736 +    switch (param) {
54737 +        case IEEE80211_PARAM_WPA:
54738 +            switch (value) {
54739 +                case WPA_MODE_WPA1:
54740 +                    ar->arAuthMode = WPA_AUTH;
54741 +                    profChanged    = TRUE;
54742 +                    break;
54743 +                case WPA_MODE_WPA2:
54744 +                    ar->arAuthMode = WPA2_AUTH;
54745 +                    profChanged    = TRUE;
54746 +                    break;
54747 +                case WPA_MODE_NONE:
54748 +                    ar->arAuthMode = NONE_AUTH;
54749 +                    profChanged    = TRUE;
54750 +                    break;
54751 +           default:
54752 +                   printk("IEEE80211_PARAM_WPA: Unknown value %d\n", value);
54753 +            }
54754 +            break;
54755 +        case IEEE80211_PARAM_AUTHMODE:
54756 +            switch(value) {
54757 +                case IEEE80211_AUTH_WPA_PSK:
54758 +                    if (WPA_AUTH == ar->arAuthMode) {
54759 +                        ar->arAuthMode = WPA_PSK_AUTH;
54760 +                        profChanged    = TRUE;
54761 +                    } else if (WPA2_AUTH == ar->arAuthMode) {
54762 +                        ar->arAuthMode = WPA2_PSK_AUTH;
54763 +                        profChanged    = TRUE;
54764 +                    } else {
54765 +                        AR_DEBUG_PRINTF("Error -  Setting PSK mode when WPA "\
54766 +                                        "param was set to %d\n",
54767 +                                        ar->arAuthMode);
54768 +                        ret = -1;
54769 +                    }
54770 +                    break;
54771 +                case IEEE80211_AUTH_WPA_CCKM:
54772 +                    if (WPA2_AUTH == ar->arAuthMode) {
54773 +                        ar->arAuthMode = WPA2_AUTH_CCKM;
54774 +                    } else {
54775 +                        ar->arAuthMode = WPA_AUTH_CCKM;
54776 +                    }
54777 +                    break;
54778 +                default:
54779 +                    break;
54780 +            }
54781 +            break;
54782 +        case IEEE80211_PARAM_UCASTCIPHER:
54783 +            switch (value) {
54784 +                case IEEE80211_CIPHER_AES_CCM:
54785 +                    ar->arPairwiseCrypto = AES_CRYPT;
54786 +                    profChanged          = TRUE;
54787 +                    break;
54788 +                case IEEE80211_CIPHER_TKIP:
54789 +                    ar->arPairwiseCrypto = TKIP_CRYPT;
54790 +                    profChanged          = TRUE;
54791 +                    break;
54792 +                case IEEE80211_CIPHER_WEP:
54793 +                    ar->arPairwiseCrypto = WEP_CRYPT;
54794 +                    profChanged          = TRUE;
54795 +                    break;
54796 +                case IEEE80211_CIPHER_NONE:
54797 +                    ar->arPairwiseCrypto = NONE_CRYPT;
54798 +                    profChanged          = TRUE;
54799 +                    break;
54800 +            }
54801 +            break;
54802 +        case IEEE80211_PARAM_UCASTKEYLEN:
54803 +            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
54804 +                ret = -EIO;
54805 +            } else {
54806 +                ar->arPairwiseCryptoLen = value;
54807 +            }
54808 +            break;
54809 +        case IEEE80211_PARAM_MCASTCIPHER:
54810 +            switch (value) {
54811 +                case IEEE80211_CIPHER_AES_CCM:
54812 +                    ar->arGroupCrypto = AES_CRYPT;
54813 +                    profChanged       = TRUE;
54814 +                    break;
54815 +                case IEEE80211_CIPHER_TKIP:
54816 +                    ar->arGroupCrypto = TKIP_CRYPT;
54817 +                    profChanged       = TRUE;
54818 +                    break;
54819 +                case IEEE80211_CIPHER_WEP:
54820 +                    ar->arGroupCrypto = WEP_CRYPT;
54821 +                    profChanged       = TRUE;
54822 +                    break;
54823 +                case IEEE80211_CIPHER_NONE:
54824 +                    ar->arGroupCrypto = NONE_CRYPT;
54825 +                    profChanged       = TRUE;
54826 +                    break;
54827 +            }
54828 +            break;
54829 +        case IEEE80211_PARAM_MCASTKEYLEN:
54830 +            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
54831 +                ret = -EIO;
54832 +            } else {
54833 +                ar->arGroupCryptoLen = value;
54834 +            }
54835 +            break;
54836 +        case IEEE80211_PARAM_COUNTERMEASURES:
54837 +            if (ar->arWmiReady == FALSE) {
54838 +                return -EIO;
54839 +            }
54840 +            wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
54841 +            break;
54842 +        default:
54843 +            break;
54844 +    }
54845 +
54846 +    if (profChanged == TRUE) {
54847 +        /*
54848 +         * profile has changed.  Erase ssid to signal change
54849 +         */
54850 +       A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
54851 +       ar->arSsidLen = 0;
54852 +    }
54853 +
54854 +    return ret;
54855 +}
54856 +
54857 +int
54858 +ar6000_ioctl_getparam(struct net_device *dev, struct iw_request_info *info,
54859 +            void *w, char *extra)
54860 +{
54861 +    return -EIO;            /* for now */
54862 +}
54863 +
54864 +int
54865 +ar6000_ioctl_setkey(struct net_device *dev, struct iw_request_info *info,
54866 +                   void *w, char *extra)
54867 +{
54868 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54869 +    struct ieee80211req_key *ik = (struct ieee80211req_key *)extra;
54870 +    KEY_USAGE keyUsage;
54871 +    A_STATUS status;
54872 +    CRYPTO_TYPE keyType = NONE_CRYPT;
54873 +
54874 +    if (ar->arWlanState == WLAN_DISABLED) {
54875 +        return -EIO;
54876 +    }
54877 +
54878 +    ar->user_saved_keys.keyOk = FALSE;
54879 +
54880 +    if ( 0 == memcmp(ik->ik_macaddr, "\x00\x00\x00\x00\x00\x00",
54881 +                     IEEE80211_ADDR_LEN)) {
54882 +        keyUsage = GROUP_USAGE;
54883 +        A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik,
54884 +                 sizeof(struct ieee80211req_key));
54885 +    } else {
54886 +        keyUsage = PAIRWISE_USAGE;
54887 +        A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik,
54888 +                 sizeof(struct ieee80211req_key));
54889 +    }
54890 +
54891 +    switch (ik->ik_type) {
54892 +        case IEEE80211_CIPHER_WEP:
54893 +            keyType = WEP_CRYPT;
54894 +            break;
54895 +        case IEEE80211_CIPHER_TKIP:
54896 +            keyType = TKIP_CRYPT;
54897 +            break;
54898 +        case IEEE80211_CIPHER_AES_CCM:
54899 +            keyType = AES_CRYPT;
54900 +            break;
54901 +        default:
54902 +            break;
54903 +    }
54904 +    ar->user_saved_keys.keyType = keyType;
54905 +
54906 +    if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) {
54907 +        if (NONE_CRYPT == keyType) {
54908 +            return -EIO;
54909 +        }
54910 +
54911 +        status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage,
54912 +                                ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
54913 +                                ik->ik_keydata, KEY_OP_INIT_VAL,
54914 +                                SYNC_BEFORE_WMIFLAG);
54915 +
54916 +        if (status != A_OK) {
54917 +            return -EIO;
54918 +        }
54919 +    } else {
54920 +        status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata);
54921 +    }
54922 +
54923 +    ar->user_saved_keys.keyOk = TRUE;
54924 +
54925 +    return 0;
54926 +}
54927 +
54928 +
54929 +/*
54930 + * SIOCGIWNAME
54931 + */
54932 +int
54933 +ar6000_ioctl_giwname(struct net_device *dev,
54934 +           struct iw_request_info *info,
54935 +           char *name, char *extra)
54936 +{
54937 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54938 +
54939 +    if (ar->arWlanState == WLAN_DISABLED) {
54940 +        return -EIO;
54941 +    }
54942 +
54943 +    switch (ar->arPhyCapability) {
54944 +    case (WMI_11A_CAPABILITY):
54945 +        strncpy(name, "AR6000 802.11a", IFNAMSIZ);
54946 +        break;
54947 +    case (WMI_11G_CAPABILITY):
54948 +        strncpy(name, "AR6000 802.11g", IFNAMSIZ);
54949 +        break;
54950 +    case (WMI_11AG_CAPABILITY):
54951 +        strncpy(name, "AR6000 802.11ag", IFNAMSIZ);
54952 +        break;
54953 +    default:
54954 +        strncpy(name, "AR6000 802.11", IFNAMSIZ);
54955 +        break;
54956 +    }
54957 +
54958 +    return 0;
54959 +}
54960 +
54961 +/*
54962 + * SIOCSIWFREQ
54963 + */
54964 +int
54965 +ar6000_ioctl_siwfreq(struct net_device *dev,
54966 +            struct iw_request_info *info,
54967 +            struct iw_freq *freq, char *extra)
54968 +{
54969 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54970 +
54971 +    if (ar->arWlanState == WLAN_DISABLED) {
54972 +        return -EIO;
54973 +    }
54974 +
54975 +    /*
54976 +     * We support limiting the channels via wmiconfig.
54977 +     *
54978 +     * We use this command to configure the channel hint for the connect cmd
54979 +     * so it is possible the target will end up connecting to a different
54980 +     * channel.
54981 +     */
54982 +    if (freq->e > 1) {
54983 +        return -EINVAL;
54984 +    } else if (freq->e == 1) {
54985 +        ar->arChannelHint = freq->m / 100000;
54986 +    } else {
54987 +        ar->arChannelHint = wlan_ieee2freq(freq->m);
54988 +    }
54989 +
54990 +    A_PRINTF("channel hint set to %d\n", ar->arChannelHint);
54991 +    return 0;
54992 +}
54993 +
54994 +/*
54995 + * SIOCGIWFREQ
54996 + */
54997 +int
54998 +ar6000_ioctl_giwfreq(struct net_device *dev,
54999 +                struct iw_request_info *info,
55000 +                struct iw_freq *freq, char *extra)
55001 +{
55002 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55003 +
55004 +    if (ar->arWlanState == WLAN_DISABLED) {
55005 +        return -EIO;
55006 +    }
55007 +
55008 +    if (ar->arConnected != TRUE) {
55009 +        return -EINVAL;
55010 +    }
55011 +
55012 +    freq->m = ar->arBssChannel * 100000;
55013 +    freq->e = 1;
55014 +
55015 +    return 0;
55016 +}
55017 +
55018 +/*
55019 + * SIOCSIWMODE
55020 + */
55021 +int
55022 +ar6000_ioctl_siwmode(struct net_device *dev,
55023 +            struct iw_request_info *info,
55024 +            __u32 *mode, char *extra)
55025 +{
55026 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55027 +
55028 +    if (ar->arWlanState == WLAN_DISABLED) {
55029 +        return -EIO;
55030 +    }
55031 +
55032 +    switch (*mode) {
55033 +    case IW_MODE_INFRA:
55034 +        ar->arNetworkType = INFRA_NETWORK;
55035 +        break;
55036 +    case IW_MODE_ADHOC:
55037 +        ar->arNetworkType = ADHOC_NETWORK;
55038 +        break;
55039 +    default:
55040 +        return -EINVAL;
55041 +    }
55042 +
55043 +    return 0;
55044 +}
55045 +
55046 +/*
55047 + * SIOCGIWMODE
55048 + */
55049 +int
55050 +ar6000_ioctl_giwmode(struct net_device *dev,
55051 +            struct iw_request_info *info,
55052 +            __u32 *mode, char *extra)
55053 +{
55054 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55055 +
55056 +    if (ar->arWlanState == WLAN_DISABLED) {
55057 +        return -EIO;
55058 +    }
55059 +
55060 +    switch (ar->arNetworkType) {
55061 +    case INFRA_NETWORK:
55062 +        *mode = IW_MODE_INFRA;
55063 +        break;
55064 +    case ADHOC_NETWORK:
55065 +        *mode = IW_MODE_ADHOC;
55066 +        break;
55067 +    default:
55068 +        return -EIO;
55069 +    }
55070 +    return 0;
55071 +}
55072 +
55073 +/*
55074 + * SIOCSIWSENS
55075 + */
55076 +int
55077 +ar6000_ioctl_siwsens(struct net_device *dev,
55078 +            struct iw_request_info *info,
55079 +            struct iw_param *sens, char *extra)
55080 +{
55081 +    return 0;
55082 +}
55083 +
55084 +/*
55085 + * SIOCGIWSENS
55086 + */
55087 +int
55088 +ar6000_ioctl_giwsens(struct net_device *dev,
55089 +            struct iw_request_info *info,
55090 +            struct iw_param *sens, char *extra)
55091 +{
55092 +    sens->value = 0;
55093 +    sens->fixed = 1;
55094 +
55095 +    return 0;
55096 +}
55097 +
55098 +/*
55099 + * SIOCGIWRANGE
55100 + */
55101 +int
55102 +ar6000_ioctl_giwrange(struct net_device *dev,
55103 +             struct iw_request_info *info,
55104 +             struct iw_point *data, char *extra)
55105 +{
55106 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55107 +    struct iw_range *range = (struct iw_range *) extra;
55108 +    int i, ret = 0;
55109 +
55110 +    if (ar->arWmiReady == FALSE) {
55111 +        return -EIO;
55112 +    }
55113 +
55114 +    if (ar->arWlanState == WLAN_DISABLED) {
55115 +        return -EIO;
55116 +    }
55117 +
55118 +    if (down_interruptible(&ar->arSem)) {
55119 +        return -ERESTARTSYS;
55120 +    }
55121 +    ar->arNumChannels = -1;
55122 +    A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList));
55123 +
55124 +    if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) {
55125 +        up(&ar->arSem);
55126 +        return -EIO;
55127 +    }
55128 +
55129 +    wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ);
55130 +
55131 +    if (signal_pending(current)) {
55132 +        up(&ar->arSem);
55133 +        return -EINTR;
55134 +    }
55135 +
55136 +    data->length = sizeof(struct iw_range);
55137 +    A_MEMZERO(range, sizeof(struct iw_range));
55138 +
55139 +    range->txpower_capa = IW_TXPOW_DBM;
55140 +
55141 +    range->min_pmp = 1 * 1024;
55142 +    range->max_pmp = 65535 * 1024;
55143 +    range->min_pmt = 1 * 1024;
55144 +    range->max_pmt = 1000 * 1024;
55145 +    range->pmp_flags = IW_POWER_PERIOD;
55146 +    range->pmt_flags = IW_POWER_TIMEOUT;
55147 +    range->pm_capa = 0;
55148 +
55149 +    range->we_version_compiled = WIRELESS_EXT;
55150 +    range->we_version_source = 13;
55151 +
55152 +    range->retry_capa = IW_RETRY_LIMIT;
55153 +    range->retry_flags = IW_RETRY_LIMIT;
55154 +    range->min_retry = 0;
55155 +    range->max_retry = 255;
55156 +
55157 +    range->num_frequency = range->num_channels = ar->arNumChannels;
55158 +    for (i = 0; i < ar->arNumChannels; i++) {
55159 +        range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]);
55160 +        range->freq[i].m = ar->arChannelList[i] * 100000;
55161 +        range->freq[i].e = 1;
55162 +         /*
55163 +         * Linux supports max of 32 channels, bail out once you
55164 +         * reach the max.
55165 +         */
55166 +        if (i == IW_MAX_FREQUENCIES) {
55167 +            break;
55168 +        }
55169 +    }
55170 +
55171 +    /* Max quality is max field value minus noise floor */
55172 +    range->max_qual.qual  = 0xff - 161;
55173 +
55174 +    /*
55175 +     * In order to use dBm measurements, 'level' must be lower
55176 +     * than any possible measurement (see iw_print_stats() in
55177 +     * wireless tools).  It's unclear how this is meant to be
55178 +     * done, but setting zero in these values forces dBm and
55179 +     * the actual numbers are not used.
55180 +     */
55181 +    range->max_qual.level = 0;
55182 +    range->max_qual.noise = 0;
55183 +
55184 +    range->sensitivity = 3;
55185 +
55186 +    range->max_encoding_tokens = 4;
55187 +    /* XXX query driver to find out supported key sizes */
55188 +    range->num_encoding_sizes = 3;
55189 +    range->encoding_size[0] = 5;        /* 40-bit */
55190 +    range->encoding_size[1] = 13;       /* 104-bit */
55191 +    range->encoding_size[2] = 16;       /* 128-bit */
55192 +
55193 +    range->num_bitrates = 0;
55194 +
55195 +    /* estimated maximum TCP throughput values (bps) */
55196 +    range->throughput = 22000000;
55197 +
55198 +    range->min_rts = 0;
55199 +    range->max_rts = 2347;
55200 +    range->min_frag = 256;
55201 +    range->max_frag = 2346;
55202 +
55203 +    up(&ar->arSem);
55204 +
55205 +    return ret;
55206 +}
55207 +
55208 +
55209 +/*
55210 + * SIOCSIWAP
55211 + * This ioctl is used to set the desired bssid for the connect command.
55212 + */
55213 +int
55214 +ar6000_ioctl_siwap(struct net_device *dev,
55215 +              struct iw_request_info *info,
55216 +              struct sockaddr *ap_addr, char *extra)
55217 +{
55218 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55219 +
55220 +    if (ar->arWlanState == WLAN_DISABLED) {
55221 +        return -EIO;
55222 +    }
55223 +
55224 +    if (ap_addr->sa_family != ARPHRD_ETHER) {
55225 +        return -EIO;
55226 +    }
55227 +
55228 +    if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) {
55229 +        A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
55230 +    } else {
55231 +        A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data,  sizeof(ar->arReqBssid));
55232 +    }
55233 +
55234 +    return 0;
55235 +}
55236 +
55237 +/*
55238 + * SIOCGIWAP
55239 + */
55240 +int
55241 +ar6000_ioctl_giwap(struct net_device *dev,
55242 +              struct iw_request_info *info,
55243 +              struct sockaddr *ap_addr, char *extra)
55244 +{
55245 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55246 +
55247 +    if (ar->arWlanState == WLAN_DISABLED) {
55248 +        return -EIO;
55249 +    }
55250 +
55251 +    if (ar->arConnected != TRUE) {
55252 +        return -EINVAL;
55253 +    }
55254 +
55255 +    A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid));
55256 +    ap_addr->sa_family = ARPHRD_ETHER;
55257 +
55258 +    return 0;
55259 +}
55260 +
55261 +/*
55262 + * SIOCGIWAPLIST
55263 + */
55264 +int
55265 +ar6000_ioctl_iwaplist(struct net_device *dev,
55266 +            struct iw_request_info *info,
55267 +            struct iw_point *data, char *extra)
55268 +{
55269 +    return -EIO;            /* for now */
55270 +}
55271 +
55272 +/*
55273 + * SIOCSIWSCAN
55274 + */
55275 +int
55276 +ar6000_ioctl_siwscan(struct net_device *dev,
55277 +                     struct iw_request_info *info,
55278 +                     struct iw_point *data, char *extra)
55279 +{
55280 +#define ACT_DWELLTIME_DEFAULT   105
55281 +#define HOME_TXDRAIN_TIME       100
55282 +#define SCAN_INT                HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT
55283 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55284 +    int ret = 0;
55285 +
55286 +    if (ar->arWmiReady == FALSE) {
55287 +        return -EIO;
55288 +    }
55289 +
55290 +    if (ar->arWlanState == WLAN_DISABLED) {
55291 +        return -EIO;
55292 +    }
55293 +
55294 +    /* We ask for everything from the target */
55295 +    if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
55296 +           printk("Couldn't set filtering\n");
55297 +           ret = -EIO;
55298 +    }
55299 +
55300 +    if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, FALSE, FALSE, \
55301 +                          HOME_TXDRAIN_TIME, SCAN_INT) != A_OK) {
55302 +        ret = -EIO;
55303 +    }
55304 +
55305 +    ar->scan_complete = 0;
55306 +    wait_event_interruptible_timeout(ar6000_scan_queue, ar->scan_complete,
55307 +                                    5 * HZ);
55308 +
55309 +    if (wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0) != A_OK) {
55310 +           printk("Couldn't set filtering\n");
55311 +           ret = -EIO;
55312 +    }
55313 +
55314 +    return ret;
55315 +#undef  ACT_DWELLTIME_DEFAULT
55316 +#undef HOME_TXDRAIN_TIME
55317 +#undef SCAN_INT
55318 +}
55319 +
55320 +
55321 +/*
55322 + * Units are in db above the noise floor. That means the
55323 + * rssi values reported in the tx/rx descriptors in the
55324 + * driver are the SNR expressed in db.
55325 + *
55326 + * If you assume that the noise floor is -95, which is an
55327 + * excellent assumption 99.5 % of the time, then you can
55328 + * derive the absolute signal level (i.e. -95 + rssi).
55329 + * There are some other slight factors to take into account
55330 + * depending on whether the rssi measurement is from 11b,
55331 + * 11g, or 11a.   These differences are at most 2db and
55332 + * can be documented.
55333 + *
55334 + * NB: various calculations are based on the orinoco/wavelan
55335 + *     drivers for compatibility
55336 + */
55337 +static void
55338 +ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi)
55339 +{
55340 +    if (rssi < 0) {
55341 +        iq->qual = 0;
55342 +    } else {
55343 +        iq->qual = rssi;
55344 +    }
55345 +
55346 +    /* NB: max is 94 because noise is hardcoded to 161 */
55347 +    if (iq->qual > 94)
55348 +        iq->qual = 94;
55349 +
55350 +    iq->noise = 161;        /* -95dBm */
55351 +    iq->level = iq->noise + iq->qual;
55352 +    iq->updated = 7;
55353 +}
55354 +
55355 +
55356 +/* Structures to export the Wireless Handlers */
55357 +static const iw_handler ath_handlers[] = {
55358 +    (iw_handler) NULL,                          /* SIOCSIWCOMMIT */
55359 +    (iw_handler) ar6000_ioctl_giwname,          /* SIOCGIWNAME */
55360 +    (iw_handler) NULL,                          /* SIOCSIWNWID */
55361 +    (iw_handler) NULL,                          /* SIOCGIWNWID */
55362 +    (iw_handler) ar6000_ioctl_siwfreq,          /* SIOCSIWFREQ */
55363 +    (iw_handler) ar6000_ioctl_giwfreq,          /* SIOCGIWFREQ */
55364 +    (iw_handler) ar6000_ioctl_siwmode,          /* SIOCSIWMODE */
55365 +    (iw_handler) ar6000_ioctl_giwmode,          /* SIOCGIWMODE */
55366 +    (iw_handler) ar6000_ioctl_siwsens,          /* SIOCSIWSENS */
55367 +    (iw_handler) ar6000_ioctl_giwsens,          /* SIOCGIWSENS */
55368 +    (iw_handler) NULL /* not _used */,          /* SIOCSIWRANGE */
55369 +    (iw_handler) ar6000_ioctl_giwrange,         /* SIOCGIWRANGE */
55370 +    (iw_handler) NULL /* not used */,           /* SIOCSIWPRIV */
55371 +    (iw_handler) NULL /* kernel code */,        /* SIOCGIWPRIV */
55372 +    (iw_handler) NULL /* not used */,           /* SIOCSIWSTATS */
55373 +    (iw_handler) NULL /* kernel code */,        /* SIOCGIWSTATS */
55374 +    (iw_handler) NULL,                          /* SIOCSIWSPY */
55375 +    (iw_handler) NULL,                          /* SIOCGIWSPY */
55376 +    (iw_handler) NULL,                          /* SIOCSIWTHRSPY */
55377 +    (iw_handler) NULL,                          /* SIOCGIWTHRSPY */
55378 +    (iw_handler) ar6000_ioctl_siwap,            /* SIOCSIWAP */
55379 +    (iw_handler) ar6000_ioctl_giwap,            /* SIOCGIWAP */
55380 +    (iw_handler) NULL,                          /* -- hole -- */
55381 +    (iw_handler) ar6000_ioctl_iwaplist,         /* SIOCGIWAPLIST */
55382 +    (iw_handler) ar6000_ioctl_siwscan,          /* SIOCSIWSCAN */
55383 +    (iw_handler) ar6000_ioctl_giwscan,          /* SIOCGIWSCAN */
55384 +    (iw_handler) ar6000_ioctl_siwessid,         /* SIOCSIWESSID */
55385 +    (iw_handler) ar6000_ioctl_giwessid,         /* SIOCGIWESSID */
55386 +    (iw_handler) NULL,                          /* SIOCSIWNICKN */
55387 +    (iw_handler) NULL,                          /* SIOCGIWNICKN */
55388 +    (iw_handler) NULL,                          /* -- hole -- */
55389 +    (iw_handler) NULL,                          /* -- hole -- */
55390 +    (iw_handler) ar6000_ioctl_siwrate,          /* SIOCSIWRATE */
55391 +    (iw_handler) ar6000_ioctl_giwrate,          /* SIOCGIWRATE */
55392 +    (iw_handler) NULL,           /* SIOCSIWRTS */
55393 +    (iw_handler) NULL,           /* SIOCGIWRTS */
55394 +    (iw_handler) NULL,          /* SIOCSIWFRAG */
55395 +    (iw_handler) NULL,          /* SIOCGIWFRAG */
55396 +    (iw_handler) ar6000_ioctl_siwtxpow,         /* SIOCSIWTXPOW */
55397 +    (iw_handler) ar6000_ioctl_giwtxpow,         /* SIOCGIWTXPOW */
55398 +    (iw_handler) ar6000_ioctl_siwretry,         /* SIOCSIWRETRY */
55399 +    (iw_handler) ar6000_ioctl_giwretry,         /* SIOCGIWRETRY */
55400 +    (iw_handler) ar6000_ioctl_siwencode,        /* SIOCSIWENCODE */
55401 +    (iw_handler) ar6000_ioctl_giwencode,        /* SIOCGIWENCODE */
55402 +    (iw_handler) ar6000_ioctl_siwpower,         /* SIOCSIWPOWER */
55403 +    (iw_handler) ar6000_ioctl_giwpower,         /* SIOCGIWPOWER */
55404 +    (iw_handler) NULL, /* -- hole -- */
55405 +    (iw_handler) NULL, /* -- hole -- */
55406 +    (iw_handler) ar6000_ioctl_siwgenie,        /* SIOCSIWGENIE */
55407 +    (iw_handler) ar6000_ioctl_giwgenie,        /* SIOCGIWGENIE */
55408 +    (iw_handler) ar6000_ioctl_siwauth, /* SIOCSIWAUTH */
55409 +    (iw_handler) ar6000_ioctl_giwauth, /* SIOCGIWAUTH */
55410 +    (iw_handler) ar6000_ioctl_siwencodeext,/* SIOCSIWENCODEEXT */
55411 +    (iw_handler) ar6000_ioctl_giwencodeext,/* SIOCGIWENCODEEXT */
55412 +    (iw_handler) NULL,         /* SIOCSIWPMKSA */
55413 +};
55414 +
55415 +static const iw_handler ath_priv_handlers[] = {
55416 +    (iw_handler) ar6000_ioctl_setparam,         /* SIOCWFIRSTPRIV+0 */
55417 +    (iw_handler) ar6000_ioctl_getparam,         /* SIOCWFIRSTPRIV+1 */
55418 +    (iw_handler) ar6000_ioctl_setkey,           /* SIOCWFIRSTPRIV+2 */
55419 +    (iw_handler) ar6000_ioctl_setwmmparams,     /* SIOCWFIRSTPRIV+3 */
55420 +    (iw_handler) ar6000_ioctl_delkey,           /* SIOCWFIRSTPRIV+4 */
55421 +    (iw_handler) ar6000_ioctl_getwmmparams,     /* SIOCWFIRSTPRIV+5 */
55422 +    (iw_handler) ar6000_ioctl_setoptie,         /* SIOCWFIRSTPRIV+6 */
55423 +    (iw_handler) ar6000_ioctl_setmlme,          /* SIOCWFIRSTPRIV+7 */
55424 +    (iw_handler) ar6000_ioctl_addpmkid,         /* SIOCWFIRSTPRIV+8 */
55425 +};
55426 +
55427 +#define IW_PRIV_TYPE_KEY \
55428 +    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_key))
55429 +#define IW_PRIV_TYPE_DELKEY \
55430 +    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_del_key))
55431 +#define IW_PRIV_TYPE_MLME \
55432 +    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_mlme))
55433 +#define IW_PRIV_TYPE_ADDPMKID \
55434 +    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_addpmkid))
55435 +
55436 +static const struct iw_priv_args ar6000_priv_args[] = {
55437 +    { IEEE80211_IOCTL_SETKEY,
55438 +      IW_PRIV_TYPE_KEY | IW_PRIV_SIZE_FIXED, 0,       "setkey"},
55439 +    { IEEE80211_IOCTL_DELKEY,
55440 +      IW_PRIV_TYPE_DELKEY | IW_PRIV_SIZE_FIXED, 0,    "delkey"},
55441 +    { IEEE80211_IOCTL_SETPARAM,
55442 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0,   "setparam"},
55443 +    { IEEE80211_IOCTL_GETPARAM,
55444 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
55445 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,      "getparam"},
55446 +    { IEEE80211_IOCTL_SETWMMPARAMS,
55447 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 4, 0,   "setwmmparams"},
55448 +    { IEEE80211_IOCTL_GETWMMPARAMS,
55449 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3,
55450 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,      "getwmmparams"},
55451 +    { IEEE80211_IOCTL_SETOPTIE,
55452 +      IW_PRIV_TYPE_BYTE, 0,       "setie"},
55453 +    { IEEE80211_IOCTL_SETMLME,
55454 +      IW_PRIV_TYPE_MLME, 0,       "setmlme"},
55455 +    { IEEE80211_IOCTL_ADDPMKID,
55456 +      IW_PRIV_TYPE_ADDPMKID | IW_PRIV_SIZE_FIXED, 0,  "addpmkid"},
55457 +};
55458 +
55459 +void ar6000_ioctl_iwsetup(struct iw_handler_def *def)
55460 +{
55461 +    def->private_args = (struct iw_priv_args *)ar6000_priv_args;
55462 +    def->num_private_args = ARRAY_SIZE(ar6000_priv_args);
55463 +}
55464 +
55465 +struct iw_handler_def ath_iw_handler_def = {
55466 +    .standard         = (iw_handler *)ath_handlers,
55467 +    .num_standard     = ARRAY_SIZE(ath_handlers),
55468 +    .private          = (iw_handler *)ath_priv_handlers,
55469 +    .num_private      = ARRAY_SIZE(ath_priv_handlers),
55470 +};
55471 +
55472 +
55473 --- /dev/null
55474 +++ b/drivers/ar6000/bmi/bmi.c
55475 @@ -0,0 +1,657 @@
55476 +/*
55477 + * Copyright (c) 2004-2007 Atheros Communications Inc.
55478 + * All rights reserved.
55479 + *
55480 + *
55481 + *  This program is free software; you can redistribute it and/or modify
55482 + *  it under the terms of the GNU General Public License version 2 as
55483 + *  published by the Free Software Foundation;
55484 + *
55485 + *  Software distributed under the License is distributed on an "AS
55486 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
55487 + *  implied. See the License for the specific language governing
55488 + *  rights and limitations under the License.
55489 + *
55490 + *
55491 + *
55492 + */
55493 +
55494 +#include "hif.h"
55495 +#include "bmi.h"
55496 +#include "htc_api.h"
55497 +#include "bmi_internal.h"
55498 +
55499 +/*
55500 +Although we had envisioned BMI to run on top of HTC, this is not what the
55501 +final implementation boiled down to on dragon. Its a part of BSP and does
55502 +not use the HTC protocol either. On the host side, however, we were still
55503 +living with the original idea. I think the time has come to accept the truth
55504 +and separate it from HTC which has been carrying BMI's burden all this while.
55505 +It shall make HTC state machine relatively simpler
55506 +*/
55507 +
55508 +/* APIs visible to the driver */
55509 +void
55510 +BMIInit(void)
55511 +{
55512 +    bmiDone = FALSE;
55513 +}
55514 +
55515 +A_STATUS
55516 +BMIDone(HIF_DEVICE *device)
55517 +{
55518 +    A_STATUS status;
55519 +    A_UINT32 cid;
55520 +
55521 +    if (bmiDone) {
55522 +        AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n"));
55523 +        return A_OK;
55524 +    }
55525 +
55526 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device));
55527 +    bmiDone = TRUE;
55528 +    cid = BMI_DONE;
55529 +
55530 +    status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
55531 +    if (status != A_OK) {
55532 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
55533 +        return A_ERROR;
55534 +    }
55535 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n"));
55536 +
55537 +    return A_OK;
55538 +}
55539 +
55540 +A_STATUS
55541 +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info)
55542 +{
55543 +    A_STATUS status;
55544 +    A_UINT32 cid;
55545 +
55546 +    if (bmiDone) {
55547 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
55548 +        return A_ERROR;
55549 +    }
55550 +
55551 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device));
55552 +    cid = BMI_GET_TARGET_INFO;
55553 +
55554 +    status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
55555 +    if (status != A_OK) {
55556 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
55557 +        return A_ERROR;
55558 +    }
55559 +
55560 +    status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver,
55561 +                                                sizeof(targ_info->target_ver));
55562 +    if (status != A_OK) {
55563 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n"));
55564 +        return A_ERROR;
55565 +    }
55566 +
55567 +    if (targ_info->target_ver == TARGET_VERSION_SENTINAL) {
55568 +        /* Determine how many bytes are in the Target's targ_info */
55569 +        status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count,
55570 +                                            sizeof(targ_info->target_info_byte_count));
55571 +        if (status != A_OK) {
55572 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n"));
55573 +            return A_ERROR;
55574 +        }
55575 +
55576 +        /*
55577 +         * The Target's targ_info doesn't match the Host's targ_info.
55578 +         * We need to do some backwards compatibility work to make this OK.
55579 +         */
55580 +        A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info));
55581 +
55582 +        /* Read the remainder of the targ_info */
55583 +        status = bmiBufferReceive(device,
55584 +                        ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count),
55585 +                        sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count));
55586 +        if (status != A_OK) {
55587 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n",
55588 +                                                               targ_info->target_info_byte_count));
55589 +            return A_ERROR;
55590 +        }
55591 +    } else {
55592 +        /*
55593 +         * Target must be an AR6001 whose firmware does not
55594 +         * support BMI_GET_TARGET_INFO.  Construct the data
55595 +         * that it would have sent.
55596 +         */
55597 +        targ_info->target_info_byte_count = sizeof(targ_info);
55598 +        targ_info->target_type = TARGET_TYPE_AR6001;
55599 +    }
55600 +
55601 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n",
55602 +                                                               targ_info->target_ver, targ_info->target_type));
55603 +    printk("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n",
55604 +          targ_info->target_ver, targ_info->target_type);
55605 +
55606 +    return A_OK;
55607 +}
55608 +
55609 +A_STATUS
55610 +BMIReadMemory(HIF_DEVICE *device,
55611 +              A_UINT32 address,
55612 +              A_UCHAR *buffer,
55613 +              A_UINT32 length)
55614 +{
55615 +    A_UINT32 cid;
55616 +    A_STATUS status;
55617 +    A_UINT32 offset;
55618 +    A_UINT32 remaining, rxlen;
55619 +    static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)];
55620 +    memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length));
55621 +
55622 +    if (bmiDone) {
55623 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
55624 +        return A_ERROR;
55625 +    }
55626 +
55627 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
55628 +                               ("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
55629 +                               device, address, length));
55630 +
55631 +    cid = BMI_READ_MEMORY;
55632 +
55633 +    remaining = length;
55634 +
55635 +    while (remaining)
55636 +    {
55637 +        rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX;
55638 +        offset = 0;
55639 +        A_MEMCPY(&data[offset], &cid, sizeof(cid));
55640 +        offset += sizeof(cid);
55641 +        A_MEMCPY(&data[offset], &address, sizeof(address));
55642 +        offset += sizeof(address);
55643 +        A_MEMCPY(&data[offset], &rxlen, sizeof(rxlen));
55644 +        offset += sizeof(length);
55645 +
55646 +        status = bmiBufferSend(device, data, offset);
55647 +        if (status != A_OK) {
55648 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
55649 +            return A_ERROR;
55650 +        }
55651 +        status = bmiBufferReceive(device, data, rxlen);
55652 +        if (status != A_OK) {
55653 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
55654 +            return A_ERROR;
55655 +        }
55656 +        A_MEMCPY(&buffer[length - remaining], data, rxlen);
55657 +        remaining -= rxlen; address += rxlen;
55658 +    }
55659 +
55660 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n"));
55661 +    return A_OK;
55662 +}
55663 +
55664 +A_STATUS
55665 +BMIWriteMemory(HIF_DEVICE *device,
55666 +               A_UINT32 address,
55667 +               A_UCHAR *buffer,
55668 +               A_UINT32 length)
55669 +{
55670 +    A_UINT32 cid;
55671 +    A_STATUS status;
55672 +    A_UINT32 offset;
55673 +    A_UINT32 remaining, txlen;
55674 +    const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length);
55675 +    static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)];
55676 +       memset (&data, 0, header);
55677 +
55678 +    if (bmiDone) {
55679 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
55680 +        return A_ERROR;
55681 +    }
55682 +
55683 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
55684 +         ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
55685 +         device, address, length));
55686 +
55687 +    cid = BMI_WRITE_MEMORY;
55688 +
55689 +    remaining = length;
55690 +    while (remaining)
55691 +    {
55692 +        txlen = (remaining < (BMI_DATASZ_MAX - header)) ?
55693 +                                       remaining : (BMI_DATASZ_MAX - header);
55694 +        offset = 0;
55695 +        A_MEMCPY(&data[offset], &cid, sizeof(cid));
55696 +        offset += sizeof(cid);
55697 +        A_MEMCPY(&data[offset], &address, sizeof(address));
55698 +        offset += sizeof(address);
55699 +        A_MEMCPY(&data[offset], &txlen, sizeof(txlen));
55700 +        offset += sizeof(txlen);
55701 +        A_MEMCPY(&data[offset], &buffer[length - remaining], txlen);
55702 +        offset += txlen;
55703 +        status = bmiBufferSend(device, data, offset);
55704 +        if (status != A_OK) {
55705 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
55706 +            return A_ERROR;
55707 +        }
55708 +        remaining -= txlen; address += txlen;
55709 +    }
55710 +
55711 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n"));
55712 +
55713 +    return A_OK;
55714 +}
55715 +
55716 +A_STATUS
55717 +BMIExecute(HIF_DEVICE *device,
55718 +           A_UINT32 address,
55719 +           A_UINT32 *param)
55720 +{
55721 +    A_UINT32 cid;
55722 +    A_STATUS status;
55723 +    A_UINT32 offset;
55724 +    static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(*param)];
55725 +    memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(*param));
55726 +
55727 +    if (bmiDone) {
55728 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
55729 +        return A_ERROR;
55730 +    }
55731 +
55732 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
55733 +       ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
55734 +        device, address, *param));
55735 +
55736 +    cid = BMI_EXECUTE;
55737 +
55738 +    offset = 0;
55739 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
55740 +    offset += sizeof(cid);
55741 +    A_MEMCPY(&data[offset], &address, sizeof(address));
55742 +    offset += sizeof(address);
55743 +    A_MEMCPY(&data[offset], param, sizeof(*param));
55744 +    offset += sizeof(*param);
55745 +    status = bmiBufferSend(device, data, offset);
55746 +    if (status != A_OK) {
55747 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
55748 +        return A_ERROR;
55749 +    }
55750 +
55751 +    status = bmiBufferReceive(device, data, sizeof(*param));
55752 +    if (status != A_OK) {
55753 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
55754 +        return A_ERROR;
55755 +    }
55756 +
55757 +    A_MEMCPY(param, data, sizeof(*param));
55758 +
55759 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param));
55760 +    return A_OK;
55761 +}
55762 +
55763 +A_STATUS
55764 +BMISetAppStart(HIF_DEVICE *device,
55765 +               A_UINT32 address)
55766 +{
55767 +    A_UINT32 cid;
55768 +    A_STATUS status;
55769 +    A_UINT32 offset;
55770 +    static A_UCHAR data[sizeof(cid) + sizeof(address)];
55771 +    memset (&data, 0, sizeof(cid) + sizeof(address));
55772 +
55773 +    if (bmiDone) {
55774 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
55775 +        return A_ERROR;
55776 +    }
55777 +
55778 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
55779 +       ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n",
55780 +        device, address));
55781 +
55782 +    cid = BMI_SET_APP_START;
55783 +
55784 +    offset = 0;
55785 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
55786 +    offset += sizeof(cid);
55787 +    A_MEMCPY(&data[offset], &address, sizeof(address));
55788 +    offset += sizeof(address);
55789 +    status = bmiBufferSend(device, data, offset);
55790 +    if (status != A_OK) {
55791 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
55792 +        return A_ERROR;
55793 +    }
55794 +
55795 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n"));
55796 +    return A_OK;
55797 +}
55798 +
55799 +A_STATUS
55800 +BMIReadSOCRegister(HIF_DEVICE *device,
55801 +                   A_UINT32 address,
55802 +                   A_UINT32 *param)
55803 +{
55804 +    A_UINT32 cid;
55805 +    A_STATUS status;
55806 +    A_UINT32 offset;
55807 +    static A_UCHAR data[sizeof(cid) + sizeof(address)];
55808 +    memset (&data, 0, sizeof(cid) + sizeof(address));
55809 +
55810 +    if (bmiDone) {
55811 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
55812 +        return A_ERROR;
55813 +    }
55814 +
55815 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
55816 +       ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n",
55817 +       device, address));
55818 +
55819 +    cid = BMI_READ_SOC_REGISTER;
55820 +
55821 +    offset = 0;
55822 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
55823 +    offset += sizeof(cid);
55824 +    A_MEMCPY(&data[offset], &address, sizeof(address));
55825 +    offset += sizeof(address);
55826 +
55827 +    status = bmiBufferSend(device, data, offset);
55828 +    if (status != A_OK) {
55829 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
55830 +        return A_ERROR;
55831 +    }
55832 +
55833 +    status = bmiBufferReceive(device, data, sizeof(*param));
55834 +    if (status != A_OK) {
55835 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
55836 +        return A_ERROR;
55837 +    }
55838 +    A_MEMCPY(param, data, sizeof(*param));
55839 +
55840 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param));
55841 +    return A_OK;
55842 +}
55843 +
55844 +A_STATUS
55845 +BMIWriteSOCRegister(HIF_DEVICE *device,
55846 +                    A_UINT32 address,
55847 +                    A_UINT32 param)
55848 +{
55849 +    A_UINT32 cid;
55850 +    A_STATUS status;
55851 +    A_UINT32 offset;
55852 +    static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(param)];
55853 +
55854 +    memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(param));
55855 +
55856 +    if (bmiDone) {
55857 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
55858 +        return A_ERROR;
55859 +    }
55860 +
55861 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
55862 +     ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
55863 +     device, address, param));
55864 +
55865 +    cid = BMI_WRITE_SOC_REGISTER;
55866 +
55867 +    offset = 0;
55868 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
55869 +    offset += sizeof(cid);
55870 +    A_MEMCPY(&data[offset], &address, sizeof(address));
55871 +    offset += sizeof(address);
55872 +    A_MEMCPY(&data[offset], &param, sizeof(param));
55873 +    offset += sizeof(param);
55874 +    status = bmiBufferSend(device, data, offset);
55875 +    if (status != A_OK) {
55876 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
55877 +        return A_ERROR;
55878 +    }
55879 +
55880 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n"));
55881 +    return A_OK;
55882 +}
55883 +
55884 +A_STATUS
55885 +BMIrompatchInstall(HIF_DEVICE *device,
55886 +                   A_UINT32 ROM_addr,
55887 +                   A_UINT32 RAM_addr,
55888 +                   A_UINT32 nbytes,
55889 +                   A_UINT32 do_activate,
55890 +                   A_UINT32 *rompatch_id)
55891 +{
55892 +    A_UINT32 cid;
55893 +    A_STATUS status;
55894 +    A_UINT32 offset;
55895 +    static A_UCHAR data[sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
55896 +                                sizeof(nbytes) + sizeof(do_activate)];
55897 +
55898 +       memset (&data, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
55899 +                      sizeof(nbytes) + sizeof(do_activate));
55900 +
55901 +    if (bmiDone) {
55902 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
55903 +        return A_ERROR;
55904 +    }
55905 +
55906 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
55907 +         ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n",
55908 +         device, ROM_addr, RAM_addr, nbytes, do_activate));
55909 +
55910 +    cid = BMI_ROMPATCH_INSTALL;
55911 +
55912 +    offset = 0;
55913 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
55914 +    offset += sizeof(cid);
55915 +    A_MEMCPY(&data[offset], &ROM_addr, sizeof(ROM_addr));
55916 +    offset += sizeof(ROM_addr);
55917 +    A_MEMCPY(&data[offset], &RAM_addr, sizeof(RAM_addr));
55918 +    offset += sizeof(RAM_addr);
55919 +    A_MEMCPY(&data[offset], &nbytes, sizeof(nbytes));
55920 +    offset += sizeof(nbytes);
55921 +    A_MEMCPY(&data[offset], &do_activate, sizeof(do_activate));
55922 +    offset += sizeof(do_activate);
55923 +    status = bmiBufferSend(device, data, offset);
55924 +    if (status != A_OK) {
55925 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
55926 +        return A_ERROR;
55927 +    }
55928 +
55929 +    status = bmiBufferReceive(device, (A_UCHAR *)rompatch_id, sizeof(*rompatch_id));
55930 +    if (status != A_OK) {
55931 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
55932 +        return A_ERROR;
55933 +    }
55934 +
55935 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id));
55936 +    return A_OK;
55937 +}
55938 +
55939 +A_STATUS
55940 +BMIrompatchUninstall(HIF_DEVICE *device,
55941 +                     A_UINT32 rompatch_id)
55942 +{
55943 +    A_UINT32 cid;
55944 +    A_STATUS status;
55945 +    A_UINT32 offset;
55946 +    static A_UCHAR data[sizeof(cid) + sizeof(rompatch_id)];
55947 +    memset (&data, 0, sizeof(cid) + sizeof(rompatch_id));
55948 +
55949 +    if (bmiDone) {
55950 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
55951 +        return A_ERROR;
55952 +    }
55953 +
55954 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
55955 +         ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n",
55956 +                                                                        device, rompatch_id));
55957 +
55958 +    cid = BMI_ROMPATCH_UNINSTALL;
55959 +
55960 +    offset = 0;
55961 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
55962 +    offset += sizeof(cid);
55963 +    A_MEMCPY(&data[offset], &rompatch_id, sizeof(rompatch_id));
55964 +    offset += sizeof(rompatch_id);
55965 +    status = bmiBufferSend(device, data, offset);
55966 +    if (status != A_OK) {
55967 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
55968 +        return A_ERROR;
55969 +    }
55970 +
55971 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id));
55972 +    return A_OK;
55973 +}
55974 +
55975 +static A_STATUS
55976 +_BMIrompatchChangeActivation(HIF_DEVICE *device,
55977 +                             A_UINT32 rompatch_count,
55978 +                             A_UINT32 *rompatch_list,
55979 +                             A_UINT32 do_activate)
55980 +{
55981 +    A_UINT32 cid;
55982 +    A_STATUS status;
55983 +    A_UINT32 offset;
55984 +    static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)];
55985 +    A_UINT32 length;
55986 +
55987 +       memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count));
55988 +
55989 +    if (bmiDone) {
55990 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
55991 +        return A_ERROR;
55992 +    }
55993 +
55994 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
55995 +         ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n",
55996 +           device, rompatch_count));
55997 +
55998 +    cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE;
55999 +
56000 +    offset = 0;
56001 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
56002 +    offset += sizeof(cid);
56003 +    A_MEMCPY(&data[offset], &rompatch_count, sizeof(rompatch_count));
56004 +    offset += sizeof(rompatch_count);
56005 +    length = rompatch_count * sizeof(*rompatch_list);
56006 +    A_MEMCPY(&data[offset], rompatch_list, length);
56007 +    offset += length;
56008 +    status = bmiBufferSend(device, data, offset);
56009 +    if (status != A_OK) {
56010 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56011 +        return A_ERROR;
56012 +    }
56013 +
56014 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n"));
56015 +
56016 +    return A_OK;
56017 +}
56018 +
56019 +A_STATUS
56020 +BMIrompatchActivate(HIF_DEVICE *device,
56021 +                    A_UINT32 rompatch_count,
56022 +                    A_UINT32 *rompatch_list)
56023 +{
56024 +    return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1);
56025 +}
56026 +
56027 +A_STATUS
56028 +BMIrompatchDeactivate(HIF_DEVICE *device,
56029 +                      A_UINT32 rompatch_count,
56030 +                      A_UINT32 *rompatch_list)
56031 +{
56032 +    return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0);
56033 +}
56034 +
56035 +/* BMI Access routines */
56036 +A_STATUS
56037 +bmiBufferSend(HIF_DEVICE *device,
56038 +              A_UCHAR *buffer,
56039 +              A_UINT32 length)
56040 +{
56041 +    A_STATUS status;
56042 +    A_UINT32 timeout;
56043 +    A_UINT32 address;
56044 +    static A_UINT32 cmdCredits;
56045 +    A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
56046 +
56047 +    HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
56048 +                       &mboxAddress, sizeof(mboxAddress));
56049 +
56050 +    cmdCredits = 0;
56051 +    timeout = BMI_COMMUNICATION_TIMEOUT;
56052 +
56053 +    while(timeout-- && !cmdCredits) {
56054 +        /* Read the counter register to get the command credits */
56055 +        address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
56056 +        /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause
56057 +         * a decrement, while the remaining 3 bytes has no effect.  The rationale behind this is to
56058 +         * make all HIF accesses 4-byte aligned */
56059 +        status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, 4,
56060 +            HIF_RD_SYNC_BYTE_INC, NULL);
56061 +        if (status != A_OK) {
56062 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n"));
56063 +            return A_ERROR;
56064 +        }
56065 +        /* the counter is only 8=bits, ignore anything in the upper 3 bytes */
56066 +        cmdCredits &= 0xFF;
56067 +    }
56068 +
56069 +    if (cmdCredits) {
56070 +        address = mboxAddress[ENDPOINT1];
56071 +        status = HIFReadWrite(device, address, buffer, length,
56072 +            HIF_WR_SYNC_BYTE_INC, NULL);
56073 +        if (status != A_OK) {
56074 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n"));
56075 +            return A_ERROR;
56076 +        }
56077 +    } else {
56078 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout\n"));
56079 +        return A_ERROR;
56080 +    }
56081 +
56082 +    return status;
56083 +}
56084 +
56085 +A_STATUS
56086 +bmiBufferReceive(HIF_DEVICE *device,
56087 +                 A_UCHAR *buffer,
56088 +                 A_UINT32 length)
56089 +{
56090 +    A_STATUS status;
56091 +    A_UINT32 address;
56092 +    A_UINT32 timeout;
56093 +    static A_UINT32 cmdCredits;
56094 +    A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
56095 +
56096 +    HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
56097 +                       &mboxAddress, sizeof(mboxAddress));
56098 +
56099 +    cmdCredits = 0;
56100 +    timeout = BMI_COMMUNICATION_TIMEOUT;
56101 +    while(timeout-- && !cmdCredits) {
56102 +        /* Read the counter register to get the command credits */
56103 +        address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1;
56104 +        /* read the counter using a 4-byte read.  Since the counter is NOT auto-decrementing,
56105 +         * we can read this counter multiple times using a non-incrementing address mode.
56106 +         * The rationale here is to make all HIF accesses a multiple of 4 bytes */
56107 +        status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, sizeof(cmdCredits),
56108 +            HIF_RD_SYNC_BYTE_FIX, NULL);
56109 +        if (status != A_OK) {
56110 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n"));
56111 +            return A_ERROR;
56112 +        }
56113 +            /* we did a 4-byte read to the same count register so mask off upper bytes */
56114 +        cmdCredits &= 0xFF;
56115 +        status = A_ERROR;
56116 +    }
56117 +
56118 +    if (cmdCredits) {
56119 +        address = mboxAddress[ENDPOINT1];
56120 +        status = HIFReadWrite(device, address, buffer, length,
56121 +            HIF_RD_SYNC_BYTE_INC, NULL);
56122 +        if (status != A_OK) {
56123 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n"));
56124 +            return A_ERROR;
56125 +        }
56126 +    } else {
56127 +        AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout\n"));
56128 +        return A_ERROR;
56129 +    }
56130 +
56131 +    return status;
56132 +}
56133 --- /dev/null
56134 +++ b/drivers/ar6000/bmi/bmi_internal.h
56135 @@ -0,0 +1,45 @@
56136 +#ifndef BMI_INTERNAL_H
56137 +#define BMI_INTERNAL_H
56138 +/*
56139 + *
56140 + * Copyright (c) 2004-2007 Atheros Communications Inc.
56141 + * All rights reserved.
56142 + *
56143 + *
56144 + *  This program is free software; you can redistribute it and/or modify
56145 + *  it under the terms of the GNU General Public License version 2 as
56146 + *  published by the Free Software Foundation;
56147 + *
56148 + *  Software distributed under the License is distributed on an "AS
56149 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
56150 + *  implied. See the License for the specific language governing
56151 + *  rights and limitations under the License.
56152 + *
56153 + *
56154 + *
56155 + */
56156 +
56157 +#include "a_config.h"
56158 +#include "athdefs.h"
56159 +#include "a_types.h"
56160 +#include "a_osapi.h"
56161 +#include "a_debug.h"
56162 +#include "AR6Khwreg.h"
56163 +#include "bmi_msg.h"
56164 +
56165 +#define BMI_COMMUNICATION_TIMEOUT       100000
56166 +
56167 +/* ------ Global Variable Declarations ------- */
56168 +A_BOOL bmiDone;
56169 +
56170 +A_STATUS
56171 +bmiBufferSend(HIF_DEVICE *device,
56172 +              A_UCHAR *buffer,
56173 +              A_UINT32 length);
56174 +
56175 +A_STATUS
56176 +bmiBufferReceive(HIF_DEVICE *device,
56177 +                 A_UCHAR *buffer,
56178 +                 A_UINT32 length);
56179 +
56180 +#endif
56181 --- /dev/null
56182 +++ b/drivers/ar6000/hif/hif2.c
56183 @@ -0,0 +1,646 @@
56184 +/*
56185 + * hif2.c - HIF layer re-implementation for the Linux SDIO stack
56186 + *
56187 + * Copyright (C) 2008 by OpenMoko, Inc.
56188 + * Written by Werner Almesberger <werner@openmoko.org>
56189 + * All Rights Reserved
56190 + *
56191 + * This program is free software; you can redistribute it and/or modify
56192 + * it under the terms of the GNU General Public License version 2 as
56193 + * published by the Free Software Foundation;
56194 + *
56195 + * Based on:
56196 + *
56197 + * @abstract: HIF layer reference implementation for Atheros SDIO stack
56198 + * @notice: Copyright (c) 2004-2006 Atheros Communications Inc.
56199 + */
56200 +
56201 +
56202 +#include <linux/kernel.h>
56203 +#include <linux/kthread.h>
56204 +#include <linux/list.h>
56205 +#include <linux/wait.h>
56206 +#include <linux/spinlock.h>
56207 +#include <linux/sched.h>
56208 +#include <linux/mmc/sdio_func.h>
56209 +#include <linux/mmc/sdio.h>
56210 +#include <linux/mmc/sdio_ids.h>
56211 +#include <asm/gpio.h>
56212 +
56213 +#include "athdefs.h"
56214 +#include "a_types.h"
56215 +#include "hif.h"
56216 +
56217 +
56218 +/*
56219 + * KNOWN BUGS:
56220 + *
56221 + * - HIF_DEVICE_IRQ_ASYNC_SYNC doesn't work yet (gets MMC errors)
56222 + * - latency can reach hundreds of ms, probably because of scheduling delays
56223 + * - packets go through about three queues before finally hitting the network
56224 + */
56225 +
56226 +/*
56227 + * Differences from Atheros' HIFs:
56228 + *
56229 + * - synchronous and asynchronous requests may get reordered with respect to
56230 + *   each other, e.g., if HIFReadWrite returns for an asynchronous request and
56231 + *   then HIFReadWrite is called for a synchronous request, the synchronous
56232 + *   request may be executed before the asynchronous request.
56233 + *
56234 + * - request queue locking seems unnecessarily complex in the Atheros HIFs.
56235 + *
56236 + * - Atheros mask interrupts by calling sdio_claim_irq/sdio_release_irq, which
56237 + *   can cause quite a bit of overhead. This HIF has its own light-weight
56238 + *   interrupt masking.
56239 + *
56240 + * - Atheros call deviceInsertedHandler from a thread spawned off the probe or
56241 + *   device insertion function. The original explanation for the Atheros SDIO
56242 + *   stack said that this is done because a delay is needed to let the chip
56243 + *   complete initialization. There is indeed a one second delay in the thread.
56244 + *
56245 + *   The Atheros Linux SDIO HIF removes the delay and only retains the thread.
56246 + *   Experimentally removing the thread didn't show any conflicts, so let's get
56247 + *   rid of it for good.
56248 + *
56249 + * - The Atheros SDIO stack with Samuel's driver sets SDIO_CCCR_POWER in
56250 + *   SDIO_POWER_EMPC. Atheros' Linux SDIO code apparently doesn't. We don't
56251 + *   either, and this seems to work fine.
56252 + *   @@@ Need to check this with Atheros.
56253 + */
56254 +
56255 +
56256 +#define MBOXES                 4
56257 +
56258 +#define HIF_MBOX_BLOCK_SIZE    128
56259 +#define        HIF_MBOX_BASE_ADDR      0x800
56260 +#define        HIF_MBOX_WIDTH          0x800
56261 +#define        HIF_MBOX_START_ADDR(mbox) \
56262 +    (HIF_MBOX_BASE_ADDR+(mbox)*HIF_MBOX_WIDTH)
56263 +
56264 +
56265 +struct hif_device {
56266 +       void *htc_handle;
56267 +       struct sdio_func *func;
56268 +
56269 +       /*
56270 +        * @@@ our sweet little bit of bogosity - the mechanism that lets us
56271 +        * use the SDIO stack from softirqs. This really wants to use skbs.
56272 +        */
56273 +       struct list_head queue;
56274 +       spinlock_t queue_lock;
56275 +       struct task_struct *io_task;
56276 +       wait_queue_head_t wait;
56277 +};
56278 +
56279 +struct hif_request {
56280 +       struct list_head list;
56281 +       struct sdio_func *func;
56282 +       int (*read)(struct sdio_func *func,
56283 +           void *dst, unsigned int addr, int count);
56284 +       int (*write)(struct sdio_func *func,
56285 +           unsigned int addr, void *src, int count);
56286 +       void *buf;
56287 +       unsigned long addr;
56288 +       int len;
56289 +       A_STATUS (*completion)(void *context, A_STATUS status);
56290 +       void *context;
56291 +};
56292 +
56293 +
56294 +static HTC_CALLBACKS htcCallbacks;
56295 +
56296 +/*
56297 + * shutdown_lock prevents recursion through HIFShutDownDevice
56298 + */
56299 +static DEFINE_MUTEX(shutdown_lock);
56300 +
56301 +
56302 +/* ----- Request processing ------------------------------------------------ */
56303 +
56304 +
56305 +static A_STATUS process_request(struct hif_request *req)
56306 +{
56307 +       int ret;
56308 +       A_STATUS status;
56309 +
56310 +       dev_dbg(&req->func->dev, "process_request(req %p)\n", req);
56311 +       sdio_claim_host(req->func);
56312 +       if (req->read)
56313 +               ret = req->read(req->func, req->buf, req->addr, req->len);
56314 +       else
56315 +               ret = req->write(req->func, req->addr, req->buf, req->len);
56316 +       sdio_release_host(req->func);
56317 +       status = ret ? A_ERROR : A_OK;
56318 +       if (req->completion)
56319 +               req->completion(req->context, status);
56320 +       kfree(req);
56321 +       return status;
56322 +}
56323 +
56324 +
56325 +static void enqueue_request(struct hif_device *hif, struct hif_request *req)
56326 +{
56327 +       unsigned long flags;
56328 +
56329 +       dev_dbg(&req->func->dev, "enqueue_request(req %p)\n", req);
56330 +       spin_lock_irqsave(&hif->queue_lock, flags);
56331 +       list_add_tail(&req->list, &hif->queue);
56332 +       spin_unlock_irqrestore(&hif->queue_lock, flags);
56333 +       wake_up(&hif->wait);
56334 +}
56335 +
56336 +
56337 +static struct hif_request *dequeue_request(struct hif_device *hif)
56338 +{
56339 +       struct hif_request *req;
56340 +       unsigned long flags;
56341 +
56342 +       spin_lock_irqsave(&hif->queue_lock, flags);
56343 +       if (list_empty(&hif->queue))
56344 +               req = NULL;
56345 +       else {
56346 +               req = list_first_entry(&hif->queue,
56347 +                   struct hif_request, list);
56348 +               list_del(&req->list);
56349 +       }
56350 +       spin_unlock_irqrestore(&hif->queue_lock, flags);
56351 +       return req;
56352 +}
56353 +
56354 +
56355 +static void wait_queue_empty(struct hif_device *hif)
56356 +{
56357 +       unsigned long flags;
56358 +       int empty;
56359 +
56360 +       while (1) {
56361 +               spin_lock_irqsave(&hif->queue_lock, flags);
56362 +               empty = list_empty(&hif->queue);
56363 +               spin_unlock_irqrestore(&hif->queue_lock, flags);
56364 +               if (empty)
56365 +                       break;
56366 +               else
56367 +                       yield();
56368 +       }
56369 +}
56370 +
56371 +
56372 +static int io(void *data)
56373 +{
56374 +       struct hif_device *hif = data;
56375 +       struct sched_param param = { .sched_priority = 2 };
56376 +               /* one priority level slower than ksdioirqd (which is at 1) */
56377 +       DEFINE_WAIT(wait);
56378 +       struct hif_request *req;
56379 +
56380 +       sched_setscheduler(current, SCHED_FIFO, &param);
56381 +
56382 +       while (1) {
56383 +               while (1) {
56384 +                       /*
56385 +                        * Since we never use signals here, one might think
56386 +                        * that this ought to be TASK_UNINTERRUPTIBLE. However,
56387 +                        * such a task would increase the load average and,
56388 +                        * worse, it would trigger the softlockup check.
56389 +                        */
56390 +                       prepare_to_wait(&hif->wait, &wait, TASK_INTERRUPTIBLE);
56391 +                       if (kthread_should_stop()) {
56392 +                               finish_wait(&hif->wait, &wait);
56393 +                               return 0;
56394 +                       }
56395 +                       req = dequeue_request(hif);
56396 +                       if (req)
56397 +                               break;
56398 +                       schedule();
56399 +               }
56400 +               finish_wait(&hif->wait, &wait);
56401 +
56402 +               (void) process_request(req);
56403 +       }
56404 +       return 0;
56405 +}
56406 +
56407 +
56408 +A_STATUS HIFReadWrite(HIF_DEVICE *hif, A_UINT32 address, A_UCHAR *buffer,
56409 +    A_UINT32 length, A_UINT32 request, void *context)
56410 +{
56411 +       struct device *dev = HIFGetOSDevice(hif);
56412 +       struct hif_request *req;
56413 +
56414 +       dev_dbg(dev, "HIFReadWrite(device %p, address 0x%x, buffer %p, "
56415 +           "length %d, request 0x%x, context %p)\n",
56416 +           hif, address, buffer, length, request, context);
56417 +
56418 +       BUG_ON(!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)));
56419 +       BUG_ON(!(request & (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)));
56420 +       BUG_ON(!(request & (HIF_READ | HIF_WRITE)));
56421 +       BUG_ON(!(request & HIF_EXTENDED_IO));
56422 +
56423 +       if (address >= HIF_MBOX_START_ADDR(0) &&
56424 +           address < HIF_MBOX_START_ADDR(MBOXES+1)) {
56425 +               BUG_ON(length > HIF_MBOX_WIDTH);
56426 +               /* Adjust the address so that the last byte falls on the EOM
56427 +                  address. */
56428 +               address += HIF_MBOX_WIDTH-length;
56429 +       }
56430 +
56431 +       req = kzalloc(sizeof(*req), GFP_ATOMIC);
56432 +       if (!req) {
56433 +               if (request & HIF_ASYNCHRONOUS)
56434 +                       htcCallbacks.rwCompletionHandler(context, A_ERROR);
56435 +               return A_ERROR;
56436 +       }
56437 +
56438 +       req->func = hif->func;
56439 +       req->addr = address;
56440 +       req->buf = buffer;
56441 +       req->len = length;
56442 +
56443 +       if (request & HIF_READ) {
56444 +               if (request & HIF_FIXED_ADDRESS)
56445 +                       req->read = sdio_readsb;
56446 +               else
56447 +                       req->read = sdio_memcpy_fromio;
56448 +       } else {
56449 +               if (request & HIF_FIXED_ADDRESS)
56450 +                       req->write = sdio_writesb;
56451 +               else
56452 +                       req->write = sdio_memcpy_toio;
56453 +       }
56454 +
56455 +       if (!(request & HIF_ASYNCHRONOUS))
56456 +               return process_request(req);
56457 +
56458 +       req->completion = htcCallbacks.rwCompletionHandler;
56459 +       req->context = context;
56460 +       enqueue_request(hif, req);
56461 +
56462 +       return A_OK;
56463 +}
56464 +
56465 +
56466 +/* ----- Interrupt handling ------------------------------------------------ */
56467 +
56468 +/*
56469 + * Volatile ought to be good enough to make gcc do the right thing on S3C24xx.
56470 + * No need to use atomic or put barriers, keeping the code more readable.
56471 + *
56472 + * Warning: this story changes if going SMP/SMT.
56473 + */
56474 +
56475 +static volatile int masked = 1;
56476 +static volatile int pending;
56477 +static volatile int in_interrupt;
56478 +
56479 +
56480 +static void ar6000_do_irq(struct sdio_func *func)
56481 +{
56482 +       HIF_DEVICE *hif = sdio_get_drvdata(func);
56483 +       struct device *dev = HIFGetOSDevice(hif);
56484 +       A_STATUS status;
56485 +
56486 +       dev_dbg(dev, "ar6000_do_irq -> %p\n", htcCallbacks.dsrHandler);
56487 +
56488 +       status = htcCallbacks.dsrHandler(hif->htc_handle);
56489 +       BUG_ON(status != A_OK);
56490 +}
56491 +
56492 +
56493 +static void sdio_ar6000_irq(struct sdio_func *func)
56494 +{
56495 +       HIF_DEVICE *hif = sdio_get_drvdata(func);
56496 +       struct device *dev = HIFGetOSDevice(hif);
56497 +
56498 +       dev_dbg(dev, "sdio_ar6000_irq\n");
56499 +
56500 +       in_interrupt = 1;
56501 +       if (masked) {
56502 +               in_interrupt = 0;
56503 +               pending++;
56504 +               return;
56505 +       }
56506 +       /*
56507 +        * @@@ This is ugly. If we don't drop the lock, we'll deadlock when
56508 +        * the handler tries to do SDIO. So there are four choices:
56509 +        *
56510 +        * 1) Break the call chain by calling the callback from a workqueue.
56511 +        *    Ugh.
56512 +        * 2) Make process_request aware that we already have the lock.
56513 +        * 3) Drop the lock. Which is ugly but should be safe as long as we're
56514 +        *    making sure the device doesn't go away.
56515 +        * 4) Change the AR6k driver such that it only issues asynchronous
56516 +        *    quests when called from an interrupt.
56517 +        *
56518 +        * Solution 2) is probably the best for now. Will try it later.
56519 +        */
56520 +       sdio_release_host(func);
56521 +       ar6000_do_irq(func);
56522 +       sdio_claim_host(func);
56523 +       in_interrupt = 0;
56524 +}
56525 +
56526 +
56527 +void HIFAckInterrupt(HIF_DEVICE *hif)
56528 +{
56529 +       struct device *dev = HIFGetOSDevice(hif);
56530 +
56531 +       dev_dbg(dev, "HIFAckInterrupt\n");
56532 +       /* do nothing */
56533 +}
56534 +
56535 +
56536 +void HIFUnMaskInterrupt(HIF_DEVICE *hif)
56537 +{
56538 +       struct device *dev = HIFGetOSDevice(hif);
56539 +
56540 +       dev_dbg(dev, "HIFUnMaskInterrupt\n");
56541 +       do {
56542 +               masked = 1;
56543 +               if (pending) {
56544 +                       pending = 0;
56545 +                       ar6000_do_irq(hif->func);
56546 +                       /* We may take an interrupt before unmasking and thus
56547 +                          get it pending. In this case, we just loop back. */
56548 +               }
56549 +               masked = 0;
56550 +       }
56551 +       while (pending);
56552 +}
56553 +
56554 +
56555 +void HIFMaskInterrupt(HIF_DEVICE *hif)
56556 +{
56557 +       struct device *dev = HIFGetOSDevice(hif);
56558 +
56559 +       dev_dbg(dev, "HIFMaskInterrupt\n");
56560 +       /*
56561 +        * Since sdio_ar6000_irq can also be called from a process context, we
56562 +        * may conceivably end up racing with it. Thus, we need to wait until
56563 +        * we can be sure that no concurrent interrupt processing is going on
56564 +        * before we return.
56565 +        *
56566 +        * Note: this may be a bit on the paranoid side - the callers may
56567 +        * actually be nice enough to disable scheduling. Check later.
56568 +        */
56569 +       masked = 1;
56570 +       while (in_interrupt)
56571 +               yield();
56572 +}
56573 +
56574 +
56575 +/* ----- HIF API glue functions -------------------------------------------- */
56576 +
56577 +
56578 +struct device *HIFGetOSDevice(HIF_DEVICE *hif)
56579 +{
56580 +       return &hif->func->dev;
56581 +}
56582 +
56583 +
56584 +void HIFSetHandle(void *hif_handle, void *handle)
56585 +{
56586 +       HIF_DEVICE *hif = (HIF_DEVICE *) hif_handle;
56587 +
56588 +       hif->htc_handle = handle;
56589 +}
56590 +
56591 +
56592 +/* ----- Device configuration (HIF side) ----------------------------------- */
56593 +
56594 +
56595 +A_STATUS HIFConfigureDevice(HIF_DEVICE *hif,
56596 +    HIF_DEVICE_CONFIG_OPCODE opcode, void *config, A_UINT32 configLen)
56597 +{
56598 +       struct device *dev = HIFGetOSDevice(hif);
56599 +       HIF_DEVICE_IRQ_PROCESSING_MODE *ipm_cfg = config;
56600 +       A_UINT32 *mbs_cfg = config;
56601 +       int i;
56602 +
56603 +       dev_dbg(dev, "HIFConfigureDevice\n");
56604 +
56605 +       switch (opcode) {
56606 +       case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
56607 +               for (i = 0; i != MBOXES; i++)
56608 +                       mbs_cfg[i] = HIF_MBOX_BLOCK_SIZE;
56609 +               break;
56610 +       case HIF_DEVICE_GET_MBOX_ADDR:
56611 +               for (i = 0; i != MBOXES; i++)
56612 +                       mbs_cfg[i] = HIF_MBOX_START_ADDR(i);
56613 +               break;
56614 +       case HIF_DEVICE_GET_IRQ_PROC_MODE:
56615 +               *ipm_cfg = HIF_DEVICE_IRQ_SYNC_ONLY;
56616 +//             *ipm_cfg = HIF_DEVICE_IRQ_ASYNC_SYNC;
56617 +               break;
56618 +       default:
56619 +               return A_ERROR;
56620 +       }
56621 +       return A_OK;
56622 +}
56623 +
56624 +
56625 +/* ----- Device probe and removal (Linux side) ----------------------------- */
56626 +
56627 +
56628 +static int sdio_ar6000_probe(struct sdio_func *func,
56629 +    const struct sdio_device_id *id)
56630 +{
56631 +       struct device *dev = &func->dev;
56632 +       struct hif_device *hif;
56633 +       int ret;
56634 +
56635 +       dev_dbg(dev, "sdio_ar6000_probe\n");
56636 +       BUG_ON(!htcCallbacks.deviceInsertedHandler);
56637 +
56638 +       hif = kzalloc(sizeof(*hif), GFP_KERNEL);
56639 +       if (!hif)
56640 +               return -ENOMEM;
56641 +
56642 +       sdio_set_drvdata(func, hif);
56643 +       sdio_claim_host(func);
56644 +       sdio_enable_func(func);
56645 +
56646 +       hif->func = func;
56647 +       INIT_LIST_HEAD(&hif->queue);
56648 +       init_waitqueue_head(&hif->wait);
56649 +       spin_lock_init(&hif->queue_lock);
56650 +
56651 +       ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
56652 +       if (ret < 0) {
56653 +               dev_err(dev, "sdio_set_block_size returns %d\n", ret);
56654 +               goto out_enabled;
56655 +       }
56656 +       ret = sdio_claim_irq(func, sdio_ar6000_irq);
56657 +       if (ret) {
56658 +               dev_err(dev, "sdio_claim_irq returns %d\n", ret);
56659 +               goto out_enabled;
56660 +       }
56661 +       /* Set SDIO_BUS_CD_DISABLE in SDIO_CCCR_IF ? */
56662 +#if 0
56663 +       sdio_f0_writeb(func, SDIO_CCCR_CAP_E4MI, SDIO_CCCR_CAPS, &ret);
56664 +       if (ret) {
56665 +               dev_err(dev, "sdio_f0_writeb(SDIO_CCCR_CAPS) returns %d\n",
56666 +                   ret);
56667 +               goto out_got_irq;
56668 +       }
56669 +#else
56670 +       if (0) /* avoid warning */
56671 +               goto out_got_irq;
56672 +#endif
56673 +
56674 +       sdio_release_host(func);
56675 +
56676 +       hif->io_task = kthread_run(io, hif, "ar6000_io");
56677 +       if (IS_ERR(hif->io_task)) {
56678 +               dev_err(dev, "kthread_run(ar6000_io): %d\n", ret);
56679 +               goto out_func_ready;
56680 +       }
56681 +
56682 +       ret = htcCallbacks.deviceInsertedHandler(hif);
56683 +       if (ret == A_OK)
56684 +               return 0;
56685 +
56686 +       dev_err(dev, "deviceInsertedHandler: %d\n", ret);
56687 +
56688 +       ret = kthread_stop(hif->io_task);
56689 +       if (ret)
56690 +               dev_err(dev, "kthread_stop (ar6000_io): %d\n", ret);
56691 +
56692 +out_func_ready:
56693 +       sdio_claim_host(func);
56694 +
56695 +out_got_irq:
56696 +       sdio_release_irq(func);
56697 +
56698 +out_enabled:
56699 +       sdio_set_drvdata(func, NULL);
56700 +       sdio_disable_func(func);
56701 +       sdio_release_host(func);
56702 +
56703 +       return ret;
56704 +}
56705 +
56706 +
56707 +static void sdio_ar6000_remove(struct sdio_func *func)
56708 +{
56709 +       struct device *dev = &func->dev;
56710 +       HIF_DEVICE *hif = sdio_get_drvdata(func);
56711 +       int ret;
56712 +
56713 +       dev_dbg(dev, "sdio_ar6000_remove\n");
56714 +       if (mutex_trylock(&shutdown_lock)) {
56715 +               /*
56716 +                * Funny, Atheros' HIF does this call, but this just puts us in
56717 +                * a recursion through HTCShutDown/HIFShutDown if unloading the
56718 +                * module.
56719 +                *
56720 +                * However, we need it for suspend/resume. See the comment at
56721 +                * HIFShutDown, below.
56722 +                */
56723 +               ret = htcCallbacks.deviceRemovedHandler(hif->htc_handle, A_OK);
56724 +               if (ret != A_OK)
56725 +                       dev_err(dev, "deviceRemovedHandler: %d\n", ret);
56726 +               mutex_unlock(&shutdown_lock);
56727 +       }
56728 +       wait_queue_empty(hif);
56729 +       ret = kthread_stop(hif->io_task);
56730 +       if (ret)
56731 +               dev_err(dev, "kthread_stop (ar6000_io): %d\n", ret);
56732 +       sdio_claim_host(func);
56733 +       sdio_release_irq(func);
56734 +       sdio_set_drvdata(func, NULL);
56735 +       sdio_disable_func(func);
56736 +       sdio_release_host(func);
56737 +       kfree(hif);
56738 +}
56739 +
56740 +
56741 +/* ----- Device registration/unregistration (called by HIF) ---------------- */
56742 +
56743 +
56744 +#define ATHEROS_SDIO_DEVICE(id, offset) \
56745 +    SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_##id | (offset))
56746 +
56747 +static const struct sdio_device_id sdio_ar6000_ids[] = {
56748 +       { ATHEROS_SDIO_DEVICE(AR6000, 0)        },
56749 +       { ATHEROS_SDIO_DEVICE(AR6000, 0x1)      },
56750 +       { ATHEROS_SDIO_DEVICE(AR6000, 0x8)      },
56751 +       { ATHEROS_SDIO_DEVICE(AR6000, 0x9)      },
56752 +       { ATHEROS_SDIO_DEVICE(AR6000, 0xa)      },
56753 +       { ATHEROS_SDIO_DEVICE(AR6000, 0xb)      },
56754 +       { /* end: all zeroes */                 },
56755 +};
56756 +
56757 +MODULE_DEVICE_TABLE(sdio, sdio_ar6000_ids);
56758 +
56759 +
56760 +static struct sdio_driver sdio_ar6000_driver = {
56761 +       .probe          = sdio_ar6000_probe,
56762 +       .remove         = sdio_ar6000_remove,
56763 +       .name           = "sdio_ar6000",
56764 +       .id_table       = sdio_ar6000_ids,
56765 +};
56766 +
56767 +
56768 +int HIFInit(HTC_CALLBACKS *callbacks)
56769 +{
56770 +       int ret;
56771 +
56772 +       BUG_ON(!callbacks);
56773 +
56774 +       printk(KERN_DEBUG "HIFInit\n");
56775 +       htcCallbacks = *callbacks;
56776 +
56777 +       ret = sdio_register_driver(&sdio_ar6000_driver);
56778 +       if (ret) {
56779 +               printk(KERN_ERR
56780 +                   "sdio_register_driver(sdio_ar6000_driver): %d\n", ret);
56781 +               return A_ERROR;
56782 +       }
56783 +
56784 +       return 0;
56785 +}
56786 +
56787 +
56788 +/*
56789 + * We have three possible call chains here:
56790 + *
56791 + * System shutdown/reboot:
56792 + *
56793 + *   kernel_restart_prepare ...> device_shutdown ... > s3cmci_shutdown ->
56794 + *     mmc_remove_host ..> sdio_bus_remove -> sdio_ar6000_remove ->
56795 + *     deviceRemovedHandler (HTCTargetRemovedHandler) -> HIFShutDownDevice
56796 + *
56797 + *   This is roughly the same sequence as suspend, described below.
56798 + *
56799 + * Module removal:
56800 + *
56801 + *   sys_delete_module -> ar6000_cleanup_module -> HTCShutDown ->
56802 + *     HIFShutDownDevice -> sdio_unregister_driver ...> sdio_bus_remove ->
56803 + *     sdio_ar6000_remove
56804 + *
56805 + *   In this case, HIFShutDownDevice must call sdio_unregister_driver to
56806 + *   notify the driver about its removal. sdio_ar6000_remove must not call
56807 + *   deviceRemovedHandler, because that would loop back into HIFShutDownDevice.
56808 + *
56809 + * Suspend:
56810 + *
56811 + *   device_suspend ...> s3cmci_suspend ...> sdio_bus_remove ->
56812 + *     sdio_ar6000_remove -> deviceRemovedHandler (HTCTargetRemovedHandler) ->
56813 + *     HIFShutDownDevice
56814 + *
56815 + *   We must call deviceRemovedHandler to inform the ar6k stack that the device
56816 + *   has been removed. Since HTCTargetRemovedHandler calls back into
56817 + *   HIFShutDownDevice, we must also prevent the call to
56818 + *   sdio_unregister_driver, or we'd end up recursing into the SDIO stack,
56819 + *   eventually deadlocking somewhere.
56820 + */
56821 +
56822 +void HIFShutDownDevice(HIF_DEVICE *hif)
56823 +{
56824 +       /* Beware, HTCShutDown calls us with hif == NULL ! */
56825 +       if (mutex_trylock(&shutdown_lock)) {
56826 +               sdio_unregister_driver(&sdio_ar6000_driver);
56827 +               mutex_unlock(&shutdown_lock);
56828 +       }
56829 +}
56830 --- /dev/null
56831 +++ b/drivers/ar6000/hif/hif.c
56832 @@ -0,0 +1,824 @@
56833 +/*
56834 + * @file: hif.c
56835 + *
56836 + * @abstract: HIF layer reference implementation for Atheros SDIO stack
56837 + *
56838 + * @notice: Copyright (c) 2004-2006 Atheros Communications Inc.
56839 + *
56840 + *
56841 + *  This program is free software; you can redistribute it and/or modify
56842 + *  it under the terms of the GNU General Public License version 2 as
56843 + *  published by the Free Software Foundation;
56844 + *
56845 + *  Software distributed under the License is distributed on an "AS
56846 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
56847 + *  implied. See the License for the specific language governing
56848 + *  rights and limitations under the License.
56849 + *
56850 + *
56851 + *
56852 + */
56853 +
56854 +#include "hif_internal.h"
56855 +
56856 +/* ------ Static Variables ------ */
56857 +
56858 +/* ------ Global Variable Declarations ------- */
56859 +SD_PNP_INFO Ids[] = {
56860 +    {
56861 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0xB,
56862 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
56863 +        .SDIO_FunctionClass = FUNCTION_CLASS,
56864 +        .SDIO_FunctionNo = 1
56865 +    },
56866 +    {
56867 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0xA,
56868 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
56869 +        .SDIO_FunctionClass = FUNCTION_CLASS,
56870 +        .SDIO_FunctionNo = 1
56871 +    },
56872 +    {
56873 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0x9,
56874 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
56875 +        .SDIO_FunctionClass = FUNCTION_CLASS,
56876 +        .SDIO_FunctionNo = 1
56877 +    },
56878 +    {
56879 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0x8,
56880 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
56881 +        .SDIO_FunctionClass = FUNCTION_CLASS,
56882 +        .SDIO_FunctionNo = 1
56883 +    },
56884 +    {
56885 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6002_BASE | 0x0,
56886 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
56887 +        .SDIO_FunctionClass = FUNCTION_CLASS,
56888 +        .SDIO_FunctionNo = 1
56889 +    },
56890 +    {
56891 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6002_BASE | 0x1,
56892 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
56893 +        .SDIO_FunctionClass = FUNCTION_CLASS,
56894 +        .SDIO_FunctionNo = 1
56895 +    },
56896 +    {
56897 +    }                      //list is null termintaed
56898 +};
56899 +
56900 +TARGET_FUNCTION_CONTEXT FunctionContext = {
56901 +    .function.Version    = CT_SDIO_STACK_VERSION_CODE,
56902 +    .function.pName      = "sdio_wlan",
56903 +    .function.MaxDevices = 1,
56904 +    .function.NumDevices = 0,
56905 +    .function.pIds       = Ids,
56906 +    .function.pProbe     = hifDeviceInserted,
56907 +    .function.pRemove    = hifDeviceRemoved,
56908 +    .function.pSuspend   = NULL,
56909 +    .function.pResume    = NULL,
56910 +    .function.pWake      = NULL,
56911 +    .function.pContext   = &FunctionContext,
56912 +};
56913 +
56914 +HIF_DEVICE hifDevice[HIF_MAX_DEVICES];
56915 +HTC_CALLBACKS htcCallbacks;
56916 +BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM];
56917 +static BUS_REQUEST *s_busRequestFreeQueue = NULL;
56918 +OS_CRITICALSECTION lock;
56919 +extern A_UINT32 onebitmode;
56920 +extern A_UINT32 busspeedlow;
56921 +
56922 +#ifdef DEBUG
56923 +extern A_UINT32 debughif;
56924 +#define ATH_DEBUG_ERROR 1
56925 +#define ATH_DEBUG_WARN  2
56926 +#define ATH_DEBUG_TRACE 3
56927 +#define _AR_DEBUG_PRINTX_ARG(arg...) arg
56928 +#define AR_DEBUG_PRINTF(lvl, args)\
56929 +    {if (lvl <= debughif)\
56930 +        A_PRINTF(KERN_ALERT _AR_DEBUG_PRINTX_ARG args);\
56931 +    }
56932 +#else
56933 +#define AR_DEBUG_PRINTF(lvl, args)
56934 +#endif
56935 +
56936 +static BUS_REQUEST *hifAllocateBusRequest(void);
56937 +static void hifFreeBusRequest(BUS_REQUEST *busrequest);
56938 +static THREAD_RETURN insert_helper_func(POSKERNEL_HELPER pHelper);
56939 +static void ResetAllCards(void);
56940 +
56941 +/* ------ Functions ------ */
56942 +int HIFInit(HTC_CALLBACKS *callbacks)
56943 +{
56944 +    SDIO_STATUS status;
56945 +    DBG_ASSERT(callbacks != NULL);
56946 +
56947 +    /* Store the callback and event handlers */
56948 +    htcCallbacks.deviceInsertedHandler = callbacks->deviceInsertedHandler;
56949 +    htcCallbacks.deviceRemovedHandler = callbacks->deviceRemovedHandler;
56950 +    htcCallbacks.deviceSuspendHandler = callbacks->deviceSuspendHandler;
56951 +    htcCallbacks.deviceResumeHandler = callbacks->deviceResumeHandler;
56952 +    htcCallbacks.deviceWakeupHandler = callbacks->deviceWakeupHandler;
56953 +    htcCallbacks.rwCompletionHandler = callbacks->rwCompletionHandler;
56954 +    htcCallbacks.dsrHandler = callbacks->dsrHandler;
56955 +
56956 +    CriticalSectionInit(&lock);
56957 +
56958 +    /* Register with bus driver core */
56959 +    status = SDIO_RegisterFunction(&FunctionContext.function);
56960 +    DBG_ASSERT(SDIO_SUCCESS(status));
56961 +
56962 +    return(0);
56963 +}
56964 +
56965 +A_STATUS
56966 +HIFReadWrite(HIF_DEVICE *device,
56967 +             A_UINT32 address,
56968 +             A_UCHAR *buffer,
56969 +             A_UINT32 length,
56970 +             A_UINT32 request,
56971 +             void *context)
56972 +{
56973 +    A_UINT8 rw;
56974 +    A_UINT8 mode;
56975 +    A_UINT8 funcNo;
56976 +    A_UINT8 opcode;
56977 +    A_UINT16 count;
56978 +    SDREQUEST *sdrequest;
56979 +    SDIO_STATUS sdiostatus;
56980 +    BUS_REQUEST *busrequest;
56981 +    A_STATUS    status = A_OK;
56982 +
56983 +    DBG_ASSERT(device != NULL);
56984 +    DBG_ASSERT(device->handle != NULL);
56985 +
56986 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
56987 +
56988 +    do {
56989 +        busrequest = hifAllocateBusRequest();
56990 +        if (busrequest == NULL) {
56991 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF Unable to allocate bus request\n"));
56992 +            status = A_NO_RESOURCE;
56993 +            break;
56994 +        }
56995 +
56996 +        sdrequest = busrequest->request;
56997 +        busrequest->context = context;
56998 +
56999 +        sdrequest->pDataBuffer = buffer;
57000 +        if (request & HIF_SYNCHRONOUS) {
57001 +            sdrequest->Flags = SDREQ_FLAGS_RESP_SDIO_R5 | SDREQ_FLAGS_DATA_TRANS;
57002 +            sdrequest->pCompleteContext = NULL;
57003 +            sdrequest->pCompletion = NULL;
57004 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Execution mode: Synchronous\n"));
57005 +        } else if (request & HIF_ASYNCHRONOUS) {
57006 +            sdrequest->Flags = SDREQ_FLAGS_RESP_SDIO_R5 | SDREQ_FLAGS_DATA_TRANS |
57007 +                               SDREQ_FLAGS_TRANS_ASYNC;
57008 +            sdrequest->pCompleteContext = busrequest;
57009 +            sdrequest->pCompletion = hifRWCompletionHandler;
57010 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Execution mode: Asynchronous\n"));
57011 +        } else {
57012 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57013 +                            ("Invalid execution mode: 0x%08x\n", request));
57014 +            status = A_EINVAL;
57015 +            break;
57016 +        }
57017 +
57018 +        if (request & HIF_EXTENDED_IO) {
57019 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Command type: CMD53\n"));
57020 +            sdrequest->Command = CMD53;
57021 +        } else {
57022 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57023 +                            ("Invalid command type: 0x%08x\n", request));
57024 +            status = A_EINVAL;
57025 +            break;
57026 +        }
57027 +
57028 +        if (request & HIF_BLOCK_BASIS) {
57029 +            mode = CMD53_BLOCK_BASIS;
57030 +            sdrequest->BlockLen = HIF_MBOX_BLOCK_SIZE;
57031 +            sdrequest->BlockCount = length / HIF_MBOX_BLOCK_SIZE;
57032 +            count = sdrequest->BlockCount;
57033 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57034 +                            ("Block mode (BlockLen: %d, BlockCount: %d)\n",
57035 +                            sdrequest->BlockLen, sdrequest->BlockCount));
57036 +        } else if (request & HIF_BYTE_BASIS) {
57037 +            mode = CMD53_BYTE_BASIS;
57038 +            sdrequest->BlockLen = length;
57039 +            sdrequest->BlockCount = 1;
57040 +            count = sdrequest->BlockLen;
57041 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57042 +                            ("Byte mode (BlockLen: %d, BlockCount: %d)\n",
57043 +                            sdrequest->BlockLen, sdrequest->BlockCount));
57044 +        } else {
57045 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57046 +                            ("Invalid data mode: 0x%08x\n", request));
57047 +            status = A_EINVAL;
57048 +            break;
57049 +        }
57050 +
57051 +#if 0
57052 +        /* useful for checking register accesses */
57053 +        if (length & 0x3) {
57054 +            A_PRINTF(KERN_ALERT"HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n",
57055 +                                request & HIF_WRITE ? "write":"read", address, length);
57056 +        }
57057 +#endif
57058 +
57059 +        if ((address >= HIF_MBOX_START_ADDR(0)) &&
57060 +            (address <= HIF_MBOX_END_ADDR(3)))
57061 +        {
57062 +
57063 +            DBG_ASSERT(length <= HIF_MBOX_WIDTH);
57064 +
57065 +            /*
57066 +             * Mailbox write. Adjust the address so that the last byte
57067 +             * falls on the EOM address.
57068 +             */
57069 +            address += (HIF_MBOX_WIDTH - length);
57070 +        }
57071 +
57072 +
57073 +
57074 +        if (request & HIF_WRITE) {
57075 +            rw = CMD53_WRITE;
57076 +            sdrequest->Flags |= SDREQ_FLAGS_DATA_WRITE;
57077 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Direction: Write\n"));
57078 +        } else if (request & HIF_READ) {
57079 +            rw = CMD53_READ;
57080 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Direction: Read\n"));
57081 +        } else {
57082 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57083 +                            ("Invalid direction: 0x%08x\n", request));
57084 +            status = A_EINVAL;
57085 +            break;
57086 +        }
57087 +
57088 +        if (request & HIF_FIXED_ADDRESS) {
57089 +            opcode = CMD53_FIXED_ADDRESS;
57090 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Address mode: Fixed\n"));
57091 +        } else if (request & HIF_INCREMENTAL_ADDRESS) {
57092 +            opcode = CMD53_INCR_ADDRESS;
57093 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Address mode: Incremental\n"));
57094 +        } else {
57095 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57096 +                            ("Invalid address mode: 0x%08x\n", request));
57097 +            status = A_EINVAL;
57098 +            break;
57099 +        }
57100 +
57101 +        funcNo = SDDEVICE_GET_SDIO_FUNCNO(device->handle);
57102 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Function number: %d\n", funcNo));
57103 +        SDIO_SET_CMD53_ARG(sdrequest->Argument, rw, funcNo,
57104 +                           mode, opcode, address, count);
57105 +
57106 +        /* Send the command out */
57107 +        sdiostatus = SDDEVICE_CALL_REQUEST_FUNC(device->handle, sdrequest);
57108 +
57109 +        if (!SDIO_SUCCESS(sdiostatus)) {
57110 +            status = A_ERROR;
57111 +        }
57112 +
57113 +    } while (FALSE);
57114 +
57115 +    if (A_FAILED(status) || (request & HIF_SYNCHRONOUS)) {
57116 +        if (busrequest != NULL) {
57117 +            hifFreeBusRequest(busrequest);
57118 +        }
57119 +    }
57120 +
57121 +    if (A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
57122 +            /* call back async handler on failure */
57123 +        htcCallbacks.rwCompletionHandler(context, status);
57124 +    }
57125 +
57126 +    return status;
57127 +}
57128 +
57129 +A_STATUS
57130 +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
57131 +                   void *config, A_UINT32 configLen)
57132 +{
57133 +    A_UINT32 count;
57134 +
57135 +    switch(opcode) {
57136 +        case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
57137 +            ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE;
57138 +            ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE;
57139 +            ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE;
57140 +            ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE;
57141 +            break;
57142 +
57143 +        case HIF_DEVICE_GET_MBOX_ADDR:
57144 +            for (count = 0; count < 4; count ++) {
57145 +                ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count);
57146 +            }
57147 +            break;
57148 +        case HIF_DEVICE_GET_IRQ_PROC_MODE:
57149 +                /* the SDIO stack allows the interrupts to be processed either way, ASYNC or SYNC */
57150 +            *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_ASYNC_SYNC;
57151 +            break;
57152 +        default:
57153 +            AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
57154 +                            ("Unsupported configuration opcode: %d\n", opcode));
57155 +            return A_ERROR;
57156 +    }
57157 +
57158 +    return A_OK;
57159 +}
57160 +
57161 +void
57162 +HIFShutDownDevice(HIF_DEVICE *device)
57163 +{
57164 +    A_UINT8 data;
57165 +    A_UINT32 count;
57166 +    SDIO_STATUS status;
57167 +    SDCONFIG_BUS_MODE_DATA busSettings;
57168 +    SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
57169 +
57170 +    if (device != NULL) {
57171 +        DBG_ASSERT(device->handle != NULL);
57172 +
57173 +        /* Remove the allocated current if any */
57174 +        status = SDLIB_IssueConfig(device->handle,
57175 +                                   SDCONFIG_FUNC_FREE_SLOT_CURRENT, NULL, 0);
57176 +        DBG_ASSERT(SDIO_SUCCESS(status));
57177 +
57178 +        /* Disable the card */
57179 +        fData.EnableFlags = SDCONFIG_DISABLE_FUNC;
57180 +        fData.TimeOut = 1;
57181 +        status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_ENABLE_DISABLE,
57182 +                                   &fData, sizeof(fData));
57183 +        DBG_ASSERT(SDIO_SUCCESS(status));
57184 +
57185 +        /* Perform a soft I/O reset */
57186 +        data = SDIO_IO_RESET;
57187 +        status = SDLIB_IssueCMD52(device->handle, 0, SDIO_IO_ABORT_REG,
57188 +                                  &data, 1, 1);
57189 +        DBG_ASSERT(SDIO_SUCCESS(status));
57190 +
57191 +        /*
57192 +         * WAR - Codetelligence driver does not seem to shutdown correctly in 1
57193 +         * bit mode. By default it configures the HC in the 4 bit. Its later in
57194 +         * our driver that we switch to 1 bit mode. If we try to shutdown, the
57195 +         * driver hangs so we revert to 4 bit mode, to be transparent to the
57196 +         * underlying bus driver.
57197 +         */
57198 +        if (onebitmode) {
57199 +            ZERO_OBJECT(busSettings);
57200 +            busSettings.BusModeFlags = SDDEVICE_GET_BUSMODE_FLAGS(device->handle);
57201 +            SDCONFIG_SET_BUS_WIDTH(busSettings.BusModeFlags,
57202 +                                   SDCONFIG_BUS_WIDTH_4_BIT);
57203 +
57204 +            /* Issue config request to change the bus width to 4 bit */
57205 +            status = SDLIB_IssueConfig(device->handle, SDCONFIG_BUS_MODE_CTRL,
57206 +                                       &busSettings,
57207 +                                       sizeof(SDCONFIG_BUS_MODE_DATA));
57208 +            DBG_ASSERT(SDIO_SUCCESS(status));
57209 +        }
57210 +
57211 +        /* Free the bus requests */
57212 +        for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
57213 +            SDDeviceFreeRequest(device->handle, busRequest[count].request);
57214 +        }
57215 +        /* Clean up the queue */
57216 +        s_busRequestFreeQueue = NULL;
57217 +    } else {
57218 +            /* since we are unloading the driver anyways, reset all cards in case the SDIO card
57219 +             * is externally powered and we are unloading the SDIO stack.  This avoids the problem when
57220 +             * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already
57221 +             * enumerated */
57222 +        ResetAllCards();
57223 +        /* Unregister with bus driver core */
57224 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57225 +                        ("Unregistering with the bus driver\n"));
57226 +        status = SDIO_UnregisterFunction(&FunctionContext.function);
57227 +        DBG_ASSERT(SDIO_SUCCESS(status));
57228 +    }
57229 +}
57230 +
57231 +void
57232 +hifRWCompletionHandler(SDREQUEST *request)
57233 +{
57234 +    A_STATUS status;
57235 +    void *context;
57236 +    BUS_REQUEST *busrequest;
57237 +
57238 +    if (SDIO_SUCCESS(request->Status)) {
57239 +        status = A_OK;
57240 +    } else {
57241 +        status = A_ERROR;
57242 +    }
57243 +
57244 +    DBG_ASSERT(status == A_OK);
57245 +    busrequest = (BUS_REQUEST *) request->pCompleteContext;
57246 +    context = (void *) busrequest->context;
57247 +        /* free the request before calling the callback, in case the
57248 +         * callback submits another request, this guarantees that
57249 +         * there is at least 1 free request available everytime the callback
57250 +         * is invoked */
57251 +    hifFreeBusRequest(busrequest);
57252 +    htcCallbacks.rwCompletionHandler(context, status);
57253 +}
57254 +
57255 +void
57256 +hifIRQHandler(void *context)
57257 +{
57258 +    A_STATUS status;
57259 +    HIF_DEVICE *device;
57260 +
57261 +    device = (HIF_DEVICE *)context;
57262 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
57263 +    status = htcCallbacks.dsrHandler(device->htc_handle);
57264 +    DBG_ASSERT(status == A_OK);
57265 +}
57266 +
57267 +BOOL
57268 +hifDeviceInserted(SDFUNCTION *function, SDDEVICE *handle)
57269 +{
57270 +    BOOL enabled;
57271 +    A_UINT8 data;
57272 +    A_UINT32 count;
57273 +    HIF_DEVICE *device;
57274 +    SDIO_STATUS status;
57275 +    A_UINT16 maxBlocks;
57276 +    A_UINT16 maxBlockSize;
57277 +    SDCONFIG_BUS_MODE_DATA busSettings;
57278 +    SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
57279 +    TARGET_FUNCTION_CONTEXT *functionContext;
57280 +    SDCONFIG_FUNC_SLOT_CURRENT_DATA slotCurrent;
57281 +    SD_BUSCLOCK_RATE                currentBusClock;
57282 +
57283 +    DBG_ASSERT(function != NULL);
57284 +    DBG_ASSERT(handle != NULL);
57285 +
57286 +    device = addHifDevice(handle);
57287 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
57288 +    functionContext =  (TARGET_FUNCTION_CONTEXT *)function->pContext;
57289 +
57290 +    /*
57291 +     * Issue commands to get the manufacturer ID and stuff and compare it
57292 +     * against the rev Id derived from the ID registered during the
57293 +     * initialization process. Report the device only in the case there
57294 +     * is a match. In the case od SDIO, the bus driver has already queried
57295 +     * these details so we just need to use their data structures to get the
57296 +     * relevant values. Infact, the driver has already matched it against
57297 +     * the Ids that we registered with it so we dont need to the step here.
57298 +     */
57299 +
57300 +    /* Configure the SDIO Bus Width */
57301 +    if (onebitmode) {
57302 +        data = SDIO_BUS_WIDTH_1_BIT;
57303 +        status = SDLIB_IssueCMD52(handle, 0, SDIO_BUS_IF_REG, &data, 1, 1);
57304 +        if (!SDIO_SUCCESS(status)) {
57305 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57306 +                            ("Unable to set the bus width to 1 bit\n"));
57307 +            return FALSE;
57308 +        }
57309 +    }
57310 +
57311 +    /* Get current bus flags */
57312 +    ZERO_OBJECT(busSettings);
57313 +
57314 +    busSettings.BusModeFlags = SDDEVICE_GET_BUSMODE_FLAGS(handle);
57315 +    if (onebitmode) {
57316 +        SDCONFIG_SET_BUS_WIDTH(busSettings.BusModeFlags,
57317 +                               SDCONFIG_BUS_WIDTH_1_BIT);
57318 +    }
57319 +
57320 +        /* get the current operating clock, the bus driver sets us up based
57321 +         * on what our CIS reports and what the host controller can handle
57322 +         * we can use this to determine whether we want to drop our clock rate
57323 +         * down */
57324 +    currentBusClock = SDDEVICE_GET_OPER_CLOCK(handle);
57325 +    busSettings.ClockRate = currentBusClock;
57326 +
57327 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57328 +                        ("HIF currently running at: %d \n",currentBusClock));
57329 +
57330 +        /* see if HIF wants to run at a lower clock speed, we may already be
57331 +         * at that lower clock speed */
57332 +    if (currentBusClock > (SDIO_CLOCK_FREQUENCY_DEFAULT >> busspeedlow)) {
57333 +        busSettings.ClockRate = SDIO_CLOCK_FREQUENCY_DEFAULT >> busspeedlow;
57334 +        AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
57335 +                        ("HIF overriding clock to %d \n",busSettings.ClockRate));
57336 +    }
57337 +
57338 +    /* Issue config request to override clock rate */
57339 +    status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_CHANGE_BUS_MODE, &busSettings,
57340 +                               sizeof(SDCONFIG_BUS_MODE_DATA));
57341 +    if (!SDIO_SUCCESS(status)) {
57342 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57343 +                        ("Unable to configure the host clock\n"));
57344 +        return FALSE;
57345 +    } else {
57346 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57347 +                        ("Configured clock: %d, Maximum clock: %d\n",
57348 +                        busSettings.ActualClockRate,
57349 +                        SDDEVICE_GET_MAX_CLOCK(handle)));
57350 +    }
57351 +
57352 +    /*
57353 +     * Check if the target supports block mode. This result of this check
57354 +     * can be used to implement the HIFReadWrite API.
57355 +     */
57356 +    if (SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(handle)) {
57357 +        /* Limit block size to operational block limit or card function
57358 +           capability */
57359 +        maxBlockSize = min(SDDEVICE_GET_OPER_BLOCK_LEN(handle),
57360 +                           SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(handle));
57361 +
57362 +        /* check if the card support multi-block transfers */
57363 +        if (!(SDDEVICE_GET_SDIOCARD_CAPS(handle) & SDIO_CAPS_MULTI_BLOCK)) {
57364 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Byte basis only\n"));
57365 +
57366 +            /* Limit block size to max byte basis */
57367 +            maxBlockSize =  min(maxBlockSize,
57368 +                                (A_UINT16)SDIO_MAX_LENGTH_BYTE_BASIS);
57369 +            maxBlocks = 1;
57370 +        } else {
57371 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Multi-block capable\n"));
57372 +            maxBlocks = SDDEVICE_GET_OPER_BLOCKS(handle);
57373 +            status = SDLIB_SetFunctionBlockSize(handle, HIF_MBOX_BLOCK_SIZE);
57374 +            if (!SDIO_SUCCESS(status)) {
57375 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57376 +                                ("Failed to set block size. Err:%d\n", status));
57377 +                return FALSE;
57378 +            }
57379 +        }
57380 +
57381 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57382 +                        ("Bytes Per Block: %d bytes, Block Count:%d \n",
57383 +                        maxBlockSize, maxBlocks));
57384 +    } else {
57385 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57386 +                        ("Function does not support Block Mode!\n"));
57387 +        return FALSE;
57388 +    }
57389 +
57390 +    /* Allocate the slot current */
57391 +    status = SDLIB_GetDefaultOpCurrent(handle, &slotCurrent.SlotCurrent);
57392 +    if (SDIO_SUCCESS(status)) {
57393 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Allocating Slot current: %d mA\n",
57394 +                                slotCurrent.SlotCurrent));
57395 +        status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_ALLOC_SLOT_CURRENT,
57396 +                                   &slotCurrent, sizeof(slotCurrent));
57397 +        if (!SDIO_SUCCESS(status)) {
57398 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57399 +                            ("Failed to allocate slot current %d\n", status));
57400 +            return FALSE;
57401 +        }
57402 +    }
57403 +
57404 +    /* Enable the dragon function */
57405 +    count = 0;
57406 +    enabled = FALSE;
57407 +    fData.TimeOut = 1;
57408 +    fData.EnableFlags = SDCONFIG_ENABLE_FUNC;
57409 +    while ((count++ < SDWLAN_ENABLE_DISABLE_TIMEOUT) && !enabled)
57410 +    {
57411 +        /* Enable dragon */
57412 +        status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_ENABLE_DISABLE,
57413 +                                   &fData, sizeof(fData));
57414 +        if (!SDIO_SUCCESS(status)) {
57415 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57416 +                            ("Attempting to enable the card again\n"));
57417 +            continue;
57418 +        }
57419 +
57420 +        /* Mark the status as enabled */
57421 +        enabled = TRUE;
57422 +    }
57423 +
57424 +    /* Check if we were succesful in enabling the target */
57425 +    if (!enabled) {
57426 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57427 +                        ("Failed to communicate with the target\n"));
57428 +        return FALSE;
57429 +    }
57430 +
57431 +    /* Allocate the bus requests to be used later */
57432 +    A_MEMZERO(busRequest, sizeof(busRequest));
57433 +    for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
57434 +        if ((busRequest[count].request = SDDeviceAllocRequest(handle)) == NULL){
57435 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("Unable to allocate memory\n"));
57436 +            /* TODO: Free the memory that has already been allocated */
57437 +            return FALSE;
57438 +        }
57439 +        hifFreeBusRequest(&busRequest[count]);
57440 +
57441 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57442 +                ("0x%08x = busRequest[%d].request = 0x%08x\n",
57443 +                               (unsigned int) &busRequest[count], count,
57444 +                               (unsigned int) busRequest[count].request));
57445 +    }
57446 +
57447 +        /* Schedule a worker to handle device inserted, this is a temporary workaround
57448 +         * to fix a deadlock if the device fails to intialize in the insertion handler
57449 +         * The failure causes the instance to shutdown the HIF layer and unregister the
57450 +         * function driver within the busdriver probe context which can deadlock
57451 +         *
57452 +         * NOTE: we cannot use the default work queue because that would block
57453 +         * SD bus request processing for all synchronous I/O. We must use a kernel
57454 +         * thread that is creating using the helper library.
57455 +         * */
57456 +
57457 +    if (SDIO_SUCCESS(SDLIB_OSCreateHelper(&device->insert_helper,
57458 +                         insert_helper_func,
57459 +                         device))) {
57460 +        device->helper_started = TRUE;
57461 +    }
57462 +
57463 +    return TRUE;
57464 +}
57465 +
57466 +static THREAD_RETURN insert_helper_func(POSKERNEL_HELPER pHelper)
57467 +{
57468 +
57469 +    /*
57470 +     * Adding a wait of around a second before we issue the very first
57471 +     * command to dragon. During the process of loading/unloading the
57472 +     * driver repeatedly it was observed that we get a data timeout
57473 +     * while accessing function 1 registers in the chip. The theory at
57474 +     * this point is that some initialization delay in dragon is
57475 +     * causing the SDIO state in dragon core to be not ready even after
57476 +     * the ready bit indicates that function 1 is ready. Accomodating
57477 +     * for this behavior by adding some delay in the driver before it
57478 +     * issues the first command after switching on dragon. Need to
57479 +     * investigate this a bit more - TODO
57480 +     */
57481 +
57482 +    A_MDELAY(1000);
57483 +        /* Inform HTC */
57484 +    if ((htcCallbacks.deviceInsertedHandler(SD_GET_OS_HELPER_CONTEXT(pHelper))) != A_OK) {
57485 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device rejected\n"));
57486 +    }
57487 +
57488 +    return 0;
57489 +}
57490 +
57491 +void
57492 +HIFAckInterrupt(HIF_DEVICE *device)
57493 +{
57494 +    SDIO_STATUS status;
57495 +    DBG_ASSERT(device != NULL);
57496 +    DBG_ASSERT(device->handle != NULL);
57497 +
57498 +    /* Acknowledge our function IRQ */
57499 +    status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_ACK_IRQ,
57500 +                               NULL, 0);
57501 +    DBG_ASSERT(SDIO_SUCCESS(status));
57502 +}
57503 +
57504 +void
57505 +HIFUnMaskInterrupt(HIF_DEVICE *device)
57506 +{
57507 +    SDIO_STATUS status;
57508 +
57509 +    DBG_ASSERT(device != NULL);
57510 +    DBG_ASSERT(device->handle != NULL);
57511 +
57512 +    /* Register the IRQ Handler */
57513 +    SDDEVICE_SET_IRQ_HANDLER(device->handle, hifIRQHandler, device);
57514 +
57515 +    /* Unmask our function IRQ */
57516 +    status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_UNMASK_IRQ,
57517 +                               NULL, 0);
57518 +    DBG_ASSERT(SDIO_SUCCESS(status));
57519 +}
57520 +
57521 +void HIFMaskInterrupt(HIF_DEVICE *device)
57522 +{
57523 +    SDIO_STATUS status;
57524 +    DBG_ASSERT(device != NULL);
57525 +    DBG_ASSERT(device->handle != NULL);
57526 +
57527 +    /* Mask our function IRQ */
57528 +    status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_MASK_IRQ,
57529 +                               NULL, 0);
57530 +    DBG_ASSERT(SDIO_SUCCESS(status));
57531 +
57532 +    /* Unregister the IRQ Handler */
57533 +    SDDEVICE_SET_IRQ_HANDLER(device->handle, NULL, NULL);
57534 +}
57535 +
57536 +static BUS_REQUEST *hifAllocateBusRequest(void)
57537 +{
57538 +    BUS_REQUEST *busrequest;
57539 +
57540 +    /* Acquire lock */
57541 +    CriticalSectionAcquire(&lock);
57542 +
57543 +    /* Remove first in list */
57544 +    if((busrequest = s_busRequestFreeQueue) != NULL)
57545 +    {
57546 +        s_busRequestFreeQueue = busrequest->next;
57547 +    }
57548 +
57549 +    /* Release lock */
57550 +    CriticalSectionRelease(&lock);
57551 +
57552 +    return busrequest;
57553 +}
57554 +
57555 +static void
57556 +hifFreeBusRequest(BUS_REQUEST *busrequest)
57557 +{
57558 +    DBG_ASSERT(busrequest != NULL);
57559 +
57560 +    /* Acquire lock */
57561 +    CriticalSectionAcquire(&lock);
57562 +
57563 +    /* Insert first in list */
57564 +    busrequest->next = s_busRequestFreeQueue;
57565 +    s_busRequestFreeQueue = busrequest;
57566 +
57567 +    /* Release lock */
57568 +    CriticalSectionRelease(&lock);
57569 +}
57570 +
57571 +void
57572 +hifDeviceRemoved(SDFUNCTION *function, SDDEVICE *handle)
57573 +{
57574 +    A_STATUS status;
57575 +    HIF_DEVICE *device;
57576 +    DBG_ASSERT(function != NULL);
57577 +    DBG_ASSERT(handle != NULL);
57578 +
57579 +    device = getHifDevice(handle);
57580 +    status = htcCallbacks.deviceRemovedHandler(device->htc_handle, A_OK);
57581 +
57582 +        /* cleanup the helper thread */
57583 +    if (device->helper_started) {
57584 +        SDLIB_OSDeleteHelper(&device->insert_helper);
57585 +        device->helper_started = FALSE;
57586 +    }
57587 +
57588 +    delHifDevice(handle);
57589 +    DBG_ASSERT(status == A_OK);
57590 +}
57591 +
57592 +HIF_DEVICE *
57593 +addHifDevice(SDDEVICE *handle)
57594 +{
57595 +    DBG_ASSERT(handle != NULL);
57596 +    hifDevice[0].handle = handle;
57597 +    return &hifDevice[0];
57598 +}
57599 +
57600 +HIF_DEVICE *
57601 +getHifDevice(SDDEVICE *handle)
57602 +{
57603 +    DBG_ASSERT(handle != NULL);
57604 +    return &hifDevice[0];
57605 +}
57606 +
57607 +void
57608 +delHifDevice(SDDEVICE *handle)
57609 +{
57610 +    DBG_ASSERT(handle != NULL);
57611 +    hifDevice[0].handle = NULL;
57612 +}
57613 +
57614 +struct device*
57615 +HIFGetOSDevice(HIF_DEVICE *device)
57616 +{
57617 +    return &device->handle->Device->dev;
57618 +}
57619 +
57620 +static void ResetAllCards(void)
57621 +{
57622 +    UINT8       data;
57623 +    SDIO_STATUS status;
57624 +    int         i;
57625 +
57626 +    data = SDIO_IO_RESET;
57627 +
57628 +    /* set the I/O CARD reset bit:
57629 +     * NOTE: we are exploiting a "feature" of the SDIO core that resets the core when you
57630 +     * set the RES bit in the SDIO_IO_ABORT register.  This bit however "normally" resets the
57631 +     * I/O functions leaving the SDIO core in the same state (as per SDIO spec).
57632 +     * In this design, this reset can be used to reset the SDIO core itself */
57633 +    for (i = 0; i < HIF_MAX_DEVICES; i++) {
57634 +        if (hifDevice[i].handle != NULL) {
57635 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57636 +                        ("Issuing I/O Card reset for instance: %d \n",i));
57637 +                /* set the I/O Card reset bit */
57638 +            status = SDLIB_IssueCMD52(hifDevice[i].handle,
57639 +                                      0,                    /* function 0 space */
57640 +                                      SDIO_IO_ABORT_REG,
57641 +                                      &data,
57642 +                                      1,                    /* 1 byte */
57643 +                                      TRUE);                /* write */
57644 +        }
57645 +    }
57646 +
57647 +}
57648 +
57649 +void HIFSetHandle(void *hif_handle, void *handle)
57650 +{
57651 +    HIF_DEVICE *device = (HIF_DEVICE *) hif_handle;
57652 +
57653 +    device->htc_handle = handle;
57654 +
57655 +    return;
57656 +}
57657 --- /dev/null
57658 +++ b/drivers/ar6000/hif/hif_internal.h
57659 @@ -0,0 +1,102 @@
57660 +/*
57661 + * @file: hif_internal.h
57662 + *
57663 + * @abstract: internal header file for hif layer
57664 + *
57665 + * @notice: Copyright (c) 2004-2006 Atheros Communications Inc.
57666 + *
57667 + *
57668 + *  This program is free software; you can redistribute it and/or modify
57669 + *  it under the terms of the GNU General Public License version 2 as
57670 + *  published by the Free Software Foundation;
57671 + *
57672 + *  Software distributed under the License is distributed on an "AS
57673 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
57674 + *  implied. See the License for the specific language governing
57675 + *  rights and limitations under the License.
57676 + *
57677 + *
57678 + *
57679 + */
57680 +
57681 +#include <linux/sdio/ctsystem.h>
57682 +#include <linux/sdio/sdio_busdriver.h>
57683 +#include <linux/sdio/_sdio_defs.h>
57684 +#include <linux/sdio/sdio_lib.h>
57685 +#include "a_config.h"
57686 +#include "athdefs.h"
57687 +#include "a_types.h"
57688 +#include "a_osapi.h"
57689 +#include "hif.h"
57690 +
57691 +#define MANUFACTURER_ID_AR6001_BASE        0x100
57692 +#define MANUFACTURER_ID_AR6002_BASE        0x200
57693 +#define FUNCTION_CLASS                     0x0
57694 +#define MANUFACTURER_CODE                  0x271
57695 +
57696 +#define BUS_REQUEST_MAX_NUM                64
57697 +
57698 +#define SDIO_CLOCK_FREQUENCY_DEFAULT       25000000
57699 +#define SDWLAN_ENABLE_DISABLE_TIMEOUT      20
57700 +#define FLAGS_CARD_ENAB                    0x02
57701 +#define FLAGS_CARD_IRQ_UNMSK               0x04
57702 +
57703 +#define HIF_MBOX_BLOCK_SIZE                128
57704 +#define HIF_MBOX_BASE_ADDR                 0x800
57705 +#define HIF_MBOX_WIDTH                     0x800
57706 +#define HIF_MBOX0_BLOCK_SIZE               1
57707 +#define HIF_MBOX1_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
57708 +#define HIF_MBOX2_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
57709 +#define HIF_MBOX3_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
57710 +
57711 +#define HIF_MBOX_START_ADDR(mbox)                        \
57712 +    HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH
57713 +
57714 +#define HIF_MBOX_END_ADDR(mbox)                                 \
57715 +    HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1
57716 +
57717 +struct hif_device {
57718 +    SDDEVICE *handle;
57719 +    void *htc_handle;
57720 +    OSKERNEL_HELPER insert_helper;
57721 +    BOOL  helper_started;
57722 +};
57723 +
57724 +typedef struct target_function_context {
57725 +    SDFUNCTION           function; /* function description of the bus driver */
57726 +    OS_SEMAPHORE         instanceSem; /* instance lock. Unused */
57727 +    SDLIST               instanceList; /* list of instances. Unused */
57728 +} TARGET_FUNCTION_CONTEXT;
57729 +
57730 +typedef struct bus_request {
57731 +    struct bus_request *next;
57732 +    SDREQUEST *request;
57733 +    void *context;
57734 +} BUS_REQUEST;
57735 +
57736 +BOOL
57737 +hifDeviceInserted(SDFUNCTION *function, SDDEVICE *device);
57738 +
57739 +void
57740 +hifDeviceRemoved(SDFUNCTION *function, SDDEVICE *device);
57741 +
57742 +SDREQUEST *
57743 +hifAllocateDeviceRequest(SDDEVICE *device);
57744 +
57745 +void
57746 +hifFreeDeviceRequest(SDREQUEST *request);
57747 +
57748 +void
57749 +hifRWCompletionHandler(SDREQUEST *request);
57750 +
57751 +void
57752 +hifIRQHandler(void *context);
57753 +
57754 +HIF_DEVICE *
57755 +addHifDevice(SDDEVICE *handle);
57756 +
57757 +HIF_DEVICE *
57758 +getHifDevice(SDDEVICE *handle);
57759 +
57760 +void
57761 +delHifDevice(SDDEVICE *handle);
57762 --- /dev/null
57763 +++ b/drivers/ar6000/htc/ar6k.c
57764 @@ -0,0 +1,991 @@
57765 +/*
57766 + * AR6K device layer that handles register level I/O
57767 + *
57768 + * Copyright (c) 2007 Atheros Communications Inc.
57769 + * All rights reserved.
57770 + *
57771 + *
57772 + *  This program is free software; you can redistribute it and/or modify
57773 + *  it under the terms of the GNU General Public License version 2 as
57774 + *  published by the Free Software Foundation;
57775 + *
57776 + *  Software distributed under the License is distributed on an "AS
57777 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
57778 + *  implied. See the License for the specific language governing
57779 + *  rights and limitations under the License.
57780 + *
57781 + *
57782 + *
57783 + */
57784 +#include "a_config.h"
57785 +#include "athdefs.h"
57786 +#include "a_types.h"
57787 +#include "AR6Khwreg.h"
57788 +#include "a_osapi.h"
57789 +#include "a_debug.h"
57790 +#include "hif.h"
57791 +#include "htc_packet.h"
57792 +#include "ar6k.h"
57793 +
57794 +#define MAILBOX_FOR_BLOCK_SIZE 1
57795 +
57796 +extern A_UINT32 resetok;
57797 +
57798 +static A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
57799 +static A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
57800 +
57801 +#define LOCK_AR6K(p)      A_MUTEX_LOCK(&(p)->Lock);
57802 +#define UNLOCK_AR6K(p)    A_MUTEX_UNLOCK(&(p)->Lock);
57803 +
57804 +void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket)
57805 +{
57806 +    LOCK_AR6K(pDev);
57807 +    HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket);
57808 +    UNLOCK_AR6K(pDev);
57809 +}
57810 +
57811 +HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev)
57812 +{
57813 +    HTC_PACKET *pPacket;
57814 +
57815 +    LOCK_AR6K(pDev);
57816 +    pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList);
57817 +    UNLOCK_AR6K(pDev);
57818 +
57819 +    return pPacket;
57820 +}
57821 +
57822 +A_STATUS DevSetup(AR6K_DEVICE *pDev)
57823 +{
57824 +    A_UINT32 mailboxaddrs[AR6K_MAILBOXES];
57825 +    A_UINT32 blocksizes[AR6K_MAILBOXES];
57826 +    A_STATUS status = A_OK;
57827 +    int      i;
57828 +
57829 +    AR_DEBUG_ASSERT(AR6K_IRQ_PROC_REGS_SIZE == 16);
57830 +    AR_DEBUG_ASSERT(AR6K_IRQ_ENABLE_REGS_SIZE == 4);
57831 +
57832 +    do {
57833 +            /* give a handle to HIF for this target */
57834 +        HIFSetHandle(pDev->HIFDevice, (void *)pDev);
57835 +            /* initialize our free list of IO packets */
57836 +        INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList);
57837 +        A_MUTEX_INIT(&pDev->Lock);
57838 +
57839 +            /* get the addresses for all 4 mailboxes */
57840 +        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
57841 +                                    mailboxaddrs, sizeof(mailboxaddrs));
57842 +
57843 +        if (status != A_OK) {
57844 +            AR_DEBUG_ASSERT(FALSE);
57845 +            break;
57846 +        }
57847 +
57848 +            /* carve up register I/O packets (these are for ASYNC register I/O ) */
57849 +        for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) {
57850 +            HTC_PACKET *pIOPacket;
57851 +            pIOPacket = &pDev->RegIOBuffers[i].HtcPacket;
57852 +            SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket,
57853 +                                          pDev,
57854 +                                          pDev->RegIOBuffers[i].Buffer,
57855 +                                          AR6K_REG_IO_BUFFER_SIZE,
57856 +                                          0); /* don't care */
57857 +            AR6KFreeIOPacket(pDev,pIOPacket);
57858 +        }
57859 +
57860 +            /* get the address of the mailbox we are using */
57861 +        pDev->MailboxAddress = mailboxaddrs[HTC_MAILBOX];
57862 +
57863 +            /* get the block sizes */
57864 +        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
57865 +                                    blocksizes, sizeof(blocksizes));
57866 +
57867 +        if (status != A_OK) {
57868 +            AR_DEBUG_ASSERT(FALSE);
57869 +            break;
57870 +        }
57871 +
57872 +            /* note: we actually get the block size of a mailbox other than 0, for SDIO the block
57873 +             * size on mailbox 0 is artificially set to 1.  So we use the block size that is set
57874 +             * for the other 3 mailboxes */
57875 +        pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE];
57876 +            /* must be a power of 2 */
57877 +        AR_DEBUG_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0);
57878 +
57879 +            /* assemble mask, used for padding to a block */
57880 +        pDev->BlockMask = pDev->BlockSize - 1;
57881 +
57882 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n",
57883 +                    pDev->BlockSize, pDev->MailboxAddress));
57884 +
57885 +        pDev->GetPendingEventsFunc = NULL;
57886 +            /* see if the HIF layer implements the get pending events function  */
57887 +        HIFConfigureDevice(pDev->HIFDevice,
57888 +                           HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
57889 +                           &pDev->GetPendingEventsFunc,
57890 +                           sizeof(pDev->GetPendingEventsFunc));
57891 +
57892 +            /* assume we can process HIF interrupt events asynchronously */
57893 +        pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC;
57894 +
57895 +            /* see if the HIF layer overrides this assumption */
57896 +        HIFConfigureDevice(pDev->HIFDevice,
57897 +                           HIF_DEVICE_GET_IRQ_PROC_MODE,
57898 +                           &pDev->HifIRQProcessingMode,
57899 +                           sizeof(pDev->HifIRQProcessingMode));
57900 +
57901 +        switch (pDev->HifIRQProcessingMode) {
57902 +            case HIF_DEVICE_IRQ_SYNC_ONLY:
57903 +                AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is SYNC ONLY\n"));
57904 +                break;
57905 +            case HIF_DEVICE_IRQ_ASYNC_SYNC:
57906 +                AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n"));
57907 +                break;
57908 +            default:
57909 +                AR_DEBUG_ASSERT(FALSE);
57910 +        }
57911 +
57912 +        pDev->HifMaskUmaskRecvEvent = NULL;
57913 +
57914 +            /* see if the HIF layer implements the mask/unmask recv events function  */
57915 +        HIFConfigureDevice(pDev->HIFDevice,
57916 +                           HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
57917 +                           &pDev->HifMaskUmaskRecvEvent,
57918 +                           sizeof(pDev->HifMaskUmaskRecvEvent));
57919 +
57920 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%X , 0x%X\n",
57921 +                 (A_UINT32)pDev->GetPendingEventsFunc, (A_UINT32)pDev->HifMaskUmaskRecvEvent));
57922 +
57923 +        status = DevDisableInterrupts(pDev);
57924 +
57925 +    } while (FALSE);
57926 +
57927 +    if (A_FAILED(status)) {
57928 +            /* make sure handle is cleared */
57929 +        HIFSetHandle(pDev->HIFDevice, NULL);
57930 +    }
57931 +
57932 +    return status;
57933 +
57934 +}
57935 +
57936 +static A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev)
57937 +{
57938 +    A_STATUS                  status;
57939 +    AR6K_IRQ_ENABLE_REGISTERS regs;
57940 +
57941 +    LOCK_AR6K(pDev);
57942 +
57943 +        /* Enable all the interrupts except for the dragon interrupt */
57944 +    pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) |
57945 +                                      INT_STATUS_ENABLE_CPU_SET(0x01) |
57946 +                                      INT_STATUS_ENABLE_COUNTER_SET(0x01);
57947 +
57948 +    if (NULL == pDev->GetPendingEventsFunc) {
57949 +        pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
57950 +    } else {
57951 +        /* The HIF layer provided us with a pending events function which means that
57952 +         * the detection of pending mbox messages is handled in the HIF layer.
57953 +         * This is the case for the SPI2 interface.
57954 +         * In the normal case we enable MBOX interrupts, for the case
57955 +         * with HIFs that offer this mechanism, we keep these interrupts
57956 +         * masked */
57957 +        pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
57958 +    }
57959 +
57960 +
57961 +    /* Set up the CPU Interrupt Status Register */
57962 +    pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00);
57963 +
57964 +    /* Set up the Error Interrupt Status Register */
57965 +    pDev->IrqEnableRegisters.error_status_enable =
57966 +                                  ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) |
57967 +                                  ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01);
57968 +
57969 +    /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */
57970 +    pDev->IrqEnableRegisters.counter_int_status_enable =
57971 +        COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK);
57972 +
57973 +        /* copy into our temp area */
57974 +    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
57975 +
57976 +    UNLOCK_AR6K(pDev);
57977 +
57978 +        /* always synchronous */
57979 +    status = HIFReadWrite(pDev->HIFDevice,
57980 +                          INT_STATUS_ENABLE_ADDRESS,
57981 +                          &regs.int_status_enable,
57982 +                          AR6K_IRQ_ENABLE_REGS_SIZE,
57983 +                          HIF_WR_SYNC_BYTE_INC,
57984 +                          NULL);
57985 +
57986 +    if (status != A_OK) {
57987 +        /* Can't write it for some reason */
57988 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
57989 +                        ("Failed to update interrupt control registers err: %d\n", status));
57990 +
57991 +    }
57992 +
57993 +    return status;
57994 +}
57995 +
57996 +static A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev)
57997 +{
57998 +    AR6K_IRQ_ENABLE_REGISTERS regs;
57999 +
58000 +    LOCK_AR6K(pDev);
58001 +        /* Disable all interrupts */
58002 +    pDev->IrqEnableRegisters.int_status_enable = 0;
58003 +    pDev->IrqEnableRegisters.cpu_int_status_enable = 0;
58004 +    pDev->IrqEnableRegisters.error_status_enable = 0;
58005 +    pDev->IrqEnableRegisters.counter_int_status_enable = 0;
58006 +        /* copy into our temp area */
58007 +    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
58008 +
58009 +    UNLOCK_AR6K(pDev);
58010 +
58011 +        /* always synchronous */
58012 +    return HIFReadWrite(pDev->HIFDevice,
58013 +                        INT_STATUS_ENABLE_ADDRESS,
58014 +                        &regs.int_status_enable,
58015 +                        AR6K_IRQ_ENABLE_REGS_SIZE,
58016 +                        HIF_WR_SYNC_BYTE_INC,
58017 +                        NULL);
58018 +}
58019 +
58020 +/* enable device interrupts */
58021 +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev)
58022 +{
58023 +        /* Unmask the host controller interrupts */
58024 +    HIFUnMaskInterrupt(pDev->HIFDevice);
58025 +
58026 +    return DevEnableInterrupts(pDev);
58027 +}
58028 +
58029 +/* disable all device interrupts */
58030 +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev)
58031 +{
58032 +    A_STATUS status;
58033 +
58034 +    status = DevDisableInterrupts(pDev);
58035 +
58036 +    if (A_SUCCESS(status)) {
58037 +            /* Disable the interrupt at the HIF layer */
58038 +        HIFMaskInterrupt(pDev->HIFDevice);
58039 +    }
58040 +
58041 +    return status;
58042 +}
58043 +
58044 +/* callback when our fetch to enable/disable completes */
58045 +static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket)
58046 +{
58047 +    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
58048 +
58049 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
58050 +
58051 +    if (A_FAILED(pPacket->Status)) {
58052 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
58053 +                (" Failed to disable receiver, status:%d \n", pPacket->Status));
58054 +    }
58055 +        /* free this IO packet */
58056 +    AR6KFreeIOPacket(pDev,pPacket);
58057 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n"));
58058 +}
58059 +
58060 +/* disable packet reception (used in case the host runs out of buffers)
58061 + * this is the "override" method when the HIF reports another methods to
58062 + * disable recv events */
58063 +static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
58064 +{
58065 +    A_STATUS                  status = A_OK;
58066 +    HTC_PACKET                *pIOPacket = NULL;
58067 +
58068 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n",
58069 +            EnableRecv,AsyncMode));
58070 +
58071 +    do {
58072 +
58073 +        if (AsyncMode) {
58074 +
58075 +            pIOPacket = AR6KAllocIOPacket(pDev);
58076 +
58077 +            if (NULL == pIOPacket) {
58078 +                status = A_NO_MEMORY;
58079 +                AR_DEBUG_ASSERT(FALSE);
58080 +                break;
58081 +            }
58082 +
58083 +                /* stick in our completion routine when the I/O operation completes */
58084 +            pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
58085 +            pIOPacket->pContext = pDev;
58086 +
58087 +                /* call the HIF layer override and do this asynchronously */
58088 +            status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
58089 +                                                 EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
58090 +                                                 pIOPacket);
58091 +            break;
58092 +        }
58093 +
58094 +            /* if we get here we are doing it synchronously */
58095 +        status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
58096 +                                             EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
58097 +                                             NULL);
58098 +
58099 +    } while (FALSE);
58100 +
58101 +    if (A_FAILED(status) && (pIOPacket != NULL)) {
58102 +        AR6KFreeIOPacket(pDev,pIOPacket);
58103 +    }
58104 +
58105 +    return status;
58106 +}
58107 +
58108 +/* disable packet reception (used in case the host runs out of buffers)
58109 + * this is the "normal" method using the interrupt enable registers through
58110 + * the host I/F */
58111 +static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
58112 +{
58113 +    A_STATUS                  status = A_OK;
58114 +    HTC_PACKET                *pIOPacket = NULL;
58115 +    AR6K_IRQ_ENABLE_REGISTERS regs;
58116 +
58117 +        /* take the lock to protect interrupt enable shadows */
58118 +    LOCK_AR6K(pDev);
58119 +
58120 +    if (EnableRecv) {
58121 +        pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
58122 +    } else {
58123 +        pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
58124 +    }
58125 +
58126 +        /* copy into our temp area */
58127 +    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
58128 +    UNLOCK_AR6K(pDev);
58129 +
58130 +    do {
58131 +
58132 +        if (AsyncMode) {
58133 +
58134 +            pIOPacket = AR6KAllocIOPacket(pDev);
58135 +
58136 +            if (NULL == pIOPacket) {
58137 +                status = A_NO_MEMORY;
58138 +                AR_DEBUG_ASSERT(FALSE);
58139 +                break;
58140 +            }
58141 +
58142 +                /* copy values to write to our async I/O buffer */
58143 +            A_MEMCPY(pIOPacket->pBuffer,&regs,AR6K_IRQ_ENABLE_REGS_SIZE);
58144 +
58145 +                /* stick in our completion routine when the I/O operation completes */
58146 +            pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
58147 +            pIOPacket->pContext = pDev;
58148 +
58149 +                /* write it out asynchronously */
58150 +            HIFReadWrite(pDev->HIFDevice,
58151 +                         INT_STATUS_ENABLE_ADDRESS,
58152 +                         pIOPacket->pBuffer,
58153 +                         AR6K_IRQ_ENABLE_REGS_SIZE,
58154 +                         HIF_WR_ASYNC_BYTE_INC,
58155 +                         pIOPacket);
58156 +            break;
58157 +        }
58158 +
58159 +        /* if we get here we are doing it synchronously */
58160 +
58161 +        status = HIFReadWrite(pDev->HIFDevice,
58162 +                              INT_STATUS_ENABLE_ADDRESS,
58163 +                              &regs.int_status_enable,
58164 +                              AR6K_IRQ_ENABLE_REGS_SIZE,
58165 +                              HIF_WR_SYNC_BYTE_INC,
58166 +                              NULL);
58167 +
58168 +    } while (FALSE);
58169 +
58170 +    if (A_FAILED(status) && (pIOPacket != NULL)) {
58171 +        AR6KFreeIOPacket(pDev,pIOPacket);
58172 +    }
58173 +
58174 +    return status;
58175 +}
58176 +
58177 +
58178 +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
58179 +{
58180 +    if (NULL == pDev->HifMaskUmaskRecvEvent) {
58181 +        return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode);
58182 +    } else {
58183 +        return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode);
58184 +    }
58185 +}
58186 +
58187 +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
58188 +{
58189 +    if (NULL == pDev->HifMaskUmaskRecvEvent) {
58190 +        return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode);
58191 +    } else {
58192 +        return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode);
58193 +    }
58194 +}
58195 +
58196 +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS   *pIrqProcRegs,
58197 +                      AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs)
58198 +{
58199 +
58200 +    AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("\n<------- Register Table -------->\n"));
58201 +
58202 +    if (pIrqProcRegs != NULL) {
58203 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58204 +            ("Int Status:               0x%x\n",pIrqProcRegs->host_int_status));
58205 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58206 +            ("CPU Int Status:            0x%x\n",pIrqProcRegs->cpu_int_status));
58207 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58208 +            ("Error Int Status:          0x%x\n",pIrqProcRegs->error_int_status));
58209 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58210 +            ("Counter Int Status:        0x%x\n",pIrqProcRegs->counter_int_status));
58211 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58212 +            ("Mbox Frame:                0x%x\n",pIrqProcRegs->mbox_frame));
58213 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58214 +            ("Rx Lookahead Valid:        0x%x\n",pIrqProcRegs->rx_lookahead_valid));
58215 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58216 +            ("Rx Lookahead 0:            0x%x\n",pIrqProcRegs->rx_lookahead[0]));
58217 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58218 +            ("Rx Lookahead 1:            0x%x\n",pIrqProcRegs->rx_lookahead[1]));
58219 +    }
58220 +
58221 +    if (pIrqEnableRegs != NULL) {
58222 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58223 +            ("Int Status Enable:         0x%x\n",pIrqEnableRegs->int_status_enable));
58224 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58225 +            ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable));
58226 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("<------------------------------->\n"));
58227 +    }
58228 +}
58229 +
58230 +
58231 +#ifdef MBOXHW_UNIT_TEST
58232 +
58233 +
58234 +/* This is a mailbox hardware unit test that must be called in a schedulable context
58235 + * This test is very simple, it will send a list of buffers with a counting pattern
58236 + * and the target will invert the data and send the message back
58237 + *
58238 + * the unit test has the following constraints:
58239 + *
58240 + * The target has at least 8 buffers of 256 bytes each. The host will send
58241 + * the following pattern of buffers in rapid succession :
58242 + *
58243 + * 1 buffer - 128 bytes
58244 + * 1 buffer - 256 bytes
58245 + * 1 buffer - 512 bytes
58246 + * 1 buffer - 1024 bytes
58247 + *
58248 + * The host will send the buffers to one mailbox and wait for buffers to be reflected
58249 + * back from the same mailbox. The target sends the buffers FIFO order.
58250 + * Once the final buffer has been received for a mailbox, the next mailbox is tested.
58251 + *
58252 + *
58253 + * Note:  To simplifythe test , we assume that the chosen buffer sizes
58254 + *        will fall on a nice block pad
58255 + *
58256 + * It is expected that higher-order tests will be written to stress the mailboxes using
58257 + * a message-based protocol (with some performance timming) that can create more
58258 + * randomness in the packets sent over mailboxes.
58259 + *
58260 + * */
58261 +
58262 +#define A_ROUND_UP_PWR2(x, align)    (((int) (x) + ((align)-1)) & ~((align)-1))
58263 +
58264 +#define BUFFER_BLOCK_PAD 128
58265 +
58266 +#if 0
58267 +#define BUFFER1 128
58268 +#define BUFFER2 256
58269 +#define BUFFER3 512
58270 +#define BUFFER4 1024
58271 +#endif
58272 +
58273 +#if 1
58274 +#define BUFFER1 80
58275 +#define BUFFER2 200
58276 +#define BUFFER3 444
58277 +#define BUFFER4 800
58278 +#endif
58279 +
58280 +#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \
58281 +                     A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \
58282 +                     A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \
58283 +                     A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) )
58284 +
58285 +#define TEST_BYTES (BUFFER1 +  BUFFER2 + BUFFER3 + BUFFER4)
58286 +
58287 +#define TEST_CREDITS_RECV_TIMEOUT 100
58288 +
58289 +static A_UINT8  g_Buffer[TOTAL_BYTES];
58290 +static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES];
58291 +static A_UINT32 g_BlockSizes[AR6K_MAILBOXES];
58292 +
58293 +#define BUFFER_PROC_LIST_DEPTH 4
58294 +
58295 +typedef struct _BUFFER_PROC_LIST{
58296 +    A_UINT8  *pBuffer;
58297 +    A_UINT32 length;
58298 +}BUFFER_PROC_LIST;
58299 +
58300 +
58301 +#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \
58302 +{                                                   \
58303 +    (pList)->pBuffer = (pCurrpos);                  \
58304 +    (pList)->length = (len);                        \
58305 +    (pCurrpos) += (len);                            \
58306 +    (pList)++;                                      \
58307 +}
58308 +
58309 +/* a simple and crude way to send different "message" sizes */
58310 +static void AssembleBufferList(BUFFER_PROC_LIST *pList)
58311 +{
58312 +    A_UINT8 *pBuffer = g_Buffer;
58313 +
58314 +#if BUFFER_PROC_LIST_DEPTH < 4
58315 +#error "Buffer processing list depth is not deep enough!!"
58316 +#endif
58317 +
58318 +    PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer);
58319 +    PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer);
58320 +    PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer);
58321 +    PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer);
58322 +
58323 +}
58324 +
58325 +#define FILL_ZERO     TRUE
58326 +#define FILL_COUNTING FALSE
58327 +static void InitBuffers(A_BOOL Zero)
58328 +{
58329 +    A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer;
58330 +    int      i;
58331 +
58332 +        /* fill buffer with 16 bit counting pattern or zeros */
58333 +    for (i = 0; i <  (TOTAL_BYTES / 2) ; i++) {
58334 +        if (!Zero) {
58335 +            pBuffer16[i] = (A_UINT16)i;
58336 +        } else {
58337 +            pBuffer16[i] = 0;
58338 +        }
58339 +    }
58340 +}
58341 +
58342 +
58343 +static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length)
58344 +{
58345 +    int      i;
58346 +    A_UINT16 startCount;
58347 +    A_BOOL   success = TRUE;
58348 +
58349 +        /* get the starting count */
58350 +    startCount = pBuffer16[0];
58351 +        /* invert it, this is the expected value */
58352 +    startCount = ~startCount;
58353 +        /* scan the buffer and verify */
58354 +    for (i = 0; i < (Length / 2) ; i++,startCount++) {
58355 +            /* target will invert all the data */
58356 +        if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) {
58357 +            success = FALSE;
58358 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n",
58359 +                        pBuffer16[i], ((A_UINT16)~startCount), i, Length));
58360 +             AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n",
58361 +                        pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3]));
58362 +            break;
58363 +        }
58364 +    }
58365 +
58366 +    return success;
58367 +}
58368 +
58369 +static A_BOOL CheckBuffers(void)
58370 +{
58371 +    int      i;
58372 +    A_BOOL   success = TRUE;
58373 +    BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
58374 +
58375 +        /* assemble the list */
58376 +    AssembleBufferList(checkList);
58377 +
58378 +        /* scan the buffers and verify */
58379 +    for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) {
58380 +        success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length);
58381 +        if (!success) {
58382 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n",
58383 +                        (A_UINT32)checkList[i].pBuffer, checkList[i].length));
58384 +            break;
58385 +        }
58386 +    }
58387 +
58388 +    return success;
58389 +}
58390 +
58391 +    /* find the end marker for the last buffer we will be sending */
58392 +static A_UINT16 GetEndMarker(void)
58393 +{
58394 +    A_UINT8  *pBuffer;
58395 +    BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
58396 +
58397 +        /* fill up buffers with the normal counting pattern */
58398 +    InitBuffers(FILL_COUNTING);
58399 +
58400 +        /* assemble the list we will be sending down */
58401 +    AssembleBufferList(checkList);
58402 +        /* point to the last 2 bytes of the last buffer */
58403 +    pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]);
58404 +
58405 +        /* the last count in the last buffer is the marker */
58406 +    return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8);
58407 +}
58408 +
58409 +#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR
58410 +
58411 +/* send the ordered buffers to the target */
58412 +static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox)
58413 +{
58414 +    A_STATUS         status = A_OK;
58415 +    A_UINT32         request = HIF_WR_SYNC_BLOCK_INC;
58416 +    BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH];
58417 +    int              i;
58418 +    int              totalBytes = 0;
58419 +    int              paddedLength;
58420 +    int              totalwPadding = 0;
58421 +
58422 +    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox));
58423 +
58424 +        /* fill buffer with counting pattern */
58425 +    InitBuffers(FILL_COUNTING);
58426 +
58427 +        /* assemble the order in which we send */
58428 +    AssembleBufferList(sendList);
58429 +
58430 +    for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) {
58431 +
58432 +            /* we are doing block transfers, so we need to pad everything to a block size */
58433 +        paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) &
58434 +                       (~(g_BlockSizes[mbox] - 1));
58435 +
58436 +            /* send each buffer synchronously */
58437 +        status = HIFReadWrite(pDev->HIFDevice,
58438 +                              g_MailboxAddrs[mbox],
58439 +                              sendList[i].pBuffer,
58440 +                              paddedLength,
58441 +                              request,
58442 +                              NULL);
58443 +        if (status != A_OK) {
58444 +            break;
58445 +        }
58446 +        totalBytes += sendList[i].length;
58447 +        totalwPadding += paddedLength;
58448 +    }
58449 +
58450 +    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox));
58451 +
58452 +    return status;
58453 +}
58454 +
58455 +/* poll the mailbox credit counter until we get a credit or timeout */
58456 +static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits)
58457 +{
58458 +    A_STATUS status = A_OK;
58459 +    int      timeout = TEST_CREDITS_RECV_TIMEOUT;
58460 +    A_UINT8  credits = 0;
58461 +    A_UINT32 address;
58462 +
58463 +    while (TRUE) {
58464 +
58465 +            /* Read the counter register to get credits, this auto-decrements  */
58466 +        address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4;
58467 +        status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits),
58468 +                              HIF_RD_SYNC_BYTE_FIX, NULL);
58469 +        if (status != A_OK) {
58470 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
58471 +                ("Unable to decrement the command credit count register (mbox=%d)\n",mbox));
58472 +            status = A_ERROR;
58473 +            break;
58474 +        }
58475 +
58476 +        if (credits) {
58477 +            break;
58478 +        }
58479 +
58480 +        timeout--;
58481 +
58482 +        if (timeout <= 0) {
58483 +              AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
58484 +                (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address));
58485 +            status = A_ERROR;
58486 +            break;
58487 +        }
58488 +
58489 +         /* delay a little, target may not be ready */
58490 +         A_MDELAY(1000);
58491 +
58492 +    }
58493 +
58494 +    if (status == A_OK) {
58495 +        *pCredits = credits;
58496 +    }
58497 +
58498 +    return status;
58499 +}
58500 +
58501 +
58502 +/* wait for the buffers to come back */
58503 +static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox)
58504 +{
58505 +    A_STATUS         status = A_OK;
58506 +    A_UINT32         request = HIF_RD_SYNC_BLOCK_INC;
58507 +    BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH];
58508 +    int              curBuffer;
58509 +    int              credits;
58510 +    int              i;
58511 +    int              totalBytes = 0;
58512 +    int              paddedLength;
58513 +    int              totalwPadding = 0;
58514 +
58515 +    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox));
58516 +
58517 +        /* zero the buffers */
58518 +    InitBuffers(FILL_ZERO);
58519 +
58520 +        /* assemble the order in which we should receive */
58521 +    AssembleBufferList(recvList);
58522 +
58523 +    curBuffer = 0;
58524 +
58525 +    while (curBuffer < BUFFER_PROC_LIST_DEPTH) {
58526 +
58527 +            /* get number of buffers that have been completed, this blocks
58528 +             * until we get at least 1 credit or it times out */
58529 +        status = GetCredits(pDev, mbox, &credits);
58530 +
58531 +        if (status != A_OK) {
58532 +            break;
58533 +        }
58534 +
58535 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox));
58536 +
58537 +            /* get all the buffers that are sitting on the queue */
58538 +        for (i = 0; i < credits; i++) {
58539 +            AR_DEBUG_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH);
58540 +                /* recv the current buffer synchronously, the buffers should come back in
58541 +                 * order... with padding applied by the target */
58542 +            paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) &
58543 +                       (~(g_BlockSizes[mbox] - 1));
58544 +
58545 +            status = HIFReadWrite(pDev->HIFDevice,
58546 +                                  g_MailboxAddrs[mbox],
58547 +                                  recvList[curBuffer].pBuffer,
58548 +                                  paddedLength,
58549 +                                  request,
58550 +                                  NULL);
58551 +            if (status != A_OK) {
58552 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n",
58553 +                        recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox]));
58554 +                break;
58555 +            }
58556 +
58557 +            totalwPadding += paddedLength;
58558 +            totalBytes += recvList[curBuffer].length;
58559 +            curBuffer++;
58560 +        }
58561 +
58562 +        if (status != A_OK) {
58563 +            break;
58564 +        }
58565 +            /* go back and get some more */
58566 +        credits = 0;
58567 +    }
58568 +
58569 +    if (totalBytes != TEST_BYTES) {
58570 +        AR_DEBUG_ASSERT(FALSE);
58571 +    }  else {
58572 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n",
58573 +            mbox, totalBytes, totalwPadding));
58574 +    }
58575 +
58576 +    return status;
58577 +
58578 +
58579 +}
58580 +
58581 +static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox)
58582 +{
58583 +    A_STATUS status;
58584 +
58585 +    do {
58586 +            /* send out buffers */
58587 +        status = SendBuffers(pDev,mbox);
58588 +
58589 +        if (status != A_OK) {
58590 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox));
58591 +            break;
58592 +        }
58593 +
58594 +            /* go get them, this will block */
58595 +        status =  RecvBuffers(pDev, mbox);
58596 +
58597 +        if (status != A_OK) {
58598 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox));
58599 +            break;
58600 +        }
58601 +
58602 +            /* check the returned data patterns */
58603 +        if (!CheckBuffers()) {
58604 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox));
58605 +            status = A_ERROR;
58606 +            break;
58607 +        }
58608 +
58609 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox));
58610 +
58611 +    }  while (FALSE);
58612 +
58613 +    return status;
58614 +}
58615 +
58616 +/* here is where the test starts */
58617 +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev)
58618 +{
58619 +    int      i;
58620 +    A_STATUS status;
58621 +    int      credits = 0;
58622 +    A_UINT8  params[4];
58623 +    int      numBufs;
58624 +    int      bufferSize;
58625 +    A_UINT16 temp;
58626 +
58627 +
58628 +    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START -  \n"));
58629 +
58630 +    do {
58631 +            /* get the addresses for all 4 mailboxes */
58632 +        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
58633 +                                    g_MailboxAddrs, sizeof(g_MailboxAddrs));
58634 +
58635 +        if (status != A_OK) {
58636 +            AR_DEBUG_ASSERT(FALSE);
58637 +            break;
58638 +        }
58639 +
58640 +            /* get the block sizes */
58641 +        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
58642 +                                    g_BlockSizes, sizeof(g_BlockSizes));
58643 +
58644 +        if (status != A_OK) {
58645 +            AR_DEBUG_ASSERT(FALSE);
58646 +            break;
58647 +        }
58648 +
58649 +            /* note, the HIF layer usually reports mbox 0 to have a block size of
58650 +             * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes
58651 +             * the same. */
58652 +        g_BlockSizes[0] = g_BlockSizes[1];
58653 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0]));
58654 +
58655 +        if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) {
58656 +            AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n",
58657 +                g_BlockSizes[1], BUFFER_BLOCK_PAD));
58658 +            break;
58659 +        }
58660 +
58661 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n"));
58662 +
58663 +            /* the target lets us know it is ready by giving us 1 credit on
58664 +             * mailbox 0 */
58665 +        status = GetCredits(pDev, 0, &credits);
58666 +
58667 +        if (status != A_OK) {
58668 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n"));
58669 +            break;
58670 +        }
58671 +
58672 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n"));
58673 +
58674 +            /* read the first 4 scratch registers */
58675 +        status = HIFReadWrite(pDev->HIFDevice,
58676 +                              SCRATCH_ADDRESS,
58677 +                              params,
58678 +                              4,
58679 +                              HIF_RD_SYNC_BYTE_INC,
58680 +                              NULL);
58681 +
58682 +        if (status != A_OK) {
58683 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n"));
58684 +            break;
58685 +        }
58686 +
58687 +        numBufs = params[0];
58688 +        bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]);
58689 +
58690 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE,
58691 +            ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n",
58692 +            numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES));
58693 +
58694 +        if ((numBufs * bufferSize) < TOTAL_BYTES) {
58695 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n",
58696 +                TOTAL_BYTES, (numBufs*bufferSize)));
58697 +            status = A_ERROR;
58698 +            break;
58699 +        }
58700 +
58701 +        temp = GetEndMarker();
58702 +
58703 +        status = HIFReadWrite(pDev->HIFDevice,
58704 +                              SCRATCH_ADDRESS + 4,
58705 +                              (A_UINT8 *)&temp,
58706 +                              2,
58707 +                              HIF_WR_SYNC_BYTE_INC,
58708 +                              NULL);
58709 +
58710 +        if (status != A_OK) {
58711 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n"));
58712 +            break;
58713 +        }
58714 +
58715 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp));
58716 +
58717 +        temp = (A_UINT16)g_BlockSizes[1];
58718 +            /* convert to a mask */
58719 +        temp = temp - 1;
58720 +        status = HIFReadWrite(pDev->HIFDevice,
58721 +                              SCRATCH_ADDRESS + 6,
58722 +                              (A_UINT8 *)&temp,
58723 +                              2,
58724 +                              HIF_WR_SYNC_BYTE_INC,
58725 +                              NULL);
58726 +
58727 +        if (status != A_OK) {
58728 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n"));
58729 +            break;
58730 +        }
58731 +
58732 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp));
58733 +
58734 +            /* execute the test on each mailbox */
58735 +        for (i = 0; i < AR6K_MAILBOXES; i++) {
58736 +            status = DoOneMboxHWTest(pDev, i);
58737 +            if (status != A_OK) {
58738 +                break;
58739 +            }
58740 +        }
58741 +
58742 +    } while (FALSE);
58743 +
58744 +    if (status == A_OK) {
58745 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! -  \n"));
58746 +    } else {
58747 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! -  \n"));
58748 +    }
58749 +        /* don't let HTC_Start continue, the target is actually not running any HTC code */
58750 +    return A_ERROR;
58751 +}
58752 +#endif
58753 +
58754 +
58755 +
58756 --- /dev/null
58757 +++ b/drivers/ar6000/htc/ar6k_events.c
58758 @@ -0,0 +1,638 @@
58759 +/*
58760 + * AR6K Driver layer event handling (i.e. interrupts, message polling)
58761 + *
58762 + * Copyright (c) 2007 Atheros Communications Inc.
58763 + * All rights reserved.
58764 + *
58765 + *
58766 + *  This program is free software; you can redistribute it and/or modify
58767 + *  it under the terms of the GNU General Public License version 2 as
58768 + *  published by the Free Software Foundation;
58769 + *
58770 + *  Software distributed under the License is distributed on an "AS
58771 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
58772 + *  implied. See the License for the specific language governing
58773 + *  rights and limitations under the License.
58774 + *
58775 + *
58776 + *
58777 + */
58778 +#include "a_config.h"
58779 +#include "athdefs.h"
58780 +#include "a_types.h"
58781 +#include "AR6Khwreg.h"
58782 +#include "a_osapi.h"
58783 +#include "a_debug.h"
58784 +#include "hif.h"
58785 +#include "htc_packet.h"
58786 +#include "ar6k.h"
58787 +
58788 +extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
58789 +extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
58790 +
58791 +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev);
58792 +
58793 +#define DELAY_PER_INTERVAL_MS 10  /* 10 MS delay per polling interval */
58794 +
58795 +/* completion routine for ALL HIF layer async I/O */
58796 +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status)
58797 +{
58798 +    HTC_PACKET *pPacket = (HTC_PACKET *)context;
58799 +
58800 +    COMPLETE_HTC_PACKET(pPacket,status);
58801 +
58802 +    return A_OK;
58803 +}
58804 +
58805 +/* mailbox recv message polling */
58806 +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
58807 +                            A_UINT32    *pLookAhead,
58808 +                            int          TimeoutMS)
58809 +{
58810 +    A_STATUS status = A_OK;
58811 +    int      timeout = TimeoutMS/DELAY_PER_INTERVAL_MS;
58812 +
58813 +    AR_DEBUG_ASSERT(timeout > 0);
58814 +
58815 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n"));
58816 +
58817 +    while (TRUE) {
58818 +
58819 +        if (pDev->GetPendingEventsFunc != NULL)
58820 +               {
58821 +
58822 +            HIF_PENDING_EVENTS_INFO events;
58823 +
58824 +            /* the HIF layer uses a special mechanism to get events, do this
58825 +             * synchronously */
58826 +            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
58827 +                                            &events,
58828 +                                            NULL);
58829 +            if (A_FAILED(status))
58830 +                       {
58831 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n"));
58832 +                               break;
58833 +            }
58834 +
58835 +            if (events.Events & HIF_RECV_MSG_AVAIL)
58836 +                       {
58837 +                    /*  there is a message available, the lookahead should be valid now */
58838 +                *pLookAhead = events.LookAhead;
58839 +
58840 +                break;
58841 +            }
58842 +        }
58843 +               else
58844 +               {
58845 +
58846 +                /* this is the standard HIF way.... */
58847 +                /* load the register table */
58848 +            status = HIFReadWrite(pDev->HIFDevice,
58849 +                                  HOST_INT_STATUS_ADDRESS,
58850 +                                  (A_UINT8 *)&pDev->IrqProcRegisters,
58851 +                                  AR6K_IRQ_PROC_REGS_SIZE,
58852 +                                  HIF_RD_SYNC_BYTE_INC,
58853 +                                  NULL);
58854 +
58855 +            if (A_FAILED(status))
58856 +                       {
58857 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n"));
58858 +                break;
58859 +            }
58860 +
58861 +                /* check for MBOX data and valid lookahead */
58862 +            if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX))
58863 +                       {
58864 +                if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX))
58865 +                               {
58866 +                    /* mailbox has a message and the look ahead is valid */
58867 +                    *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
58868 +                    break;
58869 +                }
58870 +            }
58871 +
58872 +        }
58873 +
58874 +        timeout--;
58875 +
58876 +        if (timeout <= 0)
58877 +               {
58878 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n"));
58879 +            status = A_ERROR;
58880 +
58881 +                /* check if the target asserted */
58882 +            if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
58883 +                    /* target signaled an assert, process this pending interrupt
58884 +                     * this will call the target failure handler */
58885 +                DevServiceDebugInterrupt(pDev);
58886 +            }
58887 +
58888 +            break;
58889 +        }
58890 +
58891 +            /* delay a little  */
58892 +         A_MDELAY(DELAY_PER_INTERVAL_MS);
58893 +         AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("  Retry Mbox Poll : %d \n",timeout));
58894 +    }
58895 +
58896 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n"));
58897 +
58898 +    return status;
58899 +}
58900 +
58901 +static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev)
58902 +{
58903 +    A_STATUS status;
58904 +    A_UINT8  cpu_int_status;
58905 +    A_UINT8  regBuffer[4];
58906 +
58907 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n"));
58908 +    cpu_int_status = pDev->IrqProcRegisters.cpu_int_status &
58909 +                     pDev->IrqEnableRegisters.cpu_int_status_enable;
58910 +    AR_DEBUG_ASSERT(cpu_int_status);
58911 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
58912 +                    ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
58913 +                    cpu_int_status));
58914 +
58915 +        /* Clear the interrupt */
58916 +    pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */
58917 +
58918 +        /* set up the register transfer buffer to hit the register 4 times , this is done
58919 +         * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
58920 +         * restrict bus transfer lengths to be a multiple of 4-bytes */
58921 +
58922 +        /* set W1C value to clear the interrupt, this hits the register first */
58923 +    regBuffer[0] = cpu_int_status;
58924 +        /* the remaining 4 values are set to zero which have no-effect  */
58925 +    regBuffer[1] = 0;
58926 +    regBuffer[2] = 0;
58927 +    regBuffer[3] = 0;
58928 +
58929 +    status = HIFReadWrite(pDev->HIFDevice,
58930 +                          CPU_INT_STATUS_ADDRESS,
58931 +                          regBuffer,
58932 +                          4,
58933 +                          HIF_WR_SYNC_BYTE_FIX,
58934 +                          NULL);
58935 +
58936 +    AR_DEBUG_ASSERT(status == A_OK);
58937 +    return status;
58938 +}
58939 +
58940 +
58941 +static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev)
58942 +{
58943 +    A_STATUS status;
58944 +    A_UINT8  error_int_status;
58945 +    A_UINT8  regBuffer[4];
58946 +
58947 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n"));
58948 +    error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F;
58949 +    AR_DEBUG_ASSERT(error_int_status);
58950 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
58951 +                    ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
58952 +                    error_int_status));
58953 +
58954 +    if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
58955 +        /* Wakeup */
58956 +        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n"));
58957 +    }
58958 +
58959 +    if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
58960 +        /* Rx Underflow */
58961 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n"));
58962 +    }
58963 +
58964 +    if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
58965 +        /* Tx Overflow */
58966 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n"));
58967 +    }
58968 +
58969 +        /* Clear the interrupt */
58970 +    pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */
58971 +
58972 +        /* set up the register transfer buffer to hit the register 4 times , this is done
58973 +         * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
58974 +         * restrict bus transfer lengths to be a multiple of 4-bytes */
58975 +
58976 +        /* set W1C value to clear the interrupt, this hits the register first */
58977 +    regBuffer[0] = error_int_status;
58978 +        /* the remaining 4 values are set to zero which have no-effect  */
58979 +    regBuffer[1] = 0;
58980 +    regBuffer[2] = 0;
58981 +    regBuffer[3] = 0;
58982 +
58983 +    status = HIFReadWrite(pDev->HIFDevice,
58984 +                          ERROR_INT_STATUS_ADDRESS,
58985 +                          regBuffer,
58986 +                          4,
58987 +                          HIF_WR_SYNC_BYTE_FIX,
58988 +                          NULL);
58989 +
58990 +    AR_DEBUG_ASSERT(status == A_OK);
58991 +    return status;
58992 +}
58993 +
58994 +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev)
58995 +{
58996 +    A_UINT32 dummy;
58997 +    A_STATUS status;
58998 +
58999 +    /* Send a target failure event to the application */
59000 +    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n"));
59001 +
59002 +    if (pDev->TargetFailureCallback != NULL) {
59003 +        pDev->TargetFailureCallback(pDev->HTCContext);
59004 +    }
59005 +
59006 +    /* clear the interrupt , the debug error interrupt is
59007 +     * counter 0 */
59008 +        /* read counter to clear interrupt */
59009 +    status = HIFReadWrite(pDev->HIFDevice,
59010 +                          COUNT_DEC_ADDRESS,
59011 +                          (A_UINT8 *)&dummy,
59012 +                          4,
59013 +                          HIF_RD_SYNC_BYTE_INC,
59014 +                          NULL);
59015 +
59016 +    AR_DEBUG_ASSERT(status == A_OK);
59017 +    return status;
59018 +}
59019 +
59020 +static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev)
59021 +{
59022 +    A_UINT8 counter_int_status;
59023 +
59024 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n"));
59025 +
59026 +    counter_int_status = pDev->IrqProcRegisters.counter_int_status &
59027 +                         pDev->IrqEnableRegisters.counter_int_status_enable;
59028 +
59029 +    AR_DEBUG_ASSERT(counter_int_status);
59030 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
59031 +                    ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
59032 +                    counter_int_status));
59033 +
59034 +    /* Check if the debug interrupt is pending */
59035 +    if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
59036 +        return DevServiceDebugInterrupt(pDev);
59037 +    }
59038 +
59039 +    return A_OK;
59040 +}
59041 +
59042 +/* callback when our fetch to get interrupt status registers completes */
59043 +static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket)
59044 +{
59045 +    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
59046 +    A_UINT32    lookAhead = 0;
59047 +    A_BOOL      otherInts = FALSE;
59048 +
59049 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
59050 +
59051 +    do {
59052 +
59053 +        if (A_FAILED(pPacket->Status)) {
59054 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
59055 +                    (" GetEvents I/O request failed, status:%d \n", pPacket->Status));
59056 +            /* bail out, don't unmask HIF interrupt */
59057 +            break;
59058 +        }
59059 +
59060 +        if (pDev->GetPendingEventsFunc != NULL) {
59061 +                /* the HIF layer collected the information for us */
59062 +            HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer;
59063 +            if (pEvents->Events & HIF_RECV_MSG_AVAIL) {
59064 +                lookAhead = pEvents->LookAhead;
59065 +                if (0 == lookAhead) {
59066 +                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
59067 +                }
59068 +            }
59069 +            if (pEvents->Events & HIF_OTHER_EVENTS) {
59070 +                otherInts = TRUE;
59071 +            }
59072 +        } else {
59073 +                /* standard interrupt table handling.... */
59074 +            AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer;
59075 +            A_UINT8                 host_int_status;
59076 +
59077 +            host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable;
59078 +
59079 +            if (host_int_status & (1 << HTC_MAILBOX)) {
59080 +                host_int_status &= ~(1 << HTC_MAILBOX);
59081 +                if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) {
59082 +                        /* mailbox has a message and the look ahead is valid */
59083 +                    lookAhead = pReg->rx_lookahead[HTC_MAILBOX];
59084 +                    if (0 == lookAhead) {
59085 +                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
59086 +                    }
59087 +                }
59088 +            }
59089 +
59090 +            if (host_int_status) {
59091 +                    /* there are other interrupts to handle */
59092 +                otherInts = TRUE;
59093 +            }
59094 +        }
59095 +
59096 +        if (otherInts || (lookAhead == 0)) {
59097 +            /* if there are other interrupts to process, we cannot do this in the async handler so
59098 +             * ack the interrupt which will cause our sync handler to run again
59099 +             * if however there are no more messages, we can now ack the interrupt  */
59100 +            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
59101 +                (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
59102 +                otherInts, lookAhead));
59103 +            HIFAckInterrupt(pDev->HIFDevice);
59104 +        } else {
59105 +            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
59106 +                    (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
59107 +                    lookAhead));
59108 +                /* lookahead is non-zero and there are no other interrupts to service,
59109 +                 * go get the next message */
59110 +            pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, NULL);
59111 +        }
59112 +
59113 +    } while (FALSE);
59114 +
59115 +        /* free this IO packet */
59116 +    AR6KFreeIOPacket(pDev,pPacket);
59117 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n"));
59118 +}
59119 +
59120 +/* called by the HTC layer when it wants us to check if the device has any more pending
59121 + * recv messages, this starts off a series of async requests to read interrupt registers  */
59122 +A_STATUS DevCheckPendingRecvMsgsAsync(void *context)
59123 +{
59124 +    AR6K_DEVICE  *pDev = (AR6K_DEVICE *)context;
59125 +    A_STATUS      status = A_OK;
59126 +    HTC_PACKET   *pIOPacket;
59127 +
59128 +    /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
59129 +     * cause us to switch contexts */
59130 +
59131 +   AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev));
59132 +
59133 +   do {
59134 +
59135 +        if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
59136 +                /* break the async processing chain right here, no need to continue.
59137 +                 * The DevDsrHandler() will handle things in a loop when things are driven
59138 +                 * synchronously  */
59139 +            break;
59140 +        }
59141 +            /* first allocate one of our HTC packets we created for async I/O
59142 +             * we reuse HTC packet definitions so that we can use the completion mechanism
59143 +             * in DevRWCompletionHandler() */
59144 +        pIOPacket = AR6KAllocIOPacket(pDev);
59145 +
59146 +        if (NULL == pIOPacket) {
59147 +                /* there should be only 1 asynchronous request out at a time to read these registers
59148 +                 * so this should actually never happen */
59149 +            status = A_NO_MEMORY;
59150 +            AR_DEBUG_ASSERT(FALSE);
59151 +            break;
59152 +        }
59153 +
59154 +            /* stick in our completion routine when the I/O operation completes */
59155 +        pIOPacket->Completion = DevGetEventAsyncHandler;
59156 +        pIOPacket->pContext = pDev;
59157 +
59158 +        if (pDev->GetPendingEventsFunc) {
59159 +                /* HIF layer has it's own mechanism, pass the IO to it.. */
59160 +            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
59161 +                                                (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer,
59162 +                                                pIOPacket);
59163 +
59164 +        } else {
59165 +                /* standard way, read the interrupt register table asynchronously again */
59166 +            status = HIFReadWrite(pDev->HIFDevice,
59167 +                                  HOST_INT_STATUS_ADDRESS,
59168 +                                  pIOPacket->pBuffer,
59169 +                                  AR6K_IRQ_PROC_REGS_SIZE,
59170 +                                  HIF_RD_ASYNC_BYTE_INC,
59171 +                                  pIOPacket);
59172 +        }
59173 +
59174 +        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n"));
59175 +   } while (FALSE);
59176 +
59177 +   AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n"));
59178 +
59179 +   return status;
59180 +}
59181 +
59182 +/* process pending interrupts synchronously */
59183 +static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing)
59184 +{
59185 +    A_STATUS    status = A_OK;
59186 +    A_UINT8     host_int_status = 0;
59187 +    A_UINT32    lookAhead = 0;
59188 +
59189 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev));
59190 +
59191 +    /*** NOTE: the HIF implementation guarantees that the context of this call allows
59192 +     *         us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
59193 +     *         can block or switch thread/task ontexts.
59194 +     *         This is a fully schedulable context.
59195 +     * */
59196 +    do {
59197 +
59198 +        if (pDev->GetPendingEventsFunc != NULL) {
59199 +            HIF_PENDING_EVENTS_INFO events;
59200 +
59201 +                /* the HIF layer uses a special mechanism to get events
59202 +                 * get this synchronously  */
59203 +            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
59204 +                                                &events,
59205 +                                                NULL);
59206 +
59207 +            if (A_FAILED(status)) {
59208 +                break;
59209 +            }
59210 +
59211 +            if (events.Events & HIF_RECV_MSG_AVAIL) {
59212 +                lookAhead = events.LookAhead;
59213 +                if (0 == lookAhead) {
59214 +                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
59215 +                }
59216 +            }
59217 +
59218 +            if (!(events.Events & HIF_OTHER_EVENTS) ||
59219 +                !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) {
59220 +                    /* no need to read the register table, no other interesting interrupts.
59221 +                     * Some interfaces (like SPI) can shadow interrupt sources without
59222 +                     * requiring the host to do a full table read */
59223 +                break;
59224 +            }
59225 +
59226 +            /* otherwise fall through and read the register table */
59227 +        }
59228 +
59229 +        /*
59230 +         * Read the first 28 bytes of the HTC register table. This will yield us
59231 +         * the value of different int status registers and the lookahead
59232 +         * registers.
59233 +         *    length = sizeof(int_status) + sizeof(cpu_int_status) +
59234 +         *             sizeof(error_int_status) + sizeof(counter_int_status) +
59235 +         *             sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
59236 +         *             sizeof(hole) +  sizeof(rx_lookahead) +
59237 +         *             sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
59238 +         *             sizeof(error_status_enable) +
59239 +         *             sizeof(counter_int_status_enable);
59240 +         *
59241 +        */
59242 +        status = HIFReadWrite(pDev->HIFDevice,
59243 +                              HOST_INT_STATUS_ADDRESS,
59244 +                              (A_UINT8 *)&pDev->IrqProcRegisters,
59245 +                              AR6K_IRQ_PROC_REGS_SIZE,
59246 +                              HIF_RD_SYNC_BYTE_INC,
59247 +                              NULL);
59248 +
59249 +        if (A_FAILED(status)) {
59250 +            break;
59251 +        }
59252 +
59253 +        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) {
59254 +            DevDumpRegisters(&pDev->IrqProcRegisters,
59255 +                             &pDev->IrqEnableRegisters);
59256 +        }
59257 +
59258 +            /* Update only those registers that are enabled */
59259 +        host_int_status = pDev->IrqProcRegisters.host_int_status &
59260 +                          pDev->IrqEnableRegisters.int_status_enable;
59261 +
59262 +        if (NULL == pDev->GetPendingEventsFunc) {
59263 +                /* only look at mailbox status if the HIF layer did not provide this function,
59264 +                 * on some HIF interfaces reading the RX lookahead is not valid to do */
59265 +            if (host_int_status & (1 << HTC_MAILBOX)) {
59266 +                    /* mask out pending mailbox value, we use "lookAhead" as the real flag for
59267 +                     * mailbox processing below */
59268 +                host_int_status &= ~(1 << HTC_MAILBOX);
59269 +                if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) {
59270 +                        /* mailbox has a message and the look ahead is valid */
59271 +                    lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
59272 +                    if (0 == lookAhead) {
59273 +                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
59274 +                    }
59275 +                }
59276 +            }
59277 +        } else {
59278 +                /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
59279 +            host_int_status &= ~(1 << HTC_MAILBOX);
59280 +        }
59281 +
59282 +    } while (FALSE);
59283 +
59284 +
59285 +    do {
59286 +
59287 +            /* did the interrupt status fetches succeed? */
59288 +        if (A_FAILED(status)) {
59289 +            break;
59290 +        }
59291 +
59292 +        if ((0 == host_int_status) && (0 == lookAhead)) {
59293 +                /* nothing to process, the caller can use this to break out of a loop */
59294 +            *pDone = TRUE;
59295 +            break;
59296 +        }
59297 +
59298 +        if (lookAhead != 0) {
59299 +            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead));
59300 +                /* Mailbox Interrupt, the HTC layer may issue async requests to empty the
59301 +                 * mailbox...
59302 +                 * When emptying the recv mailbox we use the async handler above called from the
59303 +                 * completion routine of the callers read request. This can improve performance
59304 +                 * by reducing context switching when we rapidly pull packets */
59305 +            status = pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, pASyncProcessing);
59306 +            if (A_FAILED(status)) {
59307 +                break;
59308 +            }
59309 +        }
59310 +
59311 +            /* now handle the rest of them */
59312 +        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
59313 +                            (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
59314 +                            host_int_status));
59315 +
59316 +        if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
59317 +                /* CPU Interrupt */
59318 +            status = DevServiceCPUInterrupt(pDev);
59319 +            if (A_FAILED(status)){
59320 +                break;
59321 +            }
59322 +        }
59323 +
59324 +        if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
59325 +                /* Error Interrupt */
59326 +            status = DevServiceErrorInterrupt(pDev);
59327 +            if (A_FAILED(status)){
59328 +                break;
59329 +            }
59330 +        }
59331 +
59332 +        if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
59333 +                /* Counter Interrupt */
59334 +            status = DevServiceCounterInterrupt(pDev);
59335 +            if (A_FAILED(status)){
59336 +                break;
59337 +            }
59338 +        }
59339 +
59340 +    } while (FALSE);
59341 +
59342 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
59343 +                *pDone, *pASyncProcessing, status));
59344 +
59345 +    return status;
59346 +}
59347 +
59348 +
59349 +/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
59350 +A_STATUS DevDsrHandler(void *context)
59351 +{
59352 +    AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
59353 +    A_STATUS    status = A_OK;
59354 +    A_BOOL      done = FALSE;
59355 +    A_BOOL      asyncProc = FALSE;
59356 +
59357 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
59358 +
59359 +
59360 +    while (!done) {
59361 +        status = ProcessPendingIRQs(pDev, &done, &asyncProc);
59362 +        if (A_FAILED(status)) {
59363 +            break;
59364 +        }
59365 +
59366 +        if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
59367 +            /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
59368 +            asyncProc = FALSE;
59369 +            /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
59370 +             * this has a nice side effect of blocking us until all async read requests are completed.
59371 +             * This behavior is required on some HIF implementations that do not allow ASYNC
59372 +             * processing in interrupt handlers (like Windows CE) */
59373 +        }
59374 +
59375 +        if (asyncProc) {
59376 +                /* the function performed some async I/O for performance, we
59377 +                   need to exit the ISR immediately, the check below will prevent the interrupt from being
59378 +                   Ack'd while we handle it asynchronously */
59379 +            break;
59380 +        }
59381 +
59382 +    }
59383 +
59384 +    if (A_SUCCESS(status) && !asyncProc) {
59385 +            /* Ack the interrupt only if :
59386 +             *  1. we did not get any errors in processing interrupts
59387 +             *  2. there are no outstanding async processing requests */
59388 +        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n"));
59389 +        HIFAckInterrupt(pDev->HIFDevice);
59390 +    }
59391 +
59392 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n"));
59393 +    return A_OK;
59394 +}
59395 +
59396 +
59397 --- /dev/null
59398 +++ b/drivers/ar6000/htc/ar6k.h
59399 @@ -0,0 +1,191 @@
59400 +/*
59401 + *
59402 + * Copyright (c) 2007 Atheros Communications Inc.
59403 + * All rights reserved.
59404 + *
59405 + *
59406 + *  This program is free software; you can redistribute it and/or modify
59407 + *  it under the terms of the GNU General Public License version 2 as
59408 + *  published by the Free Software Foundation;
59409 + *
59410 + *  Software distributed under the License is distributed on an "AS
59411 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
59412 + *  implied. See the License for the specific language governing
59413 + *  rights and limitations under the License.
59414 + *
59415 + *
59416 + *
59417 + */
59418 +
59419 +#ifndef AR6K_H_
59420 +#define AR6K_H_
59421 +
59422 +#define AR6K_MAILBOXES 4
59423 +
59424 +/* HTC runs over mailbox 0 */
59425 +#define HTC_MAILBOX          0
59426 +
59427 +#define AR6K_TARGET_DEBUG_INTR_MASK     0x01
59428 +
59429 +#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK |   \
59430 +                            INT_STATUS_ENABLE_CPU_MASK   |   \
59431 +                            INT_STATUS_ENABLE_COUNTER_MASK)
59432 +
59433 +//#define MBOXHW_UNIT_TEST 1
59434 +
59435 +#include "athstartpack.h"
59436 +typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS {
59437 +    A_UINT8                      host_int_status;
59438 +    A_UINT8                      cpu_int_status;
59439 +    A_UINT8                      error_int_status;
59440 +    A_UINT8                      counter_int_status;
59441 +    A_UINT8                      mbox_frame;
59442 +    A_UINT8                      rx_lookahead_valid;
59443 +    A_UINT8                      hole[2];
59444 +    A_UINT32                     rx_lookahead[2];
59445 +} POSTPACK AR6K_IRQ_PROC_REGISTERS;
59446 +
59447 +#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS)
59448 +
59449 +
59450 +
59451 +typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS {
59452 +    A_UINT8                      int_status_enable;
59453 +    A_UINT8                      cpu_int_status_enable;
59454 +    A_UINT8                      error_status_enable;
59455 +    A_UINT8                      counter_int_status_enable;
59456 +} POSTPACK AR6K_IRQ_ENABLE_REGISTERS;
59457 +
59458 +#include "athendpack.h"
59459 +
59460 +#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS)
59461 +
59462 +#define AR6K_REG_IO_BUFFER_SIZE     32
59463 +#define AR6K_MAX_REG_IO_BUFFERS     8
59464 +
59465 +/* buffers for ASYNC I/O */
59466 +typedef struct AR6K_ASYNC_REG_IO_BUFFER {
59467 +    HTC_PACKET    HtcPacket;   /* we use an HTC packet as a wrapper for our async register-based I/O */
59468 +    A_UINT8       Buffer[AR6K_REG_IO_BUFFER_SIZE];
59469 +} AR6K_ASYNC_REG_IO_BUFFER;
59470 +
59471 +typedef struct _AR6K_DEVICE {
59472 +    A_MUTEX_T                   Lock;
59473 +    AR6K_IRQ_PROC_REGISTERS     IrqProcRegisters;
59474 +    AR6K_IRQ_ENABLE_REGISTERS   IrqEnableRegisters;
59475 +    void                        *HIFDevice;
59476 +    A_UINT32                    BlockSize;
59477 +    A_UINT32                    BlockMask;
59478 +    A_UINT32                    MailboxAddress;
59479 +    HIF_PENDING_EVENTS_FUNC     GetPendingEventsFunc;
59480 +    void                        *HTCContext;
59481 +    HTC_PACKET_QUEUE            RegisterIOList;
59482 +    AR6K_ASYNC_REG_IO_BUFFER    RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
59483 +    void                        (*TargetFailureCallback)(void *Context);
59484 +    A_STATUS                    (*MessagePendingCallback)(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc);
59485 +    HIF_DEVICE_IRQ_PROCESSING_MODE  HifIRQProcessingMode;
59486 +    HIF_MASK_UNMASK_RECV_EVENT      HifMaskUmaskRecvEvent;
59487 +} AR6K_DEVICE;
59488 +
59489 +#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
59490 +
59491 +A_STATUS DevSetup(AR6K_DEVICE *pDev);
59492 +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev);
59493 +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev);
59494 +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
59495 +                            A_UINT32    *pLookAhead,
59496 +                            int          TimeoutMS);
59497 +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status);
59498 +A_STATUS DevDsrHandler(void *context);
59499 +A_STATUS DevCheckPendingRecvMsgsAsync(void *context);
59500 +void     DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS   *pIrqProcRegs,
59501 +                          AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs);
59502 +
59503 +#define DEV_STOP_RECV_ASYNC TRUE
59504 +#define DEV_STOP_RECV_SYNC  FALSE
59505 +#define DEV_ENABLE_RECV_ASYNC TRUE
59506 +#define DEV_ENABLE_RECV_SYNC  FALSE
59507 +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
59508 +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
59509 +
59510 +static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) {
59511 +    A_UINT32 paddedLength;
59512 +    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
59513 +    A_STATUS status;
59514 +
59515 +       /* adjust the length to be a multiple of block size if appropriate */
59516 +    paddedLength = (SendLength + (pDev->BlockMask)) &
59517 +                    (~(pDev->BlockMask));
59518 +#if 0 // BufferLength may not be set in , fix this...
59519 +    if (paddedLength > pPacket->BufferLength) {
59520 +        AR_DEBUG_ASSERT(FALSE);
59521 +        if (pPacket->Completion != NULL) {
59522 +            COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
59523 +        }
59524 +        return A_EINVAL;
59525 +    }
59526 +#endif
59527 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
59528 +                ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
59529 +                paddedLength,
59530 +                pDev->MailboxAddress,
59531 +                sync ? "SYNC" : "ASYNC"));
59532 +
59533 +    status = HIFReadWrite(pDev->HIFDevice,
59534 +                          pDev->MailboxAddress,
59535 +                          pPacket->pBuffer,
59536 +                          paddedLength,     /* the padded length */
59537 +                          sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
59538 +                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
59539 +
59540 +    if (sync) {
59541 +        pPacket->Status = status;
59542 +    }
59543 +
59544 +    return status;
59545 +}
59546 +
59547 +static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) {
59548 +    A_UINT32 paddedLength;
59549 +    A_STATUS status;
59550 +    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
59551 +
59552 +        /* adjust the length to be a multiple of block size if appropriate */
59553 +    paddedLength = (RecvLength + (pDev->BlockMask)) &
59554 +                    (~(pDev->BlockMask));
59555 +    if (paddedLength > pPacket->BufferLength) {
59556 +        AR_DEBUG_ASSERT(FALSE);
59557 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
59558 +                ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
59559 +                    paddedLength,RecvLength,pPacket->BufferLength));
59560 +        if (pPacket->Completion != NULL) {
59561 +            COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
59562 +        }
59563 +        return A_EINVAL;
59564 +    }
59565 +
59566 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
59567 +                ("DevRecvPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
59568 +                paddedLength,
59569 +                pDev->MailboxAddress,
59570 +                sync ? "SYNC" : "ASYNC"));
59571 +
59572 +    status = HIFReadWrite(pDev->HIFDevice,
59573 +                          pDev->MailboxAddress,
59574 +                          pPacket->pBuffer,
59575 +                          paddedLength,
59576 +                          sync ? HIF_RD_SYNC_BLOCK_INC : HIF_RD_ASYNC_BLOCK_INC,
59577 +                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
59578 +
59579 +    if (sync) {
59580 +        pPacket->Status = status;
59581 +    }
59582 +
59583 +    return status;
59584 +}
59585 +
59586 +#ifdef MBOXHW_UNIT_TEST
59587 +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev);
59588 +#endif
59589 +
59590 +#endif /*AR6K_H_*/
59591 --- /dev/null
59592 +++ b/drivers/ar6000/htc/htc.c
59593 @@ -0,0 +1,507 @@
59594 +/*
59595 + *
59596 + * Copyright (c) 2007 Atheros Communications Inc.
59597 + * All rights reserved.
59598 + *
59599 + *
59600 + *  This program is free software; you can redistribute it and/or modify
59601 + *  it under the terms of the GNU General Public License version 2 as
59602 + *  published by the Free Software Foundation;
59603 + *
59604 + *  Software distributed under the License is distributed on an "AS
59605 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
59606 + *  implied. See the License for the specific language governing
59607 + *  rights and limitations under the License.
59608 + *
59609 + *
59610 + *
59611 + */
59612 +
59613 +#include "htc_internal.h"
59614 +
59615 +
59616 +static HTC_INIT_INFO  HTCInitInfo = {NULL,NULL,NULL};
59617 +static A_BOOL         HTCInitialized = FALSE;
59618 +
59619 +static A_STATUS HTCTargetInsertedHandler(void *hif_handle);
59620 +static A_STATUS HTCTargetRemovedHandler(void *handle, A_STATUS status);
59621 +static void HTCReportFailure(void *Context);
59622 +
59623 +/* Initializes the HTC layer */
59624 +A_STATUS HTCInit(HTC_INIT_INFO *pInitInfo)
59625 +{
59626 +    HTC_CALLBACKS htcCallbacks;
59627 +
59628 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Enter\n"));
59629 +    if (HTCInitialized) {
59630 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n"));
59631 +        return A_OK;
59632 +    }
59633 +
59634 +    A_MEMCPY(&HTCInitInfo,pInitInfo,sizeof(HTC_INIT_INFO));
59635 +
59636 +    A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS));
59637 +
59638 +        /* setup HIF layer callbacks */
59639 +    htcCallbacks.deviceInsertedHandler = HTCTargetInsertedHandler;
59640 +    htcCallbacks.deviceRemovedHandler = HTCTargetRemovedHandler;
59641 +        /* the device layer handles these */
59642 +    htcCallbacks.rwCompletionHandler = DevRWCompletionHandler;
59643 +    htcCallbacks.dsrHandler = DevDsrHandler;
59644 +    HIFInit(&htcCallbacks);
59645 +    HTCInitialized = TRUE;
59646 +
59647 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n"));
59648 +    return A_OK;
59649 +}
59650 +
59651 +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList)
59652 +{
59653 +    LOCK_HTC(target);
59654 +    HTC_PACKET_ENQUEUE(pList,pPacket);
59655 +    UNLOCK_HTC(target);
59656 +}
59657 +
59658 +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target,  HTC_PACKET_QUEUE *pList)
59659 +{
59660 +    HTC_PACKET *pPacket;
59661 +
59662 +    LOCK_HTC(target);
59663 +    pPacket = HTC_PACKET_DEQUEUE(pList);
59664 +    UNLOCK_HTC(target);
59665 +
59666 +    return pPacket;
59667 +}
59668 +
59669 +/* cleanup the HTC instance */
59670 +static void HTCCleanup(HTC_TARGET *target)
59671 +{
59672 +    if (A_IS_MUTEX_VALID(&target->HTCLock)) {
59673 +        A_MUTEX_DELETE(&target->HTCLock);
59674 +    }
59675 +
59676 +    if (A_IS_MUTEX_VALID(&target->HTCRxLock)) {
59677 +        A_MUTEX_DELETE(&target->HTCRxLock);
59678 +    }
59679 +
59680 +    if (A_IS_MUTEX_VALID(&target->HTCTxLock)) {
59681 +        A_MUTEX_DELETE(&target->HTCTxLock);
59682 +    }
59683 +        /* free our instance */
59684 +    A_FREE(target);
59685 +}
59686 +
59687 +/* registered target arrival callback from the HIF layer */
59688 +static A_STATUS HTCTargetInsertedHandler(void *hif_handle)
59689 +{
59690 +    HTC_TARGET              *target = NULL;
59691 +    A_STATUS                 status;
59692 +    int                      i;
59693 +
59694 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Enter\n"));
59695 +
59696 +    do {
59697 +
59698 +            /* allocate target memory */
59699 +        if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) {
59700 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
59701 +            status = A_ERROR;
59702 +            break;
59703 +        }
59704 +
59705 +        A_MEMZERO(target, sizeof(HTC_TARGET));
59706 +        A_MUTEX_INIT(&target->HTCLock);
59707 +        A_MUTEX_INIT(&target->HTCRxLock);
59708 +        A_MUTEX_INIT(&target->HTCTxLock);
59709 +        INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList);
59710 +        INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList);
59711 +
59712 +            /* give device layer the hif device handle */
59713 +        target->Device.HIFDevice = hif_handle;
59714 +            /* give the device layer our context (for event processing)
59715 +             * the device layer will register it's own context with HIF
59716 +             * so we need to set this so we can fetch it in the target remove handler */
59717 +        target->Device.HTCContext = target;
59718 +            /* set device layer target failure callback */
59719 +        target->Device.TargetFailureCallback = HTCReportFailure;
59720 +            /* set device layer recv message pending callback */
59721 +        target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler;
59722 +        target->EpWaitingForBuffers = ENDPOINT_MAX;
59723 +
59724 +            /* setup device layer */
59725 +        status = DevSetup(&target->Device);
59726 +
59727 +        if (A_FAILED(status)) {
59728 +            break;
59729 +        }
59730 +
59731 +            /* carve up buffers/packets for control messages */
59732 +        for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) {
59733 +            HTC_PACKET *pControlPacket;
59734 +            pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
59735 +            SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket,
59736 +                                          target,
59737 +                                          target->HTCControlBuffers[i].Buffer,
59738 +                                          HTC_CONTROL_BUFFER_SIZE,
59739 +                                          ENDPOINT_0);
59740 +            HTC_FREE_CONTROL_RX(target,pControlPacket);
59741 +        }
59742 +
59743 +        for (;i < NUM_CONTROL_BUFFERS;i++) {
59744 +             HTC_PACKET *pControlPacket;
59745 +             pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
59746 +             INIT_HTC_PACKET_INFO(pControlPacket,
59747 +                                  target->HTCControlBuffers[i].Buffer,
59748 +                                  HTC_CONTROL_BUFFER_SIZE);
59749 +             HTC_FREE_CONTROL_TX(target,pControlPacket);
59750 +        }
59751 +
59752 +    } while (FALSE);
59753 +
59754 +    if (A_SUCCESS(status)) {
59755 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" calling AddInstance callback \n"));
59756 +            /* announce ourselves */
59757 +        HTCInitInfo.AddInstance((HTC_HANDLE)target);
59758 +    } else {
59759 +        if (target != NULL) {
59760 +            HTCCleanup(target);
59761 +        }
59762 +    }
59763 +
59764 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Exit\n"));
59765 +
59766 +    return status;
59767 +}
59768 +
59769 +/* registered removal callback from the HIF layer */
59770 +static A_STATUS HTCTargetRemovedHandler(void *handle, A_STATUS status)
59771 +{
59772 +    HTC_TARGET *target;
59773 +
59774 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCTargetRemovedHandler handle:0x%X \n",(A_UINT32)handle));
59775 +
59776 +    if (NULL == handle) {
59777 +            /* this could be NULL in the event that target initialization failed */
59778 +        return A_OK;
59779 +    }
59780 +
59781 +    target = ((AR6K_DEVICE *)handle)->HTCContext;
59782 +
59783 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("   removing target:0x%X instance:0x%X ... \n",
59784 +            (A_UINT32)target, (A_UINT32)target->pInstanceContext));
59785 +
59786 +    if (target->pInstanceContext != NULL) {
59787 +            /* let upper layer know, it needs to call HTCStop() */
59788 +        HTCInitInfo.DeleteInstance(target->pInstanceContext);
59789 +    }
59790 +
59791 +    HIFShutDownDevice(target->Device.HIFDevice);
59792 +
59793 +    HTCCleanup(target);
59794 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCTargetRemovedHandler \n"));
59795 +    return A_OK;
59796 +}
59797 +
59798 +/* get the low level HIF device for the caller , the caller may wish to do low level
59799 + * HIF requests */
59800 +void *HTCGetHifDevice(HTC_HANDLE HTCHandle)
59801 +{
59802 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
59803 +    return target->Device.HIFDevice;
59804 +}
59805 +
59806 +/* set the instance block for this HTC handle, so that on removal, the blob can be
59807 + * returned to the caller */
59808 +void HTCSetInstance(HTC_HANDLE HTCHandle, void *Instance)
59809 +{
59810 +    HTC_TARGET  *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
59811 +
59812 +    target->pInstanceContext = Instance;
59813 +}
59814 +
59815 +/* wait for the target to arrive (sends HTC Ready message)
59816 + * this operation is fully synchronous and the message is polled for */
59817 +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle)
59818 +{
59819 +    HTC_TARGET              *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
59820 +    A_STATUS                 status;
59821 +    HTC_PACKET              *pPacket = NULL;
59822 +    HTC_READY_MSG           *pRdyMsg;
59823 +    HTC_SERVICE_CONNECT_REQ  connect;
59824 +    HTC_SERVICE_CONNECT_RESP resp;
59825 +
59826 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%X) \n", (A_UINT32)target));
59827 +
59828 +    do {
59829 +
59830 +#ifdef MBOXHW_UNIT_TEST
59831 +
59832 +        status = DoMboxHWTest(&target->Device);
59833 +
59834 +        if (status != A_OK) {
59835 +            break;
59836 +        }
59837 +
59838 +#endif
59839 +
59840 +            /* we should be getting 1 control message that the target is ready */
59841 +        status = HTCWaitforControlMessage(target, &pPacket);
59842 +
59843 +        if (A_FAILED(status)) {
59844 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n"));
59845 +            break;
59846 +        }
59847 +
59848 +            /* we controlled the buffer creation so it has to be properly aligned */
59849 +        pRdyMsg = (HTC_READY_MSG *)pPacket->pBuffer;
59850 +
59851 +        if ((pRdyMsg->MessageID != HTC_MSG_READY_ID) ||
59852 +            (pPacket->ActualLength < sizeof(HTC_READY_MSG))) {
59853 +                /* this message is not valid */
59854 +            AR_DEBUG_ASSERT(FALSE);
59855 +            status = A_EPROTO;
59856 +            break;
59857 +        }
59858 +
59859 +        if (pRdyMsg->CreditCount == 0 || pRdyMsg->CreditSize == 0) {
59860 +              /* this message is not valid */
59861 +            AR_DEBUG_ASSERT(FALSE);
59862 +            status = A_EPROTO;
59863 +            break;
59864 +        }
59865 +
59866 +        target->TargetCredits = pRdyMsg->CreditCount;
59867 +        target->TargetCreditSize = pRdyMsg->CreditSize;
59868 +
59869 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Target Ready: credits: %d credit size: %d\n",
59870 +                target->TargetCredits, target->TargetCreditSize));
59871 +
59872 +            /* setup our pseudo HTC control endpoint connection */
59873 +        A_MEMZERO(&connect,sizeof(connect));
59874 +        A_MEMZERO(&resp,sizeof(resp));
59875 +        connect.EpCallbacks.pContext = target;
59876 +        connect.EpCallbacks.EpTxComplete = HTCControlTxComplete;
59877 +        connect.EpCallbacks.EpRecv = HTCControlRecv;
59878 +        connect.EpCallbacks.EpRecvRefill = NULL;  /* not needed */
59879 +        connect.EpCallbacks.EpSendFull = NULL;    /* not nedded */
59880 +        connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS;
59881 +        connect.ServiceID = HTC_CTRL_RSVD_SVC;
59882 +
59883 +            /* connect fake service */
59884 +        status = HTCConnectService((HTC_HANDLE)target,
59885 +                                   &connect,
59886 +                                   &resp);
59887 +
59888 +        if (!A_FAILED(status)) {
59889 +            break;
59890 +        }
59891 +
59892 +    } while (FALSE);
59893 +
59894 +    if (pPacket != NULL) {
59895 +        HTC_FREE_CONTROL_RX(target,pPacket);
59896 +    }
59897 +
59898 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n"));
59899 +
59900 +    return status;
59901 +}
59902 +
59903 +
59904 +
59905 +/* Start HTC, enable interrupts and let the target know host has finished setup */
59906 +A_STATUS HTCStart(HTC_HANDLE HTCHandle)
59907 +{
59908 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
59909 +    HTC_PACKET *pPacket;
59910 +    A_STATUS   status;
59911 +
59912 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n"));
59913 +
59914 +        /* now that we are starting, push control receive buffers into the
59915 +         * HTC control endpoint */
59916 +
59917 +    while (1) {
59918 +        pPacket = HTC_ALLOC_CONTROL_RX(target);
59919 +        if (NULL == pPacket) {
59920 +            break;
59921 +        }
59922 +        HTCAddReceivePkt((HTC_HANDLE)target,pPacket);
59923 +    }
59924 +
59925 +    do {
59926 +
59927 +        AR_DEBUG_ASSERT(target->InitCredits != NULL);
59928 +        AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL);
59929 +        AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL);
59930 +
59931 +            /* call init credits callback to do the distribution ,
59932 +             * NOTE: the first entry in the distribution list is ENDPOINT_0, so
59933 +             * we pass the start of the list after this one. */
59934 +        target->InitCredits(target->pCredDistContext,
59935 +                            target->EpCreditDistributionListHead->pNext,
59936 +                            target->TargetCredits);
59937 +
59938 +        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
59939 +            DumpCreditDistStates(target);
59940 +        }
59941 +
59942 +            /* the caller is done connecting to services, so we can indicate to the
59943 +            * target that the setup phase is complete */
59944 +        status = HTCSendSetupComplete(target);
59945 +
59946 +        if (A_FAILED(status)) {
59947 +            break;
59948 +        }
59949 +
59950 +            /* unmask interrupts */
59951 +        status = DevUnmaskInterrupts(&target->Device);
59952 +
59953 +        if (A_FAILED(status)) {
59954 +            HTCStop(target);
59955 +        }
59956 +
59957 +    } while (FALSE);
59958 +
59959 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n"));
59960 +    return status;
59961 +}
59962 +
59963 +
59964 +/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */
59965 +void HTCStop(HTC_HANDLE HTCHandle)
59966 +{
59967 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
59968 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n"));
59969 +
59970 +        /* mark that we are shutting down .. */
59971 +    target->HTCStateFlags |= HTC_STATE_STOPPING;
59972 +
59973 +        /* Masking interrupts is a synchronous operation, when this function returns
59974 +         * all pending HIF I/O has completed, we can safely flush the queues */
59975 +    DevMaskInterrupts(&target->Device);
59976 +
59977 +        /* flush all send packets */
59978 +    HTCFlushSendPkts(target);
59979 +        /* flush all recv buffers */
59980 +    HTCFlushRecvBuffers(target);
59981 +
59982 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n"));
59983 +}
59984 +
59985 +/* undo what was done in HTCInit() */
59986 +void HTCShutDown(void)
59987 +{
59988 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCShutDown: \n"));
59989 +    HTCInitialized = FALSE;
59990 +        /* undo HTCInit */
59991 +    HIFShutDownDevice(NULL);
59992 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCShutDown: \n"));
59993 +}
59994 +
59995 +void HTCDumpCreditStates(HTC_HANDLE HTCHandle)
59996 +{
59997 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
59998 +
59999 +    LOCK_HTC_TX(target);
60000 +
60001 +    DumpCreditDistStates(target);
60002 +
60003 +    UNLOCK_HTC_TX(target);
60004 +}
60005 +
60006 +/* report a target failure from the device, this is a callback from the device layer
60007 + * which uses a mechanism to report errors from the target (i.e. special interrupts) */
60008 +static void HTCReportFailure(void *Context)
60009 +{
60010 +    HTC_TARGET *target = (HTC_TARGET *)Context;
60011 +
60012 +    target->TargetFailure = TRUE;
60013 +
60014 +    if ((target->pInstanceContext != NULL) && (HTCInitInfo.TargetFailure != NULL)) {
60015 +            /* let upper layer know, it needs to call HTCStop() */
60016 +        HTCInitInfo.TargetFailure(target->pInstanceContext, A_ERROR);
60017 +    }
60018 +}
60019 +
60020 +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription)
60021 +{
60022 +    A_CHAR stream[60];
60023 +    A_UINT32 i;
60024 +    A_UINT16 offset, count;
60025 +
60026 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<---------Dumping %d Bytes : %s ------>\n", length, pDescription));
60027 +
60028 +    count = 0;
60029 +    offset = 0;
60030 +    for(i = 0; i < length; i++) {
60031 +        sprintf(stream + offset, "%2.2X ", buffer[i]);
60032 +        count ++;
60033 +        offset += 3;
60034 +
60035 +        if(count == 16) {
60036 +            count = 0;
60037 +            offset = 0;
60038 +            AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream));
60039 +            A_MEMZERO(stream, 60);
60040 +        }
60041 +    }
60042 +
60043 +    if(offset != 0) {
60044 +        AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream));
60045 +    }
60046 +
60047 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------------------------->\n"));
60048 +}
60049 +
60050 +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE               HTCHandle,
60051 +                                HTC_ENDPOINT_ID          Endpoint,
60052 +                                HTC_ENDPOINT_STAT_ACTION Action,
60053 +                                HTC_ENDPOINT_STATS       *pStats)
60054 +{
60055 +
60056 +#ifdef HTC_EP_STAT_PROFILING
60057 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
60058 +    A_BOOL     clearStats = FALSE;
60059 +    A_BOOL     sample = FALSE;
60060 +
60061 +    switch (Action) {
60062 +        case HTC_EP_STAT_SAMPLE :
60063 +            sample = TRUE;
60064 +            break;
60065 +        case HTC_EP_STAT_SAMPLE_AND_CLEAR :
60066 +            sample = TRUE;
60067 +            clearStats = TRUE;
60068 +            break;
60069 +        case HTC_EP_STAT_CLEAR :
60070 +            clearStats = TRUE;
60071 +            break;
60072 +        default:
60073 +            break;
60074 +    }
60075 +
60076 +    A_ASSERT(Endpoint < ENDPOINT_MAX);
60077 +
60078 +        /* lock out TX and RX while we sample and/or clear */
60079 +    LOCK_HTC_TX(target);
60080 +    LOCK_HTC_RX(target);
60081 +
60082 +    if (sample) {
60083 +        A_ASSERT(pStats != NULL);
60084 +            /* return the stats to the caller */
60085 +        A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
60086 +    }
60087 +
60088 +    if (clearStats) {
60089 +            /* reset stats */
60090 +        A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
60091 +    }
60092 +
60093 +    UNLOCK_HTC_RX(target);
60094 +    UNLOCK_HTC_TX(target);
60095 +
60096 +    return TRUE;
60097 +#else
60098 +    return FALSE;
60099 +#endif
60100 +}
60101 --- /dev/null
60102 +++ b/drivers/ar6000/htc/htc_debug.h
60103 @@ -0,0 +1,65 @@
60104 +#ifndef HTC_DEBUG_H_
60105 +#define HTC_DEBUG_H_
60106 +/*
60107 + *
60108 + * Copyright (c) 2004-2007 Atheros Communications Inc.
60109 + * All rights reserved.
60110 + *
60111 + *
60112 + *  This program is free software; you can redistribute it and/or modify
60113 + *  it under the terms of the GNU General Public License version 2 as
60114 + *  published by the Free Software Foundation;
60115 + *
60116 + *  Software distributed under the License is distributed on an "AS
60117 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
60118 + *  implied. See the License for the specific language governing
60119 + *  rights and limitations under the License.
60120 + *
60121 + *
60122 + *
60123 + */
60124 +
60125 +/* ------- Debug related stuff ------- */
60126 +enum {
60127 +    ATH_DEBUG_SEND = 0x0001,
60128 +    ATH_DEBUG_RECV = 0x0002,
60129 +    ATH_DEBUG_SYNC = 0x0004,
60130 +    ATH_DEBUG_DUMP = 0x0008,
60131 +    ATH_DEBUG_IRQ  = 0x0010,
60132 +    ATH_DEBUG_TRC  = 0x0020,
60133 +    ATH_DEBUG_WARN = 0x0040,
60134 +    ATH_DEBUG_ERR  = 0x0080,
60135 +    ATH_DEBUG_ANY  = 0xFFFF,
60136 +};
60137 +
60138 +#ifdef DEBUG
60139 +
60140 +// TODO FIX usage of A_PRINTF!
60141 +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl))
60142 +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do {   \
60143 +    if (debughtc & ATH_DEBUG_DUMP) {             \
60144 +        DebugDumpBytes(buffer, length,desc);               \
60145 +    }                                            \
60146 +} while(0)
60147 +#define PRINTX_ARG(arg...) arg
60148 +#define AR_DEBUG_PRINTF(flags, args) do {        \
60149 +    if (debughtc & (flags)) {                    \
60150 +        A_PRINTF(KERN_ALERT PRINTX_ARG args);    \
60151 +    }                                            \
60152 +} while (0)
60153 +#define AR_DEBUG_ASSERT(test) do {               \
60154 +    if (!(test)) {                               \
60155 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test));         \
60156 +    }                                            \
60157 +} while(0)
60158 +extern int debughtc;
60159 +#else
60160 +#define AR_DEBUG_PRINTF(flags, args)
60161 +#define AR_DEBUG_PRINTBUF(buffer, length, desc)
60162 +#define AR_DEBUG_ASSERT(test)
60163 +#define AR_DEBUG_LVL_CHECK(lvl) 0
60164 +#endif
60165 +
60166 +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
60167 +
60168 +#endif /*HTC_DEBUG_H_*/
60169 --- /dev/null
60170 +++ b/drivers/ar6000/htc/htc_internal.h
60171 @@ -0,0 +1,168 @@
60172 +/*
60173 + *
60174 + * Copyright (c) 2007 Atheros Communications Inc.
60175 + * All rights reserved.
60176 + *
60177 + *
60178 + *  This program is free software; you can redistribute it and/or modify
60179 + *  it under the terms of the GNU General Public License version 2 as
60180 + *  published by the Free Software Foundation;
60181 + *
60182 + *  Software distributed under the License is distributed on an "AS
60183 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
60184 + *  implied. See the License for the specific language governing
60185 + *  rights and limitations under the License.
60186 + *
60187 + *
60188 + *
60189 + */
60190 +
60191 +#ifndef _HTC_INTERNAL_H_
60192 +#define _HTC_INTERNAL_H_
60193 +
60194 +/* for debugging, uncomment this to capture the last frame header, on frame header
60195 + * processing errors, the last frame header is dump for comparison */
60196 +//#define HTC_CAPTURE_LAST_FRAME
60197 +
60198 +//#define HTC_EP_STAT_PROFILING
60199 +
60200 +#ifdef __cplusplus
60201 +extern "C" {
60202 +#endif /* __cplusplus */
60203 +
60204 +/* Header files */
60205 +#include "a_config.h"
60206 +#include "athdefs.h"
60207 +#include "a_types.h"
60208 +#include "a_osapi.h"
60209 +#include "a_debug.h"
60210 +#include "htc.h"
60211 +#include "htc_api.h"
60212 +#include "bmi_msg.h"
60213 +#include "hif.h"
60214 +#include "ar6k.h"
60215 +
60216 +/* HTC operational parameters */
60217 +#define HTC_TARGET_RESPONSE_TIMEOUT        2000 /* in ms */
60218 +#define HTC_TARGET_DEBUG_INTR_MASK         0x01
60219 +#define HTC_TARGET_CREDIT_INTR_MASK        0xF0
60220 +
60221 +typedef struct _HTC_ENDPOINT {
60222 +    HTC_SERVICE_ID              ServiceID;      /* service ID this endpoint is bound to
60223 +                                                   non-zero value means this endpoint is in use */
60224 +    HTC_PACKET_QUEUE            TxQueue;        /* HTC frame buffer TX queue */
60225 +    HTC_PACKET_QUEUE            RxBuffers;      /* HTC frame buffer RX list */
60226 +    HTC_ENDPOINT_CREDIT_DIST    CreditDist;     /* credit distribution structure (exposed to driver layer) */
60227 +    HTC_EP_CALLBACKS            EpCallBacks;    /* callbacks associated with this endpoint */
60228 +    int                         MaxTxQueueDepth;   /* max depth of the TX queue before we need to
60229 +                                                      call driver's full handler */
60230 +    int                         CurrentTxQueueDepth; /* current TX queue depth */
60231 +    int                         MaxMsgLength;        /* max length of endpoint message */
60232 +#ifdef HTC_EP_STAT_PROFILING
60233 +    HTC_ENDPOINT_STATS          EndPointStats;  /* endpoint statistics */
60234 +#endif
60235 +} HTC_ENDPOINT;
60236 +
60237 +#ifdef HTC_EP_STAT_PROFILING
60238 +#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count);
60239 +#else
60240 +#define INC_HTC_EP_STAT(p,stat,count)
60241 +#endif
60242 +
60243 +#define HTC_SERVICE_TX_PACKET_TAG  HTC_TX_PACKET_TAG_INTERNAL
60244 +
60245 +#define NUM_CONTROL_BUFFERS     8
60246 +#define NUM_CONTROL_TX_BUFFERS  2
60247 +#define NUM_CONTROL_RX_BUFFERS  (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS)
60248 +
60249 +#define HTC_CONTROL_BUFFER_SIZE (HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH)
60250 +
60251 +typedef struct HTC_CONTROL_BUFFER {
60252 +    HTC_PACKET    HtcPacket;
60253 +    A_UINT8       Buffer[HTC_CONTROL_BUFFER_SIZE];
60254 +} HTC_CONTROL_BUFFER;
60255 +
60256 +/* our HTC target state */
60257 +typedef struct _HTC_TARGET {
60258 +    HTC_ENDPOINT                EndPoint[ENDPOINT_MAX];
60259 +    HTC_CONTROL_BUFFER          HTCControlBuffers[NUM_CONTROL_BUFFERS];
60260 +    HTC_ENDPOINT_CREDIT_DIST   *EpCreditDistributionListHead;
60261 +    HTC_PACKET_QUEUE            ControlBufferTXFreeList;
60262 +    HTC_PACKET_QUEUE            ControlBufferRXFreeList;
60263 +    HTC_CREDIT_DIST_CALLBACK    DistributeCredits;
60264 +    HTC_CREDIT_INIT_CALLBACK    InitCredits;
60265 +    void                       *pCredDistContext;
60266 +    int                         TargetCredits;
60267 +    int                         TargetCreditSize;
60268 +    A_MUTEX_T                   HTCLock;
60269 +    A_MUTEX_T                   HTCRxLock;
60270 +    A_MUTEX_T                   HTCTxLock;
60271 +    AR6K_DEVICE                 Device;         /* AR6K - specific state */
60272 +    A_UINT32                    HTCStateFlags;
60273 +    HTC_ENDPOINT_ID             EpWaitingForBuffers;
60274 +    A_BOOL                      TargetFailure;
60275 +    void                       *pInstanceContext;
60276 +#define HTC_STATE_WAIT_BUFFERS  (1 << 0)
60277 +#define HTC_STATE_STOPPING      (1 << 1)
60278 +#ifdef HTC_CAPTURE_LAST_FRAME
60279 +    HTC_FRAME_HDR               LastFrameHdr;  /* useful for debugging */
60280 +    A_UINT8                     LastTrailer[256];
60281 +    A_UINT8                     LastTrailerLength;
60282 +#endif
60283 +} HTC_TARGET;
60284 +
60285 +#define HTC_STOPPING(t) ((t)->HTCStateFlags & HTC_STATE_STOPPING)
60286 +#define LOCK_HTC(t)      A_MUTEX_LOCK(&(t)->HTCLock);
60287 +#define UNLOCK_HTC(t)    A_MUTEX_UNLOCK(&(t)->HTCLock);
60288 +#define LOCK_HTC_RX(t)   A_MUTEX_LOCK(&(t)->HTCRxLock);
60289 +#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock);
60290 +#define LOCK_HTC_TX(t)   A_MUTEX_LOCK(&(t)->HTCTxLock);
60291 +#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock);
60292 +
60293 +#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd))
60294 +#define HTC_RECYCLE_RX_PKT(target,p)                \
60295 +{                                                   \
60296 +    HTC_PACKET_RESET_RX(pPacket);                   \
60297 +    HTCAddReceivePkt((HTC_HANDLE)(target),(p));     \
60298 +}
60299 +
60300 +/* internal HTC functions */
60301 +void        HTCControlTxComplete(void *Context, HTC_PACKET *pPacket);
60302 +void        HTCControlRecv(void *Context, HTC_PACKET *pPacket);
60303 +A_STATUS    HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket);
60304 +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList);
60305 +void        HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList);
60306 +A_STATUS    HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 Flags);
60307 +A_STATUS    HTCIssueRecv(HTC_TARGET *target, HTC_PACKET *pPacket);
60308 +void        HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket);
60309 +A_STATUS    HTCRecvMessagePendingHandler(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc);
60310 +void        HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint);
60311 +A_STATUS    HTCSendSetupComplete(HTC_TARGET *target);
60312 +void        HTCFlushRecvBuffers(HTC_TARGET *target);
60313 +void        HTCFlushSendPkts(HTC_TARGET *target);
60314 +void        DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist);
60315 +void        DumpCreditDistStates(HTC_TARGET *target);
60316 +void           DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
60317 +
60318 +static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) {
60319 +    HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList);
60320 +    if (pPacket != NULL) {
60321 +            /* set payload pointer area with some headroom */
60322 +        pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH;
60323 +    }
60324 +    return pPacket;
60325 +}
60326 +
60327 +#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList)
60328 +#define HTC_ALLOC_CONTROL_RX(t)  HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList)
60329 +#define HTC_FREE_CONTROL_RX(t,p) \
60330 +{                                                                \
60331 +    HTC_PACKET_RESET_RX(p);                                      \
60332 +    HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \
60333 +}
60334 +
60335 +#ifdef __cplusplus
60336 +}
60337 +#endif
60338 +
60339 +#endif /* _HTC_INTERNAL_H_ */
60340 --- /dev/null
60341 +++ b/drivers/ar6000/htc/htc_recv.c
60342 @@ -0,0 +1,703 @@
60343 +/*
60344 + *
60345 + * Copyright (c) 2007 Atheros Communications Inc.
60346 + * All rights reserved.
60347 + *
60348 + *
60349 + *  This program is free software; you can redistribute it and/or modify
60350 + *  it under the terms of the GNU General Public License version 2 as
60351 + *  published by the Free Software Foundation;
60352 + *
60353 + *  Software distributed under the License is distributed on an "AS
60354 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
60355 + *  implied. See the License for the specific language governing
60356 + *  rights and limitations under the License.
60357 + *
60358 + *
60359 + *
60360 + */
60361 +
60362 +#include "htc_internal.h"
60363 +
60364 +#define HTCIssueRecv(t, p) \
60365 +    DevRecvPacket(&(t)->Device,  \
60366 +                  (p),          \
60367 +                  (p)->ActualLength)
60368 +
60369 +#define DO_RCV_COMPLETION(t,p,e)            \
60370 +{                                           \
60371 +    if ((p)->ActualLength > 0) {            \
60372 +        AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" completing packet 0x%X (%d bytes) on ep : %d \n", \
60373 +            (A_UINT32)(p), (p)->ActualLength, (p)->Endpoint));  \
60374 +        (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext,      \
60375 +                                (p));                           \
60376 +    } else {                                                    \
60377 +        AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" recycling empty packet \n"));  \
60378 +        HTC_RECYCLE_RX_PKT((t), (p));                           \
60379 +    }                                                           \
60380 +}
60381 +
60382 +#ifdef HTC_EP_STAT_PROFILING
60383 +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead)            \
60384 +{                                                      \
60385 +    LOCK_HTC_RX((t));                                  \
60386 +    INC_HTC_EP_STAT((ep), RxReceived, 1);              \
60387 +    if ((lookAhead) != 0) {                            \
60388 +        INC_HTC_EP_STAT((ep), RxLookAheads, 1);        \
60389 +    }                                                  \
60390 +    UNLOCK_HTC_RX((t));                                \
60391 +}
60392 +#else
60393 +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead)
60394 +#endif
60395 +
60396 +static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target,
60397 +                                         A_UINT8    *pBuffer,
60398 +                                         int         Length,
60399 +                                         A_UINT32   *pNextLookAhead,
60400 +                                         HTC_ENDPOINT_ID FromEndpoint)
60401 +{
60402 +    HTC_RECORD_HDR          *pRecord;
60403 +    A_UINT8                 *pRecordBuf;
60404 +    HTC_LOOKAHEAD_REPORT    *pLookAhead;
60405 +    A_UINT8                 *pOrigBuffer;
60406 +    int                     origLength;
60407 +    A_STATUS                status;
60408 +
60409 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length));
60410 +
60411 +    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
60412 +        AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer");
60413 +    }
60414 +
60415 +    pOrigBuffer = pBuffer;
60416 +    origLength = Length;
60417 +    status = A_OK;
60418 +
60419 +    while (Length > 0) {
60420 +
60421 +        if (Length < sizeof(HTC_RECORD_HDR)) {
60422 +            status = A_EPROTO;
60423 +            break;
60424 +        }
60425 +            /* these are byte aligned structs */
60426 +        pRecord = (HTC_RECORD_HDR *)pBuffer;
60427 +        Length -= sizeof(HTC_RECORD_HDR);
60428 +        pBuffer += sizeof(HTC_RECORD_HDR);
60429 +
60430 +        if (pRecord->Length > Length) {
60431 +                /* no room left in buffer for record */
60432 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
60433 +                (" invalid record length: %d (id:%d) buffer has: %d bytes left \n",
60434 +                        pRecord->Length, pRecord->RecordID, Length));
60435 +            status = A_EPROTO;
60436 +            break;
60437 +        }
60438 +            /* start of record follows the header */
60439 +        pRecordBuf = pBuffer;
60440 +
60441 +        switch (pRecord->RecordID) {
60442 +            case HTC_RECORD_CREDITS:
60443 +                AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT));
60444 +                HTCProcessCreditRpt(target,
60445 +                                    (HTC_CREDIT_REPORT *)pRecordBuf,
60446 +                                    pRecord->Length / (sizeof(HTC_CREDIT_REPORT)),
60447 +                                    FromEndpoint);
60448 +                break;
60449 +            case HTC_RECORD_LOOKAHEAD:
60450 +                AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT));
60451 +                pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf;
60452 +                if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) &&
60453 +                    (pNextLookAhead != NULL)) {
60454 +
60455 +                    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
60456 +                                (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n",
60457 +                                pLookAhead->PreValid,
60458 +                                pLookAhead->PostValid));
60459 +
60460 +                        /* look ahead bytes are valid, copy them over */
60461 +                    ((A_UINT8 *)pNextLookAhead)[0] = pLookAhead->LookAhead[0];
60462 +                    ((A_UINT8 *)pNextLookAhead)[1] = pLookAhead->LookAhead[1];
60463 +                    ((A_UINT8 *)pNextLookAhead)[2] = pLookAhead->LookAhead[2];
60464 +                    ((A_UINT8 *)pNextLookAhead)[3] = pLookAhead->LookAhead[3];
60465 +
60466 +                    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
60467 +                        DebugDumpBytes((A_UINT8 *)pNextLookAhead,4,"Next Look Ahead");
60468 +                    }
60469 +                }
60470 +                break;
60471 +            default:
60472 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n",
60473 +                        pRecord->RecordID, pRecord->Length));
60474 +                break;
60475 +        }
60476 +
60477 +        if (A_FAILED(status)) {
60478 +            break;
60479 +        }
60480 +
60481 +            /* advance buffer past this record for next time around */
60482 +        pBuffer += pRecord->Length;
60483 +        Length -= pRecord->Length;
60484 +    }
60485 +
60486 +    if (A_FAILED(status)) {
60487 +        DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer");
60488 +    }
60489 +
60490 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n"));
60491 +    return status;
60492 +
60493 +}
60494 +
60495 +/* process a received message (i.e. strip off header, process any trailer data)
60496 + * note : locks must be released when this function is called */
60497 +static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT32 *pNextLookAhead)
60498 +{
60499 +    A_UINT8   temp;
60500 +    A_UINT8   *pBuf;
60501 +    A_STATUS  status = A_OK;
60502 +    A_UINT16  payloadLen;
60503 +    A_UINT32  lookAhead;
60504 +
60505 +    pBuf = pPacket->pBuffer;
60506 +
60507 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n"));
60508 +
60509 +    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
60510 +        AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT");
60511 +    }
60512 +
60513 +    do {
60514 +        /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to
60515 +         * retrieve 16 bit fields */
60516 +        payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen);
60517 +
60518 +        ((A_UINT8 *)&lookAhead)[0] = pBuf[0];
60519 +        ((A_UINT8 *)&lookAhead)[1] = pBuf[1];
60520 +        ((A_UINT8 *)&lookAhead)[2] = pBuf[2];
60521 +        ((A_UINT8 *)&lookAhead)[3] = pBuf[3];
60522 +
60523 +        if (lookAhead != pPacket->HTCReserved) {
60524 +            /* somehow the lookahead that gave us the full read length did not
60525 +             * reflect the actual header in the pending message */
60526 +             AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
60527 +                    ("HTCProcessRecvHeader, lookahead mismatch! \n"));
60528 +             DebugDumpBytes((A_UINT8 *)&pPacket->HTCReserved,4,"Expected Message LookAhead");
60529 +             DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header");
60530 +#ifdef HTC_CAPTURE_LAST_FRAME
60531 +            DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header");
60532 +            if (target->LastTrailerLength != 0) {
60533 +                DebugDumpBytes(target->LastTrailer,
60534 +                               target->LastTrailerLength,
60535 +                               "Last trailer");
60536 +            }
60537 +#endif
60538 +            status = A_EPROTO;
60539 +            break;
60540 +        }
60541 +
60542 +            /* get flags */
60543 +        temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags);
60544 +
60545 +        if (temp & HTC_FLAGS_RECV_TRAILER) {
60546 +            /* this packet has a trailer */
60547 +
60548 +                /* extract the trailer length in control byte 0 */
60549 +            temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]);
60550 +
60551 +            if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) {
60552 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
60553 +                    ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n",
60554 +                        payloadLen, temp));
60555 +                status = A_EPROTO;
60556 +                break;
60557 +            }
60558 +
60559 +                /* process trailer data that follows HDR + application payload */
60560 +            status = HTCProcessTrailer(target,
60561 +                                       (pBuf + HTC_HDR_LENGTH + payloadLen - temp),
60562 +                                       temp,
60563 +                                       pNextLookAhead,
60564 +                                       pPacket->Endpoint);
60565 +
60566 +            if (A_FAILED(status)) {
60567 +                break;
60568 +            }
60569 +
60570 +#ifdef HTC_CAPTURE_LAST_FRAME
60571 +            A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp);
60572 +            target->LastTrailerLength = temp;
60573 +#endif
60574 +                /* trim length by trailer bytes */
60575 +            pPacket->ActualLength -= temp;
60576 +        }
60577 +#ifdef HTC_CAPTURE_LAST_FRAME
60578 +         else {
60579 +            target->LastTrailerLength = 0;
60580 +        }
60581 +#endif
60582 +
60583 +            /* if we get to this point, the packet is good */
60584 +            /* remove header and adjust length */
60585 +        pPacket->pBuffer += HTC_HDR_LENGTH;
60586 +        pPacket->ActualLength -= HTC_HDR_LENGTH;
60587 +
60588 +    } while (FALSE);
60589 +
60590 +    if (A_FAILED(status)) {
60591 +            /* dump the whole packet */
60592 +        DebugDumpBytes(pBuf,pPacket->ActualLength,"BAD HTC Recv PKT");
60593 +    } else {
60594 +#ifdef HTC_CAPTURE_LAST_FRAME
60595 +        A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR));
60596 +#endif
60597 +        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
60598 +            if (pPacket->ActualLength > 0) {
60599 +                AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg");
60600 +            }
60601 +        }
60602 +    }
60603 +
60604 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n"));
60605 +    return status;
60606 +}
60607 +
60608 +/* asynchronous completion handler for recv packet fetching, when the device layer
60609 + * completes a read request, it will call this completion handler */
60610 +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket)
60611 +{
60612 +    HTC_TARGET      *target = (HTC_TARGET *)Context;
60613 +    HTC_ENDPOINT    *pEndpoint;
60614 +    A_UINT32        nextLookAhead = 0;
60615 +    A_STATUS        status;
60616 +
60617 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (status:%d, ep:%d) \n",
60618 +                pPacket->Status, pPacket->Endpoint));
60619 +
60620 +    AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
60621 +    pEndpoint = &target->EndPoint[pPacket->Endpoint];
60622 +    pPacket->Completion = NULL;
60623 +
60624 +        /* get completion status */
60625 +    status = pPacket->Status;
60626 +
60627 +    do {
60628 +        if (A_FAILED(status)) {
60629 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n",
60630 +                pPacket->Status, pPacket->Endpoint));
60631 +            break;
60632 +        }
60633 +            /* process the header for any trailer data */
60634 +        status = HTCProcessRecvHeader(target,pPacket,&nextLookAhead);
60635 +
60636 +        if (A_FAILED(status)) {
60637 +            break;
60638 +        }
60639 +            /* was there a lookahead for the next packet? */
60640 +        if (nextLookAhead != 0) {
60641 +            A_STATUS nextStatus;
60642 +            AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
60643 +                            ("HTCRecvCompleteHandler - next look ahead was non-zero : 0x%X \n",
60644 +                             nextLookAhead));
60645 +                /* we have another packet, get the next packet fetch started (pipelined) before
60646 +                 * we call into the endpoint's callback, this will start another async request */
60647 +            nextStatus = HTCRecvMessagePendingHandler(target,nextLookAhead,NULL);
60648 +            if (A_EPROTO == nextStatus) {
60649 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
60650 +                            ("Next look ahead from recv header was INVALID\n"));
60651 +                DebugDumpBytes((A_UINT8 *)&nextLookAhead,
60652 +                                4,
60653 +                                "BAD lookahead from lookahead report");
60654 +            }
60655 +        } else {
60656 +             AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
60657 +            ("HTCRecvCompleteHandler - rechecking for more messages...\n"));
60658 +            /* if we did not get anything on the look-ahead,
60659 +             * call device layer to asynchronously re-check for messages. If we can keep the async
60660 +             * processing going we get better performance.  If there is a pending message we will keep processing
60661 +             * messages asynchronously which should pipeline things nicely */
60662 +            DevCheckPendingRecvMsgsAsync(&target->Device);
60663 +        }
60664 +
60665 +        HTC_RX_STAT_PROFILE(target,pEndpoint,nextLookAhead);
60666 +        DO_RCV_COMPLETION(target,pPacket,pEndpoint);
60667 +
60668 +    } while (FALSE);
60669 +
60670 +    if (A_FAILED(status)) {
60671 +         AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
60672 +                         ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n",
60673 +                         status));
60674 +            /* recyle this packet */
60675 +         HTC_RECYCLE_RX_PKT(target, pPacket);
60676 +    }
60677 +
60678 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n"));
60679 +}
60680 +
60681 +/* synchronously wait for a control message from the target,
60682 + * This function is used at initialization time ONLY.  At init messages
60683 + * on ENDPOINT 0 are expected. */
60684 +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket)
60685 +{
60686 +    A_STATUS        status;
60687 +    A_UINT32        lookAhead;
60688 +    HTC_PACKET      *pPacket = NULL;
60689 +    HTC_FRAME_HDR   *pHdr;
60690 +
60691 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n"));
60692 +
60693 +    do  {
60694 +
60695 +        *ppControlPacket = NULL;
60696 +
60697 +            /* call the polling function to see if we have a message */
60698 +        status = DevPollMboxMsgRecv(&target->Device,
60699 +                                    &lookAhead,
60700 +                                    HTC_TARGET_RESPONSE_TIMEOUT);
60701 +
60702 +        if (A_FAILED(status)) {
60703 +            break;
60704 +        }
60705 +
60706 +        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
60707 +                ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead));
60708 +
60709 +            /* check the lookahead */
60710 +        pHdr = (HTC_FRAME_HDR *)&lookAhead;
60711 +
60712 +        if (pHdr->EndpointID != ENDPOINT_0) {
60713 +                /* unexpected endpoint number, should be zero */
60714 +            AR_DEBUG_ASSERT(FALSE);
60715 +            status = A_EPROTO;
60716 +            break;
60717 +        }
60718 +
60719 +        if (A_FAILED(status)) {
60720 +                /* bad message */
60721 +            AR_DEBUG_ASSERT(FALSE);
60722 +            status = A_EPROTO;
60723 +            break;
60724 +        }
60725 +
60726 +        pPacket = HTC_ALLOC_CONTROL_RX(target);
60727 +
60728 +        if (pPacket == NULL) {
60729 +            AR_DEBUG_ASSERT(FALSE);
60730 +            status = A_NO_MEMORY;
60731 +            break;
60732 +        }
60733 +
60734 +        pPacket->HTCReserved = lookAhead;
60735 +        pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
60736 +
60737 +        if (pPacket->ActualLength > pPacket->BufferLength) {
60738 +            AR_DEBUG_ASSERT(FALSE);
60739 +            status = A_EPROTO;
60740 +            break;
60741 +        }
60742 +
60743 +            /* we want synchronous operation */
60744 +        pPacket->Completion = NULL;
60745 +
60746 +            /* get the message from the device, this will block */
60747 +        status = HTCIssueRecv(target, pPacket);
60748 +
60749 +        if (A_FAILED(status)) {
60750 +            break;
60751 +        }
60752 +
60753 +            /* process receive header */
60754 +        status = HTCProcessRecvHeader(target,pPacket,NULL);
60755 +
60756 +        pPacket->Status = status;
60757 +
60758 +        if (A_FAILED(status)) {
60759 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
60760 +                    ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n",
60761 +                     status));
60762 +            break;
60763 +        }
60764 +
60765 +            /* give the caller this control message packet, they are responsible to free */
60766 +        *ppControlPacket = pPacket;
60767 +
60768 +    } while (FALSE);
60769 +
60770 +    if (A_FAILED(status)) {
60771 +        if (pPacket != NULL) {
60772 +                /* cleanup buffer on error */
60773 +            HTC_FREE_CONTROL_RX(target,pPacket);
60774 +        }
60775 +    }
60776 +
60777 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n"));
60778 +
60779 +    return status;
60780 +}
60781 +
60782 +/* callback when device layer or lookahead report parsing detects a pending message */
60783 +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc)
60784 +{
60785 +    HTC_TARGET      *target = (HTC_TARGET *)Context;
60786 +    A_STATUS         status = A_OK;
60787 +    HTC_PACKET      *pPacket = NULL;
60788 +    HTC_FRAME_HDR   *pHdr;
60789 +    HTC_ENDPOINT    *pEndpoint;
60790 +    A_BOOL          asyncProc = FALSE;
60791 +
60792 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler LookAhead:0x%X \n",LookAhead));
60793 +
60794 +    if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) {
60795 +            /* We use async mode to get the packets if the device layer supports it.
60796 +             * The device layer interfaces with HIF in which HIF may have restrictions on
60797 +             * how interrupts are processed */
60798 +        asyncProc = TRUE;
60799 +    }
60800 +
60801 +    if (pAsyncProc != NULL) {
60802 +            /* indicate to caller how we decided to process this */
60803 +        *pAsyncProc = asyncProc;
60804 +    }
60805 +
60806 +    while (TRUE) {
60807 +
60808 +        pHdr = (HTC_FRAME_HDR *)&LookAhead;
60809 +
60810 +        if (pHdr->EndpointID >= ENDPOINT_MAX) {
60811 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID));
60812 +                /* invalid endpoint */
60813 +            status = A_EPROTO;
60814 +            break;
60815 +        }
60816 +
60817 +        if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) {
60818 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n",
60819 +                    pHdr->PayloadLen, HTC_MAX_PAYLOAD_LENGTH));
60820 +            status = A_EPROTO;
60821 +            break;
60822 +        }
60823 +
60824 +        pEndpoint = &target->EndPoint[pHdr->EndpointID];
60825 +
60826 +        if (0 == pEndpoint->ServiceID) {
60827 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID));
60828 +                /* endpoint isn't even connected */
60829 +            status = A_EPROTO;
60830 +            break;
60831 +        }
60832 +
60833 +            /* lock RX to get a buffer */
60834 +        LOCK_HTC_RX(target);
60835 +
60836 +            /* get a packet from the endpoint recv queue */
60837 +        pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
60838 +
60839 +        if (NULL == pPacket) {
60840 +                /* check for refill handler */
60841 +            if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) {
60842 +                UNLOCK_HTC_RX(target);
60843 +                    /* call the re-fill handler */
60844 +                pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext,
60845 +                                                    pHdr->EndpointID);
60846 +                LOCK_HTC_RX(target);
60847 +                    /* check if we have more buffers */
60848 +                pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
60849 +                    /* fall through */
60850 +            }
60851 +        }
60852 +
60853 +        if (NULL == pPacket) {
60854 +                /* this is not an error, we simply need to mark that we are waiting for buffers.*/
60855 +            target->HTCStateFlags |= HTC_STATE_WAIT_BUFFERS;
60856 +            target->EpWaitingForBuffers = pHdr->EndpointID;
60857 +            status = A_NO_MEMORY;
60858 +        }
60859 +
60860 +        UNLOCK_HTC_RX(target);
60861 +
60862 +        if (A_FAILED(status)) {
60863 +                /* no buffers */
60864 +            break;
60865 +        }
60866 +
60867 +        AR_DEBUG_ASSERT(pPacket->Endpoint == pHdr->EndpointID);
60868 +
60869 +            /* make sure this message can fit in the endpoint buffer */
60870 +        if ((pHdr->PayloadLen + HTC_HDR_LENGTH) > pPacket->BufferLength) {
60871 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
60872 +                    ("Payload Length Error : header reports payload of: %d, endpoint buffer size: %d \n",
60873 +                    pHdr->PayloadLen, pPacket->BufferLength));
60874 +            status = A_EPROTO;
60875 +            break;
60876 +        }
60877 +
60878 +        pPacket->HTCReserved = LookAhead; /* set expected look ahead */
60879 +            /* set the amount of data to fetch */
60880 +        pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
60881 +
60882 +        if (asyncProc) {
60883 +                /* we use async mode to get the packet if the device layer supports it
60884 +                 * set our callback and context */
60885 +            pPacket->Completion = HTCRecvCompleteHandler;
60886 +            pPacket->pContext = target;
60887 +        } else {
60888 +                /* fully synchronous */
60889 +            pPacket->Completion = NULL;
60890 +        }
60891 +
60892 +            /* go fetch the packet */
60893 +        status = HTCIssueRecv(target, pPacket);
60894 +
60895 +        if (A_FAILED(status)) {
60896 +            break;
60897 +        }
60898 +
60899 +        if (asyncProc) {
60900 +                /* we did this asynchronously so we can get out of the loop, the asynch processing
60901 +                 * creates a chain of requests to continue processing pending messages in the
60902 +                 * context of callbacks  */
60903 +            break;
60904 +        }
60905 +
60906 +            /* in the sync case, we process the packet, check lookaheads and then repeat */
60907 +
60908 +        LookAhead = 0;
60909 +        status = HTCProcessRecvHeader(target,pPacket,&LookAhead);
60910 +
60911 +        if (A_FAILED(status)) {
60912 +            break;
60913 +        }
60914 +
60915 +        HTC_RX_STAT_PROFILE(target,pEndpoint,LookAhead);
60916 +        DO_RCV_COMPLETION(target,pPacket,pEndpoint);
60917 +
60918 +        pPacket = NULL;
60919 +
60920 +        if (0 == LookAhead) {
60921 +            break;
60922 +        }
60923 +
60924 +    }
60925 +
60926 +    if (A_NO_MEMORY == status) {
60927 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
60928 +                (" Endpoint :%d has no buffers, blocking receiver to prevent overrun.. \n",
60929 +                pHdr->EndpointID));
60930 +            /* try to stop receive at the device layer */
60931 +        DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC);
60932 +        status = A_OK;
60933 +    } else if (A_FAILED(status)) {
60934 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
60935 +                        ("Failed to get pending message : LookAhead Value: 0x%X (status = %d) \n",
60936 +                        LookAhead, status));
60937 +        if (pPacket != NULL) {
60938 +                /* clean up packet on error */
60939 +            HTC_RECYCLE_RX_PKT(target, pPacket);
60940 +        }
60941 +    }
60942 +
60943 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n"));
60944 +
60945 +    return status;
60946 +}
60947 +
60948 +/* Makes a buffer available to the HTC module */
60949 +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
60950 +{
60951 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
60952 +    HTC_ENDPOINT *pEndpoint;
60953 +    A_BOOL       unblockRecv = FALSE;
60954 +    A_STATUS     status = A_OK;
60955 +
60956 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
60957 +                    ("+- HTCAddReceivePkt: endPointId: %d, buffer: 0x%X, length: %d\n",
60958 +                    pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->BufferLength));
60959 +
60960 +    do {
60961 +
60962 +        if (HTC_STOPPING(target)) {
60963 +            status = A_ECANCELED;
60964 +            break;
60965 +        }
60966 +
60967 +        AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
60968 +
60969 +        pEndpoint = &target->EndPoint[pPacket->Endpoint];
60970 +
60971 +        LOCK_HTC_RX(target);
60972 +
60973 +            /* store receive packet */
60974 +        HTC_PACKET_ENQUEUE(&pEndpoint->RxBuffers, pPacket);
60975 +
60976 +            /* check if we are blocked waiting for a new buffer */
60977 +        if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) {
60978 +            if (target->EpWaitingForBuffers == pPacket->Endpoint) {
60979 +                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n",
60980 +                    target->EpWaitingForBuffers));
60981 +                target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS;
60982 +                target->EpWaitingForBuffers = ENDPOINT_MAX;
60983 +                unblockRecv = TRUE;
60984 +            }
60985 +        }
60986 +
60987 +        UNLOCK_HTC_RX(target);
60988 +
60989 +        if (unblockRecv && !HTC_STOPPING(target)) {
60990 +                /* TODO : implement a buffer threshold count? */
60991 +            DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
60992 +        }
60993 +
60994 +    } while (FALSE);
60995 +
60996 +    return status;
60997 +}
60998 +
60999 +static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint)
61000 +{
61001 +    HTC_PACKET  *pPacket;
61002 +
61003 +    LOCK_HTC_RX(target);
61004 +
61005 +    while (1) {
61006 +        pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
61007 +        if (NULL == pPacket) {
61008 +            break;
61009 +        }
61010 +        UNLOCK_HTC_RX(target);
61011 +        pPacket->Status = A_ECANCELED;
61012 +        pPacket->ActualLength = 0;
61013 +        AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("  Flushing RX packet:0x%X, length:%d, ep:%d \n",
61014 +                (A_UINT32)pPacket, pPacket->BufferLength, pPacket->Endpoint));
61015 +            /* give the packet back */
61016 +        pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext,
61017 +                                      pPacket);
61018 +        LOCK_HTC_RX(target);
61019 +    }
61020 +
61021 +    UNLOCK_HTC_RX(target);
61022 +
61023 +
61024 +}
61025 +
61026 +void HTCFlushRecvBuffers(HTC_TARGET *target)
61027 +{
61028 +    HTC_ENDPOINT    *pEndpoint;
61029 +    int             i;
61030 +
61031 +        /* NOTE: no need to flush endpoint 0, these buffers were
61032 +         * allocated as part of the HTC struct */
61033 +    for (i = ENDPOINT_1; i < ENDPOINT_MAX; i++) {
61034 +        pEndpoint = &target->EndPoint[i];
61035 +        if (pEndpoint->ServiceID == 0) {
61036 +                /* not in use.. */
61037 +            continue;
61038 +        }
61039 +        HTCFlushEndpointRX(target,pEndpoint);
61040 +    }
61041 +
61042 +
61043 +}
61044 +
61045 +
61046 --- /dev/null
61047 +++ b/drivers/ar6000/htc/htc_send.c
61048 @@ -0,0 +1,543 @@
61049 +/*
61050 + *
61051 + * Copyright (c) 2007 Atheros Communications Inc.
61052 + * All rights reserved.
61053 + *
61054 + *
61055 + *  This program is free software; you can redistribute it and/or modify
61056 + *  it under the terms of the GNU General Public License version 2 as
61057 + *  published by the Free Software Foundation;
61058 + *
61059 + *  Software distributed under the License is distributed on an "AS
61060 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
61061 + *  implied. See the License for the specific language governing
61062 + *  rights and limitations under the License.
61063 + *
61064 + *
61065 + *
61066 + */
61067 +
61068 +#include "htc_internal.h"
61069 +
61070 +#define DO_EP_TX_COMPLETION(ep,p)                                    \
61071 +{                                                                    \
61072 +    (p)->Completion = NULL;                                          \
61073 +    (ep)->EpCallBacks.EpTxComplete((ep)->EpCallBacks.pContext,(p));  \
61074 +}
61075 +
61076 +
61077 +/* call the distribute credits callback with the distribution */
61078 +#define DO_DISTRIBUTION(t,reason,description,pList) \
61079 +{                                             \
61080 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,           \
61081 +        ("  calling distribute function (%s) (dfn:0x%X, ctxt:0x%X, dist:0x%X) \n", \
61082 +                (description),                                           \
61083 +                (A_UINT32)(t)->DistributeCredits,                        \
61084 +                (A_UINT32)(t)->pCredDistContext,                         \
61085 +                (A_UINT32)pList));                                       \
61086 +    (t)->DistributeCredits((t)->pCredDistContext,                        \
61087 +                           (pList),                                      \
61088 +                           (reason));                                    \
61089 +}
61090 +
61091 +/* our internal send packet completion handler when packets are submited to the AR6K device
61092 + * layer */
61093 +static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket)
61094 +{
61095 +    HTC_TARGET      *target = (HTC_TARGET *)Context;
61096 +    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[pPacket->Endpoint];
61097 +
61098 +
61099 +    if (A_FAILED(pPacket->Status)) {
61100 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61101 +            ("HTCSendPktCompletionHandler: request failed (status:%d, ep:%d) \n",
61102 +                pPacket->Status, pPacket->Endpoint));
61103 +    }
61104 +        /* first, fixup the head room we allocated */
61105 +    pPacket->pBuffer += HTC_HDR_LENGTH;
61106 +        /* do completion */
61107 +    DO_EP_TX_COMPLETION(pEndpoint,pPacket);
61108 +}
61109 +
61110 +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 SendFlags)
61111 +{
61112 +    A_STATUS status;
61113 +    A_UINT8 *pHdrBuf;
61114 +    A_BOOL   sync = FALSE;
61115 +
61116 +        /* caller always provides headrooom */
61117 +    pPacket->pBuffer -= HTC_HDR_LENGTH;
61118 +    pHdrBuf = pPacket->pBuffer;
61119 +        /* setup frame header */
61120 +    A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)pPacket->ActualLength);
61121 +    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,SendFlags);
61122 +    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)pPacket->Endpoint);
61123 +
61124 +    if (pPacket->Completion == NULL) {
61125 +            /* mark that this request was synchronously issued */
61126 +        sync = TRUE;
61127 +    }
61128 +
61129 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
61130 +                    ("+-HTCIssueSend: transmit length : %d (%s) \n",
61131 +                    pPacket->ActualLength + HTC_HDR_LENGTH,
61132 +                    sync ? "SYNC" : "ASYNC" ));
61133 +
61134 +        /* send message to device */
61135 +    status = DevSendPacket(&target->Device,
61136 +                           pPacket,
61137 +                           pPacket->ActualLength + HTC_HDR_LENGTH);
61138 +
61139 +    if (sync) {
61140 +            /* use local sync variable.  If this was issued asynchronously, pPacket is no longer
61141 +             * safe to access. */
61142 +        pPacket->pBuffer += HTC_HDR_LENGTH;
61143 +    }
61144 +
61145 +    /* if this request was asynchronous, the packet completion routine will be invoked by
61146 +     * the device layer when the HIF layer completes the request */
61147 +
61148 +    return status;
61149 +}
61150 +
61151 +/* try to send the current packet or a packet at the head of the TX queue,
61152 + * if there are no credits, the packet remains in the queue.
61153 + * this function always succeeds and returns a flag if the TX queue for
61154 + * the endpoint has hit the set limit */
61155 +static A_BOOL HTCTrySend(HTC_TARGET   *target,
61156 +                         HTC_ENDPOINT *pEndpoint,
61157 +                         HTC_PACKET   *pPacketToSend)
61158 +{
61159 +    HTC_PACKET  *pPacket;
61160 +    int         creditsRequired;
61161 +    int         remainder;
61162 +    A_UINT8     sendFlags;
61163 +    A_BOOL      epFull = FALSE;
61164 +
61165 +    LOCK_HTC_TX(target);
61166 +
61167 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (pPkt:0x%X)\n",(A_UINT32)pPacketToSend));
61168 +
61169 +    if (pPacketToSend != NULL) {
61170 +        /* caller supplied us a packet to queue to the tail of the HTC TX queue before
61171 +         * we check the tx queue */
61172 +        HTC_PACKET_ENQUEUE(&pEndpoint->TxQueue,pPacketToSend);
61173 +        pEndpoint->CurrentTxQueueDepth++;
61174 +    }
61175 +
61176 +        /* now drain the TX queue for transmission as long as we have enough
61177 +         * credits */
61178 +
61179 +    while (1) {
61180 +
61181 +        if (HTC_QUEUE_EMPTY(&pEndpoint->TxQueue)) {
61182 +                /* nothing in the queue */
61183 +            break;
61184 +        }
61185 +
61186 +        sendFlags = 0;
61187 +
61188 +            /* get packet at head, but don't remove it */
61189 +        pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue);
61190 +        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%X , Queue Depth: %d\n",
61191 +                (A_UINT32)pPacket, pEndpoint->CurrentTxQueueDepth));
61192 +
61193 +            /* figure out how many credits this message requires */
61194 +        creditsRequired = (pPacket->ActualLength + HTC_HDR_LENGTH) / target->TargetCreditSize;
61195 +        remainder = (pPacket->ActualLength + HTC_HDR_LENGTH) % target->TargetCreditSize;
61196 +
61197 +        if (remainder) {
61198 +            creditsRequired++;
61199 +        }
61200 +
61201 +        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d   Got:%d\n",
61202 +                            creditsRequired, pEndpoint->CreditDist.TxCredits));
61203 +
61204 +        if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
61205 +
61206 +            /* not enough credits */
61207 +
61208 +            if (pPacket->Endpoint == ENDPOINT_0) {
61209 +                    /* leave it in the queue */
61210 +                break;
61211 +            }
61212 +                /* invoke the registered distribution function only if this is not
61213 +                 * endpoint 0, we let the driver layer provide more credits if it can.
61214 +                 * We pass the credit distribution list starting at the endpoint in question
61215 +                 * */
61216 +
61217 +                /* set how many credits we need  */
61218 +            pEndpoint->CreditDist.TxCreditsSeek =
61219 +                                    creditsRequired - pEndpoint->CreditDist.TxCredits;
61220 +            DO_DISTRIBUTION(target,
61221 +                            HTC_CREDIT_DIST_SEEK_CREDITS,
61222 +                            "Seek Credits",
61223 +                            &pEndpoint->CreditDist);
61224 +
61225 +            pEndpoint->CreditDist.TxCreditsSeek = 0;
61226 +
61227 +            if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
61228 +                    /* still not enough credits to send, leave packet in the queue */
61229 +                AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
61230 +                    (" Not enough credits for ep %d leaving packet in queue..\n",
61231 +                    pPacket->Endpoint));
61232 +                break;
61233 +            }
61234 +
61235 +        }
61236 +
61237 +        pEndpoint->CreditDist.TxCredits -= creditsRequired;
61238 +        INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired);
61239 +
61240 +            /* check if we need credits */
61241 +        if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
61242 +            sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE;
61243 +            INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1);
61244 +            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits  \n"));
61245 +        }
61246 +
61247 +            /* now we can fully dequeue */
61248 +        pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue);
61249 +        pEndpoint->CurrentTxQueueDepth--;
61250 +
61251 +        INC_HTC_EP_STAT(pEndpoint, TxIssued, 1);
61252 +
61253 +        UNLOCK_HTC_TX(target);
61254 +
61255 +        HTCIssueSend(target, pPacket, sendFlags);
61256 +
61257 +        LOCK_HTC_TX(target);
61258 +
61259 +        /* go back and check for more messages */
61260 +    }
61261 +
61262 +    if (pEndpoint->CurrentTxQueueDepth >= pEndpoint->MaxTxQueueDepth) {
61263 +            /* let caller know that this endpoint has reached the maximum depth */
61264 +        epFull = TRUE;
61265 +    }
61266 +
61267 +    UNLOCK_HTC_TX(target);
61268 +
61269 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend:  \n"));
61270 +    return epFull;
61271 +}
61272 +
61273 +/* HTC API - HTCSendPkt */
61274 +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
61275 +{
61276 +    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
61277 +    HTC_ENDPOINT    *pEndpoint;
61278 +    HTC_ENDPOINT_ID ep;
61279 +    A_STATUS        status = A_OK;
61280 +
61281 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
61282 +                    ("+HTCSendPkt: Enter endPointId: %d, buffer: 0x%X, length: %d \n",
61283 +                    pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->ActualLength));
61284 +
61285 +    ep = pPacket->Endpoint;
61286 +    AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
61287 +    pEndpoint = &target->EndPoint[ep];
61288 +
61289 +    do {
61290 +
61291 +        if (HTC_STOPPING(target)) {
61292 +            status = A_ECANCELED;
61293 +            pPacket->Status = status;
61294 +            DO_EP_TX_COMPLETION(pEndpoint,pPacket);
61295 +            break;
61296 +        }
61297 +            /* everything sent through this interface is asynchronous */
61298 +            /* fill in HTC completion routines */
61299 +        pPacket->Completion = HTCSendPktCompletionHandler;
61300 +        pPacket->pContext = target;
61301 +
61302 +        if (HTCTrySend(target, pEndpoint, pPacket)) {
61303 +            AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX queue is full, Depth:%d, Max:%d \n",
61304 +                    ep, pEndpoint->CurrentTxQueueDepth, pEndpoint->MaxTxQueueDepth));
61305 +                /* queue is now full, let caller know */
61306 +            if (pEndpoint->EpCallBacks.EpSendFull != NULL) {
61307 +                AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Calling driver's send full callback.... \n"));
61308 +                pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext,
61309 +                                                  ep);
61310 +            }
61311 +        }
61312 +
61313 +        AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPkt \n"));
61314 +    } while (FALSE);
61315 +
61316 +    return status;
61317 +}
61318 +
61319 +
61320 +/* check TX queues to drain because of credit distribution update */
61321 +static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target)
61322 +{
61323 +    HTC_ENDPOINT                *pEndpoint;
61324 +    HTC_ENDPOINT_CREDIT_DIST    *pDistItem;
61325 +
61326 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n"));
61327 +    pDistItem = target->EpCreditDistributionListHead;
61328 +
61329 +        /* run through the credit distribution list to see
61330 +         * if there are packets queued
61331 +         * NOTE: no locks need to be taken since the distribution list
61332 +         * is not dynamic (cannot be re-ordered) and we are not modifying any state */
61333 +    while (pDistItem != NULL) {
61334 +        pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved;
61335 +
61336 +        if (pEndpoint->CurrentTxQueueDepth > 0) {
61337 +            AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n",
61338 +                    pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, pEndpoint->CurrentTxQueueDepth));
61339 +                /* try to start the stalled queue, this list is ordered by priority.
61340 +                 * Highest priority queue get's processed first, if there are credits available the
61341 +                 * highest priority queue will get a chance to reclaim credits from lower priority
61342 +                 * ones */
61343 +            HTCTrySend(target, pEndpoint, NULL);
61344 +        }
61345 +
61346 +        pDistItem = pDistItem->pNext;
61347 +    }
61348 +
61349 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n"));
61350 +}
61351 +
61352 +/* process credit reports and call distribution function */
61353 +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint)
61354 +{
61355 +    int             i;
61356 +    HTC_ENDPOINT    *pEndpoint;
61357 +    int             totalCredits = 0;
61358 +    A_BOOL          doDist = FALSE;
61359 +
61360 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries));
61361 +
61362 +        /* lock out TX while we update credits */
61363 +    LOCK_HTC_TX(target);
61364 +
61365 +    for (i = 0; i < NumEntries; i++, pRpt++) {
61366 +        if (pRpt->EndpointID >= ENDPOINT_MAX) {
61367 +            AR_DEBUG_ASSERT(FALSE);
61368 +            break;
61369 +        }
61370 +
61371 +        pEndpoint = &target->EndPoint[pRpt->EndpointID];
61372 +
61373 +        AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("  Endpoint %d got %d credits \n",
61374 +                pRpt->EndpointID, pRpt->Credits));
61375 +
61376 +
61377 +#ifdef HTC_EP_STAT_PROFILING
61378 +
61379 +        INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1);
61380 +        INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits);
61381 +
61382 +        if (FromEndpoint == pRpt->EndpointID) {
61383 +                /* this credit report arrived on the same endpoint indicating it arrived in an RX
61384 +                 * packet */
61385 +            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits);
61386 +            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1);
61387 +        } else if (FromEndpoint == ENDPOINT_0) {
61388 +                /* this credit arrived on endpoint 0 as a NULL message */
61389 +            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits);
61390 +            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1);
61391 +        } else {
61392 +                /* arrived on another endpoint */
61393 +            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits);
61394 +            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1);
61395 +        }
61396 +
61397 +#endif
61398 +
61399 +        if (ENDPOINT_0 == pRpt->EndpointID) {
61400 +                /* always give endpoint 0 credits back */
61401 +            pEndpoint->CreditDist.TxCredits += pRpt->Credits;
61402 +        } else {
61403 +                /* for all other endpoints, update credits to distribute, the distribution function
61404 +                 * will handle giving out credits back to the endpoints */
61405 +            pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits;
61406 +                /* flag that we have to do the distribution */
61407 +            doDist = TRUE;
61408 +        }
61409 +
61410 +        totalCredits += pRpt->Credits;
61411 +    }
61412 +
61413 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("  Report indicated %d credits to distribute \n", totalCredits));
61414 +
61415 +    if (doDist) {
61416 +            /* this was a credit return based on a completed send operations
61417 +             * note, this is done with the lock held */
61418 +        DO_DISTRIBUTION(target,
61419 +                        HTC_CREDIT_DIST_SEND_COMPLETE,
61420 +                        "Send Complete",
61421 +                        target->EpCreditDistributionListHead->pNext);
61422 +    }
61423 +
61424 +    UNLOCK_HTC_TX(target);
61425 +
61426 +    if (totalCredits) {
61427 +        HTCCheckEndpointTxQueues(target);
61428 +    }
61429 +
61430 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n"));
61431 +}
61432 +
61433 +/* flush endpoint TX queue */
61434 +static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag)
61435 +{
61436 +    HTC_PACKET          *pPacket;
61437 +    HTC_PACKET_QUEUE    discardQueue;
61438 +
61439 +        /* initialize the discard queue */
61440 +    INIT_HTC_PACKET_QUEUE(&discardQueue);
61441 +
61442 +    LOCK_HTC_TX(target);
61443 +
61444 +        /* interate from the front of the TX queue and flush out packets */
61445 +    ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue, pPacket, HTC_PACKET, ListLink) {
61446 +
61447 +            /* check for removal */
61448 +        if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) {
61449 +                /* remove from queue */
61450 +            HTC_PACKET_REMOVE(pPacket);
61451 +                /* add it to the discard pile */
61452 +            HTC_PACKET_ENQUEUE(&discardQueue, pPacket);
61453 +            pEndpoint->CurrentTxQueueDepth--;
61454 +        }
61455 +
61456 +    } ITERATE_END;
61457 +
61458 +    UNLOCK_HTC_TX(target);
61459 +
61460 +        /* empty the discard queue */
61461 +    while (1) {
61462 +        pPacket = HTC_PACKET_DEQUEUE(&discardQueue);
61463 +        if (NULL == pPacket) {
61464 +            break;
61465 +        }
61466 +        pPacket->Status = A_ECANCELED;
61467 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("  Flushing TX packet:0x%X, length:%d, ep:%d tag:0x%X \n",
61468 +                (A_UINT32)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag));
61469 +        DO_EP_TX_COMPLETION(pEndpoint,pPacket);
61470 +    }
61471 +
61472 +}
61473 +
61474 +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist)
61475 +{
61476 +#ifdef DEBUG
61477 +    HTC_ENDPOINT *pEndpoint = (HTC_ENDPOINT *)pEPDist->pHTCReserved;
61478 +#endif
61479 +
61480 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d  ServiceID: 0x%X    --------------\n",
61481 +                        pEPDist->Endpoint, pEPDist->ServiceID));
61482 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%X next:0x%X prev:0x%X\n",
61483 +                (A_UINT32)pEPDist, (A_UINT32)pEPDist->pNext, (A_UINT32)pEPDist->pPrev));
61484 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags          : 0x%X \n", pEPDist->DistFlags));
61485 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm      : %d \n", pEPDist->TxCreditsNorm));
61486 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin       : %d \n", pEPDist->TxCreditsMin));
61487 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits          : %d \n", pEPDist->TxCredits));
61488 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned  : %d \n", pEPDist->TxCreditsAssigned));
61489 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek      : %d \n", pEPDist->TxCreditsSeek));
61490 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize       : %d \n", pEPDist->TxCreditSize));
61491 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg));
61492 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist    : %d \n", pEPDist->TxCreditsToDist));
61493 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth       : %d \n", pEndpoint->CurrentTxQueueDepth));
61494 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n"));
61495 +}
61496 +
61497 +void DumpCreditDistStates(HTC_TARGET *target)
61498 +{
61499 +    HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead;
61500 +
61501 +    while (pEPList != NULL) {
61502 +        DumpCreditDist(pEPList);
61503 +        pEPList = pEPList->pNext;
61504 +    }
61505 +
61506 +    if (target->DistributeCredits != NULL) {
61507 +        DO_DISTRIBUTION(target,
61508 +                        HTC_DUMP_CREDIT_STATE,
61509 +                        "Dump State",
61510 +                        NULL);
61511 +    }
61512 +}
61513 +
61514 +/* flush all send packets from all endpoint queues */
61515 +void HTCFlushSendPkts(HTC_TARGET *target)
61516 +{
61517 +    HTC_ENDPOINT    *pEndpoint;
61518 +    int             i;
61519 +
61520 +    DumpCreditDistStates(target);
61521 +
61522 +    for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
61523 +        pEndpoint = &target->EndPoint[i];
61524 +        if (pEndpoint->ServiceID == 0) {
61525 +                /* not in use.. */
61526 +            continue;
61527 +        }
61528 +        HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL);
61529 +    }
61530 +
61531 +
61532 +}
61533 +
61534 +/* HTC API to flush an endpoint's TX queue*/
61535 +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag)
61536 +{
61537 +    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
61538 +    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[Endpoint];
61539 +
61540 +    if (pEndpoint->ServiceID == 0) {
61541 +        AR_DEBUG_ASSERT(FALSE);
61542 +        /* not in use.. */
61543 +        return;
61544 +    }
61545 +
61546 +    HTCFlushEndpointTX(target, pEndpoint, Tag);
61547 +}
61548 +
61549 +/* HTC API to indicate activity to the credit distribution function */
61550 +void HTCIndicateActivityChange(HTC_HANDLE      HTCHandle,
61551 +                               HTC_ENDPOINT_ID Endpoint,
61552 +                               A_BOOL          Active)
61553 +{
61554 +    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
61555 +    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[Endpoint];
61556 +    A_BOOL          doDist = FALSE;
61557 +
61558 +    if (pEndpoint->ServiceID == 0) {
61559 +        AR_DEBUG_ASSERT(FALSE);
61560 +        /* not in use.. */
61561 +        return;
61562 +    }
61563 +
61564 +    LOCK_HTC_TX(target);
61565 +
61566 +    if (Active) {
61567 +        if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) {
61568 +                /* mark active now */
61569 +            pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE;
61570 +            doDist = TRUE;
61571 +        }
61572 +    } else {
61573 +        if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) {
61574 +                /* mark inactive now */
61575 +            pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE;
61576 +            doDist = TRUE;
61577 +        }
61578 +    }
61579 +
61580 +    if (doDist) {
61581 +        /* do distribution again based on activity change
61582 +         * note, this is done with the lock held */
61583 +        DO_DISTRIBUTION(target,
61584 +                        HTC_CREDIT_DIST_ACTIVITY_CHANGE,
61585 +                        "Activity Change",
61586 +                        target->EpCreditDistributionListHead->pNext);
61587 +    }
61588 +
61589 +    UNLOCK_HTC_TX(target);
61590 +
61591 +}
61592 --- /dev/null
61593 +++ b/drivers/ar6000/htc/htc_services.c
61594 @@ -0,0 +1,403 @@
61595 +/*
61596 + *
61597 + * Copyright (c) 2007 Atheros Communications Inc.
61598 + * All rights reserved.
61599 + *
61600 + *
61601 + *  This program is free software; you can redistribute it and/or modify
61602 + *  it under the terms of the GNU General Public License version 2 as
61603 + *  published by the Free Software Foundation;
61604 + *
61605 + *  Software distributed under the License is distributed on an "AS
61606 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
61607 + *  implied. See the License for the specific language governing
61608 + *  rights and limitations under the License.
61609 + *
61610 + *
61611 + *
61612 + */
61613 +
61614 +#include "htc_internal.h"
61615 +
61616 +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket)
61617 +{
61618 +        /* not implemented
61619 +         * we do not send control TX frames during normal runtime, only during setup  */
61620 +    AR_DEBUG_ASSERT(FALSE);
61621 +}
61622 +
61623 +    /* callback when a control message arrives on this endpoint */
61624 +void HTCControlRecv(void *Context, HTC_PACKET *pPacket)
61625 +{
61626 +    AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0);
61627 +
61628 +        /* the only control messages we are expecting are NULL messages (credit resports), which should
61629 +         * never get here */
61630 +    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61631 +                    ("HTCControlRecv, got message with length:%d \n",
61632 +                    pPacket->ActualLength + HTC_HDR_LENGTH));
61633 +
61634 +        /* dump header and message */
61635 +    DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH,
61636 +                   pPacket->ActualLength + HTC_HDR_LENGTH,
61637 +                   "Unexpected ENDPOINT 0 Message");
61638 +
61639 +    HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket);
61640 +}
61641 +
61642 +A_STATUS HTCSendSetupComplete(HTC_TARGET *target)
61643 +{
61644 +    HTC_PACKET             *pSendPacket = NULL;
61645 +    A_STATUS                status;
61646 +    HTC_SETUP_COMPLETE_MSG *pSetupComplete;
61647 +
61648 +    do {
61649 +           /* allocate a packet to send to the target */
61650 +        pSendPacket = HTC_ALLOC_CONTROL_TX(target);
61651 +
61652 +        if (NULL == pSendPacket) {
61653 +            status = A_NO_MEMORY;
61654 +            break;
61655 +        }
61656 +
61657 +            /* assemble setup complete message */
61658 +        pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer;
61659 +        A_MEMZERO(pSetupComplete,sizeof(HTC_SETUP_COMPLETE_MSG));
61660 +        pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID;
61661 +
61662 +        SET_HTC_PACKET_INFO_TX(pSendPacket,
61663 +                               NULL,
61664 +                               (A_UINT8 *)pSetupComplete,
61665 +                               sizeof(HTC_SETUP_COMPLETE_MSG),
61666 +                               ENDPOINT_0,
61667 +                               HTC_SERVICE_TX_PACKET_TAG);
61668 +
61669 +            /* we want synchronous operation */
61670 +        pSendPacket->Completion = NULL;
61671 +            /* send the message */
61672 +        status = HTCIssueSend(target,pSendPacket,0);
61673 +
61674 +    } while (FALSE);
61675 +
61676 +    if (pSendPacket != NULL) {
61677 +        HTC_FREE_CONTROL_TX(target,pSendPacket);
61678 +    }
61679 +
61680 +    return status;
61681 +}
61682 +
61683 +
61684 +A_STATUS HTCConnectService(HTC_HANDLE               HTCHandle,
61685 +                           HTC_SERVICE_CONNECT_REQ  *pConnectReq,
61686 +                           HTC_SERVICE_CONNECT_RESP *pConnectResp)
61687 +{
61688 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
61689 +    A_STATUS                            status = A_OK;
61690 +    HTC_PACKET                          *pRecvPacket = NULL;
61691 +    HTC_PACKET                          *pSendPacket = NULL;
61692 +    HTC_CONNECT_SERVICE_RESPONSE_MSG    *pResponseMsg;
61693 +    HTC_CONNECT_SERVICE_MSG             *pConnectMsg;
61694 +    HTC_ENDPOINT_ID                     assignedEndpoint = ENDPOINT_MAX;
61695 +    HTC_ENDPOINT                        *pEndpoint;
61696 +    int                                 maxMsgSize = 0;
61697 +
61698 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%X SvcID:0x%X \n",
61699 +               (A_UINT32)target, pConnectReq->ServiceID));
61700 +
61701 +    do {
61702 +
61703 +        AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0);
61704 +
61705 +        if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) {
61706 +                /* special case for pseudo control service */
61707 +            assignedEndpoint = ENDPOINT_0;
61708 +            maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH;
61709 +        } else {
61710 +                /* allocate a packet to send to the target */
61711 +            pSendPacket = HTC_ALLOC_CONTROL_TX(target);
61712 +
61713 +            if (NULL == pSendPacket) {
61714 +                AR_DEBUG_ASSERT(FALSE);
61715 +                status = A_NO_MEMORY;
61716 +                break;
61717 +            }
61718 +                /* assemble connect service message */
61719 +            pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer;
61720 +            AR_DEBUG_ASSERT(pConnectMsg != NULL);
61721 +            A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG));
61722 +            pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID;
61723 +            pConnectMsg->ServiceID = pConnectReq->ServiceID;
61724 +            pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags;
61725 +                /* check caller if it wants to transfer meta data */
61726 +            if ((pConnectReq->pMetaData != NULL) &&
61727 +                (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
61728 +                    /* copy meta data into message buffer (after header ) */
61729 +                A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG),
61730 +                         pConnectReq->pMetaData,
61731 +                         pConnectReq->MetaDataLength);
61732 +                pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength;
61733 +            }
61734 +
61735 +            SET_HTC_PACKET_INFO_TX(pSendPacket,
61736 +                                   NULL,
61737 +                                   (A_UINT8 *)pConnectMsg,
61738 +                                   sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength,
61739 +                                   ENDPOINT_0,
61740 +                                   HTC_SERVICE_TX_PACKET_TAG);
61741 +
61742 +                /* we want synchronous operation */
61743 +            pSendPacket->Completion = NULL;
61744 +
61745 +            status = HTCIssueSend(target,pSendPacket,0);
61746 +
61747 +            if (A_FAILED(status)) {
61748 +                break;
61749 +            }
61750 +
61751 +                /* wait for response */
61752 +            status = HTCWaitforControlMessage(target, &pRecvPacket);
61753 +
61754 +            if (A_FAILED(status)) {
61755 +                break;
61756 +            }
61757 +                /* we controlled the buffer creation so it has to be properly aligned */
61758 +            pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer;
61759 +
61760 +            if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) ||
61761 +                (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) {
61762 +                    /* this message is not valid */
61763 +                AR_DEBUG_ASSERT(FALSE);
61764 +                status = A_EPROTO;
61765 +                break;
61766 +            }
61767 +
61768 +            pConnectResp->ConnectRespCode = pResponseMsg->Status;
61769 +                /* check response status */
61770 +            if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) {
61771 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61772 +                    (" Target failed service 0x%X connect request (status:%d)\n",
61773 +                                pResponseMsg->ServiceID, pResponseMsg->Status));
61774 +                status = A_EPROTO;
61775 +                break;
61776 +            }
61777 +
61778 +            assignedEndpoint = pResponseMsg->EndpointID;
61779 +            maxMsgSize = pResponseMsg->MaxMsgSize;
61780 +
61781 +            if ((pConnectResp->pMetaData != NULL) &&
61782 +                (pResponseMsg->ServiceMetaLength > 0) &&
61783 +                (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
61784 +                    /* caller supplied a buffer and the target responded with data */
61785 +                int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength);
61786 +                    /* copy the meta data */
61787 +                A_MEMCPY(pConnectResp->pMetaData,
61788 +                         ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG),
61789 +                         copyLength);
61790 +                pConnectResp->ActualLength = copyLength;
61791 +            }
61792 +
61793 +        }
61794 +
61795 +            /* the rest of these are parameter checks so set the error status */
61796 +        status = A_EPROTO;
61797 +
61798 +        if (assignedEndpoint >= ENDPOINT_MAX) {
61799 +            AR_DEBUG_ASSERT(FALSE);
61800 +            break;
61801 +        }
61802 +
61803 +        if (0 == maxMsgSize) {
61804 +            AR_DEBUG_ASSERT(FALSE);
61805 +            break;
61806 +        }
61807 +
61808 +        pEndpoint = &target->EndPoint[assignedEndpoint];
61809 +
61810 +        if (pEndpoint->ServiceID != 0) {
61811 +            /* endpoint already in use! */
61812 +            AR_DEBUG_ASSERT(FALSE);
61813 +            break;
61814 +        }
61815 +
61816 +            /* return assigned endpoint to caller */
61817 +        pConnectResp->Endpoint = assignedEndpoint;
61818 +        pConnectResp->MaxMsgLength = maxMsgSize;
61819 +
61820 +            /* setup the endpoint */
61821 +        pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */
61822 +        pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth;
61823 +        pEndpoint->MaxMsgLength = maxMsgSize;
61824 +            /* copy all the callbacks */
61825 +        pEndpoint->EpCallBacks = pConnectReq->EpCallbacks;
61826 +        INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers);
61827 +        INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
61828 +            /* set the credit distribution info for this endpoint, this information is
61829 +             * passed back to the credit distribution callback function */
61830 +        pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID;
61831 +        pEndpoint->CreditDist.pHTCReserved = pEndpoint;
61832 +        pEndpoint->CreditDist.Endpoint = assignedEndpoint;
61833 +        pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize;
61834 +        pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize;
61835 +
61836 +        if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
61837 +            pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1;
61838 +        }
61839 +
61840 +        status = A_OK;
61841 +
61842 +    } while (FALSE);
61843 +
61844 +    if (pSendPacket != NULL) {
61845 +        HTC_FREE_CONTROL_TX(target,pSendPacket);
61846 +    }
61847 +
61848 +    if (pRecvPacket != NULL) {
61849 +        HTC_FREE_CONTROL_RX(target,pRecvPacket);
61850 +    }
61851 +
61852 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n"));
61853 +
61854 +    return status;
61855 +}
61856 +
61857 +static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist)
61858 +{
61859 +    HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry;
61860 +
61861 +    if (NULL == target->EpCreditDistributionListHead) {
61862 +        target->EpCreditDistributionListHead = pEpDist;
61863 +        pEpDist->pNext = NULL;
61864 +        pEpDist->pPrev = NULL;
61865 +        return;
61866 +    }
61867 +
61868 +        /* queue to the end of the list, this does not have to be very
61869 +         * fast since this list is built at startup time */
61870 +    pCurEntry = target->EpCreditDistributionListHead;
61871 +
61872 +    while (pCurEntry) {
61873 +        pLastEntry = pCurEntry;
61874 +        pCurEntry = pCurEntry->pNext;
61875 +    }
61876 +
61877 +    pLastEntry->pNext = pEpDist;
61878 +    pEpDist->pPrev = pLastEntry;
61879 +    pEpDist->pNext = NULL;
61880 +}
61881 +
61882 +
61883 +
61884 +/* default credit init callback */
61885 +static void HTCDefaultCreditInit(void                     *Context,
61886 +                                 HTC_ENDPOINT_CREDIT_DIST *pEPList,
61887 +                                 int                      TotalCredits)
61888 +{
61889 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
61890 +    int                      totalEps = 0;
61891 +    int                      creditsPerEndpoint;
61892 +
61893 +    pCurEpDist = pEPList;
61894 +        /* first run through the list and figure out how many endpoints we are dealing with */
61895 +    while (pCurEpDist != NULL) {
61896 +        pCurEpDist = pCurEpDist->pNext;
61897 +        totalEps++;
61898 +    }
61899 +
61900 +        /* even distribution */
61901 +    creditsPerEndpoint = TotalCredits/totalEps;
61902 +
61903 +    pCurEpDist = pEPList;
61904 +        /* run through the list and set minimum and normal credits and
61905 +         * provide the endpoint with some credits to start */
61906 +    while (pCurEpDist != NULL) {
61907 +
61908 +        if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) {
61909 +                /* too many endpoints and not enough credits */
61910 +            AR_DEBUG_ASSERT(FALSE);
61911 +            break;
61912 +        }
61913 +            /* our minimum is set for at least 1 max message */
61914 +        pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
61915 +            /* this value is ignored by our credit alg, since we do
61916 +             * not dynamically adjust credits, this is the policy of
61917 +             * the "default" credit distribution, something simple and easy */
61918 +        pCurEpDist->TxCreditsNorm = 0xFFFF;
61919 +            /* give the endpoint minimum credits */
61920 +        pCurEpDist->TxCredits = creditsPerEndpoint;
61921 +        pCurEpDist->TxCreditsAssigned = creditsPerEndpoint;
61922 +        pCurEpDist = pCurEpDist->pNext;
61923 +    }
61924 +
61925 +}
61926 +
61927 +/* default credit distribution callback, NOTE, this callback holds the TX lock */
61928 +void HTCDefaultCreditDist(void                     *Context,
61929 +                          HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
61930 +                          HTC_CREDIT_DIST_REASON   Reason)
61931 +{
61932 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
61933 +
61934 +    if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) {
61935 +        pCurEpDist = pEPDistList;
61936 +            /* simple distribution */
61937 +        while (pCurEpDist != NULL) {
61938 +            if (pCurEpDist->TxCreditsToDist > 0) {
61939 +                    /* just give the endpoint back the credits */
61940 +                pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
61941 +                pCurEpDist->TxCreditsToDist = 0;
61942 +            }
61943 +            pCurEpDist = pCurEpDist->pNext;
61944 +        }
61945 +    }
61946 +
61947 +    /* note we do not need to handle the other reason codes as this is a very
61948 +     * simple distribution scheme, no need to seek for more credits or handle inactivity */
61949 +}
61950 +
61951 +void HTCSetCreditDistribution(HTC_HANDLE               HTCHandle,
61952 +                              void                     *pCreditDistContext,
61953 +                              HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
61954 +                              HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
61955 +                              HTC_SERVICE_ID           ServicePriorityOrder[],
61956 +                              int                      ListLength)
61957 +{
61958 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
61959 +    int i;
61960 +    int ep;
61961 +
61962 +    if (CreditInitFunc != NULL) {
61963 +            /* caller has supplied their own distribution functions */
61964 +        target->InitCredits = CreditInitFunc;
61965 +        AR_DEBUG_ASSERT(CreditDistFunc != NULL);
61966 +        target->DistributeCredits = CreditDistFunc;
61967 +        target->pCredDistContext = pCreditDistContext;
61968 +    } else {
61969 +        /* caller wants HTC to do distribution */
61970 +        /* if caller wants service to handle distributions then
61971 +         * it must set both of these to NULL! */
61972 +        AR_DEBUG_ASSERT(CreditDistFunc == NULL);
61973 +        target->InitCredits = HTCDefaultCreditInit;
61974 +        target->DistributeCredits = HTCDefaultCreditDist;
61975 +        target->pCredDistContext = target;
61976 +    }
61977 +
61978 +        /* always add HTC control endpoint first, we only expose the list after the
61979 +         * first one, this is added for TX queue checking */
61980 +    AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist);
61981 +
61982 +        /* build the list of credit distribution structures in priority order
61983 +         * supplied by the caller, these will follow endpoint 0 */
61984 +    for (i = 0; i < ListLength; i++) {
61985 +            /* match services with endpoints and add the endpoints to the distribution list
61986 +             * in FIFO order */
61987 +        for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) {
61988 +            if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) {
61989 +                    /* queue this one to the list */
61990 +                AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist);
61991 +                break;
61992 +            }
61993 +        }
61994 +        AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
61995 +    }
61996 +
61997 +}
61998 --- /dev/null
61999 +++ b/drivers/ar6000/include/a_config.h
62000 @@ -0,0 +1,27 @@
62001 +#ifndef _A_CONFIG_H_
62002 +#define _A_CONFIG_H_
62003 +/*
62004 + * Copyright (c) 2004-2005 Atheros Communications Inc.
62005 + * All rights reserved.
62006 + *
62007 + *
62008 + *  This program is free software; you can redistribute it and/or modify
62009 + *  it under the terms of the GNU General Public License version 2 as
62010 + *  published by the Free Software Foundation;
62011 + *
62012 + *  Software distributed under the License is distributed on an "AS
62013 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62014 + *  implied. See the License for the specific language governing
62015 + *  rights and limitations under the License.
62016 + *
62017 + *
62018 + *
62019 + */
62020 +
62021 +/*
62022 + * This file contains software configuration options that enables
62023 + * specific software "features"
62024 + */
62025 +#include "../ar6000/config_linux.h"
62026 +
62027 +#endif
62028 --- /dev/null
62029 +++ b/drivers/ar6000/include/a_debug.h
62030 @@ -0,0 +1,41 @@
62031 +#ifndef _A_DEBUG_H_
62032 +#define _A_DEBUG_H_
62033 +/*
62034 + * Copyright (c) 2004-2006 Atheros Communications Inc.
62035 + * All rights reserved.
62036 + *
62037 + * Copyright (c) 2004-2007 Atheros Communications Inc.
62038 + * All rights reserved.
62039 + *
62040 + *
62041 + *  This program is free software; you can redistribute it and/or modify
62042 + *  it under the terms of the GNU General Public License version 2 as
62043 + *  published by the Free Software Foundation;
62044 + *
62045 + *  Software distributed under the License is distributed on an "AS
62046 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62047 + *  implied. See the License for the specific language governing
62048 + *  rights and limitations under the License.
62049 + *
62050 + *
62051 + *
62052 + */
62053 +
62054 +#include <a_types.h>
62055 +#include <a_osapi.h>
62056 +
62057 +#define DBG_INFO               0x00000001
62058 +#define DBG_ERROR              0x00000002
62059 +#define DBG_WARNING            0x00000004
62060 +#define DBG_SDIO               0x00000008
62061 +#define DBG_HIF                        0x00000010
62062 +#define DBG_HTC                        0x00000020
62063 +#define DBG_WMI                        0x00000040
62064 +#define DBG_WMI2               0x00000080
62065 +#define DBG_DRIVER             0x00000100
62066 +
62067 +#define DBG_DEFAULTS   (DBG_ERROR|DBG_WARNING)
62068 +
62069 +#include "../ar6000/debug_linux.h"
62070 +
62071 +#endif
62072 --- /dev/null
62073 +++ b/drivers/ar6000/include/a_drv_api.h
62074 @@ -0,0 +1,185 @@
62075 +#ifndef _A_DRV_API_H_
62076 +#define _A_DRV_API_H_
62077 +/*
62078 + * Copyright (c) 2004-2006 Atheros Communications Inc.
62079 + * All rights reserved.
62080 + *
62081 + *
62082 + *  This program is free software; you can redistribute it and/or modify
62083 + *  it under the terms of the GNU General Public License version 2 as
62084 + *  published by the Free Software Foundation;
62085 + *
62086 + *  Software distributed under the License is distributed on an "AS
62087 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62088 + *  implied. See the License for the specific language governing
62089 + *  rights and limitations under the License.
62090 + *
62091 + *
62092 + *
62093 + */
62094 +
62095 +#ifdef __cplusplus
62096 +extern "C" {
62097 +#endif
62098 +
62099 +/****************************************************************************/
62100 +/****************************************************************************/
62101 +/**                                                                        **/
62102 +/** WMI related hooks                                                      **/
62103 +/**                                                                        **/
62104 +/****************************************************************************/
62105 +/****************************************************************************/
62106 +
62107 +#include <ar6000_api.h>
62108 +
62109 +#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList)  \
62110 +       ar6000_channelList_rx((devt), (numChan), (chanList))
62111 +
62112 +#define A_WMI_SET_NUMDATAENDPTS(devt, num)     \
62113 +       ar6000_set_numdataendpts((devt), (num))
62114 +
62115 +#define A_WMI_CONTROL_TX(devt, osbuf, streamID)        \
62116 +       ar6000_control_tx((devt), (osbuf), (streamID))
62117 +
62118 +#define A_WMI_TARGETSTATS_EVENT(devt, pStats)  \
62119 +       ar6000_targetStats_event((devt), (pStats))
62120 +
62121 +#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \
62122 +       ar6000_scanComplete_event((devt), (status))
62123 +
62124 +#ifdef CONFIG_HOST_DSET_SUPPORT
62125 +
62126 +#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg)      \
62127 +       ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg))
62128 +
62129 +#define A_WMI_DSET_CLOSE(devt, access_cookie)  \
62130 +       ar6000_dset_close((devt), (access_cookie))
62131 +
62132 +#endif
62133 +
62134 +#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \
62135 +       ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg))
62136 +
62137 +#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \
62138 +       ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo))
62139 +
62140 +#define A_WMI_REGDOMAIN_EVENT(devt, regCode)   \
62141 +       ar6000_regDomain_event((devt), (regCode))
62142 +
62143 +#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \
62144 +       ar6000_neighborReport_event((devt), (numAps), (info))
62145 +
62146 +#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus)     \
62147 +       ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus))
62148 +
62149 +#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast)  \
62150 +       ar6000_tkip_micerr_event((devt), (keyid), (ismcast))
62151 +
62152 +#define A_WMI_BITRATE_RX(devt, rateKbps)       \
62153 +       ar6000_bitrate_rx((devt), (rateKbps))
62154 +
62155 +#define A_WMI_TXPWR_RX(devt, txPwr)    \
62156 +       ar6000_txPwr_rx((devt), (txPwr))
62157 +
62158 +#define A_WMI_READY_EVENT(devt, datap, phyCap) \
62159 +       ar6000_ready_event((devt), (datap), (phyCap))
62160 +
62161 +#define A_WMI_DBGLOG_INIT_DONE(ar) \
62162 +        ar6000_dbglog_init_done(ar);
62163 +
62164 +#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi)   \
62165 +       ar6000_rssiThreshold_event((devt), (newThreshold), (rssi))
62166 +
62167 +#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal)       \
62168 +       ar6000_reportError_event((devt), (errorVal))
62169 +
62170 +#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \
62171 +       ar6000_roam_tbl_event((devt), (pTbl))
62172 +
62173 +#define A_WMI_ROAM_DATA_EVENT(devt, p) \
62174 +       ar6000_roam_data_event((devt), (p))
62175 +
62176 +#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters)   \
62177 +       ar6000_wow_list_event((devt), (num_filters), (wow_filters))
62178 +
62179 +#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion)  \
62180 +       ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion))
62181 +
62182 +#define A_WMI_IPTOS_TO_USERPRIORITY(pkt)    \
62183 +       ar6000_iptos_to_userPriority((pkt))
62184 +
62185 +#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list)    \
62186 +       ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list))
62187 +
62188 +#ifdef CONFIG_HOST_GPIO_SUPPORT
62189 +
62190 +#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \
62191 +       ar6000_gpio_intr_rx((intr_mask), (input_values))
62192 +
62193 +#define A_WMI_GPIO_DATA_RX(reg_id, value) \
62194 +       ar6000_gpio_data_rx((reg_id), (value))
62195 +
62196 +#define A_WMI_GPIO_ACK_RX() \
62197 +       ar6000_gpio_ack_rx()
62198 +
62199 +#endif
62200 +
62201 +#ifdef SEND_EVENT_TO_APP
62202 +
62203 +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \
62204 +       ar6000_send_event_to_app((ar), (eventId), (datap), (len))
62205 +
62206 +#else
62207 +
62208 +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len)
62209 +
62210 +#endif
62211 +
62212 +#ifdef CONFIG_HOST_TCMD_SUPPORT
62213 +#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \
62214 +       ar6000_tcmd_rx_report_event((devt), (results), (len))
62215 +#endif
62216 +
62217 +#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source)    \
62218 +    ar6000_hbChallengeResp_event((devt), (cookie), (source))
62219 +
62220 +#define A_WMI_TX_RETRY_ERR_EVENT(devt) \
62221 +       ar6000_tx_retry_err_event((devt))
62222 +
62223 +#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \
62224 +       ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr))
62225 +
62226 +#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \
62227 +       ar6000_lqThresholdEvent_rx((devt), (range), (lqVal))
62228 +
62229 +#define A_WMI_RATEMASK_RX(devt, ratemask) \
62230 +       ar6000_ratemask_rx((devt), (ratemask))
62231 +
62232 +#define A_WMI_KEEPALIVE_RX(devt, configured)    \
62233 +        ar6000_keepalive_rx((devt), (configured))
62234 +
62235 +#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len)   \
62236 +        ar6000_bssInfo_event_rx((ar), (datap), (len))
62237 +
62238 +#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \
62239 +        ar6000_dbglog_event((ar), (dropped), (buffer), (length));
62240 +
62241 +#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \
62242 +    ar6000_indicate_tx_activity((devt),(trafficClass), TRUE)
62243 +
62244 +#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \
62245 +    ar6000_indicate_tx_activity((devt),(trafficClass), FALSE)
62246 +
62247 +/****************************************************************************/
62248 +/****************************************************************************/
62249 +/**                                                                        **/
62250 +/** HTC related hooks                                                      **/
62251 +/**                                                                        **/
62252 +/****************************************************************************/
62253 +/****************************************************************************/
62254 +
62255 +#ifdef __cplusplus
62256 +}
62257 +#endif
62258 +
62259 +#endif
62260 --- /dev/null
62261 +++ b/drivers/ar6000/include/a_drv.h
62262 @@ -0,0 +1,28 @@
62263 +#ifndef _A_DRV_H_
62264 +#define _A_DRV_H_
62265 +/*
62266 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/a_drv.h#1 $
62267 + *
62268 + * This file contains the definitions of the basic atheros data types.
62269 + * It is used to map the data types in atheros files to a platform specific
62270 + * type.
62271 + *
62272 + * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
62273 + *
62274 + *
62275 + *  This program is free software; you can redistribute it and/or modify
62276 + *  it under the terms of the GNU General Public License version 2 as
62277 + *  published by the Free Software Foundation;
62278 + *
62279 + *  Software distributed under the License is distributed on an "AS
62280 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62281 + *  implied. See the License for the specific language governing
62282 + *  rights and limitations under the License.
62283 + *
62284 + *
62285 + *
62286 + */
62287 +
62288 +#include "../ar6000/athdrv_linux.h"
62289 +
62290 +#endif /* _ADRV_H_ */
62291 --- /dev/null
62292 +++ b/drivers/ar6000/include/a_osapi.h
62293 @@ -0,0 +1,28 @@
62294 +#ifndef _A_OSAPI_H_
62295 +#define _A_OSAPI_H_
62296 +/*
62297 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/a_osapi.h#1 $
62298 + *
62299 + * This file contains the definitions of the basic atheros data types.
62300 + * It is used to map the data types in atheros files to a platform specific
62301 + * type.
62302 + *
62303 + * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
62304 + *
62305 + *
62306 + *  This program is free software; you can redistribute it and/or modify
62307 + *  it under the terms of the GNU General Public License version 2 as
62308 + *  published by the Free Software Foundation;
62309 + *
62310 + *  Software distributed under the License is distributed on an "AS
62311 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62312 + *  implied. See the License for the specific language governing
62313 + *  rights and limitations under the License.
62314 + *
62315 + *
62316 + *
62317 + */
62318 +
62319 +#include "../ar6000/osapi_linux.h"
62320 +
62321 +#endif /* _OSAPI_H_ */
62322 --- /dev/null
62323 +++ b/drivers/ar6000/include/ar6000_api.h
62324 @@ -0,0 +1,29 @@
62325 +#ifndef _AR6000_API_H_
62326 +#define _AR6000_API_H_
62327 +/*
62328 + * Copyright (c) 2004-2005 Atheros Communications Inc.
62329 + * All rights reserved.
62330 + *
62331 + * This file contains the API to access the OS dependent atheros host driver
62332 + * by the WMI or WLAN generic modules.
62333 + *
62334 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/ar6000_api.h#1 $
62335 + *
62336 + *
62337 + *  This program is free software; you can redistribute it and/or modify
62338 + *  it under the terms of the GNU General Public License version 2 as
62339 + *  published by the Free Software Foundation;
62340 + *
62341 + *  Software distributed under the License is distributed on an "AS
62342 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62343 + *  implied. See the License for the specific language governing
62344 + *  rights and limitations under the License.
62345 + *
62346 + *
62347 + *
62348 + */
62349 +
62350 +#include "../ar6000/ar6xapi_linux.h"
62351 +
62352 +#endif /* _AR6000_API_H */
62353 +
62354 --- /dev/null
62355 +++ b/drivers/ar6000/include/ar6000_diag.h
62356 @@ -0,0 +1,38 @@
62357 +/*
62358 + *
62359 + * Copyright (c) 2004-2007 Atheros Communications Inc.
62360 + * All rights reserved.
62361 + *
62362 + *
62363 + *  This program is free software; you can redistribute it and/or modify
62364 + *  it under the terms of the GNU General Public License version 2 as
62365 + *  published by the Free Software Foundation;
62366 + *
62367 + *  Software distributed under the License is distributed on an "AS
62368 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62369 + *  implied. See the License for the specific language governing
62370 + *  rights and limitations under the License.
62371 + *
62372 + *
62373 + *
62374 + */
62375 +
62376 +#ifndef AR6000_DIAG_H_
62377 +#define AR6000_DIAG_H_
62378 +
62379 +
62380 +A_STATUS
62381 +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
62382 +
62383 +A_STATUS
62384 +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
62385 +
62386 +A_STATUS
62387 +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
62388 +                    A_UCHAR *data, A_UINT32 length);
62389 +
62390 +A_STATUS
62391 +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
62392 +                     A_UCHAR *data, A_UINT32 length);
62393 +
62394 +#endif /*AR6000_DIAG_H_*/
62395 --- /dev/null
62396 +++ b/drivers/ar6000/include/AR6001_regdump.h
62397 @@ -0,0 +1,100 @@
62398 +/*
62399 + * Copyright (c) 2006 Atheros Communications Inc.
62400 + * All rights reserved.
62401 + *
62402 + * $ATH_LICENSE_HOSTSDK0_C$
62403 + *
62404 + */
62405 +
62406 +#ifndef __AR6000_REGDUMP_H__
62407 +#define __AR6000_REGDUMP_H__
62408 +
62409 +#if !defined(__ASSEMBLER__)
62410 +/*
62411 + * Target CPU state at the time of failure is reflected
62412 + * in a register dump, which the Host can fetch through
62413 + * the diagnostic window.
62414 + */
62415 +
62416 +struct MIPS_exception_frame_s {
62417 +    A_UINT32 pc;        /* Program Counter */
62418 +    A_UINT32 at;        /* MIPS General Purpose registers */
62419 +    A_UINT32 v0;
62420 +    A_UINT32 v1;
62421 +    A_UINT32 a0;
62422 +    A_UINT32 a1;
62423 +    A_UINT32 a2;
62424 +    A_UINT32 a3;
62425 +    A_UINT32 t0;
62426 +    A_UINT32 t1;
62427 +    A_UINT32 t2;
62428 +    A_UINT32 t3;
62429 +    A_UINT32 t4;
62430 +    A_UINT32 t5;
62431 +    A_UINT32 t6;
62432 +    A_UINT32 t7;
62433 +    A_UINT32 s0;
62434 +    A_UINT32 s1;
62435 +    A_UINT32 s2;
62436 +    A_UINT32 s3;
62437 +    A_UINT32 s4;
62438 +    A_UINT32 s5;
62439 +    A_UINT32 s6;
62440 +    A_UINT32 s7;
62441 +    A_UINT32 t8;
62442 +    A_UINT32 t9;
62443 +    A_UINT32 k0;
62444 +    A_UINT32 k1;
62445 +    A_UINT32 gp;
62446 +    A_UINT32 sp;
62447 +    A_UINT32 s8;
62448 +    A_UINT32 ra;
62449 +    A_UINT32 cause; /* Selected coprocessor regs */
62450 +    A_UINT32 status;
62451 +};
62452 +typedef struct MIPS_exception_frame_s CPU_exception_frame_t;
62453 +
62454 +#endif
62455 +
62456 +/*
62457 + * Offsets into MIPS_exception_frame structure, for use in assembler code
62458 + * MUST MATCH C STRUCTURE ABOVE
62459 + */
62460 +#define RD_pc           0
62461 +#define RD_at           1
62462 +#define RD_v0           2
62463 +#define RD_v1           3
62464 +#define RD_a0           4
62465 +#define RD_a1           5
62466 +#define RD_a2           6
62467 +#define RD_a3           7
62468 +#define RD_t0           8
62469 +#define RD_t1           9
62470 +#define RD_t2           10
62471 +#define RD_t3           11
62472 +#define RD_t4           12
62473 +#define RD_t5           13
62474 +#define RD_t6           14
62475 +#define RD_t7           15
62476 +#define RD_s0           16
62477 +#define RD_s1           17
62478 +#define RD_s2           18
62479 +#define RD_s3           19
62480 +#define RD_s4           20
62481 +#define RD_s5           21
62482 +#define RD_s6           22
62483 +#define RD_s7           23
62484 +#define RD_t8           24
62485 +#define RD_t9           25
62486 +#define RD_k0           26
62487 +#define RD_k1           27
62488 +#define RD_gp           28
62489 +#define RD_sp           29
62490 +#define RD_s8           30
62491 +#define RD_ra           31
62492 +#define RD_cause        32
62493 +#define RD_status       33
62494 +
62495 +#define RD_SIZE         (34*4) /* Space for this number of words */
62496 +
62497 +#endif /* __AR6000_REGDUMP_H__ */
62498 --- /dev/null
62499 +++ b/drivers/ar6000/include/AR6Khwreg.h
62500 @@ -0,0 +1,147 @@
62501 +/*
62502 + * Copyright (c) 2004-2007 Atheros Communications Inc.
62503 + * All rights reserved.
62504 + *
62505 + * $ATH_LICENSE_HOSTSDK0_C$
62506 + *
62507 + * This file contains the definitions for AR6001 registers
62508 + * that may be directly manipulated by Host software.
62509 + */
62510 +
62511 +#ifndef __AR6KHWREG_H__
62512 +#define __AR6KHWREG_H__
62513 +
62514 +#ifdef __cplusplus
62515 +extern "C" {
62516 +#endif
62517 +
62518 +/* Host registers */
62519 +#define HOST_INT_STATUS_ADDRESS                  0x00000400
62520 +#define CPU_INT_STATUS_ADDRESS                   0x00000401
62521 +#define ERROR_INT_STATUS_ADDRESS                 0x00000402
62522 +#define INT_STATUS_ENABLE_ADDRESS                0x00000418
62523 +#define CPU_INT_STATUS_ENABLE_ADDRESS            0x00000419
62524 +#define COUNT_ADDRESS                            0x00000420
62525 +#define COUNT_DEC_ADDRESS                        0x00000440
62526 +#define WINDOW_DATA_ADDRESS                      0x00000474
62527 +#define WINDOW_WRITE_ADDR_ADDRESS                0x00000478
62528 +#define WINDOW_READ_ADDR_ADDRESS                 0x0000047c
62529 +
62530 +/* Target addresses */
62531 +#define RESET_CONTROL_ADDRESS                    0x0c000000
62532 +#define MC_REMAP_VALID_ADDRESS                   0x0c004080
62533 +#define MC_REMAP_SIZE_ADDRESS                    0x0c004100
62534 +#define MC_REMAP_COMPARE_ADDRESS                 0x0c004180
62535 +#define MC_REMAP_TARGET_ADDRESS                  0x0c004200
62536 +#define LOCAL_COUNT_ADDRESS                      0x0c014080
62537 +#define LOCAL_SCRATCH_ADDRESS                    0x0c0140c0
62538 +
62539 +
62540 +#define INT_STATUS_ENABLE_ERROR_MSB              7
62541 +#define INT_STATUS_ENABLE_ERROR_LSB              7
62542 +#define INT_STATUS_ENABLE_ERROR_MASK             0x00000080
62543 +#define INT_STATUS_ENABLE_ERROR_GET(x)           (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
62544 +#define INT_STATUS_ENABLE_ERROR_SET(x)           (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
62545 +
62546 +#define INT_STATUS_ENABLE_CPU_MSB                6
62547 +#define INT_STATUS_ENABLE_CPU_LSB                6
62548 +#define INT_STATUS_ENABLE_CPU_MASK               0x00000040
62549 +#define INT_STATUS_ENABLE_CPU_GET(x)             (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
62550 +#define INT_STATUS_ENABLE_CPU_SET(x)             (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
62551 +
62552 +#define INT_STATUS_ENABLE_COUNTER_MSB            4
62553 +#define INT_STATUS_ENABLE_COUNTER_LSB            4
62554 +#define INT_STATUS_ENABLE_COUNTER_MASK           0x00000010
62555 +#define INT_STATUS_ENABLE_COUNTER_GET(x)         (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
62556 +#define INT_STATUS_ENABLE_COUNTER_SET(x)         (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
62557 +
62558 +#define INT_STATUS_ENABLE_MBOX_DATA_MSB          3
62559 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB          0
62560 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK         0x0000000f
62561 +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x)       (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
62562 +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x)       (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
62563 +
62564 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB     1
62565 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     1
62566 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    0x00000002
62567 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x)  (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
62568 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x)  (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
62569 +
62570 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB      0
62571 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB      0
62572 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     0x00000001
62573 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x)   (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
62574 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)   (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
62575 +
62576 +
62577 +#define CPU_INT_STATUS_ENABLE_BIT_MSB            7
62578 +#define CPU_INT_STATUS_ENABLE_BIT_LSB            0
62579 +#define CPU_INT_STATUS_ENABLE_BIT_MASK           0x000000ff
62580 +#define CPU_INT_STATUS_ENABLE_BIT_GET(x)         (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
62581 +#define CPU_INT_STATUS_ENABLE_BIT_SET(x)         (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
62582 +
62583 +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB        7
62584 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB        0
62585 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK       0x000000ff
62586 +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x)     (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
62587 +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)     (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
62588 +
62589 +#define ERROR_INT_STATUS_WAKEUP_MSB              2
62590 +#define ERROR_INT_STATUS_WAKEUP_LSB              2
62591 +#define ERROR_INT_STATUS_WAKEUP_MASK             0x00000004
62592 +#define ERROR_INT_STATUS_WAKEUP_GET(x)           (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
62593 +#define ERROR_INT_STATUS_WAKEUP_SET(x)           (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
62594 +
62595 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB        1
62596 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB        1
62597 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK       0x00000002
62598 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
62599 +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
62600 +
62601 +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB         0
62602 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB         0
62603 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK        0x00000001
62604 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
62605 +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
62606 +
62607 +#define HOST_INT_STATUS_ERROR_MSB                7
62608 +#define HOST_INT_STATUS_ERROR_LSB                7
62609 +#define HOST_INT_STATUS_ERROR_MASK               0x00000080
62610 +#define HOST_INT_STATUS_ERROR_GET(x)             (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
62611 +#define HOST_INT_STATUS_ERROR_SET(x)             (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
62612 +
62613 +#define HOST_INT_STATUS_CPU_MSB                  6
62614 +#define HOST_INT_STATUS_CPU_LSB                  6
62615 +#define HOST_INT_STATUS_CPU_MASK                 0x00000040
62616 +#define HOST_INT_STATUS_CPU_GET(x)               (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
62617 +#define HOST_INT_STATUS_CPU_SET(x)               (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
62618 +
62619 +#define HOST_INT_STATUS_COUNTER_MSB              4
62620 +#define HOST_INT_STATUS_COUNTER_LSB              4
62621 +#define HOST_INT_STATUS_COUNTER_MASK             0x00000010
62622 +#define HOST_INT_STATUS_COUNTER_GET(x)           (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
62623 +#define HOST_INT_STATUS_COUNTER_SET(x)           (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
62624 +
62625 +#define RESET_CONTROL_WARM_RST_MSB               7
62626 +#define RESET_CONTROL_WARM_RST_LSB               7
62627 +#define RESET_CONTROL_WARM_RST_MASK              0x00000080
62628 +#define RESET_CONTROL_WARM_RST_GET(x)            (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
62629 +#define RESET_CONTROL_WARM_RST_SET(x)            (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
62630 +
62631 +#define RESET_CONTROL_COLD_RST_MSB               8
62632 +#define RESET_CONTROL_COLD_RST_LSB               8
62633 +#define RESET_CONTROL_COLD_RST_MASK              0x00000100
62634 +#define RESET_CONTROL_COLD_RST_GET(x)            (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
62635 +#define RESET_CONTROL_COLD_RST_SET(x)            (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
62636 +
62637 +#define RESET_CAUSE_LAST_MSB                     2
62638 +#define RESET_CAUSE_LAST_LSB                     0
62639 +#define RESET_CAUSE_LAST_MASK                    0x00000007
62640 +#define RESET_CAUSE_LAST_GET(x)                  (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
62641 +#define RESET_CAUSE_LAST_SET(x)                  (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
62642 +
62643 +#ifdef __cplusplus
62644 +}
62645 +#endif
62646 +
62647 +#endif /* __AR6KHWREG_H__ */
62648 --- /dev/null
62649 +++ b/drivers/ar6000/include/AR6K_version.h
62650 @@ -0,0 +1,36 @@
62651 +#define __VER_MAJOR_ 2
62652 +#define __VER_MINOR_ 0
62653 +#define __VER_PATCH_ 0
62654 +
62655 +
62656 +/*
62657 + * Copyright (c) 2004-2007 Atheros Communications Inc.
62658 + * All rights reserved.
62659 + *
62660 + * $ATH_LICENSE_HOSTSDK0_C$
62661 + *
62662 + * The makear6ksdk script (used for release builds) modifies the following line.
62663 + */
62664 +#define __BUILD_NUMBER_ 18
62665 +
62666 +
62667 +/* Format of the version number. */
62668 +#define VER_MAJOR_BIT_OFFSET           28
62669 +#define VER_MINOR_BIT_OFFSET           24
62670 +#define VER_PATCH_BIT_OFFSET           16
62671 +#define VER_BUILD_NUM_BIT_OFFSET       0
62672 +
62673 +
62674 +/*
62675 + * The version has the following format:
62676 + * Bits 28-31: Major version
62677 + * Bits 24-27: Minor version
62678 + * Bits 16-23: Patch version
62679 + * Bits 0-15:  Build number (automatically generated during build process )
62680 + * E.g. Build 1.1.3.7 would be represented as 0x11030007.
62681 + *
62682 + * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
62683 + */
62684 +#define AR6K_SW_VERSION        ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
62685 +
62686 +
62687 --- /dev/null
62688 +++ b/drivers/ar6000/include/AR6K_version.h.NEW
62689 @@ -0,0 +1,36 @@
62690 +#define __VER_MAJOR_ 2
62691 +#define __VER_MINOR_ 0
62692 +#define __VER_PATCH_ 0
62693 +
62694 +
62695 +/*
62696 + * Copyright (c) 2004-2007 Atheros Communications Inc.
62697 + * All rights reserved.
62698 + *
62699 + * $ATH_LICENSE_HOSTSDK0_C$
62700 + *
62701 + * The makear6ksdk script (used for release builds) modifies the following line.
62702 + */
62703 +#define __BUILD_NUMBER_ 18
62704 +
62705 +
62706 +/* Format of the version number. */
62707 +#define VER_MAJOR_BIT_OFFSET           28
62708 +#define VER_MINOR_BIT_OFFSET           24
62709 +#define VER_PATCH_BIT_OFFSET           16
62710 +#define VER_BUILD_NUM_BIT_OFFSET       0
62711 +
62712 +
62713 +/*
62714 + * The version has the following format:
62715 + * Bits 28-31: Major version
62716 + * Bits 24-27: Minor version
62717 + * Bits 16-23: Patch version
62718 + * Bits 0-15:  Build number (automatically generated during build process )
62719 + * E.g. Build 1.1.3.7 would be represented as 0x11030007.
62720 + *
62721 + * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
62722 + */
62723 +#define AR6K_SW_VERSION        ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
62724 +
62725 +
62726 --- /dev/null
62727 +++ b/drivers/ar6000/include/athdefs.h
62728 @@ -0,0 +1,85 @@
62729 +#ifndef __ATHDEFS_H__
62730 +#define __ATHDEFS_H__
62731 +
62732 +/*
62733 + * Copyright (c) 2004-2007 Atheros Communications Inc.
62734 + * All rights reserved.
62735 + *
62736 + * $ATH_LICENSE_HOSTSDK0_C$
62737 + *
62738 + * This file contains definitions that may be used across both
62739 + * Host and Target software.  Nothing here is module-dependent
62740 + * or platform-dependent.
62741 + */
62742 +
62743 +/*
62744 + * Generic error codes that can be used by hw, sta, ap, sim, dk
62745 + * and any other environments. Since these are enums, feel free to
62746 + * add any more codes that you need.
62747 + */
62748 +
62749 +typedef enum {
62750 +    A_ERROR = -1,               /* Generic error return */
62751 +    A_OK = 0,                   /* success */
62752 +                                /* Following values start at 1 */
62753 +    A_DEVICE_NOT_FOUND,         /* not able to find PCI device */
62754 +    A_NO_MEMORY,                /* not able to allocate memory, not available */
62755 +    A_MEMORY_NOT_AVAIL,         /* memory region is not free for mapping */
62756 +    A_NO_FREE_DESC,             /* no free descriptors available */
62757 +    A_BAD_ADDRESS,              /* address does not match descriptor */
62758 +    A_WIN_DRIVER_ERROR,         /* used in NT_HW version, if problem at init */
62759 +    A_REGS_NOT_MAPPED,          /* registers not correctly mapped */
62760 +    A_EPERM,                    /* Not superuser */
62761 +    A_EACCES,                   /* Access denied */
62762 +    A_ENOENT,                   /* No such entry, search failed, etc. */
62763 +    A_EEXIST,                   /* The object already exists (can't create) */
62764 +    A_EFAULT,                   /* Bad address fault */
62765 +    A_EBUSY,                    /* Object is busy */
62766 +    A_EINVAL,                   /* Invalid parameter */
62767 +    A_EMSGSIZE,                 /* Inappropriate message buffer length */
62768 +    A_ECANCELED,                /* Operation canceled */
62769 +    A_ENOTSUP,                  /* Operation not supported */
62770 +    A_ECOMM,                    /* Communication error on send */
62771 +    A_EPROTO,                   /* Protocol error */
62772 +    A_ENODEV,                   /* No such device */
62773 +    A_EDEVNOTUP,                /* device is not UP */
62774 +    A_NO_RESOURCE,              /* No resources for requested operation */
62775 +    A_HARDWARE,                 /* Hardware failure */
62776 +    A_PENDING,                  /* Asynchronous routine; will send up results la
62777 +ter (typically in callback) */
62778 +    A_EBADCHANNEL,              /* The channel cannot be used */
62779 +    A_DECRYPT_ERROR,            /* Decryption error */
62780 +    A_PHY_ERROR,                /* RX PHY error */
62781 +    A_CONSUMED                  /* Object was consumed */
62782 +} A_STATUS;
62783 +
62784 +#define A_SUCCESS(x)        (x == A_OK)
62785 +#define A_FAILED(x)         (!A_SUCCESS(x))
62786 +
62787 +#ifndef TRUE
62788 +#define TRUE 1
62789 +#endif
62790 +
62791 +#ifndef FALSE
62792 +#define FALSE 0
62793 +#endif
62794 +
62795 +/*
62796 + * The following definition is WLAN specific definition
62797 + */
62798 +typedef enum {
62799 +    MODE_11A = 0,   /* 11a Mode */
62800 +    MODE_11G = 1,   /* 11g + 11b Mode */
62801 +    MODE_11B = 2,   /* 11b Mode */
62802 +    MODE_11GONLY = 3, /* 11g only Mode */
62803 +    MODE_UNKNOWN = 4,
62804 +    MODE_MAX = 4
62805 +} WLAN_PHY_MODE;
62806 +
62807 +typedef enum {
62808 +    WLAN_11A_CAPABILITY   = 1,
62809 +    WLAN_11G_CAPABILITY   = 2,
62810 +    WLAN_11AG_CAPABILITY  = 3,
62811 +}WLAN_CAPABILITY;
62812 +
62813 +#endif /* __ATHDEFS_H__ */
62814 --- /dev/null
62815 +++ b/drivers/ar6000/include/athdrv.h
62816 @@ -0,0 +1,32 @@
62817 +/*
62818 + * Copyright (c) 2004-2006 Atheros Communications Inc.
62819 + * All rights reserved.
62820 + *
62821 + *
62822 + *
62823 + *  This program is free software; you can redistribute it and/or modify
62824 + *  it under the terms of the GNU General Public License version 2 as
62825 + *  published by the Free Software Foundation;
62826 + *
62827 + *  Software distributed under the License is distributed on an "AS
62828 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62829 + *  implied. See the License for the specific language governing
62830 + *  rights and limitations under the License.
62831 + *
62832 + *
62833 + *
62834 + */
62835 +
62836 +#ifndef _ATHDRV_H_
62837 +#define _ATHDRV_H_
62838 +
62839 +#ifdef __cplusplus
62840 +extern "C" {
62841 +#endif
62842 +
62843 +
62844 +#ifdef __cplusplus
62845 +}
62846 +#endif
62847 +
62848 +#endif /* _ATHDRV_H_ */
62849 --- /dev/null
62850 +++ b/drivers/ar6000/include/athendpack.h
62851 @@ -0,0 +1,41 @@
62852 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
62853 + * @file: athendpack.h
62854 + *
62855 + * @abstract: end compiler-specific structure packing
62856 + *
62857 + * Copyright (c) 2004-2007 Atheros Communications Inc.
62858 + * All rights reserved.
62859 + *
62860 + *
62861 + *  This program is free software; you can redistribute it and/or modify
62862 + *  it under the terms of the GNU General Public License version 2 as
62863 + *  published by the Free Software Foundation;
62864 + *
62865 + *  Software distributed under the License is distributed on an "AS
62866 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62867 + *  implied. See the License for the specific language governing
62868 + *  rights and limitations under the License.
62869 + *
62870 + *
62871 + *
62872 + */
62873 +#ifdef VXWORKS
62874 +#endif /* VXWORKS */
62875 +
62876 +#ifdef LINUX
62877 +#endif /* LINUX */
62878 +
62879 +#ifdef QNX
62880 +#endif /* QNX */
62881 +
62882 +#ifdef INTEGRITY
62883 +#include "integrity/athendpack_integrity.h"
62884 +#endif /* INTEGRITY */
62885 +
62886 +#ifdef NUCLEUS
62887 +#endif /* NUCLEUS */
62888 +
62889 +#ifdef UNDER_CE
62890 +#include "../os/wince/include/athendpack_wince.h"
62891 +#endif /* WINCE */
62892 +
62893 --- /dev/null
62894 +++ b/drivers/ar6000/include/athstartpack.h
62895 @@ -0,0 +1,42 @@
62896 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
62897 + * @file: athstartpack.h
62898 + *
62899 + * @abstract: start compiler-specific structure packing
62900 + *
62901 + * Copyright (c) 2004-2007 Atheros Communications Inc.
62902 + * All rights reserved.
62903 + *
62904 + *
62905 + *  This program is free software; you can redistribute it and/or modify
62906 + *  it under the terms of the GNU General Public License version 2 as
62907 + *  published by the Free Software Foundation;
62908 + *
62909 + *  Software distributed under the License is distributed on an "AS
62910 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62911 + *  implied. See the License for the specific language governing
62912 + *  rights and limitations under the License.
62913 + *
62914 + *
62915 + *
62916 + */
62917 +
62918 +#ifdef VXWORKS
62919 +#endif /* VXWORKS */
62920 +
62921 +#ifdef LINUX
62922 +#endif /* LINUX */
62923 +
62924 +#ifdef QNX
62925 +#endif /* QNX */
62926 +
62927 +#ifdef INTEGRITY
62928 +#include "integrity/athstartpack_integrity.h"
62929 +#endif /* INTEGRITY */
62930 +
62931 +#ifdef NUCLEUS
62932 +#endif /* NUCLEUS */
62933 +
62934 +#ifdef UNDER_CE
62935 +#include "../os/wince/include/athstartpack_wince.h"
62936 +#endif /* WINCE */
62937 +
62938 --- /dev/null
62939 +++ b/drivers/ar6000/include/a_types.h
62940 @@ -0,0 +1,28 @@
62941 +#ifndef _A_TYPES_H_
62942 +#define _A_TYPES_H_
62943 +/*
62944 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/a_types.h#1 $
62945 + *
62946 + * This file contains the definitions of the basic atheros data types.
62947 + * It is used to map the data types in atheros files to a platform specific
62948 + * type.
62949 + *
62950 + * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
62951 + *
62952 + *
62953 + *  This program is free software; you can redistribute it and/or modify
62954 + *  it under the terms of the GNU General Public License version 2 as
62955 + *  published by the Free Software Foundation;
62956 + *
62957 + *  Software distributed under the License is distributed on an "AS
62958 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62959 + *  implied. See the License for the specific language governing
62960 + *  rights and limitations under the License.
62961 + *
62962 + *
62963 + *
62964 + */
62965 +
62966 +#include "../ar6000/athtypes_linux.h"
62967 +
62968 +#endif /* _ATHTYPES_H_ */
62969 --- /dev/null
62970 +++ b/drivers/ar6000/include/bmi.h
62971 @@ -0,0 +1,100 @@
62972 +#ifndef _BMI_H_
62973 +#define _BMI_H_
62974 +/*
62975 + * Copyright (c) 2004-2005 Atheros Communications Inc.
62976 + * All rights reserved.
62977 + *
62978 + *
62979 + *  This program is free software; you can redistribute it and/or modify
62980 + *  it under the terms of the GNU General Public License version 2 as
62981 + *  published by the Free Software Foundation;
62982 + *
62983 + *  Software distributed under the License is distributed on an "AS
62984 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62985 + *  implied. See the License for the specific language governing
62986 + *  rights and limitations under the License.
62987 + *
62988 + *
62989 + *
62990 + * BMI declarations and prototypes
62991 + */
62992 +
62993 +#ifdef __cplusplus
62994 +extern "C" {
62995 +#endif /* __cplusplus */
62996 +
62997 +/* Header files */
62998 +#include "a_config.h"
62999 +#include "athdefs.h"
63000 +#include "a_types.h"
63001 +#include "hif.h"
63002 +#include "a_osapi.h"
63003 +#include "bmi_msg.h"
63004 +
63005 +void
63006 +BMIInit(void);
63007 +
63008 +A_STATUS
63009 +BMIDone(HIF_DEVICE *device);
63010 +
63011 +A_STATUS
63012 +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info);
63013 +
63014 +A_STATUS
63015 +BMIReadMemory(HIF_DEVICE *device,
63016 +              A_UINT32 address,
63017 +              A_UCHAR *buffer,
63018 +              A_UINT32 length);
63019 +
63020 +A_STATUS
63021 +BMIWriteMemory(HIF_DEVICE *device,
63022 +               A_UINT32 address,
63023 +               A_UCHAR *buffer,
63024 +               A_UINT32 length);
63025 +
63026 +A_STATUS
63027 +BMIExecute(HIF_DEVICE *device,
63028 +           A_UINT32 address,
63029 +           A_UINT32 *param);
63030 +
63031 +A_STATUS
63032 +BMISetAppStart(HIF_DEVICE *device,
63033 +               A_UINT32 address);
63034 +
63035 +A_STATUS
63036 +BMIReadSOCRegister(HIF_DEVICE *device,
63037 +                   A_UINT32 address,
63038 +                   A_UINT32 *param);
63039 +
63040 +A_STATUS
63041 +BMIWriteSOCRegister(HIF_DEVICE *device,
63042 +                    A_UINT32 address,
63043 +                    A_UINT32 param);
63044 +
63045 +A_STATUS
63046 +BMIrompatchInstall(HIF_DEVICE *device,
63047 +                   A_UINT32 ROM_addr,
63048 +                   A_UINT32 RAM_addr,
63049 +                   A_UINT32 nbytes,
63050 +                   A_UINT32 do_activate,
63051 +                   A_UINT32 *patch_id);
63052 +
63053 +A_STATUS
63054 +BMIrompatchUninstall(HIF_DEVICE *device,
63055 +                     A_UINT32 rompatch_id);
63056 +
63057 +A_STATUS
63058 +BMIrompatchActivate(HIF_DEVICE *device,
63059 +                    A_UINT32 rompatch_count,
63060 +                    A_UINT32 *rompatch_list);
63061 +
63062 +A_STATUS
63063 +BMIrompatchDeactivate(HIF_DEVICE *device,
63064 +                      A_UINT32 rompatch_count,
63065 +                      A_UINT32 *rompatch_list);
63066 +
63067 +#ifdef __cplusplus
63068 +}
63069 +#endif
63070 +
63071 +#endif /* _BMI_H_ */
63072 --- /dev/null
63073 +++ b/drivers/ar6000/include/bmi_msg.h
63074 @@ -0,0 +1,199 @@
63075 +#ifndef __BMI_MSG_H__
63076 +#define __BMI_MSG_H__
63077 +/*
63078 + *
63079 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63080 + * All rights reserved.
63081 + *
63082 + *
63083 + *  This program is free software; you can redistribute it and/or modify
63084 + *  it under the terms of the GNU General Public License version 2 as
63085 + *  published by the Free Software Foundation;
63086 + *
63087 + *  Software distributed under the License is distributed on an "AS
63088 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63089 + *  implied. See the License for the specific language governing
63090 + *  rights and limitations under the License.
63091 + *
63092 + *
63093 + *
63094 + */
63095 +
63096 +/*
63097 + * Bootloader Messaging Interface (BMI)
63098 + *
63099 + * BMI is a very simple messaging interface used during initialization
63100 + * to read memory, write memory, execute code, and to define an
63101 + * application entry PC.
63102 + *
63103 + * It is used to download an application to AR6K, to provide
63104 + * patches to code that is already resident on AR6K, and generally
63105 + * to examine and modify state.  The Host has an opportunity to use
63106 + * BMI only once during bootup.  Once the Host issues a BMI_DONE
63107 + * command, this opportunity ends.
63108 + *
63109 + * The Host writes BMI requests to mailbox0, and reads BMI responses
63110 + * from mailbox0.   BMI requests all begin with a command
63111 + * (see below for specific commands), and are followed by
63112 + * command-specific data.
63113 + *
63114 + * Flow control:
63115 + * The Host can only issue a command once the Target gives it a
63116 + * "BMI Command Credit", using AR6K Counter #4.  As soon as the
63117 + * Target has completed a command, it issues another BMI Command
63118 + * Credit (so the Host can issue the next command).
63119 + *
63120 + * BMI handles all required Target-side cache flushing.
63121 + */
63122 +
63123 +
63124 +/* Maximum data size used for BMI transfers */
63125 +#define BMI_DATASZ_MAX                     32
63126 +
63127 +/* BMI Commands */
63128 +
63129 +#define BMI_NO_COMMAND                      0
63130 +
63131 +#define BMI_DONE                            1
63132 +        /*
63133 +         * Semantics: Host is done using BMI
63134 +         * Request format:
63135 +         *    A_UINT32      command (BMI_DONE)
63136 +         * Response format: none
63137 +         */
63138 +
63139 +#define BMI_READ_MEMORY                     2
63140 +        /*
63141 +         * Semantics: Host reads AR6K memory
63142 +         * Request format:
63143 +         *    A_UINT32      command (BMI_READ_MEMORY)
63144 +         *    A_UINT32      address
63145 +         *    A_UINT32      length, at most BMI_DATASZ_MAX
63146 +         * Response format:
63147 +         *    A_UINT8       data[length]
63148 +         */
63149 +
63150 +#define BMI_WRITE_MEMORY                    3
63151 +        /*
63152 +         * Semantics: Host writes AR6K memory
63153 +         * Request format:
63154 +         *    A_UINT32       command (BMI_WRITE_MEMORY)
63155 +         *    A_UINT32      address
63156 +         *    A_UINT32      length, at most BMI_DATASZ_MAX
63157 +         *    A_UINT8       data[length]
63158 +         * Response format: none
63159 +         */
63160 +
63161 +#define BMI_EXECUTE                         4
63162 +        /*
63163 +         * Semantics: Causes AR6K to execute code
63164 +         * Request format:
63165 +         *    A_UINT32      command (BMI_EXECUTE)
63166 +         *    A_UINT32      address
63167 +         *    A_UINT32      parameter
63168 +         * Response format:
63169 +         *    A_UINT32      return value
63170 +         */
63171 +
63172 +#define BMI_SET_APP_START                   5
63173 +        /*
63174 +         * Semantics: Set Target application starting address
63175 +         * Request format:
63176 +         *    A_UINT32      command (BMI_SET_APP_START)
63177 +         *    A_UINT32      address
63178 +         * Response format: none
63179 +         */
63180 +
63181 +#define BMI_READ_SOC_REGISTER               6
63182 +        /*
63183 +         * Semantics: Read a 32-bit Target SOC register.
63184 +         * Request format:
63185 +         *    A_UINT32      command (BMI_READ_REGISTER)
63186 +         *    A_UINT32      address
63187 +         * Response format:
63188 +         *    A_UINT32      value
63189 +         */
63190 +
63191 +#define BMI_WRITE_SOC_REGISTER              7
63192 +        /*
63193 +         * Semantics: Write a 32-bit Target SOC register.
63194 +         * Request format:
63195 +         *    A_UINT32      command (BMI_WRITE_REGISTER)
63196 +         *    A_UINT32      address
63197 +         *    A_UINT32      value
63198 +         *
63199 +         * Response format: none
63200 +         */
63201 +
63202 +#define BMI_GET_TARGET_ID                  8
63203 +#define BMI_GET_TARGET_INFO                8
63204 +        /*
63205 +         * Semantics: Fetch the 4-byte Target information
63206 +         * Request format:
63207 +         *    A_UINT32      command (BMI_GET_TARGET_ID/INFO)
63208 +         * Response format1 (old firmware):
63209 +         *    A_UINT32      TargetVersionID
63210 +         * Response format2 (newer firmware):
63211 +         *    A_UINT32      TARGET_VERSION_SENTINAL
63212 +         *    struct bmi_target_info;
63213 +         */
63214 +
63215 +struct bmi_target_info {
63216 +    A_UINT32 target_info_byte_count; /* size of this structure */
63217 +    A_UINT32 target_ver;             /* Target Version ID */
63218 +    A_UINT32 target_type;            /* Target type */
63219 +};
63220 +#define TARGET_VERSION_SENTINAL 0xffffffff
63221 +#define TARGET_TYPE_AR6001 1
63222 +#define TARGET_TYPE_AR6002 2
63223 +
63224 +
63225 +#define BMI_ROMPATCH_INSTALL               9
63226 +        /*
63227 +         * Semantics: Install a ROM Patch.
63228 +         * Request format:
63229 +         *    A_UINT32      command (BMI_ROMPATCH_INSTALL)
63230 +         *    A_UINT32      Target ROM Address
63231 +         *    A_UINT32      Target RAM Address
63232 +         *    A_UINT32      Size, in bytes
63233 +         *    A_UINT32      Activate? 1-->activate;
63234 +         *                            0-->install but do not activate
63235 +         * Response format:
63236 +         *    A_UINT32      PatchID
63237 +         */
63238 +
63239 +#define BMI_ROMPATCH_UNINSTALL             10
63240 +        /*
63241 +         * Semantics: Uninstall a previously-installed ROM Patch,
63242 +         * automatically deactivating, if necessary.
63243 +         * Request format:
63244 +         *    A_UINT32      command (BMI_ROMPATCH_UNINSTALL)
63245 +         *    A_UINT32      PatchID
63246 +         *
63247 +         * Response format: none
63248 +         */
63249 +
63250 +#define BMI_ROMPATCH_ACTIVATE              11
63251 +        /*
63252 +         * Semantics: Activate a list of previously-installed ROM Patches.
63253 +         * Request format:
63254 +         *    A_UINT32      command (BMI_ROMPATCH_ACTIVATE)
63255 +         *    A_UINT32      rompatch_count
63256 +         *    A_UINT32      PatchID[rompatch_count]
63257 +         *
63258 +         * Response format: none
63259 +         */
63260 +
63261 +#define BMI_ROMPATCH_DEACTIVATE            12
63262 +        /*
63263 +         * Semantics: Deactivate a list of active ROM Patches.
63264 +         * Request format:
63265 +         *    A_UINT32      command (BMI_ROMPATCH_DEACTIVATE)
63266 +         *    A_UINT32      rompatch_count
63267 +         *    A_UINT32      PatchID[rompatch_count]
63268 +         *
63269 +         * Response format: none
63270 +         */
63271 +
63272 +
63273 +#endif /* __BMI_MSG_H__ */
63274 --- /dev/null
63275 +++ b/drivers/ar6000/include/common_drv.h
63276 @@ -0,0 +1,61 @@
63277 +/*
63278 + *
63279 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63280 + * All rights reserved.
63281 + *
63282 + *
63283 + *  This program is free software; you can redistribute it and/or modify
63284 + *  it under the terms of the GNU General Public License version 2 as
63285 + *  published by the Free Software Foundation;
63286 + *
63287 + *  Software distributed under the License is distributed on an "AS
63288 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63289 + *  implied. See the License for the specific language governing
63290 + *  rights and limitations under the License.
63291 + *
63292 + *
63293 + *
63294 + */
63295 +
63296 +
63297 +#ifndef COMMON_DRV_H_
63298 +#define COMMON_DRV_H_
63299 +
63300 +#include "hif.h"
63301 +#include "htc_packet.h"
63302 +
63303 +
63304 +
63305 +/* structure that is the state information for the default credit distribution callback
63306 + * drivers should instantiate (zero-init as well) this structure in their driver instance
63307 + * and pass it as a context to the HTC credit distribution functions */
63308 +typedef struct _COMMON_CREDIT_STATE_INFO {
63309 +    int TotalAvailableCredits;      /* total credits in the system at startup */
63310 +    int CurrentFreeCredits;         /* credits available in the pool that have not been
63311 +                                       given out to endpoints */
63312 +    HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist;  /* pointer to the lowest priority endpoint dist struct */
63313 +} COMMON_CREDIT_STATE_INFO;
63314 +
63315 +
63316 +/* HTC TX packet tagging definitions */
63317 +#define AR6K_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
63318 +#define AR6K_DATA_PKT_TAG       (AR6K_CONTROL_PKT_TAG + 1)
63319 +
63320 +#ifdef __cplusplus
63321 +extern "C" {
63322 +#endif
63323 +
63324 +/* OS-independent APIs */
63325 +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo);
63326 +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
63327 +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
63328 +A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,  A_UCHAR *data, A_UINT32 length);
63329 +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
63330 +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
63331 +A_STATUS ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice);
63332 +
63333 +#ifdef __cplusplus
63334 +}
63335 +#endif
63336 +
63337 +#endif /*COMMON_DRV_H_*/
63338 --- /dev/null
63339 +++ b/drivers/ar6000/include/dbglog_api.h
63340 @@ -0,0 +1,46 @@
63341 +#ifndef _DBGLOG_API_H_
63342 +#define _DBGLOG_API_H_
63343 +/*
63344 + * Copyright (c) 2004-2006 Atheros Communications Inc.
63345 + * All rights reserved.
63346 + *
63347 + *
63348 + *  This program is free software; you can redistribute it and/or modify
63349 + *  it under the terms of the GNU General Public License version 2 as
63350 + *  published by the Free Software Foundation;
63351 + *
63352 + *  Software distributed under the License is distributed on an "AS
63353 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63354 + *  implied. See the License for the specific language governing
63355 + *  rights and limitations under the License.
63356 + *
63357 + *
63358 + *
63359 + * This file contains host side debug primitives.
63360 + */
63361 +
63362 +#ifdef __cplusplus
63363 +extern "C" {
63364 +#endif
63365 +
63366 +#include "dbglog.h"
63367 +
63368 +#define DBGLOG_HOST_LOG_BUFFER_SIZE            DBGLOG_LOG_BUFFER_SIZE
63369 +
63370 +#define DBGLOG_GET_DBGID(arg) \
63371 +    ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
63372 +
63373 +#define DBGLOG_GET_MODULEID(arg) \
63374 +    ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
63375 +
63376 +#define DBGLOG_GET_NUMARGS(arg) \
63377 +    ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
63378 +
63379 +#define DBGLOG_GET_TIMESTAMP(arg) \
63380 +    ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
63381 +
63382 +#ifdef __cplusplus
63383 +}
63384 +#endif
63385 +
63386 +#endif /* _DBGLOG_API_H_ */
63387 --- /dev/null
63388 +++ b/drivers/ar6000/include/dbglog.h
63389 @@ -0,0 +1,107 @@
63390 +/*
63391 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63392 + * All rights reserved.
63393 + *
63394 + * $ATH_LICENSE_HOSTSDK0_C$
63395 + *
63396 + * This file contains the definitions and data structures associated with
63397 + * the log based debug mechanism.
63398 + *
63399 + */
63400 +
63401 +#ifndef _DBGLOG_H_
63402 +#define _DBGLOG_H_
63403 +
63404 +#ifdef __cplusplus
63405 +extern "C" {
63406 +#endif
63407 +
63408 +#define DBGLOG_TIMESTAMP_OFFSET          0
63409 +#define DBGLOG_TIMESTAMP_MASK            0x0000FFFF /* Bit 0-15. Contains bit
63410 +                                                       8-23 of the LF0 timer */
63411 +#define DBGLOG_DBGID_OFFSET              16
63412 +#define DBGLOG_DBGID_MASK                0x03FF0000 /* Bit 16-25 */
63413 +#define DBGLOG_DBGID_NUM_MAX             256 /* Upper limit is width of mask */
63414 +
63415 +#define DBGLOG_MODULEID_OFFSET           26
63416 +#define DBGLOG_MODULEID_MASK             0x3C000000 /* Bit 26-29 */
63417 +#define DBGLOG_MODULEID_NUM_MAX          16 /* Upper limit is width of mask */
63418 +
63419 +/*
63420 + * Please ensure that the definition of any new module intrduced is captured
63421 + * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The
63422 + * structure is required for the parser to correctly pick up the values for
63423 + * different modules.
63424 + */
63425 +#define DBGLOG_MODULEID_START
63426 +#define DBGLOG_MODULEID_INF                   0
63427 +#define DBGLOG_MODULEID_WMI                   1
63428 +#define DBGLOG_MODULEID_CSERV                 2
63429 +#define DBGLOG_MODULEID_PM                    3
63430 +#define DBGLOG_MODULEID_TXRX_MGMTBUF          4
63431 +#define DBGLOG_MODULEID_TXRX_TXBUF            5
63432 +#define DBGLOG_MODULEID_TXRX_RXBUF            6
63433 +#define DBGLOG_MODULEID_WOW                   7
63434 +#define DBGLOG_MODULEID_WHAL                  8
63435 +#define DBGLOG_MODULEID_END
63436 +
63437 +#define DBGLOG_NUM_ARGS_OFFSET             30
63438 +#define DBGLOG_NUM_ARGS_MASK               0xC0000000 /* Bit 30-31 */
63439 +#define DBGLOG_NUM_ARGS_MAX                2 /* Upper limit is width of mask */
63440 +
63441 +#define DBGLOG_MODULE_LOG_ENABLE_OFFSET    0
63442 +#define DBGLOG_MODULE_LOG_ENABLE_MASK      0x0000FFFF
63443 +
63444 +#define DBGLOG_REPORTING_ENABLED_OFFSET    16
63445 +#define DBGLOG_REPORTING_ENABLED_MASK      0x00010000
63446 +
63447 +#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17
63448 +#define DBGLOG_TIMESTAMP_RESOLUTION_MASK   0x000E0000
63449 +
63450 +#define DBGLOG_REPORT_SIZE_OFFSET          20
63451 +#define DBGLOG_REPORT_SIZE_MASK            0x3FF00000
63452 +
63453 +#define DBGLOG_LOG_BUFFER_SIZE             1500
63454 +#define DBGLOG_DBGID_DEFINITION_LEN_MAX    64
63455 +
63456 +struct dbglog_buf_s {
63457 +    struct dbglog_buf_s *next;
63458 +    A_INT8              *buffer;
63459 +    A_UINT32             bufsize;
63460 +    A_UINT32             length;
63461 +    A_UINT32             count;
63462 +    A_UINT32             free;
63463 +};
63464 +
63465 +struct dbglog_hdr_s {
63466 +    struct dbglog_buf_s *dbuf;
63467 +    A_UINT32             dropped;
63468 +};
63469 +
63470 +struct dbglog_config_s {
63471 +    A_UINT32                    cfgvalid; /* Mask with valid config bits */
63472 +    union {
63473 +        /* TODO: Take care of endianness */
63474 +        struct {
63475 +            A_UINT32            mmask:16; /* Mask of modules with logging on */
63476 +            A_UINT32            rep:1; /* Reporting enabled or not */
63477 +            A_UINT32            tsr:3; /* Time stamp resolution. Def: 1 ms */
63478 +            A_UINT32            size:10; /* Report size in number of messages */
63479 +            A_UINT32            reserved:2;
63480 +        } dbglog_config;
63481 +
63482 +        A_UINT32                value;
63483 +    } u;
63484 +};
63485 +
63486 +#define cfgmmask                   u.dbglog_config.mmask
63487 +#define cfgrep                     u.dbglog_config.rep
63488 +#define cfgtsr                     u.dbglog_config.tsr
63489 +#define cfgsize                    u.dbglog_config.size
63490 +#define cfgvalue                   u.value
63491 +
63492 +#ifdef __cplusplus
63493 +}
63494 +#endif
63495 +
63496 +#endif /* _DBGLOG_H_ */
63497 --- /dev/null
63498 +++ b/drivers/ar6000/include/dbglog_id.h
63499 @@ -0,0 +1,307 @@
63500 +/*
63501 + *
63502 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63503 + * All rights reserved.
63504 + *
63505 + * $ATH_LICENSE_HOSTSDK0_C$
63506 + *
63507 + * This file contains the definitions of the debug identifiers for different
63508 + * modules.
63509 + *
63510 + */
63511 +
63512 +#ifndef _DBGLOG_ID_H_
63513 +#define _DBGLOG_ID_H_
63514 +
63515 +#ifdef __cplusplus
63516 +extern "C" {
63517 +#endif
63518 +
63519 +/*
63520 + * The nomenclature for the debug identifiers is MODULE_DESCRIPTION.
63521 + * Please ensure that the definition of any new debugid introduced is captured
63522 + * between the <MODULE>_DBGID_DEFINITION_START and
63523 + * <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the
63524 + * parser to correctly pick up the values for different debug identifiers.
63525 + */
63526 +
63527 +/* INF debug identifier definitions */
63528 +#define INF_DBGID_DEFINITION_START
63529 +#define INF_ASSERTION_FAILED                          1
63530 +#define INF_TARGET_ID                                 2
63531 +#define INF_DBGID_DEFINITION_END
63532 +
63533 +/* WMI debug identifier definitions */
63534 +#define WMI_DBGID_DEFINITION_START
63535 +#define WMI_CMD_RX_XTND_PKT_TOO_SHORT                 1
63536 +#define WMI_EXTENDED_CMD_NOT_HANDLED                  2
63537 +#define WMI_CMD_RX_PKT_TOO_SHORT                      3
63538 +#define WMI_CALLING_WMI_EXTENSION_FN                  4
63539 +#define WMI_CMD_NOT_HANDLED                           5
63540 +#define WMI_IN_SYNC                                   6
63541 +#define WMI_TARGET_WMI_SYNC_CMD                       7
63542 +#define WMI_SET_SNR_THRESHOLD_PARAMS                  8
63543 +#define WMI_SET_RSSI_THRESHOLD_PARAMS                 9
63544 +#define WMI_SET_LQ_TRESHOLD_PARAMS                   10
63545 +#define WMI_TARGET_CREATE_PSTREAM_CMD                11
63546 +#define WMI_WI_DTM_INUSE                             12
63547 +#define WMI_TARGET_DELETE_PSTREAM_CMD                13
63548 +#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD       14
63549 +#define WMI_TARGET_GET_BIT_RATE_CMD                  15
63550 +#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS       16
63551 +#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD        17
63552 +#define WMI_TARGET_GET_TX_PWR_CMD                    18
63553 +#define WMI_FREE_EVBUF_WMIBUF                        19
63554 +#define WMI_FREE_EVBUF_DATABUF                       20
63555 +#define WMI_FREE_EVBUF_BADFLAG                       21
63556 +#define WMI_HTC_RX_ERROR_DATA_PACKET                 22
63557 +#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX             23
63558 +#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT      24
63559 +#define WMI_SENDING_READY_EVENT                      25
63560 +#define WMI_SETPOWER_MDOE_TO_MAXPERF                 26
63561 +#define WMI_SETPOWER_MDOE_TO_REC                     27
63562 +#define WMI_BSSINFO_EVENT_FROM                       28
63563 +#define WMI_TARGET_GET_STATS_CMD                     29
63564 +#define WMI_SENDING_SCAN_COMPLETE_EVENT              30
63565 +#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT        31
63566 +#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT       32
63567 +#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT     33
63568 +#define WMI_SENDING_ERROR_REPORT_EVENT               34
63569 +#define WMI_SENDING_CAC_EVENT                        35
63570 +#define WMI_TARGET_GET_ROAM_TABLE_CMD                36
63571 +#define WMI_TARGET_GET_ROAM_DATA_CMD                 37
63572 +#define WMI_SENDING_GPIO_INTR_EVENT                  38
63573 +#define WMI_SENDING_GPIO_ACK_EVENT                   39
63574 +#define WMI_SENDING_GPIO_DATA_EVENT                  40
63575 +#define WMI_CMD_RX                                   41
63576 +#define WMI_CMD_RX_XTND                              42
63577 +#define WMI_EVENT_SEND                               43
63578 +#define WMI_EVENT_SEND_XTND                          44
63579 +#define WMI_DBGID_DEFINITION_END
63580 +
63581 +/* CSERV debug identifier definitions */
63582 +#define CSERV_DBGID_DEFINITION_START
63583 +#define CSERV_BEGIN_SCAN1                             1
63584 +#define CSERV_BEGIN_SCAN2                             2
63585 +#define CSERV_END_SCAN1                               3
63586 +#define CSERV_END_SCAN2                               4
63587 +#define CSERV_CHAN_SCAN_START                         5
63588 +#define CSERV_CHAN_SCAN_STOP                          6
63589 +#define CSERV_CHANNEL_OPPPORTUNITY                    7
63590 +#define CSERV_NC_TIMEOUT                              8
63591 +#define CSERV_BACK_HOME                              10
63592 +#define CSERV_CHMGR_CH_CALLBACK1                     11
63593 +#define CSERV_CHMGR_CH_CALLBACK2                     12
63594 +#define CSERV_CHMGR_CH_CALLBACK3                     13
63595 +#define CSERV_SET_SCAN_PARAMS1                       14
63596 +#define CSERV_SET_SCAN_PARAMS2                       15
63597 +#define CSERV_SET_SCAN_PARAMS3                       16
63598 +#define CSERV_SET_SCAN_PARAMS4                       17
63599 +#define CSERV_ABORT_SCAN                             18
63600 +#define CSERV_NEWSTATE                               19
63601 +#define CSERV_MINCHMGR_OP_END                        20
63602 +#define CSERV_CHMGR_OP_END                           21
63603 +#define CSERV_DISCONNECT_TIMEOUT                     22
63604 +#define CSERV_ROAM_TIMEOUT                           23
63605 +#define CSERV_FORCE_SCAN1                            24
63606 +#define CSERV_FORCE_SCAN2                            25
63607 +#define CSERV_FORCE_SCAN3                            26
63608 +#define CSERV_UTIL_TIMEOUT                           27
63609 +#define CSERV_RSSIPOLLER                             28
63610 +#define CSERV_RETRY_CONNECT_TIMEOUT                  29
63611 +#define CSERV_RSSIINDBMPOLLER                        30
63612 +#define CSERV_BGSCAN_ENABLE                          31
63613 +#define CSERV_BGSCAN_DISABLE                         32
63614 +#define CSERV_WLAN_START_SCAN_CMD1                   33
63615 +#define CSERV_WLAN_START_SCAN_CMD2                   34
63616 +#define CSERV_WLAN_START_SCAN_CMD3                   35
63617 +#define CSERV_START_SCAN_CMD                         36
63618 +#define CSERV_START_FORCE_SCAN                       37
63619 +#define CSERV_NEXT_CHAN                              38
63620 +#define CSERV_SET_REGCODE                            39
63621 +#define CSERV_START_ADHOC                            40
63622 +#define CSERV_ADHOC_AT_HOME                          41
63623 +#define CSERV_OPT_AT_HOME                            42
63624 +#define CSERV_WLAN_CONNECT_CMD                       43
63625 +#define CSERV_WLAN_RECONNECT_CMD                     44
63626 +#define CSERV_WLAN_DISCONNECT_CMD                    45
63627 +#define CSERV_BSS_CHANGE_CHANNEL                     46
63628 +#define CSERV_BEACON_RX                              47
63629 +#define CSERV_KEEPALIVE_CHECK                        48
63630 +#define CSERV_RC_BEGIN_SCAN                          49
63631 +#define CSERV_RC_SCAN_START                          50
63632 +#define CSERV_RC_SCAN_STOP                           51
63633 +#define CSERV_RC_NEXT                                52
63634 +#define CSERV_RC_SCAN_END                            53
63635 +#define CSERV_PROBE_CALLBACK                         54
63636 +#define CSERV_ROAM1                                  55
63637 +#define CSERV_ROAM2                                  56
63638 +#define CSERV_ROAM3                                  57
63639 +#define CSERV_CONNECT_EVENT                          58
63640 +#define CSERV_DISCONNECT_EVENT                       59
63641 +#define CSERV_BMISS_HANDLER1                         60
63642 +#define CSERV_BMISS_HANDLER2                         61
63643 +#define CSERV_BMISS_HANDLER3                         62
63644 +#define CSERV_LOWRSSI_HANDLER                        63
63645 +#define CSERV_WLAN_SET_PMKID_CMD                     64
63646 +#define CSERV_RECONNECT_REQUEST                      65
63647 +#define CSERV_KEYSPLUMBED_EVENT                      66
63648 +#define CSERV_NEW_REG                                67
63649 +#define CSERV_SET_RSSI_THOLD                         68
63650 +#define CSERV_RSSITHRESHOLDCHECK                     69
63651 +#define CSERV_RSSIINDBMTHRESHOLDCHECK                70
63652 +#define CSERV_WLAN_SET_OPT_CMD1                      71
63653 +#define CSERV_WLAN_SET_OPT_CMD2                      72
63654 +#define CSERV_WLAN_SET_OPT_CMD3                      73
63655 +#define CSERV_WLAN_SET_OPT_CMD4                      74
63656 +#define CSERV_SCAN_CONNECT_STOP                      75
63657 +#define CSERV_BMISS_HANDLER4                         76
63658 +#define CSERV_INITIALIZE_TIMER                       77
63659 +#define CSERV_ARM_TIMER                              78
63660 +#define CSERV_DISARM_TIMER                           79
63661 +#define CSERV_UNINITIALIZE_TIMER                     80
63662 +#define CSERV_DISCONNECT_EVENT2                      81
63663 +#define CSERV_SCAN_CONNECT_START                     82
63664 +#define CSERV_BSSINFO_MEMORY_ALLOC_FAILED            83
63665 +#define CSERV_SET_SCAN_PARAMS5                       84
63666 +#define CSERV_DBGID_DEFINITION_END
63667 +
63668 +/* TXRX debug identifier definitions */
63669 +#define TXRX_TXBUF_DBGID_DEFINITION_START
63670 +#define TXRX_TXBUF_ALLOCATE_BUF                      1
63671 +#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX                 2
63672 +#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ                  3
63673 +#define TXRX_TXBUF_TXQ_DEPTH                         4
63674 +#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ                 5
63675 +#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ         6
63676 +#define TXRX_TXBUF_INITIALIZE_TIMER                  7
63677 +#define TXRX_TXBUF_ARM_TIMER                         8
63678 +#define TXRX_TXBUF_DISARM_TIMER                      9
63679 +#define TXRX_TXBUF_UNINITIALIZE_TIMER                10
63680 +#define TXRX_TXBUF_DBGID_DEFINITION_END
63681 +
63682 +#define TXRX_RXBUF_DBGID_DEFINITION_START
63683 +#define TXRX_RXBUF_ALLOCATE_BUF                      1
63684 +#define TXRX_RXBUF_QUEUE_TO_HOST                     2
63685 +#define TXRX_RXBUF_QUEUE_TO_WLAN                     3
63686 +#define TXRX_RXBUF_ZERO_LEN_BUF                      4
63687 +#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN  5
63688 +#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF        6
63689 +#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN         7
63690 +#define TXRX_RXBUF_SEND_TO_RECV_MGMT                 8
63691 +#define TXRX_RXBUF_SEND_TO_IEEE_LAYER                9
63692 +#define TXRX_RXBUF_DBGID_DEFINITION_END
63693 +
63694 +#define TXRX_MGMTBUF_DBGID_DEFINITION_START
63695 +#define TXRX_MGMTBUF_ALLOCATE_BUF                    1
63696 +#define TXRX_MGMTBUF_ALLOCATE_SM_BUF                 2
63697 +#define TXRX_MGMTBUF_ALLOCATE_RMBUF                  3
63698 +#define TXRX_MGMTBUF_GET_BUF                         4
63699 +#define TXRX_MGMTBUF_GET_SM_BUF                      5
63700 +#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ                6
63701 +#define TXRX_MGMTBUF_REAPED_BUF                      7
63702 +#define TXRX_MGMTBUF_REAPED_SM_BUF                   8
63703 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN              9
63704 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN          10
63705 +#define TXRX_MGMTBUF_ENQUEUE_INTO_SFQ                11
63706 +#define TXRX_MGMTBUF_DEQUEUE_FROM_SFQ                12
63707 +#define TXRX_MGMTBUF_PAUSE_TXQ                       13
63708 +#define TXRX_MGMTBUF_RESUME_TXQ                      14
63709 +#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT       15
63710 +#define TXRX_MGMTBUF_DRAINQ                          16
63711 +#define TXRX_MGMTBUF_INDICATE_Q_DRAINED              17
63712 +#define TXRX_MGMTBUF_DBGID_DEFINITION_END
63713 +
63714 +/* PM (Power Module) debug identifier definitions */
63715 +#define PM_DBGID_DEFINITION_START
63716 +#define PM_INIT                                      1
63717 +#define PM_ENABLE                                    2
63718 +#define PM_SET_STATE                                 3
63719 +#define PM_SET_POWERMODE                             4
63720 +#define PM_CONN_NOTIFY                               5
63721 +#define PM_REF_COUNT_NEGATIVE                        6
63722 +#define PM_APSD_ENABLE                               7
63723 +#define PM_UPDATE_APSD_STATE                         8
63724 +#define PM_CHAN_OP_REQ                               9
63725 +#define PM_SET_MY_BEACON_POLICY                      10
63726 +#define PM_SET_ALL_BEACON_POLICY                     11
63727 +#define PM_SET_PM_PARAMS1                            12
63728 +#define PM_SET_PM_PARAMS2                            13
63729 +#define PM_ADHOC_SET_PM_CAPS_FAIL                    14
63730 +#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID              15
63731 +#define PM_DBGID_DEFINITION_END
63732 +
63733 +/* Wake on Wireless debug identifier definitions */
63734 +#define WOW_DBGID_DEFINITION_START
63735 +#define WOW_INIT                                        1
63736 +#define WOW_GET_CONFIG_DSET                             2
63737 +#define WOW_NO_CONFIG_DSET                              3
63738 +#define WOW_INVALID_CONFIG_DSET                         4
63739 +#define WOW_USE_DEFAULT_CONFIG                          5
63740 +#define WOW_SETUP_GPIO                                  6
63741 +#define WOW_INIT_DONE                                   7
63742 +#define WOW_SET_GPIO_PIN                                8
63743 +#define WOW_CLEAR_GPIO_PIN                              9
63744 +#define WOW_SET_WOW_MODE_CMD                            10
63745 +#define WOW_SET_HOST_MODE_CMD                           11
63746 +#define WOW_ADD_WOW_PATTERN_CMD                         12
63747 +#define WOW_NEW_WOW_PATTERN_AT_INDEX                    13
63748 +#define WOW_DEL_WOW_PATTERN_CMD                         14
63749 +#define WOW_LIST_CONTAINS_PATTERNS                      15
63750 +#define WOW_GET_WOW_LIST_CMD                            16
63751 +#define WOW_INVALID_FILTER_ID                           17
63752 +#define WOW_INVALID_FILTER_LISTID                       18
63753 +#define WOW_NO_VALID_FILTER_AT_ID                       19
63754 +#define WOW_NO_VALID_LIST_AT_ID                         20
63755 +#define WOW_NUM_PATTERNS_EXCEEDED                       21
63756 +#define WOW_NUM_LISTS_EXCEEDED                          22
63757 +#define WOW_GET_WOW_STATS                               23
63758 +#define WOW_CLEAR_WOW_STATS                             24
63759 +#define WOW_WAKEUP_HOST                                 25
63760 +#define WOW_EVENT_WAKEUP_HOST                           26
63761 +#define WOW_EVENT_DISCARD                               27
63762 +#define WOW_PATTERN_MATCH                               28
63763 +#define WOW_PATTERN_NOT_MATCH                           29
63764 +#define WOW_PATTERN_NOT_MATCH_OFFSET                    30
63765 +#define WOW_DISABLED_HOST_ASLEEP                        31
63766 +#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS             32
63767 +#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND          33
63768 +#define WOW_DBGID_DEFINITION_END
63769 +
63770 +/* WHAL debug identifier definitions */
63771 +#define WHAL_DBGID_DEFINITION_START
63772 +#define WHAL_ERROR_ANI_CONTROL                      1
63773 +#define WHAL_ERROR_CHIP_TEST1                       2
63774 +#define WHAL_ERROR_CHIP_TEST2                       3
63775 +#define WHAL_ERROR_EEPROM_CHECKSUM                  4
63776 +#define WHAL_ERROR_EEPROM_MACADDR                   5
63777 +#define WHAL_ERROR_INTERRUPT_HIU                    6
63778 +#define WHAL_ERROR_KEYCACHE_RESET                   7
63779 +#define WHAL_ERROR_KEYCACHE_SET                     8
63780 +#define WHAL_ERROR_KEYCACHE_TYPE                    9
63781 +#define WHAL_ERROR_KEYCACHE_TKIPENTRY              10
63782 +#define WHAL_ERROR_KEYCACHE_WEPLENGTH              11
63783 +#define WHAL_ERROR_PHY_INVALID_CHANNEL             12
63784 +#define WHAL_ERROR_POWER_AWAKE                     13
63785 +#define WHAL_ERROR_POWER_SET                       14
63786 +#define WHAL_ERROR_RECV_STOPDMA                    15
63787 +#define WHAL_ERROR_RECV_STOPPCU                    16
63788 +#define WHAL_ERROR_RESET_CHANNF1                   17
63789 +#define WHAL_ERROR_RESET_CHANNF2                   18
63790 +#define WHAL_ERROR_RESET_PM                        19
63791 +#define WHAL_ERROR_RESET_OFFSETCAL                 20
63792 +#define WHAL_ERROR_RESET_RFGRANT                   21
63793 +#define WHAL_ERROR_RESET_RXFRAME                   22
63794 +#define WHAL_ERROR_RESET_STOPDMA                   23
63795 +#define WHAL_ERROR_RESET_RECOVER                   24
63796 +#define WHAL_ERROR_XMIT_COMPUTE                    25
63797 +#define WHAL_ERROR_XMIT_NOQUEUE                    26
63798 +#define WHAL_ERROR_XMIT_ACTIVEQUEUE                27
63799 +#define WHAL_ERROR_XMIT_BADTYPE                    28
63800 +#define WHAL_DBGID_DEFINITION_END
63801 +
63802 +#ifdef __cplusplus
63803 +}
63804 +#endif
63805 +
63806 +#endif /* _DBGLOG_ID_H_ */
63807 --- /dev/null
63808 +++ b/drivers/ar6000/include/dl_list.h
63809 @@ -0,0 +1,114 @@
63810 +/*
63811 + *
63812 + * Double-link list definitions (adapted from Atheros SDIO stack)
63813 + *
63814 + * Copyright (c) 2007 Atheros Communications Inc.
63815 + * All rights reserved.
63816 + *
63817 + *
63818 + *  This program is free software; you can redistribute it and/or modify
63819 + *  it under the terms of the GNU General Public License version 2 as
63820 + *  published by the Free Software Foundation;
63821 + *
63822 + *  Software distributed under the License is distributed on an "AS
63823 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63824 + *  implied. See the License for the specific language governing
63825 + *  rights and limitations under the License.
63826 + *
63827 + *
63828 + *
63829 + */
63830 +#ifndef __DL_LIST_H___
63831 +#define __DL_LIST_H___
63832 +
63833 +#define A_CONTAINING_STRUCT(address, struct_type, field_name)\
63834 +            ((struct_type *)((A_UINT32)(address) - (A_UINT32)(&((struct_type *)0)->field_name)))
63835 +
63836 +/* list functions */
63837 +/* pointers for the list */
63838 +typedef struct _DL_LIST {
63839 +    struct _DL_LIST *pPrev;
63840 +    struct _DL_LIST *pNext;
63841 +}DL_LIST, *PDL_LIST;
63842 +/*
63843 + * DL_LIST_INIT , initialize doubly linked list
63844 +*/
63845 +#define DL_LIST_INIT(pList)\
63846 +    {(pList)->pPrev = pList; (pList)->pNext = pList;}
63847 +
63848 +#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList)))
63849 +#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext
63850 +#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev
63851 +/*
63852 + * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member
63853 + * NOT: do not use this function if the items in the list are deleted inside the
63854 + * iteration loop
63855 +*/
63856 +#define ITERATE_OVER_LIST(pStart, pTemp) \
63857 +    for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext)
63858 +
63859 +
63860 +/* safe iterate macro that allows the item to be removed from the list
63861 + * the iteration continues to the next item in the list
63862 + */
63863 +#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset)  \
63864 +{                                                       \
63865 +    PDL_LIST  pTemp;                                     \
63866 +    pTemp = (pStart)->pNext;                            \
63867 +    while (pTemp != (pStart)) {                         \
63868 +        (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset);   \
63869 +         pTemp = pTemp->pNext;                          \
63870 +
63871 +#define ITERATE_END }}
63872 +
63873 +/*
63874 + * DL_ListInsertTail - insert pAdd to the end of the list
63875 +*/
63876 +static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) {
63877 +        /* insert at tail */
63878 +    pAdd->pPrev = pList->pPrev;
63879 +    pAdd->pNext = pList;
63880 +    pList->pPrev->pNext = pAdd;
63881 +    pList->pPrev = pAdd;
63882 +    return pAdd;
63883 +}
63884 +
63885 +/*
63886 + * DL_ListInsertHead - insert pAdd into the head of the list
63887 +*/
63888 +static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) {
63889 +        /* insert at head */
63890 +    pAdd->pPrev = pList;
63891 +    pAdd->pNext = pList->pNext;
63892 +    pList->pNext->pPrev = pAdd;
63893 +    pList->pNext = pAdd;
63894 +    return pAdd;
63895 +}
63896 +
63897 +#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem))
63898 +/*
63899 + * DL_ListRemove - remove pDel from list
63900 +*/
63901 +static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) {
63902 +    pDel->pNext->pPrev = pDel->pPrev;
63903 +    pDel->pPrev->pNext = pDel->pNext;
63904 +        /* point back to itself just to be safe, incase remove is called again */
63905 +    pDel->pNext = pDel;
63906 +    pDel->pPrev = pDel;
63907 +    return pDel;
63908 +}
63909 +
63910 +/*
63911 + * DL_ListRemoveItemFromHead - get a list item from the head
63912 +*/
63913 +static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) {
63914 +    PDL_LIST pItem = NULL;
63915 +    if (pList->pNext != pList) {
63916 +        pItem = pList->pNext;
63917 +            /* remove the first item from head */
63918 +        DL_ListRemove(pItem);
63919 +    }
63920 +    return pItem;
63921 +}
63922 +
63923 +#endif /* __DL_LIST_H___ */
63924 --- /dev/null
63925 +++ b/drivers/ar6000/include/dset_api.h
63926 @@ -0,0 +1,63 @@
63927 +/*
63928 + * Copyright (c) 2004-2006 Atheros Communications Inc.
63929 + * All rights reserved.
63930 + *
63931 + *
63932 + *  This program is free software; you can redistribute it and/or modify
63933 + *  it under the terms of the GNU General Public License version 2 as
63934 + *  published by the Free Software Foundation;
63935 + *
63936 + *  Software distributed under the License is distributed on an "AS
63937 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63938 + *  implied. See the License for the specific language governing
63939 + *  rights and limitations under the License.
63940 + *
63941 + *
63942 + *
63943 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/dset_api.h#1 $
63944 + *
63945 + * Host-side DataSet API.
63946 + *
63947 + */
63948 +
63949 +#ifndef _DSET_API_H_
63950 +#define _DSET_API_H_
63951 +
63952 +#ifdef __cplusplus
63953 +extern "C" {
63954 +#endif /* __cplusplus */
63955 +
63956 +/*
63957 + * Host-side DataSet support is optional, and is not
63958 + * currently required for correct operation.  To disable
63959 + * Host-side DataSet support, set this to 0.
63960 + */
63961 +#ifndef CONFIG_HOST_DSET_SUPPORT
63962 +#define CONFIG_HOST_DSET_SUPPORT 1
63963 +#endif
63964 +
63965 +/* Called to send a DataSet Open Reply back to the Target. */
63966 +A_STATUS wmi_dset_open_reply(struct wmi_t *wmip,
63967 +                             A_UINT32 status,
63968 +                             A_UINT32 access_cookie,
63969 +                             A_UINT32 size,
63970 +                             A_UINT32 version,
63971 +                             A_UINT32 targ_handle,
63972 +                             A_UINT32 targ_reply_fn,
63973 +                             A_UINT32 targ_reply_arg);
63974 +
63975 +/* Called to send a DataSet Data Reply back to the Target. */
63976 +A_STATUS wmi_dset_data_reply(struct wmi_t *wmip,
63977 +                             A_UINT32 status,
63978 +                             A_UINT8 *host_buf,
63979 +                             A_UINT32 length,
63980 +                             A_UINT32 targ_buf,
63981 +                             A_UINT32 targ_reply_fn,
63982 +                             A_UINT32 targ_reply_arg);
63983 +
63984 +#ifdef __cplusplus
63985 +}
63986 +#endif /* __cplusplus */
63987 +
63988 +
63989 +#endif /* _DSET_API_H_ */
63990 --- /dev/null
63991 +++ b/drivers/ar6000/include/dsetid.h
63992 @@ -0,0 +1,110 @@
63993 +/*
63994 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63995 + * All rights reserved.
63996 + *
63997 + * $ATH_LICENSE_HOSTSDK0_C$
63998 + *
63999 + */
64000 +
64001 +#ifndef __DSETID_H__
64002 +#define __DSETID_H__
64003 +
64004 +/* Well-known DataSet IDs */
64005 +#define DSETID_UNUSED                     0x00000000
64006 +#define DSETID_BOARD_DATA                 0x00000001 /* Cal and board data */
64007 +#define DSETID_REGDB                      0x00000002 /* Regulatory Database */
64008 +#define DSETID_POWER_CONTROL              0x00000003 /* TX Pwr Lim & Ant Gain */
64009 +#define DSETID_USER_CONFIG                0x00000004 /* User Configuration */
64010 +
64011 +#define DSETID_ANALOG_CONTROL_DATA_START  0x00000005
64012 +#define DSETID_ANALOG_CONTROL_DATA_END    0x00000025
64013 +/*
64014 + * Get DSETID for various reference clock speeds.
64015 + * For each speed there are three DataSets that correspond
64016 + * to the three columns of bank6 data (addr, 11a, 11b/g).
64017 + * This macro returns the dsetid of the first of those
64018 + * three DataSets.
64019 + */
64020 +#define ANALOG_CONTROL_DATA_DSETID(refclk) \
64021 +        (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk)
64022 +
64023 +/*
64024 + * There are TWO STARTUP_PATCH DataSets.
64025 + * DSETID_STARTUP_PATCH is historical, and was applied before BMI on
64026 + * earlier systems.  On AR6002, it is applied after BMI, just like
64027 + * DSETID_STARTUP_PATCH2.
64028 + */
64029 +#define DSETID_STARTUP_PATCH              0x00000026
64030 +#define DSETID_GPIO_CONFIG_PATCH          0x00000027
64031 +#define DSETID_WLANREGS                   0x00000028 /* override wlan regs */
64032 +#define DSETID_STARTUP_PATCH2             0x00000029
64033 +
64034 +#define DSETID_WOW_CONFIG                 0x00000090 /* WoW Configuration */
64035 +
64036 +/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */
64037 +#define DSETID_INI_DATA                   0x00000100
64038 +/* Reserved for WHAL INI Tables: 0x100..0x11f */
64039 +#define DSETID_INI_DATA_END               0x0000011f
64040 +
64041 +#define DSETID_VENDOR_START               0x00010000 /* Vendor-defined DataSets */
64042 +
64043 +#define DSETID_INDEX_END                  0xfffffffe /* Reserved to indicate the
64044 +                                                        end of a memory-based
64045 +                                                        DataSet Index */
64046 +#define DSETID_INDEX_FREE                 0xffffffff /* An unused index entry */
64047 +
64048 +/*
64049 + * PATCH DataSet format:
64050 + * A list of patches, terminated by a patch with
64051 + * address=PATCH_END.
64052 + *
64053 + * This allows for patches to be stored in flash.
64054 + */
64055 +struct patch_s {
64056 +    A_UINT32 *address;
64057 +    A_UINT32  data;
64058 +};
64059 +
64060 +/*
64061 + * Skip some patches.  Can be used to erase a single patch in a
64062 + * patch DataSet without having to re-write the DataSet.  May
64063 + * also be used to embed information for use by subsequent
64064 + * patch code.  The "data" in a PATCH_SKIP tells how many
64065 + * bytes of length "patch_s" to skip.
64066 + */
64067 +#define PATCH_SKIP      ((A_UINT32 *)0x00000000)
64068 +
64069 +/*
64070 + * Execute code at the address specified by "data".
64071 + * The address of the patch structure is passed as
64072 + * the one parameter.
64073 + */
64074 +#define PATCH_CODE_ABS  ((A_UINT32 *)0x00000001)
64075 +
64076 +/*
64077 + * Same as PATCH_CODE_ABS, but treat "data" as an
64078 + * offset from the start of the patch word.
64079 + */
64080 +#define PATCH_CODE_REL  ((A_UINT32 *)0x00000002)
64081 +
64082 +/* Mark the end of this patch DataSet. */
64083 +#define PATCH_END       ((A_UINT32 *)0xffffffff)
64084 +
64085 +/*
64086 + * A DataSet which contains a Binary Patch to some other DataSet
64087 + * uses the original dsetid with the DSETID_BPATCH_FLAG bit set.
64088 + * Such a BPatch DataSet consists of BPatch metadata followed by
64089 + * the bdiff bytes.  BPatch metadata consists of a single 32-bit
64090 + * word that contains the size of the BPatched final image.
64091 + *
64092 + * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff
64093 + * to create "diffs":
64094 + *  bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs
64095 + * Then add BPatch metadata to the start of "diffs".
64096 + *
64097 + * NB: There are some implementation-induced restrictions
64098 + * on which DataSets can be BPatched.
64099 + */
64100 +#define DSETID_BPATCH_FLAG                0x80000000
64101 +
64102 +#endif /* __DSETID_H__ */
64103 --- /dev/null
64104 +++ b/drivers/ar6000/include/dset_internal.h
64105 @@ -0,0 +1,39 @@
64106 +/*
64107 + * Copyright (c) 2007 Atheros Communications Inc.
64108 + * All rights reserved.
64109 + *
64110 + * $ATH_LICENSE_HOSTSDK0_C$
64111 + *
64112 + */
64113 +
64114 +#ifndef __DSET_INTERNAL_H__
64115 +#define __DSET_INTERNAL_H__
64116 +
64117 +/*
64118 + * Internal dset definitions, common for DataSet layer.
64119 + */
64120 +
64121 +#define DSET_TYPE_STANDARD      0
64122 +#define DSET_TYPE_BPATCHED      1
64123 +#define DSET_TYPE_COMPRESSED    2
64124 +
64125 +/* Dataset descriptor */
64126 +
64127 +typedef struct dset_descriptor_s {
64128 +  struct dset_descriptor_s  *next;         /* List link. NULL only at the last
64129 +                                              descriptor */
64130 +  A_UINT16                   id;           /* Dset ID */
64131 +  A_UINT16                   size;         /* Dset size. */
64132 +  void                      *DataPtr;      /* Pointer to raw data for standard
64133 +                                              DataSet or pointer to original
64134 +                                              dset_descriptor for patched
64135 +                                              DataSet */
64136 +  A_UINT32                   data_type;    /* DSET_TYPE_*, above */
64137 +
64138 +  void                      *AuxPtr;       /* Additional data that might
64139 +                                              needed for data_type. For
64140 +                                              example, pointer to patch
64141 +                                              Dataset descriptor for BPatch. */
64142 +} dset_descriptor_t;
64143 +
64144 +#endif /* __DSET_INTERNAL_H__ */
64145 --- /dev/null
64146 +++ b/drivers/ar6000/include/gpio_api.h
64147 @@ -0,0 +1,57 @@
64148 +#ifndef _GPIO_API_H_
64149 +#define _GPIO_API_H_
64150 +/*
64151 + * Copyright 2005 Atheros Communications, Inc.,  All Rights Reserved.
64152 + *
64153 + *
64154 + *  This program is free software; you can redistribute it and/or modify
64155 + *  it under the terms of the GNU General Public License version 2 as
64156 + *  published by the Free Software Foundation;
64157 + *
64158 + *  Software distributed under the License is distributed on an "AS
64159 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
64160 + *  implied. See the License for the specific language governing
64161 + *  rights and limitations under the License.
64162 + *
64163 + *
64164 + *
64165 + */
64166 +
64167 +/*
64168 + * Host-side General Purpose I/O API.
64169 + *
64170 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/gpio_api.h#1 $
64171 + */
64172 +
64173 +/*
64174 + * Send a command to the Target in order to change output on GPIO pins.
64175 + */
64176 +A_STATUS wmi_gpio_output_set(struct wmi_t *wmip,
64177 +                             A_UINT32 set_mask,
64178 +                             A_UINT32 clear_mask,
64179 +                             A_UINT32 enable_mask,
64180 +                             A_UINT32 disable_mask);
64181 +
64182 +/*
64183 + * Send a command to the Target requesting input state of GPIO pins.
64184 + */
64185 +A_STATUS wmi_gpio_input_get(struct wmi_t *wmip);
64186 +
64187 +/*
64188 + * Send a command to the Target to change the value of a GPIO register.
64189 + */
64190 +A_STATUS wmi_gpio_register_set(struct wmi_t *wmip,
64191 +                               A_UINT32 gpioreg_id,
64192 +                               A_UINT32 value);
64193 +
64194 +/*
64195 + * Send a command to the Target to fetch the value of a GPIO register.
64196 + */
64197 +A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id);
64198 +
64199 +/*
64200 + * Send a command to the Target, acknowledging some GPIO interrupts.
64201 + */
64202 +A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask);
64203 +
64204 +#endif /* _GPIO_API_H_ */
64205 --- /dev/null
64206 +++ b/drivers/ar6000/include/gpio.h
64207 @@ -0,0 +1,34 @@
64208 +/*
64209 + * Copyright (c) 2005 Atheros Communications Inc.
64210 + * All rights reserved.
64211 + *
64212 + * $ATH_LICENSE_HOSTSDK0_C$
64213 + *
64214 + */
64215 +
64216 +#if defined(AR6001)
64217 +#define GPIO_PIN_COUNT 18
64218 +#else
64219 +#define GPIO_PIN_COUNT 18
64220 +#endif
64221 +
64222 +/*
64223 + * Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
64224 + * NB: These match hardware order, so that addresses can
64225 + * easily be computed.
64226 + */
64227 +#define GPIO_ID_OUT             0x00000000
64228 +#define GPIO_ID_OUT_W1TS        0x00000001
64229 +#define GPIO_ID_OUT_W1TC        0x00000002
64230 +#define GPIO_ID_ENABLE          0x00000003
64231 +#define GPIO_ID_ENABLE_W1TS     0x00000004
64232 +#define GPIO_ID_ENABLE_W1TC     0x00000005
64233 +#define GPIO_ID_IN              0x00000006
64234 +#define GPIO_ID_STATUS          0x00000007
64235 +#define GPIO_ID_STATUS_W1TS     0x00000008
64236 +#define GPIO_ID_STATUS_W1TC     0x00000009
64237 +#define GPIO_ID_PIN0            0x0000000a
64238 +#define GPIO_ID_PIN(n)          (GPIO_ID_PIN0+(n))
64239 +
64240 +#define GPIO_LAST_REGISTER_ID   GPIO_ID_PIN(17)
64241 +#define GPIO_ID_NONE            0xffffffff
64242 --- /dev/null
64243 +++ b/drivers/ar6000/include/hif.h
64244 @@ -0,0 +1,296 @@
64245 +/*
64246 + * Copyright (c) 2004-2007 Atheros Communications Inc.
64247 + * All rights reserved.
64248 + *
64249 + *
64250 + *  This program is free software; you can redistribute it and/or modify
64251 + *  it under the terms of the GNU General Public License version 2 as
64252 + *  published by the Free Software Foundation;
64253 + *
64254 + *  Software distributed under the License is distributed on an "AS
64255 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
64256 + *  implied. See the License for the specific language governing
64257 + *  rights and limitations under the License.
64258 + *
64259 + *
64260 + *
64261 + * HIF specific declarations and prototypes
64262 + */
64263 +
64264 +#ifndef _HIF_H_
64265 +#define _HIF_H_
64266 +
64267 +#ifdef __cplusplus
64268 +extern "C" {
64269 +#endif /* __cplusplus */
64270 +
64271 +/* Header files */
64272 +#include "a_config.h"
64273 +#include "athdefs.h"
64274 +#include "a_types.h"
64275 +#include "a_osapi.h"
64276 +
64277 +typedef struct htc_callbacks HTC_CALLBACKS;
64278 +typedef struct hif_device HIF_DEVICE;
64279 +
64280 +/*
64281 + * direction - Direction of transfer (HIF_READ/HIF_WRITE).
64282 + */
64283 +#define HIF_READ                    0x00000001
64284 +#define HIF_WRITE                   0x00000002
64285 +#define HIF_DIR_MASK                (HIF_READ | HIF_WRITE)
64286 +
64287 +/*
64288 + *     type - An interface may support different kind of read/write commands.
64289 + *            The command type is divided into a basic and an extended command
64290 + *            and can be specified using HIF_BASIC_IO/HIF_EXTENDED_IO.
64291 + */
64292 +#define HIF_BASIC_IO                0x00000004
64293 +#define HIF_EXTENDED_IO             0x00000008
64294 +#define HIF_TYPE_MASK               (HIF_BASIC_IO | HIF_EXTENDED_IO)
64295 +
64296 +/*
64297 + *     emode - This indicates the whether the command is to be executed in a
64298 + *             blocking or non-blocking fashion (HIF_SYNCHRONOUS/
64299 + *             HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
64300 + *             implemented using the asynchronous mode allowing the the bus
64301 + *             driver to indicate the completion of operation through the
64302 + *             registered callback routine. The requirement primarily comes
64303 + *             from the contexts these operations get called from (a driver's
64304 + *             transmit context or the ISR context in case of receive).
64305 + *             Support for both of these modes is essential.
64306 + */
64307 +#define HIF_SYNCHRONOUS             0x00000010
64308 +#define HIF_ASYNCHRONOUS            0x00000020
64309 +#define HIF_EMODE_MASK              (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
64310 +
64311 +/*
64312 + *     dmode - An interface may support different kinds of commands based on
64313 + *             the tradeoff between the amount of data it can carry and the
64314 + *             setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
64315 + *             HIF_BLOCK_BASIS). In case of latter, the data is rounded off
64316 + *             to the nearest block size by padding. The size of the block is
64317 + *             configurable at compile time using the HIF_BLOCK_SIZE and is
64318 + *             negotiated with the target during initialization after the
64319 + *             dragon interrupts are enabled.
64320 + */
64321 +#define HIF_BYTE_BASIS              0x00000040
64322 +#define HIF_BLOCK_BASIS             0x00000080
64323 +#define HIF_DMODE_MASK              (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
64324 +
64325 +/*
64326 + *     amode - This indicates if the address has to be incremented on dragon
64327 + *             after every read/write operation (HIF?FIXED_ADDRESS/
64328 + *             HIF_INCREMENTAL_ADDRESS).
64329 + */
64330 +#define HIF_FIXED_ADDRESS           0x00000100
64331 +#define HIF_INCREMENTAL_ADDRESS     0x00000200
64332 +#define HIF_AMODE_MASK              (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
64333 +
64334 +#define HIF_WR_ASYNC_BYTE_FIX   \
64335 +    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
64336 +#define HIF_WR_ASYNC_BYTE_INC   \
64337 +    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
64338 +#define HIF_WR_ASYNC_BLOCK_INC  \
64339 +    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
64340 +#define HIF_WR_SYNC_BYTE_FIX    \
64341 +    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
64342 +#define HIF_WR_SYNC_BYTE_INC    \
64343 +    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
64344 +#define HIF_WR_SYNC_BLOCK_INC  \
64345 +    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
64346 +#define HIF_RD_SYNC_BYTE_INC    \
64347 +    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
64348 +#define HIF_RD_SYNC_BYTE_FIX    \
64349 +    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
64350 +#define HIF_RD_ASYNC_BYTE_FIX   \
64351 +    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
64352 +#define HIF_RD_ASYNC_BLOCK_FIX  \
64353 +    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
64354 +#define HIF_RD_ASYNC_BYTE_INC   \
64355 +    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
64356 +#define HIF_RD_ASYNC_BLOCK_INC  \
64357 +    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
64358 +#define HIF_RD_SYNC_BLOCK_INC  \
64359 +    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
64360 +
64361 +
64362 +typedef enum {
64363 +    HIF_DEVICE_POWER_STATE = 0,
64364 +    HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
64365 +    HIF_DEVICE_GET_MBOX_ADDR,
64366 +    HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
64367 +    HIF_DEVICE_GET_IRQ_PROC_MODE,
64368 +    HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
64369 +} HIF_DEVICE_CONFIG_OPCODE;
64370 +
64371 +/*
64372 + * HIF CONFIGURE definitions:
64373 + *
64374 + *   HIF_DEVICE_GET_MBOX_BLOCK_SIZE
64375 + *   input : none
64376 + *   output : array of 4 A_UINT32s
64377 + *   notes: block size is returned for each mailbox (4)
64378 + *
64379 + *   HIF_DEVICE_GET_MBOX_ADDR
64380 + *   input : none
64381 + *   output : array of 4 A_UINT32
64382 + *   notes: address is returned for each mailbox (4) in the array
64383 + *
64384 + *   HIF_DEVICE_GET_PENDING_EVENTS_FUNC
64385 + *   input : none
64386 + *   output: HIF_PENDING_EVENTS_FUNC function pointer
64387 + *   notes: this is optional for the HIF layer, if the request is
64388 + *          not handled then it indicates that the upper layer can use
64389 + *          the standard device methods to get pending events (IRQs, mailbox messages etc..)
64390 + *          otherwise it can call the function pointer to check pending events.
64391 + *
64392 + *   HIF_DEVICE_GET_IRQ_PROC_MODE
64393 + *   input : none
64394 + *   output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode)
64395 + *   note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF
64396 + *         layer can report whether IRQ processing is requires synchronous behavior or
64397 + *         can be processed using asynchronous bus requests (typically faster).
64398 + *
64399 + *   HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC
64400 + *   input :
64401 + *   output : HIF_MASK_UNMASK_RECV_EVENT function pointer
64402 + *   notes: this is optional for the HIF layer.  The HIF layer may require a special mechanism
64403 + *          to mask receive message events.  The upper layer can call this pointer when it needs
64404 + *          to mask/unmask receive events (in case it runs out of buffers).
64405 + *
64406 + *
64407 + */
64408 +
64409 +typedef enum {
64410 +    HIF_DEVICE_IRQ_SYNC_ONLY,   /* for HIF implementations that require the DSR to process all
64411 +                                   interrupts before returning */
64412 +    HIF_DEVICE_IRQ_ASYNC_SYNC,  /* for HIF implementations that allow DSR to process interrupts
64413 +                                   using ASYNC I/O (that is HIFAckInterrupt can be called at a
64414 +                                   later time */
64415 +} HIF_DEVICE_IRQ_PROCESSING_MODE;
64416 +
64417 +#define HIF_MAX_DEVICES                 1
64418 +
64419 +struct htc_callbacks {
64420 +    A_UCHAR *name;
64421 +    A_UINT32 id;
64422 +    A_STATUS (* deviceInsertedHandler)(void *hif_handle);
64423 +    A_STATUS (* deviceRemovedHandler)(void *htc_handle, A_STATUS status);
64424 +    A_STATUS (* deviceSuspendHandler)(void *htc_handle);
64425 +    A_STATUS (* deviceResumeHandler)(void *htc_handle);
64426 +    A_STATUS (* deviceWakeupHandler)(void *htc_handle);
64427 +    A_STATUS (* rwCompletionHandler)(void *context, A_STATUS status);
64428 +    A_STATUS (* dsrHandler)(void *htc_handle);
64429 +};
64430 +
64431 +
64432 +#define HIF_OTHER_EVENTS     (1 << 0)   /* other interrupts (non-Recv) are pending, host
64433 +                                           needs to read the register table to figure out what */
64434 +#define HIF_RECV_MSG_AVAIL   (1 << 1)   /* pending recv packet */
64435 +
64436 +typedef struct _HIF_PENDING_EVENTS_INFO {
64437 +    A_UINT32 Events;
64438 +    A_UINT32 LookAhead;
64439 +} HIF_PENDING_EVENTS_INFO;
64440 +
64441 +    /* function to get pending events , some HIF modules use special mechanisms
64442 +     * to detect packet available and other interrupts */
64443 +typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE              *device,
64444 +                                             HIF_PENDING_EVENTS_INFO *pEvents,
64445 +                                             void                    *AsyncContext);
64446 +
64447 +#define HIF_MASK_RECV    TRUE
64448 +#define HIF_UNMASK_RECV  FALSE
64449 +    /* function to mask recv events */
64450 +typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE  *device,
64451 +                                                A_BOOL      Mask,
64452 +                                                void        *AsyncContext);
64453 +
64454 +
64455 +/*
64456 + * This API is used by the HTC layer to initialize the HIF layer and to
64457 + * register different callback routines. Support for following events has
64458 + * been captured - DSR, Read/Write completion, Device insertion/removal,
64459 + * Device suspension/resumption/wakeup. In addition to this, the API is
64460 + * also used to register the name and the revision of the chip. The latter
64461 + * can be used to verify the revision of the chip read from the device
64462 + * before reporting it to HTC.
64463 + */
64464 +int HIFInit(HTC_CALLBACKS *callbacks);
64465 +
64466 +/*
64467 + * This API is used to provide the read/write interface over the specific bus
64468 + * interface.
64469 + * address - Starting address in the dragon's address space. For mailbox
64470 + *           writes, it refers to the start of the mbox boundary. It should
64471 + *           be ensured that the last byte falls on the mailbox's EOM. For
64472 + *           mailbox reads, it refers to the end of the mbox boundary.
64473 + * buffer - Pointer to the buffer containg the data to be transmitted or
64474 + *          received.
64475 + * length - Amount of data to be transmitted or received.
64476 + * request - Characterizes the attributes of the command.
64477 + */
64478 +A_STATUS
64479 +HIFReadWrite(HIF_DEVICE    *device,
64480 +             A_UINT32       address,
64481 +             A_UCHAR       *buffer,
64482 +             A_UINT32       length,
64483 +             A_UINT32       request,
64484 +             void          *context);
64485 +
64486 +/*
64487 + * This can be initiated from the unload driver context ie when the HTCShutdown
64488 + * routine is called.
64489 + */
64490 +void HIFShutDownDevice(HIF_DEVICE *device);
64491 +
64492 +/*
64493 + * This should translate to an acknowledgment to the bus driver indicating that
64494 + * the previous interrupt request has been serviced and the all the relevant
64495 + * sources have been cleared. HTC is ready to process more interrupts.
64496 + * This should prevent the bus driver from raising an interrupt unless the
64497 + * previous one has been serviced and acknowledged using the previous API.
64498 + */
64499 +void HIFAckInterrupt(HIF_DEVICE *device);
64500 +
64501 +void HIFMaskInterrupt(HIF_DEVICE *device);
64502 +
64503 +void HIFUnMaskInterrupt(HIF_DEVICE *device);
64504 +
64505 +/*
64506 + * This set of functions are to be used by the bus driver to notify
64507 + * the HIF module about various events.
64508 + * These are not implemented if the bus driver provides an alternative
64509 + * way for this notification though callbacks for instance.
64510 + */
64511 +int HIFInsertEventNotify(void);
64512 +
64513 +int HIFRemoveEventNotify(void);
64514 +
64515 +int HIFIRQEventNotify(void);
64516 +
64517 +int HIFRWCompleteEventNotify(void);
64518 +
64519 +/*
64520 + * This function associates a opaque handle with the HIF layer
64521 + * to be used in communication with upper layer i.e. HTC.
64522 + * This would normaly be a pointer to htc_target data structure.
64523 + */
64524 +void HIFSetHandle(void *hif_handle, void *handle);
64525 +
64526 +A_STATUS
64527 +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
64528 +                   void *config, A_UINT32 configLen);
64529 +
64530 +
64531 +struct device;
64532 +struct device*
64533 +HIFGetOSDevice(HIF_DEVICE *device);
64534 +
64535 +
64536 +#ifdef __cplusplus
64537 +}
64538 +#endif
64539 +
64540 +#endif /* _HIF_H_ */
64541 --- /dev/null
64542 +++ b/drivers/ar6000/include/host_version.h
64543 @@ -0,0 +1,49 @@
64544 +#ifndef _HOST_VERSION_H_
64545 +#define _HOST_VERSION_H_
64546 +/*
64547 + * Copyright (c) 2004-2005 Atheros Communications Inc.
64548 + * All rights reserved.
64549 + *
64550 + * This file contains version information for the sample host driver for the
64551 + * AR6000 chip
64552 + *
64553 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/host_version.h#2 $
64554 + *
64555 + *
64556 + *  This program is free software; you can redistribute it and/or modify
64557 + *  it under the terms of the GNU General Public License version 2 as
64558 + *  published by the Free Software Foundation;
64559 + *
64560 + *  Software distributed under the License is distributed on an "AS
64561 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
64562 + *  implied. See the License for the specific language governing
64563 + *  rights and limitations under the License.
64564 + *
64565 + *
64566 + *
64567 + */
64568 +
64569 +#ifdef __cplusplus
64570 +extern "C" {
64571 +#endif
64572 +
64573 +#include <AR6K_version.h>
64574 +
64575 +/*
64576 + * The version number is made up of major, minor, patch and build
64577 + * numbers. These are 16 bit numbers.  The build and release script will
64578 + * set the build number using a Perforce counter.  Here the build number is
64579 + * set to 9999 so that builds done without the build-release script are easily
64580 + * identifiable.
64581 + */
64582 +
64583 +#define ATH_SW_VER_MAJOR      __VER_MAJOR_
64584 +#define ATH_SW_VER_MINOR      __VER_MINOR_
64585 +#define ATH_SW_VER_PATCH      __VER_PATCH_
64586 +#define ATH_SW_VER_BUILD 9999
64587 +
64588 +#ifdef __cplusplus
64589 +}
64590 +#endif
64591 +
64592 +#endif /* _HOST_VERSION_H_ */
64593 --- /dev/null
64594 +++ b/drivers/ar6000/include/htc_api.h
64595 @@ -0,0 +1,436 @@
64596 +/*
64597 + *
64598 + * Copyright (c) 2007 Atheros Communications Inc.
64599 + * All rights reserved.
64600 + *
64601 + *
64602 + *  This program is free software; you can redistribute it and/or modify
64603 + *  it under the terms of the GNU General Public License version 2 as
64604 + *  published by the Free Software Foundation;
64605 + *
64606 + *  Software distributed under the License is distributed on an "AS
64607 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
64608 + *  implied. See the License for the specific language governing
64609 + *  rights and limitations under the License.
64610 + *
64611 + *
64612 + *
64613 + */
64614 +
64615 +#ifndef _HTC_API_H_
64616 +#define _HTC_API_H_
64617 +
64618 +#include <htc.h>
64619 +#include <htc_services.h>
64620 +#include "htc_packet.h"
64621 +
64622 +#ifdef __cplusplus
64623 +extern "C" {
64624 +#endif /* __cplusplus */
64625 +
64626 +/* TODO.. for BMI */
64627 +#define ENDPOINT1 0
64628 +// TODO -remove me, but we have to fix BMI first
64629 +#define HTC_MAILBOX_NUM_MAX    4
64630 +
64631 +
64632 +/* ------ Endpoint IDS ------ */
64633 +typedef enum
64634 +{
64635 +    ENDPOINT_UNUSED = -1,
64636 +    ENDPOINT_0 = 0,
64637 +    ENDPOINT_1 = 1,
64638 +    ENDPOINT_2 = 2,
64639 +    ENDPOINT_3,
64640 +    ENDPOINT_4,
64641 +    ENDPOINT_5,
64642 +    ENDPOINT_6,
64643 +    ENDPOINT_7,
64644 +    ENDPOINT_8,
64645 +    ENDPOINT_MAX,
64646 +} HTC_ENDPOINT_ID;
64647 +
64648 +/* this is the amount of header room required by users of HTC */
64649 +#define HTC_HEADER_LEN         HTC_HDR_LENGTH
64650 +
64651 +typedef void *HTC_HANDLE;
64652 +
64653 +typedef A_UINT16 HTC_SERVICE_ID;
64654 +
64655 +typedef struct _HTC_INIT_INFO {
64656 +    void   (*AddInstance)(HTC_HANDLE);
64657 +    void   (*DeleteInstance)(void *Instance);
64658 +    void   (*TargetFailure)(void *Instance, A_STATUS Status);
64659 +} HTC_INIT_INFO;
64660 +
64661 +/* per service connection send completion */
64662 +typedef void   (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *);
64663 +/* per service connection pkt received */
64664 +typedef void   (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *);
64665 +
64666 +/* Optional per service connection receive buffer re-fill callback,
64667 + * On some OSes (like Linux) packets are allocated from a global pool and indicated up
64668 + * to the network stack.  The driver never gets the packets back from the OS.  For these OSes
64669 + * a refill callback can be used to allocate and re-queue buffers into HTC.
64670 + *
64671 + * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and
64672 + * the driver can re-queue these buffers into HTC. In this regard a refill callback is
64673 + * unnecessary */
64674 +typedef void   (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint);
64675 +
64676 +/* Optional per service connection callback when a send queue is full. This can occur if the
64677 + * host continues queueing up TX packets faster than credits can arrive
64678 + * To prevent the host (on some Oses like Linux) from continuously queueing packets
64679 + * and consuming resources, this callback is provided so that that the host
64680 + * can disable TX in the subsystem (i.e. network stack)
64681 + * Other OSes require a "per-packet" indication_RAW_STREAM_NUM_MAX for each completed TX packet, this
64682 + * closed loop mechanism will prevent the network stack from overunning the NIC */
64683 +typedef void (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_ENDPOINT_ID Endpoint);
64684 +
64685 +typedef struct _HTC_EP_CALLBACKS {
64686 +    void                     *pContext;     /* context for each callback */
64687 +    HTC_EP_SEND_PKT_COMPLETE EpTxComplete;  /* tx completion callback for connected endpoint */
64688 +    HTC_EP_RECV_PKT          EpRecv;        /* receive callback for connected endpoint */
64689 +    HTC_EP_RECV_REFILL       EpRecvRefill;  /* OPTIONAL receive re-fill callback for connected endpoint */
64690 +    HTC_EP_SEND_QUEUE_FULL   EpSendFull;    /* OPTIONAL send full callback */
64691 +} HTC_EP_CALLBACKS;
64692 +
64693 +/* service connection information */
64694 +typedef struct _HTC_SERVICE_CONNECT_REQ {
64695 +    HTC_SERVICE_ID   ServiceID;                 /* service ID to connect to */
64696 +    A_UINT16         ConnectionFlags;           /* connection flags, see htc protocol definition */
64697 +    A_UINT8         *pMetaData;                 /* ptr to optional service-specific meta-data */
64698 +    A_UINT8          MetaDataLength;            /* optional meta data length */
64699 +    HTC_EP_CALLBACKS EpCallbacks;               /* endpoint callbacks */
64700 +    int              MaxSendQueueDepth;         /* maximum depth of any send queue */
64701 +} HTC_SERVICE_CONNECT_REQ;
64702 +
64703 +/* service connection response information */
64704 +typedef struct _HTC_SERVICE_CONNECT_RESP {
64705 +    A_UINT8     *pMetaData;             /* caller supplied buffer to optional meta-data */
64706 +    A_UINT8     BufferLength;           /* length of caller supplied buffer */
64707 +    A_UINT8     ActualLength;           /* actual length of meta data */
64708 +    HTC_ENDPOINT_ID Endpoint;           /* endpoint to communicate over */
64709 +    int         MaxMsgLength;           /* max length of all messages over this endpoint */
64710 +    A_UINT8     ConnectRespCode;        /* connect response code from target */
64711 +} HTC_SERVICE_CONNECT_RESP;
64712 +
64713 +/* endpoint distribution structure */
64714 +typedef struct _HTC_ENDPOINT_CREDIT_DIST {
64715 +    struct _HTC_ENDPOINT_CREDIT_DIST *pNext;
64716 +    struct _HTC_ENDPOINT_CREDIT_DIST *pPrev;
64717 +    HTC_SERVICE_ID      ServiceID;          /* Service ID (set by HTC) */
64718 +    HTC_ENDPOINT_ID     Endpoint;           /* endpoint for this distribution struct (set by HTC) */
64719 +    A_UINT32            DistFlags;          /* distribution flags, distribution function can
64720 +                                               set default activity using SET_EP_ACTIVE() macro */
64721 +    int                 TxCreditsNorm;      /* credits for normal operation, anything above this
64722 +                                               indicates the endpoint is over-subscribed, this field
64723 +                                               is only relevant to the credit distribution function */
64724 +    int                 TxCreditsMin;       /* floor for credit distribution, this field is
64725 +                                               only relevant to the credit distribution function */
64726 +    int                 TxCreditsAssigned;  /* number of credits assigned to this EP, this field
64727 +                                               is only relevant to the credit dist function */
64728 +    int                 TxCredits;          /* current credits available, this field is used by
64729 +                                               HTC to determine whether a message can be sent or
64730 +                                               must be queued */
64731 +    int                 TxCreditsToDist;    /* pending credits to distribute on this endpoint, this
64732 +                                               is set by HTC when credit reports arrive.
64733 +                                               The credit distribution functions sets this to zero
64734 +                                               when it distributes the credits */
64735 +    int                 TxCreditsSeek;      /* this is the number of credits that the current pending TX
64736 +                                               packet needs to transmit.  This is set by HTC when
64737 +                                               and endpoint needs credits in order to transmit */
64738 +    int                 TxCreditSize;       /* size in bytes of each credit (set by HTC) */
64739 +    int                 TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */
64740 +    void                *pHTCReserved;      /* reserved for HTC use */
64741 +} HTC_ENDPOINT_CREDIT_DIST;
64742 +
64743 +#define HTC_EP_ACTIVE                            (1 << 31)
64744 +
64745 +/* macro to check if an endpoint has gone active, useful for credit
64746 + * distributions */
64747 +#define IS_EP_ACTIVE(epDist)  ((epDist)->DistFlags & HTC_EP_ACTIVE)
64748 +#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE
64749 +
64750 +    /* credit distibution code that is passed into the distrbution function,
64751 +     * there are mandatory and optional codes that must be handled */
64752 +typedef enum _HTC_CREDIT_DIST_REASON {
64753 +    HTC_CREDIT_DIST_SEND_COMPLETE = 0,     /* credits available as a result of completed
64754 +                                              send operations (MANDATORY) resulting in credit reports */
64755 +    HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1,   /* a change in endpoint activity occured (OPTIONAL) */
64756 +    HTC_CREDIT_DIST_SEEK_CREDITS,          /* an endpoint needs to "seek" credits (OPTIONAL) */
64757 +    HTC_DUMP_CREDIT_STATE                  /* for debugging, dump any state information that is kept by
64758 +                                              the distribution function */
64759 +} HTC_CREDIT_DIST_REASON;
64760 +
64761 +typedef void (*HTC_CREDIT_DIST_CALLBACK)(void                     *Context,
64762 +                                         HTC_ENDPOINT_CREDIT_DIST *pEPList,
64763 +                                         HTC_CREDIT_DIST_REASON   Reason);
64764 +
64765 +typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context,
64766 +                                         HTC_ENDPOINT_CREDIT_DIST *pEPList,
64767 +                                         int                      TotalCredits);
64768 +
64769 +    /* endpoint statistics action */
64770 +typedef enum _HTC_ENDPOINT_STAT_ACTION {
64771 +    HTC_EP_STAT_SAMPLE = 0,                /* only read statistics */
64772 +    HTC_EP_STAT_SAMPLE_AND_CLEAR = 1,      /* sample and immediately clear statistics */
64773 +    HTC_EP_STAT_CLEAR                      /* clear only */
64774 +} HTC_ENDPOINT_STAT_ACTION;
64775 +
64776 +    /* endpoint statistics */
64777 +typedef struct _HTC_ENDPOINT_STATS {
64778 +    A_UINT32  TxCreditLowIndications;  /* number of times the host set the credit-low flag in a send message on
64779 +                                        this endpoint */
64780 +    A_UINT32  TxIssued;               /* running count of TX packets issued */
64781 +    A_UINT32  TxCreditRpts;           /* running count of total credit reports received for this endpoint */
64782 +    A_UINT32  TxCreditRptsFromRx;
64783 +    A_UINT32  TxCreditRptsFromOther;
64784 +    A_UINT32  TxCreditRptsFromEp0;
64785 +    A_UINT32  TxCreditsFromRx;        /* count of credits received via Rx packets on this endpoint */
64786 +    A_UINT32  TxCreditsFromOther;     /* count of credits received via another endpoint */
64787 +    A_UINT32  TxCreditsFromEp0;       /* count of credits received via another endpoint */
64788 +    A_UINT32  TxCreditsConsummed;     /* count of consummed credits */
64789 +    A_UINT32  TxCreditsReturned;      /* count of credits returned */
64790 +    A_UINT32  RxReceived;             /* count of RX packets received */
64791 +    A_UINT32  RxLookAheads;           /* count of lookahead records
64792 +                                         found in messages received on this endpoint */
64793 +} HTC_ENDPOINT_STATS;
64794 +
64795 +/* ------ Function Prototypes ------ */
64796 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64797 +  @desc: Initialize HTC
64798 +  @function name: HTCInit
64799 +  @input:  pInfo - initialization information
64800 +  @output:
64801 +  @return: A_OK on success
64802 +  @notes: The caller initializes global HTC state and registers various instance
64803 +          notification callbacks (see HTC_INIT_INFO).
64804 +
64805 +  @example:
64806 +  @see also: HTCShutdown
64807 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64808 +A_STATUS    HTCInit(HTC_INIT_INFO *pInfo);
64809 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64810 +  @desc: Get the underlying HIF device handle
64811 +  @function name: HTCGetHifDevice
64812 +  @input:  HTCHandle - handle passed into the AddInstance callback
64813 +  @output:
64814 +  @return: opaque HIF device handle usable in HIF API calls.
64815 +  @notes:
64816 +  @example:
64817 +  @see also:
64818 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64819 +void       *HTCGetHifDevice(HTC_HANDLE HTCHandle);
64820 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64821 +  @desc: Set the associated instance for the HTC handle
64822 +  @function name: HTCSetInstance
64823 +  @input:  HTCHandle - handle passed into the AddInstance callback
64824 +           Instance - caller supplied instance object
64825 +  @output:
64826 +  @return:
64827 +  @notes:  Caller must set the instance information for the HTC handle in order to receive
64828 +           notifications for instance deletion (DeleteInstance callback is called) and for target
64829 +           failure notification.
64830 +  @example:
64831 +  @see also:
64832 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64833 +void        HTCSetInstance(HTC_HANDLE HTCHandle, void *Instance);
64834 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64835 +  @desc: Set credit distribution parameters
64836 +  @function name: HTCSetCreditDistribution
64837 +  @input:  HTCHandle - HTC handle
64838 +           pCreditDistCont - caller supplied context to pass into distribution functions
64839 +           CreditDistFunc - Distribution function callback
64840 +           CreditDistInit - Credit Distribution initialization callback
64841 +           ServicePriorityOrder - Array containing list of service IDs, lowest index is highest
64842 +                                  priority
64843 +           ListLength - number of elements in ServicePriorityOrder
64844 +  @output:
64845 +  @return:
64846 +  @notes:  The user can set a custom credit distribution function to handle special requirements
64847 +           for each endpoint.  A default credit distribution routine can be used by setting
64848 +           CreditInitFunc to NULL.  The default credit distribution is only provided for simple
64849 +           "fair" credit distribution without regard to any prioritization.
64850 +
64851 +  @example:
64852 +  @see also:
64853 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64854 +void        HTCSetCreditDistribution(HTC_HANDLE               HTCHandle,
64855 +                                     void                     *pCreditDistContext,
64856 +                                     HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
64857 +                                     HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
64858 +                                     HTC_SERVICE_ID           ServicePriorityOrder[],
64859 +                                     int                      ListLength);
64860 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64861 +  @desc: Wait for the target to indicate the HTC layer is ready
64862 +  @function name: HTCWaitTarget
64863 +  @input:  HTCHandle - HTC handle
64864 +  @output:
64865 +  @return:
64866 +  @notes:  This API blocks until the target responds with an HTC ready message.
64867 +           The caller should not connect services until the target has indicated it is
64868 +           ready.
64869 +  @example:
64870 +  @see also: HTCConnectService
64871 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64872 +A_STATUS    HTCWaitTarget(HTC_HANDLE HTCHandle);
64873 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64874 +  @desc: Start target service communications
64875 +  @function name: HTCStart
64876 +  @input:  HTCHandle - HTC handle
64877 +  @output:
64878 +  @return:
64879 +  @notes: This API indicates to the target that the service connection phase is complete
64880 +          and the target can freely start all connected services.  This API should only be
64881 +          called AFTER all service connections have been made.  TCStart will issue a
64882 +          SETUP_COMPLETE message to the target to indicate that all service connections
64883 +          have been made and the target can start communicating over the endpoints.
64884 +  @example:
64885 +  @see also: HTCConnectService
64886 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64887 +A_STATUS    HTCStart(HTC_HANDLE HTCHandle);
64888 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64889 +  @desc: Add receive packet to HTC
64890 +  @function name: HTCAddReceivePkt
64891 +  @input:  HTCHandle - HTC handle
64892 +           pPacket - HTC receive packet to add
64893 +  @output:
64894 +  @return: A_OK on success
64895 +  @notes:  user must supply HTC packets for capturing incomming HTC frames.  The caller
64896 +           must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
64897 +           macro.
64898 +  @example:
64899 +  @see also:
64900 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64901 +A_STATUS    HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
64902 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64903 +  @desc: Connect to an HTC service
64904 +  @function name: HTCConnectService
64905 +  @input:  HTCHandle - HTC handle
64906 +           pReq - connection details
64907 +  @output: pResp - connection response
64908 +  @return:
64909 +  @notes:  Service connections must be performed before HTCStart.  User provides callback handlers
64910 +           for various endpoint events.
64911 +  @example:
64912 +  @see also: HTCStart
64913 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64914 +A_STATUS    HTCConnectService(HTC_HANDLE HTCHandle,
64915 +                              HTC_SERVICE_CONNECT_REQ  *pReq,
64916 +                              HTC_SERVICE_CONNECT_RESP *pResp);
64917 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64918 +  @desc: Send an HTC packet
64919 +  @function name: HTCSendPkt
64920 +  @input:  HTCHandle - HTC handle
64921 +           pPacket - packet to send
64922 +  @output:
64923 +  @return: A_OK
64924 +  @notes:  Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro.
64925 +           This interface is fully asynchronous.  On error, HTC SendPkt will
64926 +           call the registered Endpoint callback to cleanup the packet.
64927 +  @example:
64928 +  @see also: HTCFlushEndpoint
64929 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64930 +A_STATUS    HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
64931 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64932 +  @desc: Stop HTC service communications
64933 +  @function name: HTCStop
64934 +  @input:  HTCHandle - HTC handle
64935 +  @output:
64936 +  @return:
64937 +  @notes: HTC communications is halted.  All receive and pending TX packets will
64938 +          be flushed.
64939 +  @example:
64940 +  @see also:
64941 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64942 +void        HTCStop(HTC_HANDLE HTCHandle);
64943 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64944 +  @desc: Shutdown HTC
64945 +  @function name: HTCShutdown
64946 +  @input:
64947 +  @output:
64948 +  @return:
64949 +  @notes:  This cleans up all resources allocated by HTCInit().
64950 +  @example:
64951 +  @see also: HTCInit
64952 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64953 +void        HTCShutDown(void);
64954 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64955 +  @desc: Flush pending TX packets
64956 +  @function name: HTCFlushEndpoint
64957 +  @input:  HTCHandle - HTC handle
64958 +           Endpoint - Endpoint to flush
64959 +           Tag - flush tag
64960 +  @output:
64961 +  @return:
64962 +  @notes:  The Tag parameter is used to selectively flush packets with matching tags.
64963 +           The value of 0 forces all packets to be flush regardless of tag.
64964 +  @example:
64965 +  @see also: HTCSendPkt
64966 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64967 +void        HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag);
64968 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64969 +  @desc: Dump credit distribution state
64970 +  @function name: HTCDumpCreditStates
64971 +  @input:  HTCHandle - HTC handle
64972 +  @output:
64973 +  @return:
64974 +  @notes:  This dumps all credit distribution information to the debugger
64975 +  @example:
64976 +  @see also:
64977 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64978 +void        HTCDumpCreditStates(HTC_HANDLE HTCHandle);
64979 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64980 +  @desc: Indicate a traffic activity change on an endpoint
64981 +  @function name: HTCIndicateActivityChange
64982 +  @input:  HTCHandle - HTC handle
64983 +           Endpoint - endpoint in which activity has changed
64984 +           Active - TRUE if active, FALSE if it has become inactive
64985 +  @output:
64986 +  @return:
64987 +  @notes:  This triggers the registered credit distribution function to
64988 +           re-adjust credits for active/inactive endpoints.
64989 +  @example:
64990 +  @see also:
64991 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
64992 +void        HTCIndicateActivityChange(HTC_HANDLE      HTCHandle,
64993 +                                      HTC_ENDPOINT_ID Endpoint,
64994 +                                      A_BOOL          Active);
64995 +
64996 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
64997 +  @desc: Get endpoint statistics
64998 +  @function name: HTCGetEndpointStatistics
64999 +  @input:  HTCHandle - HTC handle
65000 +           Endpoint - Endpoint identifier
65001 +           Action - action to take with statistics
65002 +  @output:
65003 +           pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR)
65004 +
65005 +  @return: TRUE if statistics profiling is enabled, otherwise FALSE.
65006 +
65007 +  @notes:  Statistics is a compile-time option and this function may return FALSE
65008 +           if HTC is not compiled with profiling.
65009 +
65010 +           The caller can specify the statistic "action" to take when sampling
65011 +           the statistics.  This includes:
65012 +
65013 +           HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values.
65014 +           HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics
65015 +                             are cleared.
65016 +           HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for
65017 +                   pStats
65018 +
65019 +  @example:
65020 +  @see also:
65021 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65022 +A_BOOL       HTCGetEndpointStatistics(HTC_HANDLE               HTCHandle,
65023 +                                      HTC_ENDPOINT_ID          Endpoint,
65024 +                                      HTC_ENDPOINT_STAT_ACTION Action,
65025 +                                      HTC_ENDPOINT_STATS       *pStats);
65026 +
65027 +#ifdef __cplusplus
65028 +}
65029 +#endif
65030 +
65031 +#endif /* _HTC_API_H_ */
65032 --- /dev/null
65033 +++ b/drivers/ar6000/include/htc.h
65034 @@ -0,0 +1,190 @@
65035 +/*
65036 + * Copyright (c) 2007 Atheros Communications Inc.
65037 + * All rights reserved.
65038 + *
65039 + * $ATH_LICENSE_HOSTSDK0_C$
65040 + *
65041 + */
65042 +
65043 +
65044 +#ifndef __HTC_H__
65045 +#define __HTC_H__
65046 +
65047 +#ifndef ATH_TARGET
65048 +#include "athstartpack.h"
65049 +#endif
65050 +
65051 +#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
65052 +
65053 +#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
65054 +        (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
65055 +
65056 +/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a
65057 + * structure using only the type and field name.
65058 + * Use these macros if there is the potential for unaligned buffer accesses. */
65059 +#define A_GET_UINT16_FIELD(p,type,field) \
65060 +    ASSEMBLE_UNALIGNED_UINT16(p,\
65061 +                              A_OFFSETOF(type,field) + 1, \
65062 +                              A_OFFSETOF(type,field))
65063 +
65064 +#define A_SET_UINT16_FIELD(p,type,field,value) \
65065 +{                                              \
65066 +    ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value);        \
65067 +    ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \
65068 +}
65069 +
65070 +#define A_GET_UINT8_FIELD(p,type,field) \
65071 +            ((A_UINT8 *)(p))[A_OFFSETOF(type,field)]
65072 +
65073 +#define A_SET_UINT8_FIELD(p,type,field,value) \
65074 +    ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value)
65075 +
65076 +/****** DANGER DANGER ***************
65077 + *
65078 + *   The frame header length and message formats defined herein were
65079 + *   selected to accommodate optimal alignment for target processing.  This reduces code
65080 + *   size and improves performance.
65081 + *
65082 + *   Any changes to the header length may alter the alignment and cause exceptions
65083 + *   on the target. When adding to the message structures insure that fields are
65084 + *   properly aligned.
65085 + *
65086 + */
65087 +
65088 +/* HTC frame header */
65089 +typedef PREPACK struct _HTC_FRAME_HDR{
65090 +        /* do not remove or re-arrange these fields, these are minimally required
65091 +         * to take advantage of 4-byte lookaheads in some hardware implementations */
65092 +    A_UINT8   EndpointID;
65093 +    A_UINT8   Flags;
65094 +    A_UINT16  PayloadLen;       /* length of data (including trailer) that follows the header */
65095 +
65096 +    /***** end of 4-byte lookahead ****/
65097 +
65098 +    A_UINT8   ControlBytes[2];
65099 +
65100 +    /* message payload starts after the header */
65101 +
65102 +} POSTPACK HTC_FRAME_HDR;
65103 +
65104 +/* frame header flags */
65105 +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
65106 +#define HTC_FLAGS_RECV_TRAILER       (1 << 1)
65107 +
65108 +
65109 +#define HTC_HDR_LENGTH  (sizeof(HTC_FRAME_HDR))
65110 +#define HTC_MAX_TRAILER_LENGTH   255
65111 +#define HTC_MAX_PAYLOAD_LENGTH   (2048 - sizeof(HTC_FRAME_HDR))
65112 +
65113 +/* HTC control message IDs */
65114 +typedef enum {
65115 +    HTC_MSG_READY_ID = 1,
65116 +    HTC_MSG_CONNECT_SERVICE_ID = 2,
65117 +    HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3,
65118 +    HTC_MSG_SETUP_COMPLETE_ID = 4,
65119 +} HTC_MSG_IDS;
65120 +
65121 +#define HTC_MAX_CONTROL_MESSAGE_LENGTH  256
65122 +
65123 +/* base message ID header */
65124 +typedef PREPACK struct {
65125 +    A_UINT16 MessageID;
65126 +} POSTPACK HTC_UNKNOWN_MSG;
65127 +
65128 +/* HTC ready message
65129 + * direction : target-to-host  */
65130 +typedef PREPACK struct {
65131 +    A_UINT16  MessageID;    /* ID */
65132 +    A_UINT16  CreditCount;  /* number of credits the target can offer */
65133 +    A_UINT16  CreditSize;   /* size of each credit */
65134 +    A_UINT8   MaxEndpoints; /* maximum number of endpoints the target has resources for */
65135 +    A_UINT8   _Pad1;
65136 +} POSTPACK HTC_READY_MSG;
65137 +
65138 +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
65139 +
65140 +/* connect service
65141 + * direction : host-to-target */
65142 +typedef PREPACK struct {
65143 +    A_UINT16  MessageID;
65144 +    A_UINT16  ServiceID;           /* service ID of the service to connect to */
65145 +    A_UINT16  ConnectionFlags;     /* connection flags */
65146 +
65147 +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2)  /* reduce credit dribbling when
65148 +                                                             the host needs credits */
65149 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK             (0x3)
65150 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH        0x0
65151 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF          0x1
65152 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS     0x2
65153 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY             0x3
65154 +
65155 +    A_UINT8   ServiceMetaLength;   /* length of meta data that follows */
65156 +    A_UINT8   _Pad1;
65157 +
65158 +    /* service-specific meta data starts after the header */
65159 +
65160 +} POSTPACK HTC_CONNECT_SERVICE_MSG;
65161 +
65162 +/* connect response
65163 + * direction : target-to-host */
65164 +typedef PREPACK struct {
65165 +    A_UINT16  MessageID;
65166 +    A_UINT16  ServiceID;            /* service ID that the connection request was made */
65167 +    A_UINT8   Status;               /* service connection status */
65168 +    A_UINT8   EndpointID;           /* assigned endpoint ID */
65169 +    A_UINT16  MaxMsgSize;           /* maximum expected message size on this endpoint */
65170 +    A_UINT8   ServiceMetaLength;    /* length of meta data that follows */
65171 +    A_UINT8   _Pad1;
65172 +
65173 +    /* service-specific meta data starts after the header */
65174 +
65175 +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
65176 +
65177 +typedef PREPACK struct {
65178 +    A_UINT16  MessageID;
65179 +    /* currently, no other fields */
65180 +} POSTPACK HTC_SETUP_COMPLETE_MSG;
65181 +
65182 +
65183 +/* connect response status codes */
65184 +#define HTC_SERVICE_SUCCESS      0  /* success */
65185 +#define HTC_SERVICE_NOT_FOUND    1  /* service could not be found */
65186 +#define HTC_SERVICE_FAILED       2  /* specific service failed the connect */
65187 +#define HTC_SERVICE_NO_RESOURCES 3  /* no resources (i.e. no more endpoints) */
65188 +#define HTC_SERVICE_NO_MORE_EP   4  /* specific service is not allowing any more
65189 +                                       endpoints */
65190 +
65191 +/* report record IDs */
65192 +typedef enum {
65193 +    HTC_RECORD_NULL  = 0,
65194 +    HTC_RECORD_CREDITS   = 1,
65195 +    HTC_RECORD_LOOKAHEAD = 2,
65196 +} HTC_RPT_IDS;
65197 +
65198 +typedef PREPACK struct {
65199 +    A_UINT8 RecordID;     /* Record ID */
65200 +    A_UINT8 Length;       /* Length of record */
65201 +} POSTPACK HTC_RECORD_HDR;
65202 +
65203 +typedef PREPACK struct {
65204 +    A_UINT8 EndpointID;     /* Endpoint that owns these credits */
65205 +    A_UINT8 Credits;        /* credits to report since last report */
65206 +} POSTPACK HTC_CREDIT_REPORT;
65207 +
65208 +typedef PREPACK struct {
65209 +    A_UINT8 PreValid;         /* pre valid guard */
65210 +    A_UINT8 LookAhead[4];     /* 4 byte lookahead */
65211 +    A_UINT8 PostValid;        /* post valid guard */
65212 +
65213 +   /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
65214 +    * The PreValid bytes must equal the inverse of the PostValid byte */
65215 +
65216 +} POSTPACK HTC_LOOKAHEAD_REPORT;
65217 +
65218 +#ifndef ATH_TARGET
65219 +#include "athendpack.h"
65220 +#endif
65221 +
65222 +
65223 +#endif /* __HTC_H__ */
65224 +
65225 --- /dev/null
65226 +++ b/drivers/ar6000/include/htc_packet.h
65227 @@ -0,0 +1,138 @@
65228 +/*
65229 + *
65230 + * Copyright (c) 2007 Atheros Communications Inc.
65231 + * All rights reserved.
65232 + *
65233 + *
65234 + *  This program is free software; you can redistribute it and/or modify
65235 + *  it under the terms of the GNU General Public License version 2 as
65236 + *  published by the Free Software Foundation;
65237 + *
65238 + *  Software distributed under the License is distributed on an "AS
65239 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
65240 + *  implied. See the License for the specific language governing
65241 + *  rights and limitations under the License.
65242 + *
65243 + *
65244 + *
65245 + */
65246 +
65247 +#ifndef HTC_PACKET_H_
65248 +#define HTC_PACKET_H_
65249 +
65250 +
65251 +#include "dl_list.h"
65252 +
65253 +struct _HTC_PACKET;
65254 +
65255 +typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *);
65256 +
65257 +typedef A_UINT16 HTC_TX_TAG;
65258 +
65259 +typedef struct _HTC_TX_PACKET_INFO {
65260 +    HTC_TX_TAG    Tag;            /* tag used to selective flush packets */
65261 +} HTC_TX_PACKET_INFO;
65262 +
65263 +#define HTC_TX_PACKET_TAG_ALL          0    /* a tag of zero is reserved and used to flush ALL packets */
65264 +#define HTC_TX_PACKET_TAG_INTERNAL     1                                /* internal tags start here */
65265 +#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */
65266 +
65267 +typedef struct _HTC_RX_PACKET_INFO {
65268 +    A_UINT32    Unused;          /* for future use and to make compilers happy */
65269 +} HTC_RX_PACKET_INFO;
65270 +
65271 +/* wrapper around endpoint-specific packets */
65272 +typedef struct _HTC_PACKET {
65273 +    DL_LIST         ListLink;       /* double link */
65274 +    void            *pPktContext;   /* caller's per packet specific context */
65275 +
65276 +    A_UINT8         *pBufferStart;  /* the true buffer start , the caller can
65277 +                                       store the real buffer start here.  In
65278 +                                       receive callbacks, the HTC layer sets pBuffer
65279 +                                       to the start of the payload past the header. This
65280 +                                       field allows the caller to reset pBuffer when it
65281 +                                       recycles receive packets back to HTC */
65282 +    /*
65283 +     * Pointer to the start of the buffer. In the transmit
65284 +     * direction this points to the start of the payload. In the
65285 +     * receive direction, however, the buffer when queued up
65286 +     * points to the start of the HTC header but when returned
65287 +     * to the caller points to the start of the payload
65288 +     */
65289 +    A_UINT8         *pBuffer;       /* payload start (RX/TX) */
65290 +    A_UINT32        BufferLength;   /* length of buffer */
65291 +    A_UINT32        ActualLength;   /* actual length of payload */
65292 +    int             Endpoint;       /* endpoint that this packet was sent/recv'd from */
65293 +    A_STATUS        Status;         /* completion status */
65294 +    union {
65295 +        HTC_TX_PACKET_INFO  AsTx;   /* Tx Packet specific info */
65296 +        HTC_RX_PACKET_INFO  AsRx;   /* Rx Packet specific info */
65297 +    } PktInfo;
65298 +
65299 +    /* the following fields are for internal HTC use */
65300 +    HTC_PACKET_COMPLETION Completion;   /* completion */
65301 +    void                  *pContext;    /* HTC private completion context */
65302 +    A_UINT32              HTCReserved;  /* reserved */
65303 +} HTC_PACKET;
65304 +
65305 +
65306 +
65307 +#define COMPLETE_HTC_PACKET(p,status)        \
65308 +{                                            \
65309 +    (p)->Status = (status);                  \
65310 +    (p)->Completion((p)->pContext,(p));      \
65311 +}
65312 +
65313 +#define INIT_HTC_PACKET_INFO(p,b,len)             \
65314 +{                                                 \
65315 +    (p)->pBufferStart = (b);                      \
65316 +    (p)->BufferLength = (len);                    \
65317 +}
65318 +
65319 +/* macro to set an initial RX packet for refilling HTC */
65320 +#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \
65321 +{                                                 \
65322 +    (p)->pPktContext = (c);                       \
65323 +    (p)->pBuffer = (b);                           \
65324 +    (p)->pBufferStart = (b);                      \
65325 +    (p)->BufferLength = (len);                    \
65326 +    (p)->Endpoint = (ep);                         \
65327 +}
65328 +
65329 +/* fast macro to recycle an RX packet that will be re-queued to HTC */
65330 +#define HTC_PACKET_RESET_RX(p)              \
65331 +    (p)->pBuffer = (p)->pBufferStart
65332 +
65333 +/* macro to set packet parameters for TX */
65334 +#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag)  \
65335 +{                                                 \
65336 +    (p)->pPktContext = (c);                       \
65337 +    (p)->pBuffer = (b);                           \
65338 +    (p)->ActualLength = (len);                    \
65339 +    (p)->Endpoint = (ep);                         \
65340 +    (p)->PktInfo.AsTx.Tag = (tag);                \
65341 +}
65342 +
65343 +/* HTC Packet Queueing Macros */
65344 +typedef DL_LIST HTC_PACKET_QUEUE;
65345 +/* initialize queue */
65346 +#define INIT_HTC_PACKET_QUEUE(pQ) DL_LIST_INIT((pQ))
65347 +/* enqueue HTC packet to the tail of the queue */
65348 +#define HTC_PACKET_ENQUEUE(pQ,p)  DL_ListInsertTail((pQ),&(p)->ListLink)
65349 +/* test if a queue is empty */
65350 +#define HTC_QUEUE_EMPTY(pQ)       DL_LIST_IS_EMPTY((pQ))
65351 +/* get packet at head without removing it */
65352 +#define HTC_GET_PKT_AT_HEAD(pQ)   A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(pQ)),HTC_PACKET,ListLink);
65353 +/* remove a packet from the current list it is linked to */
65354 +#define HTC_PACKET_REMOVE(p)      DL_ListRemove(&(p)->ListLink)
65355 +
65356 +/* dequeue an HTC packet from the head of the queue */
65357 +static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) {
65358 +    DL_LIST    *pItem = DL_ListRemoveItemFromHead(queue);
65359 +    if (pItem != NULL) {
65360 +        return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
65361 +    }
65362 +    return NULL;
65363 +}
65364 +
65365 +#endif /*HTC_PACKET_H_*/
65366 --- /dev/null
65367 +++ b/drivers/ar6000/include/htc_services.h
65368 @@ -0,0 +1,37 @@
65369 +/*
65370 + * Copyright (c) 2007 Atheros Communications Inc.
65371 + * All rights reserved.
65372 + *
65373 + * $ATH_LICENSE_HOSTSDK0_C$
65374 + *
65375 + */
65376 +
65377 +#ifndef __HTC_SERVICES_H__
65378 +#define __HTC_SERVICES_H__
65379 +
65380 +/* Current service IDs */
65381 +
65382 +typedef enum {
65383 +    RSVD_SERVICE_GROUP  = 0,
65384 +    WMI_SERVICE_GROUP   = 1,
65385 +
65386 +    HTC_TEST_GROUP = 254,
65387 +    HTC_SERVICE_GROUP_LAST = 255
65388 +}HTC_SERVICE_GROUP_IDS;
65389 +
65390 +#define MAKE_SERVICE_ID(group,index) \
65391 +            (int)(((int)group << 8) | (int)(index))
65392 +
65393 +/* NOTE: service ID of 0x0000 is reserved and should never be used */
65394 +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
65395 +#define WMI_CONTROL_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
65396 +#define WMI_DATA_BE_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
65397 +#define WMI_DATA_BK_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
65398 +#define WMI_DATA_VI_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
65399 +#define WMI_DATA_VO_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
65400 +#define WMI_MAX_SERVICES  5
65401 +
65402 +/* raw stream service (i.e. flash, tcmd, calibration apps) */
65403 +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
65404 +
65405 +#endif /*HTC_SERVICES_H_*/
65406 --- /dev/null
65407 +++ b/drivers/ar6000/include/ieee80211.h
65408 @@ -0,0 +1,342 @@
65409 +/*-
65410 + * Copyright (c) 2001 Atsushi Onoe
65411 + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
65412 + * Copyright (c) 2006 Atheros Communications, Inc.
65413 + *
65414 + * Wireless Network driver for Atheros AR6001
65415 + * All rights reserved.
65416 + *
65417 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
65418 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
65419 + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
65420 + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
65421 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
65422 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
65423 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
65424 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65425 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
65426 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65427 + *
65428 + */
65429 +#ifndef _NET80211_IEEE80211_H_
65430 +#define _NET80211_IEEE80211_H_
65431 +
65432 +#include "athstartpack.h"
65433 +
65434 +/*
65435 + * 802.11 protocol definitions.
65436 + */
65437 +
65438 +#define IEEE80211_ADDR_LEN  6       /* size of 802.11 address */
65439 +/* is 802.11 address multicast/broadcast? */
65440 +#define IEEE80211_IS_MULTICAST(_a)  (*(_a) & 0x01)
65441 +#define IEEE80211_ADDR_EQ(addr1, addr2)     \
65442 +    (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0)
65443 +
65444 +#define IEEE80211_KEYBUF_SIZE 16
65445 +#define IEEE80211_MICBUF_SIZE (8+8)  /* space for both tx and rx */
65446 +
65447 +/*
65448 + * NB: these values are ordered carefully; there are lots of
65449 + * of implications in any reordering.  In particular beware
65450 + * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY.
65451 + */
65452 +#define IEEE80211_CIPHER_WEP            0
65453 +#define IEEE80211_CIPHER_TKIP           1
65454 +#define IEEE80211_CIPHER_AES_OCB        2
65455 +#define IEEE80211_CIPHER_AES_CCM        3
65456 +#define IEEE80211_CIPHER_CKIP           5
65457 +#define IEEE80211_CIPHER_CCKM_KRK       6
65458 +#define IEEE80211_CIPHER_NONE           7       /* pseudo value */
65459 +
65460 +#define IEEE80211_CIPHER_MAX            (IEEE80211_CIPHER_NONE+1)
65461 +
65462 +#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \
65463 +        (((len) == 5) || ((len) == 13) || ((len) == 16))
65464 +
65465 +
65466 +
65467 +/*
65468 + * generic definitions for IEEE 802.11 frames
65469 + */
65470 +PREPACK struct ieee80211_frame {
65471 +    A_UINT8    i_fc[2];
65472 +    A_UINT8    i_dur[2];
65473 +    A_UINT8    i_addr1[IEEE80211_ADDR_LEN];
65474 +    A_UINT8    i_addr2[IEEE80211_ADDR_LEN];
65475 +    A_UINT8    i_addr3[IEEE80211_ADDR_LEN];
65476 +    A_UINT8    i_seq[2];
65477 +    /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */
65478 +    /* see below */
65479 +} POSTPACK;
65480 +
65481 +#define IEEE80211_FC0_VERSION_MASK          0x03
65482 +#define IEEE80211_FC0_VERSION_SHIFT         0
65483 +#define IEEE80211_FC0_VERSION_0             0x00
65484 +#define IEEE80211_FC0_TYPE_MASK             0x0c
65485 +#define IEEE80211_FC0_TYPE_SHIFT            2
65486 +#define IEEE80211_FC0_TYPE_MGT              0x00
65487 +#define IEEE80211_FC0_TYPE_CTL              0x04
65488 +#define IEEE80211_FC0_TYPE_DATA             0x08
65489 +
65490 +#define IEEE80211_FC0_SUBTYPE_MASK          0xf0
65491 +#define IEEE80211_FC0_SUBTYPE_SHIFT         4
65492 +/* for TYPE_MGT */
65493 +#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ     0x00
65494 +#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP    0x10
65495 +#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ   0x20
65496 +#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP  0x30
65497 +#define IEEE80211_FC0_SUBTYPE_PROBE_REQ     0x40
65498 +#define IEEE80211_FC0_SUBTYPE_PROBE_RESP    0x50
65499 +#define IEEE80211_FC0_SUBTYPE_BEACON        0x80
65500 +#define IEEE80211_FC0_SUBTYPE_ATIM          0x90
65501 +#define IEEE80211_FC0_SUBTYPE_DISASSOC      0xa0
65502 +#define IEEE80211_FC0_SUBTYPE_AUTH          0xb0
65503 +#define IEEE80211_FC0_SUBTYPE_DEAUTH        0xc0
65504 +/* for TYPE_CTL */
65505 +#define IEEE80211_FC0_SUBTYPE_PS_POLL       0xa0
65506 +#define IEEE80211_FC0_SUBTYPE_RTS           0xb0
65507 +#define IEEE80211_FC0_SUBTYPE_CTS           0xc0
65508 +#define IEEE80211_FC0_SUBTYPE_ACK           0xd0
65509 +#define IEEE80211_FC0_SUBTYPE_CF_END        0xe0
65510 +#define IEEE80211_FC0_SUBTYPE_CF_END_ACK    0xf0
65511 +/* for TYPE_DATA (bit combination) */
65512 +#define IEEE80211_FC0_SUBTYPE_DATA          0x00
65513 +#define IEEE80211_FC0_SUBTYPE_CF_ACK        0x10
65514 +#define IEEE80211_FC0_SUBTYPE_CF_POLL       0x20
65515 +#define IEEE80211_FC0_SUBTYPE_CF_ACPL       0x30
65516 +#define IEEE80211_FC0_SUBTYPE_NODATA        0x40
65517 +#define IEEE80211_FC0_SUBTYPE_CFACK         0x50
65518 +#define IEEE80211_FC0_SUBTYPE_CFPOLL        0x60
65519 +#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70
65520 +#define IEEE80211_FC0_SUBTYPE_QOS           0x80
65521 +#define IEEE80211_FC0_SUBTYPE_QOS_NULL      0xc0
65522 +
65523 +#define IEEE80211_FC1_DIR_MASK              0x03
65524 +#define IEEE80211_FC1_DIR_NODS              0x00    /* STA->STA */
65525 +#define IEEE80211_FC1_DIR_TODS              0x01    /* STA->AP  */
65526 +#define IEEE80211_FC1_DIR_FROMDS            0x02    /* AP ->STA */
65527 +#define IEEE80211_FC1_DIR_DSTODS            0x03    /* AP ->AP  */
65528 +
65529 +#define IEEE80211_FC1_MORE_FRAG             0x04
65530 +#define IEEE80211_FC1_RETRY                 0x08
65531 +#define IEEE80211_FC1_PWR_MGT               0x10
65532 +#define IEEE80211_FC1_MORE_DATA             0x20
65533 +#define IEEE80211_FC1_WEP                   0x40
65534 +#define IEEE80211_FC1_ORDER                 0x80
65535 +
65536 +#define IEEE80211_SEQ_FRAG_MASK             0x000f
65537 +#define IEEE80211_SEQ_FRAG_SHIFT            0
65538 +#define IEEE80211_SEQ_SEQ_MASK              0xfff0
65539 +#define IEEE80211_SEQ_SEQ_SHIFT             4
65540 +
65541 +#define IEEE80211_NWID_LEN                  32
65542 +
65543 +/*
65544 + * 802.11 rate set.
65545 + */
65546 +#define IEEE80211_RATE_SIZE     8       /* 802.11 standard */
65547 +#define IEEE80211_RATE_MAXSIZE  15      /* max rates we'll handle */
65548 +
65549 +#define WMM_NUM_AC                  4   /* 4 AC categories */
65550 +
65551 +#define WMM_PARAM_ACI_M         0x60    /* Mask for ACI field */
65552 +#define WMM_PARAM_ACI_S         5   /* Shift for ACI field */
65553 +#define WMM_PARAM_ACM_M         0x10    /* Mask for ACM bit */
65554 +#define WMM_PARAM_ACM_S         4       /* Shift for ACM bit */
65555 +#define WMM_PARAM_AIFSN_M       0x0f    /* Mask for aifsn field */
65556 +#define WMM_PARAM_LOGCWMIN_M    0x0f    /* Mask for CwMin field (in log) */
65557 +#define WMM_PARAM_LOGCWMAX_M    0xf0    /* Mask for CwMax field (in log) */
65558 +#define WMM_PARAM_LOGCWMAX_S    4   /* Shift for CwMax field */
65559 +
65560 +#define WMM_AC_TO_TID(_ac) (       \
65561 +    ((_ac) == WMM_AC_VO) ? 6 : \
65562 +    ((_ac) == WMM_AC_VI) ? 5 : \
65563 +    ((_ac) == WMM_AC_BK) ? 1 : \
65564 +    0)
65565 +
65566 +#define TID_TO_WMM_AC(_tid) (      \
65567 +    ((_tid) < 1) ? WMM_AC_BE : \
65568 +    ((_tid) < 3) ? WMM_AC_BK : \
65569 +    ((_tid) < 6) ? WMM_AC_VI : \
65570 +    WMM_AC_VO)
65571 +/*
65572 + * Management information element payloads.
65573 + */
65574 +
65575 +enum {
65576 +    IEEE80211_ELEMID_SSID       = 0,
65577 +    IEEE80211_ELEMID_RATES      = 1,
65578 +    IEEE80211_ELEMID_FHPARMS    = 2,
65579 +    IEEE80211_ELEMID_DSPARMS    = 3,
65580 +    IEEE80211_ELEMID_CFPARMS    = 4,
65581 +    IEEE80211_ELEMID_TIM        = 5,
65582 +    IEEE80211_ELEMID_IBSSPARMS  = 6,
65583 +    IEEE80211_ELEMID_COUNTRY    = 7,
65584 +    IEEE80211_ELEMID_CHALLENGE  = 16,
65585 +    /* 17-31 reserved for challenge text extension */
65586 +    IEEE80211_ELEMID_PWRCNSTR   = 32,
65587 +    IEEE80211_ELEMID_PWRCAP     = 33,
65588 +    IEEE80211_ELEMID_TPCREQ     = 34,
65589 +    IEEE80211_ELEMID_TPCREP     = 35,
65590 +    IEEE80211_ELEMID_SUPPCHAN   = 36,
65591 +    IEEE80211_ELEMID_CHANSWITCH = 37,
65592 +    IEEE80211_ELEMID_MEASREQ    = 38,
65593 +    IEEE80211_ELEMID_MEASREP    = 39,
65594 +    IEEE80211_ELEMID_QUIET      = 40,
65595 +    IEEE80211_ELEMID_IBSSDFS    = 41,
65596 +    IEEE80211_ELEMID_ERP        = 42,
65597 +    IEEE80211_ELEMID_RSN        = 48,
65598 +    IEEE80211_ELEMID_XRATES     = 50,
65599 +    IEEE80211_ELEMID_TPC        = 150,
65600 +    IEEE80211_ELEMID_CCKM       = 156,
65601 +    IEEE80211_ELEMID_VENDOR     = 221,  /* vendor private */
65602 +};
65603 +
65604 +#define ATH_OUI             0x7f0300        /* Atheros OUI */
65605 +#define ATH_OUI_TYPE        0x01
65606 +#define ATH_OUI_SUBTYPE     0x01
65607 +#define ATH_OUI_VERSION     0x00
65608 +
65609 +#define WPA_OUI             0xf25000
65610 +#define WPA_OUI_TYPE        0x01
65611 +#define WPA_VERSION         1          /* current supported version */
65612 +
65613 +#define WPA_CSE_NULL        0x00
65614 +#define WPA_CSE_WEP40       0x01
65615 +#define WPA_CSE_TKIP        0x02
65616 +#define WPA_CSE_CCMP        0x04
65617 +#define WPA_CSE_WEP104      0x05
65618 +
65619 +#define WPA_ASE_NONE        0x00
65620 +#define WPA_ASE_8021X_UNSPEC    0x01
65621 +#define WPA_ASE_8021X_PSK   0x02
65622 +
65623 +#define RSN_OUI         0xac0f00
65624 +#define RSN_VERSION     1       /* current supported version */
65625 +
65626 +#define RSN_CSE_NULL        0x00
65627 +#define RSN_CSE_WEP40       0x01
65628 +#define RSN_CSE_TKIP        0x02
65629 +#define RSN_CSE_WRAP        0x03
65630 +#define RSN_CSE_CCMP        0x04
65631 +#define RSN_CSE_WEP104      0x05
65632 +
65633 +#define RSN_ASE_NONE        0x00
65634 +#define RSN_ASE_8021X_UNSPEC    0x01
65635 +#define RSN_ASE_8021X_PSK   0x02
65636 +
65637 +#define RSN_CAP_PREAUTH     0x01
65638 +
65639 +#define WMM_OUI         0xf25000
65640 +#define WMM_OUI_TYPE        0x02
65641 +#define WMM_INFO_OUI_SUBTYPE    0x00
65642 +#define WMM_PARAM_OUI_SUBTYPE   0x01
65643 +#define WMM_VERSION     1
65644 +
65645 +/* WMM stream classes */
65646 +#define WMM_NUM_AC  4
65647 +#define WMM_AC_BE   0       /* best effort */
65648 +#define WMM_AC_BK   1       /* background */
65649 +#define WMM_AC_VI   2       /* video */
65650 +#define WMM_AC_VO   3       /* voice */
65651 +
65652 +/* TSPEC related */
65653 +#define ACTION_CATEGORY_CODE_TSPEC                 17
65654 +#define ACTION_CODE_TSPEC_ADDTS                    0
65655 +#define ACTION_CODE_TSPEC_ADDTS_RESP               1
65656 +#define ACTION_CODE_TSPEC_DELTS                    2
65657 +
65658 +typedef enum {
65659 +    TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0,
65660 +    TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1,
65661 +    TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3,
65662 +    TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8,
65663 +    TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9,
65664 +    TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA,
65665 +    TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB,
65666 +    TSPEC_STATUS_CODE_DELTS_SENT    = 0x30,
65667 +    TSPEC_STATUS_CODE_DELTS_RECV    = 0x31,
65668 +} TSPEC_STATUS_CODE;
65669 +
65670 +/*
65671 + * WMM/802.11e Tspec Element
65672 + */
65673 +typedef PREPACK struct wmm_tspec_ie_t {
65674 +    A_UINT8     elementId;
65675 +    A_UINT8     len;
65676 +    A_UINT8     oui[3];
65677 +    A_UINT8     ouiType;
65678 +    A_UINT8     ouiSubType;
65679 +    A_UINT8     version;
65680 +    A_UINT16    tsInfo_info;
65681 +    A_UINT8     tsInfo_reserved;
65682 +    A_UINT16    nominalMSDU;
65683 +    A_UINT16    maxMSDU;
65684 +    A_UINT32    minServiceInt;
65685 +    A_UINT32    maxServiceInt;
65686 +    A_UINT32    inactivityInt;
65687 +    A_UINT32    suspensionInt;
65688 +    A_UINT32    serviceStartTime;
65689 +    A_UINT32    minDataRate;
65690 +    A_UINT32    meanDataRate;
65691 +    A_UINT32    peakDataRate;
65692 +    A_UINT32    maxBurstSize;
65693 +    A_UINT32    delayBound;
65694 +    A_UINT32    minPhyRate;
65695 +    A_UINT16    sba;
65696 +    A_UINT16    mediumTime;
65697 +} POSTPACK WMM_TSPEC_IE;
65698 +
65699 +
65700 +/*
65701 + * BEACON management packets
65702 + *
65703 + *  octet timestamp[8]
65704 + *  octet beacon interval[2]
65705 + *  octet capability information[2]
65706 + *  information element
65707 + *      octet elemid
65708 + *      octet length
65709 + *      octet information[length]
65710 + */
65711 +
65712 +#define IEEE80211_BEACON_INTERVAL(beacon) \
65713 +    ((beacon)[8] | ((beacon)[9] << 8))
65714 +#define IEEE80211_BEACON_CAPABILITY(beacon) \
65715 +    ((beacon)[10] | ((beacon)[11] << 8))
65716 +
65717 +#define IEEE80211_CAPINFO_ESS               0x0001
65718 +#define IEEE80211_CAPINFO_IBSS              0x0002
65719 +#define IEEE80211_CAPINFO_CF_POLLABLE       0x0004
65720 +#define IEEE80211_CAPINFO_CF_POLLREQ        0x0008
65721 +#define IEEE80211_CAPINFO_PRIVACY           0x0010
65722 +#define IEEE80211_CAPINFO_SHORT_PREAMBLE    0x0020
65723 +#define IEEE80211_CAPINFO_PBCC              0x0040
65724 +#define IEEE80211_CAPINFO_CHNL_AGILITY      0x0080
65725 +/* bits 8-9 are reserved */
65726 +#define IEEE80211_CAPINFO_SHORT_SLOTTIME    0x0400
65727 +#define IEEE80211_CAPINFO_APSD              0x0800
65728 +/* bit 12 is reserved */
65729 +#define IEEE80211_CAPINFO_DSSSOFDM          0x2000
65730 +/* bits 14-15 are reserved */
65731 +
65732 +/*
65733 + * Authentication Modes
65734 + */
65735 +
65736 +enum ieee80211_authmode {
65737 +    IEEE80211_AUTH_NONE     = 0,
65738 +    IEEE80211_AUTH_OPEN     = 1,
65739 +    IEEE80211_AUTH_SHARED   = 2,
65740 +    IEEE80211_AUTH_8021X    = 3,
65741 +    IEEE80211_AUTH_AUTO     = 4,   /* auto-select/accept */
65742 +    /* NB: these are used only for ioctls */
65743 +    IEEE80211_AUTH_WPA      = 5,  /* WPA/RSN  w/ 802.1x */
65744 +    IEEE80211_AUTH_WPA_PSK  = 6,  /* WPA/RSN  w/ PSK */
65745 +    IEEE80211_AUTH_WPA_CCKM = 7,  /* WPA/RSN IE  w/ CCKM */
65746 +};
65747 +
65748 +#include "athendpack.h"
65749 +
65750 +#endif /* _NET80211_IEEE80211_H_ */
65751 --- /dev/null
65752 +++ b/drivers/ar6000/include/ieee80211_ioctl.h
65753 @@ -0,0 +1,163 @@
65754 +/*
65755 + * Copyright (c) 2004-2005 Atheros Communications Inc.
65756 + * All rights reserved.
65757 + *
65758 + *
65759 + *  This program is free software; you can redistribute it and/or modify
65760 + *  it under the terms of the GNU General Public License version 2 as
65761 + *  published by the Free Software Foundation;
65762 + *
65763 + *  Software distributed under the License is distributed on an "AS
65764 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
65765 + *  implied. See the License for the specific language governing
65766 + *  rights and limitations under the License.
65767 + *
65768 + *
65769 + *
65770 + *
65771 + * $Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/include/ieee80211_ioctl.h#1 $
65772 + */
65773 +
65774 +#ifndef _IEEE80211_IOCTL_H_
65775 +#define _IEEE80211_IOCTL_H_
65776 +
65777 +#ifdef __cplusplus
65778 +extern "C" {
65779 +#endif
65780 +
65781 +/*
65782 + * Extracted from the MADWIFI net80211/ieee80211_ioctl.h
65783 + */
65784 +
65785 +/*
65786 + * WPA/RSN get/set key request.  Specify the key/cipher
65787 + * type and whether the key is to be used for sending and/or
65788 + * receiving.  The key index should be set only when working
65789 + * with global keys (use IEEE80211_KEYIX_NONE for ``no index'').
65790 + * Otherwise a unicast/pairwise key is specified by the bssid
65791 + * (on a station) or mac address (on an ap).  They key length
65792 + * must include any MIC key data; otherwise it should be no
65793 + more than IEEE80211_KEYBUF_SIZE.
65794 + */
65795 +struct ieee80211req_key {
65796 +       u_int8_t        ik_type;        /* key/cipher type */
65797 +       u_int8_t        ik_pad;
65798 +       u_int16_t       ik_keyix;       /* key index */
65799 +       u_int8_t        ik_keylen;      /* key length in bytes */
65800 +       u_int8_t        ik_flags;
65801 +#define IEEE80211_KEY_XMIT  0x01
65802 +#define IEEE80211_KEY_RECV  0x02
65803 +#define        IEEE80211_KEY_DEFAULT   0x80    /* default xmit key */
65804 +       u_int8_t        ik_macaddr[IEEE80211_ADDR_LEN];
65805 +       u_int64_t       ik_keyrsc;      /* key receive sequence counter */
65806 +       u_int64_t       ik_keytsc;      /* key transmit sequence counter */
65807 +       u_int8_t        ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE];
65808 +};
65809 +/*
65810 + * Delete a key either by index or address.  Set the index
65811 + * to IEEE80211_KEYIX_NONE when deleting a unicast key.
65812 + */
65813 +struct ieee80211req_del_key {
65814 +       u_int8_t        idk_keyix;      /* key index */
65815 +       u_int8_t        idk_macaddr[IEEE80211_ADDR_LEN];
65816 +};
65817 +/*
65818 + * MLME state manipulation request.  IEEE80211_MLME_ASSOC
65819 + * only makes sense when operating as a station.  The other
65820 + * requests can be used when operating as a station or an
65821 + * ap (to effect a station).
65822 + */
65823 +struct ieee80211req_mlme {
65824 +       u_int8_t        im_op;          /* operation to perform */
65825 +#define        IEEE80211_MLME_ASSOC            1       /* associate station */
65826 +#define        IEEE80211_MLME_DISASSOC         2       /* disassociate station */
65827 +#define        IEEE80211_MLME_DEAUTH           3       /* deauthenticate station */
65828 +#define        IEEE80211_MLME_AUTHORIZE        4       /* authorize station */
65829 +#define        IEEE80211_MLME_UNAUTHORIZE      5       /* unauthorize station */
65830 +       u_int16_t       im_reason;      /* 802.11 reason code */
65831 +       u_int8_t        im_macaddr[IEEE80211_ADDR_LEN];
65832 +};
65833 +
65834 +struct ieee80211req_addpmkid {
65835 +    u_int8_t    pi_bssid[IEEE80211_ADDR_LEN];
65836 +    u_int8_t    pi_enable;
65837 +    u_int8_t    pi_pmkid[16];
65838 +};
65839 +
65840 +#define AUTH_ALG_OPEN_SYSTEM   0x01
65841 +#define AUTH_ALG_SHARED_KEY    0x02
65842 +#define AUTH_ALG_LEAP          0x04
65843 +
65844 +struct ieee80211req_authalg {
65845 +   u_int8_t auth_alg;
65846 +};
65847 +
65848 +/*
65849 + * Request to add an IE to a Management Frame
65850 + */
65851 +enum{
65852 +    IEEE80211_APPIE_FRAME_BEACON     = 0,
65853 +    IEEE80211_APPIE_FRAME_PROBE_REQ  = 1,
65854 +    IEEE80211_APPIE_FRAME_PROBE_RESP = 2,
65855 +    IEEE80211_APPIE_FRAME_ASSOC_REQ  = 3,
65856 +    IEEE80211_APPIE_FRAME_ASSOC_RESP = 4,
65857 +    IEEE80211_APPIE_NUM_OF_FRAME     = 5
65858 +};
65859 +
65860 +/*
65861 + * The Maximum length of the IE that can be added to a Management frame
65862 + */
65863 +#define IEEE80211_APPIE_FRAME_MAX_LEN  78
65864 +
65865 +struct ieee80211req_getset_appiebuf {
65866 +    u_int32_t app_frmtype; /* management frame type for which buffer is added */
65867 +    u_int32_t app_buflen;  /*application supplied buffer length */
65868 +    u_int8_t  app_buf[];
65869 +};
65870 +
65871 +/*
65872 + * The following definitions are used by an application to set filter
65873 + * for receiving management frames
65874 + */
65875 +enum {
65876 +     IEEE80211_FILTER_TYPE_BEACON      =   0x1,
65877 +     IEEE80211_FILTER_TYPE_PROBE_REQ   =   0x2,
65878 +     IEEE80211_FILTER_TYPE_PROBE_RESP  =   0x4,
65879 +     IEEE80211_FILTER_TYPE_ASSOC_REQ   =   0x8,
65880 +     IEEE80211_FILTER_TYPE_ASSOC_RESP  =   0x10,
65881 +     IEEE80211_FILTER_TYPE_AUTH        =   0x20,
65882 +     IEEE80211_FILTER_TYPE_DEAUTH      =   0x40,
65883 +     IEEE80211_FILTER_TYPE_DISASSOC    =   0x80,
65884 +     IEEE80211_FILTER_TYPE_ALL         =   0xFF  /* used to check the valid filter bits */
65885 +};
65886 +
65887 +struct ieee80211req_set_filter {
65888 +      u_int32_t app_filterype; /* management frame filter type */
65889 +};
65890 +
65891 +enum {
65892 +    IEEE80211_PARAM_AUTHMODE = 3,   /* Authentication Mode */
65893 +    IEEE80211_PARAM_MCASTCIPHER = 5,
65894 +    IEEE80211_PARAM_MCASTKEYLEN = 6,    /* multicast key length */
65895 +    IEEE80211_PARAM_UCASTCIPHER = 8,
65896 +    IEEE80211_PARAM_UCASTKEYLEN = 9,    /* unicast key length */
65897 +       IEEE80211_PARAM_WPA             = 10,   /* WPA mode (0,1,2) */
65898 +       IEEE80211_PARAM_ROAMING         = 12,   /* roaming mode */
65899 +       IEEE80211_PARAM_PRIVACY         = 13,   /* privacy invoked */
65900 +       IEEE80211_PARAM_COUNTERMEASURES = 14,   /* WPA/TKIP countermeasures */
65901 +       IEEE80211_PARAM_DROPUNENCRYPTED = 15,   /* discard unencrypted frames */
65902 +};
65903 +
65904 +/*
65905 + * Values for IEEE80211_PARAM_WPA
65906 + */
65907 +#define WPA_MODE_WPA1   1
65908 +#define WPA_MODE_WPA2   2
65909 +#define WPA_MODE_AUTO   3
65910 +#define WPA_MODE_NONE   4
65911 +
65912 +#ifdef __cplusplus
65913 +}
65914 +#endif
65915 +
65916 +#endif /* _IEEE80211_IOCTL_H_ */
65917 --- /dev/null
65918 +++ b/drivers/ar6000/include/ieee80211_node.h
65919 @@ -0,0 +1,77 @@
65920 +/*-
65921 + * Copyright (c) 2001 Atsushi Onoe
65922 + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
65923 + * Copyright (c) 2006 Atheros Communications, Inc.
65924 + *
65925 + * Wireless Network driver for Atheros AR6001
65926 + * All rights reserved.
65927 + *
65928 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
65929 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
65930 + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
65931 + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
65932 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
65933 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
65934 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
65935 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65936 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
65937 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65938 + *
65939 + */
65940 +#ifndef _IEEE80211_NODE_H_
65941 +#define _IEEE80211_NODE_H_
65942 +
65943 +/*
65944 + * Node locking definitions.
65945 + */
65946 +#define IEEE80211_NODE_LOCK_INIT(_nt)   A_MUTEX_INIT(&(_nt)->nt_nodelock)
65947 +#define IEEE80211_NODE_LOCK_DESTROY(_nt)
65948 +#define IEEE80211_NODE_LOCK(_nt)        A_MUTEX_LOCK(&(_nt)->nt_nodelock)
65949 +#define IEEE80211_NODE_UNLOCK(_nt)      A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
65950 +#define IEEE80211_NODE_LOCK_BH(_nt)     A_MUTEX_LOCK(&(_nt)->nt_nodelock)
65951 +#define IEEE80211_NODE_UNLOCK_BH(_nt)   A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
65952 +#define IEEE80211_NODE_LOCK_ASSERT(_nt)
65953 +
65954 +/*
65955 + * Node reference counting definitions.
65956 + *
65957 + * ieee80211_node_initref   initialize the reference count to 1
65958 + * ieee80211_node_incref    add a reference
65959 + * ieee80211_node_decref    remove a reference
65960 + * ieee80211_node_dectestref    remove a reference and return 1 if this
65961 + *              is the last reference, otherwise 0
65962 + * ieee80211_node_refcnt    reference count for printing (only)
65963 + */
65964 +#define ieee80211_node_initref(_ni)     ((_ni)->ni_refcnt = 1)
65965 +#define ieee80211_node_incref(_ni)      ((_ni)->ni_refcnt++)
65966 +#define ieee80211_node_decref(_ni)      ((_ni)->ni_refcnt--)
65967 +#define ieee80211_node_dectestref(_ni)  (((_ni)->ni_refcnt--) == 0)
65968 +#define ieee80211_node_refcnt(_ni)      ((_ni)->ni_refcnt)
65969 +
65970 +#define IEEE80211_NODE_HASHSIZE 32
65971 +/* simple hash is enough for variation of macaddr */
65972 +#define IEEE80211_NODE_HASH(addr)   \
65973 +    (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \
65974 +        IEEE80211_NODE_HASHSIZE)
65975 +
65976 +/*
65977 + * Table of ieee80211_node instances.  Each ieee80211com
65978 + * has at least one for holding the scan candidates.
65979 + * When operating as an access point or in ibss mode there
65980 + * is a second table for associated stations or neighbors.
65981 + */
65982 +struct ieee80211_node_table {
65983 +    void                   *nt_wmip;       /* back reference */
65984 +    A_MUTEX_T               nt_nodelock;    /* on node table */
65985 +    struct bss              *nt_node_first; /* information of all nodes */
65986 +    struct bss              *nt_node_last;  /* information of all nodes */
65987 +    struct bss              *nt_hash[IEEE80211_NODE_HASHSIZE];
65988 +    const char              *nt_name;   /* for debugging */
65989 +    A_UINT32                nt_scangen; /* gen# for timeout scan */
65990 +    A_TIMER                 nt_inact_timer;
65991 +    A_UINT8                 isTimerArmed;   /* is the node timer armed */
65992 +};
65993 +
65994 +#define WLAN_NODE_INACT_TIMEOUT_MSEC            10000
65995 +
65996 +#endif /* _IEEE80211_NODE_H_ */
65997 --- /dev/null
65998 +++ b/drivers/ar6000/include/ini_dset.h
65999 @@ -0,0 +1,40 @@
66000 +/*
66001 + * Copyright (c) 2004-2007 Atheros Communications Inc.
66002 + * All rights reserved.
66003 + *
66004 + * $ATH_LICENSE_HOSTSDK0_C$
66005 + *
66006 + */
66007 +#ifndef _INI_DSET_H_
66008 +#define _INI_DSET_H_
66009 +
66010 +/*
66011 + * Each of these represents a WHAL INI table, which consists
66012 + * of an "address column" followed by 1 or more "value columns".
66013 + *
66014 + * Software uses the base WHAL_INI_DATA_ID+column to access a
66015 + * DataSet that holds a particular column of data.
66016 + */
66017 +typedef enum {
66018 +    WHAL_INI_DATA_ID_NULL               =0,
66019 +    WHAL_INI_DATA_ID_MODE_SPECIFIC      =1,  /* 2,3 */
66020 +    WHAL_INI_DATA_ID_COMMON             =4,  /* 5 */
66021 +    WHAL_INI_DATA_ID_BB_RFGAIN          =6,  /* 7,8 */
66022 +    WHAL_INI_DATA_ID_ANALOG_BANK1       =9,  /* 10 */
66023 +    WHAL_INI_DATA_ID_ANALOG_BANK2       =11, /* 12 */
66024 +    WHAL_INI_DATA_ID_ANALOG_BANK3       =13, /* 14, 15 */
66025 +    WHAL_INI_DATA_ID_ANALOG_BANK6       =16, /* 17, 18 */
66026 +    WHAL_INI_DATA_ID_ANALOG_BANK7       =19, /* 20 */
66027 +    WHAL_INI_DATA_ID_MODE_OVERRIDES     =21, /* 22,23 */
66028 +    WHAL_INI_DATA_ID_COMMON_OVERRIDES   =24, /* 25 */
66029 +
66030 +    WHAL_INI_DATA_ID_MAX                =25
66031 +} WHAL_INI_DATA_ID;
66032 +
66033 +typedef PREPACK struct {
66034 +    A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
66035 +    A_UINT16 offset;
66036 +    A_UINT32 newValue;
66037 +} POSTPACK INI_DSET_REG_OVERRIDE;
66038 +
66039 +#endif
66040 --- /dev/null
66041 +++ b/drivers/ar6000/include/regDb.h
66042 @@ -0,0 +1,19 @@
66043 +/*
66044 + * Copyright (c) 2005 Atheros Communications, Inc.
66045 + * All rights reserved.
66046 + *
66047 + *
66048 + * $ATH_LICENSE_HOSTSDK0_C$
66049 + *
66050 + * This module contains the header files for regulatory module,
66051 + * which include the DB schema and DB values.
66052 + * $Id:
66053 + */
66054 +
66055 +#ifndef __REG_DB_H__
66056 +#define __REG_DB_H__
66057 +
66058 +#include "./regulatory/reg_dbschema.h"
66059 +#include "./regulatory/reg_dbvalues.h"
66060 +
66061 +#endif  /* __REG_DB_H__ */
66062 --- /dev/null
66063 +++ b/drivers/ar6000/include/regdump.h
66064 @@ -0,0 +1,33 @@
66065 +#ifndef __REGDUMP_H__
66066 +#define __REGDUMP_H__
66067 +/*
66068 + * Copyright (c) 2004-2007 Atheros Communications Inc.
66069 + * All rights reserved.
66070 + *
66071 + * $ATH_LICENSE_HOSTSDK0_C$
66072 + *
66073 + */
66074 +#if defined(AR6001)
66075 +#include "AR6001/AR6001_regdump.h"
66076 +#endif
66077 +#if defined(AR6002)
66078 +#include "AR6002/AR6002_regdump.h"
66079 +#endif
66080 +
66081 +#if !defined(__ASSEMBLER__)
66082 +/*
66083 + * Target CPU state at the time of failure is reflected
66084 + * in a register dump, which the Host can fetch through
66085 + * the diagnostic window.
66086 + */
66087 +struct register_dump_s {
66088 +    A_UINT32 target_id;               /* Target ID */
66089 +    A_UINT32 assline;                 /* Line number (if assertion failure) */
66090 +    A_UINT32 pc;                      /* Program Counter at time of exception */
66091 +    A_UINT32 badvaddr;                /* Virtual address causing exception */
66092 +    CPU_exception_frame_t exc_frame;  /* CPU-specific exception info */
66093 +
66094 +    /* Could copy top of stack here, too.... */
66095 +};
66096 +#endif /* __ASSEMBLER__ */
66097 +#endif /* __REGDUMP_H__ */
66098 --- /dev/null
66099 +++ b/drivers/ar6000/include/targaddrs.h
66100 @@ -0,0 +1,158 @@
66101 +/*
66102 + * Copyright (c) 2004-2007 Atheros Communications Inc.
66103 + * All rights reserved.
66104 + *
66105 + * $ATH_LICENSE_HOSTSDK0_C$
66106 + *
66107 + */
66108 +
66109 +#ifndef __TARGADDRS_H__
66110 +#define __TARGADDRS_H__
66111 +#if defined(AR6001)
66112 +#include "AR6001/addrs.h"
66113 +#endif
66114 +#if defined(AR6002)
66115 +#include "AR6002/addrs.h"
66116 +#endif
66117 +
66118 +/*
66119 + * AR6K option bits, to enable/disable various features.
66120 + * By default, all option bits are 0.
66121 + * These bits can be set in LOCAL_SCRATCH register 0.
66122 + */
66123 +#define AR6K_OPTION_BMI_DISABLE      0x01 /* Disable BMI comm with Host */
66124 +#define AR6K_OPTION_SERIAL_ENABLE    0x02 /* Enable serial port msgs */
66125 +#define AR6K_OPTION_WDT_DISABLE      0x04 /* WatchDog Timer override */
66126 +#define AR6K_OPTION_SLEEP_DISABLE    0x08 /* Disable system sleep */
66127 +#define AR6K_OPTION_STOP_BOOT        0x10 /* Stop boot processes (for ATE) */
66128 +#define AR6K_OPTION_ENABLE_NOANI     0x20 /* Operate without ANI */
66129 +#define AR6K_OPTION_DSET_DISABLE     0x40 /* Ignore DataSets */
66130 +#define AR6K_OPTION_IGNORE_FLASH     0x80 /* Ignore flash during bootup */
66131 +
66132 +/*
66133 + * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
66134 + * host_interest structure.  It must match the address of the _host_interest
66135 + * symbol (see linker script).
66136 + *
66137 + * Host Interest is shared between Host and Target in order to coordinate
66138 + * between the two, and is intended to remain constant (with additions only
66139 + * at the end) across software releases.
66140 + */
66141 +#define AR6001_HOST_INTEREST_ADDRESS     0x80000600
66142 +#define AR6002_HOST_INTEREST_ADDRESS     0x00500400
66143 +
66144 +#define HOST_INTEREST_MAX_SIZE          0x100
66145 +
66146 +#if !defined(__ASSEMBLER__)
66147 +struct register_dump_s;
66148 +struct dbglog_hdr_s;
66149 +
66150 +/*
66151 + * These are items that the Host may need to access
66152 + * via BMI or via the Diagnostic Window. The position
66153 + * of items in this structure must remain constant
66154 + * across firmware revisions!
66155 + *
66156 + * Types for each item must be fixed size across
66157 + * target and host platforms.
66158 + *
66159 + * More items may be added at the end.
66160 + */
66161 +struct host_interest_s {
66162 +    /*
66163 +     * Pointer to application-defined area, if any.
66164 +     * Set by Target application during startup.
66165 +     */
66166 +    A_UINT32               hi_app_host_interest;                      /* 0x00 */
66167 +
66168 +    /* Pointer to register dump area, valid after Target crash. */
66169 +    A_UINT32               hi_failure_state;                          /* 0x04 */
66170 +
66171 +    /* Pointer to debug logging header */
66172 +    A_UINT32               hi_dbglog_hdr;                             /* 0x08 */
66173 +
66174 +    /* Indicates whether or not flash is present on Target.
66175 +     * NB: flash_is_present indicator is here not just
66176 +     * because it might be of interest to the Host; but
66177 +     * also because it's set early on by Target's startup
66178 +     * asm code and we need it to have a special RAM address
66179 +     * so that it doesn't get reinitialized with the rest
66180 +     * of data.
66181 +     */
66182 +    A_UINT32               hi_flash_is_present;                       /* 0x0c */
66183 +
66184 +    /*
66185 +     * General-purpose flag bits, similar to AR6000_OPTION_* flags.
66186 +     * Can be used by application rather than by OS.
66187 +     */
66188 +    A_UINT32               hi_option_flag;                            /* 0x10 */
66189 +
66190 +    /*
66191 +     * Boolean that determines whether or not to
66192 +     * display messages on the serial port.
66193 +     */
66194 +    A_UINT32               hi_serial_enable;                          /* 0x14 */
66195 +
66196 +    /* Start address of Flash DataSet index, if any */
66197 +    A_UINT32               hi_dset_list_head;                         /* 0x18 */
66198 +
66199 +    /* Override Target application start address */
66200 +    A_UINT32               hi_app_start;                              /* 0x1c */
66201 +
66202 +    /* Clock and voltage tuning */
66203 +    A_UINT32               hi_skip_clock_init;                        /* 0x20 */
66204 +    A_UINT32               hi_core_clock_setting;                     /* 0x24 */
66205 +    A_UINT32               hi_cpu_clock_setting;                      /* 0x28 */
66206 +    A_UINT32               hi_system_sleep_setting;                   /* 0x2c */
66207 +    A_UINT32               hi_xtal_control_setting;                   /* 0x30 */
66208 +    A_UINT32               hi_pll_ctrl_setting_24ghz;                 /* 0x34 */
66209 +    A_UINT32               hi_pll_ctrl_setting_5ghz;                  /* 0x38 */
66210 +    A_UINT32               hi_ref_voltage_trim_setting;               /* 0x3c */
66211 +    A_UINT32               hi_clock_info;                             /* 0x40 */
66212 +
66213 +    /*
66214 +     * Flash configuration overrides, used only
66215 +     * when firmware is not executing from flash.
66216 +     * (When using flash, modify the global variables
66217 +     * with equivalent names.)
66218 +     */
66219 +    A_UINT32               hi_bank0_addr_value;                       /* 0x44 */
66220 +    A_UINT32               hi_bank0_read_value;                       /* 0x48 */
66221 +    A_UINT32               hi_bank0_write_value;                      /* 0x4c */
66222 +    A_UINT32               hi_bank0_config_value;                     /* 0x50 */
66223 +
66224 +    /* Pointer to Board Data  */
66225 +    A_UINT32               hi_board_data;                             /* 0x54 */
66226 +    A_UINT32               hi_board_data_initialized;                 /* 0x58 */
66227 +
66228 +    A_UINT32               hi_dset_RAM_index_table;                   /* 0x5c */
66229 +
66230 +    A_UINT32               hi_desired_baud_rate;                      /* 0x60 */
66231 +    A_UINT32               hi_dbglog_config;                          /* 0x64 */
66232 +    A_UINT32               hi_end_RAM_reserve_sz;                     /* 0x68 */
66233 +    A_UINT32               hi_mbox_io_block_sz;                       /* 0x6c */
66234 +
66235 +    A_UINT32               hi_num_bpatch_streams;                     /* 0x70 */
66236 +    A_UINT32               hi_mbox_isr_yield_limit;                   /* 0x74 */
66237 +
66238 +    A_UINT32               hi_refclk_hz;                              /* 0x78 */
66239 +};
66240 +
66241 +/* Bits defined in hi_option_flag */
66242 +#define HI_OPTION_TIMER_WAR     1 /* not really used */
66243 +
66244 +/*
66245 + * Intended for use by Host software, this macro returns the Target RAM
66246 + * address of any item in the host_interest structure.
66247 + * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
66248 + */
66249 +#define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \
66250 +    ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->item)))
66251 +
66252 +#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
66253 +    ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
66254 +
66255 +
66256 +#endif /* !__ASSEMBLER__ */
66257 +
66258 +#endif /* __TARGADDRS_H__ */
66259 --- /dev/null
66260 +++ b/drivers/ar6000/include/testcmd.h
66261 @@ -0,0 +1,144 @@
66262 +/*
66263 + * Copyright (c) 2004-2005 Atheros Communications Inc.
66264 + * All rights reserved.
66265 + *
66266 + *
66267 + * $ATH_LICENSE_HOSTSDK0_C$
66268 + *
66269 + */
66270 +
66271 +#ifndef  TESTCMD_H_
66272 +#define  TESTCMD_H_
66273 +
66274 +#ifdef __cplusplus
66275 +extern "C" {
66276 +#endif
66277 +
66278 +typedef enum {
66279 +    ZEROES_PATTERN = 0,
66280 +    ONES_PATTERN,
66281 +    REPEATING_10,
66282 +    PN7_PATTERN,
66283 +    PN9_PATTERN,
66284 +    PN15_PATTERN
66285 +}TX_DATA_PATTERN;
66286 +
66287 +/* Continous tx
66288 +   mode : TCMD_CONT_TX_OFF - Disabling continous tx
66289 +          TCMD_CONT_TX_SINE - Enable continuous unmodulated tx
66290 +          TCMD_CONT_TX_FRAME- Enable continuous modulated tx
66291 +   freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g)
66292 +dataRate: 0 - 1 Mbps
66293 +          1 - 2 Mbps
66294 +          2 - 5.5 Mbps
66295 +          3 - 11 Mbps
66296 +          4 - 6 Mbps
66297 +          5 - 9 Mbps
66298 +          6 - 12 Mbps
66299 +          7 - 18 Mbps
66300 +          8 - 24 Mbps
66301 +          9 - 36 Mbps
66302 +         10 - 28 Mbps
66303 +         11 - 54 Mbps
66304 +  txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx
66305 +antenna:  1 - one antenna
66306 +          2 - two antenna
66307 +Note : Enable/disable continuous tx test cmd works only when target is awake.
66308 +*/
66309 +
66310 +typedef enum {
66311 +    TCMD_CONT_TX_OFF = 0,
66312 +    TCMD_CONT_TX_SINE,
66313 +    TCMD_CONT_TX_FRAME,
66314 +    TCMD_CONT_TX_TX99,
66315 +    TCMD_CONT_TX_TX100
66316 +} TCMD_CONT_TX_MODE;
66317 +
66318 +typedef PREPACK struct {
66319 +    A_UINT32                 testCmdId;
66320 +    A_UINT32                mode;
66321 +    A_UINT32                freq;
66322 +    A_UINT32                dataRate;
66323 +    A_INT32                 txPwr;
66324 +    A_UINT32                antenna;
66325 +    A_UINT32                enANI;
66326 +    A_UINT32                scramblerOff;
66327 +    A_UINT32                aifsn;
66328 +    A_UINT16                pktSz;
66329 +    A_UINT16                txPattern;
66330 +} POSTPACK TCMD_CONT_TX;
66331 +
66332 +#define TCMD_TXPATTERN_ZERONE                 0x1
66333 +#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE    0x2
66334 +
66335 +/* Continuous Rx
66336 + act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames)
66337 +      TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest
66338 +                                             address equal specified
66339 +                                             mac address (set via act =3)
66340 +      TCMD_CONT_RX_REPORT  off mode  (disable cont rx mode and get the
66341 +                                          report from the last cont
66342 +                                          Rx test)
66343 +
66344 +     TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the
66345 +                                                 target. This Overrides
66346 +                                                 the default MAC address.)
66347 +
66348 +*/
66349 +typedef enum {
66350 +    TCMD_CONT_RX_PROMIS =0,
66351 +    TCMD_CONT_RX_FILTER,
66352 +    TCMD_CONT_RX_REPORT,
66353 +    TCMD_CONT_RX_SETMAC
66354 +} TCMD_CONT_RX_ACT;
66355 +
66356 +typedef PREPACK struct {
66357 +    A_UINT32         testCmdId;
66358 +    A_UINT32        act;
66359 +    A_UINT32        enANI;
66360 +    PREPACK union {
66361 +        struct PREPACK TCMD_CONT_RX_PARA {
66362 +            A_UINT32    freq;
66363 +            A_UINT32    antenna;
66364 +        } POSTPACK para;
66365 +        struct PREPACK TCMD_CONT_RX_REPORT {
66366 +            A_UINT32    totalPkt;
66367 +            A_INT32    rssiInDBm;
66368 +        } POSTPACK report;
66369 +        struct PREPACK TCMD_CONT_RX_MAC {
66370 +            A_UCHAR    addr[ATH_MAC_LEN];
66371 +        } POSTPACK mac;
66372 +    } POSTPACK u;
66373 +} POSTPACK TCMD_CONT_RX;
66374 +
66375 +/* Force sleep/wake  test cmd
66376 + mode: TCMD_PM_WAKEUP - Wakeup the target
66377 +       TCMD_PM_SLEEP - Force the target to sleep.
66378 + */
66379 +typedef enum {
66380 +    TCMD_PM_WAKEUP = 1, /* be consistent with target */
66381 +    TCMD_PM_SLEEP
66382 +} TCMD_PM_MODE;
66383 +
66384 +typedef PREPACK struct {
66385 +       A_UINT32  testCmdId;
66386 +    A_UINT32  mode;
66387 +} POSTPACK TCMD_PM;
66388 +
66389 +typedef enum{
66390 +    TCMD_CONT_TX_ID,
66391 +    TCMD_CONT_RX_ID,
66392 +    TCMD_PM_ID
66393 +   } TCMD_ID;
66394 +
66395 +typedef PREPACK union {
66396 +          TCMD_CONT_TX contTx;
66397 +          TCMD_CONT_RX contRx;
66398 +          TCMD_PM pm ;
66399 +} POSTPACK TEST_CMD;
66400 +
66401 +#ifdef __cplusplus
66402 +}
66403 +#endif
66404 +
66405 +#endif /* TESTCMD_H_ */
66406 --- /dev/null
66407 +++ b/drivers/ar6000/include/wlan_api.h
66408 @@ -0,0 +1,101 @@
66409 +#ifndef _HOST_WLAN_API_H_
66410 +#define _HOST_WLAN_API_H_
66411 +/*
66412 + * Copyright (c) 2004-2005 Atheros Communications Inc.
66413 + * All rights reserved.
66414 + *
66415 + * This file contains the API for the host wlan module
66416 + *
66417 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/wlan_api.h#1 $
66418 + *
66419 + *
66420 + *  This program is free software; you can redistribute it and/or modify
66421 + *  it under the terms of the GNU General Public License version 2 as
66422 + *  published by the Free Software Foundation;
66423 + *
66424 + *  Software distributed under the License is distributed on an "AS
66425 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
66426 + *  implied. See the License for the specific language governing
66427 + *  rights and limitations under the License.
66428 + *
66429 + *
66430 + *
66431 + */
66432 +
66433 +#ifdef __cplusplus
66434 +extern "C" {
66435 +#endif
66436 +
66437 +struct ieee80211_node_table;
66438 +struct ieee80211_frame;
66439 +
66440 +struct ieee80211_common_ie {
66441 +    A_UINT16    ie_chan;
66442 +    A_UINT8     *ie_tstamp;
66443 +    A_UINT8     *ie_ssid;
66444 +    A_UINT8     *ie_rates;
66445 +    A_UINT8     *ie_xrates;
66446 +    A_UINT8     *ie_country;
66447 +    A_UINT8     *ie_wpa;
66448 +    A_UINT8     *ie_rsn;
66449 +    A_UINT8     *ie_wmm;
66450 +    A_UINT8     *ie_ath;
66451 +    A_UINT16    ie_capInfo;
66452 +    A_UINT16    ie_beaconInt;
66453 +    A_UINT8     *ie_tim;
66454 +    A_UINT8     *ie_chswitch;
66455 +    A_UINT8     ie_erp;
66456 +    A_UINT8     *ie_wsc;
66457 +};
66458 +
66459 +typedef struct bss {
66460 +    A_UINT8                      ni_macaddr[6];
66461 +    A_UINT8                      ni_snr;
66462 +    A_INT16                      ni_rssi;
66463 +    struct bss                   *ni_list_next;
66464 +    struct bss                   *ni_list_prev;
66465 +    struct bss                   *ni_hash_next;
66466 +    struct bss                   *ni_hash_prev;
66467 +    struct ieee80211_common_ie   ni_cie;
66468 +    A_UINT8                     *ni_buf;
66469 +    struct ieee80211_node_table *ni_table;
66470 +    A_UINT32                     ni_refcnt;
66471 +    int                          ni_scangen;
66472 +    A_UINT32                     ni_tstamp;
66473 +} bss_t;
66474 +
66475 +typedef void wlan_node_iter_func(void *arg, bss_t *);
66476 +
66477 +bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size);
66478 +void wlan_node_free(bss_t *ni);
66479 +void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
66480 +                const A_UINT8 *macaddr);
66481 +bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr);
66482 +void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni);
66483 +void wlan_free_allnodes(struct ieee80211_node_table *nt);
66484 +void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
66485 +                        void *arg);
66486 +
66487 +void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt);
66488 +void wlan_node_table_reset(struct ieee80211_node_table *nt);
66489 +void wlan_node_table_cleanup(struct ieee80211_node_table *nt);
66490 +
66491 +A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen,
66492 +                           struct ieee80211_common_ie *cie);
66493 +
66494 +A_UINT16 wlan_ieee2freq(int chan);
66495 +A_UINT32 wlan_freq2ieee(A_UINT16 freq);
66496 +
66497 +
66498 +bss_t *
66499 +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
66500 +                                       A_UINT32 ssidLength, A_BOOL bIsWPA2);
66501 +
66502 +void
66503 +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni);
66504 +
66505 +#ifdef __cplusplus
66506 +}
66507 +#endif
66508 +
66509 +#endif /* _HOST_WLAN_API_H_ */
66510 --- /dev/null
66511 +++ b/drivers/ar6000/include/wlan_dset.h
66512 @@ -0,0 +1,20 @@
66513 +/*
66514 + * Copyright (c) 2007 Atheros Communications, Inc.
66515 + * All rights reserved.
66516 + *
66517 + *
66518 + * $ATH_LICENSE_HOSTSDK0_C$
66519 + *
66520 + */
66521 +
66522 +#ifndef __WLAN_DSET_H__
66523 +#define __WKAN_DSET_H__
66524 +
66525 +typedef PREPACK struct wow_config_dset {
66526 +
66527 +    A_UINT8 valid_dset;
66528 +    A_UINT8 gpio_enable;
66529 +    A_UINT16 gpio_pin;
66530 +} POSTPACK WOW_CONFIG_DSET;
66531 +
66532 +#endif
66533 --- /dev/null
66534 +++ b/drivers/ar6000/include/wmi_api.h
66535 @@ -0,0 +1,260 @@
66536 +#ifndef _WMI_API_H_
66537 +#define _WMI_API_H_
66538 +/*
66539 + * Copyright (c) 2004-2006 Atheros Communications Inc.
66540 + * All rights reserved.
66541 + *
66542 + * This file contains the definitions for the Wireless Module Interface (WMI).
66543 + *
66544 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/wmi_api.h#2 $
66545 + *
66546 + *
66547 + *  This program is free software; you can redistribute it and/or modify
66548 + *  it under the terms of the GNU General Public License version 2 as
66549 + *  published by the Free Software Foundation;
66550 + *
66551 + *  Software distributed under the License is distributed on an "AS
66552 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
66553 + *  implied. See the License for the specific language governing
66554 + *  rights and limitations under the License.
66555 + *
66556 + *
66557 + *
66558 + */
66559 +
66560 +#ifdef __cplusplus
66561 +extern "C" {
66562 +#endif
66563 +
66564 +/*
66565 + * IP QoS Field definitions according to 802.1p
66566 + */
66567 +#define BEST_EFFORT_PRI         0
66568 +#define BACKGROUND_PRI          1
66569 +#define EXCELLENT_EFFORT_PRI    3
66570 +#define CONTROLLED_LOAD_PRI     4
66571 +#define VIDEO_PRI               5
66572 +#define VOICE_PRI               6
66573 +#define NETWORK_CONTROL_PRI     7
66574 +#define MAX_NUM_PRI             8
66575 +
66576 +#define UNDEFINED_PRI           (0xff)
66577 +
66578 +/* simple mapping of IP TOS field to a WMI priority stream
66579 + * this mapping was taken from the original linux driver implementation
66580 + * The operation maps the following
66581 + *
66582 + *  */
66583 +#define IP_TOS_TO_WMI_PRI(tos)  \
66584 +    ((WMI_PRI_STREAM_ID)(((tos) >> 1) & 0x03))
66585 +
66586 +#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */
66587 +
66588 +
66589 +struct wmi_t;
66590 +
66591 +void *wmi_init(void *devt);
66592 +
66593 +void wmi_qos_state_init(struct wmi_t *wmip);
66594 +void wmi_shutdown(struct wmi_t *wmip);
66595 +A_UINT16  wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8);
66596 +A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf);
66597 +A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType);
66598 +A_STATUS wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf);
66599 +A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf);
66600 +A_STATUS wmi_syncpoint(struct wmi_t *wmip);
66601 +A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip);
66602 +WMI_PRI_STREAM_ID wmi_get_stream_id(struct wmi_t *wmip, A_UINT8 trafficClass);
66603 +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT8 dir, A_UINT8 up);
66604 +
66605 +A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf);
66606 +void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg);
66607 +void wmi_free_allnodes(struct wmi_t *wmip);
66608 +bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr);
66609 +
66610 +
66611 +typedef enum {
66612 +    NO_SYNC_WMIFLAG = 0,
66613 +    SYNC_BEFORE_WMIFLAG,            /* transmit all queued data before cmd */
66614 +    SYNC_AFTER_WMIFLAG,             /* any new data waits until cmd execs */
66615 +    SYNC_BOTH_WMIFLAG,
66616 +    END_WMIFLAG                     /* end marker */
66617 +} WMI_SYNC_FLAG;
66618 +
66619 +A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
66620 +                      WMI_SYNC_FLAG flag);
66621 +A_STATUS wmi_connect_cmd(struct wmi_t *wmip,
66622 +                         NETWORK_TYPE netType,
66623 +                         DOT11_AUTH_MODE dot11AuthMode,
66624 +                         AUTH_MODE authMode,
66625 +                         CRYPTO_TYPE pairwiseCrypto,
66626 +                         A_UINT8 pairwiseCryptoLen,
66627 +                         CRYPTO_TYPE groupCrypto,
66628 +                         A_UINT8 groupCryptoLen,
66629 +                         int ssidLength,
66630 +                         A_UCHAR *ssid,
66631 +                         A_UINT8 *bssid,
66632 +                         A_UINT16 channel,
66633 +                         A_UINT32 ctrl_flags);
66634 +A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip,
66635 +                           A_UINT8 *bssid,
66636 +                           A_UINT16 channel);
66637 +A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip);
66638 +A_STATUS wmi_getrev_cmd(struct wmi_t *wmip);
66639 +A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
66640 +                           A_BOOL forceFgScan, A_BOOL isLegacy,
66641 +                           A_UINT32 homeDwellTime, A_UINT32 forceScanInterval);
66642 +A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
66643 +                            A_UINT16 fg_end_sec, A_UINT16 bg_sec,
66644 +                            A_UINT16 minact_chdw_msec,
66645 +                            A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec,
66646 +                            A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
66647 +                            A_UINT32 max_dfsch_act_time);
66648 +A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask);
66649 +A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
66650 +                            A_UINT8 ssidLength, A_UCHAR *ssid);
66651 +A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons);
66652 +A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons);
66653 +A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
66654 +                           A_UINT8 ieLen, A_UINT8 *ieInfo);
66655 +A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode);
66656 +A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
66657 +                            A_UINT16 atim_windows, A_UINT16 timeout_value);
66658 +A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
66659 +                           A_UINT16 psPollNum, A_UINT16 dtimPolicy);
66660 +A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout);
66661 +A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber);
66662 +A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream);
66663 +A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID);
66664 +A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 rate);
66665 +A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip);
66666 +A_INT8   wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate);
66667 +A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip);
66668 +A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip);
66669 +A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
66670 +                                   WMI_PHY_MODE mode, A_INT8 numChan,
66671 +                                   A_UINT16 *channelList);
66672 +
66673 +A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip,
66674 +                                       WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
66675 +A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip,
66676 +                                        WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
66677 +A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip);
66678 +A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip,
66679 +                                      WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd);
66680 +A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold);
66681 +A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status);
66682 +
66683 +A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask);
66684 +
66685 +A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie,
66686 +                                    A_UINT32 source);
66687 +A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
66688 +                                     A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
66689 +                                     A_UINT32 valid);
66690 +A_STATUS wmi_get_stats_cmd(struct wmi_t *wmip);
66691 +A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex,
66692 +                        CRYPTO_TYPE keyType, A_UINT8 keyUsage,
66693 +                        A_UINT8 keyLength,A_UINT8 *keyRSC,
66694 +                        A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl,
66695 +                        WMI_SYNC_FLAG sync_flag);
66696 +A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk);
66697 +A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip);
66698 +A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex);
66699 +A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip,
66700 +                                 WMI_SET_AKMP_PARAMS_CMD *akmpParams);
66701 +A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip);
66702 +A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
66703 +                                WMI_SET_PMKID_LIST_CMD *pmkInfo);
66704 +A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM);
66705 +A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip);
66706 +A_STATUS wmi_switch_radio(struct wmi_t *wmip, A_UINT8 on);
66707 +A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid);
66708 +A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex);
66709 +A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en);
66710 +A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
66711 +                          A_BOOL set);
66712 +A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop,
66713 +                                   A_UINT8 eCWmin, A_UINT8 eCWmax,
66714 +                                   A_UINT8 aifsn);
66715 +A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
66716 +                                  A_UINT8 trafficClass, A_UINT8 maxRetries,
66717 +                                  A_UINT8 enableNotify);
66718 +
66719 +void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid);
66720 +
66721 +A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip);
66722 +A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType);
66723 +A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
66724 +                               A_UINT8 size);
66725 +A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
66726 +                            WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
66727 +                            A_UINT8 size);
66728 +
66729 +A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode);
66730 +A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
66731 +                              A_UINT8 frmType,
66732 +                              A_UINT8 *dstMacAddr,
66733 +                              A_UINT8 *bssid,
66734 +                              A_UINT16 optIEDataLen,
66735 +                              A_UINT8 *optIEData);
66736 +
66737 +A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl);
66738 +A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize);
66739 +A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen);
66740 +A_UINT8  convert_userPriority_to_trafficClass(A_UINT8 userPriority);
66741 +A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip);
66742 +A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance);
66743 +
66744 +#ifdef CONFIG_HOST_TCMD_SUPPORT
66745 +A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32  len);
66746 +#endif
66747 +
66748 +A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status);
66749 +A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd);
66750 +
66751 +
66752 +/*
66753 + *  This function is used to configure the fix rates mask to the target.
66754 + */
66755 +A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask);
66756 +A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip);
66757 +
66758 +A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
66759 +
66760 +A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
66761 +
66762 +A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status);
66763 +A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable);
66764 +
66765 +A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip);
66766 +A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip);
66767 +A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval);
66768 +
66769 +A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType,
66770 +                           A_UINT8 ieLen,A_UINT8 *ieInfo);
66771 +
66772 +A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen);
66773 +A_INT32 wmi_get_rate(A_INT8 rateindex);
66774 +
66775 +/*Wake on Wireless WMI commands*/
66776 +A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd);
66777 +A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd);
66778 +A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd);
66779 +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
66780 +                                 WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size);
66781 +A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
66782 +                                 WMI_DEL_WOW_PATTERN_CMD *cmd);
66783 +A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status);
66784 +
66785 +bss_t *
66786 +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
66787 +                                  A_UINT32 ssidLength, A_BOOL bIsWPA2);
66788 +
66789 +void
66790 +wmi_node_return (struct wmi_t *wmip, bss_t *bss);
66791 +#ifdef __cplusplus
66792 +}
66793 +#endif
66794 +
66795 +#endif /* _WMI_API_H_ */
66796 --- /dev/null
66797 +++ b/drivers/ar6000/include/wmi.h
66798 @@ -0,0 +1,1743 @@
66799 +/*
66800 + * Copyright (c) 2004-2006 Atheros Communications Inc.
66801 + * All rights reserved.
66802 + *
66803 + *
66804 + * $ATH_LICENSE_HOSTSDK0_C$
66805 + *
66806 + * This file contains the definitions of the WMI protocol specified in the
66807 + * Wireless Module Interface (WMI).  It includes definitions of all the
66808 + * commands and events. Commands are messages from the host to the WM.
66809 + * Events and Replies are messages from the WM to the host.
66810 + *
66811 + * Ownership of correctness in regards to WMI commands
66812 + * belongs to the host driver and the WM is not required to validate
66813 + * parameters for value, proper range, or any other checking.
66814 + *
66815 + */
66816 +
66817 +#ifndef _WMI_H_
66818 +#define _WMI_H_
66819 +
66820 +#ifndef ATH_TARGET
66821 +#include "athstartpack.h"
66822 +#endif
66823 +
66824 +#include "wmix.h"
66825 +
66826 +#ifdef __cplusplus
66827 +extern "C" {
66828 +#endif
66829 +
66830 +#define WMI_PROTOCOL_VERSION    0x0002
66831 +#define WMI_PROTOCOL_REVISION   0x0000
66832 +
66833 +#define ATH_MAC_LEN             6               /* length of mac in bytes */
66834 +#define WMI_CMD_MAX_LEN         100
66835 +#define WMI_CONTROL_MSG_MAX_LEN     256
66836 +#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536
66837 +#define IS_ETHERTYPE(_typeOrLen)        ((_typeOrLen) >= 0x0600)
66838 +#define RFC1042OUI      {0x00, 0x00, 0x00}
66839 +
66840 +#define IP_ETHERTYPE 0x0800
66841 +
66842 +#define WMI_IMPLICIT_PSTREAM 0xFF
66843 +#define WMI_MAX_THINSTREAM 15
66844 +
66845 +struct host_app_area_s {
66846 +    A_UINT32 wmi_protocol_ver;
66847 +};
66848 +
66849 +/*
66850 + * Data Path
66851 + */
66852 +typedef PREPACK struct {
66853 +    A_UINT8     dstMac[ATH_MAC_LEN];
66854 +    A_UINT8     srcMac[ATH_MAC_LEN];
66855 +    A_UINT16    typeOrLen;
66856 +} POSTPACK ATH_MAC_HDR;
66857 +
66858 +typedef PREPACK struct {
66859 +    A_UINT8     dsap;
66860 +    A_UINT8     ssap;
66861 +    A_UINT8     cntl;
66862 +    A_UINT8     orgCode[3];
66863 +    A_UINT16    etherType;
66864 +} POSTPACK ATH_LLC_SNAP_HDR;
66865 +
66866 +typedef enum {
66867 +    DATA_MSGTYPE = 0x0,
66868 +    CNTL_MSGTYPE,
66869 +    SYNC_MSGTYPE
66870 +} WMI_MSG_TYPE;
66871 +
66872 +
66873 +typedef PREPACK struct {
66874 +    A_INT8      rssi;
66875 +    A_UINT8     info;            /* WMI_MSG_TYPE in lower 2 bits - b1b0 */
66876 +                                 /* UP in next 3 bits - b4b3b2 */
66877 +#define WMI_DATA_HDR_MSG_TYPE_MASK  0x03
66878 +#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0
66879 +#define WMI_DATA_HDR_UP_MASK        0x07
66880 +#define WMI_DATA_HDR_UP_SHIFT       2
66881 +#define WMI_DATA_HDR_IS_MSG_TYPE(h, t)  (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t))
66882 +} POSTPACK WMI_DATA_HDR;
66883 +
66884 +
66885 +#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT))
66886 +#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT))
66887 +
66888 +/*
66889 + * Control Path
66890 + */
66891 +typedef PREPACK struct {
66892 +    A_UINT16    commandId;
66893 +} POSTPACK WMI_CMD_HDR;        /* used for commands and events */
66894 +
66895 +/*
66896 + * List of Commnands
66897 + */
66898 +typedef enum {
66899 +    WMI_CONNECT_CMDID           = 0x0001,
66900 +    WMI_RECONNECT_CMDID,
66901 +    WMI_DISCONNECT_CMDID,
66902 +    WMI_SYNCHRONIZE_CMDID,
66903 +    WMI_CREATE_PSTREAM_CMDID,
66904 +    WMI_DELETE_PSTREAM_CMDID,
66905 +    WMI_START_SCAN_CMDID,
66906 +    WMI_SET_SCAN_PARAMS_CMDID,
66907 +    WMI_SET_BSS_FILTER_CMDID,
66908 +    WMI_SET_PROBED_SSID_CMDID,
66909 +    WMI_SET_LISTEN_INT_CMDID,
66910 +    WMI_SET_BMISS_TIME_CMDID,
66911 +    WMI_SET_DISC_TIMEOUT_CMDID,
66912 +    WMI_GET_CHANNEL_LIST_CMDID,
66913 +    WMI_SET_BEACON_INT_CMDID,
66914 +    WMI_GET_STATISTICS_CMDID,
66915 +    WMI_SET_CHANNEL_PARAMS_CMDID,
66916 +    WMI_SET_POWER_MODE_CMDID,
66917 +    WMI_SET_IBSS_PM_CAPS_CMDID,
66918 +    WMI_SET_POWER_PARAMS_CMDID,
66919 +    WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
66920 +    WMI_ADD_CIPHER_KEY_CMDID,
66921 +    WMI_DELETE_CIPHER_KEY_CMDID,
66922 +    WMI_ADD_KRK_CMDID,
66923 +    WMI_DELETE_KRK_CMDID,
66924 +    WMI_SET_PMKID_CMDID,
66925 +    WMI_SET_TX_PWR_CMDID,
66926 +    WMI_GET_TX_PWR_CMDID,
66927 +    WMI_SET_ASSOC_INFO_CMDID,
66928 +    WMI_ADD_BAD_AP_CMDID,
66929 +    WMI_DELETE_BAD_AP_CMDID,
66930 +    WMI_SET_TKIP_COUNTERMEASURES_CMDID,
66931 +    WMI_RSSI_THRESHOLD_PARAMS_CMDID,
66932 +    WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
66933 +    WMI_SET_ACCESS_PARAMS_CMDID,
66934 +    WMI_SET_RETRY_LIMITS_CMDID,
66935 +    WMI_SET_OPT_MODE_CMDID,
66936 +    WMI_OPT_TX_FRAME_CMDID,
66937 +    WMI_SET_VOICE_PKT_SIZE_CMDID,
66938 +    WMI_SET_MAX_SP_LEN_CMDID,
66939 +    WMI_SET_ROAM_CTRL_CMDID,
66940 +    WMI_GET_ROAM_TBL_CMDID,
66941 +    WMI_GET_ROAM_DATA_CMDID,
66942 +    WMI_ENABLE_RM_CMDID,
66943 +    WMI_SET_MAX_OFFHOME_DURATION_CMDID,
66944 +    WMI_EXTENSION_CMDID,                        /* Non-wireless extensions */
66945 +    WMI_SNR_THRESHOLD_PARAMS_CMDID,
66946 +    WMI_LQ_THRESHOLD_PARAMS_CMDID,
66947 +    WMI_SET_LPREAMBLE_CMDID,
66948 +    WMI_SET_RTS_CMDID,
66949 +    WMI_CLR_RSSI_SNR_CMDID,
66950 +    WMI_SET_FIXRATES_CMDID,
66951 +    WMI_GET_FIXRATES_CMDID,
66952 +    WMI_SET_AUTH_MODE_CMDID,
66953 +    WMI_SET_REASSOC_MODE_CMDID,
66954 +    WMI_SET_WMM_CMDID,
66955 +    WMI_SET_WMM_TXOP_CMDID,
66956 +    WMI_TEST_CMDID,
66957 +    WMI_SET_BT_STATUS_CMDID,
66958 +    WMI_SET_BT_PARAMS_CMDID,
66959 +
66960 +    WMI_SET_KEEPALIVE_CMDID,
66961 +    WMI_GET_KEEPALIVE_CMDID,
66962 +    WMI_SET_APPIE_CMDID,
66963 +    WMI_GET_APPIE_CMDID,
66964 +    WMI_SET_WSC_STATUS_CMDID,
66965 +
66966 +    /* Wake on Wireless */
66967 +    WMI_SET_HOST_SLEEP_MODE_CMDID,
66968 +    WMI_SET_WOW_MODE_CMDID,
66969 +    WMI_GET_WOW_LIST_CMDID,
66970 +    WMI_ADD_WOW_PATTERN_CMDID,
66971 +    WMI_DEL_WOW_PATTERN_CMDID,
66972 +    WMI_SET_MAC_ADDRESS_CMDID,
66973 +    WMI_SET_AKMP_PARAMS_CMDID,
66974 +    WMI_SET_PMKID_LIST_CMDID,
66975 +    WMI_GET_PMKID_LIST_CMDID,
66976 +
66977 +    /*
66978 +     * Developer commands starts at 0xF000
66979 +     */
66980 +    WMI_SET_BITRATE_CMDID = 0xF000,
66981 +    WMI_GET_BITRATE_CMDID,
66982 +    WMI_SET_WHALPARAM_CMDID,
66983 +
66984 +} WMI_COMMAND_ID;
66985 +
66986 +/*
66987 + * Frame Types
66988 + */
66989 +typedef enum {
66990 +    WMI_FRAME_BEACON        =   0,
66991 +    WMI_FRAME_PROBE_REQ,
66992 +    WMI_FRAME_PROBE_RESP,
66993 +    WMI_FRAME_ASSOC_REQ,
66994 +    WMI_FRAME_ASSOC_RESP,
66995 +    WMI_NUM_MGMT_FRAME
66996 +} WMI_MGMT_FRAME_TYPE;
66997 +
66998 +/*
66999 + * Connect Command
67000 + */
67001 +typedef enum {
67002 +    INFRA_NETWORK       = 0x01,
67003 +    ADHOC_NETWORK       = 0x02,
67004 +    ADHOC_CREATOR       = 0x04,
67005 +} NETWORK_TYPE;
67006 +
67007 +typedef enum {
67008 +    OPEN_AUTH           = 0x01,
67009 +    SHARED_AUTH         = 0x02,
67010 +    LEAP_AUTH           = 0x04,  /* different from IEEE_AUTH_MODE definitions */
67011 +} DOT11_AUTH_MODE;
67012 +
67013 +typedef enum {
67014 +    NONE_AUTH           = 0x01,
67015 +    WPA_AUTH            = 0x02,
67016 +    WPA_PSK_AUTH        = 0x03,
67017 +    WPA2_AUTH           = 0x04,
67018 +    WPA2_PSK_AUTH       = 0x05,
67019 +    WPA_AUTH_CCKM       = 0x06,
67020 +    WPA2_AUTH_CCKM      = 0x07,
67021 +} AUTH_MODE;
67022 +
67023 +typedef enum {
67024 +    NONE_CRYPT          = 0x01,
67025 +    WEP_CRYPT           = 0x02,
67026 +    TKIP_CRYPT          = 0x03,
67027 +    AES_CRYPT           = 0x04,
67028 +} CRYPTO_TYPE;
67029 +
67030 +#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT
67031 +#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1)
67032 +
67033 +#define WMI_MIN_KEY_INDEX   0
67034 +#define WMI_MAX_KEY_INDEX   3
67035 +
67036 +#define WMI_MAX_KEY_LEN     32
67037 +
67038 +#define WMI_MAX_SSID_LEN    32
67039 +
67040 +typedef enum {
67041 +    CONNECT_ASSOC_POLICY_USER = 0x0001,
67042 +    CONNECT_SEND_REASSOC = 0x0002,
67043 +    CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004,
67044 +    CONNECT_PROFILE_MATCH_DONE = 0x0008,
67045 +    CONNECT_IGNORE_AAC_BEACON = 0x0010,
67046 +    CONNECT_CSA_FOLLOW_BSS = 0x0020,
67047 +} WMI_CONNECT_CTRL_FLAGS_BITS;
67048 +
67049 +#define DEFAULT_CONNECT_CTRL_FLAGS         (CONNECT_CSA_FOLLOW_BSS)
67050 +
67051 +typedef PREPACK struct {
67052 +    A_UINT8     networkType;
67053 +    A_UINT8     dot11AuthMode;
67054 +    A_UINT8     authMode;
67055 +    A_UINT8     pairwiseCryptoType;
67056 +    A_UINT8     pairwiseCryptoLen;
67057 +    A_UINT8     groupCryptoType;
67058 +    A_UINT8     groupCryptoLen;
67059 +    A_UINT8     ssidLength;
67060 +    A_UCHAR     ssid[WMI_MAX_SSID_LEN];
67061 +    A_UINT16    channel;
67062 +    A_UINT8     bssid[ATH_MAC_LEN];
67063 +    A_UINT32    ctrl_flags;
67064 +} POSTPACK WMI_CONNECT_CMD;
67065 +
67066 +/*
67067 + * WMI_RECONNECT_CMDID
67068 + */
67069 +typedef PREPACK struct {
67070 +    A_UINT16    channel;                    /* hint */
67071 +    A_UINT8     bssid[ATH_MAC_LEN];         /* mandatory if set */
67072 +} POSTPACK WMI_RECONNECT_CMD;
67073 +
67074 +/*
67075 + * WMI_ADD_CIPHER_KEY_CMDID
67076 + */
67077 +typedef enum {
67078 +    PAIRWISE_USAGE      = 0x00,
67079 +    GROUP_USAGE         = 0x01,
67080 +    TX_USAGE            = 0x02,     /* default Tx Key - Static WEP only */
67081 +} KEY_USAGE;
67082 +
67083 +/*
67084 + * Bit Flag
67085 + * Bit 0 - Initialise TSC - default is Initialize
67086 + */
67087 +#define KEY_OP_INIT_TSC       0x01
67088 +#define KEY_OP_INIT_RSC       0x02
67089 +
67090 +#define KEY_OP_INIT_VAL     0x03     /* Default Initialise the TSC & RSC */
67091 +#define KEY_OP_VALID_MASK   0x03
67092 +
67093 +typedef PREPACK struct {
67094 +    A_UINT8     keyIndex;
67095 +    A_UINT8     keyType;
67096 +    A_UINT8     keyUsage;           /* KEY_USAGE */
67097 +    A_UINT8     keyLength;
67098 +    A_UINT8     keyRSC[8];          /* key replay sequence counter */
67099 +    A_UINT8     key[WMI_MAX_KEY_LEN];
67100 +    A_UINT8     key_op_ctrl;       /* Additional Key Control information */
67101 +} POSTPACK WMI_ADD_CIPHER_KEY_CMD;
67102 +
67103 +/*
67104 + * WMI_DELETE_CIPHER_KEY_CMDID
67105 + */
67106 +typedef PREPACK struct {
67107 +    A_UINT8     keyIndex;
67108 +} POSTPACK WMI_DELETE_CIPHER_KEY_CMD;
67109 +
67110 +#define WMI_KRK_LEN     16
67111 +/*
67112 + * WMI_ADD_KRK_CMDID
67113 + */
67114 +typedef PREPACK struct {
67115 +    A_UINT8     krk[WMI_KRK_LEN];
67116 +} POSTPACK WMI_ADD_KRK_CMD;
67117 +
67118 +/*
67119 + * WMI_SET_TKIP_COUNTERMEASURES_CMDID
67120 + */
67121 +typedef enum {
67122 +    WMI_TKIP_CM_DISABLE = 0x0,
67123 +    WMI_TKIP_CM_ENABLE  = 0x1,
67124 +} WMI_TKIP_CM_CONTROL;
67125 +
67126 +typedef PREPACK struct {
67127 +    A_UINT8  cm_en;                     /* WMI_TKIP_CM_CONTROL */
67128 +} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD;
67129 +
67130 +/*
67131 + * WMI_SET_PMKID_CMDID
67132 + */
67133 +
67134 +#define WMI_PMKID_LEN 16
67135 +
67136 +typedef enum {
67137 +   PMKID_DISABLE = 0,
67138 +   PMKID_ENABLE  = 1,
67139 +} PMKID_ENABLE_FLG;
67140 +
67141 +typedef PREPACK struct {
67142 +    A_UINT8     bssid[ATH_MAC_LEN];
67143 +    A_UINT8     enable;                 /* PMKID_ENABLE_FLG */
67144 +    A_UINT8     pmkid[WMI_PMKID_LEN];
67145 +} POSTPACK WMI_SET_PMKID_CMD;
67146 +
67147 +/*
67148 + * WMI_START_SCAN_CMD
67149 + */
67150 +typedef enum {
67151 +    WMI_LONG_SCAN  = 0,
67152 +    WMI_SHORT_SCAN = 1,
67153 +} WMI_SCAN_TYPE;
67154 +
67155 +typedef PREPACK struct {
67156 +    A_BOOL   forceFgScan;
67157 +    A_BOOL   isLegacy;        /* For Legacy Cisco AP compatibility */
67158 +    A_UINT32 homeDwellTime;   /* Maximum duration in the home channel(milliseconds) */
67159 +    A_UINT32 forceScanInterval;    /* Time interval between scans (milliseconds)*/
67160 +    A_UINT8  scanType;           /* WMI_SCAN_TYPE */
67161 +} POSTPACK WMI_START_SCAN_CMD;
67162 +
67163 +/*
67164 + * WMI_SET_SCAN_PARAMS_CMDID
67165 + */
67166 +#define WMI_SHORTSCANRATIO_DEFAULT      3
67167 +typedef enum {
67168 +    CONNECT_SCAN_CTRL_FLAGS = 0x01,    /* set if can scan in the Connect cmd */
67169 +    SCAN_CONNECTED_CTRL_FLAGS = 0x02,  /* set if scan for the SSID it is */
67170 +                                       /* already connected to */
67171 +    ACTIVE_SCAN_CTRL_FLAGS = 0x04,     /* set if enable active scan */
67172 +    ROAM_SCAN_CTRL_FLAGS = 0x08,       /* set if enable roam scan when bmiss and lowrssi */
67173 +    REPORT_BSSINFO_CTRL_FLAGS = 0x10,   /* set if follows customer BSSINFO reporting rule */
67174 +    ENABLE_AUTO_CTRL_FLAGS = 0x20,      /* if disabled, target doesn't
67175 +                                          scan after a disconnect event  */
67176 +    ENABLE_SCAN_ABORT_EVENT = 0x40      /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */
67177 +
67178 +} WMI_SCAN_CTRL_FLAGS_BITS;
67179 +
67180 +#define CAN_SCAN_IN_CONNECT(flags)      (flags & CONNECT_SCAN_CTRL_FLAGS)
67181 +#define CAN_SCAN_CONNECTED(flags)       (flags & SCAN_CONNECTED_CTRL_FLAGS)
67182 +#define ENABLE_ACTIVE_SCAN(flags)       (flags & ACTIVE_SCAN_CTRL_FLAGS)
67183 +#define ENABLE_ROAM_SCAN(flags)         (flags & ROAM_SCAN_CTRL_FLAGS)
67184 +#define CONFIG_REPORT_BSSINFO(flags)     (flags & REPORT_BSSINFO_CTRL_FLAGS)
67185 +#define IS_AUTO_SCAN_ENABLED(flags)      (flags & ENABLE_AUTO_CTRL_FLAGS)
67186 +#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT)
67187 +
67188 +#define DEFAULT_SCAN_CTRL_FLAGS         (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS)
67189 +
67190 +
67191 +typedef PREPACK struct {
67192 +    A_UINT16    fg_start_period;        /* seconds */
67193 +    A_UINT16    fg_end_period;          /* seconds */
67194 +    A_UINT16    bg_period;              /* seconds */
67195 +    A_UINT16    maxact_chdwell_time;    /* msec */
67196 +    A_UINT16    pas_chdwell_time;       /* msec */
67197 +    A_UINT8     shortScanRatio;         /* how many shorts scan for one long */
67198 +    A_UINT8     scanCtrlFlags;
67199 +    A_UINT16    minact_chdwell_time;    /* msec */
67200 +    A_UINT32    max_dfsch_act_time;  /* msecs */
67201 +} POSTPACK WMI_SCAN_PARAMS_CMD;
67202 +
67203 +/*
67204 + * WMI_SET_BSS_FILTER_CMDID
67205 + */
67206 +typedef enum {
67207 +    NONE_BSS_FILTER = 0x0,              /* no beacons forwarded */
67208 +    ALL_BSS_FILTER,                     /* all beacons forwarded */
67209 +    PROFILE_FILTER,                     /* only beacons matching profile */
67210 +    ALL_BUT_PROFILE_FILTER,             /* all but beacons matching profile */
67211 +    CURRENT_BSS_FILTER,                 /* only beacons matching current BSS */
67212 +    ALL_BUT_BSS_FILTER,                 /* all but beacons matching BSS */
67213 +    PROBED_SSID_FILTER,                 /* beacons matching probed ssid */
67214 +    LAST_BSS_FILTER,                    /* marker only */
67215 +} WMI_BSS_FILTER;
67216 +
67217 +typedef PREPACK struct {
67218 +    A_UINT8    bssFilter;                      /* see WMI_BSS_FILTER */
67219 +    A_UINT32   ieMask;
67220 +} POSTPACK WMI_BSS_FILTER_CMD;
67221 +
67222 +/*
67223 + * WMI_SET_PROBED_SSID_CMDID
67224 + */
67225 +#define MAX_PROBED_SSID_INDEX   5
67226 +
67227 +typedef enum {
67228 +    DISABLE_SSID_FLAG  = 0,                  /* disables entry */
67229 +    SPECIFIC_SSID_FLAG = 0x01,               /* probes specified ssid */
67230 +    ANY_SSID_FLAG      = 0x02,               /* probes for any ssid */
67231 +} WMI_SSID_FLAG;
67232 +
67233 +typedef PREPACK struct {
67234 +    A_UINT8     entryIndex;                     /* 0 to MAX_PROBED_SSID_INDEX */
67235 +    A_UINT8     flag;                           /* WMI_SSID_FLG */
67236 +    A_UINT8     ssidLength;
67237 +    A_UINT8     ssid[32];
67238 +} POSTPACK WMI_PROBED_SSID_CMD;
67239 +
67240 +/*
67241 + * WMI_SET_LISTEN_INT_CMDID
67242 + * The Listen interval is between 15 and 3000 TUs
67243 + */
67244 +#define MIN_LISTEN_INTERVAL 15
67245 +#define MAX_LISTEN_INTERVAL 5000
67246 +#define MIN_LISTEN_BEACONS 1
67247 +#define MAX_LISTEN_BEACONS 50
67248 +
67249 +typedef PREPACK struct {
67250 +    A_UINT16     listenInterval;
67251 +    A_UINT16     numBeacons;
67252 +} POSTPACK WMI_LISTEN_INT_CMD;
67253 +
67254 +/*
67255 + * WMI_SET_BEACON_INT_CMDID
67256 + */
67257 +typedef PREPACK struct {
67258 +    A_UINT16     beaconInterval;
67259 +} POSTPACK WMI_BEACON_INT_CMD;
67260 +
67261 +/*
67262 + * WMI_SET_BMISS_TIME_CMDID
67263 + * valid values are between 1000 and 5000 TUs
67264 + */
67265 +
67266 +#define MIN_BMISS_TIME     1000
67267 +#define MAX_BMISS_TIME     5000
67268 +#define MIN_BMISS_BEACONS  1
67269 +#define MAX_BMISS_BEACONS  50
67270 +
67271 +typedef PREPACK struct {
67272 +    A_UINT16     bmissTime;
67273 +    A_UINT16     numBeacons;
67274 +} POSTPACK WMI_BMISS_TIME_CMD;
67275 +
67276 +/*
67277 + * WMI_SET_POWER_MODE_CMDID
67278 + */
67279 +typedef enum {
67280 +    REC_POWER = 0x01,
67281 +    MAX_PERF_POWER,
67282 +} WMI_POWER_MODE;
67283 +
67284 +typedef PREPACK struct {
67285 +    A_UINT8     powerMode;      /* WMI_POWER_MODE */
67286 +} POSTPACK WMI_POWER_MODE_CMD;
67287 +
67288 +/*
67289 + * WMI_SET_POWER_PARAMS_CMDID
67290 + */
67291 +typedef enum {
67292 +    IGNORE_DTIM = 0x01,
67293 +    NORMAL_DTIM = 0x02,
67294 +    STICK_DTIM  = 0x03,
67295 +} WMI_DTIM_POLICY;
67296 +
67297 +typedef PREPACK struct {
67298 +    A_UINT16    idle_period;             /* msec */
67299 +    A_UINT16    pspoll_number;
67300 +    A_UINT16    dtim_policy;
67301 +} POSTPACK WMI_POWER_PARAMS_CMD;
67302 +
67303 +typedef PREPACK struct {
67304 +    A_UINT8    power_saving;
67305 +    A_UINT8    ttl; /* number of beacon periods */
67306 +    A_UINT16   atim_windows;          /* msec */
67307 +    A_UINT16   timeout_value;         /* msec */
67308 +} POSTPACK WMI_IBSS_PM_CAPS_CMD;
67309 +
67310 +/*
67311 + * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID
67312 + */
67313 +typedef enum {
67314 +    IGNORE_TIM_ALL_QUEUES_APSD = 0,
67315 +    PROCESS_TIM_ALL_QUEUES_APSD = 1,
67316 +    IGNORE_TIM_SIMULATED_APSD = 2,
67317 +    PROCESS_TIM_SIMULATED_APSD = 3,
67318 +} APSD_TIM_POLICY;
67319 +
67320 +typedef PREPACK struct {
67321 +    A_UINT16    psPollTimeout;          /* msec */
67322 +    A_UINT16    triggerTimeout;         /* msec */
67323 +    A_UINT32    apsdTimPolicy;      /* TIM behavior with  ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */
67324 +    A_UINT32    simulatedAPSDTimPolicy;      /* TIM behavior with  simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */
67325 +} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD;
67326 +
67327 +/*
67328 + * WMI_SET_VOICE_PKT_SIZE_CMDID
67329 + */
67330 +typedef PREPACK struct {
67331 +    A_UINT16    voicePktSize;
67332 +} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD;
67333 +
67334 +/*
67335 + * WMI_SET_MAX_SP_LEN_CMDID
67336 + */
67337 +typedef enum {
67338 +    DELIVER_ALL_PKT = 0x0,
67339 +    DELIVER_2_PKT = 0x1,
67340 +    DELIVER_4_PKT = 0x2,
67341 +    DELIVER_6_PKT = 0x3,
67342 +} APSD_SP_LEN_TYPE;
67343 +
67344 +typedef PREPACK struct {
67345 +    A_UINT8    maxSPLen;
67346 +} POSTPACK WMI_SET_MAX_SP_LEN_CMD;
67347 +
67348 +/*
67349 + * WMI_SET_DISC_TIMEOUT_CMDID
67350 + */
67351 +typedef PREPACK struct {
67352 +    A_UINT8     disconnectTimeout;          /* seconds */
67353 +} POSTPACK WMI_DISC_TIMEOUT_CMD;
67354 +
67355 +typedef enum {
67356 +    UPLINK_TRAFFIC = 0,
67357 +    DNLINK_TRAFFIC = 1,
67358 +    BIDIR_TRAFFIC = 2,
67359 +} DIR_TYPE;
67360 +
67361 +typedef enum {
67362 +    DISABLE_FOR_THIS_AC = 0,
67363 +    ENABLE_FOR_THIS_AC  = 1,
67364 +    ENABLE_FOR_ALL_AC   = 2,
67365 +} VOICEPS_CAP_TYPE;
67366 +
67367 +typedef enum {
67368 +    TRAFFIC_TYPE_APERIODIC = 0,
67369 +    TRAFFIC_TYPE_PERIODIC = 1,
67370 +}TRAFFIC_TYPE;
67371 +
67372 +/*
67373 + * WMI_CREATE_PSTREAM_CMDID
67374 + */
67375 +typedef PREPACK struct {
67376 +    A_UINT32        minServiceInt;           /* in milli-sec */
67377 +    A_UINT32        maxServiceInt;           /* in milli-sec */
67378 +    A_UINT32        inactivityInt;           /* in milli-sec */
67379 +    A_UINT32        suspensionInt;           /* in milli-sec */
67380 +    A_UINT32        serviceStartTime;
67381 +    A_UINT32        minDataRate;             /* in bps */
67382 +    A_UINT32        meanDataRate;            /* in bps */
67383 +    A_UINT32        peakDataRate;            /* in bps */
67384 +    A_UINT32        maxBurstSize;
67385 +    A_UINT32        delayBound;
67386 +    A_UINT32        minPhyRate;              /* in bps */
67387 +    A_UINT32        sba;
67388 +    A_UINT32        mediumTime;
67389 +    A_UINT16        nominalMSDU;             /* in octects */
67390 +    A_UINT16        maxMSDU;                 /* in octects */
67391 +    A_UINT8         trafficClass;
67392 +    A_UINT8         trafficType;             /* TRAFFIC_TYPE */
67393 +    A_UINT8         trafficDirection;        /* TRAFFIC_DIR */
67394 +    A_UINT8         voicePSCapability;       /* VOICEPS_CAP_TYPE */
67395 +    A_UINT8         tsid;
67396 +    A_UINT8         userPriority;            /* 802.1D user priority */
67397 +} POSTPACK WMI_CREATE_PSTREAM_CMD;
67398 +
67399 +/*
67400 + * WMI_DELETE_PSTREAM_CMDID
67401 + */
67402 +typedef PREPACK struct {
67403 +    A_UINT8     trafficClass;
67404 +    A_UINT8     tsid;
67405 +} POSTPACK WMI_DELETE_PSTREAM_CMD;
67406 +
67407 +/*
67408 + * WMI_SET_CHANNEL_PARAMS_CMDID
67409 + */
67410 +typedef enum {
67411 +    WMI_11A_MODE  = 0x1,
67412 +    WMI_11G_MODE  = 0x2,
67413 +    WMI_11AG_MODE = 0x3,
67414 +    WMI_11B_MODE  = 0x4,
67415 +    WMI_11GONLY_MODE = 0x5,
67416 +} WMI_PHY_MODE;
67417 +
67418 +#define WMI_MAX_CHANNELS        32
67419 +
67420 +typedef PREPACK struct {
67421 +    A_UINT8     reserved1;
67422 +    A_UINT8     scanParam;              /* set if enable scan */
67423 +    A_UINT8     phyMode;                /* see WMI_PHY_MODE */
67424 +    A_UINT8     numChannels;            /* how many channels follow */
67425 +    A_UINT16    channelList[1];         /* channels in Mhz */
67426 +} POSTPACK WMI_CHANNEL_PARAMS_CMD;
67427 +
67428 +
67429 +/*
67430 + *  WMI_RSSI_THRESHOLD_PARAMS_CMDID
67431 + *  Setting the polltime to 0 would disable polling.
67432 + *  Threshold values are in the ascending order, and should agree to:
67433 + *  (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal
67434 + *      < highThreshold_upperVal)
67435 + */
67436 +
67437 +typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{
67438 +    A_UINT32    pollTime;               /* Polling time as a factor of LI */
67439 +    A_INT16     thresholdAbove1_Val;          /* lowest of upper */
67440 +    A_INT16     thresholdAbove2_Val;
67441 +    A_INT16     thresholdAbove3_Val;
67442 +    A_INT16     thresholdAbove4_Val;
67443 +    A_INT16     thresholdAbove5_Val;
67444 +    A_INT16     thresholdAbove6_Val;          /* highest of upper */
67445 +    A_INT16     thresholdBelow1_Val;         /* lowest of bellow */
67446 +    A_INT16     thresholdBelow2_Val;
67447 +    A_INT16     thresholdBelow3_Val;
67448 +    A_INT16     thresholdBelow4_Val;
67449 +    A_INT16     thresholdBelow5_Val;
67450 +    A_INT16     thresholdBelow6_Val;         /* highest of bellow */
67451 +    A_UINT8     weight;                  /* "alpha" */
67452 +    A_UINT8     reserved[3];
67453 +} POSTPACK  WMI_RSSI_THRESHOLD_PARAMS_CMD;
67454 +
67455 +/*
67456 + *  WMI_SNR_THRESHOLD_PARAMS_CMDID
67457 + *  Setting the polltime to 0 would disable polling.
67458 + */
67459 +
67460 +typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{
67461 +    A_UINT32    pollTime;               /* Polling time as a factor of LI */
67462 +    A_UINT8     weight;                  /* "alpha" */
67463 +    A_UINT8     thresholdAbove1_Val;      /* lowest of uppper*/
67464 +    A_UINT8     thresholdAbove2_Val;
67465 +    A_UINT8     thresholdAbove3_Val;
67466 +    A_UINT8     thresholdAbove4_Val;      /* highest of upper */
67467 +    A_UINT8     thresholdBelow1_Val;     /* lowest of bellow */
67468 +    A_UINT8     thresholdBelow2_Val;
67469 +    A_UINT8     thresholdBelow3_Val;
67470 +    A_UINT8     thresholdBelow4_Val;     /* highest of bellow */
67471 +    A_UINT8     reserved[3];
67472 +} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD;
67473 +
67474 +/*
67475 + *  WMI_LQ_THRESHOLD_PARAMS_CMDID
67476 + */
67477 +typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS {
67478 +    A_UINT8     enable;
67479 +    A_UINT8     thresholdAbove1_Val;
67480 +    A_UINT8     thresholdAbove2_Val;
67481 +    A_UINT8     thresholdAbove3_Val;
67482 +    A_UINT8     thresholdAbove4_Val;
67483 +    A_UINT8     thresholdBelow1_Val;
67484 +    A_UINT8     thresholdBelow2_Val;
67485 +    A_UINT8     thresholdBelow3_Val;
67486 +    A_UINT8     thresholdBelow4_Val;
67487 +    A_UINT8     reserved[3];
67488 +} POSTPACK  WMI_LQ_THRESHOLD_PARAMS_CMD;
67489 +
67490 +typedef enum {
67491 +    WMI_LPREAMBLE_DISABLED = 0,
67492 +    WMI_LPREAMBLE_ENABLED
67493 +} WMI_LPREAMBLE_STATUS;
67494 +
67495 +typedef PREPACK struct {
67496 +    A_UINT8     status;
67497 +}POSTPACK WMI_SET_LPREAMBLE_CMD;
67498 +
67499 +typedef PREPACK struct {
67500 +    A_UINT16    threshold;
67501 +}POSTPACK WMI_SET_RTS_CMD;
67502 +
67503 +/*
67504 + *  WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
67505 + *  Sets the error reporting event bitmask in target. Target clears it
67506 + *  upon an error. Subsequent errors are counted, but not reported
67507 + *  via event, unless the bitmask is set again.
67508 + */
67509 +typedef PREPACK struct {
67510 +    A_UINT32    bitmask;
67511 +} POSTPACK  WMI_TARGET_ERROR_REPORT_BITMASK;
67512 +
67513 +/*
67514 + * WMI_SET_TX_PWR_CMDID
67515 + */
67516 +typedef PREPACK struct {
67517 +    A_UINT8     dbM;                  /* in dbM units */
67518 +} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY;
67519 +
67520 +/*
67521 + * WMI_SET_ASSOC_INFO_CMDID
67522 + *
67523 + * A maximum of 2 private IEs can be sent in the [Re]Assoc request.
67524 + * A 3rd one, the CCX version IE can also be set from the host.
67525 + */
67526 +#define WMI_MAX_ASSOC_INFO_TYPE    2
67527 +#define WMI_CCX_VER_IE             2 /* ieType to set CCX Version IE */
67528 +
67529 +#define WMI_MAX_ASSOC_INFO_LEN     240
67530 +
67531 +typedef PREPACK struct {
67532 +    A_UINT8     ieType;
67533 +    A_UINT8     bufferSize;
67534 +    A_UINT8     assocInfo[1];       /* up to WMI_MAX_ASSOC_INFO_LEN */
67535 +} POSTPACK WMI_SET_ASSOC_INFO_CMD;
67536 +
67537 +
67538 +/*
67539 + * WMI_GET_TX_PWR_CMDID does not take any parameters
67540 + */
67541 +
67542 +/*
67543 + * WMI_ADD_BAD_AP_CMDID
67544 + */
67545 +#define WMI_MAX_BAD_AP_INDEX      1
67546 +
67547 +typedef PREPACK struct {
67548 +    A_UINT8     badApIndex;         /* 0 to WMI_MAX_BAD_AP_INDEX */
67549 +    A_UINT8     bssid[ATH_MAC_LEN];
67550 +} POSTPACK WMI_ADD_BAD_AP_CMD;
67551 +
67552 +/*
67553 + * WMI_DELETE_BAD_AP_CMDID
67554 + */
67555 +typedef PREPACK struct {
67556 +    A_UINT8     badApIndex;         /* 0 to WMI_MAX_BAD_AP_INDEX */
67557 +} POSTPACK WMI_DELETE_BAD_AP_CMD;
67558 +
67559 +/*
67560 + * WMI_SET_ACCESS_PARAMS_CMDID
67561 + */
67562 +#define WMI_DEFAULT_TXOP_ACPARAM    0       /* implies one MSDU */
67563 +#define WMI_DEFAULT_ECWMIN_ACPARAM  4       /* corresponds to CWmin of 15 */
67564 +#define WMI_DEFAULT_ECWMAX_ACPARAM  10      /* corresponds to CWmax of 1023 */
67565 +#define WMI_MAX_CW_ACPARAM          15      /* maximum eCWmin or eCWmax */
67566 +#define WMI_DEFAULT_AIFSN_ACPARAM   2
67567 +#define WMI_MAX_AIFSN_ACPARAM       15
67568 +typedef PREPACK struct {
67569 +    A_UINT16 txop;                      /* in units of 32 usec */
67570 +    A_UINT8  eCWmin;
67571 +    A_UINT8  eCWmax;
67572 +    A_UINT8  aifsn;
67573 +} POSTPACK WMI_SET_ACCESS_PARAMS_CMD;
67574 +
67575 +
67576 +/*
67577 + * WMI_SET_RETRY_LIMITS_CMDID
67578 + *
67579 + * This command is used to customize the number of retries the
67580 + * wlan device will perform on a given frame.
67581 + */
67582 +#define WMI_MIN_RETRIES 2
67583 +#define WMI_MAX_RETRIES 13
67584 +typedef enum {
67585 +    MGMT_FRAMETYPE    = 0,
67586 +    CONTROL_FRAMETYPE = 1,
67587 +    DATA_FRAMETYPE    = 2
67588 +} WMI_FRAMETYPE;
67589 +
67590 +typedef PREPACK struct {
67591 +    A_UINT8 frameType;                      /* WMI_FRAMETYPE */
67592 +    A_UINT8 trafficClass;                   /* applies only to DATA_FRAMETYPE */
67593 +    A_UINT8 maxRetries;
67594 +    A_UINT8 enableNotify;
67595 +} POSTPACK WMI_SET_RETRY_LIMITS_CMD;
67596 +
67597 +/*
67598 + * WMI_SET_ROAM_CTRL_CMDID
67599 + *
67600 + * This command is used to influence the Roaming behaviour
67601 + * Set the host biases of the BSSs before setting the roam mode as bias
67602 + * based.
67603 + */
67604 +
67605 +/*
67606 + * Different types of Roam Control
67607 + */
67608 +
67609 +typedef enum {
67610 +        WMI_FORCE_ROAM          = 1,      /* Roam to the specified BSSID */
67611 +        WMI_SET_ROAM_MODE       = 2,      /* default ,progd bias, no roam */
67612 +        WMI_SET_HOST_BIAS       = 3,     /* Set the Host Bias */
67613 +        WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */
67614 +} WMI_ROAM_CTRL_TYPE;
67615 +
67616 +#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM
67617 +#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS
67618 +
67619 +/*
67620 + * ROAM MODES
67621 + */
67622 +
67623 +typedef enum {
67624 +        WMI_DEFAULT_ROAM_MODE   = 1,  /* RSSI based ROAM */
67625 +        WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */
67626 +        WMI_LOCK_BSS_MODE  = 3  /* Lock to the Current BSS - no Roam */
67627 +} WMI_ROAM_MODE;
67628 +
67629 +/*
67630 + * BSS HOST BIAS INFO
67631 + */
67632 +
67633 +typedef PREPACK struct {
67634 +        A_UINT8 bssid[ATH_MAC_LEN];
67635 +        A_INT8  bias;
67636 +} POSTPACK WMI_BSS_BIAS;
67637 +
67638 +typedef PREPACK struct {
67639 +        A_UINT8 numBss;
67640 +        WMI_BSS_BIAS bssBias[1];
67641 +} POSTPACK WMI_BSS_BIAS_INFO;
67642 +
67643 +typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS {
67644 +        A_UINT16 lowrssi_scan_period;
67645 +        A_INT16  lowrssi_scan_threshold;
67646 +        A_INT16  lowrssi_roam_threshold;
67647 +        A_UINT8  roam_rssi_floor;
67648 +        A_UINT8  reserved[1];              /* For alignment */
67649 +} POSTPACK WMI_LOWRSSI_SCAN_PARAMS;
67650 +
67651 +typedef PREPACK struct {
67652 +    PREPACK union {
67653 +        A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */
67654 +        A_UINT8 roamMode;           /* WMI_SET_ROAM_MODE  */
67655 +        WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */
67656 +        WMI_LOWRSSI_SCAN_PARAMS lrScanParams;
67657 +    } POSTPACK info;
67658 +    A_UINT8   roamCtrlType ;
67659 +} POSTPACK WMI_SET_ROAM_CTRL_CMD;
67660 +
67661 +/*
67662 + * WMI_ENABLE_RM_CMDID
67663 + */
67664 +typedef PREPACK struct {
67665 +        A_BOOL enable_radio_measurements;
67666 +} POSTPACK WMI_ENABLE_RM_CMD;
67667 +
67668 +/*
67669 + * WMI_SET_MAX_OFFHOME_DURATION_CMDID
67670 + */
67671 +typedef PREPACK struct {
67672 +        A_UINT8 max_offhome_duration;
67673 +} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD;
67674 +
67675 +typedef PREPACK struct {
67676 +    A_UINT32 frequency;
67677 +    A_UINT8  threshold;
67678 +} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD;
67679 +
67680 +typedef enum {
67681 +    BT_STREAM_UNDEF = 0,
67682 +    BT_STREAM_SCO,             /* SCO stream */
67683 +    BT_STREAM_A2DP,            /* A2DP stream */
67684 +    BT_STREAM_MAX
67685 +} BT_STREAM_TYPE;
67686 +
67687 +typedef enum {
67688 +    BT_PARAM_SCO = 1,         /* SCO stream parameters */
67689 +    BT_PARAM_A2DP,            /* A2DP stream parameters */
67690 +    BT_PARAM_MISC,            /* miscellaneous parameters */
67691 +    BT_PARAM_REGS,            /* co-existence register parameters */
67692 +    BT_PARAM_MAX
67693 +} BT_PARAM_TYPE;
67694 +
67695 +typedef enum {
67696 +    BT_STATUS_UNDEF = 0,
67697 +    BT_STATUS_START,
67698 +    BT_STATUS_STOP,
67699 +    BT_STATUS_RESUME,
67700 +    BT_STATUS_SUSPEND,
67701 +    BT_STATUS_MAX
67702 +} BT_STREAM_STATUS;
67703 +
67704 +typedef PREPACK struct {
67705 +    A_UINT8 streamType;
67706 +    A_UINT8 status;
67707 +} POSTPACK WMI_SET_BT_STATUS_CMD;
67708 +
67709 +typedef PREPACK struct {
67710 +    A_UINT8 noSCOPkts;
67711 +    A_UINT8 pspollTimeout;
67712 +    A_UINT8 stompbt;
67713 +} POSTPACK BT_PARAMS_SCO;
67714 +
67715 +typedef PREPACK struct {
67716 +    A_UINT32 period;
67717 +    A_UINT32 dutycycle;
67718 +    A_UINT8  stompbt;
67719 +} POSTPACK BT_PARAMS_A2DP;
67720 +
67721 +typedef PREPACK struct {
67722 +    A_UINT32 mode;
67723 +    A_UINT32 scoWghts;
67724 +    A_UINT32 a2dpWghts;
67725 +    A_UINT32 genWghts;
67726 +    A_UINT32 mode2;
67727 +    A_UINT8  setVal;
67728 +} POSTPACK BT_COEX_REGS;
67729 +
67730 +typedef enum {
67731 +    WLAN_PROTECT_POLICY = 1,
67732 +    WLAN_COEX_CTRL_FLAGS
67733 +} BT_PARAMS_MISC_TYPE;
67734 +
67735 +typedef enum {
67736 +    WLAN_PROTECT_PER_STREAM = 0x01,   /* default */
67737 +    WLAN_PROTECT_ANY_TX = 0x02
67738 +} WLAN_PROTECT_FLAGS;
67739 +
67740 +
67741 +#define WLAN_DISABLE_COEX_IN_DISCONNECT   0x01 /* default */
67742 +#define WLAN_KEEP_COEX_IN_DISCONNECT      0x02
67743 +#define WLAN_STOMPBT_IN_DISCONNECT        0x04
67744 +
67745 +#define WLAN_DISABLE_COEX_IN_ROAM         0x10 /* default */
67746 +#define WLAN_KEEP_COEX_IN_ROAM            0x20
67747 +#define WLAN_STOMPBT_IN_ROAM              0x40
67748 +
67749 +#define WLAN_DISABLE_COEX_IN_SCAN        0x100 /* default */
67750 +#define WLAN_KEEP_COEX_IN_SCAN           0x200
67751 +#define WLAN_STOMPBT_IN_SCAN             0x400
67752 +
67753 +#define WLAN_DISABLE_COEX_BT_OFF        0x1000 /* default */
67754 +#define WLAN_KEEP_COEX_BT_OFF           0x2000
67755 +#define WLAN_STOMPBT_BT_OFF             0x4000
67756 +
67757 +typedef PREPACK struct {
67758 +    A_UINT32 period;
67759 +    A_UINT32 dutycycle;
67760 +    A_UINT8  stompbt;
67761 +    A_UINT8  policy;
67762 +} POSTPACK WLAN_PROTECT_POLICY_TYPE;
67763 +
67764 +typedef PREPACK struct {
67765 +    PREPACK union {
67766 +        WLAN_PROTECT_POLICY_TYPE protectParams;
67767 +        A_UINT16 wlanCtrlFlags;
67768 +    } POSTPACK info;
67769 +    A_UINT8 paramType;
67770 +} POSTPACK BT_PARAMS_MISC;
67771 +
67772 +typedef PREPACK struct {
67773 +    PREPACK union {
67774 +        BT_PARAMS_SCO scoParams;
67775 +        BT_PARAMS_A2DP a2dpParams;
67776 +        BT_PARAMS_MISC miscParams;
67777 +        BT_COEX_REGS regs;
67778 +    } POSTPACK info;
67779 +    A_UINT8 paramType;
67780 +} POSTPACK WMI_SET_BT_PARAMS_CMD;
67781 +
67782 +/*
67783 + * Command Replies
67784 + */
67785 +
67786 +/*
67787 + * WMI_GET_CHANNEL_LIST_CMDID reply
67788 + */
67789 +typedef PREPACK struct {
67790 +    A_UINT8     reserved1;
67791 +    A_UINT8     numChannels;            /* number of channels in reply */
67792 +    A_UINT16    channelList[1];         /* channel in Mhz */
67793 +} POSTPACK WMI_CHANNEL_LIST_REPLY;
67794 +
67795 +typedef enum {
67796 +    A_SUCCEEDED = A_OK,
67797 +    A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250,
67798 +    A_SUCCEEDED_MODIFY_STREAM=251,
67799 +    A_FAILED_INVALID_STREAM = 252,
67800 +    A_FAILED_MAX_THINSTREAMS = 253,
67801 +    A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254,
67802 +} PSTREAM_REPLY_STATUS;
67803 +
67804 +/*
67805 + * List of Events (target to host)
67806 + */
67807 +typedef enum {
67808 +    WMI_READY_EVENTID           = 0x1001,
67809 +    WMI_CONNECT_EVENTID,
67810 +    WMI_DISCONNECT_EVENTID,
67811 +    WMI_BSSINFO_EVENTID,
67812 +    WMI_CMDERROR_EVENTID,
67813 +    WMI_REGDOMAIN_EVENTID,
67814 +    WMI_PSTREAM_TIMEOUT_EVENTID,
67815 +    WMI_NEIGHBOR_REPORT_EVENTID,
67816 +    WMI_TKIP_MICERR_EVENTID,
67817 +    WMI_SCAN_COMPLETE_EVENTID,
67818 +    WMI_REPORT_STATISTICS_EVENTID,
67819 +    WMI_RSSI_THRESHOLD_EVENTID,
67820 +    WMI_ERROR_REPORT_EVENTID,
67821 +    WMI_OPT_RX_FRAME_EVENTID,
67822 +    WMI_REPORT_ROAM_TBL_EVENTID,
67823 +    WMI_EXTENSION_EVENTID,
67824 +    WMI_CAC_EVENTID,
67825 +    WMI_SNR_THRESHOLD_EVENTID,
67826 +    WMI_LQ_THRESHOLD_EVENTID,
67827 +    WMI_TX_RETRY_ERR_EVENTID,
67828 +    WMI_REPORT_ROAM_DATA_EVENTID,
67829 +    WMI_TEST_EVENTID,
67830 +    WMI_APLIST_EVENTID,
67831 +    WMI_GET_WOW_LIST_EVENTID,
67832 +    WMI_GET_PMKID_LIST_EVENTID
67833 +} WMI_EVENT_ID;
67834 +
67835 +typedef enum {
67836 +    WMI_11A_CAPABILITY   = 1,
67837 +    WMI_11G_CAPABILITY   = 2,
67838 +    WMI_11AG_CAPABILITY  = 3,
67839 +} WMI_PHY_CAPABILITY;
67840 +
67841 +typedef PREPACK struct {
67842 +    A_UINT8     macaddr[ATH_MAC_LEN];
67843 +    A_UINT8     phyCapability;              /* WMI_PHY_CAPABILITY */
67844 +} POSTPACK WMI_READY_EVENT;
67845 +
67846 +/*
67847 + * Connect Event
67848 + */
67849 +typedef PREPACK struct {
67850 +    A_UINT16    channel;
67851 +    A_UINT8     bssid[ATH_MAC_LEN];
67852 +    A_UINT16    listenInterval;
67853 +    A_UINT16    beaconInterval;
67854 +    A_UINT32    networkType;
67855 +    A_UINT8     beaconIeLen;
67856 +    A_UINT8     assocReqLen;
67857 +    A_UINT8     assocRespLen;
67858 +    A_UINT8     assocInfo[1];
67859 +} POSTPACK WMI_CONNECT_EVENT;
67860 +
67861 +/*
67862 + * Disconnect Event
67863 + */
67864 +typedef enum {
67865 +    NO_NETWORK_AVAIL   = 0x01,
67866 +    LOST_LINK          = 0x02,     /* bmiss */
67867 +    DISCONNECT_CMD     = 0x03,
67868 +    BSS_DISCONNECTED   = 0x04,
67869 +    AUTH_FAILED        = 0x05,
67870 +    ASSOC_FAILED       = 0x06,
67871 +    NO_RESOURCES_AVAIL = 0x07,
67872 +    CSERV_DISCONNECT   = 0x08,
67873 +    INVALID_PROFILE    = 0x0a,
67874 +    DOT11H_CHANNEL_SWITCH = 0x0b,
67875 +} WMI_DISCONNECT_REASON;
67876 +
67877 +typedef PREPACK struct {
67878 +    A_UINT16    protocolReasonStatus;  /* reason code, see 802.11 spec. */
67879 +    A_UINT8     bssid[ATH_MAC_LEN];    /* set if known */
67880 +    A_UINT8     disconnectReason ;      /* see WMI_DISCONNECT_REASON */
67881 +    A_UINT8     assocRespLen;
67882 +    A_UINT8     assocInfo[1];
67883 +} POSTPACK WMI_DISCONNECT_EVENT;
67884 +
67885 +/*
67886 + * BSS Info Event.
67887 + * Mechanism used to inform host of the presence and characteristic of
67888 + * wireless networks present.  Consists of bss info header followed by
67889 + * the beacon or probe-response frame body.  The 802.11 header is not included.
67890 + */
67891 +typedef enum {
67892 +    BEACON_FTYPE = 0x1,
67893 +    PROBERESP_FTYPE,
67894 +    ACTION_MGMT_FTYPE,
67895 +} WMI_BI_FTYPE;
67896 +
67897 +enum {
67898 +    BSS_ELEMID_CHANSWITCH = 0x01,
67899 +    BSS_ELEMID_ATHEROS = 0x02,
67900 +};
67901 +
67902 +typedef PREPACK struct {
67903 +    A_UINT16    channel;
67904 +    A_UINT8     frameType;          /* see WMI_BI_FTYPE */
67905 +    A_UINT8     snr;
67906 +    A_INT16     rssi;
67907 +    A_UINT8     bssid[ATH_MAC_LEN];
67908 +    A_UINT32    ieMask;
67909 +} POSTPACK WMI_BSS_INFO_HDR;
67910 +
67911 +/*
67912 + * Command Error Event
67913 + */
67914 +typedef enum {
67915 +    INVALID_PARAM  = 0x01,
67916 +    ILLEGAL_STATE  = 0x02,
67917 +    INTERNAL_ERROR = 0x03,
67918 +} WMI_ERROR_CODE;
67919 +
67920 +typedef PREPACK struct {
67921 +    A_UINT16    commandId;
67922 +    A_UINT8     errorCode;
67923 +} POSTPACK WMI_CMD_ERROR_EVENT;
67924 +
67925 +/*
67926 + * New Regulatory Domain Event
67927 + */
67928 +typedef PREPACK struct {
67929 +    A_UINT32    regDomain;
67930 +} POSTPACK WMI_REG_DOMAIN_EVENT;
67931 +
67932 +typedef PREPACK struct {
67933 +    A_UINT8     trafficClass;
67934 +} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT;
67935 +
67936 +/*
67937 + * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform
67938 + * the host of BSS's it has found that matches the current profile.
67939 + * It can be used by the host to cache PMKs and/to initiate pre-authentication
67940 + * if the BSS supports it.  The first bssid is always the current associated
67941 + * BSS.
67942 + * The bssid and bssFlags information repeats according to the number
67943 + * or APs reported.
67944 + */
67945 +typedef enum {
67946 +    WMI_DEFAULT_BSS_FLAGS   = 0x00,
67947 +    WMI_PREAUTH_CAPABLE_BSS = 0x01,
67948 +    WMI_PMKID_VALID_BSS     = 0x02,
67949 +} WMI_BSS_FLAGS;
67950 +
67951 +typedef PREPACK struct {
67952 +    A_UINT8     bssid[ATH_MAC_LEN];
67953 +    A_UINT8     bssFlags;            /* see WMI_BSS_FLAGS */
67954 +} POSTPACK WMI_NEIGHBOR_INFO;
67955 +
67956 +typedef PREPACK struct {
67957 +    A_INT8      numberOfAps;
67958 +    WMI_NEIGHBOR_INFO neighbor[1];
67959 +} POSTPACK WMI_NEIGHBOR_REPORT_EVENT;
67960 +
67961 +/*
67962 + * TKIP MIC Error Event
67963 + */
67964 +typedef PREPACK struct {
67965 +    A_UINT8 keyid;
67966 +    A_UINT8 ismcast;
67967 +} POSTPACK WMI_TKIP_MICERR_EVENT;
67968 +
67969 +/*
67970 + * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new)
67971 + */
67972 +typedef PREPACK struct {
67973 +    A_STATUS status;
67974 +} POSTPACK WMI_SCAN_COMPLETE_EVENT;
67975 +
67976 +#define MAX_OPT_DATA_LEN 1400
67977 +
67978 +/*
67979 + * WMI_SET_ADHOC_BSSID_CMDID
67980 + */
67981 +typedef PREPACK struct {
67982 +    A_UINT8     bssid[ATH_MAC_LEN];
67983 +} POSTPACK WMI_SET_ADHOC_BSSID_CMD;
67984 +
67985 +/*
67986 + * WMI_SET_OPT_MODE_CMDID
67987 + */
67988 +typedef enum {
67989 +    SPECIAL_OFF,
67990 +    SPECIAL_ON,
67991 +} OPT_MODE_TYPE;
67992 +
67993 +typedef PREPACK struct {
67994 +    A_UINT8     optMode;
67995 +} POSTPACK WMI_SET_OPT_MODE_CMD;
67996 +
67997 +/*
67998 + * WMI_TX_OPT_FRAME_CMDID
67999 + */
68000 +typedef enum {
68001 +    OPT_PROBE_REQ   = 0x01,
68002 +    OPT_PROBE_RESP  = 0x02,
68003 +    OPT_CPPP_START  = 0x03,
68004 +    OPT_CPPP_STOP   = 0x04,
68005 +} WMI_OPT_FTYPE;
68006 +
68007 +typedef PREPACK struct {
68008 +    A_UINT16    optIEDataLen;
68009 +    A_UINT8     frmType;
68010 +    A_UINT8     dstAddr[ATH_MAC_LEN];
68011 +    A_UINT8     bssid[ATH_MAC_LEN];
68012 +    A_UINT8     reserved;               /* For alignment */
68013 +    A_UINT8     optIEData[1];
68014 +} POSTPACK WMI_OPT_TX_FRAME_CMD;
68015 +
68016 +/*
68017 + * Special frame receive Event.
68018 + * Mechanism used to inform host of the receiption of the special frames.
68019 + * Consists of special frame info header followed by special frame body.
68020 + * The 802.11 header is not included.
68021 + */
68022 +typedef PREPACK struct {
68023 +    A_UINT16    channel;
68024 +    A_UINT8     frameType;          /* see WMI_OPT_FTYPE */
68025 +    A_INT8      snr;
68026 +    A_UINT8     srcAddr[ATH_MAC_LEN];
68027 +    A_UINT8     bssid[ATH_MAC_LEN];
68028 +} POSTPACK WMI_OPT_RX_INFO_HDR;
68029 +
68030 +/*
68031 + * Reporting statistics.
68032 + */
68033 +typedef PREPACK struct {
68034 +    A_UINT32   tx_packets;
68035 +    A_UINT32   tx_bytes;
68036 +    A_UINT32   tx_unicast_pkts;
68037 +    A_UINT32   tx_unicast_bytes;
68038 +    A_UINT32   tx_multicast_pkts;
68039 +    A_UINT32   tx_multicast_bytes;
68040 +    A_UINT32   tx_broadcast_pkts;
68041 +    A_UINT32   tx_broadcast_bytes;
68042 +    A_UINT32   tx_rts_success_cnt;
68043 +    A_UINT32   tx_packet_per_ac[4];
68044 +    A_UINT32   tx_errors_per_ac[4];
68045 +
68046 +    A_UINT32   tx_errors;
68047 +    A_UINT32   tx_failed_cnt;
68048 +    A_UINT32   tx_retry_cnt;
68049 +    A_UINT32   tx_rts_fail_cnt;
68050 +    A_INT32    tx_unicast_rate;
68051 +}POSTPACK tx_stats_t;
68052 +
68053 +typedef PREPACK struct {
68054 +    A_UINT32   rx_packets;
68055 +    A_UINT32   rx_bytes;
68056 +    A_UINT32   rx_unicast_pkts;
68057 +    A_UINT32   rx_unicast_bytes;
68058 +    A_UINT32   rx_multicast_pkts;
68059 +    A_UINT32   rx_multicast_bytes;
68060 +    A_UINT32   rx_broadcast_pkts;
68061 +    A_UINT32   rx_broadcast_bytes;
68062 +    A_UINT32   rx_fragment_pkt;
68063 +
68064 +    A_UINT32   rx_errors;
68065 +    A_UINT32   rx_crcerr;
68066 +    A_UINT32   rx_key_cache_miss;
68067 +    A_UINT32   rx_decrypt_err;
68068 +    A_UINT32   rx_duplicate_frames;
68069 +    A_INT32    rx_unicast_rate;
68070 +}POSTPACK rx_stats_t;
68071 +
68072 +typedef PREPACK struct {
68073 +    A_UINT32   tkip_local_mic_failure;
68074 +    A_UINT32   tkip_counter_measures_invoked;
68075 +    A_UINT32   tkip_replays;
68076 +    A_UINT32   tkip_format_errors;
68077 +    A_UINT32   ccmp_format_errors;
68078 +    A_UINT32   ccmp_replays;
68079 +}POSTPACK tkip_ccmp_stats_t;
68080 +
68081 +typedef PREPACK struct {
68082 +    A_UINT32   power_save_failure_cnt;
68083 +}POSTPACK pm_stats_t;
68084 +
68085 +typedef PREPACK struct {
68086 +    A_UINT32    cs_bmiss_cnt;
68087 +    A_UINT32    cs_lowRssi_cnt;
68088 +    A_UINT16    cs_connect_cnt;
68089 +    A_UINT16    cs_disconnect_cnt;
68090 +    A_INT16     cs_aveBeacon_rssi;
68091 +    A_UINT16    cs_roam_count;
68092 +    A_UINT16    cs_rssi;
68093 +    A_UINT8     cs_snr;
68094 +    A_UINT8     cs_aveBeacon_snr;
68095 +    A_UINT8     cs_lastRoam_msec;
68096 +} POSTPACK cserv_stats_t;
68097 +
68098 +typedef PREPACK struct {
68099 +    tx_stats_t          tx_stats;
68100 +    rx_stats_t          rx_stats;
68101 +    tkip_ccmp_stats_t   tkipCcmpStats;
68102 +}POSTPACK wlan_net_stats_t;
68103 +
68104 +typedef PREPACK struct {
68105 +    A_UINT32    wow_num_pkts_dropped;
68106 +    A_UINT16    wow_num_events_discarded;
68107 +    A_UINT8     wow_num_host_pkt_wakeups;
68108 +    A_UINT8     wow_num_host_event_wakeups;
68109 +} POSTPACK wlan_wow_stats_t;
68110 +
68111 +typedef PREPACK struct {
68112 +    A_UINT32            lqVal;
68113 +    A_INT32             noise_floor_calibation;
68114 +    pm_stats_t          pmStats;
68115 +    wlan_net_stats_t    txrxStats;
68116 +    wlan_wow_stats_t    wowStats;
68117 +    cserv_stats_t       cservStats;
68118 +} POSTPACK WMI_TARGET_STATS;
68119 +
68120 +/*
68121 + * WMI_RSSI_THRESHOLD_EVENTID.
68122 + * Indicate the RSSI events to host. Events are indicated when we breach a
68123 + * thresold value.
68124 + */
68125 +typedef enum{
68126 +    WMI_RSSI_THRESHOLD1_ABOVE = 0,
68127 +    WMI_RSSI_THRESHOLD2_ABOVE,
68128 +    WMI_RSSI_THRESHOLD3_ABOVE,
68129 +    WMI_RSSI_THRESHOLD4_ABOVE,
68130 +    WMI_RSSI_THRESHOLD5_ABOVE,
68131 +    WMI_RSSI_THRESHOLD6_ABOVE,
68132 +    WMI_RSSI_THRESHOLD1_BELOW,
68133 +    WMI_RSSI_THRESHOLD2_BELOW,
68134 +    WMI_RSSI_THRESHOLD3_BELOW,
68135 +    WMI_RSSI_THRESHOLD4_BELOW,
68136 +    WMI_RSSI_THRESHOLD5_BELOW,
68137 +    WMI_RSSI_THRESHOLD6_BELOW
68138 +}WMI_RSSI_THRESHOLD_VAL;
68139 +
68140 +typedef PREPACK struct {
68141 +    A_INT16 rssi;
68142 +    A_UINT8 range;
68143 +}POSTPACK WMI_RSSI_THRESHOLD_EVENT;
68144 +
68145 +/*
68146 + *  WMI_ERROR_REPORT_EVENTID
68147 + */
68148 +typedef enum{
68149 +    WMI_TARGET_PM_ERR_FAIL      = 0x00000001,
68150 +    WMI_TARGET_KEY_NOT_FOUND    = 0x00000002,
68151 +    WMI_TARGET_DECRYPTION_ERR   = 0x00000004,
68152 +    WMI_TARGET_BMISS            = 0x00000008,
68153 +    WMI_PSDISABLE_NODE_JOIN     = 0x00000010,
68154 +    WMI_TARGET_COM_ERR          = 0x00000020,
68155 +    WMI_TARGET_FATAL_ERR        = 0x00000040
68156 +} WMI_TARGET_ERROR_VAL;
68157 +
68158 +typedef PREPACK struct {
68159 +    A_UINT32 errorVal;
68160 +}POSTPACK  WMI_TARGET_ERROR_REPORT_EVENT;
68161 +
68162 +typedef PREPACK struct {
68163 +    A_UINT8 retrys;
68164 +}POSTPACK  WMI_TX_RETRY_ERR_EVENT;
68165 +
68166 +typedef enum{
68167 +    WMI_SNR_THRESHOLD1_ABOVE = 1,
68168 +    WMI_SNR_THRESHOLD1_BELOW,
68169 +    WMI_SNR_THRESHOLD2_ABOVE,
68170 +    WMI_SNR_THRESHOLD2_BELOW,
68171 +    WMI_SNR_THRESHOLD3_ABOVE,
68172 +    WMI_SNR_THRESHOLD3_BELOW,
68173 +    WMI_SNR_THRESHOLD4_ABOVE,
68174 +    WMI_SNR_THRESHOLD4_BELOW
68175 +} WMI_SNR_THRESHOLD_VAL;
68176 +
68177 +typedef PREPACK struct {
68178 +    A_UINT8 range;  /* WMI_SNR_THRESHOLD_VAL */
68179 +    A_UINT8 snr;
68180 +}POSTPACK  WMI_SNR_THRESHOLD_EVENT;
68181 +
68182 +typedef enum{
68183 +    WMI_LQ_THRESHOLD1_ABOVE = 1,
68184 +    WMI_LQ_THRESHOLD1_BELOW,
68185 +    WMI_LQ_THRESHOLD2_ABOVE,
68186 +    WMI_LQ_THRESHOLD2_BELOW,
68187 +    WMI_LQ_THRESHOLD3_ABOVE,
68188 +    WMI_LQ_THRESHOLD3_BELOW,
68189 +    WMI_LQ_THRESHOLD4_ABOVE,
68190 +    WMI_LQ_THRESHOLD4_BELOW
68191 +} WMI_LQ_THRESHOLD_VAL;
68192 +
68193 +typedef PREPACK struct {
68194 +    A_INT32 lq;
68195 +    A_UINT8 range;  /* WMI_LQ_THRESHOLD_VAL */
68196 +}POSTPACK  WMI_LQ_THRESHOLD_EVENT;
68197 +/*
68198 + * WMI_REPORT_ROAM_TBL_EVENTID
68199 + */
68200 +#define MAX_ROAM_TBL_CAND   5
68201 +
68202 +typedef PREPACK struct {
68203 +    A_INT32 roam_util;
68204 +    A_UINT8 bssid[ATH_MAC_LEN];
68205 +    A_INT8  rssi;
68206 +    A_INT8  rssidt;
68207 +    A_INT8  last_rssi;
68208 +    A_INT8  util;
68209 +    A_INT8  bias;
68210 +    A_UINT8 reserved; /* For alignment */
68211 +} POSTPACK WMI_BSS_ROAM_INFO;
68212 +
68213 +
68214 +typedef PREPACK struct {
68215 +    A_UINT16  roamMode;
68216 +    A_UINT16  numEntries;
68217 +    WMI_BSS_ROAM_INFO bssRoamInfo[1];
68218 +} POSTPACK WMI_TARGET_ROAM_TBL;
68219 +
68220 +/*
68221 + *  WMI_CAC_EVENTID
68222 + */
68223 +typedef enum {
68224 +    CAC_INDICATION_ADMISSION = 0x00,
68225 +    CAC_INDICATION_ADMISSION_RESP = 0x01,
68226 +    CAC_INDICATION_DELETE = 0x02,
68227 +    CAC_INDICATION_NO_RESP = 0x03,
68228 +}CAC_INDICATION;
68229 +
68230 +#define WMM_TSPEC_IE_LEN   63
68231 +
68232 +typedef PREPACK struct {
68233 +    A_UINT8 ac;
68234 +    A_UINT8 cac_indication;
68235 +    A_UINT8 statusCode;
68236 +    A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN];
68237 +}POSTPACK  WMI_CAC_EVENT;
68238 +
68239 +/*
68240 + * WMI_APLIST_EVENTID
68241 + */
68242 +
68243 +typedef enum {
68244 +    APLIST_VER1 = 1,
68245 +} APLIST_VER;
68246 +
68247 +typedef PREPACK struct {
68248 +    A_UINT8     bssid[ATH_MAC_LEN];
68249 +    A_UINT16    channel;
68250 +} POSTPACK  WMI_AP_INFO_V1;
68251 +
68252 +typedef PREPACK union {
68253 +    WMI_AP_INFO_V1  apInfoV1;
68254 +} POSTPACK WMI_AP_INFO;
68255 +
68256 +typedef PREPACK struct {
68257 +    A_UINT8     apListVer;
68258 +    A_UINT8     numAP;
68259 +    WMI_AP_INFO apList[1];
68260 +} POSTPACK WMI_APLIST_EVENT;
68261 +
68262 +/*
68263 + * developer commands
68264 + */
68265 +
68266 +/*
68267 + * WMI_SET_BITRATE_CMDID
68268 + *
68269 + * Get bit rate cmd uses same definition as set bit rate cmd
68270 + */
68271 +typedef enum {
68272 +    RATE_AUTO   = -1,
68273 +    RATE_1Mb    = 0,
68274 +    RATE_2Mb    = 1,
68275 +    RATE_5_5Mb  = 2,
68276 +    RATE_11Mb   = 3,
68277 +    RATE_6Mb    = 4,
68278 +    RATE_9Mb    = 5,
68279 +    RATE_12Mb   = 6,
68280 +    RATE_18Mb   = 7,
68281 +    RATE_24Mb   = 8,
68282 +    RATE_36Mb   = 9,
68283 +    RATE_48Mb   = 10,
68284 +    RATE_54Mb   = 11,
68285 +} WMI_BIT_RATE;
68286 +
68287 +typedef PREPACK struct {
68288 +    A_INT8      rateIndex;          /* see WMI_BIT_RATE */
68289 +} POSTPACK WMI_BIT_RATE_CMD, WMI_BIT_RATE_REPLY;
68290 +
68291 +/*
68292 + * WMI_SET_FIXRATES_CMDID
68293 + *
68294 + * Get fix rates cmd uses same definition as set fix rates cmd
68295 + */
68296 +typedef enum {
68297 +    FIX_RATE_1Mb    = 0x1,
68298 +    FIX_RATE_2Mb    = 0x2,
68299 +    FIX_RATE_5_5Mb  = 0x4,
68300 +    FIX_RATE_11Mb   = 0x8,
68301 +    FIX_RATE_6Mb    = 0x10,
68302 +    FIX_RATE_9Mb    = 0x20,
68303 +    FIX_RATE_12Mb   = 0x40,
68304 +    FIX_RATE_18Mb   = 0x80,
68305 +    FIX_RATE_24Mb   = 0x100,
68306 +    FIX_RATE_36Mb   = 0x200,
68307 +    FIX_RATE_48Mb   = 0x400,
68308 +    FIX_RATE_54Mb   = 0x800,
68309 +} WMI_FIX_RATES_MASK;
68310 +
68311 +typedef PREPACK struct {
68312 +    A_UINT16      fixRateMask;          /* see WMI_BIT_RATE */
68313 +} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY;
68314 +
68315 +/*
68316 + * WMI_SET_RECONNECT_AUTH_MODE_CMDID
68317 + *
68318 + * Set authentication mode
68319 + */
68320 +typedef enum {
68321 +    RECONN_DO_AUTH = 0x00,
68322 +    RECONN_NOT_AUTH = 0x01
68323 +} WMI_AUTH_MODE;
68324 +
68325 +typedef PREPACK struct {
68326 +    A_UINT8 mode;
68327 +} POSTPACK WMI_SET_AUTH_MODE_CMD;
68328 +
68329 +/*
68330 + * WMI_SET_REASSOC_MODE_CMDID
68331 + *
68332 + * Set authentication mode
68333 + */
68334 +typedef enum {
68335 +    REASSOC_DO_DISASSOC = 0x00,
68336 +    REASSOC_DONOT_DISASSOC = 0x01
68337 +} WMI_REASSOC_MODE;
68338 +
68339 +typedef PREPACK struct {
68340 +    A_UINT8 mode;
68341 +}POSTPACK WMI_SET_REASSOC_MODE_CMD;
68342 +
68343 +typedef enum {
68344 +    ROAM_DATA_TIME = 1,            /* Get The Roam Time Data */
68345 +} ROAM_DATA_TYPE;
68346 +
68347 +typedef PREPACK struct {
68348 +    A_UINT32        disassoc_time;
68349 +    A_UINT32        no_txrx_time;
68350 +    A_UINT32        assoc_time;
68351 +    A_UINT32        allow_txrx_time;
68352 +    A_UINT32        last_data_txrx_time;
68353 +    A_UINT32        first_data_txrx_time;
68354 +    A_UINT8         disassoc_bssid[ATH_MAC_LEN];
68355 +    A_INT8          disassoc_bss_rssi;
68356 +    A_UINT8         assoc_bssid[ATH_MAC_LEN];
68357 +    A_INT8          assoc_bss_rssi;
68358 +} POSTPACK WMI_TARGET_ROAM_TIME;
68359 +
68360 +typedef PREPACK struct {
68361 +    PREPACK union {
68362 +        WMI_TARGET_ROAM_TIME roamTime;
68363 +    } POSTPACK u;
68364 +    A_UINT8 roamDataType ;
68365 +} POSTPACK WMI_TARGET_ROAM_DATA;
68366 +
68367 +typedef enum {
68368 +    WMI_WMM_DISABLED = 0,
68369 +    WMI_WMM_ENABLED
68370 +} WMI_WMM_STATUS;
68371 +
68372 +typedef PREPACK struct {
68373 +    A_UINT8    status;
68374 +}POSTPACK WMI_SET_WMM_CMD;
68375 +
68376 +typedef enum {
68377 +    WMI_TXOP_DISABLED = 0,
68378 +    WMI_TXOP_ENABLED
68379 +} WMI_TXOP_CFG;
68380 +
68381 +typedef PREPACK struct {
68382 +    A_UINT8    txopEnable;
68383 +}POSTPACK WMI_SET_WMM_TXOP_CMD;
68384 +
68385 +typedef PREPACK struct {
68386 +    A_UINT8 keepaliveInterval;
68387 +} POSTPACK WMI_SET_KEEPALIVE_CMD;
68388 +
68389 +typedef PREPACK struct {
68390 +    A_BOOL configured;
68391 +    A_UINT8 keepaliveInterval;
68392 +} POSTPACK WMI_GET_KEEPALIVE_CMD;
68393 +
68394 +/*
68395 + * Add Application specified IE to a management frame
68396 + */
68397 +#define WMI_MAX_IE_LEN  78
68398 +
68399 +typedef PREPACK struct {
68400 +    A_UINT8 mgmtFrmType;  /* one of WMI_MGMT_FRAME_TYPE */
68401 +    A_UINT8 ieLen;    /* Length  of the IE that should be added to the MGMT frame */
68402 +    A_UINT8 ieInfo[1];
68403 +} POSTPACK WMI_SET_APPIE_CMD;
68404 +
68405 +/*
68406 + * Notify the WSC registration status to the target
68407 + */
68408 +#define WSC_REG_ACTIVE     1
68409 +#define WSC_REG_INACTIVE   0
68410 +/* Generic Hal Interface for setting hal paramters. */
68411 +/* Add new Set HAL Param cmdIds here for newer params */
68412 +typedef enum {
68413 +   WHAL_SETCABTO_CMDID = 1,
68414 +}WHAL_CMDID;
68415 +
68416 +typedef PREPACK struct {
68417 +    A_UINT8 cabTimeOut;
68418 +} POSTPACK WHAL_SETCABTO_PARAM;
68419 +
68420 +typedef PREPACK struct {
68421 +    A_UINT8  whalCmdId;
68422 +    A_UINT8 data[1];
68423 +} POSTPACK WHAL_PARAMCMD;
68424 +
68425 +
68426 +#define WOW_MAX_FILTER_LISTS 1 /*4*/
68427 +#define WOW_MAX_FILTERS_PER_LIST 4
68428 +#define WOW_PATTERN_SIZE 64
68429 +#define WOW_MASK_SIZE 64
68430 +
68431 +typedef PREPACK struct {
68432 +    A_UINT8 wow_valid_filter;
68433 +    A_UINT8 wow_filter_id;
68434 +    A_UINT8 wow_filter_size;
68435 +    A_UINT8 wow_filter_offset;
68436 +    A_UINT8 wow_filter_mask[WOW_MASK_SIZE];
68437 +    A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE];
68438 +} POSTPACK WOW_FILTER;
68439 +
68440 +
68441 +typedef PREPACK struct {
68442 +    A_UINT8 wow_valid_list;
68443 +    A_UINT8 wow_list_id;
68444 +    A_UINT8 wow_num_filters;
68445 +    A_UINT8 wow_total_list_size;
68446 +    WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST];
68447 +} POSTPACK WOW_FILTER_LIST;
68448 +
68449 +typedef PREPACK struct {
68450 +    A_BOOL awake;
68451 +    A_BOOL asleep;
68452 +} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD;
68453 +
68454 +typedef PREPACK struct {
68455 +    A_BOOL enable_wow;
68456 +} POSTPACK WMI_SET_WOW_MODE_CMD;
68457 +
68458 +typedef PREPACK struct {
68459 +    A_UINT8 filter_list_id;
68460 +} POSTPACK WMI_GET_WOW_LIST_CMD;
68461 +
68462 +/*
68463 + * WMI_GET_WOW_LIST_CMD reply
68464 + */
68465 +typedef PREPACK struct {
68466 +    A_UINT8     num_filters;     /* number of patterns in reply */
68467 +    A_UINT8     this_filter_num; /*  this is filter # x of total num_filters */
68468 +    A_UINT8     wow_mode;
68469 +    A_UINT8     host_mode;
68470 +    WOW_FILTER  wow_filters[1];
68471 +} POSTPACK WMI_GET_WOW_LIST_REPLY;
68472 +
68473 +typedef PREPACK struct {
68474 +    A_UINT8 filter_list_id;
68475 +    A_UINT8 filter_size;
68476 +    A_UINT8 filter_offset;
68477 +    A_UINT8 filter[1];
68478 +} POSTPACK WMI_ADD_WOW_PATTERN_CMD;
68479 +
68480 +typedef PREPACK struct {
68481 +    A_UINT16 filter_list_id;
68482 +    A_UINT16 filter_id;
68483 +} POSTPACK WMI_DEL_WOW_PATTERN_CMD;
68484 +
68485 +typedef PREPACK struct {
68486 +    A_UINT8 macaddr[ATH_MAC_LEN];
68487 +} POSTPACK WMI_SET_MAC_ADDRESS_CMD;
68488 +
68489 +/*
68490 + * WMI_SET_AKMP_PARAMS_CMD
68491 + */
68492 +
68493 +#define WMI_AKMP_MULTI_PMKID_EN   0x000001
68494 +
68495 +typedef PREPACK struct {
68496 +    A_UINT32    akmpInfo;
68497 +} POSTPACK WMI_SET_AKMP_PARAMS_CMD;
68498 +
68499 +typedef PREPACK struct {
68500 +    A_UINT8 pmkid[WMI_PMKID_LEN];
68501 +} POSTPACK WMI_PMKID;
68502 +
68503 +/*
68504 + * WMI_SET_PMKID_LIST_CMD
68505 + */
68506 +#define WMI_MAX_PMKID_CACHE   8
68507 +
68508 +typedef PREPACK struct {
68509 +    A_UINT32    numPMKID;
68510 +    WMI_PMKID   pmkidList[WMI_MAX_PMKID_CACHE];
68511 +} POSTPACK WMI_SET_PMKID_LIST_CMD;
68512 +
68513 +/*
68514 + * WMI_GET_PMKID_LIST_CMD  Reply
68515 + * Following the Number of PMKIDs is the list of PMKIDs
68516 + */
68517 +typedef PREPACK struct {
68518 +    A_UINT32    numPMKID;
68519 +    WMI_PMKID   pmkidList[1];
68520 +} POSTPACK WMI_PMKID_LIST_REPLY;
68521 +
68522 +/* index used for priority streams */
68523 +typedef enum {
68524 +    WMI_NOT_MAPPED  = -1,
68525 +    WMI_CONTROL_PRI = 0,
68526 +    WMI_BEST_EFFORT_PRI = 1,
68527 +    WMI_LOW_PRI = 2,
68528 +    WMI_HIGH_PRI = 3,
68529 +    WMI_HIGHEST_PRI,
68530 +    WMI_PRI_MAX_COUNT
68531 +} WMI_PRI_STREAM_ID;
68532 +
68533 +#ifndef ATH_TARGET
68534 +#include "athendpack.h"
68535 +#endif
68536 +
68537 +#ifdef __cplusplus
68538 +}
68539 +#endif
68540 +
68541 +#endif /* _WMI_H_ */
68542 --- /dev/null
68543 +++ b/drivers/ar6000/include/wmix.h
68544 @@ -0,0 +1,233 @@
68545 +/*
68546 + * Copyright (c) 2004-2005 Atheros Communications Inc.
68547 + * All rights reserved.
68548 + *
68549 + *
68550 + * $ATH_LICENSE_HOSTSDK0_C$
68551 + *
68552 + * This file contains extensions of the WMI protocol specified in the
68553 + * Wireless Module Interface (WMI).  It includes definitions of all
68554 + * extended commands and events.  Extensions include useful commands
68555 + * that are not directly related to wireless activities.  They may
68556 + * be hardware-specific, and they might not be supported on all
68557 + * implementations.
68558 + *
68559 + * Extended WMIX commands are encapsulated in a WMI message with
68560 + * cmd=WMI_EXTENSION_CMD.
68561 + *
68562 + */
68563 +
68564 +#ifndef _WMIX_H_
68565 +#define _WMIX_H_
68566 +
68567 +#ifdef __cplusplus
68568 +extern "C" {
68569 +#endif
68570 +
68571 +#ifndef ATH_TARGET
68572 +#include "athstartpack.h"
68573 +#endif
68574 +
68575 +#include "dbglog.h"
68576 +
68577 +/*
68578 + * Extended WMI commands are those that are needed during wireless
68579 + * operation, but which are not really wireless commands.  This allows,
68580 + * for instance, platform-specific commands.  Extended WMI commands are
68581 + * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
68582 + * Extended WMI events are similarly embedded in a WMI event message with
68583 + * WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
68584 + */
68585 +typedef PREPACK struct {
68586 +    A_UINT32    commandId;
68587 +} POSTPACK WMIX_CMD_HDR;
68588 +
68589 +typedef enum {
68590 +    WMIX_DSETOPEN_REPLY_CMDID           = 0x2001,
68591 +    WMIX_DSETDATA_REPLY_CMDID,
68592 +    WMIX_GPIO_OUTPUT_SET_CMDID,
68593 +    WMIX_GPIO_INPUT_GET_CMDID,
68594 +    WMIX_GPIO_REGISTER_SET_CMDID,
68595 +    WMIX_GPIO_REGISTER_GET_CMDID,
68596 +    WMIX_GPIO_INTR_ACK_CMDID,
68597 +    WMIX_HB_CHALLENGE_RESP_CMDID,
68598 +    WMIX_DBGLOG_CFG_MODULE_CMDID,
68599 +} WMIX_COMMAND_ID;
68600 +
68601 +typedef enum {
68602 +    WMIX_DSETOPENREQ_EVENTID            = 0x3001,
68603 +    WMIX_DSETCLOSE_EVENTID,
68604 +    WMIX_DSETDATAREQ_EVENTID,
68605 +    WMIX_GPIO_INTR_EVENTID,
68606 +    WMIX_GPIO_DATA_EVENTID,
68607 +    WMIX_GPIO_ACK_EVENTID,
68608 +    WMIX_HB_CHALLENGE_RESP_EVENTID,
68609 +    WMIX_DBGLOG_EVENTID,
68610 +} WMIX_EVENT_ID;
68611 +
68612 +/*
68613 + * =============DataSet support=================
68614 + */
68615 +
68616 +/*
68617 + * WMIX_DSETOPENREQ_EVENTID
68618 + * DataSet Open Request Event
68619 + */
68620 +typedef PREPACK struct {
68621 +    A_UINT32 dset_id;
68622 +    A_UINT32 targ_dset_handle;  /* echo'ed, not used by Host, */
68623 +    A_UINT32 targ_reply_fn;     /* echo'ed, not used by Host, */
68624 +    A_UINT32 targ_reply_arg;    /* echo'ed, not used by Host, */
68625 +} POSTPACK WMIX_DSETOPENREQ_EVENT;
68626 +
68627 +/*
68628 + * WMIX_DSETCLOSE_EVENTID
68629 + * DataSet Close Event
68630 + */
68631 +typedef PREPACK struct {
68632 +    A_UINT32 access_cookie;
68633 +} POSTPACK WMIX_DSETCLOSE_EVENT;
68634 +
68635 +/*
68636 + * WMIX_DSETDATAREQ_EVENTID
68637 + * DataSet Data Request Event
68638 + */
68639 +typedef PREPACK struct {
68640 +    A_UINT32 access_cookie;
68641 +    A_UINT32 offset;
68642 +    A_UINT32 length;
68643 +    A_UINT32 targ_buf;         /* echo'ed, not used by Host, */
68644 +    A_UINT32 targ_reply_fn;    /* echo'ed, not used by Host, */
68645 +    A_UINT32 targ_reply_arg;   /* echo'ed, not used by Host, */
68646 +} POSTPACK WMIX_DSETDATAREQ_EVENT;
68647 +
68648 +typedef PREPACK struct {
68649 +    A_UINT32              status;
68650 +    A_UINT32              targ_dset_handle;
68651 +    A_UINT32              targ_reply_fn;
68652 +    A_UINT32              targ_reply_arg;
68653 +    A_UINT32              access_cookie;
68654 +    A_UINT32              size;
68655 +    A_UINT32              version;
68656 +} POSTPACK WMIX_DSETOPEN_REPLY_CMD;
68657 +
68658 +typedef PREPACK struct {
68659 +    A_UINT32              status;
68660 +    A_UINT32              targ_buf;
68661 +    A_UINT32              targ_reply_fn;
68662 +    A_UINT32              targ_reply_arg;
68663 +    A_UINT32              length;
68664 +    A_UINT8               buf[1];
68665 +} POSTPACK WMIX_DSETDATA_REPLY_CMD;
68666 +
68667 +
68668 +/*
68669 + * =============GPIO support=================
68670 + * All masks are 18-bit masks with bit N operating on GPIO pin N.
68671 + */
68672 +
68673 +#include "gpio.h"
68674 +
68675 +/*
68676 + * Set GPIO pin output state.
68677 + * In order for output to be driven, a pin must be enabled for output.
68678 + * This can be done during initialization through the GPIO Configuration
68679 + * DataSet, or during operation with the enable_mask.
68680 + *
68681 + * If a request is made to simultaneously set/clear or set/disable or
68682 + * clear/disable or disable/enable, results are undefined.
68683 + */
68684 +typedef PREPACK struct {
68685 +    A_UINT32              set_mask;             /* pins to set */
68686 +    A_UINT32              clear_mask;           /* pins to clear */
68687 +    A_UINT32              enable_mask;          /* pins to enable for output */
68688 +    A_UINT32              disable_mask;         /* pins to disable/tristate */
68689 +} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD;
68690 +
68691 +/*
68692 + * Set a GPIO register.  For debug/exceptional cases.
68693 + * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a
68694 + * platform-dependent header.
68695 + */
68696 +typedef PREPACK struct {
68697 +    A_UINT32              gpioreg_id;           /* GPIO register ID */
68698 +    A_UINT32              value;                /* value to write */
68699 +} POSTPACK WMIX_GPIO_REGISTER_SET_CMD;
68700 +
68701 +/* Get a GPIO register.  For debug/exceptional cases. */
68702 +typedef PREPACK struct {
68703 +    A_UINT32              gpioreg_id;           /* GPIO register to read */
68704 +} POSTPACK WMIX_GPIO_REGISTER_GET_CMD;
68705 +
68706 +/*
68707 + * Host acknowledges and re-arms GPIO interrupts.  A single
68708 + * message should be used to acknowledge all interrupts that
68709 + * were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
68710 + */
68711 +typedef PREPACK struct {
68712 +    A_UINT32              ack_mask;             /* interrupts to acknowledge */
68713 +} POSTPACK WMIX_GPIO_INTR_ACK_CMD;
68714 +
68715 +/*
68716 + * Target informs Host of GPIO interrupts that have ocurred since the
68717 + * last WMIX_GIPO_INTR_ACK_CMD was received.  Additional information --
68718 + * the current GPIO input values is provided -- in order to support
68719 + * use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
68720 + */
68721 +typedef PREPACK struct {
68722 +    A_UINT32              intr_mask;            /* pending GPIO interrupts */
68723 +    A_UINT32              input_values;         /* recent GPIO input values */
68724 +} POSTPACK WMIX_GPIO_INTR_EVENT;
68725 +
68726 +/*
68727 + * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request
68728 + * using a GPIO_DATA_EVENT with
68729 + *   value set to the mask of GPIO pin inputs and
68730 + *   reg_id set to GPIO_ID_NONE
68731 + *
68732 + *
68733 + * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request
68734 + * using a GPIO_DATA_EVENT with
68735 + *   value set to the value of the requested register and
68736 + *   reg_id identifying the register (reflects the original request)
68737 + * NB: reg_id supports the future possibility of unsolicited
68738 + * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may
68739 + * simplify Host GPIO support.
68740 + */
68741 +typedef PREPACK struct {
68742 +    A_UINT32              value;
68743 +    A_UINT32              reg_id;
68744 +} POSTPACK WMIX_GPIO_DATA_EVENT;
68745 +
68746 +/*
68747 + * =============Error Detection support=================
68748 + */
68749 +
68750 +/*
68751 + * WMIX_HB_CHALLENGE_RESP_CMDID
68752 + * Heartbeat Challenge Response command
68753 + */
68754 +typedef PREPACK struct {
68755 +    A_UINT32              cookie;
68756 +    A_UINT32              source;
68757 +} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD;
68758 +
68759 +/*
68760 + * WMIX_HB_CHALLENGE_RESP_EVENTID
68761 + * Heartbeat Challenge Response Event
68762 + */
68763 +#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD
68764 +
68765 +typedef PREPACK struct {
68766 +    struct dbglog_config_s config;
68767 +} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD;
68768 +
68769 +#ifndef ATH_TARGET
68770 +#include "athendpack.h"
68771 +#endif
68772 +
68773 +#ifdef __cplusplus
68774 +}
68775 +#endif
68776 +
68777 +#endif /* _WMIX_H_ */
68778 --- /dev/null
68779 +++ b/drivers/ar6000/Kconfig
68780 @@ -0,0 +1,7 @@
68781 +config AR6000_WLAN
68782 +        tristate "AR6000 wireless networking over SDIO"
68783 +       depends on MMC
68784 +        select WIRELESS_EXT
68785 +        default m
68786 +        help
68787 +          good luck.
68788 --- /dev/null
68789 +++ b/drivers/ar6000/Makefile
68790 @@ -0,0 +1,38 @@
68791 +REV ?= 2
68792 +
68793 +PWD := $(shell pwd)
68794 +
68795 +EXTRA_CFLAGS += -I$(src)/include
68796 +
68797 +EXTRA_CFLAGS += -DLINUX -D__KERNEL__ -DHTC_RAW_INTERFACE\
68798 +                -DTCMD -DUSER_KEYS \
68799 +                -DNO_SYNC_FLUSH #\
68800 +                -DMULTIPLE_FRAMES_PER_INTERRUPT -DAR6000REV$(REV) \
68801 +                -DBLOCK_TX_PATH_FLAG \
68802 +               -DSDIO \
68803 +
68804 +EXTRA_CFLAGS += -DKERNEL_2_6
68805 +
68806 +obj-$(CONFIG_AR6000_WLAN) += ar6000.o
68807 +
68808 +ar6000-objs += htc/ar6k.o                         \
68809 +              htc/ar6k_events.o           \
68810 +               htc/htc_send.o             \
68811 +               htc/htc_recv.o             \
68812 +               htc/htc_services.o          \
68813 +               htc/htc.o                  \
68814 +               hif/hif2.o                 \
68815 +               bmi/bmi.o                   \
68816 +               ar6000/ar6000_drv.o         \
68817 +               ar6000/ar6000_raw_if.o     \
68818 +               ar6000/netbuf.o            \
68819 +               ar6000/wireless_ext.o      \
68820 +               ar6000/ioctl.o             \
68821 +               miscdrv/common_drv.o       \
68822 +               miscdrv/credit_dist.o      \
68823 +               wmi/wmi.o                   \
68824 +               wlan/wlan_node.o            \
68825 +               wlan/wlan_recv_beacon.o     \
68826 +               wlan/wlan_utils.o
68827 +
68828 +
68829 --- /dev/null
68830 +++ b/drivers/ar6000/miscdrv/common_drv.c
68831 @@ -0,0 +1,467 @@
68832 +
68833 +/*
68834 + *
68835 + * Copyright (c) 2004-2007 Atheros Communications Inc.
68836 + * All rights reserved.
68837 + *
68838 + *
68839 + *  This program is free software; you can redistribute it and/or modify
68840 + *  it under the terms of the GNU General Public License version 2 as
68841 + *  published by the Free Software Foundation;
68842 + *
68843 + *  Software distributed under the License is distributed on an "AS
68844 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
68845 + *  implied. See the License for the specific language governing
68846 + *  rights and limitations under the License.
68847 + *
68848 + *
68849 + *
68850 + */
68851 +
68852 +#include "a_config.h"
68853 +#include "athdefs.h"
68854 +#include "a_types.h"
68855 +#include "AR6Khwreg.h"
68856 +#include "targaddrs.h"
68857 +#include "a_osapi.h"
68858 +#include "hif.h"
68859 +#include "htc_api.h"
68860 +#include "bmi.h"
68861 +#include "bmi_msg.h"
68862 +#include "common_drv.h"
68863 +#include "a_debug.h"
68864 +#include "targaddrs.h"
68865 +
68866 +#define HOST_INTEREST_ITEM_ADDRESS(target, item)    \
68867 +(((TargetType) == TARGET_TYPE_AR6001) ?     \
68868 +   AR6001_HOST_INTEREST_ITEM_ADDRESS(item) :    \
68869 +   AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
68870 +
68871 +
68872 +/* Compile the 4BYTE version of the window register setup routine,
68873 + * This mitigates host interconnect issues with non-4byte aligned bus requests, some
68874 + * interconnects use bus adapters that impose strict limitations.
68875 + * Since diag window access is not intended for performance critical operations, the 4byte mode should
68876 + * be satisfactory even though it generates 4X the bus activity. */
68877 +
68878 +#ifdef USE_4BYTE_REGISTER_ACCESS
68879 +
68880 +    /* set the window address register (using 4-byte register access ). */
68881 +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
68882 +{
68883 +    A_STATUS status;
68884 +    A_UINT8 addrValue[4];
68885 +    int i;
68886 +
68887 +        /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
68888 +         * last to initiate the access cycle */
68889 +
68890 +    for (i = 1; i <= 3; i++) {
68891 +            /* fill the buffer with the address byte value we want to hit 4 times*/
68892 +        addrValue[0] = ((A_UINT8 *)&Address)[i];
68893 +        addrValue[1] = addrValue[0];
68894 +        addrValue[2] = addrValue[0];
68895 +        addrValue[3] = addrValue[0];
68896 +
68897 +            /* hit each byte of the register address with a 4-byte write operation to the same address,
68898 +             * this is a harmless operation */
68899 +        status = HIFReadWrite(hifDevice,
68900 +                              RegisterAddr+i,
68901 +                              addrValue,
68902 +                              4,
68903 +                              HIF_WR_SYNC_BYTE_FIX,
68904 +                              NULL);
68905 +        if (status != A_OK) {
68906 +            break;
68907 +        }
68908 +    }
68909 +
68910 +    if (status != A_OK) {
68911 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
68912 +             RegisterAddr, Address));
68913 +        return status;
68914 +    }
68915 +
68916 +        /* write the address register again, this time write the whole 4-byte value.
68917 +         * The effect here is that the LSB write causes the cycle to start, the extra
68918 +         * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
68919 +    status = HIFReadWrite(hifDevice,
68920 +                          RegisterAddr,
68921 +                          (A_UCHAR *)(&Address),
68922 +                          4,
68923 +                          HIF_WR_SYNC_BYTE_INC,
68924 +                          NULL);
68925 +
68926 +    if (status != A_OK) {
68927 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
68928 +            RegisterAddr, Address));
68929 +        return status;
68930 +    }
68931 +
68932 +    return A_OK;
68933 +
68934 +
68935 +
68936 +}
68937 +
68938 +
68939 +#else
68940 +
68941 +    /* set the window address register */
68942 +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
68943 +{
68944 +    A_STATUS status;
68945 +
68946 +        /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
68947 +         * last to initiate the access cycle */
68948 +    status = HIFReadWrite(hifDevice,
68949 +                          RegisterAddr+1,  /* write upper 3 bytes */
68950 +                          ((A_UCHAR *)(&Address))+1,
68951 +                          sizeof(A_UINT32)-1,
68952 +                          HIF_WR_SYNC_BYTE_INC,
68953 +                          NULL);
68954 +
68955 +    if (status != A_OK) {
68956 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
68957 +             RegisterAddr, Address));
68958 +        return status;
68959 +    }
68960 +
68961 +        /* write the LSB of the register, this initiates the operation */
68962 +    status = HIFReadWrite(hifDevice,
68963 +                          RegisterAddr,
68964 +                          (A_UCHAR *)(&Address),
68965 +                          sizeof(A_UINT8),
68966 +                          HIF_WR_SYNC_BYTE_INC,
68967 +                          NULL);
68968 +
68969 +    if (status != A_OK) {
68970 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
68971 +            RegisterAddr, Address));
68972 +        return status;
68973 +    }
68974 +
68975 +    return A_OK;
68976 +}
68977 +
68978 +#endif
68979 +
68980 +/*
68981 + * Read from the AR6000 through its diagnostic window.
68982 + * No cooperation from the Target is required for this.
68983 + */
68984 +A_STATUS
68985 +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
68986 +{
68987 +    A_STATUS status;
68988 +
68989 +        /* set window register to start read cycle */
68990 +    status = ar6000_SetAddressWindowRegister(hifDevice,
68991 +                                             WINDOW_READ_ADDR_ADDRESS,
68992 +                                             *address);
68993 +
68994 +    if (status != A_OK) {
68995 +        return status;
68996 +    }
68997 +
68998 +        /* read the data */
68999 +    status = HIFReadWrite(hifDevice,
69000 +                          WINDOW_DATA_ADDRESS,
69001 +                          (A_UCHAR *)data,
69002 +                          sizeof(A_UINT32),
69003 +                          HIF_RD_SYNC_BYTE_INC,
69004 +                          NULL);
69005 +    if (status != A_OK) {
69006 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
69007 +        return status;
69008 +    }
69009 +
69010 +    return status;
69011 +}
69012 +
69013 +
69014 +/*
69015 + * Write to the AR6000 through its diagnostic window.
69016 + * No cooperation from the Target is required for this.
69017 + */
69018 +A_STATUS
69019 +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
69020 +{
69021 +    A_STATUS status;
69022 +
69023 +        /* set write data */
69024 +    status = HIFReadWrite(hifDevice,
69025 +                          WINDOW_DATA_ADDRESS,
69026 +                          (A_UCHAR *)data,
69027 +                          sizeof(A_UINT32),
69028 +                          HIF_WR_SYNC_BYTE_INC,
69029 +                          NULL);
69030 +    if (status != A_OK) {
69031 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data));
69032 +        return status;
69033 +    }
69034 +
69035 +        /* set window register, which starts the write cycle */
69036 +    return ar6000_SetAddressWindowRegister(hifDevice,
69037 +                                           WINDOW_WRITE_ADDR_ADDRESS,
69038 +                                           *address);
69039 +}
69040 +
69041 +A_STATUS
69042 +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
69043 +                    A_UCHAR *data, A_UINT32 length)
69044 +{
69045 +    A_UINT32 count;
69046 +    A_STATUS status = A_OK;
69047 +
69048 +    for (count = 0; count < length; count += 4, address += 4) {
69049 +        if ((status = ar6000_ReadRegDiag(hifDevice, &address,
69050 +                                         (A_UINT32 *)&data[count])) != A_OK)
69051 +        {
69052 +            break;
69053 +        }
69054 +    }
69055 +
69056 +    return status;
69057 +}
69058 +
69059 +A_STATUS
69060 +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
69061 +                     A_UCHAR *data, A_UINT32 length)
69062 +{
69063 +    A_UINT32 count;
69064 +    A_STATUS status = A_OK;
69065 +
69066 +    for (count = 0; count < length; count += 4, address += 4) {
69067 +        if ((status = ar6000_WriteRegDiag(hifDevice, &address,
69068 +                                          (A_UINT32 *)&data[count])) != A_OK)
69069 +        {
69070 +            break;
69071 +        }
69072 +    }
69073 +
69074 +    return status;
69075 +}
69076 +
69077 +A_STATUS
69078 +ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice)
69079 +{
69080 +    int i;
69081 +    struct forceROM_s {
69082 +        A_UINT32 addr;
69083 +        A_UINT32 data;
69084 +    };
69085 +    struct forceROM_s *ForceROM;
69086 +    int szForceROM;
69087 +    A_UINT32 instruction;
69088 +
69089 +    static struct forceROM_s ForceROM_REV2[] = {
69090 +        /* NB: This works for old REV2 ROM (old). */
69091 +        {0x00001ff0, 0x175b0027}, /* jump instruction at 0xa0001ff0 */
69092 +        {0x00001ff4, 0x00000000}, /* nop instruction at 0xa0001ff4 */
69093 +
69094 +        {MC_REMAP_TARGET_ADDRESS, 0x00001ff0}, /* remap to 0xa0001ff0 */
69095 +        {MC_REMAP_COMPARE_ADDRESS, 0x01000040},/* ...from 0xbfc00040 */
69096 +        {MC_REMAP_SIZE_ADDRESS, 0x00000000},   /* ...1 cache line */
69097 +        {MC_REMAP_VALID_ADDRESS, 0x00000001},  /* ...remap is valid */
69098 +
69099 +        {LOCAL_COUNT_ADDRESS+0x10, 0}, /* clear BMI credit counter */
69100 +
69101 +        {RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
69102 +    };
69103 +
69104 +    static struct forceROM_s ForceROM_NEW[] = {
69105 +        /* NB: This works for AR6000 ROM REV3 and beyond.  */
69106 +        {LOCAL_SCRATCH_ADDRESS, AR6K_OPTION_IGNORE_FLASH},
69107 +        {LOCAL_COUNT_ADDRESS+0x10, 0}, /* clear BMI credit counter */
69108 +        {RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
69109 +    };
69110 +
69111 +    /*
69112 +     * Examine a semi-arbitrary instruction that's different
69113 +     * in REV2 and other revisions.
69114 +     * NB: If a Host port does not require simultaneous support
69115 +     * for multiple revisions of Target ROM, this code can be elided.
69116 +     */
69117 +    (void)ar6000_ReadDataDiag(hifDevice, 0x01000040,
69118 +                              (A_UCHAR *)&instruction, 4);
69119 +
69120 +    AR_DEBUG_PRINTF(ATH_LOG_ERR, ("instruction=0x%x\n", instruction));
69121 +
69122 +    if (instruction == 0x3c1aa200) {
69123 +        /* It's an old ROM */
69124 +        ForceROM = ForceROM_REV2;
69125 +        szForceROM = sizeof(ForceROM_REV2)/sizeof(*ForceROM);
69126 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Using OLD method\n"));
69127 +    } else {
69128 +        ForceROM = ForceROM_NEW;
69129 +        szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM);
69130 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Using NEW method\n"));
69131 +    }
69132 +
69133 +    AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Force Target to execute from ROM....\n"));
69134 +    for (i = 0; i < szForceROM; i++)
69135 +    {
69136 +        if (ar6000_WriteRegDiag(hifDevice,
69137 +                                &ForceROM[i].addr,
69138 +                                &ForceROM[i].data) != A_OK)
69139 +        {
69140 +            AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n"));
69141 +            return A_ERROR;
69142 +        }
69143 +    }
69144 +
69145 +    A_MDELAY(50); /* delay to allow dragon to come to BMI phase  */
69146 +    return A_OK;
69147 +}
69148 +
69149 +/* reset device */
69150 +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
69151 +{
69152 +
69153 +#if !defined(DWSIM)
69154 +    A_STATUS status = A_OK;
69155 +    A_UINT32 address;
69156 +    A_UINT32 data;
69157 +
69158 +    do {
69159 +
69160 +        // address = RESET_CONTROL_ADDRESS;
69161 +        data = RESET_CONTROL_COLD_RST_MASK;
69162 +
69163 +          /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */
69164 +        if (TargetType == TARGET_TYPE_AR6001) {
69165 +            address = 0x0C000000;
69166 +        } else {
69167 +            if (TargetType == TARGET_TYPE_AR6002) {
69168 +                address = 0x00004000;
69169 +            } else {
69170 +                A_ASSERT(0);
69171 +            }
69172 +        }
69173 +
69174 +        status = ar6000_WriteRegDiag(hifDevice, &address, &data);
69175 +
69176 +        if (A_FAILED(status)) {
69177 +            break;
69178 +        }
69179 +
69180 +        /*
69181 +         * Read back the RESET CAUSE register to ensure that the cold reset
69182 +         * went through.
69183 +         */
69184 +        A_MDELAY(2000); /* 2 second delay to allow things to settle down */
69185 +
69186 +
69187 +        // address = RESET_CAUSE_ADDRESS;
69188 +        /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */
69189 +        if (TargetType == TARGET_TYPE_AR6001) {
69190 +            address = 0x0C0000CC;
69191 +        } else {
69192 +            if (TargetType == TARGET_TYPE_AR6002) {
69193 +                address = 0x000040C0;
69194 +            } else {
69195 +                A_ASSERT(0);
69196 +            }
69197 +        }
69198 +
69199 +        data = 0;
69200 +        status = ar6000_ReadRegDiag(hifDevice, &address, &data);
69201 +
69202 +        if (A_FAILED(status)) {
69203 +            break;
69204 +        }
69205 +
69206 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data));
69207 +        data &= RESET_CAUSE_LAST_MASK;
69208 +        if (data != 2) {
69209 +            AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n"));
69210 +        }
69211 +
69212 +    } while (FALSE);
69213 +
69214 +    if (A_FAILED(status)) {
69215 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n"));
69216 +    }
69217 +#endif
69218 +    return A_OK;
69219 +}
69220 +
69221 +#define REG_DUMP_COUNT_AR6001   38  /* WORDs, derived from AR6001_regdump.h */
69222 +#define REG_DUMP_COUNT_AR6002   32  /* WORDs, derived from AR6002_regdump.h */
69223 +
69224 +
69225 +#if REG_DUMP_COUNT_AR6001 <= REG_DUMP_COUNT_AR6002
69226 +#define REGISTER_DUMP_LEN_MAX  REG_DUMP_COUNT_AR6002
69227 +#else
69228 +#define REGISTER_DUMP_LEN_MAX  REG_DUMP_COUNT_AR6001
69229 +#endif
69230 +
69231 +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
69232 +{
69233 +    A_UINT32 address;
69234 +    A_UINT32 regDumpArea = 0;
69235 +    A_STATUS status;
69236 +    A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX];
69237 +    A_UINT32 regDumpCount = 0;
69238 +    A_UINT32 i;
69239 +
69240 +    do {
69241 +
69242 +            /* the reg dump pointer is copied to the host interest area */
69243 +        address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state);
69244 +
69245 +        if (TargetType == TARGET_TYPE_AR6001) {
69246 +                /* for AR6001, this is a fixed location because the ptr is actually stuck in cache,
69247 +                 * this may be fixed in later firmware versions */
69248 +            address = 0x18a0;
69249 +            regDumpCount = REG_DUMP_COUNT_AR6001;
69250 +
69251 +        } else  if (TargetType == TARGET_TYPE_AR6002) {
69252 +
69253 +            regDumpCount = REG_DUMP_COUNT_AR6002;
69254 +
69255 +        } else {
69256 +            A_ASSERT(0);
69257 +        }
69258 +
69259 +            /* read RAM location through diagnostic window */
69260 +        status = ar6000_ReadRegDiag(hifDevice, &address, &regDumpArea);
69261 +
69262 +        if (A_FAILED(status)) {
69263 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n"));
69264 +            break;
69265 +        }
69266 +
69267 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea));
69268 +
69269 +        if (regDumpArea == 0) {
69270 +                /* no reg dump */
69271 +            break;
69272 +        }
69273 +
69274 +        if (TargetType == TARGET_TYPE_AR6001) {
69275 +            regDumpArea &= 0x0FFFFFFF;  /* convert to physical address in target memory */
69276 +        }
69277 +
69278 +            /* fetch register dump data */
69279 +        status = ar6000_ReadDataDiag(hifDevice,
69280 +                                     regDumpArea,
69281 +                                     (A_UCHAR *)&regDumpValues[0],
69282 +                                     regDumpCount * (sizeof(A_UINT32)));
69283 +
69284 +        if (A_FAILED(status)) {
69285 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n"));
69286 +            break;
69287 +        }
69288 +
69289 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n"));
69290 +
69291 +        for (i = 0; i < regDumpCount; i++) {
69292 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d :  0x%8.8X \n",i, regDumpValues[i]));
69293 +        }
69294 +
69295 +    } while (FALSE);
69296 +
69297 +}
69298 +
69299 --- /dev/null
69300 +++ b/drivers/ar6000/miscdrv/credit_dist.c
69301 @@ -0,0 +1,346 @@
69302 +
69303 +/*
69304 + *
69305 + * Copyright (c) 2004-2007 Atheros Communications Inc.
69306 + * All rights reserved.
69307 + *
69308 + *
69309 + *  This program is free software; you can redistribute it and/or modify
69310 + *  it under the terms of the GNU General Public License version 2 as
69311 + *  published by the Free Software Foundation;
69312 + *
69313 + *  Software distributed under the License is distributed on an "AS
69314 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
69315 + *  implied. See the License for the specific language governing
69316 + *  rights and limitations under the License.
69317 + *
69318 + *
69319 + *
69320 + */
69321 +
69322 +#include "a_config.h"
69323 +#include "athdefs.h"
69324 +#include "a_types.h"
69325 +#include "a_osapi.h"
69326 +#include "a_debug.h"
69327 +#include "htc_api.h"
69328 +#include "common_drv.h"
69329 +
69330 +/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/
69331 +
69332 +#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */
69333 +
69334 +#ifdef NO_VO_SERVICE
69335 +#define DATA_SVCS_USED 3
69336 +#else
69337 +#define DATA_SVCS_USED 4
69338 +#endif
69339 +
69340 +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
69341 +                                HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
69342 +
69343 +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
69344 +                        HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
69345 +
69346 +/* reduce an ep's credits back to a set limit */
69347 +static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
69348 +                                HTC_ENDPOINT_CREDIT_DIST  *pEpDist,
69349 +                                int                       Limit)
69350 +{
69351 +    int credits;
69352 +
69353 +        /* set the new limit */
69354 +    pEpDist->TxCreditsAssigned = Limit;
69355 +
69356 +    if (pEpDist->TxCredits <= Limit) {
69357 +        return;
69358 +    }
69359 +
69360 +        /* figure out how much to take away */
69361 +    credits = pEpDist->TxCredits - Limit;
69362 +        /* take them away */
69363 +    pEpDist->TxCredits -= credits;
69364 +    pCredInfo->CurrentFreeCredits += credits;
69365 +}
69366 +
69367 +/* give an endpoint some credits from the free credit pool */
69368 +#define GiveCredits(pCredInfo,pEpDist,credits)      \
69369 +{                                                   \
69370 +    (pEpDist)->TxCredits += (credits);              \
69371 +    (pEpDist)->TxCreditsAssigned += (credits);      \
69372 +    (pCredInfo)->CurrentFreeCredits -= (credits);   \
69373 +}
69374 +
69375 +
69376 +/* default credit init callback.
69377 + * This function is called in the context of HTCStart() to setup initial (application-specific)
69378 + * credit distributions */
69379 +static void ar6000_credit_init(void                     *Context,
69380 +                               HTC_ENDPOINT_CREDIT_DIST *pEPList,
69381 +                               int                      TotalCredits)
69382 +{
69383 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
69384 +    int                      count;
69385 +    COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
69386 +
69387 +    pCredInfo->CurrentFreeCredits = TotalCredits;
69388 +    pCredInfo->TotalAvailableCredits = TotalCredits;
69389 +
69390 +    pCurEpDist = pEPList;
69391 +
69392 +        /* run through the list and initialize */
69393 +    while (pCurEpDist != NULL) {
69394 +
69395 +            /* set minimums for each endpoint */
69396 +        pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
69397 +
69398 +        if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
69399 +                /* give control service some credits */
69400 +            GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin);
69401 +                /* control service is always marked active, it never goes inactive EVER */
69402 +            SET_EP_ACTIVE(pCurEpDist);
69403 +        } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) {
69404 +                /* this is the lowest priority data endpoint, save this off for easy access */
69405 +            pCredInfo->pLowestPriEpDist = pCurEpDist;
69406 +        }
69407 +
69408 +        /* Streams have to be created (explicit | implicit)for all kinds
69409 +         * of traffic. BE endpoints are also inactive in the beginning.
69410 +         * When BE traffic starts it creates implicit streams that
69411 +         * redistributes credits.
69412 +         */
69413 +
69414 +        /* note, all other endpoints have minimums set but are initially given NO credits.
69415 +         * Credits will be distributed as traffic activity demands */
69416 +        pCurEpDist = pCurEpDist->pNext;
69417 +    }
69418 +
69419 +    if (pCredInfo->CurrentFreeCredits <= 0) {
69420 +        AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits));
69421 +        A_ASSERT(FALSE);
69422 +        return;
69423 +    }
69424 +
69425 +        /* reset list */
69426 +    pCurEpDist = pEPList;
69427 +        /* now run through the list and set max operating credit limits for everyone */
69428 +    while (pCurEpDist != NULL) {
69429 +        if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
69430 +                /* control service max is just 1 max message */
69431 +            pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg;
69432 +        } else {
69433 +                /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are
69434 +                 * the same.
69435 +                 * We use a simple calculation here, we take the remaining credits and
69436 +                 * determine how many max messages this can cover and then set each endpoint's
69437 +                 * normal value equal to half this amount.
69438 +                 * */
69439 +            count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg;
69440 +            count = count >> 1;
69441 +            count = max(count,pCurEpDist->TxCreditsPerMaxMsg);
69442 +                /* set normal */
69443 +            pCurEpDist->TxCreditsNorm = count;
69444 +
69445 +        }
69446 +        pCurEpDist = pCurEpDist->pNext;
69447 +    }
69448 +
69449 +}
69450 +
69451 +
69452 +/* default credit distribution callback
69453 + * This callback is invoked whenever endpoints require credit distributions.
69454 + * A lock is held while this function is invoked, this function shall NOT block.
69455 + * The pEPDistList is a list of distribution structures in prioritized order as
69456 + * defined by the call to the HTCSetCreditDistribution() api.
69457 + *
69458 + */
69459 +static void ar6000_credit_distribute(void                     *Context,
69460 +                                     HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
69461 +                                     HTC_CREDIT_DIST_REASON   Reason)
69462 +{
69463 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
69464 +    COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
69465 +
69466 +    switch (Reason) {
69467 +        case HTC_CREDIT_DIST_SEND_COMPLETE :
69468 +            pCurEpDist = pEPDistList;
69469 +                /* we are given the start of the endpoint distribution list.
69470 +                 * There may be one or more endpoints to service.
69471 +                 * Run through the list and distribute credits */
69472 +            while (pCurEpDist != NULL) {
69473 +
69474 +                if (pCurEpDist->TxCreditsToDist > 0) {
69475 +                        /* return the credits back to the endpoint */
69476 +                    pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
69477 +                        /* always zero out when we are done */
69478 +                    pCurEpDist->TxCreditsToDist = 0;
69479 +
69480 +                    if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) {
69481 +                            /* reduce to the assigned limit, previous credit reductions
69482 +                             * could have caused the limit to change */
69483 +                        ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned);
69484 +                    }
69485 +
69486 +                    if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) {
69487 +                            /* oversubscribed endpoints need to reduce back to normal */
69488 +                        ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm);
69489 +                    }
69490 +                }
69491 +
69492 +                pCurEpDist = pCurEpDist->pNext;
69493 +            }
69494 +
69495 +            A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits);
69496 +
69497 +            break;
69498 +
69499 +        case HTC_CREDIT_DIST_ACTIVITY_CHANGE :
69500 +            RedistributeCredits(pCredInfo,pEPDistList);
69501 +            break;
69502 +        case HTC_CREDIT_DIST_SEEK_CREDITS :
69503 +            SeekCredits(pCredInfo,pEPDistList);
69504 +            break;
69505 +        case HTC_DUMP_CREDIT_STATE :
69506 +            AR_DEBUG_PRINTF(ATH_LOG_INF, ("Credit Distribution, total : %d, free : %d\n",
69507 +                                                                       pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits));
69508 +            break;
69509 +        default:
69510 +            break;
69511 +
69512 +    }
69513 +
69514 +}
69515 +
69516 +/* redistribute credits based on activity change */
69517 +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
69518 +                                HTC_ENDPOINT_CREDIT_DIST *pEPDistList)
69519 +{
69520 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList;
69521 +
69522 +        /* walk through the list and remove credits from inactive endpoints */
69523 +    while (pCurEpDist != NULL) {
69524 +
69525 +        if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) {
69526 +            if (!IS_EP_ACTIVE(pCurEpDist)) {
69527 +                    /* EP is inactive, reduce credits back to zero */
69528 +                ReduceCredits(pCredInfo, pCurEpDist, 0);
69529 +            }
69530 +        }
69531 +
69532 +        /* NOTE in the active case, we do not need to do anything further,
69533 +         * when an EP goes active and needs credits, HTC will call into
69534 +         * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS  */
69535 +
69536 +        pCurEpDist = pCurEpDist->pNext;
69537 +    }
69538 +
69539 +    A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits);
69540 +
69541 +}
69542 +
69543 +/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */
69544 +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
69545 +                        HTC_ENDPOINT_CREDIT_DIST *pEPDist)
69546 +{
69547 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
69548 +    int                      credits = 0;
69549 +    int                      need;
69550 +
69551 +    do {
69552 +
69553 +        if (pEPDist->ServiceID == WMI_CONTROL_SVC) {
69554 +                /* we never oversubscribe on the control service, this is not
69555 +                 * a high performance path and the target never holds onto control
69556 +                 * credits for too long */
69557 +            break;
69558 +        }
69559 +
69560 +        /* for all other services, we follow a simple algorithm of
69561 +         * 1. checking the free pool for credits
69562 +         * 2. checking lower priority endpoints for credits to take */
69563 +
69564 +        if (pCredInfo->CurrentFreeCredits >= 2 * pEPDist->TxCreditsSeek) {
69565 +                /* try to give more credits than it needs */
69566 +            credits = 2 * pEPDist->TxCreditsSeek;
69567 +        } else {
69568 +                /* give what we can */
69569 +            credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
69570 +        }
69571 +
69572 +        if (credits >= pEPDist->TxCreditsSeek) {
69573 +                /* we found some to fullfill the seek request */
69574 +            break;
69575 +        }
69576 +
69577 +        /* we don't have enough in the free pool, try taking away from lower priority services
69578 +         *
69579 +         * The rule for taking away credits:
69580 +         *   1. Only take from lower priority endpoints
69581 +         *   2. Only take what is allocated above the minimum (never starve an endpoint completely)
69582 +         *   3. Only take what you need.
69583 +         *
69584 +         * */
69585 +
69586 +            /* starting at the lowest priority */
69587 +        pCurEpDist = pCredInfo->pLowestPriEpDist;
69588 +
69589 +            /* work backwards until we hit the endpoint again */
69590 +        while (pCurEpDist != pEPDist) {
69591 +                /* calculate how many we need so far */
69592 +            need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits;
69593 +
69594 +            if ((pCurEpDist->TxCreditsAssigned - need) > pCurEpDist->TxCreditsMin) {
69595 +                    /* the current one has been allocated more than it's minimum and it
69596 +                     * has enough credits assigned above it's minimum to fullfill our need
69597 +                     * try to take away just enough to fullfill our need */
69598 +                ReduceCredits(pCredInfo,
69599 +                              pCurEpDist,
69600 +                              pCurEpDist->TxCreditsAssigned - need);
69601 +
69602 +                if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) {
69603 +                        /* we have enough */
69604 +                    break;
69605 +                }
69606 +            }
69607 +
69608 +            pCurEpDist = pCurEpDist->pPrev;
69609 +        }
69610 +
69611 +            /* return what we can get */
69612 +        credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
69613 +
69614 +    } while (FALSE);
69615 +
69616 +        /* did we find some credits? */
69617 +    if (credits) {
69618 +            /* give what we can */
69619 +        GiveCredits(pCredInfo, pEPDist, credits);
69620 +    }
69621 +
69622 +}
69623 +
69624 +/* initialize and setup credit distribution */
69625 +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo)
69626 +{
69627 +    HTC_SERVICE_ID servicepriority[5];
69628 +
69629 +    A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO));
69630 +
69631 +    servicepriority[0] = WMI_CONTROL_SVC;  /* highest */
69632 +    servicepriority[1] = WMI_DATA_VO_SVC;
69633 +    servicepriority[2] = WMI_DATA_VI_SVC;
69634 +    servicepriority[3] = WMI_DATA_BE_SVC;
69635 +    servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */
69636 +
69637 +        /* set callbacks and priority list */
69638 +    HTCSetCreditDistribution(HTCHandle,
69639 +                             pCredInfo,
69640 +                             ar6000_credit_distribute,
69641 +                             ar6000_credit_init,
69642 +                             servicepriority,
69643 +                             5);
69644 +
69645 +    return A_OK;
69646 +}
69647 +
69648 --- /dev/null
69649 +++ b/drivers/ar6000/wlan/wlan_node.c
69650 @@ -0,0 +1,371 @@
69651 +/*-
69652 + * Copyright (c) 2001 Atsushi Onoe
69653 + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
69654 + * Copyright (c) 2004-2005 Atheros Communications
69655 + * All rights reserved.
69656 + *
69657 + * Redistribution and use in source and binary forms, with or without
69658 + * modification, are permitted provided that the following conditions
69659 + * are met:
69660 + * 1. Redistributions of source code must retain the above copyright
69661 + *    notice, this list of conditions and the following disclaimer.
69662 + * 2. Redistributions in binary form must reproduce the above copyright
69663 + *    notice, this list of conditions and the following disclaimer in the
69664 + *    documentation and/or other materials provided with the distribution.
69665 + * 3. The name of the author may not be used to endorse or promote products
69666 + *    derived from this software without specific prior written permission.
69667 + *
69668 + * Alternatively, this software may be distributed under the terms of the
69669 + * GNU General Public License ("GPL") version 2 as published by the Free
69670 + * Software Foundation.
69671 + *
69672 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
69673 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
69674 + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
69675 + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
69676 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
69677 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
69678 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
69679 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
69680 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
69681 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
69682 + *
69683 + * $Id: //depot/sw/releases/olca2.0-GPL/host/wlan/src/wlan_node.c#1 $
69684 + */
69685 +/*
69686 + * IEEE 802.11 node handling support.
69687 + */
69688 +#include <a_config.h>
69689 +#include <athdefs.h>
69690 +#include <a_types.h>
69691 +#include <a_osapi.h>
69692 +#include <a_debug.h>
69693 +#include <ieee80211.h>
69694 +#include <wlan_api.h>
69695 +#include <ieee80211_node.h>
69696 +#include <htc_api.h>
69697 +#include <wmi.h>
69698 +#include <wmi_api.h>
69699 +
69700 +static void wlan_node_timeout(A_ATH_TIMER arg);
69701 +static bss_t * _ieee80211_find_node(struct ieee80211_node_table *nt,
69702 +                                    const A_UINT8 *macaddr);
69703 +
69704 +bss_t *
69705 +wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size)
69706 +{
69707 +    bss_t *ni;
69708 +
69709 +    ni = A_MALLOC_NOWAIT(sizeof(bss_t));
69710 +
69711 +    if (ni != NULL) {
69712 +        ni->ni_buf = A_MALLOC_NOWAIT(wh_size);
69713 +        if (ni->ni_buf == NULL) {
69714 +            A_FREE(ni);
69715 +            ni = NULL;
69716 +            return ni;
69717 +        }
69718 +    } else {
69719 +        return ni;
69720 +    }
69721 +
69722 +    /* Make sure our lists are clean */
69723 +    ni->ni_list_next = NULL;
69724 +    ni->ni_list_prev = NULL;
69725 +    ni->ni_hash_next = NULL;
69726 +    ni->ni_hash_prev = NULL;
69727 +
69728 +    //
69729 +    // ni_scangen never initialized before and during suspend/resume of winmobile, customer (LG/SEMCO) identified
69730 +    // that some junk has been stored in this, due to this scan list didn't properly updated
69731 +    //
69732 +    ni->ni_scangen      = 0;
69733 +
69734 +    return ni;
69735 +}
69736 +
69737 +void
69738 +wlan_node_free(bss_t *ni)
69739 +{
69740 +    if (ni->ni_buf != NULL) {
69741 +        A_FREE(ni->ni_buf);
69742 +    }
69743 +    A_FREE(ni);
69744 +}
69745 +
69746 +void
69747 +wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
69748 +                const A_UINT8 *macaddr)
69749 +{
69750 +    int hash;
69751 +
69752 +    A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN);
69753 +    hash = IEEE80211_NODE_HASH(macaddr);
69754 +    ieee80211_node_initref(ni);     /* mark referenced */
69755 +
69756 +    ni->ni_tstamp = A_GET_MS(WLAN_NODE_INACT_TIMEOUT_MSEC);
69757 +    IEEE80211_NODE_LOCK_BH(nt);
69758 +
69759 +    /* Insert at the end of the node list */
69760 +    ni->ni_list_next = NULL;
69761 +    ni->ni_list_prev = nt->nt_node_last;
69762 +    if(nt->nt_node_last != NULL)
69763 +    {
69764 +        nt->nt_node_last->ni_list_next = ni;
69765 +    }
69766 +    nt->nt_node_last = ni;
69767 +    if(nt->nt_node_first == NULL)
69768 +    {
69769 +        nt->nt_node_first = ni;
69770 +    }
69771 +
69772 +    /* Insert into the hash list i.e. the bucket */
69773 +    if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL)
69774 +    {
69775 +        nt->nt_hash[hash]->ni_hash_prev = ni;
69776 +    }
69777 +    ni->ni_hash_prev = NULL;
69778 +    nt->nt_hash[hash] = ni;
69779 +
69780 +    if (!nt->isTimerArmed) {
69781 +        A_TIMEOUT_MS(&nt->nt_inact_timer, WLAN_NODE_INACT_TIMEOUT_MSEC, 0);
69782 +        nt->isTimerArmed = TRUE;
69783 +    }
69784 +
69785 +    IEEE80211_NODE_UNLOCK_BH(nt);
69786 +}
69787 +
69788 +static bss_t *
69789 +_ieee80211_find_node(struct ieee80211_node_table *nt,
69790 +    const A_UINT8 *macaddr)
69791 +{
69792 +    bss_t *ni;
69793 +    int hash;
69794 +
69795 +    IEEE80211_NODE_LOCK_ASSERT(nt);
69796 +
69797 +    hash = IEEE80211_NODE_HASH(macaddr);
69798 +    for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) {
69799 +        if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) {
69800 +            ieee80211_node_incref(ni);  /* mark referenced */
69801 +            return ni;
69802 +        }
69803 +    }
69804 +    return NULL;
69805 +}
69806 +
69807 +bss_t *
69808 +wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr)
69809 +{
69810 +    bss_t *ni;
69811 +
69812 +    IEEE80211_NODE_LOCK(nt);
69813 +    ni = _ieee80211_find_node(nt, macaddr);
69814 +    IEEE80211_NODE_UNLOCK(nt);
69815 +    return ni;
69816 +}
69817 +
69818 +/*
69819 + * Reclaim a node.  If this is the last reference count then
69820 + * do the normal free work.  Otherwise remove it from the node
69821 + * table and mark it gone by clearing the back-reference.
69822 + */
69823 +void
69824 +wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni)
69825 +{
69826 +    IEEE80211_NODE_LOCK(nt);
69827 +
69828 +    if(ni->ni_list_prev == NULL)
69829 +    {
69830 +        /* First in list so fix the list head */
69831 +        nt->nt_node_first = ni->ni_list_next;
69832 +    }
69833 +    else
69834 +    {
69835 +        ni->ni_list_prev->ni_list_next = ni->ni_list_next;
69836 +    }
69837 +
69838 +    if(ni->ni_list_next == NULL)
69839 +    {
69840 +        /* Last in list so fix list tail */
69841 +        nt->nt_node_last = ni->ni_list_prev;
69842 +    }
69843 +    else
69844 +    {
69845 +        ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
69846 +    }
69847 +
69848 +    if(ni->ni_hash_prev == NULL)
69849 +    {
69850 +        /* First in list so fix the list head */
69851 +        int hash;
69852 +        hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
69853 +        nt->nt_hash[hash] = ni->ni_hash_next;
69854 +    }
69855 +    else
69856 +    {
69857 +        ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
69858 +    }
69859 +
69860 +    if(ni->ni_hash_next != NULL)
69861 +    {
69862 +        ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
69863 +    }
69864 +    wlan_node_free(ni);
69865 +
69866 +    IEEE80211_NODE_UNLOCK(nt);
69867 +}
69868 +
69869 +static void
69870 +wlan_node_dec_free(bss_t *ni)
69871 +{
69872 +    if (ieee80211_node_dectestref(ni)) {
69873 +        wlan_node_free(ni);
69874 +    }
69875 +}
69876 +
69877 +void
69878 +wlan_free_allnodes(struct ieee80211_node_table *nt)
69879 +{
69880 +    bss_t *ni;
69881 +
69882 +    while ((ni = nt->nt_node_first) != NULL) {
69883 +        wlan_node_reclaim(nt, ni);
69884 +    }
69885 +}
69886 +
69887 +void
69888 +wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
69889 +                   void *arg)
69890 +{
69891 +    bss_t *ni;
69892 +    A_UINT32 gen;
69893 +
69894 +    gen = ++nt->nt_scangen;
69895 +
69896 +    IEEE80211_NODE_LOCK(nt);
69897 +    for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
69898 +        if (ni->ni_scangen != gen) {
69899 +            ni->ni_scangen = gen;
69900 +            (void) ieee80211_node_incref(ni);
69901 +            (*f)(arg, ni);
69902 +            wlan_node_dec_free(ni);
69903 +        }
69904 +    }
69905 +    IEEE80211_NODE_UNLOCK(nt);
69906 +}
69907 +
69908 +/*
69909 + * Node table support.
69910 + */
69911 +void
69912 +wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt)
69913 +{
69914 +    int i;
69915 +
69916 +    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%x\n", (A_UINT32)nt));
69917 +    IEEE80211_NODE_LOCK_INIT(nt);
69918 +
69919 +    nt->nt_node_first = nt->nt_node_last = NULL;
69920 +    for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++)
69921 +    {
69922 +        nt->nt_hash[i] = NULL;
69923 +    }
69924 +    A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt);
69925 +    nt->isTimerArmed = FALSE;
69926 +    nt->nt_wmip = wmip;
69927 +}
69928 +
69929 +static void
69930 +wlan_node_timeout(A_ATH_TIMER arg)
69931 +{
69932 +    struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg;
69933 +    bss_t *bss, *nextBss;
69934 +    A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE;
69935 +
69936 +    wmi_get_current_bssid(nt->nt_wmip, myBssid);
69937 +
69938 +    bss = nt->nt_node_first;
69939 +    while (bss != NULL)
69940 +    {
69941 +        nextBss = bss->ni_list_next;
69942 +        if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0)
69943 +        {
69944 +
69945 +            if (bss->ni_tstamp <= A_GET_MS(0))
69946 +            {
69947 +               /*
69948 +                * free up all but the current bss - if set
69949 +                */
69950 +                wlan_node_reclaim(nt, bss);
69951 +            }
69952 +            else
69953 +            {
69954 +                /*
69955 +                 * Re-arm timer, only when we have a bss other than
69956 +                 * current bss AND it is not aged-out.
69957 +                 */
69958 +                reArmTimer = TRUE;
69959 +            }
69960 +        }
69961 +        bss = nextBss;
69962 +    }
69963 +
69964 +    if(reArmTimer)
69965 +        A_TIMEOUT_MS(&nt->nt_inact_timer, WLAN_NODE_INACT_TIMEOUT_MSEC, 0);
69966 +
69967 +    nt->isTimerArmed = reArmTimer;
69968 +}
69969 +
69970 +void
69971 +wlan_node_table_cleanup(struct ieee80211_node_table *nt)
69972 +{
69973 +    A_UNTIMEOUT(&nt->nt_inact_timer);
69974 +    A_DELETE_TIMER(&nt->nt_inact_timer);
69975 +    wlan_free_allnodes(nt);
69976 +    IEEE80211_NODE_LOCK_DESTROY(nt);
69977 +}
69978 +
69979 +bss_t *
69980 +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
69981 +                                       A_UINT32 ssidLength, A_BOOL bIsWPA2)
69982 +{
69983 +    bss_t   *ni = NULL;
69984 +       A_UCHAR *pIESsid = NULL;
69985 +
69986 +    IEEE80211_NODE_LOCK (nt);
69987 +
69988 +    for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
69989 +               pIESsid = ni->ni_cie.ie_ssid;
69990 +               if (pIESsid[1] <= 32) {
69991 +
69992 +                       // Step 1 : Check SSID
69993 +                       if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) {
69994 +
69995 +                               // Step 2 : if SSID matches, check WPA or WPA2
69996 +                               if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) {
69997 +                                       ieee80211_node_incref (ni);  /* mark referenced */
69998 +                                       IEEE80211_NODE_UNLOCK (nt);
69999 +                                       return ni;
70000 +                               }
70001 +                               if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) {
70002 +                                       ieee80211_node_incref(ni);  /* mark referenced */
70003 +                                       IEEE80211_NODE_UNLOCK (nt);
70004 +                                       return ni;
70005 +                               }
70006 +                       }
70007 +               }
70008 +    }
70009 +
70010 +    IEEE80211_NODE_UNLOCK (nt);
70011 +
70012 +    return NULL;
70013 +}
70014 +
70015 +void
70016 +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni)
70017 +{
70018 +       IEEE80211_NODE_LOCK (nt);
70019 +       wlan_node_dec_free (ni);
70020 +       IEEE80211_NODE_UNLOCK (nt);
70021 +}
70022 --- /dev/null
70023 +++ b/drivers/ar6000/wlan/wlan_recv_beacon.c
70024 @@ -0,0 +1,192 @@
70025 +/*-
70026 + * Copyright (c) 2001 Atsushi Onoe
70027 + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
70028 + * All rights reserved.
70029 + *
70030 + * Redistribution and use in source and binary forms, with or without
70031 + * modification, are permitted provided that the following conditions
70032 + * are met:
70033 + * 1. Redistributions of source code must retain the above copyright
70034 + *    notice, this list of conditions and the following disclaimer.
70035 + * 2. Redistributions in binary form must reproduce the above copyright
70036 + *    notice, this list of conditions and the following disclaimer in the
70037 + *    documentation and/or other materials provided with the distribution.
70038 + * 3. The name of the author may not be used to endorse or promote products
70039 + *    derived from this software without specific prior written permission.
70040 + *
70041 + * Alternatively, this software may be distributed under the terms of the
70042 + * GNU General Public License ("GPL") version 2 as published by the Free
70043 + * Software Foundation.
70044 + *
70045 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
70046 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
70047 + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
70048 + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
70049 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
70050 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
70051 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
70052 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
70053 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
70054 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
70055 + */
70056 +/*
70057 + * IEEE 802.11 input handling.
70058 + */
70059 +
70060 +#include "a_config.h"
70061 +#include "athdefs.h"
70062 +#include "a_types.h"
70063 +#include "a_osapi.h"
70064 +#include <wmi.h>
70065 +#include <ieee80211.h>
70066 +#include <wlan_api.h>
70067 +
70068 +#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do {         \
70069 +    if ((_len) < (_minlen)) {                   \
70070 +        return A_EINVAL;                         \
70071 +    }                               \
70072 +} while (0)
70073 +
70074 +#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do {         \
70075 +    if ((__elem) == NULL) {                     \
70076 +        return A_EINVAL;                         \
70077 +    }                               \
70078 +    if ((__elem)[1] > (__maxlen)) {                 \
70079 +        return A_EINVAL;                         \
70080 +    }                               \
70081 +} while (0)
70082 +
70083 +
70084 +/* unaligned little endian access */
70085 +#define LE_READ_2(p)                            \
70086 +    ((A_UINT16)                            \
70087 +     ((((A_UINT8 *)(p))[0]      ) | (((A_UINT8 *)(p))[1] <<  8)))
70088 +
70089 +#define LE_READ_4(p)                            \
70090 +    ((A_UINT32)                            \
70091 +     ((((A_UINT8 *)(p))[0]      ) | (((A_UINT8 *)(p))[1] <<  8) | \
70092 +      (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
70093 +
70094 +
70095 +static int __inline
70096 +iswpaoui(const A_UINT8 *frm)
70097 +{
70098 +    return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI);
70099 +}
70100 +
70101 +static int __inline
70102 +iswmmoui(const A_UINT8 *frm)
70103 +{
70104 +    return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI);
70105 +}
70106 +
70107 +static int __inline
70108 +iswmmparam(const A_UINT8 *frm)
70109 +{
70110 +    return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
70111 +}
70112 +
70113 +static int __inline
70114 +iswmminfo(const A_UINT8 *frm)
70115 +{
70116 +    return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE;
70117 +}
70118 +
70119 +static int __inline
70120 +isatherosoui(const A_UINT8 *frm)
70121 +{
70122 +    return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI);
70123 +}
70124 +
70125 +static int __inline
70126 +iswscoui(const A_UINT8 *frm)
70127 +{
70128 +    return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI);
70129 +}
70130 +
70131 +A_STATUS
70132 +wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie)
70133 +{
70134 +    A_UINT8 *frm, *efrm;
70135 +
70136 +    frm = buf;
70137 +    efrm = (A_UINT8 *) (frm + framelen);
70138 +
70139 +    /*
70140 +     * beacon/probe response frame format
70141 +     *  [8] time stamp
70142 +     *  [2] beacon interval
70143 +     *  [2] capability information
70144 +     *  [tlv] ssid
70145 +     *  [tlv] supported rates
70146 +     *  [tlv] country information
70147 +     *  [tlv] parameter set (FH/DS)
70148 +     *  [tlv] erp information
70149 +     *  [tlv] extended supported rates
70150 +     *  [tlv] WMM
70151 +     *  [tlv] WPA or RSN
70152 +     *  [tlv] Atheros Advanced Capabilities
70153 +     */
70154 +    IEEE80211_VERIFY_LENGTH(efrm - frm, 12);
70155 +    A_MEMZERO(cie, sizeof(*cie));
70156 +
70157 +    cie->ie_tstamp = frm; frm += 8;
70158 +    cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm);  frm += 2;
70159 +    cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm);  frm += 2;
70160 +    cie->ie_chan = 0;
70161 +
70162 +    while (frm < efrm) {
70163 +        switch (*frm) {
70164 +        case IEEE80211_ELEMID_SSID:
70165 +            cie->ie_ssid = frm;
70166 +            break;
70167 +        case IEEE80211_ELEMID_RATES:
70168 +            cie->ie_rates = frm;
70169 +            break;
70170 +        case IEEE80211_ELEMID_COUNTRY:
70171 +            cie->ie_country = frm;
70172 +            break;
70173 +        case IEEE80211_ELEMID_FHPARMS:
70174 +            break;
70175 +        case IEEE80211_ELEMID_DSPARMS:
70176 +            cie->ie_chan = frm[2];
70177 +            break;
70178 +        case IEEE80211_ELEMID_TIM:
70179 +            cie->ie_tim = frm;
70180 +            break;
70181 +        case IEEE80211_ELEMID_IBSSPARMS:
70182 +            break;
70183 +        case IEEE80211_ELEMID_XRATES:
70184 +            cie->ie_xrates = frm;
70185 +            break;
70186 +        case IEEE80211_ELEMID_ERP:
70187 +            if (frm[1] != 1) {
70188 +                //A_PRINTF("Discarding ERP Element - Bad Len\n");
70189 +                return A_EINVAL;
70190 +            }
70191 +            cie->ie_erp = frm[2];
70192 +            break;
70193 +        case IEEE80211_ELEMID_RSN:
70194 +            cie->ie_rsn = frm;
70195 +            break;
70196 +        case IEEE80211_ELEMID_VENDOR:
70197 +            if (iswpaoui(frm)) {
70198 +                cie->ie_wpa = frm;
70199 +            } else if (iswmmoui(frm)) {
70200 +                cie->ie_wmm = frm;
70201 +            } else if (isatherosoui(frm)) {
70202 +                cie->ie_ath = frm;
70203 +            } else if(iswscoui(frm)) {
70204 +                cie->ie_wsc = frm;
70205 +            }
70206 +            break;
70207 +        default:
70208 +            break;
70209 +        }
70210 +        frm += frm[1] + 2;
70211 +    }
70212 +    IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE);
70213 +    IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN);
70214 +
70215 +    return A_OK;
70216 +}
70217 --- /dev/null
70218 +++ b/drivers/ar6000/wlan/wlan_utils.c
70219 @@ -0,0 +1,59 @@
70220 +/*
70221 + * Copyright (c) 2004-2005 Atheros Communications Inc.
70222 + * All rights reserved.
70223 + *
70224 + * This module implements frequently used wlan utilies
70225 + *
70226 + * $Id: //depot/sw/releases/olca2.0-GPL/host/wlan/src/wlan_utils.c#1 $
70227 + *
70228 + *
70229 + *  This program is free software; you can redistribute it and/or modify
70230 + *  it under the terms of the GNU General Public License version 2 as
70231 + *  published by the Free Software Foundation;
70232 + *
70233 + *  Software distributed under the License is distributed on an "AS
70234 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
70235 + *  implied. See the License for the specific language governing
70236 + *  rights and limitations under the License.
70237 + *
70238 + *
70239 + *
70240 + */
70241 +
70242 +#include <a_config.h>
70243 +#include <athdefs.h>
70244 +#include <a_types.h>
70245 +#include <a_osapi.h>
70246 +
70247 +/*
70248 + * converts ieee channel number to frequency
70249 + */
70250 +A_UINT16
70251 +wlan_ieee2freq(int chan)
70252 +{
70253 +    if (chan == 14) {
70254 +        return 2484;
70255 +    }
70256 +    if (chan < 14) {    /* 0-13 */
70257 +        return (2407 + (chan*5));
70258 +    }
70259 +    if (chan < 27) {    /* 15-26 */
70260 +        return (2512 + ((chan-15)*20));
70261 +    }
70262 +    return (5000 + (chan*5));
70263 +}
70264 +
70265 +/*
70266 + * Converts MHz frequency to IEEE channel number.
70267 + */
70268 +A_UINT32
70269 +wlan_freq2ieee(A_UINT16 freq)
70270 +{
70271 +    if (freq == 2484)
70272 +        return 14;
70273 +    if (freq < 2484)
70274 +        return (freq - 2407) / 5;
70275 +    if (freq < 5000)
70276 +        return 15 + ((freq - 2512) / 20);
70277 +    return (freq - 5000) / 5;
70278 +}
70279 --- /dev/null
70280 +++ b/drivers/ar6000/wmi/wmi.c
70281 @@ -0,0 +1,3954 @@
70282 +/*
70283 + * Copyright (c) 2004-2007 Atheros Communications Inc.
70284 + * All rights reserved.
70285 + *
70286 + * This module implements the hardware independent layer of the
70287 + * Wireless Module Interface (WMI) protocol.
70288 + *
70289 + * $Id: //depot/sw/releases/olca2.0-GPL/host/wmi/wmi.c#3 $
70290 + *
70291 + *
70292 + *  This program is free software; you can redistribute it and/or modify
70293 + *  it under the terms of the GNU General Public License version 2 as
70294 + *  published by the Free Software Foundation;
70295 + *
70296 + *  Software distributed under the License is distributed on an "AS
70297 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
70298 + *  implied. See the License for the specific language governing
70299 + *  rights and limitations under the License.
70300 + *
70301 + *
70302 + *
70303 + */
70304 +
70305 +#include <a_config.h>
70306 +#include <athdefs.h>
70307 +#include <a_types.h>
70308 +#include <a_osapi.h>
70309 +#include "htc.h"
70310 +#include "htc_api.h"
70311 +#include "wmi.h"
70312 +#include <ieee80211.h>
70313 +#include <ieee80211_node.h>
70314 +#include <wlan_api.h>
70315 +#include <wmi_api.h>
70316 +#include "dset_api.h"
70317 +#include "gpio_api.h"
70318 +#include "wmi_host.h"
70319 +#include "a_drv.h"
70320 +#include "a_drv_api.h"
70321 +#include "a_debug.h"
70322 +#include "dbglog_api.h"
70323 +
70324 +static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70325 +
70326 +static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70327 +                                     int len);
70328 +static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70329 +                                        int len);
70330 +static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70331 +                                        int len);
70332 +static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70333 +                                     int len);
70334 +static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70335 +                                       int len);
70336 +static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70337 +                                     int len);
70338 +static A_STATUS wmi_sync_point(struct wmi_t *wmip);
70339 +
70340 +static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
70341 +                                     int len);
70342 +static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
70343 +                                     int len);
70344 +static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
70345 +                                         int len);
70346 +static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70347 +                                       int len);
70348 +static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70349 +static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70350 +                                             int len);
70351 +
70352 +static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
70353 +                                     int len);
70354 +#ifdef CONFIG_HOST_DSET_SUPPORT
70355 +static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70356 +static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
70357 +                                     int len);
70358 +#endif /* CONFIG_HOST_DSET_SUPPORT */
70359 +
70360 +
70361 +static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap,
70362 +                                     int len);
70363 +static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70364 +static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70365 +static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70366 +static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70367 +static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70368 +static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70369 +static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70370 +                                      int len);
70371 +static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70372 +                                      int len);
70373 +static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
70374 +                                      int len);
70375 +static A_STATUS
70376 +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len);
70377 +
70378 +#ifdef CONFIG_HOST_GPIO_SUPPORT
70379 +static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70380 +static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70381 +static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70382 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
70383 +
70384 +#ifdef CONFIG_HOST_TCMD_SUPPORT
70385 +static A_STATUS
70386 +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70387 +#endif
70388 +
70389 +static A_STATUS
70390 +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70391 +
70392 +static A_STATUS
70393 +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70394 +
70395 +static A_STATUS
70396 +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70397 +
70398 +static A_BOOL
70399 +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_UINT32 rateIndex);
70400 +
70401 +static A_STATUS
70402 +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70403 +
70404 +static A_STATUS
70405 +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70406 +
70407 +static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
70408 +
70409 +int wps_enable;
70410 +static const A_INT32 wmi_rateTable[] = {
70411 +    1000,
70412 +    2000,
70413 +    5500,
70414 +    11000,
70415 +    6000,
70416 +    9000,
70417 +    12000,
70418 +    18000,
70419 +    24000,
70420 +    36000,
70421 +    48000,
70422 +    54000,
70423 +    0};
70424 +
70425 +#define MODE_A_SUPPORT_RATE_START       4
70426 +#define MODE_A_SUPPORT_RATE_STOP        11
70427 +
70428 +#define MODE_GONLY_SUPPORT_RATE_START   MODE_A_SUPPORT_RATE_START
70429 +#define MODE_GONLY_SUPPORT_RATE_STOP    MODE_A_SUPPORT_RATE_STOP
70430 +
70431 +#define MODE_B_SUPPORT_RATE_START       0
70432 +#define MODE_B_SUPPORT_RATE_STOP        3
70433 +
70434 +#define MODE_G_SUPPORT_RATE_START       0
70435 +#define MODE_G_SUPPORT_RATE_STOP        11
70436 +
70437 +#define MAX_NUMBER_OF_SUPPORT_RATES     (MODE_G_SUPPORT_RATE_STOP + 1)
70438 +
70439 +/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */
70440 +const A_UINT8 up_to_ac[]= {
70441 +                WMM_AC_BE,
70442 +                WMM_AC_BK,
70443 +                WMM_AC_BK,
70444 +                WMM_AC_BE,
70445 +                WMM_AC_VI,
70446 +                WMM_AC_VI,
70447 +                WMM_AC_VO,
70448 +                WMM_AC_VO,
70449 +            };
70450 +
70451 +void *
70452 +wmi_init(void *devt)
70453 +{
70454 +    struct wmi_t *wmip;
70455 +
70456 +    wmip = A_MALLOC(sizeof(struct wmi_t));
70457 +    if (wmip == NULL) {
70458 +        return (NULL);
70459 +    }
70460 +    A_MEMZERO(wmip, sizeof(*wmip));
70461 +    A_MUTEX_INIT(&wmip->wmi_lock);
70462 +    wmip->wmi_devt = devt;
70463 +    wlan_node_table_init(wmip, &wmip->wmi_scan_table);
70464 +    wmi_qos_state_init(wmip);
70465 +    wmip->wmi_powerMode = REC_POWER;
70466 +    wmip->wmi_phyMode = WMI_11G_MODE;
70467 +
70468 +    return (wmip);
70469 +}
70470 +
70471 +void
70472 +wmi_qos_state_init(struct wmi_t *wmip)
70473 +{
70474 +    A_UINT8 i;
70475 +
70476 +    if (wmip == NULL) {
70477 +        return;
70478 +    }
70479 +    LOCK_WMI(wmip);
70480 +
70481 +    /* Initialize QoS States */
70482 +    wmip->wmi_numQoSStream = 0;
70483 +
70484 +    wmip->wmi_fatPipeExists = 0;
70485 +
70486 +    for (i=0; i < WMM_NUM_AC; i++) {
70487 +        wmip->wmi_streamExistsForAC[i]=0;
70488 +    }
70489 +
70490 +        /* Initialize the static Wmi stream Pri to WMM AC mappings Arrays */
70491 +    WMI_INIT_WMISTREAM_AC_MAP(wmip);
70492 +
70493 +    UNLOCK_WMI(wmip);
70494 +
70495 +    A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1);
70496 +}
70497 +
70498 +void
70499 +wmi_shutdown(struct wmi_t *wmip)
70500 +{
70501 +    if (wmip != NULL) {
70502 +        wlan_node_table_cleanup(&wmip->wmi_scan_table);
70503 +        if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) {
70504 +            A_MUTEX_DELETE(&wmip->wmi_lock);
70505 +        }
70506 +        A_FREE(wmip);
70507 +    }
70508 +}
70509 +
70510 +/*
70511 + *  performs DIX to 802.3 encapsulation for transmit packets.
70512 + *  uses passed in buffer.  Returns buffer or NULL if failed.
70513 + *  Assumes the entire DIX header is contigous and that there is
70514 + *  enough room in the buffer for a 802.3 mac header and LLC+SNAP headers.
70515 + */
70516 +A_STATUS
70517 +wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf)
70518 +{
70519 +    A_UINT8          *datap;
70520 +    A_UINT16         typeorlen;
70521 +    ATH_MAC_HDR      macHdr;
70522 +    ATH_LLC_SNAP_HDR *llcHdr;
70523 +
70524 +    A_ASSERT(osbuf != NULL);
70525 +
70526 +    if (A_NETBUF_HEADROOM(osbuf) <
70527 +        (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR)))
70528 +    {
70529 +        return A_NO_MEMORY;
70530 +    }
70531 +
70532 +    datap = A_NETBUF_DATA(osbuf);
70533 +
70534 +    typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN);
70535 +
70536 +    if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
70537 +        /*
70538 +         * packet is already in 802.3 format - return success
70539 +         */
70540 +        A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG));
70541 +        return (A_OK);
70542 +    }
70543 +
70544 +    /*
70545 +     * Save mac fields and length to be inserted later
70546 +     */
70547 +    A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
70548 +    A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
70549 +    macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) +
70550 +                                  sizeof(ATH_LLC_SNAP_HDR));
70551 +
70552 +    /*
70553 +     * Make room for LLC+SNAP headers
70554 +     */
70555 +    if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
70556 +        return A_NO_MEMORY;
70557 +    }
70558 +
70559 +    datap = A_NETBUF_DATA(osbuf);
70560 +
70561 +    A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
70562 +
70563 +    llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
70564 +    llcHdr->dsap      = 0xAA;
70565 +    llcHdr->ssap      = 0xAA;
70566 +    llcHdr->cntl      = 0x03;
70567 +    llcHdr->orgCode[0] = 0x0;
70568 +    llcHdr->orgCode[1] = 0x0;
70569 +    llcHdr->orgCode[2] = 0x0;
70570 +    llcHdr->etherType = typeorlen;
70571 +
70572 +    return (A_OK);
70573 +}
70574 +
70575 +/*
70576 + * Adds a WMI data header
70577 + * Assumes there is enough room in the buffer to add header.
70578 + */
70579 +A_STATUS
70580 +wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType)
70581 +{
70582 +    WMI_DATA_HDR     *dtHdr;
70583 +
70584 +    A_ASSERT(osbuf != NULL);
70585 +
70586 +    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
70587 +        return A_NO_MEMORY;
70588 +    }
70589 +
70590 +    dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
70591 +    dtHdr->info = msgType;
70592 +    dtHdr->rssi = 0;
70593 +
70594 +    return (A_OK);
70595 +}
70596 +
70597 +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT8 dir, A_UINT8 up)
70598 +{
70599 +    A_UINT8         *datap;
70600 +    A_UINT8         trafficClass = WMM_AC_BE, userPriority = up;
70601 +    ATH_LLC_SNAP_HDR *llcHdr;
70602 +    A_UINT16        ipType = IP_ETHERTYPE;
70603 +    WMI_DATA_HDR     *dtHdr;
70604 +    WMI_CREATE_PSTREAM_CMD  cmd;
70605 +    A_BOOL           streamExists = FALSE;
70606 +
70607 +    A_ASSERT(osbuf != NULL);
70608 +
70609 +    datap = A_NETBUF_DATA(osbuf);
70610 +
70611 +    if (up == UNDEFINED_PRI) {
70612 +    llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) +
70613 +                                  sizeof(ATH_MAC_HDR));
70614 +
70615 +        if (llcHdr->etherType == A_CPU2BE16(ipType)) {
70616 +        /* Extract the endpoint info from the TOS field in the IP header */
70617 +        userPriority = A_WMI_IPTOS_TO_USERPRIORITY(((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR));
70618 +        }
70619 +    }
70620 +
70621 +    if (userPriority < MAX_NUM_PRI) {
70622 +        trafficClass = convert_userPriority_to_trafficClass(userPriority);
70623 +    }
70624 +
70625 +    dtHdr = (WMI_DATA_HDR *)datap;
70626 +    if(dir==UPLINK_TRAFFIC)
70627 +        dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT;  /* lower 3-bits are 802.1d priority */
70628 +
70629 +    LOCK_WMI(wmip);
70630 +    streamExists = wmip->wmi_fatPipeExists;
70631 +    UNLOCK_WMI(wmip);
70632 +
70633 +    if (!(streamExists & (1 << trafficClass))) {
70634 +
70635 +        A_MEMZERO(&cmd, sizeof(cmd));
70636 +           cmd.trafficClass = trafficClass;
70637 +           cmd.userPriority = userPriority;
70638 +               cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT;
70639 +            /* Implicit streams are created with TSID 0xFF */
70640 +        cmd.tsid = WMI_IMPLICIT_PSTREAM;
70641 +        wmi_create_pstream_cmd(wmip, &cmd);
70642 +    }
70643 +
70644 +    return trafficClass;
70645 +}
70646 +
70647 +WMI_PRI_STREAM_ID
70648 +wmi_get_stream_id(struct wmi_t *wmip, A_UINT8 trafficClass)
70649 +{
70650 +    return WMI_ACCESSCATEGORY_WMISTREAM(wmip, trafficClass);
70651 +}
70652 +
70653 +/*
70654 + *  performs 802.3 to DIX encapsulation for received packets.
70655 + *  Assumes the entire 802.3 header is contigous.
70656 + */
70657 +A_STATUS
70658 +wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf)
70659 +{
70660 +    A_UINT8          *datap;
70661 +    ATH_MAC_HDR      macHdr;
70662 +    ATH_LLC_SNAP_HDR *llcHdr;
70663 +
70664 +    A_ASSERT(osbuf != NULL);
70665 +    datap = A_NETBUF_DATA(osbuf);
70666 +
70667 +    A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR));
70668 +    llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
70669 +    macHdr.typeOrLen = llcHdr->etherType;
70670 +
70671 +    if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
70672 +        return A_NO_MEMORY;
70673 +    }
70674 +
70675 +    datap = A_NETBUF_DATA(osbuf);
70676 +
70677 +    A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
70678 +
70679 +    return (A_OK);
70680 +}
70681 +
70682 +/*
70683 + * Removes a WMI data header
70684 + */
70685 +A_STATUS
70686 +wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf)
70687 +{
70688 +    A_ASSERT(osbuf != NULL);
70689 +
70690 +    return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR)));
70691 +}
70692 +
70693 +void
70694 +wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg)
70695 +{
70696 +    wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg);
70697 +}
70698 +
70699 +/*
70700 + * WMI Extended Event received from Target.
70701 + */
70702 +A_STATUS
70703 +wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf)
70704 +{
70705 +    WMIX_CMD_HDR *cmd;
70706 +    A_UINT16 id;
70707 +    A_UINT8 *datap;
70708 +    A_UINT32 len;
70709 +    A_STATUS status = A_OK;
70710 +
70711 +    if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) {
70712 +        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
70713 +        wmip->wmi_stats.cmd_len_err++;
70714 +        A_NETBUF_FREE(osbuf);
70715 +        return A_ERROR;
70716 +    }
70717 +
70718 +    cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
70719 +    id = cmd->commandId;
70720 +
70721 +    if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
70722 +        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
70723 +        wmip->wmi_stats.cmd_len_err++;
70724 +        A_NETBUF_FREE(osbuf);
70725 +        return A_ERROR;
70726 +    }
70727 +
70728 +    datap = A_NETBUF_DATA(osbuf);
70729 +    len = A_NETBUF_LEN(osbuf);
70730 +
70731 +    switch (id) {
70732 +    case (WMIX_DSETOPENREQ_EVENTID):
70733 +        status = wmi_dset_open_req_rx(wmip, datap, len);
70734 +        break;
70735 +#ifdef CONFIG_HOST_DSET_SUPPORT
70736 +    case (WMIX_DSETCLOSE_EVENTID):
70737 +        status = wmi_dset_close_rx(wmip, datap, len);
70738 +        break;
70739 +    case (WMIX_DSETDATAREQ_EVENTID):
70740 +        status = wmi_dset_data_req_rx(wmip, datap, len);
70741 +        break;
70742 +#endif /* CONFIG_HOST_DSET_SUPPORT */
70743 +#ifdef CONFIG_HOST_GPIO_SUPPORT
70744 +    case (WMIX_GPIO_INTR_EVENTID):
70745 +        wmi_gpio_intr_rx(wmip, datap, len);
70746 +        break;
70747 +    case (WMIX_GPIO_DATA_EVENTID):
70748 +        wmi_gpio_data_rx(wmip, datap, len);
70749 +        break;
70750 +    case (WMIX_GPIO_ACK_EVENTID):
70751 +        wmi_gpio_ack_rx(wmip, datap, len);
70752 +        break;
70753 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
70754 +    case (WMIX_HB_CHALLENGE_RESP_EVENTID):
70755 +        wmi_hbChallengeResp_rx(wmip, datap, len);
70756 +        break;
70757 +    case (WMIX_DBGLOG_EVENTID):
70758 +        wmi_dbglog_event_rx(wmip, datap, len);
70759 +        break;
70760 +    default:
70761 +        A_DPRINTF(DBG_WMI|DBG_ERROR,
70762 +            (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
70763 +        wmip->wmi_stats.cmd_id_err++;
70764 +        status = A_ERROR;
70765 +        break;
70766 +    }
70767 +
70768 +    return status;
70769 +}
70770 +
70771 +/*
70772 + * Control Path
70773 + */
70774 +A_UINT32 cmdRecvNum;
70775 +
70776 +A_STATUS
70777 +wmi_control_rx(struct wmi_t *wmip, void *osbuf)
70778 +{
70779 +    WMI_CMD_HDR *cmd;
70780 +    A_UINT16 id;
70781 +    A_UINT8 *datap;
70782 +    A_UINT32 len, i, loggingReq;
70783 +    A_STATUS status = A_OK;
70784 +
70785 +    A_ASSERT(osbuf != NULL);
70786 +    if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) {
70787 +        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
70788 +        wmip->wmi_stats.cmd_len_err++;
70789 +        A_NETBUF_FREE(osbuf);
70790 +        return A_ERROR;
70791 +    }
70792 +
70793 +    cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
70794 +    id = cmd->commandId;
70795 +
70796 +    if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
70797 +        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
70798 +        wmip->wmi_stats.cmd_len_err++;
70799 +        A_NETBUF_FREE(osbuf);
70800 +        return A_ERROR;
70801 +    }
70802 +
70803 +    datap = A_NETBUF_DATA(osbuf);
70804 +    len = A_NETBUF_LEN(osbuf);
70805 +
70806 +    ar6000_get_driver_cfg(wmip->wmi_devt,
70807 +                    AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS,
70808 +                    &loggingReq);
70809 +
70810 +    if(loggingReq) {
70811 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id));
70812 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum));
70813 +        for(i = 0; i < len; i++)
70814 +            AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i]));
70815 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n"));
70816 +    }
70817 +
70818 +    LOCK_WMI(wmip);
70819 +    cmdRecvNum++;
70820 +    UNLOCK_WMI(wmip);
70821 +
70822 +    switch (id) {
70823 +    case (WMI_GET_BITRATE_CMDID):
70824 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG));
70825 +        status = wmi_bitrate_reply_rx(wmip, datap, len);
70826 +        break;
70827 +    case (WMI_GET_CHANNEL_LIST_CMDID):
70828 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG));
70829 +        status = wmi_channelList_reply_rx(wmip, datap, len);
70830 +        break;
70831 +    case (WMI_GET_TX_PWR_CMDID):
70832 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG));
70833 +        status = wmi_txPwr_reply_rx(wmip, datap, len);
70834 +        break;
70835 +    case (WMI_READY_EVENTID):
70836 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG));
70837 +        status = wmi_ready_event_rx(wmip, datap, len);
70838 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
70839 +        A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt);
70840 +        break;
70841 +    case (WMI_CONNECT_EVENTID):
70842 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG));
70843 +        status = wmi_connect_event_rx(wmip, datap, len);
70844 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
70845 +        break;
70846 +    case (WMI_DISCONNECT_EVENTID):
70847 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG));
70848 +        status = wmi_disconnect_event_rx(wmip, datap, len);
70849 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
70850 +        break;
70851 +    case (WMI_TKIP_MICERR_EVENTID):
70852 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG));
70853 +        status = wmi_tkip_micerr_event_rx(wmip, datap, len);
70854 +        break;
70855 +    case (WMI_BSSINFO_EVENTID):
70856 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG));
70857 +        status = wmi_bssInfo_event_rx(wmip, datap, len);
70858 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
70859 +        break;
70860 +    case (WMI_REGDOMAIN_EVENTID):
70861 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG));
70862 +        status = wmi_regDomain_event_rx(wmip, datap, len);
70863 +        break;
70864 +    case (WMI_PSTREAM_TIMEOUT_EVENTID):
70865 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG));
70866 +        status = wmi_pstream_timeout_event_rx(wmip, datap, len);
70867 +            /* pstreams are fatpipe abstractions that get implicitly created.
70868 +             * User apps only deal with thinstreams. creation of a thinstream
70869 +             * by the user or data traffic flow in an AC triggers implicit
70870 +             * pstream creation. Do we need to send this event to App..?
70871 +             * no harm in sending it.
70872 +             */
70873 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
70874 +        break;
70875 +    case (WMI_NEIGHBOR_REPORT_EVENTID):
70876 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG));
70877 +        status = wmi_neighborReport_event_rx(wmip, datap, len);
70878 +        break;
70879 +    case (WMI_SCAN_COMPLETE_EVENTID):
70880 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG));
70881 +        status = wmi_scanComplete_rx(wmip, datap, len);
70882 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
70883 +        break;
70884 +    case (WMI_CMDERROR_EVENTID):
70885 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG));
70886 +        status = wmi_errorEvent_rx(wmip, datap, len);
70887 +        break;
70888 +    case (WMI_REPORT_STATISTICS_EVENTID):
70889 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG));
70890 +        status = wmi_statsEvent_rx(wmip, datap, len);
70891 +        break;
70892 +    case (WMI_RSSI_THRESHOLD_EVENTID):
70893 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG));
70894 +        status = wmi_rssiThresholdEvent_rx(wmip, datap, len);
70895 +        break;
70896 +    case (WMI_ERROR_REPORT_EVENTID):
70897 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG));
70898 +        status = wmi_reportErrorEvent_rx(wmip, datap, len);
70899 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
70900 +        break;
70901 +    case (WMI_OPT_RX_FRAME_EVENTID):
70902 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG));
70903 +        status = wmi_opt_frame_event_rx(wmip, datap, len);
70904 +        break;
70905 +    case (WMI_REPORT_ROAM_TBL_EVENTID):
70906 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG));
70907 +        status = wmi_roam_tbl_event_rx(wmip, datap, len);
70908 +        break;
70909 +    case (WMI_EXTENSION_EVENTID):
70910 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG));
70911 +        status = wmi_control_rx_xtnd(wmip, osbuf);
70912 +        break;
70913 +    case (WMI_CAC_EVENTID):
70914 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG));
70915 +        status = wmi_cac_event_rx(wmip, datap, len);
70916 +        break;
70917 +    case (WMI_REPORT_ROAM_DATA_EVENTID):
70918 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG));
70919 +        status = wmi_roam_data_event_rx(wmip, datap, len);
70920 +        break;
70921 +#ifdef CONFIG_HOST_TCMD_SUPPORT
70922 +    case (WMI_TEST_EVENTID):
70923 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG));
70924 +        status = wmi_tcmd_test_report_rx(wmip, datap, len);
70925 +        break;
70926 +#endif
70927 +    case (WMI_GET_FIXRATES_CMDID):
70928 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG));
70929 +        status = wmi_ratemask_reply_rx(wmip, datap, len);
70930 +        break;
70931 +    case (WMI_TX_RETRY_ERR_EVENTID):
70932 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG));
70933 +        status = wmi_txRetryErrEvent_rx(wmip, datap, len);
70934 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
70935 +        break;
70936 +    case (WMI_SNR_THRESHOLD_EVENTID):
70937 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG));
70938 +        status = wmi_snrThresholdEvent_rx(wmip, datap, len);
70939 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
70940 +        break;
70941 +    case (WMI_LQ_THRESHOLD_EVENTID):
70942 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG));
70943 +        status = wmi_lqThresholdEvent_rx(wmip, datap, len);
70944 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
70945 +        break;
70946 +    case (WMI_APLIST_EVENTID):
70947 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n"));
70948 +        status = wmi_aplistEvent_rx(wmip, datap, len);
70949 +        break;
70950 +    case (WMI_GET_KEEPALIVE_CMDID):
70951 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG));
70952 +        status = wmi_keepalive_reply_rx(wmip, datap, len);
70953 +        break;
70954 +    case (WMI_GET_WOW_LIST_EVENTID):
70955 +        status = wmi_get_wow_list_event_rx(wmip, datap, len);
70956 +        break;
70957 +    case (WMI_GET_PMKID_LIST_EVENTID):
70958 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG));
70959 +        status = wmi_get_pmkid_list_event_rx(wmip, datap, len);
70960 +        break;
70961 +    default:
70962 +        A_DPRINTF(DBG_WMI|DBG_ERROR,
70963 +            (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
70964 +        wmip->wmi_stats.cmd_id_err++;
70965 +        status = A_ERROR;
70966 +        break;
70967 +    }
70968 +
70969 +    A_NETBUF_FREE(osbuf);
70970 +
70971 +    return status;
70972 +}
70973 +
70974 +static A_STATUS
70975 +wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
70976 +{
70977 +    WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap;
70978 +
70979 +    if (len < sizeof(WMI_READY_EVENT)) {
70980 +        return A_EINVAL;
70981 +    }
70982 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
70983 +    wmip->wmi_ready = TRUE;
70984 +    A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability);
70985 +
70986 +    return A_OK;
70987 +}
70988 +
70989 +static A_STATUS
70990 +wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
70991 +{
70992 +    WMI_CONNECT_EVENT *ev;
70993 +
70994 +    if (len < sizeof(WMI_CONNECT_EVENT)) {
70995 +        return A_EINVAL;
70996 +    }
70997 +    ev = (WMI_CONNECT_EVENT *)datap;
70998 +    A_DPRINTF(DBG_WMI,
70999 +        (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
71000 +        DBGARG, ev->channel,
71001 +        ev->bssid[0], ev->bssid[1], ev->bssid[2],
71002 +        ev->bssid[3], ev->bssid[4], ev->bssid[5]));
71003 +
71004 +    A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN);
71005 +
71006 +    A_WMI_CONNECT_EVENT(wmip->wmi_devt, ev->channel, ev->bssid,
71007 +                         ev->listenInterval, ev->beaconInterval,
71008 +                         ev->networkType, ev->beaconIeLen,
71009 +                         ev->assocReqLen, ev->assocRespLen,
71010 +                         ev->assocInfo);
71011 +
71012 +    return A_OK;
71013 +}
71014 +
71015 +static A_STATUS
71016 +wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71017 +{
71018 +    WMI_REG_DOMAIN_EVENT *ev;
71019 +
71020 +    if (len < sizeof(*ev)) {
71021 +        return A_EINVAL;
71022 +    }
71023 +    ev = (WMI_REG_DOMAIN_EVENT *)datap;
71024 +
71025 +    A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain);
71026 +
71027 +    return A_OK;
71028 +}
71029 +
71030 +static A_STATUS
71031 +wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71032 +{
71033 +    WMI_NEIGHBOR_REPORT_EVENT *ev;
71034 +    int numAps;
71035 +
71036 +    if (len < sizeof(*ev)) {
71037 +        return A_EINVAL;
71038 +    }
71039 +    ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap;
71040 +    numAps = ev->numberOfAps;
71041 +
71042 +    if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) {
71043 +        return A_EINVAL;
71044 +    }
71045 +
71046 +    A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor);
71047 +
71048 +    return A_OK;
71049 +}
71050 +
71051 +static A_STATUS
71052 +wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71053 +{
71054 +    WMI_DISCONNECT_EVENT *ev;
71055 +
71056 +    if (len < sizeof(WMI_DISCONNECT_EVENT)) {
71057 +        return A_EINVAL;
71058 +    }
71059 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71060 +
71061 +    ev = (WMI_DISCONNECT_EVENT *)datap;
71062 +
71063 +    A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid));
71064 +
71065 +    A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid,
71066 +                            ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus);
71067 +
71068 +    return A_OK;
71069 +}
71070 +
71071 +static A_STATUS
71072 +wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71073 +{
71074 +    WMI_TKIP_MICERR_EVENT *ev;
71075 +
71076 +    if (len < sizeof(*ev)) {
71077 +        return A_EINVAL;
71078 +    }
71079 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71080 +
71081 +    ev = (WMI_TKIP_MICERR_EVENT *)datap;
71082 +    A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast);
71083 +
71084 +    return A_OK;
71085 +}
71086 +
71087 +static A_STATUS
71088 +wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71089 +{
71090 +    bss_t *bss;
71091 +    WMI_BSS_INFO_HDR *bih;
71092 +    A_UINT8 *buf;
71093 +    A_UINT32 nodeCachingAllowed;
71094 +
71095 +    if (len <= sizeof(WMI_BSS_INFO_HDR)) {
71096 +        return A_EINVAL;
71097 +    }
71098 +
71099 +    A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len);
71100 +    /* What is driver config for wlan node caching? */
71101 +    if(ar6000_get_driver_cfg(wmip->wmi_devt,
71102 +                    AR6000_DRIVER_CFG_GET_WLANNODECACHING,
71103 +                    &nodeCachingAllowed) != A_OK) {
71104 +        return A_EINVAL;
71105 +    }
71106 +
71107 +    if(!nodeCachingAllowed) {
71108 +        return A_OK;
71109 +    }
71110 +
71111 +
71112 +    bih = (WMI_BSS_INFO_HDR *)datap;
71113 +    buf = datap + sizeof(WMI_BSS_INFO_HDR);
71114 +    len -= sizeof(WMI_BSS_INFO_HDR);
71115 +
71116 +    A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, "
71117 +              "bssid \"%02x:%02x:%02x:%02x:%02x:%02x\"\n", DBGARG,
71118 +              bih->channel, (unsigned char) bih->rssi, bih->bssid[0],
71119 +              bih->bssid[1], bih->bssid[2], bih->bssid[3], bih->bssid[4],
71120 +              bih->bssid[5]));
71121 +
71122 +    if(wps_enable && (bih->frameType == PROBERESP_FTYPE) ) {
71123 +           printk("%s() A_OK 2\n", __FUNCTION__);
71124 +               return A_OK;
71125 +    }
71126 +
71127 +    bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
71128 +    if (bss != NULL) {
71129 +        /*
71130 +         * Free up the node.  Not the most efficient process given
71131 +         * we are about to allocate a new node but it is simple and should be
71132 +         * adequate.
71133 +         */
71134 +        wlan_node_reclaim(&wmip->wmi_scan_table, bss);
71135 +    }
71136 +
71137 +    bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
71138 +    if (bss == NULL) {
71139 +        return A_NO_MEMORY;
71140 +    }
71141 +
71142 +    bss->ni_snr        = bih->snr;
71143 +    bss->ni_rssi       = bih->rssi;
71144 +    A_ASSERT(bss->ni_buf != NULL);
71145 +    A_MEMCPY(bss->ni_buf, buf, len);
71146 +
71147 +    if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) {
71148 +        wlan_node_free(bss);
71149 +        return A_EINVAL;
71150 +    }
71151 +
71152 +    /*
71153 +     * Update the frequency in ie_chan, overwriting of channel number
71154 +     * which is done in wlan_parse_beacon
71155 +     */
71156 +    bss->ni_cie.ie_chan = bih->channel;
71157 +    wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
71158 +
71159 +    return A_OK;
71160 +}
71161 +
71162 +static A_STATUS
71163 +wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71164 +{
71165 +    bss_t *bss;
71166 +    WMI_OPT_RX_INFO_HDR *bih;
71167 +    A_UINT8 *buf;
71168 +
71169 +    if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) {
71170 +        return A_EINVAL;
71171 +    }
71172 +
71173 +    bih = (WMI_OPT_RX_INFO_HDR *)datap;
71174 +    buf = datap + sizeof(WMI_OPT_RX_INFO_HDR);
71175 +    len -= sizeof(WMI_OPT_RX_INFO_HDR);
71176 +
71177 +    A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG,
71178 +        bih->bssid[4], bih->bssid[5]));
71179 +
71180 +    bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
71181 +    if (bss != NULL) {
71182 +        /*
71183 +         * Free up the node.  Not the most efficient process given
71184 +         * we are about to allocate a new node but it is simple and should be
71185 +         * adequate.
71186 +         */
71187 +        wlan_node_reclaim(&wmip->wmi_scan_table, bss);
71188 +    }
71189 +
71190 +    bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
71191 +    if (bss == NULL) {
71192 +        return A_NO_MEMORY;
71193 +    }
71194 +
71195 +    bss->ni_snr        = bih->snr;
71196 +    bss->ni_cie.ie_chan = bih->channel;
71197 +    A_ASSERT(bss->ni_buf != NULL);
71198 +    A_MEMCPY(bss->ni_buf, buf, len);
71199 +    wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
71200 +
71201 +    return A_OK;
71202 +}
71203 +
71204 +    /* This event indicates inactivity timeout of a fatpipe(pstream)
71205 +     * at the target
71206 +     */
71207 +static A_STATUS
71208 +wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71209 +{
71210 +    WMI_PSTREAM_TIMEOUT_EVENT *ev;
71211 +
71212 +    if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) {
71213 +        return A_EINVAL;
71214 +    }
71215 +
71216 +    A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG));
71217 +
71218 +    ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap;
71219 +
71220 +        /* When the pstream (fat pipe == AC) timesout, it means there were no
71221 +         * thinStreams within this pstream & it got implicitly created due to
71222 +         * data flow on this AC. We start the inactivity timer only for
71223 +         * implicitly created pstream. Just reset the host state.
71224 +         */
71225 +        /* Set the activeTsids for this AC to 0 */
71226 +    LOCK_WMI(wmip);
71227 +    wmip->wmi_streamExistsForAC[ev->trafficClass]=0;
71228 +    wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass);
71229 +    UNLOCK_WMI(wmip);
71230 +
71231 +        /*Indicate inactivity to driver layer for this fatpipe (pstream)*/
71232 +    A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass);
71233 +
71234 +    return A_OK;
71235 +}
71236 +
71237 +static A_STATUS
71238 +wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71239 +{
71240 +    WMI_BIT_RATE_CMD *reply;
71241 +    A_INT32 rate;
71242 +
71243 +    if (len < sizeof(WMI_BIT_RATE_CMD)) {
71244 +        return A_EINVAL;
71245 +    }
71246 +    reply = (WMI_BIT_RATE_CMD *)datap;
71247 +    A_DPRINTF(DBG_WMI,
71248 +        (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex));
71249 +
71250 +    if (reply->rateIndex == RATE_AUTO) {
71251 +        rate = RATE_AUTO;
71252 +    } else {
71253 +        rate = wmi_rateTable[(A_UINT32) reply->rateIndex];
71254 +    }
71255 +
71256 +    A_WMI_BITRATE_RX(wmip->wmi_devt, rate);
71257 +
71258 +    return A_OK;
71259 +}
71260 +
71261 +static A_STATUS
71262 +wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71263 +{
71264 +    WMI_FIX_RATES_CMD *reply;
71265 +
71266 +    if (len < sizeof(WMI_BIT_RATE_CMD)) {
71267 +        return A_EINVAL;
71268 +    }
71269 +    reply = (WMI_FIX_RATES_CMD *)datap;
71270 +    A_DPRINTF(DBG_WMI,
71271 +        (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask));
71272 +
71273 +    A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask);
71274 +
71275 +    return A_OK;
71276 +}
71277 +
71278 +static A_STATUS
71279 +wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71280 +{
71281 +    WMI_CHANNEL_LIST_REPLY *reply;
71282 +
71283 +    if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) {
71284 +        return A_EINVAL;
71285 +    }
71286 +    reply = (WMI_CHANNEL_LIST_REPLY *)datap;
71287 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71288 +
71289 +    A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels,
71290 +                          reply->channelList);
71291 +
71292 +    return A_OK;
71293 +}
71294 +
71295 +static A_STATUS
71296 +wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71297 +{
71298 +    WMI_TX_PWR_REPLY *reply;
71299 +
71300 +    if (len < sizeof(*reply)) {
71301 +        return A_EINVAL;
71302 +    }
71303 +    reply = (WMI_TX_PWR_REPLY *)datap;
71304 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71305 +
71306 +    A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM);
71307 +
71308 +    return A_OK;
71309 +}
71310 +static A_STATUS
71311 +wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71312 +{
71313 +    WMI_GET_KEEPALIVE_CMD *reply;
71314 +
71315 +    if (len < sizeof(*reply)) {
71316 +        return A_EINVAL;
71317 +    }
71318 +    reply = (WMI_GET_KEEPALIVE_CMD *)datap;
71319 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71320 +
71321 +    A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured);
71322 +
71323 +    return A_OK;
71324 +}
71325 +
71326 +
71327 +static A_STATUS
71328 +wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71329 +{
71330 +    WMIX_DSETOPENREQ_EVENT *dsetopenreq;
71331 +
71332 +    if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) {
71333 +        return A_EINVAL;
71334 +    }
71335 +    dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap;
71336 +    A_DPRINTF(DBG_WMI,
71337 +        (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id));
71338 +    A_WMI_DSET_OPEN_REQ(wmip->wmi_devt,
71339 +                        dsetopenreq->dset_id,
71340 +                        dsetopenreq->targ_dset_handle,
71341 +                        dsetopenreq->targ_reply_fn,
71342 +                        dsetopenreq->targ_reply_arg);
71343 +
71344 +    return A_OK;
71345 +}
71346 +
71347 +#ifdef CONFIG_HOST_DSET_SUPPORT
71348 +static A_STATUS
71349 +wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71350 +{
71351 +    WMIX_DSETCLOSE_EVENT *dsetclose;
71352 +
71353 +    if (len < sizeof(WMIX_DSETCLOSE_EVENT)) {
71354 +        return A_EINVAL;
71355 +    }
71356 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71357 +
71358 +    dsetclose = (WMIX_DSETCLOSE_EVENT *)datap;
71359 +    A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie);
71360 +
71361 +    return A_OK;
71362 +}
71363 +
71364 +static A_STATUS
71365 +wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71366 +{
71367 +    WMIX_DSETDATAREQ_EVENT *dsetdatareq;
71368 +
71369 +    if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) {
71370 +        return A_EINVAL;
71371 +    }
71372 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71373 +
71374 +    dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap;
71375 +    A_WMI_DSET_DATA_REQ(wmip->wmi_devt,
71376 +                         dsetdatareq->access_cookie,
71377 +                         dsetdatareq->offset,
71378 +                         dsetdatareq->length,
71379 +                         dsetdatareq->targ_buf,
71380 +                         dsetdatareq->targ_reply_fn,
71381 +                         dsetdatareq->targ_reply_arg);
71382 +
71383 +    return A_OK;
71384 +}
71385 +#endif /* CONFIG_HOST_DSET_SUPPORT */
71386 +
71387 +static A_STATUS
71388 +wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71389 +{
71390 +    WMI_SCAN_COMPLETE_EVENT *ev;
71391 +
71392 +    ev = (WMI_SCAN_COMPLETE_EVENT *)datap;
71393 +    A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, ev->status);
71394 +
71395 +    return A_OK;
71396 +}
71397 +
71398 +/*
71399 + * Target is reporting a programming error.  This is for
71400 + * developer aid only.  Target only checks a few common violations
71401 + * and it is responsibility of host to do all error checking.
71402 + * Behavior of target after wmi error event is undefined.
71403 + * A reset is recommended.
71404 + */
71405 +static A_STATUS
71406 +wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71407 +{
71408 +    WMI_CMD_ERROR_EVENT *ev;
71409 +
71410 +    ev = (WMI_CMD_ERROR_EVENT *)datap;
71411 +    AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId));
71412 +    switch (ev->errorCode) {
71413 +    case (INVALID_PARAM):
71414 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n"));
71415 +        break;
71416 +    case (ILLEGAL_STATE):
71417 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n"));
71418 +        break;
71419 +    case (INTERNAL_ERROR):
71420 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n"));
71421 +        break;
71422 +    }
71423 +
71424 +    return A_OK;
71425 +}
71426 +
71427 +
71428 +static A_STATUS
71429 +wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71430 +{
71431 +    WMI_TARGET_STATS *reply;
71432 +
71433 +    if (len < sizeof(*reply)) {
71434 +        return A_EINVAL;
71435 +    }
71436 +    reply = (WMI_TARGET_STATS *)datap;
71437 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71438 +
71439 +    A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, reply);
71440 +
71441 +    return A_OK;
71442 +}
71443 +
71444 +static A_STATUS
71445 +wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71446 +{
71447 +    WMI_RSSI_THRESHOLD_EVENT *reply;
71448 +
71449 +    if (len < sizeof(*reply)) {
71450 +        return A_EINVAL;
71451 +    }
71452 +    reply = (WMI_RSSI_THRESHOLD_EVENT *)datap;
71453 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71454 +
71455 +    A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, reply->range, reply->rssi);
71456 +
71457 +    return A_OK;
71458 +}
71459 +
71460 +
71461 +static A_STATUS
71462 +wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71463 +{
71464 +    WMI_TARGET_ERROR_REPORT_EVENT *reply;
71465 +
71466 +    if (len < sizeof(*reply)) {
71467 +        return A_EINVAL;
71468 +    }
71469 +    reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap;
71470 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71471 +
71472 +    A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, reply->errorVal);
71473 +
71474 +    return A_OK;
71475 +}
71476 +
71477 +static A_STATUS
71478 +wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71479 +{
71480 +    WMI_CAC_EVENT *reply;
71481 +
71482 +    if (len < sizeof(*reply)) {
71483 +        return A_EINVAL;
71484 +    }
71485 +    reply = (WMI_CAC_EVENT *)datap;
71486 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71487 +
71488 +    A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac,
71489 +                reply->cac_indication, reply->statusCode,
71490 +                reply->tspecSuggestion);
71491 +
71492 +    return A_OK;
71493 +}
71494 +
71495 +static A_STATUS
71496 +wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71497 +{
71498 +    WMIX_HB_CHALLENGE_RESP_EVENT *reply;
71499 +
71500 +    if (len < sizeof(*reply)) {
71501 +        return A_EINVAL;
71502 +    }
71503 +    reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap;
71504 +    A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG));
71505 +
71506 +    A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source);
71507 +
71508 +    return A_OK;
71509 +}
71510 +
71511 +static A_STATUS
71512 +wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71513 +{
71514 +    WMI_TARGET_ROAM_TBL *reply;
71515 +
71516 +    if (len < sizeof(*reply)) {
71517 +        return A_EINVAL;
71518 +    }
71519 +    reply = (WMI_TARGET_ROAM_TBL *)datap;
71520 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71521 +
71522 +    A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply);
71523 +
71524 +    return A_OK;
71525 +}
71526 +
71527 +static A_STATUS
71528 +wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71529 +{
71530 +    WMI_TARGET_ROAM_DATA *reply;
71531 +
71532 +    if (len < sizeof(*reply)) {
71533 +        return A_EINVAL;
71534 +    }
71535 +    reply = (WMI_TARGET_ROAM_DATA *)datap;
71536 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71537 +
71538 +    A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply);
71539 +
71540 +    return A_OK;
71541 +}
71542 +
71543 +static A_STATUS
71544 +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71545 +{
71546 +    WMI_TX_RETRY_ERR_EVENT *reply;
71547 +
71548 +    if (len < sizeof(*reply)) {
71549 +        return A_EINVAL;
71550 +    }
71551 +    reply = (WMI_TX_RETRY_ERR_EVENT *)datap;
71552 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71553 +
71554 +    A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt);
71555 +
71556 +    return A_OK;
71557 +}
71558 +
71559 +static A_STATUS
71560 +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71561 +{
71562 +    WMI_SNR_THRESHOLD_EVENT *reply;
71563 +
71564 +    if (len < sizeof(*reply)) {
71565 +        return A_EINVAL;
71566 +    }
71567 +    reply = (WMI_SNR_THRESHOLD_EVENT *)datap;
71568 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71569 +
71570 +    A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, reply->range, reply->snr);
71571 +
71572 +    return A_OK;
71573 +}
71574 +
71575 +static A_STATUS
71576 +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71577 +{
71578 +    WMI_LQ_THRESHOLD_EVENT *reply;
71579 +
71580 +    if (len < sizeof(*reply)) {
71581 +        return A_EINVAL;
71582 +    }
71583 +    reply = (WMI_LQ_THRESHOLD_EVENT *)datap;
71584 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71585 +
71586 +    A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt, reply->range, reply->lq);
71587 +
71588 +    return A_OK;
71589 +}
71590 +
71591 +static A_STATUS
71592 +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71593 +{
71594 +    A_UINT16 ap_info_entry_size;
71595 +    WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap;
71596 +    WMI_AP_INFO_V1 *ap_info_v1;
71597 +    A_UINT8 i;
71598 +
71599 +    if (len < sizeof(WMI_APLIST_EVENT)) {
71600 +        return A_EINVAL;
71601 +    }
71602 +
71603 +    if (ev->apListVer == APLIST_VER1) {
71604 +        ap_info_entry_size = sizeof(WMI_AP_INFO_V1);
71605 +        ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList;
71606 +    } else {
71607 +        return A_EINVAL;
71608 +    }
71609 +
71610 +    AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP));
71611 +    if (len < (int)(sizeof(WMI_APLIST_EVENT) +
71612 +              (ev->numAP - 1) * ap_info_entry_size))
71613 +    {
71614 +        return A_EINVAL;
71615 +    }
71616 +
71617 +    /*
71618 +     * AP List Ver1 Contents
71619 +     */
71620 +    for (i = 0; i < ev->numAP; i++) {
71621 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\
71622 +                    "Channel %d\n", i,
71623 +                   ap_info_v1->bssid[0], ap_info_v1->bssid[1],
71624 +                   ap_info_v1->bssid[2], ap_info_v1->bssid[3],
71625 +                   ap_info_v1->bssid[4], ap_info_v1->bssid[5],
71626 +                   ap_info_v1->channel));
71627 +        ap_info_v1++;
71628 +    }
71629 +    return A_OK;
71630 +}
71631 +
71632 +static A_STATUS
71633 +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71634 +{
71635 +    A_UINT32 dropped;
71636 +
71637 +    dropped = *((A_UINT32 *)datap);
71638 +    datap += sizeof(dropped);
71639 +    len -= sizeof(dropped);
71640 +    A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, datap, len);
71641 +    return A_OK;
71642 +}
71643 +
71644 +#ifdef CONFIG_HOST_GPIO_SUPPORT
71645 +static A_STATUS
71646 +wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71647 +{
71648 +    WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap;
71649 +
71650 +    A_DPRINTF(DBG_WMI,
71651 +        (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG,
71652 +        gpio_intr->intr_mask, gpio_intr->input_values));
71653 +
71654 +    A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values);
71655 +
71656 +    return A_OK;
71657 +}
71658 +
71659 +static A_STATUS
71660 +wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71661 +{
71662 +    WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap;
71663 +
71664 +    A_DPRINTF(DBG_WMI,
71665 +        (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG,
71666 +        gpio_data->reg_id, gpio_data->value));
71667 +
71668 +    A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value);
71669 +
71670 +    return A_OK;
71671 +}
71672 +
71673 +static A_STATUS
71674 +wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71675 +{
71676 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71677 +
71678 +    A_WMI_GPIO_ACK_RX();
71679 +
71680 +    return A_OK;
71681 +}
71682 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
71683 +
71684 +/*
71685 + * Called to send a wmi command. Command specific data is already built
71686 + * on osbuf and current osbuf->data points to it.
71687 + */
71688 +A_STATUS
71689 +wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
71690 +               WMI_SYNC_FLAG syncflag)
71691 +{
71692 +#define IS_LONG_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID) || (cmdId == WMI_ADD_WOW_PATTERN_CMDID))
71693 +    WMI_CMD_HDR         *cHdr;
71694 +    WMI_PRI_STREAM_ID   streamID = WMI_CONTROL_PRI;
71695 +
71696 +    A_ASSERT(osbuf != NULL);
71697 +
71698 +    if (syncflag >= END_WMIFLAG) {
71699 +        return A_EINVAL;
71700 +    }
71701 +
71702 +    if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
71703 +        /*
71704 +         * We want to make sure all data currently queued is transmitted before
71705 +         * the cmd execution.  Establish a new sync point.
71706 +         */
71707 +        wmi_sync_point(wmip);
71708 +    }
71709 +
71710 +    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
71711 +        return A_NO_MEMORY;
71712 +    }
71713 +
71714 +    cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
71715 +    cHdr->commandId = cmdId;
71716 +
71717 +    /*
71718 +     * Send cmd, some via control pipe, others via data pipe
71719 +     */
71720 +    if (IS_LONG_CMD(cmdId)) {
71721 +        wmi_data_hdr_add(wmip, osbuf, CNTL_MSGTYPE);
71722 +        // TODO ... these can now go through the control endpoint via HTC 2.0
71723 +        streamID = WMI_BEST_EFFORT_PRI;
71724 +    }
71725 +    A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, streamID);
71726 +
71727 +    if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
71728 +        /*
71729 +         * We want to make sure all new data queued waits for the command to
71730 +         * execute. Establish a new sync point.
71731 +         */
71732 +        wmi_sync_point(wmip);
71733 +    }
71734 +    return (A_OK);
71735 +#undef IS_LONG_CMD
71736 +}
71737 +
71738 +A_STATUS
71739 +wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
71740 +                  WMI_SYNC_FLAG syncflag)
71741 +{
71742 +    WMIX_CMD_HDR     *cHdr;
71743 +
71744 +    if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
71745 +        return A_NO_MEMORY;
71746 +    }
71747 +
71748 +    cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
71749 +    cHdr->commandId = cmdId;
71750 +
71751 +    return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag);
71752 +}
71753 +
71754 +A_STATUS
71755 +wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType,
71756 +                DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode,
71757 +                CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen,
71758 +                CRYPTO_TYPE groupCrypto,A_UINT8 groupCryptoLen,
71759 +                int ssidLength, A_UCHAR *ssid,
71760 +                A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags)
71761 +{
71762 +    void *osbuf;
71763 +    WMI_CONNECT_CMD *cc;
71764 +
71765 +    if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) {
71766 +        return A_EINVAL;
71767 +    }
71768 +    if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) {
71769 +        return A_EINVAL;
71770 +    }
71771 +
71772 +    osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD));
71773 +    if (osbuf == NULL) {
71774 +        return A_NO_MEMORY;
71775 +    }
71776 +
71777 +    A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD));
71778 +
71779 +    cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf));
71780 +    A_MEMZERO(cc, sizeof(*cc));
71781 +
71782 +    A_MEMCPY(cc->ssid, ssid, ssidLength);
71783 +    cc->ssidLength          = ssidLength;
71784 +    cc->networkType         = netType;
71785 +    cc->dot11AuthMode       = dot11AuthMode;
71786 +    cc->authMode            = authMode;
71787 +    cc->pairwiseCryptoType  = pairwiseCrypto;
71788 +    cc->pairwiseCryptoLen   = pairwiseCryptoLen;
71789 +    cc->groupCryptoType     = groupCrypto;
71790 +    cc->groupCryptoLen      = groupCryptoLen;
71791 +    cc->channel             = channel;
71792 +    cc->ctrl_flags          = ctrl_flags;
71793 +
71794 +    if (bssid != NULL) {
71795 +        A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
71796 +    }
71797 +    if (wmi_set_keepalive_cmd(wmip, wmip->wmi_keepaliveInterval) != A_OK) {
71798 +        return(A_ERROR);
71799 +    }
71800 +
71801 +    return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG));
71802 +}
71803 +
71804 +A_STATUS
71805 +wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel)
71806 +{
71807 +    void *osbuf;
71808 +    WMI_RECONNECT_CMD *cc;
71809 +
71810 +    osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD));
71811 +    if (osbuf == NULL) {
71812 +        return A_NO_MEMORY;
71813 +    }
71814 +
71815 +    A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD));
71816 +
71817 +    cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf));
71818 +    A_MEMZERO(cc, sizeof(*cc));
71819 +
71820 +    cc->channel = channel;
71821 +
71822 +    if (bssid != NULL) {
71823 +        A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
71824 +    }
71825 +
71826 +    return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG));
71827 +}
71828 +
71829 +A_STATUS
71830 +wmi_disconnect_cmd(struct wmi_t *wmip)
71831 +{
71832 +    void *osbuf;
71833 +    A_STATUS status;
71834 +
71835 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
71836 +    if (osbuf == NULL) {
71837 +        return A_NO_MEMORY;
71838 +    }
71839 +
71840 +    /* Bug fix for 24817(elevator bug) - the disconnect command does not
71841 +       need to do a SYNC before.*/
71842 +    status = (wmi_cmd_send(wmip, osbuf, WMI_DISCONNECT_CMDID,
71843 +                         NO_SYNC_WMIFLAG));
71844 +
71845 +    return status;
71846 +}
71847 +
71848 +A_STATUS
71849 +wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
71850 +                  A_BOOL forceFgScan, A_BOOL isLegacy,
71851 +                  A_UINT32 homeDwellTime, A_UINT32 forceScanInterval)
71852 +{
71853 +    void *osbuf;
71854 +    WMI_START_SCAN_CMD *sc;
71855 +
71856 +    if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) {
71857 +        return A_EINVAL;
71858 +    }
71859 +
71860 +    osbuf = A_NETBUF_ALLOC(sizeof(*sc));
71861 +    if (osbuf == NULL) {
71862 +        return A_NO_MEMORY;
71863 +    }
71864 +
71865 +    A_NETBUF_PUT(osbuf, sizeof(*sc));
71866 +
71867 +    sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf));
71868 +    sc->scanType = scanType;
71869 +    sc->forceFgScan = forceFgScan;
71870 +    sc->isLegacy = isLegacy;
71871 +    sc->homeDwellTime = homeDwellTime;
71872 +    sc->forceScanInterval = forceScanInterval;
71873 +
71874 +    return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG));
71875 +}
71876 +
71877 +A_STATUS
71878 +wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
71879 +                   A_UINT16 fg_end_sec, A_UINT16 bg_sec,
71880 +                   A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec,
71881 +                   A_UINT16 pas_chdw_msec,
71882 +                   A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
71883 +                   A_UINT32 max_dfsch_act_time)
71884 +{
71885 +    void *osbuf;
71886 +    WMI_SCAN_PARAMS_CMD *sc;
71887 +
71888 +    osbuf = A_NETBUF_ALLOC(sizeof(*sc));
71889 +    if (osbuf == NULL) {
71890 +        return A_NO_MEMORY;
71891 +    }
71892 +
71893 +    A_NETBUF_PUT(osbuf, sizeof(*sc));
71894 +
71895 +    sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
71896 +    A_MEMZERO(sc, sizeof(*sc));
71897 +    sc->fg_start_period  = fg_start_sec;
71898 +    sc->fg_end_period    = fg_end_sec;
71899 +    sc->bg_period        = bg_sec;
71900 +    sc->minact_chdwell_time = minact_chdw_msec;
71901 +    sc->maxact_chdwell_time = maxact_chdw_msec;
71902 +    sc->pas_chdwell_time = pas_chdw_msec;
71903 +    sc->shortScanRatio   = shScanRatio;
71904 +    sc->scanCtrlFlags    = scanCtrlFlags;
71905 +    sc->max_dfsch_act_time = max_dfsch_act_time;
71906 +
71907 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID,
71908 +                         NO_SYNC_WMIFLAG));
71909 +}
71910 +
71911 +A_STATUS
71912 +wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask)
71913 +{
71914 +    void *osbuf;
71915 +    WMI_BSS_FILTER_CMD *cmd;
71916 +
71917 +    if (filter >= LAST_BSS_FILTER) {
71918 +        return A_EINVAL;
71919 +    }
71920 +
71921 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
71922 +    if (osbuf == NULL) {
71923 +        return A_NO_MEMORY;
71924 +    }
71925 +
71926 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
71927 +
71928 +    cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
71929 +    A_MEMZERO(cmd, sizeof(*cmd));
71930 +    cmd->bssFilter = filter;
71931 +    cmd->ieMask = ieMask;
71932 +
71933 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID,
71934 +                         NO_SYNC_WMIFLAG));
71935 +}
71936 +
71937 +A_STATUS
71938 +wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
71939 +                   A_UINT8 ssidLength, A_UCHAR *ssid)
71940 +{
71941 +    void *osbuf;
71942 +    WMI_PROBED_SSID_CMD *cmd;
71943 +
71944 +    if (index > MAX_PROBED_SSID_INDEX) {
71945 +        return A_EINVAL;
71946 +    }
71947 +    if (ssidLength > sizeof(cmd->ssid)) {
71948 +        return A_EINVAL;
71949 +    }
71950 +    if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) {
71951 +        return A_EINVAL;
71952 +    }
71953 +    if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) {
71954 +        return A_EINVAL;
71955 +    }
71956 +
71957 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
71958 +    if (osbuf == NULL) {
71959 +        return A_NO_MEMORY;
71960 +    }
71961 +
71962 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
71963 +
71964 +    cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf));
71965 +    A_MEMZERO(cmd, sizeof(*cmd));
71966 +    cmd->entryIndex = index;
71967 +    cmd->flag       = flag;
71968 +    cmd->ssidLength = ssidLength;
71969 +    A_MEMCPY(cmd->ssid, ssid, ssidLength);
71970 +
71971 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID,
71972 +                         NO_SYNC_WMIFLAG));
71973 +}
71974 +
71975 +A_STATUS
71976 +wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons)
71977 +{
71978 +    void *osbuf;
71979 +    WMI_LISTEN_INT_CMD *cmd;
71980 +
71981 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
71982 +    if (osbuf == NULL) {
71983 +        return A_NO_MEMORY;
71984 +    }
71985 +
71986 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
71987 +
71988 +    cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf));
71989 +    A_MEMZERO(cmd, sizeof(*cmd));
71990 +    cmd->listenInterval = listenInterval;
71991 +    cmd->numBeacons = listenBeacons;
71992 +
71993 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID,
71994 +                         NO_SYNC_WMIFLAG));
71995 +}
71996 +
71997 +A_STATUS
71998 +wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons)
71999 +{
72000 +    void *osbuf;
72001 +    WMI_BMISS_TIME_CMD *cmd;
72002 +
72003 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72004 +    if (osbuf == NULL) {
72005 +        return A_NO_MEMORY;
72006 +    }
72007 +
72008 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72009 +
72010 +    cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf));
72011 +    A_MEMZERO(cmd, sizeof(*cmd));
72012 +    cmd->bmissTime = bmissTime;
72013 +    cmd->numBeacons =  bmissBeacons;
72014 +
72015 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID,
72016 +                         NO_SYNC_WMIFLAG));
72017 +}
72018 +
72019 +A_STATUS
72020 +wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
72021 +                     A_UINT8 ieLen, A_UINT8 *ieInfo)
72022 +{
72023 +    void *osbuf;
72024 +    WMI_SET_ASSOC_INFO_CMD *cmd;
72025 +    A_UINT16 cmdLen;
72026 +
72027 +    cmdLen = sizeof(*cmd) + ieLen - 1;
72028 +    osbuf = A_NETBUF_ALLOC(cmdLen);
72029 +    if (osbuf == NULL) {
72030 +        return A_NO_MEMORY;
72031 +    }
72032 +
72033 +    A_NETBUF_PUT(osbuf, cmdLen);
72034 +
72035 +    cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf));
72036 +    A_MEMZERO(cmd, cmdLen);
72037 +    cmd->ieType = ieType;
72038 +    cmd->bufferSize = ieLen;
72039 +    A_MEMCPY(cmd->assocInfo, ieInfo, ieLen);
72040 +
72041 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID,
72042 +                         NO_SYNC_WMIFLAG));
72043 +}
72044 +
72045 +A_STATUS
72046 +wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode)
72047 +{
72048 +    void *osbuf;
72049 +    WMI_POWER_MODE_CMD *cmd;
72050 +
72051 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72052 +    if (osbuf == NULL) {
72053 +        return A_NO_MEMORY;
72054 +    }
72055 +
72056 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72057 +
72058 +    cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf));
72059 +    A_MEMZERO(cmd, sizeof(*cmd));
72060 +    cmd->powerMode = powerMode;
72061 +    wmip->wmi_powerMode = powerMode;
72062 +
72063 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID,
72064 +                         NO_SYNC_WMIFLAG));
72065 +}
72066 +
72067 +A_STATUS
72068 +wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
72069 +                   A_UINT16 atim_windows, A_UINT16 timeout_value)
72070 +{
72071 +    void *osbuf;
72072 +    WMI_IBSS_PM_CAPS_CMD *cmd;
72073 +
72074 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72075 +    if (osbuf == NULL) {
72076 +        return A_NO_MEMORY;
72077 +    }
72078 +
72079 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72080 +
72081 +    cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf));
72082 +    A_MEMZERO(cmd, sizeof(*cmd));
72083 +    cmd->power_saving = pmEnable;
72084 +    cmd->ttl = ttl;
72085 +    cmd->atim_windows = atim_windows;
72086 +    cmd->timeout_value = timeout_value;
72087 +
72088 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID,
72089 +                         NO_SYNC_WMIFLAG));
72090 +}
72091 +
72092 +A_STATUS
72093 +wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
72094 +                 A_UINT16 psPollNum, A_UINT16 dtimPolicy)
72095 +{
72096 +    void *osbuf;
72097 +    WMI_POWER_PARAMS_CMD *pm;
72098 +
72099 +    osbuf = A_NETBUF_ALLOC(sizeof(*pm));
72100 +    if (osbuf == NULL) {
72101 +        return A_NO_MEMORY;
72102 +    }
72103 +
72104 +    A_NETBUF_PUT(osbuf, sizeof(*pm));
72105 +
72106 +    pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
72107 +    A_MEMZERO(pm, sizeof(*pm));
72108 +    pm->idle_period   = idlePeriod;
72109 +    pm->pspoll_number = psPollNum;
72110 +    pm->dtim_policy   = dtimPolicy;
72111 +
72112 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID,
72113 +                         NO_SYNC_WMIFLAG));
72114 +}
72115 +
72116 +A_STATUS
72117 +wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout)
72118 +{
72119 +    void *osbuf;
72120 +    WMI_DISC_TIMEOUT_CMD *cmd;
72121 +
72122 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72123 +    if (osbuf == NULL) {
72124 +        return A_NO_MEMORY;
72125 +    }
72126 +
72127 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72128 +
72129 +    cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf));
72130 +    A_MEMZERO(cmd, sizeof(*cmd));
72131 +    cmd->disconnectTimeout = timeout;
72132 +
72133 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID,
72134 +                         NO_SYNC_WMIFLAG));
72135 +}
72136 +
72137 +A_STATUS
72138 +wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType,
72139 +               A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC,
72140 +               A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl,
72141 +               WMI_SYNC_FLAG sync_flag)
72142 +{
72143 +    void *osbuf;
72144 +    WMI_ADD_CIPHER_KEY_CMD *cmd;
72145 +
72146 +    if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) ||
72147 +        (keyMaterial == NULL))
72148 +    {
72149 +        return A_EINVAL;
72150 +    }
72151 +
72152 +    if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) {
72153 +        return A_EINVAL;
72154 +    }
72155 +
72156 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72157 +    if (osbuf == NULL) {
72158 +        return A_NO_MEMORY;
72159 +    }
72160 +
72161 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72162 +
72163 +    cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
72164 +    A_MEMZERO(cmd, sizeof(*cmd));
72165 +    cmd->keyIndex = keyIndex;
72166 +    cmd->keyType  = keyType;
72167 +    cmd->keyUsage = keyUsage;
72168 +    cmd->keyLength = keyLength;
72169 +    A_MEMCPY(cmd->key, keyMaterial, keyLength);
72170 +    if (NULL != keyRSC) {
72171 +        A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC));
72172 +    }
72173 +    cmd->key_op_ctrl = key_op_ctrl;
72174 +
72175 +    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag));
72176 +}
72177 +
72178 +A_STATUS
72179 +wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk)
72180 +{
72181 +    void *osbuf;
72182 +    WMI_ADD_KRK_CMD *cmd;
72183 +
72184 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72185 +
72186 +    if (osbuf == NULL) {
72187 +        return A_NO_MEMORY;
72188 +    }
72189 +
72190 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72191 +
72192 +    cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf));
72193 +    A_MEMZERO(cmd, sizeof(*cmd));
72194 +    A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN);
72195 +
72196 +    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG));
72197 +}
72198 +
72199 +A_STATUS
72200 +wmi_delete_krk_cmd(struct wmi_t *wmip)
72201 +{
72202 +    void *osbuf;
72203 +
72204 +    osbuf = A_NETBUF_ALLOC(0);
72205 +
72206 +    if (osbuf == NULL) {
72207 +        return A_NO_MEMORY;
72208 +    }
72209 +
72210 +    return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_KRK_CMDID, NO_SYNC_WMIFLAG));
72211 +}
72212 +
72213 +A_STATUS
72214 +wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex)
72215 +{
72216 +    void *osbuf;
72217 +    WMI_DELETE_CIPHER_KEY_CMD *cmd;
72218 +
72219 +    if (keyIndex > WMI_MAX_KEY_INDEX) {
72220 +        return A_EINVAL;
72221 +    }
72222 +
72223 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72224 +    if (osbuf == NULL) {
72225 +        return A_NO_MEMORY;
72226 +    }
72227 +
72228 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72229 +
72230 +    cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
72231 +    A_MEMZERO(cmd, sizeof(*cmd));
72232 +    cmd->keyIndex = keyIndex;
72233 +
72234 +    return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID,
72235 +                         NO_SYNC_WMIFLAG));
72236 +}
72237 +
72238 +A_STATUS
72239 +wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
72240 +                 A_BOOL set)
72241 +{
72242 +    void *osbuf;
72243 +    WMI_SET_PMKID_CMD *cmd;
72244 +
72245 +    if (bssid == NULL) {
72246 +        return A_EINVAL;
72247 +    }
72248 +
72249 +    if ((set == TRUE) && (pmkId == NULL)) {
72250 +        return A_EINVAL;
72251 +    }
72252 +
72253 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72254 +    if (osbuf == NULL) {
72255 +        return A_NO_MEMORY;
72256 +    }
72257 +
72258 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72259 +
72260 +    cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf));
72261 +    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
72262 +    if (set == TRUE) {
72263 +        A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid));
72264 +        cmd->enable = PMKID_ENABLE;
72265 +    } else {
72266 +        A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid));
72267 +        cmd->enable = PMKID_DISABLE;
72268 +    }
72269 +
72270 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG));
72271 +}
72272 +
72273 +A_STATUS
72274 +wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en)
72275 +{
72276 +    void *osbuf;
72277 +    WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd;
72278 +
72279 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72280 +    if (osbuf == NULL) {
72281 +        return A_NO_MEMORY;
72282 +    }
72283 +
72284 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72285 +
72286 +    cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf));
72287 +    cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE;
72288 +
72289 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID,
72290 +            NO_SYNC_WMIFLAG));
72291 +}
72292 +
72293 +A_STATUS
72294 +wmi_set_akmp_params_cmd(struct wmi_t *wmip,
72295 +                        WMI_SET_AKMP_PARAMS_CMD *akmpParams)
72296 +{
72297 +    void *osbuf;
72298 +    WMI_SET_AKMP_PARAMS_CMD *cmd;
72299 +
72300 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72301 +    if (osbuf == NULL) {
72302 +        return A_NO_MEMORY;
72303 +    }
72304 +
72305 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72306 +    cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
72307 +    cmd->akmpInfo = akmpParams->akmpInfo;
72308 +
72309 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID,
72310 +            NO_SYNC_WMIFLAG));
72311 +}
72312 +
72313 +A_STATUS
72314 +wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
72315 +                       WMI_SET_PMKID_LIST_CMD *pmkInfo)
72316 +{
72317 +    void *osbuf;
72318 +    WMI_SET_PMKID_LIST_CMD *cmd;
72319 +    A_UINT16 cmdLen;
72320 +    A_UINT8 i;
72321 +
72322 +    cmdLen = sizeof(pmkInfo->numPMKID) +
72323 +             pmkInfo->numPMKID * sizeof(WMI_PMKID);
72324 +
72325 +    osbuf = A_NETBUF_ALLOC(cmdLen);
72326 +
72327 +    if (osbuf == NULL) {
72328 +        return A_NO_MEMORY;
72329 +    }
72330 +
72331 +    A_NETBUF_PUT(osbuf, cmdLen);
72332 +    cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf));
72333 +    cmd->numPMKID = pmkInfo->numPMKID;
72334 +
72335 +    for (i = 0; i < cmd->numPMKID; i++) {
72336 +        A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i],
72337 +                 WMI_PMKID_LEN);
72338 +    }
72339 +
72340 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID,
72341 +            NO_SYNC_WMIFLAG));
72342 +}
72343 +
72344 +A_STATUS
72345 +wmi_get_pmkid_list_cmd(struct wmi_t *wmip)
72346 +{
72347 +    void *osbuf;
72348 +
72349 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
72350 +    if (osbuf == NULL) {
72351 +        return A_NO_MEMORY;
72352 +    }
72353 +
72354 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_PMKID_LIST_CMDID,
72355 +                         NO_SYNC_WMIFLAG));
72356 +}
72357 +
72358 +A_STATUS
72359 +wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, WMI_PRI_STREAM_ID streamID)
72360 +{
72361 +    WMI_DATA_HDR     *dtHdr;
72362 +
72363 +    A_ASSERT(streamID != WMI_CONTROL_PRI);
72364 +    A_ASSERT(osbuf != NULL);
72365 +
72366 +    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
72367 +        return A_NO_MEMORY;
72368 +    }
72369 +
72370 +    dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
72371 +    dtHdr->info =
72372 +      (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT;
72373 +
72374 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - streamID %d\n", DBGARG, streamID));
72375 +
72376 +    return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, streamID));
72377 +}
72378 +
72379 +typedef struct _WMI_DATA_SYNC_BUFS {
72380 +    A_UINT8            trafficClass;
72381 +    void               *osbuf;
72382 +}WMI_DATA_SYNC_BUFS;
72383 +
72384 +static A_STATUS
72385 +wmi_sync_point(struct wmi_t *wmip)
72386 +{
72387 +       void *cmd_osbuf;
72388 +    WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC];
72389 +       A_UINT8 i,numPriStreams=0;
72390 +       A_STATUS status;
72391 +
72392 +       A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72393 +
72394 +    memset(dataSyncBufs,0,sizeof(dataSyncBufs));
72395 +
72396 +    /* lock out while we walk through the priority list and assemble our local array */
72397 +    LOCK_WMI(wmip);
72398 +
72399 +    for (i=0; i < WMM_NUM_AC ; i++) {
72400 +               if (wmip->wmi_fatPipeExists & (1 << i)) {
72401 +            numPriStreams++;
72402 +            dataSyncBufs[numPriStreams-1].trafficClass = i;
72403 +        }
72404 +    }
72405 +
72406 +    UNLOCK_WMI(wmip);
72407 +
72408 +    /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */
72409 +
72410 +    do {
72411 +           /*
72412 +            * We allocate all network buffers needed so we will be able to
72413 +            * send all required frames.
72414 +            */
72415 +           cmd_osbuf = A_NETBUF_ALLOC(0);      /* no payload */
72416 +           if (cmd_osbuf == NULL) {
72417 +                   status = A_NO_MEMORY;
72418 +            break;
72419 +           }
72420 +
72421 +           for (i=0; i < numPriStreams ; i++) {
72422 +               dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0);
72423 +            if (dataSyncBufs[i].osbuf == NULL) {
72424 +                status = A_NO_MEMORY;
72425 +                break;
72426 +            }
72427 +           } //end for
72428 +
72429 +           /*
72430 +            * Send sync cmd followed by sync data messages on all endpoints being
72431 +            * used
72432 +            */
72433 +           status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID,
72434 +                                                 NO_SYNC_WMIFLAG);
72435 +
72436 +        if (A_FAILED(status)) {
72437 +            break;
72438 +        }
72439 +            /* cmd buffer sent, we no longer own it */
72440 +        cmd_osbuf = NULL;
72441 +
72442 +               for(i=0; i < numPriStreams; i++) {
72443 +            A_ASSERT(dataSyncBufs[i].osbuf != NULL);
72444 +
72445 +            status = wmi_dataSync_send(wmip, dataSyncBufs[i].osbuf,
72446 +                        WMI_ACCESSCATEGORY_WMISTREAM(wmip,dataSyncBufs[i].trafficClass));
72447 +
72448 +            if (A_FAILED(status)) {
72449 +                break;
72450 +            }
72451 +            /* we don't own this buffer anymore, NULL it out of the array so it
72452 +             * won't get cleaned up */
72453 +            dataSyncBufs[i].osbuf = NULL;
72454 +               } //end for
72455 +
72456 +    } while(FALSE);
72457 +
72458 +    /* free up any resources left over (possibly due to an error) */
72459 +
72460 +    if (cmd_osbuf != NULL) {
72461 +        A_NETBUF_FREE(cmd_osbuf);
72462 +    }
72463 +
72464 +    for (i = 0; i < numPriStreams; i++) {
72465 +        if (dataSyncBufs[i].osbuf != NULL) {
72466 +            A_NETBUF_FREE(dataSyncBufs[i].osbuf);
72467 +        }
72468 +    }
72469 +
72470 +       return (status);
72471 +}
72472 +
72473 +A_STATUS
72474 +wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params)
72475 +{
72476 +    void *osbuf;
72477 +    WMI_CREATE_PSTREAM_CMD *cmd;
72478 +       A_UINT16 activeTsids=0;
72479 +    A_UINT8 fatPipeExistsForAC=0;
72480 +
72481 +    /* Validate all the parameters. */
72482 +    if( !((params->userPriority < 8) &&
72483 +         (params->userPriority <= 0x7) &&
72484 +         (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass)  &&
72485 +         (params->trafficDirection == UPLINK_TRAFFIC ||
72486 +            params->trafficDirection == DNLINK_TRAFFIC ||
72487 +            params->trafficDirection == BIDIR_TRAFFIC) &&
72488 +         (params->trafficType == TRAFFIC_TYPE_APERIODIC ||
72489 +            params->trafficType == TRAFFIC_TYPE_PERIODIC ) &&
72490 +         (params->voicePSCapability == DISABLE_FOR_THIS_AC  ||
72491 +            params->voicePSCapability == ENABLE_FOR_THIS_AC ||
72492 +            params->voicePSCapability == ENABLE_FOR_ALL_AC) &&
72493 +         (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) )
72494 +    {
72495 +        return  A_EINVAL;
72496 +    }
72497 +
72498 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72499 +    if (osbuf == NULL) {
72500 +        return A_NO_MEMORY;
72501 +    }
72502 +
72503 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72504 +
72505 +    A_DPRINTF(DBG_WMI,
72506 +        (DBGFMT "Sending create_pstream_cmd: ac=%d    tsid:%d\n", DBGARG,
72507 +        params->trafficClass, params->tsid));
72508 +
72509 +    cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
72510 +    A_MEMZERO(cmd, sizeof(*cmd));
72511 +    A_MEMCPY(cmd, params, sizeof(*cmd));
72512 +
72513 +        /* this is an implicitly created Fat pipe */
72514 +    if (params->tsid == WMI_IMPLICIT_PSTREAM) {
72515 +        LOCK_WMI(wmip);
72516 +        fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
72517 +        wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
72518 +        UNLOCK_WMI(wmip);
72519 +    } else {
72520 +            /* this is an explicitly created thin stream within a fat pipe */
72521 +        LOCK_WMI(wmip);
72522 +        fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
72523 +        activeTsids = wmip->wmi_streamExistsForAC[params->trafficClass];
72524 +        wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<<params->tsid);
72525 +            /* if a thinstream becomes active, the fat pipe automatically
72526 +            * becomes active
72527 +            */
72528 +        wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
72529 +        UNLOCK_WMI(wmip);
72530 +    }
72531 +
72532 +        /* Indicate activty change to driver layer only if this is the
72533 +         * first TSID to get created in this AC explicitly or an implicit
72534 +         * fat pipe is getting created.
72535 +         */
72536 +    if (!fatPipeExistsForAC) {
72537 +        A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass);
72538 +    }
72539 +
72540 +    /* mike: should be SYNC_BEFORE_WMIFLAG */
72541 +    return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID,
72542 +                         NO_SYNC_WMIFLAG));
72543 +}
72544 +
72545 +A_STATUS
72546 +wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid)
72547 +{
72548 +    void *osbuf;
72549 +    WMI_DELETE_PSTREAM_CMD *cmd;
72550 +    A_STATUS status;
72551 +       A_UINT16 activeTsids=0;
72552 +
72553 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72554 +    if (osbuf == NULL) {
72555 +        return A_NO_MEMORY;
72556 +    }
72557 +
72558 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72559 +
72560 +    cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
72561 +    A_MEMZERO(cmd, sizeof(*cmd));
72562 +
72563 +    cmd->trafficClass = trafficClass;
72564 +    cmd->tsid = tsid;
72565 +
72566 +    LOCK_WMI(wmip);
72567 +    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
72568 +    UNLOCK_WMI(wmip);
72569 +
72570 +        /* Check if the tsid was created & exists */
72571 +    if (!(activeTsids & (1<<tsid))) {
72572 +
72573 +        A_DPRINTF(DBG_WMI,
72574 +        (DBGFMT "TSID %d does'nt exist for trafficClass: %d\n", DBGARG, tsid, trafficClass));
72575 +            /* TODO: return a more appropriate err code */
72576 +        return A_ERROR;
72577 +    }
72578 +
72579 +    A_DPRINTF(DBG_WMI,
72580 +        (DBGFMT "Sending delete_pstream_cmd: trafficClass: %d tsid=%d\n", DBGARG, trafficClass, tsid));
72581 +
72582 +    status = (wmi_cmd_send(wmip, osbuf, WMI_DELETE_PSTREAM_CMDID,
72583 +                         SYNC_BEFORE_WMIFLAG));
72584 +
72585 +    LOCK_WMI(wmip);
72586 +    wmip->wmi_streamExistsForAC[trafficClass] &= ~(1<<tsid);
72587 +    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
72588 +    UNLOCK_WMI(wmip);
72589 +
72590 +
72591 +        /* Indicate stream inactivity to driver layer only if all tsids
72592 +         * within this AC are deleted.
72593 +         */
72594 +    if(!activeTsids) {
72595 +        A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass);
72596 +        wmip->wmi_fatPipeExists &= ~(1<<trafficClass);
72597 +    }
72598 +
72599 +    return status;
72600 +}
72601 +
72602 +/*
72603 + * used to set the bit rate.  rate is in Kbps.  If rate == -1
72604 + * then auto selection is used.
72605 + */
72606 +A_STATUS
72607 +wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 rate)
72608 +{
72609 +    void *osbuf;
72610 +    WMI_BIT_RATE_CMD *cmd;
72611 +    A_INT8 index;
72612 +
72613 +    if (rate != -1) {
72614 +        index = wmi_validate_bitrate(wmip, rate);
72615 +        if(index == A_EINVAL){
72616 +            return A_EINVAL;
72617 +        }
72618 +    } else {
72619 +        index = -1;
72620 +    }
72621 +
72622 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72623 +    if (osbuf == NULL) {
72624 +        return A_NO_MEMORY;
72625 +    }
72626 +
72627 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72628 +
72629 +    cmd = (WMI_BIT_RATE_CMD *)(A_NETBUF_DATA(osbuf));
72630 +    A_MEMZERO(cmd, sizeof(*cmd));
72631 +
72632 +    cmd->rateIndex = index;
72633 +
72634 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
72635 +}
72636 +
72637 +A_STATUS
72638 +wmi_get_bitrate_cmd(struct wmi_t *wmip)
72639 +{
72640 +    void *osbuf;
72641 +
72642 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
72643 +    if (osbuf == NULL) {
72644 +        return A_NO_MEMORY;
72645 +    }
72646 +
72647 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
72648 +}
72649 +
72650 +/*
72651 + * Returns TRUE iff the given rate index is legal in the current PHY mode.
72652 + */
72653 +A_BOOL
72654 +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_UINT32 rateIndex)
72655 +{
72656 +    WMI_PHY_MODE phyMode = wmip->wmi_phyMode;
72657 +    A_BOOL isValid = TRUE;
72658 +    switch(phyMode) {
72659 +        case WMI_11A_MODE:
72660 +            if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) {
72661 +                isValid = FALSE;
72662 +            }
72663 +            break;
72664 +
72665 +        case WMI_11B_MODE:
72666 +            if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) {
72667 +                isValid = FALSE;
72668 +            }
72669 +            break;
72670 +
72671 +        case WMI_11GONLY_MODE:
72672 +            if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) {
72673 +                isValid = FALSE;
72674 +            }
72675 +            break;
72676 +
72677 +        case WMI_11G_MODE:
72678 +        case WMI_11AG_MODE:
72679 +            if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) {
72680 +                isValid = FALSE;
72681 +            }
72682 +            break;
72683 +
72684 +        default:
72685 +            A_ASSERT(FALSE);
72686 +            break;
72687 +    }
72688 +
72689 +    return isValid;
72690 +}
72691 +
72692 +A_INT8
72693 +wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate)
72694 +{
72695 +    A_INT8 i;
72696 +    if (rate != -1)
72697 +    {
72698 +        for (i=0;;i++)
72699 +        {
72700 +            if (wmi_rateTable[(A_UINT32) i] == 0) {
72701 +                return A_EINVAL;
72702 +            }
72703 +            if (wmi_rateTable[(A_UINT32) i] == rate) {
72704 +                break;
72705 +            }
72706 +        }
72707 +    }
72708 +    else{
72709 +     i = -1;
72710 +    }
72711 +
72712 +    if(wmi_is_bitrate_index_valid(wmip, i) != TRUE) {
72713 +        return A_EINVAL;
72714 +    }
72715 +
72716 +    return i;
72717 +}
72718 +
72719 +A_STATUS
72720 +wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask)
72721 +{
72722 +    void *osbuf;
72723 +    WMI_FIX_RATES_CMD *cmd;
72724 +    A_UINT32 rateIndex;
72725 +
72726 +    /* Make sure all rates in the mask are valid in the current PHY mode */
72727 +    for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) {
72728 +       if((1 << rateIndex) & (A_UINT32)fixRatesMask) {
72729 +            if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) {
72730 +                A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG));
72731 +                return A_EINVAL;
72732 +            }
72733 +       }
72734 +    }
72735 +
72736 +
72737 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72738 +    if (osbuf == NULL) {
72739 +        return A_NO_MEMORY;
72740 +    }
72741 +
72742 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72743 +
72744 +    cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf));
72745 +    A_MEMZERO(cmd, sizeof(*cmd));
72746 +
72747 +    cmd->fixRateMask = fixRatesMask;
72748 +
72749 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG));
72750 +}
72751 +
72752 +A_STATUS
72753 +wmi_get_ratemask_cmd(struct wmi_t *wmip)
72754 +{
72755 +    void *osbuf;
72756 +
72757 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
72758 +    if (osbuf == NULL) {
72759 +        return A_NO_MEMORY;
72760 +    }
72761 +
72762 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_FIXRATES_CMDID, NO_SYNC_WMIFLAG));
72763 +}
72764 +
72765 +A_STATUS
72766 +wmi_get_channelList_cmd(struct wmi_t *wmip)
72767 +{
72768 +    void *osbuf;
72769 +
72770 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
72771 +    if (osbuf == NULL) {
72772 +        return A_NO_MEMORY;
72773 +    }
72774 +
72775 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_CHANNEL_LIST_CMDID,
72776 +                         NO_SYNC_WMIFLAG));
72777 +}
72778 +
72779 +/*
72780 + * used to generate a wmi sey channel Parameters cmd.
72781 + * mode should always be specified and corresponds to the phy mode of the
72782 + * wlan.
72783 + * numChan should alway sbe specified. If zero indicates that all available
72784 + * channels should be used.
72785 + * channelList is an array of channel frequencies (in Mhz) which the radio
72786 + * should limit its operation to.  It should be NULL if numChan == 0.  Size of
72787 + * array should correspond to numChan entries.
72788 + */
72789 +A_STATUS
72790 +wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
72791 +                          WMI_PHY_MODE mode, A_INT8 numChan,
72792 +                          A_UINT16 *channelList)
72793 +{
72794 +    void *osbuf;
72795 +    WMI_CHANNEL_PARAMS_CMD *cmd;
72796 +    A_INT8 size;
72797 +
72798 +    size = sizeof (*cmd);
72799 +
72800 +    if (numChan) {
72801 +        if (numChan > WMI_MAX_CHANNELS) {
72802 +            return A_EINVAL;
72803 +        }
72804 +        size += sizeof(A_UINT16) * (numChan - 1);
72805 +    }
72806 +
72807 +    osbuf = A_NETBUF_ALLOC(size);
72808 +    if (osbuf == NULL) {
72809 +        return A_NO_MEMORY;
72810 +    }
72811 +
72812 +    A_NETBUF_PUT(osbuf, size);
72813 +
72814 +    cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
72815 +    A_MEMZERO(cmd, size);
72816 +
72817 +    wmip->wmi_phyMode = mode;
72818 +    cmd->scanParam   = scanParam;
72819 +    cmd->phyMode     = mode;
72820 +    cmd->numChannels = numChan;
72821 +    A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16));
72822 +
72823 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID,
72824 +                         NO_SYNC_WMIFLAG));
72825 +}
72826 +
72827 +A_STATUS
72828 +wmi_set_rssi_threshold_params(struct wmi_t *wmip,
72829 +                              WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
72830 +{
72831 +    void    *osbuf;
72832 +    A_INT8  size;
72833 +    WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd;
72834 +    /* These values are in ascending order */
72835 +    if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val ||
72836 +        rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val ||
72837 +        rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val ||
72838 +        rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val ||
72839 +        rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val ||
72840 +        rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val ||
72841 +        rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val ||
72842 +        rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val ||
72843 +        rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val ||
72844 +        rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val) {
72845 +
72846 +        return A_EINVAL;
72847 +    }
72848 +
72849 +    size = sizeof (*cmd);
72850 +
72851 +    osbuf = A_NETBUF_ALLOC(size);
72852 +    if (osbuf == NULL) {
72853 +        return A_NO_MEMORY;
72854 +    }
72855 +
72856 +    A_NETBUF_PUT(osbuf, size);
72857 +
72858 +    cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
72859 +    A_MEMZERO(cmd, size);
72860 +    A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD));
72861 +
72862 +    return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID,
72863 +                            NO_SYNC_WMIFLAG));
72864 +}
72865 +
72866 +A_STATUS
72867 +wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip,
72868 +                              WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd)
72869 +{
72870 +    void    *osbuf;
72871 +    A_INT8  size;
72872 +    WMI_SET_HOST_SLEEP_MODE_CMD *cmd;
72873 +
72874 +    if( hostModeCmd->awake == hostModeCmd->asleep) {
72875 +        return A_EINVAL;
72876 +    }
72877 +
72878 +    size = sizeof (*cmd);
72879 +
72880 +    osbuf = A_NETBUF_ALLOC(size);
72881 +    if (osbuf == NULL) {
72882 +        return A_NO_MEMORY;
72883 +    }
72884 +
72885 +    A_NETBUF_PUT(osbuf, size);
72886 +
72887 +    cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf));
72888 +    A_MEMZERO(cmd, size);
72889 +    A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD));
72890 +
72891 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID,
72892 +                            NO_SYNC_WMIFLAG));
72893 +}
72894 +
72895 +A_STATUS
72896 +wmi_set_wow_mode_cmd(struct wmi_t *wmip,
72897 +                              WMI_SET_WOW_MODE_CMD *wowModeCmd)
72898 +{
72899 +    void    *osbuf;
72900 +    A_INT8  size;
72901 +    WMI_SET_WOW_MODE_CMD *cmd;
72902 +
72903 +    size = sizeof (*cmd);
72904 +
72905 +    osbuf = A_NETBUF_ALLOC(size);
72906 +    if (osbuf == NULL) {
72907 +        return A_NO_MEMORY;
72908 +    }
72909 +
72910 +    A_NETBUF_PUT(osbuf, size);
72911 +
72912 +    cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf));
72913 +    A_MEMZERO(cmd, size);
72914 +    A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD));
72915 +
72916 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID,
72917 +                            NO_SYNC_WMIFLAG));
72918 +
72919 +}
72920 +
72921 +A_STATUS
72922 +wmi_get_wow_list_cmd(struct wmi_t *wmip,
72923 +                              WMI_GET_WOW_LIST_CMD *wowListCmd)
72924 +{
72925 +    void    *osbuf;
72926 +    A_INT8  size;
72927 +    WMI_GET_WOW_LIST_CMD *cmd;
72928 +
72929 +    size = sizeof (*cmd);
72930 +
72931 +    osbuf = A_NETBUF_ALLOC(size);
72932 +    if (osbuf == NULL) {
72933 +        return A_NO_MEMORY;
72934 +    }
72935 +
72936 +    A_NETBUF_PUT(osbuf, size);
72937 +
72938 +    cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf));
72939 +    A_MEMZERO(cmd, size);
72940 +    A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD));
72941 +
72942 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID,
72943 +                            NO_SYNC_WMIFLAG));
72944 +
72945 +}
72946 +
72947 +static A_STATUS
72948 +wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72949 +{
72950 +    WMI_GET_WOW_LIST_REPLY *reply;
72951 +
72952 +    if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) {
72953 +        return A_EINVAL;
72954 +    }
72955 +    reply = (WMI_GET_WOW_LIST_REPLY *)datap;
72956 +
72957 +    A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters,
72958 +                          reply);
72959 +
72960 +    return A_OK;
72961 +}
72962 +
72963 +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
72964 +                                 WMI_ADD_WOW_PATTERN_CMD *addWowCmd,
72965 +                                 A_UINT8* pattern, A_UINT8* mask,
72966 +                                 A_UINT8 pattern_size)
72967 +{
72968 +    void    *osbuf;
72969 +    A_INT8  size;
72970 +    WMI_ADD_WOW_PATTERN_CMD *cmd;
72971 +    A_UINT8 *filter_mask = NULL;
72972 +
72973 +    size = sizeof (*cmd);
72974 +
72975 +    size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8));
72976 +    osbuf = A_NETBUF_ALLOC(size);
72977 +    if (osbuf == NULL) {
72978 +        return A_NO_MEMORY;
72979 +    }
72980 +
72981 +    A_NETBUF_PUT(osbuf, size);
72982 +
72983 +    cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
72984 +    cmd->filter_list_id = addWowCmd->filter_list_id;
72985 +    cmd->filter_offset = addWowCmd->filter_offset;
72986 +    cmd->filter_size = addWowCmd->filter_size;
72987 +
72988 +    A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size);
72989 +
72990 +    filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size);
72991 +    A_MEMCPY(filter_mask, mask, addWowCmd->filter_size);
72992 +
72993 +
72994 +    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID,
72995 +                            NO_SYNC_WMIFLAG));
72996 +}
72997 +
72998 +A_STATUS
72999 +wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
73000 +                              WMI_DEL_WOW_PATTERN_CMD *delWowCmd)
73001 +{
73002 +    void    *osbuf;
73003 +    A_INT8  size;
73004 +    WMI_DEL_WOW_PATTERN_CMD *cmd;
73005 +
73006 +    size = sizeof (*cmd);
73007 +
73008 +    osbuf = A_NETBUF_ALLOC(size);
73009 +    if (osbuf == NULL) {
73010 +        return A_NO_MEMORY;
73011 +    }
73012 +
73013 +    A_NETBUF_PUT(osbuf, size);
73014 +
73015 +    cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
73016 +    A_MEMZERO(cmd, size);
73017 +    A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD));
73018 +
73019 +    return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID,
73020 +                            NO_SYNC_WMIFLAG));
73021 +
73022 +}
73023 +
73024 +A_STATUS
73025 +wmi_set_snr_threshold_params(struct wmi_t *wmip,
73026 +                             WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
73027 +{
73028 +    void    *osbuf;
73029 +    A_INT8  size;
73030 +    WMI_SNR_THRESHOLD_PARAMS_CMD *cmd;
73031 +    /* These values are in ascending order */
73032 +    if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val ||
73033 +        snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val ||
73034 +        snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val ||
73035 +        snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val ||
73036 +        snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val ||
73037 +        snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val) {
73038 +
73039 +        return A_EINVAL;
73040 +    }
73041 +
73042 +    size = sizeof (*cmd);
73043 +
73044 +    osbuf = A_NETBUF_ALLOC(size);
73045 +    if (osbuf == NULL) {
73046 +        return A_NO_MEMORY;
73047 +    }
73048 +
73049 +    A_NETBUF_PUT(osbuf, size);
73050 +
73051 +    cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
73052 +    A_MEMZERO(cmd, size);
73053 +    A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD));
73054 +
73055 +    return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID,
73056 +                            NO_SYNC_WMIFLAG));
73057 +}
73058 +
73059 +A_STATUS
73060 +wmi_clr_rssi_snr(struct wmi_t *wmip)
73061 +{
73062 +    void    *osbuf;
73063 +
73064 +    osbuf = A_NETBUF_ALLOC(sizeof(int));
73065 +    if (osbuf == NULL) {
73066 +        return A_NO_MEMORY;
73067 +    }
73068 +
73069 +    return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID,
73070 +                            NO_SYNC_WMIFLAG));
73071 +}
73072 +
73073 +A_STATUS
73074 +wmi_set_lq_threshold_params(struct wmi_t *wmip,
73075 +                             WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd)
73076 +{
73077 +    void    *osbuf;
73078 +    A_INT8  size;
73079 +    WMI_LQ_THRESHOLD_PARAMS_CMD *cmd;
73080 +    /* These values are in ascending order */
73081 +    if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val ||
73082 +        lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val ||
73083 +        lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val ||
73084 +        lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val ||
73085 +        lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val ||
73086 +        lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) {
73087 +
73088 +        return A_EINVAL;
73089 +    }
73090 +
73091 +    size = sizeof (*cmd);
73092 +
73093 +    osbuf = A_NETBUF_ALLOC(size);
73094 +    if (osbuf == NULL) {
73095 +        return A_NO_MEMORY;
73096 +    }
73097 +
73098 +    A_NETBUF_PUT(osbuf, size);
73099 +
73100 +    cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
73101 +    A_MEMZERO(cmd, size);
73102 +    A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD));
73103 +
73104 +    return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID,
73105 +                            NO_SYNC_WMIFLAG));
73106 +}
73107 +
73108 +A_STATUS
73109 +wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask)
73110 +{
73111 +    void    *osbuf;
73112 +    A_INT8  size;
73113 +    WMI_TARGET_ERROR_REPORT_BITMASK *cmd;
73114 +
73115 +    size = sizeof (*cmd);
73116 +
73117 +    osbuf = A_NETBUF_ALLOC(size);
73118 +    if (osbuf == NULL) {
73119 +        return A_NO_MEMORY;
73120 +    }
73121 +
73122 +    A_NETBUF_PUT(osbuf, size);
73123 +
73124 +    cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf));
73125 +    A_MEMZERO(cmd, size);
73126 +
73127 +    cmd->bitmask = mask;
73128 +
73129 +    return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
73130 +                            NO_SYNC_WMIFLAG));
73131 +}
73132 +
73133 +A_STATUS
73134 +wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source)
73135 +{
73136 +    void *osbuf;
73137 +    WMIX_HB_CHALLENGE_RESP_CMD *cmd;
73138 +
73139 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73140 +    if (osbuf == NULL) {
73141 +        return A_NO_MEMORY;
73142 +    }
73143 +
73144 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73145 +
73146 +    cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf));
73147 +    cmd->cookie = cookie;
73148 +    cmd->source = source;
73149 +
73150 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID,
73151 +                              NO_SYNC_WMIFLAG));
73152 +}
73153 +
73154 +A_STATUS
73155 +wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
73156 +                            A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
73157 +                            A_UINT32 valid)
73158 +{
73159 +    void *osbuf;
73160 +    WMIX_DBGLOG_CFG_MODULE_CMD *cmd;
73161 +
73162 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73163 +    if (osbuf == NULL) {
73164 +        return A_NO_MEMORY;
73165 +    }
73166 +
73167 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73168 +
73169 +    cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf));
73170 +    cmd->config.cfgmmask = mmask;
73171 +    cmd->config.cfgtsr = tsr;
73172 +    cmd->config.cfgrep = rep;
73173 +    cmd->config.cfgsize = size;
73174 +    cmd->config.cfgvalid = valid;
73175 +
73176 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID,
73177 +                              NO_SYNC_WMIFLAG));
73178 +}
73179 +
73180 +A_STATUS
73181 +wmi_get_stats_cmd(struct wmi_t *wmip)
73182 +{
73183 +    void *osbuf;
73184 +
73185 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
73186 +    if (osbuf == NULL) {
73187 +        return A_NO_MEMORY;
73188 +    }
73189 +
73190 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_STATISTICS_CMDID,
73191 +                         NO_SYNC_WMIFLAG));
73192 +}
73193 +
73194 +A_STATUS
73195 +wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid)
73196 +{
73197 +    void *osbuf;
73198 +    WMI_ADD_BAD_AP_CMD *cmd;
73199 +
73200 +    if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) {
73201 +        return A_EINVAL;
73202 +    }
73203 +
73204 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73205 +    if (osbuf == NULL) {
73206 +        return A_NO_MEMORY;
73207 +    }
73208 +
73209 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73210 +
73211 +    cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
73212 +    cmd->badApIndex = apIndex;
73213 +    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
73214 +
73215 +    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, NO_SYNC_WMIFLAG));
73216 +}
73217 +
73218 +A_STATUS
73219 +wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex)
73220 +{
73221 +    void *osbuf;
73222 +    WMI_DELETE_BAD_AP_CMD *cmd;
73223 +
73224 +    if (apIndex > WMI_MAX_BAD_AP_INDEX) {
73225 +        return A_EINVAL;
73226 +    }
73227 +
73228 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73229 +    if (osbuf == NULL) {
73230 +        return A_NO_MEMORY;
73231 +    }
73232 +
73233 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73234 +
73235 +    cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
73236 +    cmd->badApIndex = apIndex;
73237 +
73238 +    return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID,
73239 +                         NO_SYNC_WMIFLAG));
73240 +}
73241 +
73242 +A_STATUS
73243 +wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM)
73244 +{
73245 +    void *osbuf;
73246 +    WMI_SET_TX_PWR_CMD *cmd;
73247 +
73248 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73249 +    if (osbuf == NULL) {
73250 +        return A_NO_MEMORY;
73251 +    }
73252 +
73253 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73254 +
73255 +    cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf));
73256 +    cmd->dbM = dbM;
73257 +
73258 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
73259 +}
73260 +
73261 +A_STATUS
73262 +wmi_get_txPwr_cmd(struct wmi_t *wmip)
73263 +{
73264 +    void *osbuf;
73265 +
73266 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
73267 +    if (osbuf == NULL) {
73268 +        return A_NO_MEMORY;
73269 +    }
73270 +
73271 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
73272 +}
73273 +
73274 +A_STATUS
73275 +wmi_switch_radio(struct wmi_t *wmip, A_UINT8 on)
73276 +{
73277 +       WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0,
73278 +                                       WMI_SHORTSCANRATIO_DEFAULT,
73279 +                                       DEFAULT_SCAN_CTRL_FLAGS,
73280 +                                       0};
73281 +
73282 +       if (on) {
73283 +               /* Enable foreground scanning */
73284 +                if (wmi_scanparams_cmd(wmip, scParams.fg_start_period,
73285 +                                       scParams.fg_end_period,
73286 +                                       scParams.bg_period,
73287 +                                       scParams.minact_chdwell_time,
73288 +                                       scParams.maxact_chdwell_time,
73289 +                                       scParams.pas_chdwell_time,
73290 +                                       scParams.shortScanRatio,
73291 +                                       scParams.scanCtrlFlags,
73292 +                                       scParams.max_dfsch_act_time) != A_OK) {
73293 +                       return -EIO;
73294 +               }
73295 +       } else {
73296 +               wmi_disconnect_cmd(wmip);
73297 +               if (wmi_scanparams_cmd(wmip, 0xFFFF, 0, 0, 0,
73298 +                                      0, 0, 0, 0xFF, 0) != A_OK) {
73299 +                       return -EIO;
73300 +               }
73301 +       }
73302 +
73303 +       return A_OK;
73304 +}
73305 +
73306 +
73307 +A_UINT16
73308 +wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass)
73309 +{
73310 +       A_UINT16 activeTsids=0;
73311 +
73312 +    LOCK_WMI(wmip);
73313 +    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
73314 +    UNLOCK_WMI(wmip);
73315 +
73316 +    return activeTsids;
73317 +}
73318 +
73319 +A_STATUS
73320 +wmi_get_roam_tbl_cmd(struct wmi_t *wmip)
73321 +{
73322 +    void *osbuf;
73323 +
73324 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
73325 +    if (osbuf == NULL) {
73326 +        return A_NO_MEMORY;
73327 +    }
73328 +
73329 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_TBL_CMDID,
73330 +                         NO_SYNC_WMIFLAG));
73331 +}
73332 +
73333 +A_STATUS
73334 +wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType)
73335 +{
73336 +    void *osbuf;
73337 +    A_UINT32 size = sizeof(A_UINT8);
73338 +    WMI_TARGET_ROAM_DATA *cmd;
73339 +
73340 +    osbuf = A_NETBUF_ALLOC(size);      /* no payload */
73341 +    if (osbuf == NULL) {
73342 +        return A_NO_MEMORY;
73343 +    }
73344 +
73345 +    A_NETBUF_PUT(osbuf, size);
73346 +
73347 +    cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf));
73348 +    cmd->roamDataType = roamDataType;
73349 +
73350 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID,
73351 +                         NO_SYNC_WMIFLAG));
73352 +}
73353 +
73354 +A_STATUS
73355 +wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
73356 +                      A_UINT8 size)
73357 +{
73358 +    void *osbuf;
73359 +    WMI_SET_ROAM_CTRL_CMD *cmd;
73360 +
73361 +    osbuf = A_NETBUF_ALLOC(size);
73362 +    if (osbuf == NULL) {
73363 +        return A_NO_MEMORY;
73364 +    }
73365 +
73366 +    A_NETBUF_PUT(osbuf, size);
73367 +
73368 +    cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf));
73369 +    A_MEMZERO(cmd, size);
73370 +
73371 +    A_MEMCPY(cmd, p, size);
73372 +
73373 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID,
73374 +                         NO_SYNC_WMIFLAG));
73375 +}
73376 +
73377 +A_STATUS
73378 +wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
73379 +                            WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
73380 +                            A_UINT8 size)
73381 +{
73382 +    void *osbuf;
73383 +    WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd;
73384 +
73385 +    /* These timers can't be zero */
73386 +    if(!pCmd->psPollTimeout || !pCmd->triggerTimeout ||
73387 +       !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD ||
73388 +         pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) ||
73389 +       !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD ||
73390 +         pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD))
73391 +        return A_EINVAL;
73392 +
73393 +    osbuf = A_NETBUF_ALLOC(size);
73394 +    if (osbuf == NULL) {
73395 +        return A_NO_MEMORY;
73396 +    }
73397 +
73398 +    A_NETBUF_PUT(osbuf, size);
73399 +
73400 +    cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf));
73401 +    A_MEMZERO(cmd, size);
73402 +
73403 +    A_MEMCPY(cmd, pCmd, size);
73404 +
73405 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
73406 +                         NO_SYNC_WMIFLAG));
73407 +}
73408 +
73409 +#ifdef CONFIG_HOST_GPIO_SUPPORT
73410 +/* Send a command to Target to change GPIO output pins. */
73411 +A_STATUS
73412 +wmi_gpio_output_set(struct wmi_t *wmip,
73413 +                    A_UINT32 set_mask,
73414 +                    A_UINT32 clear_mask,
73415 +                    A_UINT32 enable_mask,
73416 +                    A_UINT32 disable_mask)
73417 +{
73418 +    void *osbuf;
73419 +    WMIX_GPIO_OUTPUT_SET_CMD *output_set;
73420 +    int size;
73421 +
73422 +    size = sizeof(*output_set);
73423 +
73424 +    A_DPRINTF(DBG_WMI,
73425 +        (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG,
73426 +        set_mask, clear_mask, enable_mask, disable_mask));
73427 +
73428 +    osbuf = A_NETBUF_ALLOC(size);
73429 +    if (osbuf == NULL) {
73430 +        return A_NO_MEMORY;
73431 +    }
73432 +    A_NETBUF_PUT(osbuf, size);
73433 +    output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf));
73434 +
73435 +    output_set->set_mask                   = set_mask;
73436 +    output_set->clear_mask                 = clear_mask;
73437 +    output_set->enable_mask                = enable_mask;
73438 +    output_set->disable_mask               = disable_mask;
73439 +
73440 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID,
73441 +                             NO_SYNC_WMIFLAG));
73442 +}
73443 +
73444 +/* Send a command to the Target requesting state of the GPIO input pins */
73445 +A_STATUS
73446 +wmi_gpio_input_get(struct wmi_t *wmip)
73447 +{
73448 +    void *osbuf;
73449 +
73450 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
73451 +
73452 +    osbuf = A_NETBUF_ALLOC(0);
73453 +    if (osbuf == NULL) {
73454 +        return A_NO_MEMORY;
73455 +    }
73456 +
73457 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INPUT_GET_CMDID,
73458 +                             NO_SYNC_WMIFLAG));
73459 +}
73460 +
73461 +/* Send a command to the Target that changes the value of a GPIO register. */
73462 +A_STATUS
73463 +wmi_gpio_register_set(struct wmi_t *wmip,
73464 +                      A_UINT32 gpioreg_id,
73465 +                      A_UINT32 value)
73466 +{
73467 +    void *osbuf;
73468 +    WMIX_GPIO_REGISTER_SET_CMD *register_set;
73469 +    int size;
73470 +
73471 +    size = sizeof(*register_set);
73472 +
73473 +    A_DPRINTF(DBG_WMI,
73474 +        (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value));
73475 +
73476 +    osbuf = A_NETBUF_ALLOC(size);
73477 +    if (osbuf == NULL) {
73478 +        return A_NO_MEMORY;
73479 +    }
73480 +    A_NETBUF_PUT(osbuf, size);
73481 +    register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf));
73482 +
73483 +    register_set->gpioreg_id               = gpioreg_id;
73484 +    register_set->value                    = value;
73485 +
73486 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID,
73487 +                             NO_SYNC_WMIFLAG));
73488 +}
73489 +
73490 +/* Send a command to the Target to fetch the value of a GPIO register. */
73491 +A_STATUS
73492 +wmi_gpio_register_get(struct wmi_t *wmip,
73493 +                      A_UINT32 gpioreg_id)
73494 +{
73495 +    void *osbuf;
73496 +    WMIX_GPIO_REGISTER_GET_CMD *register_get;
73497 +    int size;
73498 +
73499 +    size = sizeof(*register_get);
73500 +
73501 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id));
73502 +
73503 +    osbuf = A_NETBUF_ALLOC(size);
73504 +    if (osbuf == NULL) {
73505 +        return A_NO_MEMORY;
73506 +    }
73507 +    A_NETBUF_PUT(osbuf, size);
73508 +    register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf));
73509 +
73510 +    register_get->gpioreg_id               = gpioreg_id;
73511 +
73512 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID,
73513 +                             NO_SYNC_WMIFLAG));
73514 +}
73515 +
73516 +/* Send a command to the Target acknowledging some GPIO interrupts. */
73517 +A_STATUS
73518 +wmi_gpio_intr_ack(struct wmi_t *wmip,
73519 +                  A_UINT32 ack_mask)
73520 +{
73521 +    void *osbuf;
73522 +    WMIX_GPIO_INTR_ACK_CMD *intr_ack;
73523 +    int size;
73524 +
73525 +    size = sizeof(*intr_ack);
73526 +
73527 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask));
73528 +
73529 +    osbuf = A_NETBUF_ALLOC(size);
73530 +    if (osbuf == NULL) {
73531 +        return A_NO_MEMORY;
73532 +    }
73533 +    A_NETBUF_PUT(osbuf, size);
73534 +    intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf));
73535 +
73536 +    intr_ack->ack_mask               = ack_mask;
73537 +
73538 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID,
73539 +                             NO_SYNC_WMIFLAG));
73540 +}
73541 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
73542 +
73543 +A_STATUS
73544 +wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, A_UINT8 eCWmin,
73545 +                          A_UINT8 eCWmax, A_UINT8 aifsn)
73546 +{
73547 +    void *osbuf;
73548 +    WMI_SET_ACCESS_PARAMS_CMD *cmd;
73549 +
73550 +    if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) ||
73551 +        (aifsn > WMI_MAX_AIFSN_ACPARAM))
73552 +    {
73553 +        return A_EINVAL;
73554 +    }
73555 +
73556 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73557 +    if (osbuf == NULL) {
73558 +        return A_NO_MEMORY;
73559 +    }
73560 +
73561 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73562 +
73563 +    cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
73564 +    cmd->txop   = txop;
73565 +    cmd->eCWmin = eCWmin;
73566 +    cmd->eCWmax = eCWmax;
73567 +    cmd->aifsn  = aifsn;
73568 +
73569 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID,
73570 +                         NO_SYNC_WMIFLAG));
73571 +}
73572 +
73573 +A_STATUS
73574 +wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
73575 +                         A_UINT8 trafficClass, A_UINT8 maxRetries,
73576 +                         A_UINT8 enableNotify)
73577 +{
73578 +    void *osbuf;
73579 +    WMI_SET_RETRY_LIMITS_CMD *cmd;
73580 +
73581 +    if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) &&
73582 +        (frameType != DATA_FRAMETYPE))
73583 +    {
73584 +        return A_EINVAL;
73585 +    }
73586 +
73587 +    if (maxRetries > WMI_MAX_RETRIES) {
73588 +        return A_EINVAL;
73589 +    }
73590 +
73591 +    if (frameType != DATA_FRAMETYPE) {
73592 +        trafficClass = 0;
73593 +    }
73594 +
73595 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73596 +    if (osbuf == NULL) {
73597 +        return A_NO_MEMORY;
73598 +    }
73599 +
73600 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73601 +
73602 +    cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf));
73603 +    cmd->frameType    = frameType;
73604 +    cmd->trafficClass = trafficClass;
73605 +    cmd->maxRetries   = maxRetries;
73606 +    cmd->enableNotify = enableNotify;
73607 +
73608 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID,
73609 +                         NO_SYNC_WMIFLAG));
73610 +}
73611 +
73612 +void
73613 +wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid)
73614 +{
73615 +    if (bssid != NULL) {
73616 +        A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN);
73617 +    }
73618 +}
73619 +
73620 +A_STATUS
73621 +wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode)
73622 +{
73623 +    void *osbuf;
73624 +    WMI_SET_OPT_MODE_CMD *cmd;
73625 +
73626 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73627 +    if (osbuf == NULL) {
73628 +        return A_NO_MEMORY;
73629 +    }
73630 +
73631 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73632 +
73633 +    cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf));
73634 +    A_MEMZERO(cmd, sizeof(*cmd));
73635 +    cmd->optMode = optMode;
73636 +
73637 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID,
73638 +                         SYNC_BOTH_WMIFLAG));
73639 +}
73640 +
73641 +A_STATUS
73642 +wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
73643 +                      A_UINT8 frmType,
73644 +                      A_UINT8 *dstMacAddr,
73645 +                      A_UINT8 *bssid,
73646 +                      A_UINT16 optIEDataLen,
73647 +                      A_UINT8 *optIEData)
73648 +{
73649 +    void *osbuf;
73650 +    WMI_OPT_TX_FRAME_CMD *cmd;
73651 +    osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd));
73652 +    if (osbuf == NULL) {
73653 +        return A_NO_MEMORY;
73654 +    }
73655 +
73656 +    A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd)));
73657 +
73658 +    cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf));
73659 +    A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1));
73660 +
73661 +    cmd->frmType    = frmType;
73662 +    cmd->optIEDataLen   = optIEDataLen;
73663 +    //cmd->optIEData     = (A_UINT8 *)((int)cmd + sizeof(*cmd));
73664 +    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
73665 +    A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr));
73666 +    A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen);
73667 +
73668 +    return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID,
73669 +                         NO_SYNC_WMIFLAG));
73670 +}
73671 +
73672 +A_STATUS
73673 +wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl)
73674 +{
73675 +    void *osbuf;
73676 +    WMI_BEACON_INT_CMD *cmd;
73677 +
73678 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73679 +    if (osbuf == NULL) {
73680 +        return A_NO_MEMORY;
73681 +    }
73682 +
73683 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73684 +
73685 +    cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf));
73686 +    A_MEMZERO(cmd, sizeof(*cmd));
73687 +    cmd->beaconInterval = intvl;
73688 +
73689 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID,
73690 +            NO_SYNC_WMIFLAG));
73691 +}
73692 +
73693 +
73694 +A_STATUS
73695 +wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize)
73696 +{
73697 +    void *osbuf;
73698 +    WMI_SET_VOICE_PKT_SIZE_CMD *cmd;
73699 +
73700 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73701 +    if (osbuf == NULL) {
73702 +        return A_NO_MEMORY;
73703 +    }
73704 +
73705 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73706 +
73707 +    cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf));
73708 +    A_MEMZERO(cmd, sizeof(*cmd));
73709 +    cmd->voicePktSize = voicePktSize;
73710 +
73711 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID,
73712 +            NO_SYNC_WMIFLAG));
73713 +}
73714 +
73715 +
73716 +A_STATUS
73717 +wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen)
73718 +{
73719 +    void *osbuf;
73720 +    WMI_SET_MAX_SP_LEN_CMD *cmd;
73721 +
73722 +    /* maxSPLen is a two-bit value. If user trys to set anything
73723 +     * other than this, then its invalid
73724 +     */
73725 +    if(maxSPLen & ~0x03)
73726 +        return  A_EINVAL;
73727 +
73728 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73729 +    if (osbuf == NULL) {
73730 +        return A_NO_MEMORY;
73731 +    }
73732 +
73733 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73734 +
73735 +    cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf));
73736 +    A_MEMZERO(cmd, sizeof(*cmd));
73737 +    cmd->maxSPLen = maxSPLen;
73738 +
73739 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID,
73740 +            NO_SYNC_WMIFLAG));
73741 +}
73742 +
73743 +A_UINT8
73744 +convert_userPriority_to_trafficClass(A_UINT8 userPriority)
73745 +{
73746 +        return  (up_to_ac[userPriority & 0x7]);
73747 +}
73748 +
73749 +A_UINT8
73750 +wmi_get_power_mode_cmd(struct wmi_t *wmip)
73751 +{
73752 +    return wmip->wmi_powerMode;
73753 +}
73754 +
73755 +A_STATUS
73756 +wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance)
73757 +{
73758 +    return A_OK;
73759 +}
73760 +
73761 +#ifdef CONFIG_HOST_TCMD_SUPPORT
73762 +static A_STATUS
73763 +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
73764 +{
73765 +
73766 +   A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
73767 +
73768 +   A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len);
73769 +
73770 +   return A_OK;
73771 +}
73772 +
73773 +#endif /* CONFIG_HOST_TCMD_SUPPORT*/
73774 +
73775 +A_STATUS
73776 +wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
73777 +{
73778 +    void *osbuf;
73779 +    WMI_SET_AUTH_MODE_CMD *cmd;
73780 +
73781 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73782 +    if (osbuf == NULL) {
73783 +        return A_NO_MEMORY;
73784 +    }
73785 +
73786 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73787 +
73788 +    cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf));
73789 +    A_MEMZERO(cmd, sizeof(*cmd));
73790 +    cmd->mode = mode;
73791 +
73792 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID,
73793 +            NO_SYNC_WMIFLAG));
73794 +}
73795 +
73796 +A_STATUS
73797 +wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
73798 +{
73799 +    void *osbuf;
73800 +    WMI_SET_REASSOC_MODE_CMD *cmd;
73801 +
73802 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73803 +    if (osbuf == NULL) {
73804 +        return A_NO_MEMORY;
73805 +    }
73806 +
73807 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73808 +
73809 +    cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf));
73810 +    A_MEMZERO(cmd, sizeof(*cmd));
73811 +    cmd->mode = mode;
73812 +
73813 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID,
73814 +            NO_SYNC_WMIFLAG));
73815 +}
73816 +
73817 +A_STATUS
73818 +wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status)
73819 +{
73820 +    void *osbuf;
73821 +    WMI_SET_LPREAMBLE_CMD *cmd;
73822 +
73823 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73824 +    if (osbuf == NULL) {
73825 +        return A_NO_MEMORY;
73826 +    }
73827 +
73828 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73829 +
73830 +    cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf));
73831 +    A_MEMZERO(cmd, sizeof(*cmd));
73832 +    cmd->status = status;
73833 +
73834 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID,
73835 +            NO_SYNC_WMIFLAG));
73836 +}
73837 +
73838 +A_STATUS
73839 +wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold)
73840 +{
73841 +    void *osbuf;
73842 +    WMI_SET_RTS_CMD *cmd;
73843 +
73844 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73845 +    if (osbuf == NULL) {
73846 +        return A_NO_MEMORY;
73847 +    }
73848 +
73849 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73850 +
73851 +    cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf));
73852 +    A_MEMZERO(cmd, sizeof(*cmd));
73853 +    cmd->threshold = threshold;
73854 +
73855 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID,
73856 +            NO_SYNC_WMIFLAG));
73857 +}
73858 +
73859 +A_STATUS
73860 +wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status)
73861 +{
73862 +    void *osbuf;
73863 +    WMI_SET_WMM_CMD *cmd;
73864 +
73865 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73866 +    if (osbuf == NULL) {
73867 +        return A_NO_MEMORY;
73868 +    }
73869 +
73870 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73871 +
73872 +    cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf));
73873 +    A_MEMZERO(cmd, sizeof(*cmd));
73874 +    cmd->status = status;
73875 +
73876 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID,
73877 +            NO_SYNC_WMIFLAG));
73878 +
73879 +}
73880 +
73881 +A_STATUS
73882 +wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg)
73883 +{
73884 +    void *osbuf;
73885 +    WMI_SET_WMM_TXOP_CMD *cmd;
73886 +
73887 +    if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) )
73888 +        return A_EINVAL;
73889 +
73890 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73891 +    if (osbuf == NULL) {
73892 +        return A_NO_MEMORY;
73893 +    }
73894 +
73895 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73896 +
73897 +    cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf));
73898 +    A_MEMZERO(cmd, sizeof(*cmd));
73899 +    cmd->txopEnable = cfg;
73900 +
73901 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID,
73902 +            NO_SYNC_WMIFLAG));
73903 +
73904 +}
73905 +
73906 +#ifdef CONFIG_HOST_TCMD_SUPPORT
73907 +/* WMI  layer doesn't need to know the data type of the test cmd.
73908 +   This would be beneficial for customers like Qualcomm, who might
73909 +   have different test command requirements from differnt manufacturers
73910 + */
73911 +A_STATUS
73912 +wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32  len)
73913 +{
73914 +    void *osbuf;
73915 +    char *data;
73916 +
73917 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
73918 +
73919 +    osbuf= A_NETBUF_ALLOC(len);
73920 +    if(osbuf == NULL)
73921 +    {
73922 +        return A_NO_MEMORY;
73923 +    }
73924 +    A_NETBUF_PUT(osbuf, len);
73925 +    data = A_NETBUF_DATA(osbuf);
73926 +    A_MEMCPY(data, buf, len);
73927 +
73928 +    return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID,
73929 +         NO_SYNC_WMIFLAG));
73930 +}
73931 +
73932 +#endif
73933 +
73934 +A_STATUS
73935 +wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status)
73936 +{
73937 +    void *osbuf;
73938 +    WMI_SET_BT_STATUS_CMD *cmd;
73939 +
73940 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73941 +    if (osbuf == NULL) {
73942 +        return A_NO_MEMORY;
73943 +    }
73944 +
73945 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73946 +
73947 +    cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf));
73948 +    A_MEMZERO(cmd, sizeof(*cmd));
73949 +    cmd->streamType = streamType;
73950 +    cmd->status = status;
73951 +
73952 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID,
73953 +            NO_SYNC_WMIFLAG));
73954 +}
73955 +
73956 +A_STATUS
73957 +wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd)
73958 +{
73959 +    void *osbuf;
73960 +    WMI_SET_BT_PARAMS_CMD* alloc_cmd;
73961 +
73962 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73963 +    if (osbuf == NULL) {
73964 +        return A_NO_MEMORY;
73965 +    }
73966 +
73967 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73968 +
73969 +    alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
73970 +    A_MEMZERO(alloc_cmd, sizeof(*cmd));
73971 +    A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd));
73972 +
73973 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID,
73974 +            NO_SYNC_WMIFLAG));
73975 +}
73976 +
73977 +A_STATUS
73978 +wmi_get_keepalive_configured(struct wmi_t *wmip)
73979 +{
73980 +    void *osbuf;
73981 +    WMI_GET_KEEPALIVE_CMD *cmd;
73982 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73983 +    if (osbuf == NULL) {
73984 +        return A_NO_MEMORY;
73985 +    }
73986 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73987 +    cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
73988 +    A_MEMZERO(cmd, sizeof(*cmd));
73989 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID,
73990 +                         NO_SYNC_WMIFLAG));
73991 +}
73992 +
73993 +A_UINT8
73994 +wmi_get_keepalive_cmd(struct wmi_t *wmip)
73995 +{
73996 +    return wmip->wmi_keepaliveInterval;
73997 +}
73998 +
73999 +A_STATUS
74000 +wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval)
74001 +{
74002 +    void *osbuf;
74003 +    WMI_SET_KEEPALIVE_CMD *cmd;
74004 +
74005 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74006 +    if (osbuf == NULL) {
74007 +        return A_NO_MEMORY;
74008 +    }
74009 +
74010 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74011 +
74012 +    cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
74013 +    A_MEMZERO(cmd, sizeof(*cmd));
74014 +    cmd->keepaliveInterval = keepaliveInterval;
74015 +    wmip->wmi_keepaliveInterval = keepaliveInterval;
74016 +
74017 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID,
74018 +                         NO_SYNC_WMIFLAG));
74019 +}
74020 +
74021 +A_STATUS
74022 +wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen,
74023 +                  A_UINT8 *ieInfo)
74024 +{
74025 +    void *osbuf;
74026 +    WMI_SET_APPIE_CMD *cmd;
74027 +    A_UINT16 cmdLen;
74028 +
74029 +    if (ieLen > WMI_MAX_IE_LEN) {
74030 +        return A_ERROR;
74031 +    }
74032 +    cmdLen = sizeof(*cmd) + ieLen - 1;
74033 +    osbuf = A_NETBUF_ALLOC(cmdLen);
74034 +    if (osbuf == NULL) {
74035 +        return A_NO_MEMORY;
74036 +    }
74037 +
74038 +    A_NETBUF_PUT(osbuf, cmdLen);
74039 +
74040 +    cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf));
74041 +    A_MEMZERO(cmd, cmdLen);
74042 +
74043 +    cmd->mgmtFrmType = mgmtFrmType;
74044 +    cmd->ieLen = ieLen;
74045 +    A_MEMCPY(cmd->ieInfo, ieInfo, ieLen);
74046 +
74047 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG));
74048 +}
74049 +
74050 +A_STATUS
74051 +wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen)
74052 +{
74053 +    void *osbuf;
74054 +    A_UINT8 *data;
74055 +
74056 +    osbuf = A_NETBUF_ALLOC(dataLen);
74057 +    if (osbuf == NULL) {
74058 +        return A_NO_MEMORY;
74059 +    }
74060 +
74061 +    A_NETBUF_PUT(osbuf, dataLen);
74062 +
74063 +    data = A_NETBUF_DATA(osbuf);
74064 +
74065 +    A_MEMCPY(data, cmd, dataLen);
74066 +
74067 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG));
74068 +}
74069 +
74070 +A_INT32
74071 +wmi_get_rate(A_INT8 rateindex)
74072 +{
74073 +    if (rateindex == RATE_AUTO) {
74074 +        return 0;
74075 +    } else {
74076 +        return(wmi_rateTable[(A_UINT32) rateindex]);
74077 +    }
74078 +}
74079 +
74080 +void
74081 +wmi_node_return (struct wmi_t *wmip, bss_t *bss)
74082 +{
74083 +       if (NULL != bss)
74084 +       {
74085 +               wlan_node_return (&wmip->wmi_scan_table, bss);
74086 +       }
74087 +}
74088 +
74089 +bss_t *
74090 +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
74091 +                                  A_UINT32 ssidLength, A_BOOL bIsWPA2)
74092 +{
74093 +       bss_t *node = NULL;
74094 +    node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid,
74095 +                                                          ssidLength, bIsWPA2);
74096 +       return node;
74097 +}
74098 +
74099 +void
74100 +wmi_free_allnodes(struct wmi_t *wmip)
74101 +{
74102 +       wlan_free_allnodes(&wmip->wmi_scan_table);
74103 +}
74104 +
74105 +bss_t *
74106 +wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr)
74107 +{
74108 +       bss_t *ni=NULL;
74109 +       ni=wlan_find_node(&wmip->wmi_scan_table,macaddr);
74110 +       return ni;
74111 +}
74112 +
74113 +A_STATUS
74114 +wmi_dset_open_reply(struct wmi_t *wmip,
74115 +                    A_UINT32 status,
74116 +                    A_UINT32 access_cookie,
74117 +                    A_UINT32 dset_size,
74118 +                    A_UINT32 dset_version,
74119 +                    A_UINT32 targ_handle,
74120 +                    A_UINT32 targ_reply_fn,
74121 +                    A_UINT32 targ_reply_arg)
74122 +{
74123 +    void *osbuf;
74124 +    WMIX_DSETOPEN_REPLY_CMD *open_reply;
74125 +
74126 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%x\n", DBGARG, (int)wmip));
74127 +
74128 +    osbuf = A_NETBUF_ALLOC(sizeof(*open_reply));
74129 +    if (osbuf == NULL) {
74130 +        return A_NO_MEMORY;
74131 +    }
74132 +
74133 +    A_NETBUF_PUT(osbuf, sizeof(*open_reply));
74134 +    open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
74135 +
74136 +    open_reply->status                   = status;
74137 +    open_reply->targ_dset_handle         = targ_handle;
74138 +    open_reply->targ_reply_fn            = targ_reply_fn;
74139 +    open_reply->targ_reply_arg           = targ_reply_arg;
74140 +    open_reply->access_cookie            = access_cookie;
74141 +    open_reply->size                     = dset_size;
74142 +    open_reply->version                  = dset_version;
74143 +
74144 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID,
74145 +                             NO_SYNC_WMIFLAG));
74146 +}
74147 +
74148 +static A_STATUS
74149 +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len)
74150 +{
74151 +    WMI_PMKID_LIST_REPLY *reply;
74152 +    A_UINT32 expected_len;
74153 +
74154 +    if (len < sizeof(WMI_PMKID_LIST_REPLY)) {
74155 +        return A_EINVAL;
74156 +    }
74157 +    reply = (WMI_PMKID_LIST_REPLY *)datap;
74158 +    expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN;
74159 +
74160 +    if (len < expected_len) {
74161 +        return A_EINVAL;
74162 +    }
74163 +
74164 +    A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID,
74165 +                           reply->pmkidList);
74166 +
74167 +    return A_OK;
74168 +}
74169 +
74170 +#ifdef CONFIG_HOST_DSET_SUPPORT
74171 +A_STATUS
74172 +wmi_dset_data_reply(struct wmi_t *wmip,
74173 +                    A_UINT32 status,
74174 +                    A_UINT8 *user_buf,
74175 +                    A_UINT32 length,
74176 +                    A_UINT32 targ_buf,
74177 +                    A_UINT32 targ_reply_fn,
74178 +                    A_UINT32 targ_reply_arg)
74179 +{
74180 +    void *osbuf;
74181 +    WMIX_DSETDATA_REPLY_CMD *data_reply;
74182 +    int size;
74183 +
74184 +    size = sizeof(*data_reply) + length;
74185 +
74186 +    A_DPRINTF(DBG_WMI,
74187 +        (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status));
74188 +
74189 +    osbuf = A_NETBUF_ALLOC(size);
74190 +    if (osbuf == NULL) {
74191 +        return A_NO_MEMORY;
74192 +    }
74193 +    A_NETBUF_PUT(osbuf, size);
74194 +    data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
74195 +
74196 +    data_reply->status                     = status;
74197 +    data_reply->targ_buf                   = targ_buf;
74198 +    data_reply->targ_reply_fn              = targ_reply_fn;
74199 +    data_reply->targ_reply_arg             = targ_reply_arg;
74200 +    data_reply->length                     = length;
74201 +
74202 +    if (status == A_OK) {
74203 +        if (a_copy_from_user(data_reply->buf, user_buf, length)) {
74204 +            return A_ERROR;
74205 +        }
74206 +    }
74207 +
74208 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID,
74209 +                             NO_SYNC_WMIFLAG));
74210 +}
74211 +#endif /* CONFIG_HOST_DSET_SUPPORT */
74212 +
74213 +A_STATUS
74214 +wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status)
74215 +{
74216 +    void *osbuf;
74217 +    char *cmd;
74218 +
74219 +       wps_enable = status;
74220 +
74221 +    osbuf = a_netbuf_alloc(sizeof(1));
74222 +    if (osbuf == NULL) {
74223 +        return A_NO_MEMORY;
74224 +    }
74225 +
74226 +    a_netbuf_put(osbuf, sizeof(1));
74227 +
74228 +    cmd = (char *)(a_netbuf_to_data(osbuf));
74229 +
74230 +    A_MEMZERO(cmd, sizeof(*cmd));
74231 +    cmd[0] = (status?1:0);
74232 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID,
74233 +                         NO_SYNC_WMIFLAG));
74234 +}
74235 +
74236 --- /dev/null
74237 +++ b/drivers/ar6000/wmi/wmi_doc.h
74238 @@ -0,0 +1,4421 @@
74239 +/*
74240 + *
74241 + * Copyright (c) 2004-2007 Atheros Communications Inc.
74242 + * All rights reserved.
74243 + *
74244 + *
74245 + *  This program is free software; you can redistribute it and/or modify
74246 + *  it under the terms of the GNU General Public License version 2 as
74247 + *  published by the Free Software Foundation;
74248 + *
74249 + *  Software distributed under the License is distributed on an "AS
74250 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
74251 + *  implied. See the License for the specific language governing
74252 + *  rights and limitations under the License.
74253 + *
74254 + *
74255 + *
74256 + */
74257 +
74258 +
74259 +#if 0
74260 +Wireless Module Interface (WMI) Documentaion
74261 +
74262 +   This section describes the format and the usage model for WMI control and
74263 +   data messages between the host and the AR6000-based targets. The header
74264 +   file include/wmi.h contains all command and event manifest constants as
74265 +   well as structure typedefs for each set of command and reply parameters.
74266 +
74267 +Data Frames
74268 +
74269 +   The data payload transmitted and received by the target follows RFC-1042
74270 +   encapsulation and thus starts with an 802.2-style LLC-SNAP header. The
74271 +   WLAN module completes 802.11 encapsulation of the payload, including the
74272 +   MAC header, FCS, and WLAN security related fields. At the interface to the
74273 +   message transport (HTC), a data frame is encapsulated in a WMI message.
74274 +
74275 +WMI Message Structure
74276 +
74277 +   The WMI protocol leverages an 802.3-style Ethernet header in communicating
74278 +   the source and destination information between the host and the AR6000
74279 +   modules using a 14-byte 802.3 header ahead of the 802.2-style payload. In
74280 +   addition, the WMI protocol adds a header to all data messages:
74281 +
74282 +    {
74283 +    INT8    rssi
74284 +                  The RSSI of the received packet and its units are shown in db above the
74285 +                      noise floor, and the noise floor is shown in dbm.
74286 +    UINT8   info
74287 +                      Contains information on message type and user priority. Message type
74288 +                      differentiates between a data packet and a synchronization message.
74289 +    } WMI_DATA_HDR
74290 +
74291 +   User priority contains the 802.1d user priority info from host to target. Host
74292 +   software translates the host Ethernet format to 802.3 format prior to Tx and
74293 +   802.3 format to host format in the Rx direction. The host does not transmit the
74294 +   FCS that follows the data. MsgType differentiates between a regular data
74295 +   packet (msgType=0) and a synchronization message (msgType=1).
74296 +
74297 +Data Endpoints
74298 +
74299 +   The AR6000 chipset provides several data endpoints to support quality of
74300 +   service (QoS) and maintains separate queues and separate DMA engines for
74301 +   each data endpoint. A data endpoint can be bi-directional.
74302 +
74303 +   Best effort (BE) class traffic uses the default data endpoint (2). The host can
74304 +   establish up to two additional data endpoints for other traffic classes. Once
74305 +   such a data endpoint is established, it sends and receives corresponding QoS
74306 +   traffic in a manner similar to the default data endpoint.
74307 +
74308 +   If QoS is desired over the interconnect, host software must classify each data
74309 +   packet and place it on the appropriate data endpoint. The information
74310 +   required to classify data is generally available in-band as an 802.1p/q style
74311 +   tag or as the ToS field in the IP header. The information may also be available
74312 +   out-of-band depending on the host DDI.
74313 +
74314 +Connection States
74315 +
74316 +   Table B-1 describes the AR6000 WLAN connection states:
74317 +
74318 +   Table B-1.  AR6000 Connection States
74319 +
74320 +Connection State
74321 +    Description
74322 +
74323 +   DISCONNECTED
74324 +    In this state, the AR6000 device is not connected to a wireless
74325 +   network. The device is in this state after reset when it sends the
74326 +   WIRELESS MODULE \93READY\94 EVENT, after it processes a
74327 +   DISCONNECT command, and when it loses its link with the
74328 +   access point (AP) that it was connected to. The device signals a
74329 +   transition to the DISCONNECTED state with a \93DISCONNECT\94
74330 +   event.
74331 +
74332 +CONNECTED
74333 +    In this state, the AR6000 device is connected to wireless networks.
74334 +   The device enters this state after successfully processing a
74335 +   CONNECT, which establishes a connection with a wireless
74336 +   network. The device signals a transition to the CONNECTED state
74337 +   with a \93CONNECT\94 event.
74338 +
74339 +
74340 +Message Types
74341 +
74342 +   WMI uses commands, replies, and events for the control and configuration of
74343 +   the AR6000 device. The control protocol is asynchronous. Table B-2 describes
74344 +   AR6000 message types:
74345 +
74346 +Table B-2.  AR6000 Message Types
74347 +
74348 +Message Type
74349 +    Description
74350 +
74351 +Commands
74352 +    Control messages that flow from the host to the device
74353 +
74354 +Replies/Events
74355 +    Control messages that flow from the device to the host.
74356 +
74357 +   The device issues a reply to some WMI commands, but not to others.
74358 +   The payload in a reply is command-specific, and some commands do
74359 +   not trigger a reply message at all. Events are control messages issued
74360 +   by the device to signal the occurrence of an asynchronous event.
74361 +
74362 +
74363 +WMI Message Format
74364 +
74365 +   All WMI control commands, replies and events use the header format:
74366 +
74367 +   WMI_CMD_HDR Header Format
74368 +   {
74369 +        UINT16 id
74370 +                 This 16-bit constant identifies which WMI command the host is issuing,
74371 +                 which command the target is replying to, or which event has occurred.
74372 +        WMI_CMD_HDR
74373 +   }
74374 +
74375 +
74376 +   A variable-size command-, reply-, or event-specific payload follows the
74377 +   header. Over the interconnect, all fields in control messages (including
74378 +   WMI_CMD_HDR and the command specific payload) use 32-bit little Endian
74379 +   byte ordering and fields are packed. The AR6000 device always executes
74380 +   commands in order, and the host may send multiple commands without
74381 +   waiting for previous commands to complete. A majority of commands are
74382 +   processed to completion once received. Other commands trigger a longer
74383 +   duration activity whose completion is signaled to the host through an event.
74384 +
74385 +Command Restrictions
74386 +
74387 +   Some commands may only be issued when the AR6000 device is in a certain
74388 +   state. The host is required to wait for an event signaling a state transition
74389 +   before such a command can be issued. For example, if a command requires
74390 +   the device to be in the CONNECTED state, then the host is required to wait
74391 +   for a \93CONNECT\94 event before it issues that command.
74392 +
74393 +   The device ignores any commands inappropriate for its current state. If the
74394 +   command triggers a reply, the device generates an error reply. Otherwise, the
74395 +   device silently ignores the inappropriate command.
74396 +
74397 +Command and Data Synchronization
74398 +
74399 +   WMI provides a mechanism for a host to advise the device of necessary
74400 +   synchronization between commands and data. The device implements
74401 +   synchronization; no implicit synchronization exists between endpoints.
74402 +
74403 +   The host controls synchronization using the \93SYNCHRONIZE\94 command
74404 +   over the control channel and synchronization messages over data channels.
74405 +   The device stops each data channel upon receiving a synchronization message
74406 +   on that channel, processing all data packets received prior to that message.
74407 +   After the device receives synchronization messages for each data endpoint
74408 +   and the \93SYNCHRONIZE\94 command, it resumes all channels.
74409 +
74410 +   When the host must guarantee a command executes before processing new
74411 +   data packets, it first issues the command, then issues the \93SYNCHRONIZE\94
74412 +   command and sends synchronization messages on data channels. When the
74413 +   host must guarantee the device has processed all old data packets before a
74414 +   processing a new command, it issues a \93SYNCHRONIZE\94 command and
74415 +   synchronization messages on all data channels, then issues the desired
74416 +   command.
74417 +
74418 +
74419 +
74420 +WMI Commands
74421 +
74422 +   ADD_BAD_AP
74423 +    Cause the AR6000 device to avoid a particular AP
74424 +   ADD_CIPHER_KEY
74425 +    Add or replace any of the four AR6000 encryption keys
74426 +   ADD_WOW_PATTERN
74427 +    Used to add a pattern to the WoW pattern list
74428 +   CLR_RSSI_SNR
74429 +    Clear the current calculated RSSI and SNR value
74430 +   CONNECT_CMD
74431 +    Request that the AR6000 device establish a wireless connection
74432 +        with the specified SSID
74433 +   CREATE_PSTREAM
74434 +    Create prioritized data endpoint between the host and device
74435 +   DELETE_BAD_AP
74436 +    Clear an entry in the bad AP table
74437 +   DELETE_CIPHER_KEY
74438 +    Delete a previously added cipher key
74439 +   DELETE_PSTREAM
74440 +    Delete a prioritized data endpoint
74441 +   DELETE_WOW_PATTERN
74442 +    Remove a pre-specified pattern from the WoW pattern list
74443 +   EXTENSION
74444 +    WMI message interface command
74445 +   GET_BIT_RATE
74446 +    Retrieve rate most recently used by the AR6000
74447 +   GET_CHANNEL_LIST
74448 +    Retrieve list of channels used by the AR6000
74449 +   GET_FIXRATES
74450 +    Retrieves the rate-mask set via the SET_FIXRATES command.
74451 +   GET_PMKID_LIST_CMD
74452 +    Retrieve the firmware list of PMKIDs
74453 +   GET_ROAM_DATA
74454 +    Internal use for data collection; available in special build only
74455 +   GET_ROAM_TBL
74456 +    Retrieve the roaming table maintained on the target
74457 +   GET_TARGET_STATS
74458 +    Request that the target send the statistics it maintains
74459 +   GET_TX_PWR
74460 +    Retrieve the current AR6000 device Tx power levels
74461 +   GET_WOW_LIST
74462 +    Retrieve the current list of WoW patterns
74463 +   LQ_THRESHOLD_PARAMS
74464 +    Set the link quality thresholds
74465 +   OPT_TX_FRAME
74466 +    Send a special frame (special feature)
74467 +   RECONNECT
74468 +    Request a reconnection to a BSS
74469 +   RSSI_THRESHOLD_PARAMS
74470 +    Configure how the AR6000 device monitors and reports signal
74471 +       strength (RSSI) of the connected BSS
74472 +   SCAN_PARAMS
74473 +    Determine dwell time and changes scanned channels
74474 +   SET_ACCESS_PARAMS
74475 +    Set access parameters for the wireless network
74476 +   SET_ADHOC_BSSID
74477 +    Set the BSSID for an ad hoc network
74478 +   SET_AKMP_PARAMS
74479 +    Set multiPMKID mode
74480 +   SET_APPIE
74481 +    Add application-specified IE to a management frame
74482 +   SET_ASSOC_INFO
74483 +    Specify the IEs the device should add to association or
74484 +        reassociation requests
74485 +   SET_AUTH_MODE
74486 +    Set 802.11 authentication mode of reconnection
74487 +   SET_BEACON_INT
74488 +    Set the beacon interval for an ad hoc network
74489 +   SET_BIT_RATE
74490 +    Set the AR6000 to a specific fixed bit rate
74491 +   SET_BMISS_TIME
74492 +    Set the beacon miss time
74493 +   SET_BSS_FILTER
74494 +    Inform the AR6000 of network types about which it wants to
74495 +        receive information using a \93BSSINFO\94 event
74496 +   SET_BT_PARAMS
74497 +    Set the status of a Bluetooth stream (SCO or A2DP) or set
74498 +        Bluetooth coexistence register parameters
74499 +   SET_BT_STATUS
74500 +    Set the status of a Bluetooth stream (SCO or A2DP)
74501 +   SET_CHANNEL_PARAMETERS
74502 +    Configure WLAN channel parameters
74503 +   SET_DISC_TIMEOUT
74504 +    Set the amount of time the AR6000 spends attempting to
74505 +        reestablish a connection
74506 +   SET_FIXRATES
74507 +    Set the device to a specific fixed PHY rate (supported subset)
74508 +   SET_HALPARAM
74509 +    Internal AR6000 command to set certain hardware parameters
74510 +   SET_HOST_SLEEP_MODE
74511 +    Set the host mode to asleep or awake
74512 +   SET_IBSS_PM_CAPS
74513 +    Support a non-standard power management scheme for an
74514 +        ad hoc network
74515 +   SET_LISTEN_INT
74516 +    Request a listen interval
74517 +   SET_LPREAMBLE
74518 +    Override the short preamble capability of the AR6000 device
74519 +   SET_MAX_SP_LEN
74520 +    Set the maximum service period
74521 +   SET_OPT_MODE
74522 +    Set the special mode on/off (special feature)
74523 +   SET_PMKID
74524 +    Set the pairwise master key ID (PMKID)
74525 +   SET_PMKID_LIST_CMD
74526 +    Configure the firmware list of PMKIDs
74527 +   SET_POWER_MODE
74528 +    Set guidelines on trade-off between power utilization
74529 +   SET_POWER_PARAMS
74530 +    Configure power parameters
74531 +   SET_POWERSAVE_PARAMS
74532 +    Set the two AR6000 power save timers
74533 +   SET_PROBED_SSID
74534 +    Provide list of SSIDs the device should seek
74535 +   SET_REASSOC_MODE
74536 +    Specify whether the disassociated frame should be sent upon
74537 +        reassociation
74538 +   SET_RETRY_LIMITS
74539 +    Limit how many times the device tries to send a frame
74540 +   SET_ROAM_CTRL
74541 +    Control roaming behavior
74542 +   SET_RTS
74543 +    Determine when RTS should be sent
74544 +   SET_SCAN_PARAMS
74545 +    Set the AR6000 scan parameters
74546 +   SET_TKIP_COUNTERMEASURES
74547 +    Enable/disable reports of TKIP MIC errors
74548 +   SET_TX_PWR
74549 +    Specify the AR6000 device Tx power levels
74550 +   SET_VOICE_PKT_SIZE
74551 +    Set voice packet size
74552 +   SET_WMM
74553 +    Override the AR6000 WMM capability
74554 +   SET_WMM_TXOP
74555 +    Configure TxOP bursting when sending traffic to a WMM-
74556 +    capable AP
74557 +   SET_WOW_MODE
74558 +    Enable/disable WoW mode
74559 +   SET_WSC_STATUS
74560 +    Enable/disable profile check in cserv when the WPS protocol
74561 +    is in progress
74562 +   SNR_THRESHOLD_PARAMS
74563 +    Configure how the device monitors and reports SNR of BSS
74564 +   START_SCAN
74565 +    Start a long or short channel scan
74566 +   SYNCHRONIZE
74567 +    Force a synchronization point between command and data
74568 +    paths
74569 +   TARGET_REPORT_ERROR_BITMASK
74570 +    Control \93ERROR_REPORT\94 events from the AR6000
74571 +
74572 +
74573 +
74574 +
74575 +Name
74576 +    ADD_BAD_AP
74577 +
74578 +Synopsis
74579 +    The host uses this command to cause the AR6000 to avoid a particular AP. The
74580 +    AR6000 maintain a table with up to two APs to avoid. An ADD_BAD_AP command
74581 +    adds or replaces the specified entry in this bad AP table.
74582 +
74583 +    If the AR6000 are currently connected to the AP specified in this command, they
74584 +    disassociate.
74585 +
74586 +Command
74587 +    wmiconfig eth1 --badap <bssid> <badApIndex>
74588 +
74589 +Command Parameters
74590 +    UINT8 badApIndex    Index [0...1] that identifies which entry in the
74591 +                        bad AP table to use
74592 +
74593 +
74594 +    UINT8 bssid[6]  MAC address of the AP to avoid
74595 +
74596 +Command Values
74597 +    badApIndex = 0, 1    Entry in the bad AP table to use
74598 +
74599 +Reset Value
74600 +    The bad AP table is cleared
74601 +
74602 +Restrictions
74603 +    None
74604 +
74605 +See Also
74606 +    \93DELETE_BAD_AP\94 on page B-13
74607 +
74608 +=====================================================================
74609 +Name
74610 +    ADD_CIPHER_KEY
74611 +
74612 +Synopsis
74613 +    The host uses this command to add/replace any of four encryption keys on the
74614 +    AR6000. The ADD_CIPHER_KEY command is issued after the CONNECT event
74615 +    has been received by the host for all dot11Auth modes except for SHARED_AUTH.
74616 +    When the dot11AuthMode is SHARED_AUTH, then the ADD_CIPHER_KEY
74617 +    command should be issued before the \93CONNECT\94 command.
74618 +
74619 +Command
74620 +    wmiconfig eth1 --cipherkey <keyIndex> <keyType> <keyUsage>
74621 +                            <keyLength> <keyopctrl> <keyRSC> <key>
74622 +
74623 +Command Parameters
74624 +    UINT8 keyIndex      Index (0...3) of the key to add/replace;
74625 +                        uniquely identifies the key
74626 +    UINT8 keyType    CRYPTO_TYPE
74627 +    UINT8 keyUsage   Specifies usage parameters of the key when
74628 +                     keyType = WEP_CRYPT
74629 +    UINT8 keyLength  Length of the key in bytes
74630 +    UINT8 keyOpCtrl  bit[0] = Initialize TSC (default),
74631 +                     bit[1] = Initialize RSC
74632 +    UINT8 keyRSC[8]  Key replay sequence counter (RSC) initial
74633 +                     value the device should use
74634 +    UINT8 key[32]    Key material used for this connection
74635 +    Command Values
74636 +    {
74637 +        NONE_CRYPT = 1
74638 +        WEP_CRYPT  = 2
74639 +        TKIP_CRYPT = 3
74640 +        AES_CRYPT  = 4
74641 +        KEY_OP_INIT_TSC   0x01
74642 +        KEY_OP_INIT_RSC   0x02
74643 +        KEY_OP_INIT_VAL   0x03
74644 +                Default is to Initialize the TSC
74645 +        KEY_OP_VALID_MASK 0x04
74646 +                Two operations defined
74647 +    } CRYPTO_TYPE
74648 +
74649 +    {
74650 +        PAIRWISE_USAGE  = 0  Set if the key is used for unicast traffic only
74651 +        GROUP_USAGE     = 1  Set if the key is used to receive multicast
74652 +                              traffic (also set for static WEP keys)
74653 +        TX_USAGE        = 2  Set for the GROUP key used to transmit frames
74654 +                All others are reserved
74655 +    } KEY_USAGE
74656 +
74657 +Reset Value
74658 +    The four available keys are disabled.
74659 +
74660 +Restrictions
74661 +    The cipher should correspond to the encryption mode specified in the \93CONNECT\94
74662 +    command.
74663 +
74664 +See Also
74665 +    \93DELETE_CIPHER_KEY\94
74666 +
74667 +=====================================================================
74668 +
74669 +
74670 +Name
74671 +    ADD_WOW_PATTERN
74672 +
74673 +Synopsis
74674 +    The host uses this command to add a pattern to the WoW pattern list; used for
74675 +    pattern-matching for host wakeups by the WoW module. If the host mode is asleep
74676 +    and WoW is enabled, all packets are matched against the existing WoW patterns. If a
74677 +    packet matches any of the patterns specified, the target will wake up the host. All
74678 +    non-matching packets are discarded by the target without being sent up to the host.
74679 +
74680 +Command
74681 +    wmiconfig \96addwowpattern <list-id> <filter-size> <filter-offset>
74682 +    <pattern> <mask>
74683 +
74684 +Command Parameters
74685 +    A_UINT8  filter_list_id    ID of the list that is to include the new pattern
74686 +    A_UINT8  filter_size       Size of the new pattern
74687 +    A_UINT8  filter_offset     Offset at which the pattern matching for this
74688 +                                new pattern should begin at
74689 +    A_UINT8  filter[1]         Byte stream that contains both the pattern and
74690 +                                the mask of the new WoW wake-up pattern
74691 +
74692 +Reply Parameters
74693 +    None
74694 +
74695 +Reset Value
74696 +    None defined (default host mode is awake)
74697 +
74698 +Restrictions
74699 +    None
74700 +
74701 +See Also
74702 +    \93DELETE_WOW_PATTERN\94
74703 +
74704 +=====================================================================
74705 +
74706 +
74707 +Name
74708 +    CLR_RSSI_SNR
74709 +
74710 +Synopsis
74711 +    Clears the current calculated RSSI and SNR value. RSSI and SNR are reported by
74712 +    running-average value. This command will clear the history and have a fresh start
74713 +    for the running-average mechanism.
74714 +
74715 +Command
74716 +    wmiconfig eth1 --cleanRssiSnr
74717 +
74718 +Command Parameters
74719 +    None
74720 +
74721 +Reply Parameters
74722 +    None
74723 +
74724 +Reset Value
74725 +    None defined
74726 +
74727 +Restrictions
74728 +    None
74729 +
74730 +=====================================================================
74731 +
74732 +Name
74733 +    CONNECT_CMD
74734 +
74735 +Synopsis
74736 +    New connect control information (connectCtrl) is added, with 32 possible modifiers.
74737 +
74738 +    CONNECT_SEND_REASSOC
74739 +        Valid only for a host-controlled connection to a
74740 +        particular AP. If this bit is set, a reassociation frame is
74741 +        sent. If this bit is clear, an association request frame is
74742 +        sent to the AP.
74743 +
74744 +    CONNECT_IGNORE_WPAx_GROUP_CIPHER
74745 +        No group key is issued in the CONNECT command,
74746 +        so use the group key advertised by the AP. In a target-
74747 +        initiated roaming situation this allows a STA to roam
74748 +        between APs that support different multicast ciphers.
74749 +
74750 +    CONNECT_PROFILE_MATCH_DONE
74751 +        In a host-controlled connection case, it is possible that
74752 +        during connect, firmware may not have the
74753 +        information for a profile match (e.g, when the AP
74754 +        supports hidden SSIDs and the device may not
74755 +        transmit probe requests during connect). By setting
74756 +        this bit in the connection control information, the
74757 +        firmware waits for a beacon from the AP with the
74758 +        BSSID supplied in the CONNECT command. No
74759 +        additional profile checks are done.
74760 +
74761 +    CONNECT_IGNORE_AAC_BEACON
74762 +        Ignore the Admission Capacity information in the
74763 +        beacon of the AP
74764 +
74765 +    CONNECT_ASSOC_POLICY_USER
74766 +        When set, the CONNECT_SEND_REASSOC setting
74767 +        determines if an Assoc or Reassoc is sent to an AP
74768 +
74769 +Command
74770 +    wmiconfig --setconnectctrl <ctrl flags bitmask>
74771 +
74772 +Command Parameters
74773 +    typedef struct{
74774 +    A_UINT8 networktype;
74775 +    A_UINT8 dot11authmode;
74776 +    A_UINT8 authmode;
74777 +    A_UINT8 pairwiseCryptoType; /*CRYPTO_TYPE*/
74778 +    A_UINT8 pairwiseCryptoLen;
74779 +    A_UINT8 groupCryptoType; /*CRYPTO_TYPE*/
74780 +    A_UINT8 groupCryptoLen;
74781 +    A_UINT8 ssidLength;
74782 +    A_UCHAR ssid[WMI_MAX_SSID_LEN];
74783 +    A_UINT16 channel;
74784 +    A_UINT8 bssid[AUTH_MAC_LEN];
74785 +    A_UINT8 ctrl_flags; /*WMI_CONNECT_CTRL_FLAGS_BITS*/
74786 +    } WMI_CONNECT_CMD;
74787 +
74788 +    ctrl flags bitmask
74789 +        = 0x0001 CONNECT_ASSOC_POLICY_USER
74790 +            Assoc frames are sent using the policy specified by
74791 +            the flag
74792 +        = 0x0002 CONNECT_SEND_REASSOC
74793 +            Send Reassoc frame while connecting, otherwise send
74794 +            assoc frames
74795 +        = 0x0004 CONNECT_IGNORE_WPAx_GROUP_CIPHER
74796 +            Ignore WPAx group cipher for WPA/WPA2
74797 +        = 0x0008 CONNECT_PROFILE_MATCH_DONE
74798 +            Ignore any profile check
74799 +        = 0x0010 CONNECT_IGNORE_AAC_BEACON
74800 +            Ignore the admission control information in the
74801 +            beacon
74802 +        ... CONNECT_CMD, continued
74803 +        Command Values
74804 +        typedef enum {
74805 +            INFRA_NETWORK       = 0x01,
74806 +            ADHOC_NETWORK       = 0x02,
74807 +            ADHOC_CREATOR       = 0x04,
74808 +        } NETWORK_TYPE;
74809 +
74810 +        typedef enum {
74811 +            OPEN_AUTH           = 0x01,
74812 +            SHARED_AUTH         = 0x02,
74813 +            LEAP_AUTH           = 0x04,
74814 +        } DOT11_AUTH_MODE;
74815 +        typedef enum {
74816 +            NONE_AUTH           = 0x01,
74817 +            WPA_AUTH            = 0x02,
74818 +            WPA_PSK_AUTH        = 0x03,
74819 +            WPA2_AUTH           = 0x04,
74820 +            WPA2_PSK_AUTH       = 0x05,
74821 +            WPA_AUTH_CCKM       = 0x06,
74822 +            WPA2_AUTH_CCKM      = 0x07,
74823 +        } AUTH_MODE;
74824 +        typedef enum {
74825 +            NONE_CRYPT          = 0x01,
74826 +            WEP_CRYPT           = 0x02,
74827 +            TKIP_CRYPT          = 0x03,
74828 +            AES_CRYPT           = 0x04,
74829 +        } CRYPTO_TYPE;
74830 +        typedef enum {
74831 +            CONNECT_ASSOC_POLICY_USER = 0x0001,
74832 +            CONNECT_SEND_REASSOC = 0x0002,
74833 +            CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004,
74834 +            CONNECT_PROFILE_MATCH_DONE = 0x0008,
74835 +            CONNECT_IGNORE_AAC_BEACON = 0x0010,
74836 +        } WMI_CONNECT_CTRL_FLAGS_BITS;
74837 +
74838 +    pairwiseCryptoLen and groupCryptoLen are valid when the respective
74839 +    CryptoTypesis WEP_CRYPT, otherwise this value should be 0. This is the length in
74840 +    bytes.
74841 +
74842 +Reset Value
74843 +    None defined
74844 +
74845 +Restrictions
74846 +    None
74847 +
74848 +=====================================================================
74849 +
74850 +
74851 +Name
74852 +    CREATE_PSTREAM
74853 +
74854 +Synopsis
74855 +    The host uses this command to create a new prioritized data endpoint between the
74856 +    host and the AR6000 device that carries a prioritized stream of data. If the AP that the
74857 +    device connects to requires TSPEC stream establishment, the device requests the
74858 +    corresponding TSPEC with the AP. The maximum and minimum service interval
74859 +    ranges from 0 \96 0x7FFFFFFF (ms), where 0 = disabled. The device does not send a
74860 +    reply event for this command, as it is always assumed the command has succeeded.
74861 +    An AP admission control response comes to the host via a WMI_CAC_INDICATION
74862 +    event, once the response for the ADDTS frame comes.
74863 +
74864 +    Examples of cases where reassociation is generated (when WMM) and cases where
74865 +    ADDTS is generated (when WMM and enabling ACM) are when:
74866 +        Changing UAPSD flags in WMM mode, reassociation is generated
74867 +        Changing the interval of sending auto QoS Null frame in WMM mode;
74868 +            reassociation is not generated
74869 +        Issuing a command with same previous parameters in WMM mode and enabling
74870 +            ACM, an ADDTS request is generated
74871 +        Changing the interval of a QoS null frame sending in WMM mode and enabling
74872 +            ACM, an ADDTS request is generated
74873 +        Issuing the command in disconnected state, reassociation or ADDTS is not
74874 +            generated but the parameters are available after (re)association
74875 +
74876 +Command
74877 +    --createqos <user priority> <direction> <traffic class>
74878 +<trafficType> <voice PS capability> <min service interval> <max
74879 +service interval> <inactivity interval> <suspension interval>
74880 +<service start time> <tsid> <nominal MSDU> <max MSDU> <min data
74881 +rate> <mean data rate> <peak data rate> <max burst size> <delay
74882 +bound> <min phy rate> <sba> <medium time> where:
74883 +
74884 +    <user priority>
74885 +    802.1D user priority range (0\967)
74886 +    <direction>
74887 +        = 0    Tx (uplink) traffic
74888 +        = 1    Rx (downlink) traffic
74889 +        = 2    Bi-directional traffic
74890 +    <traffic class>
74891 +        = 1    BK
74892 +        = 2    VI
74893 +        = 3    VO
74894 +    <trafficType>
74895 +        = 0    Aperiodic
74896 +        = 1    Periodic
74897 +    <voice PS capability>
74898 +        Specifies whether the voice power save mechanism
74899 +    (APSD if AP supports it or legacy/simulated APSD
74900 +    [using PS-Poll]) should be used
74901 +        = 0    Disable voice power save for traffic class
74902 +        = 1    Enable APSD voice power save for traffic class
74903 +        = 2    Enable voice power save for all traffic classes
74904 +    <min service interval>
74905 +        (In ms)
74906 +    <max service interval>
74907 +        Inactivity interval (in ms) (0 = Infinite)
74908 +    <suspension interval>
74909 +        (In ms)
74910 +    <service start time>
74911 +        Service start time
74912 +    <tsid>
74913 +        TSID range (0\9615)
74914 +    <nominal MSDU>
74915 +        Nominal MAC SDU size
74916 +    <max MSDU>
74917 +        Maximum MAC SDU size
74918 +    <min data rate>
74919 +        Minimum data rate (in bps)
74920 +    <mean data rate>
74921 +        Mean data rate (in bps)
74922 +    <peak data rate>
74923 +        Peak data rate (in bps)
74924 +    <max burst size>
74925 +        Maximum burst size (in bps)
74926 +    <delay bound>
74927 +        Delay bound
74928 +    <min phy rate>
74929 +        Minimum PHY rate (in bps)
74930 +    <sba>
74931 +        Surplus bandwidth allowance
74932 +    <medium time>
74933 +        Medium time in TU of 32-ms periods per sec
74934 +    ... CREATE_PSTREAM (continued)
74935 +
74936 +Command Parameters
74937 +    UINT8 trafficClass    TRAFFIC_CLASS value
74938 +    UINT8 traffic
74939 +    Direction
74940 +    DIR_TYPE value
74941 +    UINT8    rxQueueNum
74942 +        AR6000 device mailbox index (2 or 3)
74943 +        corresponding to the endpoint the host
74944 +        wishes to use to receive packets for the
74945 +        prioritized stream
74946 +    UINT8 trafficType  TRAFFIC_TYPE value
74947 +    UINT8 voicePS
74948 +Capability
74949 +    VOICEPS_CAP_TYPE value
74950 +    UINT8 tsid          Traffic stream ID
74951 +    UINT8 userPriority  802.1D user priority
74952 +    UINT16 nominalMSDU  Nominal MSDU in octets
74953 +    UINT16 maxMSDU      Maximum MSDU in octets
74954 +    UINT32 minServiceInt Minimum service interval: the min.
74955 +                            period of traffic specified (in ms)
74956 +    UINT32 maxServiceInt  Maximum service interval: the max.
74957 +                        period of traffic specified (in ms)
74958 +    UINT32 inactivityInt Indicates how many ms an established
74959 +                        stream is inactive before the prioritized
74960 +                        data endpoint is taken down and the
74961 +                        corresponding T-SPEC deleted
74962 +    UINT32 suspensionInt  Suspension interval (in ms)
74963 +    UINT32 service       StartTime Service start time
74964 +    UINT32 minDataRate  Minimum data rate (in bps)
74965 +    UINT32 meanDataRate Mean data rate (in bps)
74966 +    UINT32 peakDataRate Peak data rate (in bps)
74967 +    UINT32 maxBurstSize
74968 +    UINT32 delayBound
74969 +    UINT32 minPhyRate   Minimum PHY rate for TSPEC (in bps)
74970 +    UINT32 sba          Surplus bandwidth allowance
74971 +    UINT32 mediumTime   Medium TSPEC time (in units of 32 ms)
74972 +Command Values
74973 +    {
74974 +        WMM_AC_BE = 0   Best Effort
74975 +        WMM_AC_BK = 1   Background
74976 +        WMM_AC_VI = 2   Video
74977 +        WMM_AC_VO = 3   Voice
74978 +        All other values reserved
74979 +    } TRAFFIC_CLASS
74980 +    {
74981 +        UPLINK_TRAFFIC   = 0  From the AR6000 device to the AP
74982 +        DOWNLINK_TRAFFIC = 1  From the AP to the AR6000 device
74983 +        BIDIR_TRAFFIC    = 2  Bi-directional traffic
74984 +        All other values reserved
74985 +    } DIR_TYPE
74986 +    {
74987 +        DISABLE_FOR_THIS_AC = 0
74988 +        ENABLE_FOR_THIS_AC  = 1
74989 +        ENABLE_FOR_ALL_AC   = 2
74990 +        All other values reserved
74991 +    } VOICEPS_CAP_TYPE
74992 +
74993 +    ... CREATE_PSTREAM (continued)
74994 +
74995 +
74996 +        VI  BE   BK    Supported, Y/N?
74997 +   0    0    0    0    Y
74998 +   0    0    0    1    Y
74999 +   0    0    1    0    N
75000 +   0    0    1    1    N
75001 +   0    1    0    0    Y
75002 +   0    1    0    1    Y
75003 +   0    1    1    0    N
75004 +   0    1    1    1    N
75005 +   1    0    0    0    Y
75006 +   1    0    0    1    Y
75007 +   1    0    1    0    N
75008 +   1    1    0    0    N
75009 +   1    1    0    1    Y
75010 +   1    1    0    0    N
75011 +   1    1    1    0    N
75012 +   1    1    1    1    Y
75013 +
75014 +Reset Value
75015 +    No pstream is present after reset; each of the BE, BK, VI,VO pstreams must be created
75016 +    (either implicitly by data flow or explicitly by user)
75017 +
75018 +Restrictions
75019 +    This command can only be issued when the device is in the CONNECTED state. If
75020 +    the device receives the command while in DISCONNECTED state, it replies with a
75021 +    failure indication. At most four prioritized data endpoints can be created, one for
75022 +    each AC.
75023 +
75024 +See Also
75025 +    \93DELETE_PSTREAM\94
75026 +=====================================================================
75027 +
75028 +Name
75029 +    DELETE_BAD_AP
75030 +
75031 +Synopsis
75032 +    The host uses this command to clear a particular entry in the bad AP table
75033 +
75034 +Command
75035 +    wmiconfig eth1 --rmAP [--num=<index>] // used to clear a badAP
75036 +    entry. num is index from 0-3
75037 +
75038 +Command Parameters
75039 +    UINT8  badApIndex   Index [0...n] that identifies the entry in the bad
75040 +                        AP table to delete
75041 +
75042 +Command Values
75043 +    badApIndex   = 0, 1, 2, 3
75044 +            Entry in the bad AP table
75045 +
75046 +Reset Value
75047 +    None defined
75048 +
75049 +Restrictions
75050 +    None
75051 +
75052 +See Also
75053 +    \93ADD_BAD_AP\94
75054 +
75055 +=====================================================================
75056 +
75057 +
75058 +Name
75059 +    DELETE_CIPHER_KEY
75060 +
75061 +Synopsis
75062 +    The host uses this command to delete a key that was previously added with the
75063 +    \93ADD_CIPHER_KEY\94 command.
75064 +
75065 +Command
75066 +    TBD
75067 +
75068 +Command Parameters
75069 +    UINT8   keyIndex    Index (0...3) of the key to be deleted
75070 +
75071 +Command Values
75072 +    keyIndex    = 0, 1,2, 3    Key to delete
75073 +
75074 +Reset Value
75075 +    None
75076 +
75077 +Restrictions
75078 +    The host should not delete a key that is currently in use by the AR6000.
75079 +
75080 +See Also
75081 +    \93ADD_CIPHER_KEY\94
75082 +
75083 +=====================================================================
75084 +
75085 +Name
75086 +    DELETE_PSTREAM
75087 +
75088 +Synopsis
75089 +    The host uses this command to delete a prioritized data endpoint created by a
75090 +    previous \93CREATE_PSTREAM\94 command
75091 +
75092 +Command
75093 +    --deleteqos <trafficClass> <tsid>, where:
75094 +
75095 +    <traffic class>
75096 +        = 0    BE
75097 +        = 1    BK
75098 +        = 2    VI
75099 +        = 3    VO
75100 +    <tsid>
75101 +        The TSpec ID; use the -qosqueue option
75102 +        to get the active TSpec IDs for each traffic class
75103 +
75104 +Command Parameters
75105 +    A_UINT8    trafficClass    Indicate the traffic class of the stream
75106 +                            being deleted
75107 +
75108 +Command Values
75109 +    {
75110 +        WMM_AC_BE = 0    Best effort
75111 +        WMM_AC_BK = 1    Background
75112 +        WMM_AC_VI = 2    Video
75113 +        WMM_AC_VO = 3    Voice
75114 +    } TRAFFIC CLASS
75115 +
75116 +    0-15 for TSID
75117 +
75118 +Reply Values
75119 +    N/A
75120 +
75121 +Restrictions
75122 +    This command should only be issued after a \93CREATE_PSTREAM\94 command has
75123 +    successfully created a prioritized stream
75124 +
75125 +See Also
75126 +    \93CREATE_PSTREAM\94
75127 +
75128 +=====================================================================
75129 +
75130 +
75131 +Name
75132 +    DELETE_WOW_PATTERN
75133 +
75134 +Synopsis
75135 +    The host uses this command to remove a pre-specified pattern from the
75136 +    WoW pattern list.
75137 +
75138 +Command
75139 +    wmiconfig \96delwowpattern <list-id> <pattern-id>
75140 +
75141 +Command Parameters
75142 +    A_UINT8    filter_list_id    ID of the list that contains the WoW filter
75143 +                                 pattern to delete
75144 +    A_UINT8    filter_id    ID of the WoW filter pattern to delete
75145 +
75146 +Reply Parameters
75147 +    None
75148 +
75149 +
75150 +
75151 +Reset Value
75152 +    None defined
75153 +
75154 +Restrictions
75155 +    None
75156 +
75157 +See Also
75158 +    \93ADD_WOW_PATTERN\94
75159 +
75160 +=====================================================================
75161 +
75162 +
75163 +Name
75164 +    EXTENSION
75165 +
75166 +Synopsis
75167 +    The WMI message interface is used mostly for wireless control messages to a wireless
75168 +    module applicable to wireless module management regardless of the target platform
75169 +    implementation. However, some commands only peripherally related to wireless
75170 +    management are desired during operation. These wireless extension commands may
75171 +    be platform-specific or implementation-dependent.
75172 +
75173 +Command
75174 +    N/A
75175 +
75176 +Command Parameters
75177 +    Command-specific
75178 +
75179 +Command Values
75180 +    Command-specific
75181 +
75182 +Reply Parameters
75183 +    Command-specific
75184 +
75185 +Reset Values
75186 +    None defined
75187 +
75188 +Restrictions
75189 +    None defined
75190 +
75191 +=====================================================================
75192 +
75193 +
75194 +Name
75195 +    GET_BIT_RATE
75196 +
75197 +Synopsis
75198 +    Used by the host to obtain the rate most recently used by the AR6000 device
75199 +
75200 +Command
75201 +    wmiconfig eth1 --getfixrates
75202 +
75203 +Command Parameters
75204 +    None
75205 +
75206 +
75207 +
75208 +Reply Parameters
75209 +    INT8
75210 +    rateIndex
75211 +    See the \93SET_BIT_RATE\94 command
75212 +
75213 +Reset Values
75214 +    None
75215 +
75216 +Restrictions
75217 +    This command should only be used during development/debug; it is not intended
75218 +for use in production. It is only valid when the device is in the CONNECTED state
75219 +
75220 +See Also
75221 +    \93SET_BIT_RATE\94
75222 +
75223 +=====================================================================
75224 +
75225 +
75226 +Name
75227 +    GET_CHANNEL_LIST
75228 +
75229 +Synopsis
75230 +    Used by the host uses to retrieve the list of channels that can be used by the device
75231 +    while in the current wireless mode and in the current regulatory domain.
75232 +
75233 +Command
75234 +    TBD
75235 +
75236 +Command Parameters
75237 +    None
75238 +
75239 +Reply Parameters
75240 +    UINT8    reserved    Reserved
75241 +    UINT8    numberOfChannels    Number of channels the reply contains
75242 +    UINT16    channelList[numberOfChannels]  Array of channel frequencies (in MHz)
75243 +
75244 +Reset Values
75245 +    None defined
75246 +
75247 +Restrictions
75248 +    The maximum number of channels that can be reported are 32
75249 +
75250 +=====================================================================
75251 +
75252 +
75253 +Name
75254 +    GET_FIXRATES
75255 +
75256 +Synopsis
75257 +    Clears the current calculated RSSI and SNR value. RSSI and SNR are reported by
75258 +    running-average value. This command will clear the history and have a fresh start for
75259 +    the running-average mechanism.
75260 +
75261 +Synopsis
75262 +    This returns rate-mask set via WMI_SET_FIXRATES to retrieve the current fixed rate
75263 +    that the AR6001 or AR6001 is using. See \93SET_FIXRATES\94.
75264 +
75265 +Command
75266 +    wmiconfig eth1 --getfixrates
75267 +
75268 +Command Parameters
75269 +    A_UINT16    fixRateMask;    Note: if this command is used prior to
75270 +                using WMI_SET_FIXRATES, AR6000
75271 +                returns 0xffff as fixRateMask, indicating
75272 +                all the rates are enabled
75273 +
75274 +Reply Parameters
75275 +    None
75276 +
75277 +Reset Value
75278 +    None defined
75279 +
75280 +Restrictions
75281 +    None
75282 +
75283 +See Also
75284 +    \93SET_FIXRATES\94
75285 +
75286 +=====================================================================
75287 +
75288 +
75289 +
75290 +Name
75291 +    GET_PMKID_LIST_CMD
75292 +
75293 +Synopsis
75294 +    Retrieves the list of PMKIDs on the firmware. The
75295 +    WMI_GET_PMKID_LIST_EVENT is generated by the firmware.
75296 +
75297 +Command
75298 +    TBD
75299 +
75300 +Command Parameters
75301 +
75302 +Reset Values
75303 +    None
75304 +
75305 +Restrictions
75306 +    None
75307 +
75308 +See Also
75309 +    SET_PMKID_LIST_CMD GET_PMKID_LIST_EVENT
75310 +
75311 +=====================================================================
75312 +
75313 +
75314 +Name
75315 +    GET_ROAM_TBL
75316 +
75317 +Synopsis
75318 +    Retrieve the roaming table maintained on the target. The response is reported
75319 +    asynchronously through the ROAM_TBL_EVENT.
75320 +
75321 +Command
75322 +    wmiconfig --getroamtable <roamctrl> <info>
75323 +
75324 +Command Parameters
75325 +    A_UINT8    roamCtrlType;
75326 +    A_UINT16   roamMode
75327 +    A_UINT16   numEntries
75328 +    WMI_BSS_ROAM_INFO bssRoamInfo[1]
75329 +
75330 +Reply Value
75331 +    Reported asynchronously through the ROAM_TBL_EVENT
75332 +
75333 +Reset Value
75334 +    None defined
75335 +
75336 +Restrictions
75337 +    None
75338 +
75339 +See Also
75340 +    SET_KEEPALIVE
75341 +
75342 +=====================================================================
75343 +
75344 +
75345 +Name
75346 +    GET_TARGET_STATS
75347 +
75348 +Synopsis
75349 +    The host uses this command to request that the target send the statistics that it
75350 +    maintains. The statistics obtained from the target are accrued in the host every time
75351 +    the GET_TARGET_STATS command is issued. The --clearStats option is added to
75352 +    clear the target statistics maintained in the host.
75353 +
75354 +Command
75355 +    wmiconfig --getTargetStats --clearStats
75356 +
75357 +Command Parameters
75358 +    TARGET_STATS    targetStats
75359 +    WMI_TARGET_STATS
75360 +    UINT8   clearStats
75361 +
75362 +
75363 +Reply Value
75364 +    RSSI return value (0\96100)
75365 +
75366 +Reset Values
75367 +    All statistics are cleared (zeroed)
75368 +
75369 +Restrictions
75370 +    The --getTargetStats option must be used; the --clearStats option is also available also
75371 +
75372 +
75373 +=====================================================================
75374 +
75375 +Name
75376 +    GET_TX_PWR
75377 +
75378 +Synopsis
75379 +    The host uses this command to retrieve the current Tx power level
75380 +
75381 +Command
75382 +    wmiconfig -i eth1 --getpower
75383 +
75384 +Command Parameters
75385 +    None
75386 +
75387 +Reply Parameters
75388 +    UINT16 dbM    The current Tx power level specified in dbM
75389 +
75390 +Reset Values
75391 +    The maximum permitted by the regulatory domain
75392 +
75393 +Restrictions
75394 +    None
75395 +
75396 +See Also
75397 +    \93SET_TX_PWR\94
75398 +
75399 +=====================================================================
75400 +
75401 +
75402 +Name
75403 +    GET_WOW_LIST
75404 +
75405 +Synopsis
75406 +    The host uses this command to retrieve the current list of WoW patterns.
75407 +
75408 +Command
75409 +    wmiconfig \96getwowlist <list-id>
75410 +
75411 +Command Parameters
75412 +    A_UINT8 filter_list_id    ID of the list of WoW patterns to retrieve
75413 +
75414 +Reply Value(s)
75415 +    A_UINT16  num_filters    Number of WoW patterns contained in the list
75416 +    A_UINT8   wow_mode    Current mode of WoW (enabled or disabled)
75417 +    A_UINT8    host_mode    Current host mode (asleep or awake)
75418 +    WOW_FILTER    wow_filters[1]
75419 +        Contents of the WoW filter pattern list
75420 +        (contains mask, pattern, offset and size
75421 +    information for each of the patterns)
75422 +
75423 +Reset Value
75424 +    None defined
75425 +
75426 +Restrictions
75427 +    None
75428 +
75429 +See Also
75430 +    \93SET_WSC_STATUS\94
75431 +
75432 +=====================================================================
75433 +
75434 +
75435 +Name
75436 +    LQ_THRESHOLD_PARAMS
75437 +
75438 +Synopsis
75439 +    Sets Link Quality thresholds, the sampling will happen at every unicast data frame
75440 +    Tx if a certain threshold is met, and the corresponding event will be sent to the host.
75441 +
75442 +Command
75443 +    --lqThreshold <enable> <upper_threshold_1> ...
75444 +    <upper_threshold_4> <lower_threshold_1> ... <lower_threshold_4>
75445 +
75446 +Command Parameters
75447 +    <enable>    = 0    Disable link quality sampling
75448 +                = 1    Enable link quality sampling
75449 +    <upper_threshold_x>  Above thresholds (value in [0,100]), in
75450 +                    ascending order
75451 +    <lower_threshold_x> Below thresholds (value in [0,100]), in
75452 +                    ascending order
75453 +
75454 +Command Values
75455 +    See command parameters
75456 +
75457 +Reset Value
75458 +    None defined
75459 +
75460 +Restrictions
75461 +    None
75462 +
75463 +=====================================================================
75464 +
75465 +
75466 +Name
75467 +    OPT_TX_FRAME
75468 +
75469 +Synopsis
75470 +    Special feature, sends a special frame.
75471 +
75472 +Command
75473 +    wmiconfig --sendframe <frmType> <dstaddr> <bssid> <optIEDatalen>
75474 +    <optIEData>
75475 +
75476 +Command Parameters
75477 +    {
75478 +        A_UINT16    optIEDataLen;
75479 +        A_UINT8    frmType;
75480 +        A_UINT8    dstAddr[ATH_MAC_LEN];
75481 +        A_UINT8    bssid[ATH_MAC_LEN];
75482 +        A_UINT8    optIEData[1];
75483 +    } WMI_OPT_TX_FRAME_CMD;
75484 +
75485 +Command Values
75486 +    <frmtype>   = 1    Probe request frame
75487 +                = 2    Probe response frame
75488 +                = 3    CPPP start
75489 +                = 4    CPPP stop
75490 +
75491 +Reset Value
75492 +    None defined
75493 +
75494 +Restrictions
75495 +    Send a special frame only when special mode is on.
75496 +
75497 +=====================================================================
75498 +
75499 +
75500 +Name
75501 +    RECONNECT
75502 +
75503 +Synopsis
75504 +    This command requests a reconnection to a BSS to which the AR6000 device was
75505 +    formerly connected
75506 +
75507 +Command
75508 +    TBD
75509 +
75510 +Command Parameters
75511 +    UINT16    channel    Provides a hint as to which channel was
75512 +                        used for a previous connection
75513 +    UINT8    bssid[6]    If set, indicates which BSSID to connect to
75514 +
75515 +Command Values
75516 +    None
75517 +
75518 +Reset Values
75519 +    None
75520 +
75521 +Restrictions
75522 +    None
75523 +
75524 +See Also
75525 +    \93CONNECT_CMD\94
75526 +
75527 +=====================================================================
75528 +
75529 +
75530 +Name
75531 +    RSSI_THRESHOLD_PARAMS
75532 +
75533 +Synopsis
75534 +    Configures how the AR6000 device monitors and reports signal strength (RSSI) of the
75535 +    connected BSS, which is used as a link quality metric. The four RSSI threshold sets (in
75536 +    dbM) of the host specification divide the signal strength range into six segments.
75537 +    When signal strength increases or decreases across one of the boundaries, an
75538 +    RSSI_THRESHOLD event is signaled to the host. The host may then choose to take
75539 +    action (such as influencing roaming).
75540 +
75541 +Command
75542 +    wmiconfig eth1 --rssiThreshold <weight> <pollTime>
75543 +        <above_threshold_val_1> ... <above_threshold_tag_6>
75544 +        <above_threshold_val_6>
75545 +        <below_threshold_tag_1> <below_threshold_val_1> ...
75546 +        <below_threshold_tag_6> <below_threshold_val_6>
75547 +
75548 +Command Parameters
75549 +    UINT8    weight    Range in [1, 16] used to calculate average RSSI
75550 +    UINT32   pollTime   RSSI (signal strength) sampling frequency in
75551 +                seconds (if pollTime = 0, single strength
75552 +        sampling is disabled)
75553 +    USER_RSS__THOLD tholds[12]  Thresholds (6 x 2)
75554 +
75555 +Command Values
75556 +    None defined
75557 +
75558 +Reset Values
75559 +    pollTime is 0, and sampling is disabled
75560 +
75561 +Restrictions
75562 +    Can only be issued if the AR6000 device is connected
75563 +
75564 +
75565 +=====================================================================
75566 +
75567 +Name
75568 +    SCAN_PARAMS
75569 +
75570 +Synopsis
75571 +    The minact parameter determines the minimum active channel dwell time, within
75572 +    which if the STA receives any beacon, it remains on that channel until the maxact
75573 +    channel dwell time. If the STA does not receive a beacon within the minact dwell
75574 +    time, it switches to scan the next channel.
75575 +
75576 +Command
75577 +    wmiconfig -scan -minact=<ms> --maxact=<ms>
75578 +
75579 +Command Parameters
75580 +    UINT16    maxact    Channel dwell time (in ms), default = 0
75581 +    UINT16    minact    Channel dwell time (in ms), default = 105
75582 +
75583 +Command Values
75584 +    See channel parameters
75585 +
75586 +Reset Values
75587 +    None defined
75588 +
75589 +Restrictions
75590 +    The minact value should be greater than 0; maxact should be between 5\9665535 ms
75591 +    and greater than minact
75592 +
75593 +=====================================================================
75594 +
75595 +
75596 +Name
75597 +    SET_ACCESS_PARAMS
75598 +
75599 +Synopsis
75600 +    Allows the host to set access parameters for the wireless network. A thorough
75601 +    understanding of IEEE 802.11 is required to properly manipulate these parameters.
75602 +
75603 +Command
75604 +    wmiconfig eth1 --acparams --txop <limit> --cwmin <0-15>
75605 +    --cwmax <0-15> --aifsn<0-15>
75606 +
75607 +Command Parameters
75608 +    UINT16    txop    The maximum time (expressed in units of
75609 +                        32 ms) the device can spend transmitting
75610 +                        after acquiring the right to transmit
75611 +    UINT8    eCWmin    Minimum contention window
75612 +    UINT8    eCWmax    Maximum contention window
75613 +    UINT8    aifsn    The arbitration inter-frame space number
75614 +
75615 +Command Values
75616 +    None
75617 +
75618 +Reset Values
75619 +    Reasonable defaults that vary, between endpoints (prioritized streams)
75620 +
75621 +Restrictions
75622 +    None
75623 +
75624 +=====================================================================
75625 +
75626 +
75627 +Name
75628 +    SET_ADHOC_BSSID
75629 +
75630 +Synopsis
75631 +    Allows the host to set the BSSID for an ad hoc network. If a network with this BSSID
75632 +    is not found, the target creates an ad hoc network with this BSSID after the connect
75633 +    WMI command is triggered (e.g., by the SIOCSIWESSID IOCTL).
75634 +
75635 +Command
75636 +    wmiconfig eth1 --adhocbssid <bssid>
75637 +
75638 +Command Parameters
75639 +    A_UINT8     bssid[ATH_MAC_LEN]    BSSID is specified in xx:xx:xx:xx:xx:xx format
75640 +
75641 +Command Values
75642 +    None
75643 +
75644 +Reset Values
75645 +    None
75646 +
75647 +Restrictions
75648 +    None
75649 +
75650 +=====================================================================
75651 +
75652 +
75653 +Name
75654 +    SET_AKMP_PARAMS
75655 +
75656 +Synopsis
75657 +    Enables or disables multi PMKID mode.
75658 +
75659 +Command
75660 +    wmiconfig eth1 --setakmp --multipmkid=<on/off>
75661 +
75662 +Command Parameters
75663 +    typedef struct {
75664 +      A_UINT32    akmpInfo;
75665 +    } WMI_SET_AKMP_PARAMS_CMD;
75666 +
75667 +Command Values
75668 +    akmpInfo;
75669 +    bit[0] = 0
75670 +        MultiPMKID mode is disabled and PMKIDs that
75671 +        were set using the WMI_SET_PMKID_CMD are
75672 +        used in the [Re]AssocRequest frame.
75673 +     bit[0] = 1
75674 +        MultiPMKID mode is enabled and PMKIDs issued
75675 +        by the WMI_SET_PMKID_LIST_CMD are used in
75676 +        the next [Re]AssocRequest sent to the AP.
75677 +
75678 +Reset Values
75679 +    MultiPMKID mode is disabled
75680 +
75681 +Restrictions
75682 +    None
75683 +
75684 +=====================================================================
75685 +
75686 +
75687 +Name
75688 +    SET_APPIE
75689 +
75690 +Synopsis
75691 +    Add an application-specified IE to a management frame. The maximum length is
75692 +    76 bytes. Including the length and the element ID, this translates to 78 bytes.
75693 +
75694 +Command
75695 +    wmiconfig --setappie <frame> <IE>, where:
75696 +
75697 +    frame
75698 +        One of beacon, probe, respon, assoc
75699 +
75700 +    IE
75701 +        A hex string beginning with DD (if = 0, no
75702 +        IE is sent in the management frame)
75703 +
75704 +Command Parameters
75705 +    mgmtFrmType;
75706 +        A WMI_MGMT_FRAME_TYPE
75707 +
75708 +    ieLen;
75709 +        Length of the IE to add to the GMT frame
75710 +
75711 +Command Values
75712 +    None
75713 +
75714 +Reset Value
75715 +    None defined
75716 +
75717 +Restrictions
75718 +    Supported only for the probe request and association request management frame
75719 +types. Also, only one IE can be added per management frame type.
75720 +
75721 +=====================================================================
75722 +
75723 +
75724 +Name
75725 +    SET_ASSOC_INFO
75726 +
75727 +Synopsis
75728 +    The host uses this command to specify any information elements (IEs) it wishes the
75729 +    AR6000 device to add to all future association and reassociation requests. IEs must be
75730 +    correct and are used as is by the device. IEs specified through this command are
75731 +    cleared with a DISCONNECT.
75732 +
75733 +Command
75734 +    wmiconfig eth1 --setAssocIe <IE>
75735 +
75736 +Command Parameters
75737 +    UINT8    ieType    Used directly in 802.11 frames
75738 +    UINT8    bufferSize    Size of assocInfo (in bytes) ranging from
75739 +                        0\96240. If = 0, previously set IEs are cleared.
75740 +    UINT8    assocInfo[bufferSize]    Used directly in 802.11 frames
75741 +
75742 +Command Values
75743 +    None
75744 +
75745 +Reset Values
75746 +    IEs are cleared
75747 +
75748 +Restrictions
75749 +    This command can only be issued in the DISCONNECTED state
75750 +
75751 +=====================================================================
75752 +
75753 +
75754 +Name
75755 +    SET_AUTHMODE
75756 +
75757 +Synopsis
75758 +    Sets the 802.11 authentication mode of reconnection
75759 +
75760 +Command
75761 +    wmiconfig eth1 --setauthmode <mode>
75762 +
75763 +Command Parameters
75764 +    UINT8    mode
75765 +
75766 +Command Values
75767 +    mode    = 0x00    Proceed with authentication during reconnect
75768 +            = 0x01    Do not proceed with authentication during reconnect
75769 +
75770 +Reset Values
75771 +    Authentication
75772 +
75773 +Restrictions
75774 +    None
75775 +
75776 +=====================================================================
75777 +
75778 +
75779 +Name
75780 +    SET_BEACON_INT
75781 +
75782 +Synopsis
75783 +    Sets the beacon interval for an ad hoc network. Beacon interval selection may have an
75784 +    impact on power savings. To some degree, a longer interval reduces power
75785 +    consumption but also decreases throughput. A thorough understanding of IEEE
75786 +    802.11 ad hoc networks is required to use this command effectively.
75787 +
75788 +Command
75789 +    wmiconfig eth1 --ibssconintv
75790 +
75791 +Command Parameters
75792 +    UINT16    beaconInterval    Specifies the beacon interval in TU units (1024 ms)
75793 +
75794 +Command Values
75795 +    None
75796 +
75797 +Reset Values
75798 +    The default beacon interval is 100 TUs (102.4 ms)
75799 +
75800 +Restrictions
75801 +    This command can only be issued before the AR6000 device starts an ad hoc network
75802 +
75803 +See Also
75804 +    \93SET_IBSS_PM_CAPS\94
75805 +
75806 +=====================================================================
75807 +
75808 +
75809 +Name
75810 +    SET_BIT_RATE
75811 +
75812 +Synopsis
75813 +    The host uses this command to set the AR6000 device to a specific fixed rate.
75814 +
75815 +Command
75816 +    wmiconfig eth1 --setfixrates <rate_0> ... <rate_n>
75817 +
75818 +Command Parameters
75819 +    INT8    rateIndex
75820 +    A WMI_BIT_RATE value
75821 +    {
75822 +        RATE_AUTO    = -1
75823 +        RATE_1Mb     = 0
75824 +        RATE_2Mb     = 1
75825 +        RATE_5_5M    = 2
75826 +        RATE_11Mb    = 3
75827 +        RATE_6Mb     = 4
75828 +        RATE_9Mb     = 5
75829 +        RATE_12Mb    = 6
75830 +        RATE_18Mb    = 7
75831 +        RATE_24Mb    = 8
75832 +        RATE_36Mb    = 9
75833 +        RATE_48Mb    = 10
75834 +        RATE_54Mb    = 11
75835 +      } WMI_BIT_RATE
75836 +
75837 +
75838 +Command Values
75839 +    See command parameters
75840 +
75841 +Reset Values
75842 +    The dynamic rate is determined by the AR6000 device
75843 +
75844 +Restrictions
75845 +    This command is intended for use only during development/debug; it is not
75846 +intended for use in production
75847 +
75848 +See Also
75849 +    \93GET_BIT_RATE\94
75850 +
75851 +=====================================================================
75852 +
75853 +
75854 +Name
75855 +    SET_BMISS_TIME
75856 +
75857 +Synopsis
75858 +    This command sets the beacon miss (BMISS) time, which the AR6000 hardware use
75859 +    to recognize missed beacons. When an excessive number (15) of consecutive beacons
75860 +    are missed, the AR6000 consider switching to a different BSS. The time can be
75861 +    specified in number of beacons or in TUs.
75862 +
75863 +Command(s)
75864 +    wmiconfig eth1 --setbmissbeacons=<val>
75865 +    wmiconfig eth1 --setbmisstime=<val>
75866 +
75867 +Command Parameters
75868 +    UINT16    bmissTime    Specifies the beacon miss time
75869 +                            [1000...5000] in TUs (1024 ms)
75870 +    UINT16    bmissbeacons  Specifies the number of beacons [5...50]
75871 +
75872 +Command Values
75873 +    None
75874 +
75875 +Reset Values
75876 +    bmissTime is 1500 TUs (1536 ms)
75877 +
75878 +Restrictions
75879 +    None
75880 +
75881 +=====================================================================
75882 +
75883 +
75884 +Name
75885 +    SET_BSS_FILTER
75886 +
75887 +Synopsis
75888 +    The host uses this to inform the AR6000 device of the types of networks about which
75889 +    it wants to receive information from the \93BSSINFO\94 event. As the device performs
75890 +    either foreground or background scans, it applies the filter and sends \93BSSINFO\94
75891 +    events only for the networks that pass the filter. If any of the  bssFilter or the ieMask
75892 +    filter matches, a BSS Info is sent to the host. The ieMask currently is used as a match
75893 +    for the IEs in the beacons, probe reponses and channel switch action management
75894 +    frame. See also \93Scan and Roam\94 on page C-1.
75895 +
75896 +    The BSS filter command has been enhanced to support IE based filtering. The IEs can
75897 +    be specified as a bitmask through this command using this enum.
75898 +
75899 +Command
75900 +    wmiconfig eth1 \96filter = <filter> --ieMask 0x<mask>
75901 +
75902 +Command Parameters
75903 +    UINT8    BssFilter
75904 +
75905 + Command Values
75906 +    typedef struct {
75907 +        A_UINT8    bssFilter;    See WMI_BSS_FILTER
75908 +        A_UINT32    ieMask;
75909 +    } __ATTRIB_PACK WMI_BSS_FILTER_CMD;
75910 +
75911 +    The ieMask can take this combination of values:
75912 +
75913 +    enum {
75914 +        BSS_ELEMID_CHANSWITCH   = 0x01
75915 +        BSS_ELEMID_ATHEROS      = 0x02,
75916 +    }
75917 +
75918 +Reply Value
75919 +    None
75920 +
75921 +Reset Value
75922 +    BssFilter = NONE_BSS_FILTER (0)
75923 +
75924 +Restrictions
75925 +    None
75926 +
75927 +See Also
75928 +    \93CONNECT_CMD\94
75929 +
75930 +=====================================================================
75931 +
75932 +
75933 +Name
75934 +    SET_BT_PARAMS
75935 +
75936 +Synopsis
75937 +    This command is used to set the status of a Bluetooth stream or set Bluetooth
75938 +    coexistence register parameters. The stream may be an SCO or an A2DP stream and
75939 +    its status can be started/stopped/suspended/resumed.
75940 +
75941 +Command
75942 +    wmiconfig \96setBTparams <paramType> <params>
75943 +
75944 +Command Parameters
75945 +    struct {
75946 +       union {
75947 +            BT_PARAMS_SCO    scoParams;
75948 +            BT_PARAMS_A2DP   a2dpParams;
75949 +            BT_PARAMS_MISC   miscParams;
75950 +            BT_COEX_REGS     regs;
75951 +        } info;
75952 +         A_UINT8 paramType;
75953 +        struct {
75954 +            A_UINT8 noSCOPkts;    Number of SCO packets between consecutive PS-POLLs
75955 +            A_UINT8 pspollTimeout;
75956 +            A_UINT8 stompbt;
75957 +        } BT_PARAMS_SCO;
75958 +        struct {
75959 +            A2DP BT stream parameters
75960 +            A_UINT32   period;
75961 +            A_UINT32   dutycycle;
75962 +            A_UINT8    stompbt;
75963 +        } BT_PARAMS_A2DP;
75964 +        struct {
75965 +            union {
75966 +               WLAN_PROTECT_POLICY_TYPE   protectParams;
75967 +               A_UINT16    wlanCtrlFlags;
75968 +            }info;
75969 +        A_UINT8 paramType;
75970 +        } BT_PARAMS_MISC;
75971 +        struct {
75972 +            BT coexistence registers values
75973 +            A_UINT32    mode;     Coexistence mode
75974 +            A_UINT32    scoWghts; WLAN and BT weights
75975 +            A_UINT32    a2dpWghts;
75976 +            A_UINT32    genWghts;
75977 +            A_UINT32    mode2;    Coexistence mode2
75978 +            A_UINT8    setVal;
75979 +        } BT_COEX_REGS;
75980 +
75981 +Command Values
75982 +    None defined
75983 +
75984 +Reset Value
75985 +    None
75986 +
75987 +Restrictions
75988 +    None
75989 +
75990 +=====================================================================
75991 +
75992 +
75993 +Name
75994 +    SET_BT_STATUS
75995 +
75996 +Synopsis
75997 +    Sets the status of a Bluetooth stream. The stream may be a SCO or an A2DP stream
75998 +    and its status can be started/stopped/suspended/resumed.
75999 +
76000 +Command
76001 +    wmiconfig \96setBTstatus <streamType> <status>
76002 +
76003 +Command Parameters
76004 +    {
76005 +        A_UINT8        streamType;    Stream type
76006 +        A_UINT8        status;    Stream status
76007 +    }WMI_SET_BT_STATUS_CMD;
76008 +
76009 +Command Values
76010 +    {
76011 +        BT_STREAM_UNDEF    = 0
76012 +        BT_STREAM_SCO
76013 +        SCO stream
76014 +        BT_STREAM_A2DP
76015 +        A2DP stream
76016 +        BT_STREAM_MAX
76017 +    } BT_STREAM_TYPE;
76018 +
76019 +    {
76020 +        BT_STATUS_UNDEF    = 0
76021 +        BT_STATUS_START
76022 +        BT_STATUS_STOP
76023 +        BT_STATUS_RESUME
76024 +        BT_STATUS_SUSPEND
76025 +        BT_STATUS_MAX
76026 +    } BT_STREAM_STATUS;
76027 +
76028 +Reset Value
76029 +    None defined
76030 +
76031 +Restrictions
76032 +    None
76033 +
76034 +=====================================================================
76035 +
76036 +
76037 +Name
76038 +    SET_CHANNEL_PARAMETERS
76039 +
76040 +Synopsis
76041 +    Configures various WLAN parameters related to channels, sets the wireless mode,
76042 +    and can restrict the AR6000 device to a subset of available channels. The list of
76043 +    available channels varies depending on the wireless mode and the regulatory
76044 +    domain. The device never operates on a channel outside of its regulatory domain. The
76045 +    device starts to scan the list of channels right after this command.
76046 +
76047 +Command
76048 +    wmiconfig eth1 --wmode <mode> <list>
76049 +
76050 +Command Parameters
76051 +    UINT8    phyMode    See Values below.
76052 +    UINT8    numberOfChannels
76053 +        Number of channels in the channel array that
76054 +        follows. If = 0, then the device uses all of the
76055 +        channels permitted by the regulatory domain
76056 +        and by the specified phyMode.
76057 +    UINT16    channel[numberOfChannels]
76058 +        Array listing the subset of channels (expressed
76059 +        as frequencies in MHz) the host wants the
76060 +        device to use. Any channel not permitted by
76061 +        the specified phyMode or by the specified
76062 +        regulatory domain is ignored by the device.
76063 +
76064 +Command Values
76065 +    phyMode = {
76066 +        Wireless mode
76067 +        11a    = 0x01
76068 +        11g    = 0x02
76069 +        11ag   = 0x03
76070 +        11b    = 0x04
76071 +        11g only    = 0x05
76072 +        }
76073 +
76074 +Reset Values
76075 +    phyMode
76076 +    11ag
76077 +    802.11a/g modules
76078 +        11g
76079 +    802.11g module
76080 +    channels
76081 +        Defaults to all channels permitted by the
76082 +        current regulatory domain.
76083 +
76084 +Restrictions
76085 +    This command, if issued, should be issued soon after reset and prior to the first
76086 +    connection. This command should only be issued in the DISCONNECTED state.
76087 +
76088 +=====================================================================
76089 +
76090 +
76091 +Name
76092 +    SET_DISC_TIMEOUT
76093 +
76094 +Synopsis
76095 +    The host uses this command to configure the amount of time that the AR6000 should
76096 +    spend when it attempts to reestablish a connection after losing link with its current
76097 +    BSS. If this time limit is exceeded, the AR6000 send a \93DISCONNECT\94 event. After
76098 +    sending the \93DISCONNECT\94 event the AR6000 continues to attempt to reestablish a
76099 +    connection, but they do so at the interval corresponding to a foreground scan as
76100 +    established by the \93SET_SCAN_PARAMS\94 command.
76101 +
76102 +    A timeout value of 0 indicates that the AR6000 will disable all autonomous roaming,
76103 +    so that the AR6000 will not perform any scans after sending a \93DISCONNECT\94
76104 +    event to the host. The state is maintained until a shutdown or host sets different
76105 +    timeout value from 0.
76106 +
76107 +Command
76108 +    wmiconfig eth1 --disc=<timeout in seconds>
76109 +
76110 +Command Parameters
76111 +    UINT8    disconnectTimeout
76112 +        Specifies the time limit (in seconds) after
76113 +        which a failure to reestablish a connection
76114 +        results in a \93DISCONNECT\94 event
76115 +
76116 +Command Values
76117 +    None
76118 +
76119 +Reset Values
76120 +    disconnectTimeout is 10 seconds
76121 +
76122 +Restrictions
76123 +    This command can only be issued while in a DISCONNECTED state
76124 +
76125 +=====================================================================
76126 +
76127 +
76128 +Name
76129 +    SET_FIXRATES
76130 +
76131 +Synopsis
76132 +    By default, the AR6000 device uses all PHY rates based on mode of operation. If the
76133 +    host application requires the device to use subset of supported rates, it can set those
76134 +    rates with this command. In 802.11g mode, the AR6000 device takes the entire
76135 +    802.11g basic rate set and the rates specified with this command and uses it as the
76136 +    supported rate set.
76137 +
76138 +    This rate set is advertised in the probe request and the assoc/re-assoc request as
76139 +    supported rates. Upon successful association, the device modifies the rate set pool
76140 +    using the: intersection of AP-supported rates with the union of the 802.11g basic rate
76141 +    set and rates set using this command. The device picks transmission rates from this
76142 +    pool based on a rate control algorithm.
76143 +
76144 +Command
76145 +    TBD
76146 +
76147 +Command Parameters
76148 +    A_UINT16    fixRateMask;
76149 +        The individual bit is an index for rate table,
76150 +        and setting the that index to 1 would set that
76151 +        corresponding rate. E.g., fixRateMask = 9
76152 +        (1001) sets 1 Mbps and 11 Mbps.
76153 +
76154 +Command Values
76155 +    None
76156 +
76157 +Reset Value
76158 +    None defined
76159 +
76160 +Restrictions
76161 +    None
76162 +
76163 +See Also
76164 +    \93GET_FIXRATES\94
76165 +
76166 +=====================================================================
76167 +
76168 +
76169 +Name
76170 +    SET_WHAL_PARAM
76171 +
76172 +Synopsis
76173 +    An internal AR6000 command that is used to set certain hardware parameters. The
76174 +    description of this command is in $WORKAREA/include/halapi.h.
76175 +
76176 +Command
76177 +    TBD
76178 +
76179 +Command Parameters
76180 +    ATH_HAL_SETCABTO_CMDID
76181 +        Sets the timeout waiting for the multicast
76182 +        traffic after a DTIM beacon (in TUs).
76183 +
76184 +Command Values
76185 +    None
76186 +
76187 +Reset Value
76188 +    Default = 10 TUs
76189 +
76190 +Restrictions
76191 +    This command should be executed before issuing a connect command.
76192 +
76193 +=====================================================================
76194 +
76195 +
76196 +Name
76197 +    SET_HOST_SLEEP_MODE
76198 +
76199 +Synopsis
76200 +    The host uses this command to set the host mode to asleep or awake. All packets are
76201 +    delivered to the host when the host mode is awake. When host mode is asleep, only if
76202 +    WoW is enabled and the incoming packet matches one of the specified WoW
76203 +    patterns, will the packet be delivered to the host. The host will also be woken up by
76204 +    the target for pattern-matching packets and important events.
76205 +
76206 +Command
76207 +    wmiconfig \96sethostmode=<asleep/awake>
76208 +
76209 +Command Parameters
76210 +    A_BOOL    awake    Set the host mode to awake
76211 +    A_BOOL    asleep   Set the host mode to asleep
76212 +
76213 +Command Values
76214 +    1 = awake, 0 = asleep
76215 +
76216 +Reset Value
76217 +    None defined (default host mode is awake)
76218 +
76219 +Restrictions
76220 +    None
76221 +
76222 +
76223 +=====================================================================
76224 +
76225 +Name
76226 +    SET_IBSS_PM_CAPS
76227 +
76228 +Synopsis
76229 +    Used to support a non-standard power management scheme for an ad hoc wireless
76230 +    network consisting of up to eight stations (STAs) that support this form of power
76231 +    saving (e.g., Atheros-based STAs). A thorough understanding of IEEE 802.11 ad hoc
76232 +    networks is required to use this command effectively.
76233 +
76234 +Command
76235 +    wmiconfig eth1 --ibsspmcaps --ps=<enable/disable>
76236 +        --aw=<ATIM Windows in ms>
76237 +        --ttl=<Time to live in number of beacon periods>
76238 +        --to=<timeout in ms>
76239 +
76240 +Command Parameters
76241 +    UINT8    power_saving
76242 +        = 0
76243 +        The non-standard power saving scheme is
76244 +        disabled and maximum throughput (with no
76245 +        power saving) is obtained.
76246 +
76247 +        = 1
76248 +        Ad hoc power saving scheme is enabled (but
76249 +        throughput may be decreased)
76250 +
76251 +    UINT16    atim_windows
76252 +        Specifies the length (in ms) of the ad hoc traffic
76253 +        indication message (ATIM) windows used in an ad
76254 +        hoc network. All Atheros-based STAs that join the
76255 +        network use this duration ATIM window.
76256 +
76257 +    The duration is communicated between wireless
76258 +    STAs through an IE in beacons and probe responses.
76259 +
76260 +    The host sets atim_windows to control trade-offs
76261 +    between power use and throughput. The value
76262 +    chosen should be based on the beacon interval (see
76263 +    the \93SET_BEACON_INT\94 command) on the
76264 +    expected number of STAs in the IBSS, and on the
76265 +    amount of traffic and traffic patterns between STAs.
76266 +
76267 +    UINT16    timeout_value
76268 +        Specifies the timeout (in ms). The value is the same
76269 +        for all ad hoc connections, but tracks separately for
76270 +        each.
76271 +
76272 +        Applicable only for a beacon period and used to
76273 +        derive actual timeout values on the Tx and Rx sides.
76274 +        On the Tx side, the value defines a window during
76275 +        which the STA accepts the frame(s) from the host for a
76276 +        particular connection. Until closed, the window
76277 +        restarts with every frame received from the host. On
76278 +        the Rx side, indicates the time until which the STA
76279 +        continues accepting frames from a particular
76280 +        connection. The value resets with every frame
76281 +        received. The value can be used to determine the
76282 +        trade off between throughput and power.
76283 +        Default = 10 ms
76284 +
76285 +    UINT8    ttl
76286 +        Specifies the value in number of beacon periods. The
76287 +        value is used to set a limit on the time until which a
76288 +        frame is kept alive in the AR6001 before being
76289 +        discarded. Default = 5
76290 +
76291 +Command Values
76292 +    None
76293 +
76294 +Reset Values
76295 +    By default, power_saving is enabled with atim_window = 20 ms
76296 +
76297 +Restrictions
76298 +    Can only be issued before the AR6000 starts an ad hoc network
76299 +
76300 +See Also
76301 +    \93SET_BEACON_INT\94
76302 +
76303 +=====================================================================
76304 +
76305 +
76306 +
76307 +Name
76308 +    SET_LISTEN_INT
76309 +
76310 +Synopsis
76311 +    The host uses this command to request a listen interval, which determines how often
76312 +    the AR6000 device should wake up and listen for traffic. The listen interval can be set
76313 +    by the TUs or by the number of beacons. The device may not be able to comply with
76314 +    the request (e.g., if the beacon interval is greater than the requested listen interval, the
76315 +    device sets the listen interval to the beacon interval). The actual listen interval used
76316 +    by the device is available in the \93CONNECT\94 event.
76317 +
76318 +Command
76319 +    wmiconfig eth1 --listen=<#of TUs, can range from 15 to 3000>
76320 +
76321 +    --listenbeacons=<#of beacons, can range from 1 to 50>
76322 +
76323 +Command Parameters
76324 +    UINT16    listenInterval
76325 +        Specifies the listen interval in Kms
76326 +        (1024 ms), ranging from 100 to 1000
76327 +
76328 +    UINT16    listenbeacons
76329 +        Specifies the listen interval in beacons,
76330 +        ranging from 1 to 50
76331 +
76332 +Command Values
76333 +    None
76334 +
76335 +Reset Values
76336 +    The device sets the listen interval equal to the beacon interval of the AP it associates
76337 +    to.
76338 +
76339 +Restrictions
76340 +    None
76341 +
76342 +=====================================================================
76343 +
76344 +
76345 +Name
76346 +    SET_LPREAMBLE
76347 +
76348 +Synopsis
76349 +    Overrides the short preamble capability of the AR6000 device
76350 +
76351 +Command
76352 +    TBD
76353 +
76354 +Command Parameters
76355 +    WMI_LPREAMBLE_DISABLED
76356 +        The device is short-preamble capable
76357 +
76358 +    WMI_LPREAMBLE_ENABLED
76359 +        The device supports only the long-
76360 +    preamble mode
76361 +
76362 +Command Values
76363 +    None
76364 +
76365 +Reset Value
76366 +    None defined
76367 +
76368 +Restrictions
76369 +    None
76370 +
76371 +
76372 +=====================================================================
76373 +
76374 +Name
76375 +    SET_MAX_SP_LEN
76376 +
76377 +Synopsis
76378 +    Set the maximum service period; indicates the number of packets the AR6001 can
76379 +    receive from the AP when triggered
76380 +
76381 +Command
76382 +    wmiconfig eth1 --setMaxSPLength <maxSPLen>
76383 +
76384 +Command Parameters
76385 +    UINT8    maxSPLen
76386 +        An APSD_SP_LEN_TYPE value
76387 +
76388 +Command Values
76389 +    {
76390 +        DELIVER_ALL_PKT  = 0x0
76391 +        DELIVER_2_PKT    = 0x1
76392 +        DELIVER_4_PKT    = 0x2
76393 +        DELIVER_6_PKT    = 0x3
76394 +    }APSD_SP_LEN_TYPE
76395 +
76396 +
76397 +Reset Values
76398 +    maxSPLen is DELIVER_ALL_PKT
76399 +
76400 +Restrictions
76401 +    None
76402 +
76403 +=====================================================================
76404 +
76405 +
76406 +Name
76407 +    SET_OPT_MODE
76408 +
76409 +Synopsis
76410 +    Special feature, sets the special mode on/off
76411 +
76412 +Command
76413 +    wmiconfig eth1 --mode <mode>
76414 +    Set the optional mode, where mode is special or off
76415 +
76416 +Command Parameters
76417 +    enum {
76418 +        SPECIAL_OFF
76419 +        SPECIAL_ON
76420 +    } OPT_MODE_TYPE;
76421 +
76422 +Command Values
76423 +
76424 +Reset Value
76425 +    Mode = Off
76426 +
76427 +Restrictions
76428 +    None
76429 +
76430 +=====================================================================
76431 +
76432 +
76433 +Name
76434 +    SET_PMKID
76435 +
76436 +Synopsis
76437 +    The host uses this command to enable or disable a pairwise master key ID (PMKID)
76438 +    in the AR6000 PMKID cache. The AR6000 clears its PMKID cache on receipt of a
76439 +    DISCONNECT command from the host. Individual entries in the cache might be
76440 +    deleted as the AR6000 detect new APs and decides to remove old ones.
76441 +
76442 +Command
76443 +    wmiconfig eth1 --setbsspmkid --bssid=<aabbccddeeff>
76444 +    --bsspmkid=<pmkid>
76445 +
76446 +Command Parameters
76447 +    UINT8    bssid[6]
76448 +        The MAC address of the AP that the
76449 +        PMKID corresponds to (6 bytes in hex
76450 +        format)
76451 +
76452 +    UINT8    enable
76453 +        Either PMKID_DISABLE (0) to disable
76454 +        the PMKID or PMKID_ENABLE (1) to
76455 +        enable it (16 bytes in hex format)
76456 +
76457 +    UINT8    pmkid[16]
76458 +        Meaningful only if enable is
76459 +        PMKID_ENABLE, when it is the PMKID
76460 +        that the AR6000 should use on the next
76461 +        reassociation with the specified AP
76462 +
76463 +Command Values
76464 +    enable
76465 +    = 0 (disable), 1 (enable)
76466 +    PKMID enabled/disabled
76467 +
76468 +Reset Values
76469 +    None defined
76470 +
76471 +Restrictions
76472 +    Only supported in infrastructure networks
76473 +
76474 +=====================================================================
76475 +
76476 +
76477 +Name
76478 +    SET_PMKID_LIST_CMD
76479 +
76480 +Synopsis
76481 +    Configures the list of PMKIDs on the firmware.
76482 +
76483 +Command
76484 +    wmiconfig --setpmkidlist --numpmkid=<n> --pmkid=<pmkid_1>
76485 +    ... --pmkid=<pmkid_n>
76486 +
76487 +    Where n is the number of pmkids (maximum = 8) and pmkid_i is the ith pmkid (16
76488 +    bytes in hex format)
76489 +
76490 +Command Parameters
76491 +    {
76492 +        A_UINT8 pmkid[WMI_PMKID_LEN];
76493 +    } __ATTRIB_PACK WMI_PMKID;
76494 +
76495 +    {
76496 +        A_UINT32 numPMKID;
76497 +        WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE];
76498 +    } __ATTRIB_PACK WMI_SET_PMKID_LIST_CMD;
76499 +
76500 +Command Values
76501 +    None
76502 +
76503 +Reset Values
76504 +    None
76505 +
76506 +Restrictions
76507 +    Supported only in infrastructure modes
76508 +
76509 +=====================================================================
76510 +
76511 +
76512 +Name
76513 +    SET_POWER_MODE
76514 +
76515 +Synopsis
76516 +    The host uses this command to provide the AR6000 device with guidelines on the
76517 +    desired trade-off between power utilization and performance.
76518 +
76519 +        In normal power mode, the device enters a sleep state if they have nothing to do,
76520 +        which conserves power but may cost performance as it can take up to 2 ms to
76521 +        resume operation after leaving sleep state.
76522 +
76523 +        In maximum performance mode, the device never enters sleep state, thus no time
76524 +        is spent waking up, resulting in higher power consumption and better
76525 +        performance.
76526 +
76527 +Command
76528 +    TBD
76529 +
76530 +Command Parameters
76531 +    UINT8    powerMode
76532 +        WMI_POWER_MODE value
76533 +    {
76534 +        REC_POWER   = 1
76535 +            (Recommended setting) Tries to conserve
76536 +            power without sacrificing performance
76537 +        MAX_PERF_POWER    = 2
76538 +            Setting that maximizes performance at
76539 +            the expense of power
76540 +
76541 +            All other values are reserved
76542 +    } WMI_POWER_MODE
76543 +
76544 +Command Values
76545 +    See command parameters
76546 +
76547 +Reset Values
76548 +    powerMode is REC_POWER
76549 +
76550 +Restrictions
76551 +    This command should only be issued in the DISCONNECTED state for the
76552 +    infrastructure network.
76553 +
76554 +            For a PM-disabled ad hoc network, the power mode should remain in
76555 +            MAX_PERF_POWER.
76556 +
76557 +            For a PM-enabled ad hoc network, the device can have REC_POWER or
76558 +            MAX_PERF_POWER set, but either way it must follow the power save ad hoc
76559 +            protocol. The host can change power modes in the CONNECTED state.
76560 +
76561 +    Host changes to the PS setting when the STA is off the home channel take no effect
76562 +    and cause a TARGET_PM_FAIL event.
76563 +
76564 +=====================================================================
76565 +
76566 +
76567 +Name
76568 +    SET_POWER_PARAMS
76569 +
76570 +Synopsis
76571 +    The host uses this command to configure power parameters
76572 +
76573 +Command
76574 +    wmiconfig eth1 --pmparams --it=<ms> --np=<number of PS POLL>
76575 +    --dp=<DTIM policy: ignore/normal/stick>
76576 +
76577 +Command Parameters
76578 +    UINT16    idle_period
76579 +        Length of time (in ms) the AR6000 device
76580 +        remains awake after frame Rx/Tx before going
76581 +        to SLEEP state
76582 +
76583 +    UINT16    pspoll_number
76584 +            The number of PowerSavePoll (PS-poll)
76585 +            messages the device should send before
76586 +            notifying the AP it is awake
76587 +
76588 +    UINT16    dtim_policy
76589 +            A WMI_POWER_PARAMS_CMD value
76590 +
76591 +    {
76592 +        IGNORE_DTIM    =1
76593 +            The device does not listen to any content after
76594 +            beacon (CAB) traffic
76595 +        NORMAL_DTIM    = 2
76596 +            DTIM period follows the listen interval (e.g., if
76597 +            the listen interval is 4 and the DTIM period is 2,
76598 +            the device wakes up every fourth beacon)
76599 +        STICK_DTIM    = 3
76600 +            Device attempt to receive all CAB traffic (e.g., if
76601 +            the DTIM period is 2 and the listen interval is 4,
76602 +            the device wakes up every second beacon)
76603 +    } WMI_POWER_PARAMS_CMD
76604 +
76605 +Command Parameters
76606 +    See command parameters
76607 +
76608 +Reset Values
76609 +    idle_period
76610 +        200 ms
76611 +
76612 +    pspoll_number
76613 +    = 1
76614 +
76615 +    dtim_policy
76616 +    = NORMAL_DTIM
76617 +
76618 +Restrictions
76619 +    None
76620 +
76621 +=====================================================================
76622 +
76623 +
76624 +Name
76625 +    SET_POWERSAVE_PARAMS
76626 +
76627 +Synopsis
76628 +    Set the two AR6000 power save timers (PS-POLL timer and APSD trigger timer) and
76629 +    the two ASPD TIM policies
76630 +
76631 +Command
76632 +    wmiconfig eth1--psparams --psPollTimer=<psPollTimeout in ms>
76633 +    --triggerTimer=<triggerTimeout in ms> --apsdTimPolicy=<ignore/
76634 +    adhere> --simulatedAPSDTimPolicy=<ignore/adhere>
76635 +
76636 +Command Parameters
76637 +    typedef struct {
76638 +        A_UINT16    psPollTimeout;
76639 +            Timeout (in ms) after sending PS-POLL; the
76640 +            AR6000 device sleeps if it does not receive a
76641 +            data packet from the AP
76642 +
76643 +        A_UINT16    triggerTimeout;
76644 +            Timeout (in ms) after sending a trigger; the
76645 +            device sleeps if it does not receive any data
76646 +            or null frame from the AP
76647 +
76648 +        APSD_TIM_POLICY    apsdTimPolicy;
76649 +            TIM behavior with queue APSD enabled
76650 +
76651 +        APSD_TIM_POLICY    simulatedAPSD
76652 +
76653 +        TimPolicy;
76654 +            TIM behavior with simulated APSD
76655 +            enabled
76656 +
76657 +    typedef enum {
76658 +        IGNORE_TIM_ALL_QUEUES_APSD = 0,
76659 +        PROCESS_TIM_ALL_QUEUES_APSD = 1,
76660 +        IGNORE_TIM_SIMULATED_APSD = 2,
76661 +        POWERSAVE_TIMERS_POLICY = 3,
76662 +    } APSD_TIM_POLICY;
76663 +
76664 +Command Values
76665 +    None
76666 +
76667 +Reset Values
76668 +    psPollTimeout is 50 ms; triggerTimeout is 10 ms;
76669 +    apsdTimPolicy = IGNORE_TIM_ALL_QUEUES_APSD;
76670 +    simulatedAPSDTimPolicy = POWERSAVE_TIMERS_POLICY
76671 +
76672 +Restrictions
76673 +    When this command is used, all parameters must be set; this command does not
76674 +    allow setting only one parameter.
76675 +
76676 +=====================================================================
76677 +
76678 +
76679 +Name
76680 +    SET_PROBED_SSID
76681 +
76682 +Synopsis
76683 +    The host uses this command to provide a list of up to MAX_PROBED_SSID_INDEX
76684 +    (six) SSIDs that the AR6000 device should actively look for. It lists the active SSID
76685 +    table. By default, the device actively looks for only the SSID specified in the
76686 +    \93CONNECT_CMD\94 command, and only when the regulatory domain allows active
76687 +    probing. With this command, specified SSIDs are probed for, even if they are hidden.
76688 +
76689 +Command
76690 +    wmiconfig eth1 --ssid=<ssid> [--num=<index>]
76691 +
76692 +Command Parameters
76693 +    {
76694 +        A_UINT8    numSsids
76695 +            A number from 0 to
76696 +            MAX_PROBED_SSID_INDEX indicating
76697 +            the active SSID table entry index for this
76698 +            command (if the specified entry index
76699 +            already has an SSID, the SSID specified in
76700 +            this command replaces it)
76701 +
76702 +        WMI_PROBED_SSID_INFO    probedSSID[1]
76703 +    } WMI_PROBED_SSID_CMD
76704 +
76705 +    {
76706 +        A_UINT8    flag
76707 +            WMI_SSID_FLAG indicates the current
76708 +            entry in the active SSID table
76709 +        A_UINT8    ssidLength
76710 +            Length of the specified SSID in bytes.
76711 +            If = 0, the entry corresponding to the
76712 +            index is erased
76713 +        A_UINT8    ssid[32]
76714 +            SSID string actively probed for when
76715 +            permitted by the regulatory domain
76716 +    } WMI_PROBED_SSID_INFO
76717 +
76718 +Command Values
76719 +    WMI_SSID_FLAG
76720 +    {
76721 +         DISABLE_SSID_FLAG    = 0
76722 +            Disables entry
76723 +        SPECIFIC_SSID_FLAG    = 1
76724 +            Probes specified SSID
76725 +        ANY_SSID_FLAG    = 2
76726 +            Probes for any SSID
76727 +    } WMI_SSID_FLAG
76728 +
76729 +Reset Value
76730 +    The entries are unused.
76731 +
76732 +Restrictions
76733 +    None
76734 +
76735 +=====================================================================
76736 +
76737 +
76738 +Name
76739 +    SET_REASSOC_MODE
76740 +
76741 +Synopsis
76742 +    Specify whether the disassociated frame should be sent or not upon reassociation.
76743 +
76744 +Command
76745 +    wmiconfig eth1 --setreassocmode <mode>
76746 +
76747 +Command Parameters
76748 +    UINT8    mode
76749 +
76750 +Command Values
76751 +    mode
76752 +        = 0x00
76753 +        Send disassoc to a previously connected AP
76754 +        upon reassociation
76755 +        = 0x01
76756 +        Do not send disassoc to previously connected
76757 +        AP upon reassociation
76758 +
76759 +Reset Values
76760 +    None defined
76761 +
76762 +Restrictions
76763 +    None
76764 +
76765 +
76766 +=====================================================================
76767 +
76768 +Name
76769 +    SET_RETRY_LIMITS
76770 +
76771 +Synopsis
76772 +    Allows the host to influence the number of times that the AR6000 device should
76773 +    attempt to send a frame before they give up.
76774 +
76775 +Command
76776 +    wmiconfig --setretrylimits <frameType> <trafficClass> <maxRetries>
76777 +    <enableNotify>
76778 +
76779 +Command Parameters
76780 +    {
76781 +        UINT8    frameType
76782 +            A WMI_FRAMETYPE specifying
76783 +            which type of frame is of interest.
76784 +        UINT8    trafficClass
76785 +            Specifies a traffic class (see
76786 +            \93CREATE_PSTREAM\94). This
76787 +            parameter is only significant when
76788 +            frameType = DATA_FRAMETYPE.
76789 +        UINT8    maxRetries
76790 +            Maximum number of times the
76791 +            device attempts to retry a frame Tx,
76792 +            ranging from WMI_MIN_RETRIES
76793 +            (2) to WMI_MAX_RETRIES (15). If
76794 +            the special value 0 is used,
76795 +            maxRetries is set to 15.
76796 +        A_UINT8    enableNotify
76797 +            Notify when enabled
76798 +    } WMI_RETRY_LIMIT_INFO
76799 +
76800 +    {
76801 +        A_UINT8    numEntries
76802 +        WMI_RETRY_LIMIT_INFO  retryLimitInfo[1]
76803 +    } WMI_SET_RETRY_LIMITS_CMD
76804 +
76805 +Command Values
76806 +    {
76807 +        MGMT_FRAMETYPE    = 0    Management frame
76808 +        CONTROL_FRAMETYPE = 1    Control frame
76809 +        DATA_FRAMETYPE    = 2    Data frame
76810 +    } WMI_FRAMETYPE
76811 +
76812 +Reset Values
76813 +    Retries are set to 15
76814 +
76815 +Restrictions
76816 +    None
76817 +
76818 +=====================================================================
76819 +
76820 +
76821 +Name
76822 +    SET_ROAM_CTRL
76823 +
76824 +Synopsis
76825 +    Affects how the AR6000 device selects a BSS. The host uses this command to set and
76826 +    enable low RSSI scan parameters. The time period of low RSSI background scan is
76827 +    mentioned in scan period. Low RSSI scan is triggered when the current RSSI
76828 +    threshold (75% of current RSSI) is equal to or less than scan threshold.
76829 +
76830 +    Low RSSI roam is triggered when the current RSSI threshold falls below the roam
76831 +    threshold and roams to a better AP by the end of the scan cycle. During Low RSSI
76832 +    roam, if the STA finds a new AP with an RSSI greater than roam RSSI to floor, during
76833 +    scan, it roams immediately to it instead of waiting for the end of the scan cycle. See
76834 +    also \93Scan and Roam\94 on page C-1.
76835 +
76836 +Command
76837 +    wmiconfig --roam <roamctrl> <info>, where info is <scan period>
76838 +    <scan threshold> <roam threshold> <roam rssi floor>
76839 +
76840 +Command Parameters
76841 +    A_UINT8    roamCtrlType;
76842 +
76843 +Command Values
76844 +    WMI_FORCE_ROAM     = 1
76845 +    Roam to the specified BSSID
76846 +
76847 +    WMI_SET_ROAM_MODE  = 2
76848 +    Default, progd bias, no roam
76849 +
76850 +    WMI_SET_HOST_BIAS  = 3
76851 +    Set the host bias
76852 +
76853 +    WMI_SET_LOWRSSI_SCAN_PARAMS  = 4
76854 +    Info parameters
76855 +
76856 +    A_UINT8    bssid[ATH_MAC_LEN];
76857 +    WMI_FORCE_ROAM
76858 +
76859 +    A_UINT8    roamMode;
76860 +    WMI_SET_ROAM_MODE
76861 +
76862 +    A_UINT8    bssBiasInfo;
76863 +    WMI_SET_HOST_BIAS
76864 +
76865 +    A_UINT16    lowrssi_scan_period;
76866 +    WMI_SET_LOWRSSI_SCAN_PARAMS
76867 +
76868 +    A_INT16
76869 +    lowrssi_scan_threshold;
76870 +    WMI_SET_LOWRSSI_SCAN_PARAMS
76871 +
76872 +    A_INT16    lowrssi_roam_threshold;
76873 +    WMI_SET_LOWRSSI_SCAN_PARAMS
76874 +
76875 +    A_UINT8    roam_rssi_floor;
76876 +    WMI_SET_LOWRSSI_SCAN_PARAMS
76877 +
76878 +Reset Value
76879 +    None defined (default lowrssi scan is disabled. Enabled only when scan period is set.)
76880 +
76881 +Restrictions
76882 +    None
76883 +
76884 +=====================================================================
76885 +
76886 +
76887 +Name
76888 +    SET_RTS
76889 +
76890 +Synopsis
76891 +    Decides when RTS should be sent.
76892 +
76893 +Command
76894 +    wmiconfig eth1 --setRTS <pkt length threshold>
76895 +
76896 +Command Parameters
76897 +    A_UINT16
76898 +    threshold;
76899 +    Command parameter threshold in bytes. An RTS is
76900 +    sent if the data length is more than this threshold.
76901 +    The default is to NOT send RTS.
76902 +
76903 +Command Values
76904 +    None
76905 +
76906 +Reset Value
76907 +    Not to send RTS.
76908 +
76909 +Restrictions
76910 +    None
76911 +
76912 +
76913 +=====================================================================
76914 +
76915 +Name
76916 +    SET_SCAN_PARAMS
76917 +
76918 +Synopsis
76919 +    The host uses this command to set the AR6000 scan parameters, including the duty
76920 +    cycle for both foreground and background scanning. Foreground scanning takes
76921 +    place when the AR6000 device is not connected, and discovers all available wireless
76922 +    networks to find the best BSS to join. Background scanning takes place when the
76923 +    device is already connected to a network and scans for potential roaming candidates
76924 +    and maintains them in order of best to worst. A second priority of background
76925 +    scanning is to find new wireless networks.
76926 +
76927 +    The device initiates a scan when necessary. For example, a foreground scan is always
76928 +    started on receipt of a \93CONNECT_CMD\94 command or when the device cannot find
76929 +    a BSS to connect to. Foreground scanning is disabled by default until receipt of a
76930 +    CONNECT command. Background scanning is enabled by default and occurs every
76931 +    60 seconds after the device is connected.
76932 +
76933 +    The device implements a binary backoff interval for foreground scanning when it
76934 +    enters the DISCONNECTED state after losing connectivity with an AP or when a
76935 +    CONNECT command is received. The first interval is ForegroundScanStartPeriod,
76936 +    which doubles after each scan until the interval reaches ForegroundScanEndPeriod.
76937 +    If the host terminates a connection with DISCONNECT, the foreground scan period
76938 +    is ForegroundScanEndPeriod. All scan intervals are measured from the time a full
76939 +    scan ends to the time the next full scan starts. The host starts a scan by issuing a
76940 +    \93START_SCAN\94 command. See also \93Scan and Roam\94 on page C-1.
76941 +
76942 +Command
76943 +    wmiconfig eth1 --scan --fgstart=<sec> --fgend=<sec> --bg=<sec> --
76944 +    act=<msec> --pas=<msec> --sr=<short scan ratio> --scanctrlflags
76945 +    <connScan> <scanConnected> <activeScan> <reportBSSINFO>
76946 +
76947 +Command Parameters
76948 +    UINT16    fgStartPeriod
76949 +        First interval used by the device when it
76950 +        disconnects from an AP or receives a
76951 +        CONNECT command, specified in seconds (0\96
76952 +        65535). If = 0, the device uses the reset value.
76953 +        If = 65535, the device disables foreground
76954 +        scanning.
76955 +
76956 +    UINT16    fgEndPeriod
76957 +        The maximum interval the device waits between
76958 +        foreground scans specified in seconds (from
76959 +        ForegroundScanStartPeriod to 65535). If = 0, the
76960 +        device uses the reset value.
76961 +
76962 +    UINT16    bgScanPeriod
76963 +        The period of background scan specified in
76964 +        seconds (0\9665535). By default, it is set to the reset
76965 +        value of 60 seconds. If 0 or 65535 is specified, the
76966 +        device disables background scanning.
76967 +
76968 +    UINT16    maxactChDwellTime
76969 +        The period of time the device stays on a
76970 +        particular channel while active scanning. It is
76971 +        specified in ms (10\9665535). If the special value of
76972 +        0 is specified, the device uses the reset value.
76973 +
76974 +    UINT16    PasChDwellTime
76975 +        The period of time the device remains on a
76976 +        particular channel while passive scanning. It is
76977 +        specified in ms (10\9665535). If the special value of
76978 +        0 is specified, the device uses the reset value.
76979 +
76980 +    UINT8    shortScanRatio
76981 +        Number of short scans to perform for each
76982 +        long scan.
76983 +
76984 +    UINT8    scanCtrlFlasgs
76985 +
76986 +    UINT16    minactChDwellTime
76987 +        Specified in ms
76988 +
76989 +    UINT32    maxDFSchActTime
76990 +        The maximum time a DFS channel can stay
76991 +        active before being marked passive, specified in
76992 +        ms.
76993 +
76994 +Command Values
76995 +    None
76996 +
76997 +Reset Values
76998 +    ForegroundScanStart
76999 +Period
77000 +        1 sec
77001 +
77002 +    ForegroundScanEndPeriod
77003 +        60 sec
77004 +
77005 +    BackgroundScanPeriod
77006 +        60 sec
77007 +
77008 +    ActiveChannelDwellTime
77009 +        105 ms
77010 +
77011 +=====================================================================
77012 +
77013 +
77014 +Name
77015 +    SET_TKIP_COUNTERMEASURES
77016 +
77017 +Synopsis
77018 +    The host issues this command to tell the target whether to enable or disable TKIP
77019 +    countermeasures.
77020 +
77021 +Command
77022 +    TBD
77023 +
77024 +Command Parameters
77025 +    UINT8    WMI_TKIP_CM_ENABLE
77026 +        Enables the countermeasures
77027 +
77028 +
77029 +    UINT8    TKIP_CM_DISABLE
77030 +        Disables the countermeasures
77031 +
77032 +Command Values
77033 +    None
77034 +
77035 +Reset Values
77036 +    By default, TKIP MIC reporting is disabled
77037 +
77038 +Restrictions
77039 +    None
77040 +
77041 +=====================================================================
77042 +
77043 +
77044 +Name
77045 +    SET_TX_PWR
77046 +
77047 +Synopsis
77048 +    The host uses this command to specify the Tx power level of the AR6000. Cannot be
77049 +    used to exceed the power limit permitted by the regulatory domain. The maximum
77050 +    output power is limited in the chip to 31.5 dBm; the range is 0 \96 31.5 dbm.
77051 +
77052 +Command
77053 +    wmiconfig --power <dbM>
77054 +
77055 +Command Parameters
77056 +    UINT8    dbM
77057 +        The desired Tx power specified in dbM.
77058 +        If = 0, the device chooses the maximum
77059 +        permitted by the regulatory domain.
77060 +
77061 +Command Values
77062 +    None
77063 +
77064 +Reset Values
77065 +    The maximum permitted by the regulatory domain
77066 +
77067 +Restrictions
77068 +    None
77069 +
77070 +See Also
77071 +    \93GET_TX_PWR\94
77072 +
77073 +
77074 +=====================================================================
77075 +
77076 +Name
77077 +    SET_VOICE_PKT_SIZE
77078 +
77079 +Synopsis
77080 +    If an AP does not support WMM, it has no way to differentiate voice from data.
77081 +    Because the voice packet is typically small, packet in size less than voicePktSize are
77082 +    assumed to be voice, otherwise it is treated as data.
77083 +
77084 +Command
77085 +    wmiconfig eth1 --setVoicePktSize <size-in-bytes>
77086 +
77087 +Command Parameters
77088 +    UINT16    voicePktSize
77089 +        Packet size in octets
77090 +
77091 +Command Values
77092 +    None
77093 +
77094 +Reset Values
77095 +    voicePktSize default is 400 bytes
77096 +
77097 +Restrictions
77098 +    No effect if WMM is unavailable
77099 +
77100 +
77101 +=====================================================================
77102 +
77103 +Name
77104 +    SET_WMM
77105 +
77106 +Synopsis
77107 +    Overrides the AR6000 device WMM capability
77108 +
77109 +Command
77110 +    wmiconfig eth1 --setwmm <enable>
77111 +
77112 +Command Parameters
77113 +    WMI_WMM_ENABLED
77114 +        Enables WMM
77115 +
77116 +    WMI_WMM_DISABLED
77117 +        Disables WMM support
77118 +
77119 +Command Values
77120 +    0 = disabled
77121 +    1 = enabled
77122 +
77123 +Reset Value
77124 +    WMM Disabled
77125 +
77126 +Restrictions
77127 +    None
77128 +
77129 +
77130 +=====================================================================
77131 +
77132 +Name
77133 +    SET_WMM_TXOP
77134 +
77135 +Synopsis
77136 +    Configures TxOP Bursting when sending traffic to a WMM capable AP
77137 +
77138 +Command
77139 +    wmiconfig eth1 --txopbursting <burstEnable>
77140 +
77141 +    <burstEnable>
77142 +        = 0
77143 +    Disallow TxOp bursting
77144 +
77145 +        = 1
77146 +    Allow TxOp bursting
77147 +
77148 +Command Parameters
77149 +    txopEnable
77150 +        = WMI_TXOP_DISABLED
77151 +        Disabled
77152 +
77153 +        = WMI_TXOP_ENABLED
77154 +        Enabled
77155 +
77156 +Command Values
77157 +    txopEnable
77158 +        = 0    Disabled
77159 +
77160 +        = 1    Enabled
77161 +
77162 +Reset Value
77163 +    Bursting is off by default
77164 +
77165 +Restrictions
77166 +    None
77167 +
77168 +=====================================================================
77169 +
77170 +
77171 +Name
77172 +    SET_WOW_MODE
77173 +
77174 +Synopsis
77175 +    The host uses this command to enable or disable the WoW mode. When WoW mode
77176 +    is enabled and the host is asleep, pattern matching takes place at the target level.
77177 +    Only packets that match any of the pre-specified WoW filter patterns, will be passed
77178 +    up to the host. The host will also be woken up by the target. Packets which do not
77179 +    match any of the WoW patterns are discarded.
77180 +
77181 +Command
77182 +    wmiconfig \96setwowmode <enable/disable>
77183 +
77184 +Command Parameters
77185 +    A_BOOL    enable_wow
77186 +        Enable or disable WoW:
77187 +
77188 +Command Values
77189 +        = 0
77190 +    Disable WoW
77191 +
77192 +        = 1
77193 +    Enable WoW
77194 +
77195 +Reset Value
77196 +    None defined (default WoW mode is disabled).
77197 +
77198 +Restrictions
77199 +    None
77200 +
77201 +See Also
77202 +    \93GET_WOW_LIST\94
77203 +
77204 +
77205 +=====================================================================
77206 +
77207 +Name
77208 +    SET_WSC_STATUS
77209 +
77210 +Synopsis
77211 +    The supplicant uses this command to inform the target about the status of the WSC
77212 +    registration protocol. During the WSC registration protocol, a flag is set so the target
77213 +    bypasses some of the checks in the CSERV module. At the end of the registration, this
77214 +    flag is reset.
77215 +
77216 +Command
77217 +    N/A
77218 +
77219 +Command Parameters
77220 +    A_BOOL status
77221 +        = 1    WSC registration in progress
77222 +        = 0    WSC protocol not running
77223 +
77224 +Reply Parameters
77225 +    None
77226 +
77227 +Reset Value
77228 +    None defined (default = 0)
77229 +
77230 +Restrictions
77231 +    None
77232 +
77233 +
77234 +=====================================================================
77235 +
77236 +Name
77237 +    SNR_THRESHOLD_PARAMS
77238 +
77239 +Synopsis
77240 +    Configures how the AR6000 device monitors and reports SNR of the connected BSS,
77241 +    used as a link quality metric.
77242 +
77243 +Command
77244 +    --snrThreshold <weight> <upper_threshold_1> ...
77245 +    <upper_threshold_4> <lower_threshold_1> ... <lower_threshold_4>
77246 +    <pollTimer>
77247 +
77248 +Command Parameters
77249 +    <weight>
77250 +        Share with rssiThreshold. Range in [1, 16], used
77251 +        in the formula to calculate average RSSI
77252 +
77253 +    <upper_threshold_x>
77254 +        Above thresholds expressed in db, in ascending
77255 +        order
77256 +
77257 +    <lower_threshold_x>
77258 +        Below thresholds expressed in db, in ascending
77259 +        order
77260 +
77261 +    <pollTimer>
77262 +        The signal strength sampling frequency in
77263 +        seconds. If polltime = 0, signal strength
77264 +        sampling is disabled
77265 +
77266 +Command Values
77267 +    None
77268 +
77269 +Reset Value
77270 +    None defined
77271 +
77272 +Restrictions
77273 +    None
77274 +
77275 +=====================================================================
77276 +
77277 +
77278 +Name
77279 +    START_SCAN
77280 +
77281 +Synopsis
77282 +    The host uses this command to start a long or short channel scan. All future scans are
77283 +    relative to the time the AR6000 device processes this command. The device performs
77284 +    a channel scan on receipt of this command, even if a scan was already in progress.
77285 +    The host uses this command when it wishes to refresh its cached database of wireless
77286 +    networks. The isLegacy field will be removed (0 for now) because it is achieved by
77287 +    setting CONNECT_PROFILE_MATCH_DONE in the CONNECT command. See also
77288 +    \93Scan and Roam\94
77289 +
77290 +Command
77291 +    wmiconfig eth1 --startscan <scan type> <forcefgscan> 0
77292 +    <homeDwellTime> <forceScanInterval>
77293 +
77294 +Command Parameters
77295 +    UINT8    scanType
77296 +        WMI_SCAN_TYPE
77297 +
77298 +Command Values
77299 +    {
77300 +        WMI_LONG_SCAN    =0x0
77301 +            Requests a full scan
77302 +        WMI_SHORT_SCAN   =0x1
77303 +            Requests a short scan
77304 +    } WMI_SCAN_TYPE
77305 +
77306 +    A_BOOL    forceFgScan
77307 +        forceFgScan
77308 +        = 0
77309 +        Disable the foreground scan
77310 +
77311 +        forceFgScan
77312 +        = 1
77313 +        Forces a foreground scan
77314 +
77315 +    A_UINT32    homeDwellTime
77316 +        Maximum duration in the home
77317 +        channel (in ms)
77318 +
77319 +    A_UINT32     forceScanInterval
77320 +        Time interval between scans (in ms)
77321 +
77322 +    A_UINT32     scanType
77323 +        WMI_SCAN_TYPE
77324 +
77325 +Reset Value
77326 +    Disable forcing foreground scan
77327 +
77328 +Restrictions
77329 +    isLegacy field will no longer be supported (pass as 0 for now)
77330 +
77331 +
77332 +=====================================================================
77333 +
77334 +Name
77335 +    SYNCHRONIZE
77336 +
77337 +Synopsis
77338 +    The host uses this command to force a synchronization point between the command
77339 +    and data paths
77340 +
77341 +Command
77342 +    TBD
77343 +
77344 +Command Parameters
77345 +    None
77346 +
77347 +
77348 +
77349 +Command Values
77350 +    None
77351 +
77352 +
77353 +
77354 +Reset Values
77355 +    None
77356 +
77357 +
77358 +
77359 +Restrictions
77360 +    None
77361 +
77362 +
77363 +=====================================================================
77364 +
77365 +Name
77366 +    TARGET_ERROR_REPORT_BITMASK
77367 +
77368 +Synopsis
77369 +    Allows the host to control \93ERROR_REPORT\94 events from the AR6000 device.
77370 +
77371 +        If error reporting is disabled for an error type, a count of errors of that type is
77372 +        maintained by the device.
77373 +
77374 +        If error reporting is enabled for an error type, an \93ERROR_REPORT\94 event is
77375 +        sent when an error occurs and the error report bit is cleared.
77376 +
77377 +    Error counts for each error type are available through the \93GET_TARGET_STATS\94
77378 +    command.
77379 +
77380 +Command
77381 +    wmiconfig eth1 --setErrorReportingBitmask
77382 +
77383 +Command Parameters
77384 +    UINT32    bitmask
77385 +        Represents the set of
77386 +        WMI_TARGET_ERROR_VAL error types
77387 +        enabled for reporting
77388 +
77389 +Command Values
77390 +    {
77391 +        WMI_TARGET_PM_ERR_FAIL    = 0x00000001
77392 +            Power save fails (only two cases):
77393 +               Retry out of null function/QoS null
77394 +               function to associated AP for PS
77395 +               indication'
77396 +               Host changes the PS setting when
77397 +               STA is off home channel
77398 +
77399 +        WMI_TARGET_KEY_NOT_FOUND    = 0x00000002
77400 +            No cipher key
77401 +        WMI_TARGET_DECRYPTION_ERR   = 0x00000004
77402 +            Decryption error
77403 +        WMI_TARGET_BMISS            = 0x00000008
77404 +            Beacon miss
77405 +        WMI_PSDISABLE_NODE_JOIN     = 0x00000010
77406 +            A non-PS-enabled STA joined the
77407 +            PS-enabled network
77408 +        WMI_TARGET_COM_ERR          = 0x00000020
77409 +            Host/target communication error
77410 +        WMI_TARGET_FATAL_ERR        = 0x00000040
77411 +            Fatal error
77412 +    } WMI_TARGET_ERROR_VAL
77413 +
77414 +Reset Values
77415 +    Bitmask is 0, and all error reporting is disabled
77416 +
77417 +Restrictions
77418 +    None
77419 +
77420 +
77421 +=====================================================================
77422 +WMI Events
77423 +
77424 +Event
77425 +    Description
77426 +    Page
77427 +
77428 +
77429 +BSSINFO
77430 +    Contains information describing BSSs collected during a scan
77431 +
77432 +CAC_EVENTID
77433 +    Indicates signalling events in admission control
77434 +
77435 +CMDERROR
77436 +    The AR6000 device encounters an error while attempting to process
77437 +    a command
77438 +
77439 +CONNECT
77440 +    The device has connected to a wireless network
77441 +
77442 +DISCONNECT
77443 +    The device lost connectivity with a wireless network
77444 +
77445 +ERROR_REPORT
77446 +    An error has occurred for which the host previously requested
77447 +    notification with the command
77448 +    \93TARGET_ERROR_REPORT_BITMASK\94
77449 +
77450 +EXTENSION
77451 +    WMI extension event
77452 +
77453 +GET_PMKID_LIST_EVENT
77454 +    Created in response to a \93GET_PMKID_LIST_CMD\94 command
77455 +
77456 +GET_WOW_LIST_EVENT
77457 +    Response to the wmiconfig \93GET_WOW_LIST\94 command to
77458 +    retrieve the configured WoW patterns
77459 +
77460 +NEIGHBOR_REPORT
77461 +    Neighbor APs that match the current profile were detected
77462 +
77463 +OPT_RX_FRAME_EVENT
77464 +    (Special feature) informs the host of the reception of a special frame
77465 +
77466 +PSTREAM_TIMEOUT
77467 +    A prioritized stream has been idle for a specified interval
77468 +
77469 +READY
77470 +    The AR6000 device is ready to accept commands
77471 +
77472 +REGDOMAIN
77473 +    The regulatory domain has changed
77474 +
77475 +REPORT_ROAM_DATA_EVENT
77476 +    Reports the roam time calculations made by the device
77477 +    (generated with a special build)
77478 +    \97
77479 +
77480 +REPORT_STATISTICS
77481 +    Reply to a \93GET_TARGET_STATS\94 command
77482 +
77483 +ROAM_TBL_EVENT
77484 +    Reports the roam table
77485 +
77486 +RSSI_THRESHOLD
77487 +    Signal strength from the connected AP has crossed the threshold
77488 +    defined in the \93RSSI_THRESHOLD_PARAMS\94 command
77489 +
77490 +SCAN_COMPLETE_EVENT
77491 +    A scan has completed (added status SCAN_ABORTED in release 2.0)
77492 +
77493 +TEST_EVENT
77494 +    Event generated by the TCMD
77495 +
77496 +TKIP_MICERROR
77497 +    TKIP MIC errors were detected
77498 +
77499 +=====================================================================
77500 +
77501 +Name
77502 +    BSSINFO
77503 +
77504 +Synopsis
77505 +    Contains information describing one or more BSSs as collected during a scan.
77506 +    Information includes the BSSID, SSID, RSSI, network type, channel, supported rates,
77507 +    and IEs. BSSINFO events are sent only after the device receives a beacon or probe-
77508 +    response frame that pass the filter specified in the \93SET_BSS_FILTER\94 command.
77509 +    BSSINFO events consist of a small header followed by a copy of the beacon or probe
77510 +    response frame. The 802.11 header is not present. For formats of beacon and probe-
77511 +    response frames please consult the IEEE 802.11 specification.
77512 +
77513 +    The beacons or probe responses containing the IE specified by the
77514 +    WMI_BSS_FILTER_CMD are passed to the host through the
77515 +    WMI_BSSINFO_EVENT. The event carries a 32-bit bitmask that indicates the IEs that
77516 +    were detected in the management frame. The frame type field has been extended to
77517 +    indicate action management frames. This would be helpful to route these frames
77518 +    through the same event mechanism as used by the beacon processing function.
77519 +
77520 +    If the bssFilter in the SET_BSS_FILTER matches, then the ieMask is not relevant
77521 +    because the BSSINFO event is sent to the host. If the bssFilter doesnot match in the
77522 +    beacons/probe respones, then the ieMask match dictates whether the BSSINFO
77523 +    event is sent to the host. In the case of action management frames, the ieMask is the
77524 +    filter that is applied.
77525 +
77526 +Event ID
77527 +    0x1004
77528 +
77529 +Event Parameters
77530 +    typedef struct {
77531 +        A_UINT16    channel;
77532 +            Specifies the frequency (in MHz) where the
77533 +            frame was received
77534 +        A_UINT8    frameType;
77535 +            A WMI_BI_FTYPE value
77536 +        A_UINT8    snr;
77537 +        A_INT16    rssi;
77538 +            Indicates signal strength
77539 +        A_UINT8    bssid[ATH_MAC_LEN];
77540 +        A_UINT32    ieMask;
77541 +    } _ATTRIB_PACK_WMI_BSS_INFO_HDR;
77542 +
77543 +    Beacon or Probe Response Frame
77544 +
77545 +Event Values
77546 +    {
77547 +        BEACON_FTYPE    = 0x1
77548 +            Indicates a beacon frame
77549 +        PROBERESP_FTYPE
77550 +            Indicates a probe response frame
77551 +        ACTION_MGMT_FTYPE
77552 +     } WMI_BI_FTYPE
77553 +
77554 +=====================================================================
77555 +
77556 +Name
77557 +    CAC_EVENTID
77558 +
77559 +Synopsis
77560 +    Indicates signalling events in admission control. Events are generated when
77561 +    admission is accepted, rejected, or deleted by either the host or the AP. If the AP does
77562 +    not respond to an admission request within a timeout of 500 ms, an event is
77563 +    generated to the host.
77564 +
77565 +Event ID
77566 +    0x1011
77567 +
77568 +Event Parameters
77569 +    UINT8
77570 +    ac
77571 +    Access class pertaining to the
77572 +signalling
77573 +
77574 +    UINT8    cac_indication
77575 +        Type of indication; indications are
77576 +        listed in WMI_CAC_INDICATION
77577 +
77578 +    UINT8    statusCode
77579 +        AP response status code for a
77580 +        request
77581 +
77582 +    UINT8    tspecSuggestion[63]
77583 +        Suggested TSPEC from AP
77584 +
77585 +Event Values
77586 +    {
77587 +        CAC_INDICATION_ADMISSION = 0x00
77588 +        CAC_INDICATION_ADMISSION_RESP    = 0x01
77589 +        CAC_INDICATION_DELETE    = 0x02
77590 +        CAC_INDICATION_NO_RESP   = 0x03
77591 +    } WMI_CAC_INDICATION
77592 +
77593 +
77594 +=====================================================================
77595 +
77596 +
77597 +Name
77598 +    CMDERROR
77599 +
77600 +Synopsis
77601 +    Indicates that the AR6000 device encountered an error while attempting to process a
77602 +    command. This error is fatal and indicates that the device requires a reset.
77603 +
77604 +Event ID
77605 +    0x1005
77606 +
77607 +Event Parameters
77608 +    UINT16    commandId
77609 +        Corresponds to the command which generated
77610 +        the error
77611 +    UINT8    errorCode
77612 +        A WMI_ERROR_CODE value
77613 +
77614 +Event Values
77615 +    {
77616 +        INVALID_PARAM    = 1
77617 +            Invalid parameter
77618 +        ILLEGAL_STATE    = 2
77619 +            Illegal state
77620 +        INTERNAL_ERROR   = 3
77621 +            Internal Error
77622 +        All other values reserved
77623 +    } WMI_ERROR_CODE
77624 +
77625 +
77626 +=====================================================================
77627 +
77628 +
77629 +Name
77630 +    CONNECT
77631 +
77632 +Synopsis
77633 +    Signals that the AR6000 connected to a wireless network. Connection occurs due to a
77634 +    \93CONNECT\94 command or roaming to a new AP. For infrastructure networks, shows
77635 +    that the AR6000 successfully performed 802.11 authentication and AP association.
77636 +
77637 +Event ID
77638 +    0x1002
77639 +
77640 +Event Parameters
77641 +    UINT16    channel
77642 +        Channel frequency (in MHz) of the network the
77643 +        AR6000 are connected to
77644 +
77645 +    UINT8    bssid[6]
77646 +        MAC address of the AP the AR6000 are
77647 +        connected to or the BSSID of the ad hoc
77648 +        network
77649 +
77650 +    UINT16    listenInterval
77651 +        Listen interval (in Kms) that the AR6000 are
77652 +        using
77653 +
77654 +    UINT 8    beaconIeLen
77655 +        Length (in bytes) of the beacon IEs
77656 +
77657 +    UINT8    assocInfo
77658 +        Pointer to an array containing beacon IEs,
77659 +        followed first by association request IEs then by
77660 +        association response IEs
77661 +
77662 +    UINT8    assocReqLen
77663 +        Length (in bytes) of the assocReqIEs array
77664 +
77665 +    UINT8    assocRespLen
77666 +        Length (in bytes) of the assocRespIEs array
77667 +
77668 +Event Values
77669 +    None defined
77670 +
77671 +=====================================================================
77672 +
77673 +
77674 +Name
77675 +    DISCONNECT
77676 +
77677 +Synopsis
77678 +    Signals that the AR6000 device lost connectivity with the wireless network.
77679 +    DISCONENCT is generated when the device fails to complete a \93CONNECT\94
77680 +    command or as a result of a transition from a connected state to disconnected state.
77681 +
77682 +    After sending the \93DISCONNECT\94 event the device continually tries to re-establish
77683 +    a connection. A LOST_LINK occurs when STA cannot receive beacons within the
77684 +    specified time for the SET_BMISS_TIME command.
77685 +
77686 +Event ID
77687 +    0x1003
77688 +
77689 +Event Parameters
77690 +    UINT8    disconnect
77691 +        Reason
77692 +        A WMI_DISCONNECT_REASON value
77693 +
77694 +    UINT8    bssid[6]
77695 +        Indicates which BSS the device was connected to
77696 +
77697 +    UINT8    assocRespLen
77698 +        Length of the 802.11 association response frame
77699 +        that triggered this event, or 0 if not applicable
77700 +
77701 +    UINT8    assocInfo[assocRespLen]
77702 +        Copy of the 802.11 association response frame
77703 +
77704 +Event Values
77705 +    {
77706 +        NO_NETWORK_AVAIL    =0x01
77707 +            Indicates that the device was unable to
77708 +            establish or find the desired network
77709 +        LOST_LINK    =0x02
77710 +            Indicates the devices is no longer receiving
77711 +            beacons from the BSS it was previously
77712 +            connected to
77713 +
77714 +        DISCONNECT_CMD  =0x03
77715 +            Indicates a \93DISCONNECT\94 command was
77716 +            processed
77717 +        BSS_DISCONNECTED =0x04
77718 +            Indicates the BSS explicitly disconnected the
77719 +            device. Possible mechanisms include the AP
77720 +            sending 802.11 management frames
77721 +            (e.g., disassociate or deauthentication
77722 +            messages).
77723 +        AUTH_FAILED    =0x05
77724 +            Indicates that the device failed 802.11
77725 +            authentication with the BSS
77726 +        ASSOC_FAILED    =0x06
77727 +            Indicates that the device failed 802.11
77728 +            association with the BSS
77729 +        NO_RESOURCES_AVAIL    =0x07
77730 +            Indicates that a connection failed because the
77731 +            AP had insufficient resources to complete the
77732 +            connection
77733 +        CSERV_DISCONNECT    =0x08
77734 +            Indicates that the device\92s connection services
77735 +            module decided to disconnect from a BSS,
77736 +            which can happen for a variety of reasons (e.g.,
77737 +            the host marks the current connected AP as a
77738 +            bad AP).
77739 +        INVALID_PROFILE    =0x0A
77740 +            Indicates that an attempt was made to
77741 +            reconnect to a BSS that no longer matches the
77742 +            current profile
77743 +        All other values are reserved
77744 +    } WMI_DISCONNECT_REASON
77745 +
77746 +
77747 +=====================================================================
77748 +
77749 +
77750 +Name
77751 +    ERROR_REPORT
77752 +
77753 +Synopsis
77754 +    Signals that a type of error has occurred for which the host previously requested
77755 +    notification through the \93TARGET_ERROR_REPORT_BITMASK\94 command.
77756 +
77757 +Event ID
77758 +    0x100D
77759 +
77760 +Event Parameters
77761 +    UINT32    errorVal
77762 +            WMI_TARGET_ERROR_VAL value. See
77763 +            \93TARGET_ERROR_REPORT_BITMASK\94.
77764 +
77765 +Event Values
77766 +    errorVal
77767 +    = 0x00000001
77768 +    Power save fails
77769 +
77770 +        = 0x00000002
77771 +    No cipher key
77772 +
77773 +        = 0x00000004
77774 +    Decryption error
77775 +
77776 +        = 0x00000008
77777 +    Beacon miss
77778 +
77779 +        = 0x00000010
77780 +    A non-power save disabled node has joined
77781 +    the PS-enabled network
77782 +
77783 +
77784 +=====================================================================
77785 +
77786 +
77787 +Name
77788 +    EXTENSION
77789 +
77790 +Synopsis
77791 +    The WMI is used mostly for wireless control messages to a wireless module that
77792 +    apply to wireless module management regardless of the target platform
77793 +    implementation. However, some events peripherally related to wireless management
77794 +    are desired during operation. These wireless extension events may be platform-
77795 +    specific or implementation-dependent. See \93WMI Extension Commands\94
77796 +
77797 +
77798 +Event ID
77799 +    0x1010
77800 +
77801 +
77802 +=====================================================================
77803 +
77804 +
77805 +Name
77806 +    GET_PMKID_LIST_EVENT
77807 +
77808 +Synopsis
77809 +    Generated by firmware in response to a \93GET_PMKID_LIST_CMD\94 command.
77810 +
77811 +Event Parameters
77812 +    typedef struct {
77813 +        A_UINT32    numPMKID;
77814 +            Contains the number of PMKIDs in the reply
77815 +        WMI_PMKID   pmkidList[1];
77816 +    } __ATTRIB_PACK WMI_PMKID_LIST_REPLY;
77817 +
77818 +Event Values
77819 +    None
77820 +
77821 +
77822 +=====================================================================
77823 +
77824 +
77825 +Name
77826 +    GET_WOW_LIST_EVENT
77827 +
77828 +Synopsis
77829 +    Response to the wmiconfig \96getwowlist command to retrieve the configured Wake on
77830 +    Wireless patterns
77831 +
77832 +Event ID
77833 +    0x10018
77834 +
77835 +Event Parameters
77836 +    {
77837 +
77838 +    A_UINT8    num_filters
77839 +        Total number of patterns in the list
77840 +    A_UINT8    this_filter_num
77841 +        The filter number
77842 +    A_UINT8    wow_mode
77843 +        Shows whether WoW is enabled or disabled
77844 +    A_UINT8    host_mode
77845 +        Shows whether the host is asleep or awake
77846 +    WOW_FILTER    wow_filters[1]
77847 +        List of WoW filters (pattern and mask data bytes)
77848 +    } WMI_GET_WOW_LIST_REPLY;
77849 +
77850 +    {
77851 +        Each wow_filter_list element shows:
77852 +    A_UINT8    wow_valid_filter
77853 +        Whether the filter is valid
77854 +    A_UINT8    wow_filter_list_id
77855 +        Filter List ID (23 = default)
77856 +    A_UINT8    wow_filter_size
77857 +        Size in bytes of the filter
77858 +    A_UINT8    wow_filter_offset
77859 +        Offset of the pattern to search in the data packet
77860 +    A_UINT8    wow_filter_mask[MASK_SIZE]
77861 +        The mask to be applied to the pattern
77862 +    A_UINT8    wow_filter_pattern[WOW_PATTERN_SIZE]
77863 +        The pattern that to match to wake up the host
77864 +    } WOW_FILTER
77865 +
77866 +Event Values
77867 +    None
77868 +
77869 +=====================================================================
77870 +
77871 +
77872 +
77873 +Name
77874 +    NEIGHBOR_REPORT
77875 +
77876 +Synopsis
77877 +    Indicates the existence of neighbor APs that match the current profile. The host uses
77878 +    this event to populate the PMKID cache on the AR6000 and/or to perform
77879 +    preauthentication. This event is only generated in infrastructure mode.
77880 +
77881 +    A total of numberOfAps pairs of bssid/bssFlags exist, one pair for each AP.
77882 +
77883 +Event ID
77884 +    0x1008
77885 +
77886 +Event Parameters
77887 +    UINT8    numberOfAps
77888 +        The number of APs reported about in
77889 +        this event
77890 +    {
77891 +        UINT8    bssid[6]
77892 +            MAC address of a neighbor AP
77893 +        UINT8    bssFlags
77894 +            A WMI_BSS_FLAGS value
77895 +    }[numberOfAps]
77896 +
77897 +
77898 +Event Values
77899 +    {
77900 +        WMI_DEFAULT_BSS_FLAGS    = 0
77901 +            Logical OR of 1 or more
77902 +        WMI_BSS_FLAGS
77903 +        WMI_PREAUTH_CAPABLE_BSS
77904 +            = 1
77905 +            Indicates that this AP is capable of
77906 +            preauthentication
77907 +        WMI_PMKID_VALID_BSS
77908 +            = 2
77909 +            Indicates that the AR6000 have a
77910 +            valid pairwise master key for this AP
77911 +    } WMI_BSS_FLAGS
77912 +
77913 +
77914 +=====================================================================
77915 +
77916 +
77917 +
77918 +Name
77919 +    OPT_RX_FRAME_EVENT
77920 +
77921 +Synopsis
77922 +    Special feature, informs host of the reception of a special frame.
77923 +
77924 +Event ID
77925 +    0x100E
77926 +
77927 +Event Parameters
77928 +    {
77929 +        A_UINT16    channel;
77930 +        A_UINT8    frameType;
77931 +        A_INT8    snr;
77932 +        A_UINT8    srcAddr[ATH_MAC_LEN];
77933 +        A_UINT8    bssid[ATH_MAC_LEN];
77934 +        }WMI_OPT_RX_INFO_HDR
77935 +
77936 +Event Values
77937 +    None
77938 +
77939 +=====================================================================
77940 +
77941 +
77942 +
77943 +Name
77944 +    PSTREAM_TIMEOUT
77945 +
77946 +Synopsis
77947 +    Indicates that a priority stream that got created as a result of priority-marked data
77948 +    flow (priority marked in IP TOS) being idle for the default inactivity interval period
77949 +    (specified in the \93CREATE_PSTREAM\94 command) used for priority streams created
77950 +    implicitly by the driver. This event is not indicated for user-created priority streams.
77951 +    User-created priority streams exist until the users delete them explicitly. They do not
77952 +    timeout due to data inactivity.
77953 +
77954 +Event ID
77955 +    0x1007
77956 +
77957 +Event Parameters
77958 +    A_UINT8
77959 +    trafficClass
77960 +    Indicated the traffic class of priority
77961 +    stream that timed out
77962 +
77963 +Event Values
77964 +    {
77965 +        WMM_AC_BE    = 0
77966 +            Best effort
77967 +        WMM_AC_BK    = 1
77968 +            Background
77969 +        WMM_AC_VI    = 2
77970 +            Video
77971 +        WMM_AC_VO     = 3
77972 +            Voice
77973 +    } TRAFFIC CLASS
77974 +
77975 +
77976 +=====================================================================
77977 +
77978 +Name
77979 +    READY
77980 +
77981 +Synopsis
77982 +    Indicates that the AR6000 device is prepared to accept commands. It is sent once after
77983 +    power on or reset. It also indicates the MAC address of the device.
77984 +
77985 +Event ID
77986 +    0x1001
77987 +
77988 +Event Parameters
77989 +    UINT8    macAddr[6]
77990 +        Device MAC address
77991 +    UINT8    phyCapability
77992 +        A WMI_PHY_CAPABILITY value. Indicates the
77993 +        capabilities of the device wireless module\92s radio
77994 +
77995 +Event Values
77996 +    {
77997 +        WMI_11A_CAPABILITY       = 1
77998 +        WMI_11G_CAPABILITY       = 2
77999 +        WMI_11AG_CAPABILITY      = 3
78000 +    } WMI_PHY_CAPABILITY
78001 +
78002 +
78003 +=====================================================================
78004 +
78005 +Name
78006 +    REGDOMAIN
78007 +
78008 +Synopsis
78009 +    Indicates that the regulatory domain has changed. It initially occurs when the
78010 +    AR6000 device reads the board data information. The regulatory domain can also
78011 +    change when the device is a world-mode SKU. In this case, the regulatory domain is
78012 +    based on the country advertised by APs per the IEEE 802.11d specification. A
78013 +    potential side effect of a regulatory domain change is a change in the list of available
78014 +    channels. Any channel restrictions that exist as a result of a previous
78015 +    \93SET_CHANNEL_PARAMETERS\94 command are lifted.
78016 +
78017 +Event ID
78018 +    0x1006
78019 +
78020 +Event Parameters
78021 +    UINT32    regDomain
78022 +        The range of 0x0000 \96 0x00FF
78023 +        corresponds to an ISO country code.
78024 +
78025 +    Other regCodes are reserved for world
78026 +    mode settings and specific regulatory
78027 +    domains.
78028 +
78029 +Event Values
78030 +    None
78031 +
78032 +
78033 +=====================================================================
78034 +
78035 +
78036 +
78037 +Name
78038 +    REPORT_STATISTICS
78039 +
78040 +Synopsis
78041 +    A reply to a \93GET_TARGET_STATS\94 command.
78042 +
78043 +Event ID
78044 +    0x100B
78045 +
78046 +Event Parameters
78047 +    When the statistics are sent to the host, the AR6001 clear them so that a new set of
78048 +    statistics are collected for the next report.
78049 +
78050 +    UINT32    tx_packets
78051 +    UINT32    tx_bytes
78052 +    UINT32    tx_unicast_pkts
78053 +    UINT32    tx_unicast_bytes
78054 +    UINT32    tx_multicast_pkts
78055 +    UINT32    tx_multicast_bytes
78056 +    UINT32    tx_broadcast_pkts
78057 +    UINT32    tx_broadcast_bytes
78058 +    UINT32    tx_rts_success_cnt
78059 +    UINT32    tx_packet_per_ac[4]
78060 +        Tx packets per AC: [0] = BE, [1] = BK,
78061 +        [2] = VI, [3] = VO
78062 +    UINT32    tx_errors
78063 +        Number of packets which failed Tx, due
78064 +        to all failures
78065 +    ... REPORT_STATISTICS, continued
78066 +    UINT32    tx_failed_cnt
78067 +        Number of data packets that failed Tx
78068 +    UINT32    tx_retry_cnt
78069 +        Number of Tx retries for all packets
78070 +    UINT32    tx_rts_fail_cnt
78071 +        Number of RTS Tx failed count
78072 +    UINT32    rx_packets
78073 +    UINT32    rx_bytes
78074 +    UINT32    rx_unicast_pkts
78075 +    UINT32    rx_unicast_bytes
78076 +    UINT32    rx_multicast_pkts
78077 +    UINT32    rx_multicast_bytes
78078 +    UINT32    rx_broadcast_pkts
78079 +    UINT32    rx_broadcast_bytes
78080 +    UINT32    rx_fragment_pkt
78081 +        Number of fragmented packets received
78082 +    UINT32    rx_errors
78083 +        Number of Rx errors due to all failures
78084 +    UINT32    rx_crcerr
78085 +        Number of Rx errors due to CRC errors
78086 +    UINT32    rx_key_cache_miss
78087 +        Number of Rx errors due to a key not
78088 +        being plumbed
78089 +    UINT32    rx_decrypt_err
78090 +        Number of Rx errors due to decryption
78091 +        failure
78092 +    UINT32    rx_duplicate_frames
78093 +        Number of duplicate frames received
78094 +    UINT32    tkip_local_mic_failure
78095 +        Number of TKIP MIC errors detected
78096 +    UINT32    tkip_counter_measures_invoked
78097 +        Number of times TKIP countermeasures
78098 +        were invoked
78099 +    UINT32    tkip_replays
78100 +        Number of frames that replayed a TKIP
78101 +        encrypted frame received earlier
78102 +    UINT32    tkip_format_errors
78103 +        Number of frames that did not conform
78104 +        to the TKIP frame format
78105 +    UINT32    ccmp_format_errors
78106 +        Number of frames that did not conform
78107 +        to the CCMP frame format
78108 +    UINT32    ccmp_replays
78109 +        Number of frames that replayed a CCMP
78110 +        encrypted frame received earlier
78111 +    UINT32    power_save_failure_cnt
78112 +        Number of failures that occurred when
78113 +        the AR6001 could not go to sleep
78114 +    UINT32    cs_bmiss_cnt
78115 +        Number of BMISS interrupts since
78116 +    connection
78117 +    UINT32    cs_lowRssi_cnt
78118 +        Number of the times the RSSI went below
78119 +        the low RSSI threshold
78120 +    UINT16    cs_connect_cnt
78121 +        Number of connection times
78122 +    UINT16    cs_disconnect_cnt
78123 +        Number of disconnection times
78124 +    UINT8    cs_aveBeacon_rssi
78125 +        The current averaged value of the RSSI
78126 +        from the beacons of the connected BSS
78127 +    UINT8    cs_lastRoam_msec
78128 +        Time that the last roaming took, in ms.
78129 +        This time is the difference between
78130 +        roaming start and actual connection.
78131 +
78132 +Event Values
78133 +    None defined
78134 +
78135 +
78136 +=====================================================================
78137 +
78138 +Name
78139 +    ROAM_TBL_EVENT
78140 +
78141 +Synopsis
78142 +    Reports the roam table, which contains the current roam mode and this information
78143 +    for every BSS:
78144 +
78145 +Event ID
78146 +    0x100F
78147 +
78148 +Event Parameters
78149 +    A_UINT8     bssid[ATH_MAC_LEN];
78150 +        BSSID
78151 +    A_UINT8     rssi
78152 +        Averaged RSSI
78153 +    A_UINT8     rssidt
78154 +        Change in RSSI
78155 +    A_UINT8     last_rssi
78156 +        Last recorded RSSI
78157 +    A_UINT8     roam_util
78158 +        Utility value used in roaming decision
78159 +    A_UINT8     util
78160 +        Base utility with the BSS
78161 +    A_UINT8     bias
78162 +        Host configured for this BSS
78163 +
78164 +Event Values
78165 +    roamMode
78166 +        Current roam mode
78167 +
78168 +        = 1
78169 +    RSSI based roam
78170 +
78171 +        = 2
78172 +    Host bias-based roam
78173 +
78174 +        = 3
78175 +    Lock to the current BSS
78176 +
78177 +        = 4
78178 +    Autonomous roaming disabled
78179 +
78180 +
78181 +=====================================================================
78182 +
78183 +Name
78184 +    RSSI_THRESHOLD
78185 +
78186 +Synopsis
78187 +    Alerts the host that the signal strength from the connected AP has crossed a
78188 +    interesting threshold as defined in a previous \93RSSI_THRESHOLD_PARAMS\94
78189 +    command.
78190 +
78191 +Event ID
78192 +    0x100C
78193 +
78194 +Event Parameters
78195 +    UINT8    range
78196 +        A WMI_RSSI_THRESHOLD_VAL
78197 +        value, which indicates the range of
78198 +        the average signal strength
78199 +
78200 +Event Values
78201 +    {
78202 +        WMI_RSSI_LOWTHRESHOLD_BELOW_LOWERVAL  = 1
78203 +        WMI_RSSI_LOWTHRESHOLD_LOWERVAL        = 2
78204 +        WMI_RSSI_LOWTHRESHOLD_UPPERVAL        = 3
78205 +        WMI_RSSI_HIGHTHRESHOLD_LOWERVAL       = 4
78206 +        WMI_RSSI_HIGHTHRESHOLD_HIGHERVAL      = 5
78207 +    } WMI_RSSI_THRESHOLD_VAL
78208 +
78209 +
78210 +=====================================================================
78211 +
78212 +Name
78213 +    SCAN_COMPLETE_EVENT
78214 +
78215 +Synopsis
78216 +    Indicates the scan status. if the Scan was not completed, this event is generated with
78217 +    the status A_ECANCELED.
78218 +
78219 +Event ID
78220 +    0x100A
78221 +
78222 +Event Parameters
78223 +    A_UINT8    scanStatus
78224 +
78225 +Event Values
78226 +    {
78227 +        #define     SCAN_ABORTED 16
78228 +        #define     SCAN_COMPLETED 0
78229 +        A_UINT8     scanStatus
78230 +            A_OK or A_ECANCELED
78231 +    } WMI_SCAN_COMPLETE_EVENT;
78232 +
78233 +
78234 +=====================================================================
78235 +
78236 +Name
78237 +    TEST_EVENT
78238 +
78239 +Synopsis
78240 +    The TCMD application uses a single WMI event (WMI_TEST_EVENTID) to
78241 +    communicate events from target to host. The events are parsed by the TCMD
78242 +    application and WMI layer is oblivious of it.
78243 +
78244 +Event ID
78245 +    0x1016
78246 +
78247 +Event Parameters
78248 +    WMI_TEST_EVENTID
78249 +
78250 +
78251 +Event Values
78252 +    None
78253 +
78254 +
78255 +=====================================================================
78256 +
78257 +
78258 +
78259 +Name
78260 +    TKIP_MICERR
78261 +
78262 +Synopsis
78263 +    Indicates that TKIP MIC errors were detected.
78264 +
78265 +Event ID
78266 +    0x1009
78267 +
78268 +Event Parameters
78269 +    UINT8    keyid
78270 +        Indicates the TKIP key ID
78271 +
78272 +    UINT8    ismcast
78273 +        0 = Unicast
78274 +        1 = Multicast
78275 +
78276 +Event Values
78277 +    See event parameters
78278 +
78279 +=====================================================================
78280 +
78281 +WMI Extension Commands
78282 +
78283 +The WMI EXTENSION command is used to multiplex a collection of
78284 +commands that:
78285 +
78286 +        Are not generic wireless commands
78287 +        May be implementation-specific
78288 +        May be target platform-specific
78289 +        May be optional for a host implementation
78290 +
78291 +    An extension command is sent to the AR6000 targets like any other WMI
78292 +command message and uses the WMI_EXTENSION. The first field of the
78293 +payload for this EXTENSION command is another commandId, sometimes
78294 +called the subcommandId, which indicates which extension command is
78295 +being used. A subcommandId-specific payload follows the subcommandId.
78296 +
78297 +All extensions (subcommandIds) are listed in the header file include/wmix.h.
78298 +See also \93WMI Extension Events\94 on page B-58.
78299 +
78300 +
78301 +WMI Extension Commands
78302 +
78303 +
78304 +GPIO_INPUT_GET
78305 +    Read GPIO pins configured for input
78306 +
78307 +GPIO_INTR_ACK
78308 +    Acknowledge and re-arm GPIO interrupts reported earlier
78309 +
78310 +GPIO_OUTPUT_SET
78311 +    Manage output on GPIO pins configured for output
78312 +
78313 +GPIO_REGISTER_GET
78314 +    Read an arbitrary GPIO register
78315 +
78316 +GPIO_REGISTER_SET
78317 +    Dynamically change GPIO configuration
78318 +
78319 +SET_LQTHRESHOLD
78320 +    Set link quality thresholds; the sampling happens at every unicast
78321 +    data frame Tx, if certain thresholds are met, and corresponding
78322 +    events are sent to the host
78323 +
78324 +
78325 +=====================================================================
78326 +
78327 +Name
78328 +    GPIO_INPUT_GET
78329 +
78330 +Synopsis
78331 +    Allows the host to read GPIO pins that are configured for input. The values read are
78332 +    returned through a \93GPIO_DATA\94 extension event.
78333 +
78334 +NOTE: Support for GPIO is optional.
78335 +
78336 +Command
78337 +    N/A
78338 +
78339 +Command Parameters
78340 +    None
78341 +
78342 +
78343 +
78344 +Reply Parameters
78345 +    None
78346 +
78347 +
78348 +Reset Value
78349 +    None
78350 +
78351 +
78352 +
78353 +Restrictions
78354 +    None
78355 +
78356 +=====================================================================
78357 +
78358 +
78359 +Name
78360 +    GPIO_INTR_ACK
78361 +
78362 +Synopsis
78363 +    The host uses this command to acknowledge and to re-arm GPIO interrupts reported
78364 +    through an earlier \93GPIO_INTR\94 extension event. A single \93GPIO_INTR_ACK\94
78365 +    command should be used to acknowledge all GPIO interrupts that the host knows to
78366 +    be outstanding (if pending interrupts are not acknowledged through
78367 +    \93GPIO_INTR_ACK\94, another \93GPIO_INTR\94 extension event is raised).
78368 +
78369 +NOTE: Support for GPIO is optional.
78370 +
78371 +Command
78372 +    N/A
78373 +
78374 +Command Parameters
78375 +    UINT32    ack_mask
78376 +        A mask of interrupting GPIO pins (e.g., ack_mask
78377 +        bit [3] acknowledges an interrupt from the pin GPIO3).
78378 +
78379 +Command Values
78380 +    None
78381 +
78382 +Reset Value
78383 +    None
78384 +
78385 +Restrictions
78386 +    The host should acknowledge only interrupts about which it was notified.
78387 +
78388 +
78389 +=====================================================================
78390 +
78391 +Name
78392 +    GPIO_OUTPUT_SET
78393 +
78394 +Synopsis
78395 +    Manages output on GPIO pins configured for output.
78396 +
78397 +    Conflicts between set_mask and clear_mask or enable_mask and disable_mask result
78398 +    in undefined behavior.
78399 +
78400 +NOTE: Support for GPIO is optional.
78401 +
78402 +Command
78403 +    N/A
78404 +
78405 +Command Parameters
78406 +    UINT32    set_mask
78407 +        Specifies which pins should drive a 1 out
78408 +    UINT32    clear_mask
78409 +        Specifies which pins should drive a 0 out
78410 +    UINT32    enable_mask
78411 +        Specifies which pins should be enabled for output
78412 +    UINT32    disable_mask
78413 +        Specifies which pins should be disabled for output
78414 +
78415 +Command Values
78416 +    None
78417 +
78418 +
78419 +Reset Value
78420 +    None
78421 +
78422 +
78423 +Restrictions
78424 +    None
78425 +
78426 +
78427 +
78428 +=====================================================================
78429 +
78430 +
78431 +Name
78432 +    GPIO_REGISTER_GET
78433 +
78434 +Synopsis
78435 +    Allows the host to read an arbitrary GPIO register. It is intended for use during
78436 +    bringup/debug. The target responds to this command with a \93GPIO_DATA\94 event.
78437 +
78438 +NOTE: Support for GPIO is optional.
78439 +
78440 +Command
78441 +    N/A
78442 +
78443 +Command Parameters
78444 +    UINT32
78445 +    gpioreg_id
78446 +    Specifies a GPIO register identifier, as defined
78447 +in include/AR6000/AR6000_gpio.h
78448 +
78449 +Reply Parameters
78450 +    None
78451 +
78452 +Reset Value
78453 +    N/A
78454 +
78455 +Restrictions
78456 +    None
78457 +
78458 +
78459 +=====================================================================
78460 +
78461 +Name
78462 +    GPIO_REGISTER_SET
78463 +
78464 +Synopsis
78465 +    Allows the host to dynamically change GPIO configuration (usually handled
78466 +    statically through the GPIO configuration DataSet).
78467 +
78468 +NOTE: Support for GPIO is optional.
78469 +
78470 +Command
78471 +    N/A
78472 +
78473 +Command Parameters
78474 +    UINT32    gpioreg_id
78475 +        Specifies a GPIO register identifier, as defined in
78476 +        include/AR6000/AR6000_gpio.h
78477 +    UINT32    value
78478 +        Specifies a value to write to the specified
78479 +        GPIO register
78480 +
78481 +Command Values
78482 +    None
78483 +
78484 +
78485 +Reset Value
78486 +    Initial hardware configuration is as defined in the AR6001 or AR6002 ROCmTM
78487 +    Single-Chip MAC/BB/Radio for 2.4/5 GHz Embedded WLAN Applications data sheet. This
78488 +    configuration is modified by the GPIO Configuration DataSet, if one exists.
78489 +
78490 +Restrictions
78491 +    None
78492 +
78493 +
78494 +=====================================================================
78495 +
78496 +
78497 +Name
78498 +    SET_LQTHRESHOLD
78499 +
78500 +Synopsis
78501 +    Set link quality thresholds, the sampling happens at every unicast data frame Tx, if
78502 +    certain threshold is met, corresponding event will be sent to host.
78503 +
78504 +Command
78505 +    wmiconfig eth1 --lqThreshold <enable> <upper_threshold_1>...
78506 +    <upper_threshold_4> <lower_threshold_1>... <lower_threshold_4>
78507 +
78508 +Command Parameters
78509 +    A_UINT8   enable;
78510 +    A_UINT8   thresholdAbove1_Val;
78511 +    A_UINT8   thresholdAbove2_Val;
78512 +    A_UINT8   thresholdAbove3_Val;
78513 +    A_UINT8   thresholdAbove4_Val;
78514 +    A_UINT8   thresholdBelow1_Val;
78515 +    A_UINT8   thresholdBelow2_Val;
78516 +    A_UINT8   thresholdBelow3_Val;
78517 +    A_UINT8   thresholdBelow4_Val;
78518 +
78519 +Command Values
78520 +    enable
78521 +    = 0
78522 +    Disable link quality sampling
78523 +
78524 +        = 1
78525 +    Enable link quality sampling
78526 +
78527 +
78528 +    thresholdAbove_Val
78529 +    [1...4]
78530 +    Above thresholds (value in [0,100]), in ascending
78531 +    order threshold
78532 +
78533 +    Below_Val [1...4] = below thresholds (value
78534 +    in [0,100]), in ascending order
78535 +
78536 +Reset Values
78537 +    None
78538 +
78539 +Restrictions
78540 +    None
78541 +
78542 +=====================================================================
78543 +WMI Extension Events
78544 +
78545 +The WMI EXTENSION event is used for a collection of events that:
78546 +
78547 +    Are not generic wireless events
78548 +    May be implementation-specific
78549 +    May be target platform-specific
78550 +    May be optional for a host implementation
78551 +
78552 +    An extension event is sent from the AR6000 device targets to the host just like
78553 +any other WMI event message, using the WMI_EXTENSION_EVENTID. The
78554 +first field of the payload for this \93EXTENSION\94 event is another commandId
78555 +(sometimes called the subcommandId) that indicates which \93EXTENSION\94
78556 +event is being used. A subcommandId-specific payload follows the
78557 +subcommandId.
78558 +
78559 +All extensions (subcommandIds) are listed in the header file include/wmix.h.
78560 +See also \93WMI Extension Commands\94 on page B-55.
78561 +
78562 +
78563 +WMI Extension Events
78564 +
78565 +
78566 +GPIO_ACK
78567 +    Acknowledges a host set command has been processed by the device
78568 +
78569 +GPIO_DATA
78570 +    Response to a host\92s request for data
78571 +
78572 +GPIO_INTR
78573 +    Signals that GPIO interrupts are pending
78574 +
78575 +
78576 +=====================================================================
78577 +
78578 +Name
78579 +    GPIO_ACK
78580 +
78581 +Synopsis
78582 +    Acknowledges that a host set command (either \93GPIO_OUTPUT_SET\94 or
78583 +    \93GPIO_REGISTER_SET\94) has been processed by the AR6000 device.
78584 +
78585 +NOTE: Support for GPIO is optional.
78586 +
78587 +Event ID
78588 +    N/A
78589 +
78590 +Event Parameters
78591 +    None
78592 +
78593 +
78594 +Event Values
78595 +    None
78596 +
78597 +=====================================================================
78598 +
78599 +
78600 +Name
78601 +    GPIO_DATA
78602 +
78603 +Synopsis
78604 +    The AR6000 device uses this event to respond to the host\92s earlier request for data
78605 +    (through either a \93GPIO_REGISTER_GET\94 or a \93GPIO_INPUT_GET\94 command).
78606 +
78607 +NOTE: Support for GPIO is optional.
78608 +
78609 +Event ID
78610 +    N/A
78611 +
78612 +Event Parameters
78613 +    UINT32    value
78614 +        Holds the data of interest, which is either a register value
78615 +        (in the case of \93GPIO_REGISTER_GET\94) or a mask of
78616 +        pin inputs (in the case of \93GPIO_INPUT_GET\94).
78617 +    UINT32    reg_id
78618 +        Indicates which register was read (in the case of
78619 +        \93GPIO_REGISTER_GET\94) or is GPIO_ID_NONE (in the
78620 +        case of \93GPIO_INPUT_GET\94)
78621 +
78622 +Event Values
78623 +    None
78624 +
78625 +
78626 +=====================================================================
78627 +
78628 +
78629 +
78630 +Name
78631 +    GPIO_INTR
78632 +
78633 +Synopsis
78634 +    The AR6000 device raises this event to signal that GPIO interrupts are pending.
78635 +    These GPIOs may be interrupts that occurred after the last \93GPIO_INTR_ACK\94
78636 +    command was issued, or may be GPIO interrupts that the host failed to acknowledge
78637 +    in the last \93GPIO_INTR_ACK\94. The AR6000 will not raise another GPIO_INTR
78638 +    event until this event is acknowledged through a \93GPIO_INTR_ACK\94 command.
78639 +
78640 +NOTE: Support for GPIO is optional.
78641 +
78642 +Event ID
78643 +    N/A
78644 +
78645 +Event Parameters
78646 +    UINT32    intr_mask
78647 +        Indicates which GPIO interrupts are currently pending
78648 +
78649 +    UINT32    input_values
78650 +        A recent copy of the GPIO input values, taken at the
78651 +        time the most recent GPIO interrupt was processed
78652 +
78653 +Event Values
78654 +    None
78655 +
78656 +
78657 +
78658 +=====================================================================
78659 +#endif
78660 --- /dev/null
78661 +++ b/drivers/ar6000/wmi/wmi_host.h
78662 @@ -0,0 +1,71 @@
78663 +#ifndef _WMI_HOST_H_
78664 +#define _WMI_HOST_H_
78665 +/*
78666 + * Copyright (c) 2004-2006 Atheros Communications Inc.
78667 + * All rights reserved.
78668 + *
78669 + * This file contains local definitios for the wmi host module.
78670 + *
78671 + * $Id: //depot/sw/releases/olca2.0-GPL/host/wmi/wmi_host.h#1 $
78672 + *
78673 + *
78674 + *  This program is free software; you can redistribute it and/or modify
78675 + *  it under the terms of the GNU General Public License version 2 as
78676 + *  published by the Free Software Foundation;
78677 + *
78678 + *  Software distributed under the License is distributed on an "AS
78679 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
78680 + *  implied. See the License for the specific language governing
78681 + *  rights and limitations under the License.
78682 + *
78683 + *
78684 + *
78685 + */
78686 +
78687 +#ifdef __cplusplus
78688 +extern "C" {
78689 +#endif
78690 +
78691 +struct wmi_stats {
78692 +    A_UINT32    cmd_len_err;
78693 +    A_UINT32    cmd_id_err;
78694 +};
78695 +
78696 +struct wmi_t {
78697 +    A_BOOL                          wmi_ready;
78698 +    A_BOOL                          wmi_numQoSStream;
78699 +    A_UINT8                         wmi_wmiStream2AcMapping[WMI_PRI_MAX_COUNT];
78700 +    WMI_PRI_STREAM_ID               wmi_ac2WmiStreamMapping[WMM_NUM_AC];
78701 +    A_UINT16                        wmi_streamExistsForAC[WMM_NUM_AC];
78702 +    A_UINT8                         wmi_fatPipeExists;
78703 +    void                           *wmi_devt;
78704 +    struct wmi_stats                wmi_stats;
78705 +    struct ieee80211_node_table     wmi_scan_table;
78706 +    A_UINT8                         wmi_bssid[ATH_MAC_LEN];
78707 +    A_UINT8                         wmi_powerMode;
78708 +    A_UINT8                         wmi_phyMode;
78709 +    A_UINT8                         wmi_keepaliveInterval;
78710 +    A_MUTEX_T                       wmi_lock;
78711 +};
78712 +
78713 +#define WMI_INIT_WMISTREAM_AC_MAP(w) \
78714 +{  (w)->wmi_wmiStream2AcMapping[WMI_BEST_EFFORT_PRI] = WMM_AC_BE; \
78715 +   (w)->wmi_wmiStream2AcMapping[WMI_LOW_PRI] = WMM_AC_BK; \
78716 +   (w)->wmi_wmiStream2AcMapping[WMI_HIGH_PRI] = WMM_AC_VI; \
78717 +   (w)->wmi_wmiStream2AcMapping[WMI_HIGHEST_PRI] = WMM_AC_VO; \
78718 +   (w)->wmi_ac2WmiStreamMapping[WMM_AC_BE] = WMI_BEST_EFFORT_PRI; \
78719 +   (w)->wmi_ac2WmiStreamMapping[WMM_AC_BK] = WMI_LOW_PRI; \
78720 +   (w)->wmi_ac2WmiStreamMapping[WMM_AC_VI] = WMI_HIGH_PRI; \
78721 +   (w)->wmi_ac2WmiStreamMapping[WMM_AC_VO] = WMI_HIGHEST_PRI; }
78722 +
78723 +#define WMI_WMISTREAM_ACCESSCATEGORY(w,s)      (w)->wmi_wmiStream2AcMapping[s]
78724 +#define WMI_ACCESSCATEGORY_WMISTREAM(w,ac)       (w)->wmi_ac2WmiStreamMapping[ac]
78725 +
78726 +#define LOCK_WMI(w)     A_MUTEX_LOCK(&(w)->wmi_lock);
78727 +#define UNLOCK_WMI(w)   A_MUTEX_UNLOCK(&(w)->wmi_lock);
78728 +
78729 +#ifdef __cplusplus
78730 +}
78731 +#endif
78732 +
78733 +#endif /* _WMI_HOST_H_ */
78734 --- a/drivers/base/bus.c
78735 +++ b/drivers/base/bus.c
78736 @@ -141,6 +141,29 @@ void bus_remove_file(struct bus_type *bu
78737  }
78738  EXPORT_SYMBOL_GPL(bus_remove_file);
78739
78740 +int bus_create_device_link(struct bus_type *bus, struct kobject *target,
78741 +                          const char *name)
78742 +{
78743 +       int error;
78744 +       if (bus_get(bus)) {
78745 +               error = sysfs_create_link(&bus->p->devices_kset->kobj, target,
78746 +                                         name);
78747 +               bus_put(bus);
78748 +       } else
78749 +               error = -EINVAL;
78750 +       return error;
78751 +}
78752 +EXPORT_SYMBOL_GPL(bus_create_device_link);
78753 +
78754 +void bus_remove_device_link(struct bus_type *bus, const char *name)
78755 +{
78756 +       if (bus_get(bus)) {
78757 +               sysfs_remove_link(&bus->p->devices_kset->kobj, name);
78758 +               bus_put(bus);
78759 +       }
78760 +}
78761 +EXPORT_SYMBOL_GPL(bus_remove_device_link);
78762 +
78763  static struct kobj_type bus_ktype = {
78764         .sysfs_ops      = &bus_sysfs_ops,
78765  };
78766 --- a/drivers/base/core.c
78767 +++ b/drivers/base/core.c
78768 @@ -55,6 +55,11 @@ static inline int device_is_not_partitio
78769   */
78770  const char *dev_driver_string(const struct device *dev)
78771  {
78772 +       if (!dev) {
78773 +               printk(KERN_ERR"Null dev to dev_driver_string\n");
78774 +               dump_stack();
78775 +               return "*NULL*";
78776 +       }
78777         return dev->driver ? dev->driver->name :
78778                         (dev->bus ? dev->bus->name :
78779                         (dev->class ? dev->class->name : ""));
78780 --- a/drivers/base/power/main.c
78781 +++ b/drivers/base/power/main.c
78782 @@ -69,9 +69,9 @@ void device_pm_unlock(void)
78783   */
78784  void device_pm_add(struct device *dev)
78785  {
78786 -       pr_debug("PM: Adding info for %s:%s\n",
78787 +       /* pr_debug("PM: Adding info for %s:%s\n",
78788                  dev->bus ? dev->bus->name : "No Bus",
78789 -                kobject_name(&dev->kobj));
78790 +                kobject_name(&dev->kobj)); */
78791         mutex_lock(&dpm_list_mtx);
78792         if (dev->parent) {
78793                 if (dev->parent->power.status >= DPM_SUSPENDING)
78794 --- a/drivers/char/Kconfig
78795 +++ b/drivers/char/Kconfig
78796 @@ -66,6 +66,18 @@ config VT_CONSOLE
78797
78798           If unsure, say Y.
78799
78800 +config NR_TTY_DEVICES
78801 +       int "Maximum tty device number"
78802 +       depends on VT
78803 +       default 63
78804 +       ---help---
78805 +         This is the highest numbered device created in /dev. You will actually have
78806 +         NR_TTY_DEVICES+1 devices in /dev. The default is 63, which will result in
78807 +         64 /dev entries. The lowest number you can set is 11, anything below that,
78808 +         and it will default to 11. 63 is also the upper limit so we don't overrun
78809 +         the serial consoles.
78810 +
78811 +
78812  config HW_CONSOLE
78813         bool
78814         depends on VT && !S390 && !UML
78815 --- a/drivers/gpio/gpiolib.c
78816 +++ b/drivers/gpio/gpiolib.c
78817 @@ -6,8 +6,7 @@
78818  #include <linux/err.h>
78819  #include <linux/debugfs.h>
78820  #include <linux/seq_file.h>
78821 -#include <linux/gpio.h>
78822 -
78823 +#include <mach/gpio.h>
78824
78825  /* Optional implementation infrastructure for GPIO interfaces.
78826   *
78827 --- a/drivers/i2c/busses/i2c-s3c2410.c
78828 +++ b/drivers/i2c/busses/i2c-s3c2410.c
78829 @@ -34,14 +34,12 @@
78830  #include <linux/platform_device.h>
78831  #include <linux/clk.h>
78832  #include <linux/cpufreq.h>
78833 +#include <linux/io.h>
78834
78835 -#include <mach/hardware.h>
78836  #include <asm/irq.h>
78837 -#include <asm/io.h>
78838
78839 -#include <mach/regs-gpio.h>
78840 -#include <asm/plat-s3c/regs-iic.h>
78841 -#include <asm/plat-s3c/iic.h>
78842 +#include <plat/regs-iic.h>
78843 +#include <plat/iic.h>
78844
78845  /* i2c controller state */
78846
78847 @@ -64,6 +62,7 @@ struct s3c24xx_i2c {
78848         unsigned int            msg_ptr;
78849
78850         unsigned int            tx_setup;
78851 +       unsigned int            irq;
78852
78853         enum s3c24xx_i2c_state  state;
78854         unsigned long           clkrate;
78855 @@ -71,7 +70,6 @@ struct s3c24xx_i2c {
78856         void __iomem            *regs;
78857         struct clk              *clk;
78858         struct device           *dev;
78859 -       struct resource         *irq;
78860         struct resource         *ioarea;
78861         struct i2c_adapter      adap;
78862
78863 @@ -80,16 +78,7 @@ struct s3c24xx_i2c {
78864  #endif
78865  };
78866
78867 -/* default platform data to use if not supplied in the platform_device
78868 -*/
78869 -
78870 -static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
78871 -       .flags          = 0,
78872 -       .slave_addr     = 0x10,
78873 -       .bus_freq       = 100*1000,
78874 -       .max_freq       = 400*1000,
78875 -       .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
78876 -};
78877 +/* default platform data removed, dev should always carry data. */
78878
78879  /* s3c24xx_i2c_is2440()
78880   *
78881 @@ -103,21 +92,6 @@ static inline int s3c24xx_i2c_is2440(str
78882         return !strcmp(pdev->name, "s3c2440-i2c");
78883  }
78884
78885 -
78886 -/* s3c24xx_i2c_get_platformdata
78887 - *
78888 - * get the platform data associated with the given device, or return
78889 - * the default if there is none
78890 -*/
78891 -
78892 -static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
78893 -{
78894 -       if (dev->platform_data != NULL)
78895 -               return (struct s3c2410_platform_i2c *)dev->platform_data;
78896 -
78897 -       return &s3c24xx_i2c_default_platform;
78898 -}
78899 -
78900  /* s3c24xx_i2c_master_complete
78901   *
78902   * complete the message and wake up the caller, using the given return code,
78903 @@ -130,7 +104,7 @@ static inline void s3c24xx_i2c_master_co
78904
78905         i2c->msg_ptr = 0;
78906         i2c->msg = NULL;
78907 -       i2c->msg_idx ++;
78908 +       i2c->msg_idx++;
78909         i2c->msg_num = 0;
78910         if (ret)
78911                 i2c->msg_idx = ret;
78912 @@ -141,19 +115,17 @@ static inline void s3c24xx_i2c_master_co
78913  static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
78914  {
78915         unsigned long tmp;
78916 -
78917 +
78918         tmp = readl(i2c->regs + S3C2410_IICCON);
78919         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
78920 -
78921  }
78922
78923  static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
78924  {
78925         unsigned long tmp;
78926 -
78927 +
78928         tmp = readl(i2c->regs + S3C2410_IICCON);
78929         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
78930 -
78931  }
78932
78933  /* irq enable/disable functions */
78934 @@ -161,15 +133,23 @@ static inline void s3c24xx_i2c_enable_ac
78935  static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
78936  {
78937         unsigned long tmp;
78938 -
78939 +
78940         tmp = readl(i2c->regs + S3C2410_IICCON);
78941 +
78942 +/* S3c2442 datasheet
78943 + *
78944 + * If the IICCON[5]=0, IICCON[4] does not operate correctly.
78945 + * So, It is recommended that you should set IICCON[5]=1,
78946 + * although you does not use the IIC interrupt.
78947 + */
78948 +
78949         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
78950  }
78951
78952  static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
78953  {
78954         unsigned long tmp;
78955 -
78956 +
78957         tmp = readl(i2c->regs + S3C2410_IICCON);
78958         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
78959  }
78960 @@ -177,10 +157,10 @@ static inline void s3c24xx_i2c_enable_ir
78961
78962  /* s3c24xx_i2c_message_start
78963   *
78964 - * put the start of a message onto the bus
78965 + * put the start of a message onto the bus
78966  */
78967
78968 -static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
78969 +static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
78970                                       struct i2c_msg *msg)
78971  {
78972         unsigned int addr = (msg->addr & 0x7f) << 1;
78973 @@ -199,15 +179,15 @@ static void s3c24xx_i2c_message_start(st
78974         if (msg->flags & I2C_M_REV_DIR_ADDR)
78975                 addr ^= 1;
78976
78977 -       // todo - check for wether ack wanted or not
78978 +       /* todo - check for wether ack wanted or not */
78979         s3c24xx_i2c_enable_ack(i2c);
78980
78981         iiccon = readl(i2c->regs + S3C2410_IICCON);
78982         writel(stat, i2c->regs + S3C2410_IICSTAT);
78983 -
78984 +
78985         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
78986         writeb(addr, i2c->regs + S3C2410_IICDS);
78987 -
78988 +
78989         /* delay here to ensure the data byte has gotten onto the bus
78990          * before the transaction is started */
78991
78992 @@ -215,8 +195,8 @@ static void s3c24xx_i2c_message_start(st
78993
78994         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
78995         writel(iiccon, i2c->regs + S3C2410_IICCON);
78996 -
78997 -       stat |=  S3C2410_IICSTAT_START;
78998 +
78999 +       stat |= S3C2410_IICSTAT_START;
79000         writel(stat, i2c->regs + S3C2410_IICSTAT);
79001  }
79002
79003 @@ -227,11 +207,11 @@ static inline void s3c24xx_i2c_stop(stru
79004         dev_dbg(i2c->dev, "STOP\n");
79005
79006         /* stop the transfer */
79007 -       iicstat &= ~ S3C2410_IICSTAT_START;
79008 +       iicstat &= ~S3C2410_IICSTAT_START;
79009         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
79010 -
79011 +
79012         i2c->state = STATE_STOP;
79013 -
79014 +
79015         s3c24xx_i2c_master_complete(i2c, ret);
79016         s3c24xx_i2c_disable_irq(i2c);
79017  }
79018 @@ -241,7 +221,7 @@ static inline void s3c24xx_i2c_stop(stru
79019
79020  /* is_lastmsg()
79021   *
79022 - * returns TRUE if the current message is the last in the set
79023 + * returns TRUE if the current message is the last in the set
79024  */
79025
79026  static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
79027 @@ -289,14 +269,14 @@ static int i2s_s3c_irq_nextbyte(struct s
79028
79029         case STATE_STOP:
79030                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
79031 -               s3c24xx_i2c_disable_irq(i2c);
79032 +               s3c24xx_i2c_disable_irq(i2c);
79033                 goto out_ack;
79034
79035         case STATE_START:
79036                 /* last thing we did was send a start condition on the
79037                  * bus, or started a new i2c message
79038                  */
79039 -
79040 +
79041                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
79042                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
79043                         /* ack was not received... */
79044 @@ -322,7 +302,7 @@ static int i2s_s3c_irq_nextbyte(struct s
79045                 if (i2c->state == STATE_READ)
79046                         goto prepare_read;
79047
79048 -               /* fall through to the write state, as we will need to
79049 +               /* fall through to the write state, as we will need to
79050                  * send a byte as well */
79051
79052         case STATE_WRITE:
79053 @@ -339,7 +319,7 @@ static int i2s_s3c_irq_nextbyte(struct s
79054                         }
79055                 }
79056
79057 -       retry_write:
79058 + retry_write:
79059
79060                 if (!is_msgend(i2c)) {
79061                         byte = i2c->msg->buf[i2c->msg_ptr++];
79062 @@ -359,9 +339,9 @@ static int i2s_s3c_irq_nextbyte(struct s
79063                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
79064
79065                         i2c->msg_ptr = 0;
79066 -                       i2c->msg_idx ++;
79067 +                       i2c->msg_idx++;
79068                         i2c->msg++;
79069 -
79070 +
79071                         /* check to see if we need to do another message */
79072                         if (i2c->msg->flags & I2C_M_NOSTART) {
79073
79074 @@ -375,7 +355,6 @@ static int i2s_s3c_irq_nextbyte(struct s
79075
79076                                 goto retry_write;
79077                         } else {
79078 -
79079                                 /* send the new start */
79080                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
79081                                 i2c->state = STATE_START;
79082 @@ -389,7 +368,7 @@ static int i2s_s3c_irq_nextbyte(struct s
79083                 break;
79084
79085         case STATE_READ:
79086 -               /* we have a byte of data in the data register, do
79087 +               /* we have a byte of data in the data register, do
79088                  * something with it, and then work out wether we are
79089                  * going to do any more read/write
79090                  */
79091 @@ -397,13 +376,13 @@ static int i2s_s3c_irq_nextbyte(struct s
79092                 byte = readb(i2c->regs + S3C2410_IICDS);
79093                 i2c->msg->buf[i2c->msg_ptr++] = byte;
79094
79095 -       prepare_read:
79096 + prepare_read:
79097                 if (is_msglast(i2c)) {
79098                         /* last byte of buffer */
79099
79100                         if (is_lastmsg(i2c))
79101                                 s3c24xx_i2c_disable_ack(i2c);
79102 -
79103 +
79104                 } else if (is_msgend(i2c)) {
79105                         /* ok, we've read the entire buffer, see if there
79106                          * is anything else we need to do */
79107 @@ -429,7 +408,7 @@ static int i2s_s3c_irq_nextbyte(struct s
79108         /* acknowlegde the IRQ and get back on with the work */
79109
79110   out_ack:
79111 -       tmp = readl(i2c->regs + S3C2410_IICCON);
79112 +       tmp = readl(i2c->regs + S3C2410_IICCON);
79113         tmp &= ~S3C2410_IICCON_IRQPEND;
79114         writel(tmp, i2c->regs + S3C2410_IICCON);
79115   out:
79116 @@ -450,19 +429,19 @@ static irqreturn_t s3c24xx_i2c_irq(int i
79117         status = readl(i2c->regs + S3C2410_IICSTAT);
79118
79119         if (status & S3C2410_IICSTAT_ARBITR) {
79120 -               // deal with arbitration loss
79121 +               /* deal with arbitration loss */
79122                 dev_err(i2c->dev, "deal with arbitration loss\n");
79123         }
79124
79125         if (i2c->state == STATE_IDLE) {
79126                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
79127
79128 -               tmp = readl(i2c->regs + S3C2410_IICCON);
79129 +               tmp = readl(i2c->regs + S3C2410_IICCON);
79130                 tmp &= ~S3C2410_IICCON_IRQPEND;
79131                 writel(tmp, i2c->regs +  S3C2410_IICCON);
79132                 goto out;
79133         }
79134 -
79135 +
79136         /* pretty much this leaves us with the fact that we've
79137          * transmitted or received whatever byte we last sent */
79138
79139 @@ -485,16 +464,13 @@ static int s3c24xx_i2c_set_master(struct
79140
79141         while (timeout-- > 0) {
79142                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
79143 -
79144 +
79145                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
79146                         return 0;
79147
79148                 msleep(1);
79149         }
79150
79151 -       dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
79152 -               __raw_readl(S3C2410_GPEDAT));
79153 -
79154         return -ETIMEDOUT;
79155  }
79156
79157 @@ -503,7 +479,8 @@ static int s3c24xx_i2c_set_master(struct
79158   * this starts an i2c transfer
79159  */
79160
79161 -static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num)
79162 +static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
79163 +                             struct i2c_msg *msgs, int num)
79164  {
79165         unsigned long timeout;
79166         int ret;
79167 @@ -511,6 +488,15 @@ static int s3c24xx_i2c_doxfer(struct s3c
79168         if (i2c->suspended)
79169                 return -EIO;
79170
79171 +       if (i2c->suspended) {
79172 +               dev_err(i2c->dev,
79173 +                   "Hey I am still asleep (suspended: %d), retry later\n",
79174 +                   i2c->suspended);
79175 +               dump_stack();
79176 +               ret = -EAGAIN;
79177 +               goto out;
79178 +       }
79179 +
79180         ret = s3c24xx_i2c_set_master(i2c);
79181         if (ret != 0) {
79182                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
79183 @@ -529,12 +515,12 @@ static int s3c24xx_i2c_doxfer(struct s3c
79184         s3c24xx_i2c_enable_irq(i2c);
79185         s3c24xx_i2c_message_start(i2c, msgs);
79186         spin_unlock_irq(&i2c->lock);
79187 -
79188 +
79189         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
79190
79191         ret = i2c->msg_idx;
79192
79193 -       /* having these next two as dev_err() makes life very
79194 +       /* having these next two as dev_err() makes life very
79195          * noisy when doing an i2cdetect */
79196
79197         if (timeout == 0)
79198 @@ -591,19 +577,6 @@ static const struct i2c_algorithm s3c24x
79199         .functionality          = s3c24xx_i2c_func,
79200  };
79201
79202 -static struct s3c24xx_i2c s3c24xx_i2c = {
79203 -       .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
79204 -       .wait           = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
79205 -       .tx_setup       = 50,
79206 -       .adap           = {
79207 -               .name                   = "s3c2410-i2c",
79208 -               .owner                  = THIS_MODULE,
79209 -               .algo                   = &s3c24xx_i2c_algorithm,
79210 -               .retries                = 2,
79211 -               .class                  = I2C_CLASS_HWMON | I2C_CLASS_SPD,
79212 -       },
79213 -};
79214 -
79215  /* s3c24xx_i2c_calcdivisor
79216   *
79217   * return the divisor settings for a given frequency
79218 @@ -643,7 +616,7 @@ static inline int freq_acceptable(unsign
79219  {
79220         int diff = freq - wanted;
79221
79222 -       return (diff >= -2 && diff <= 2);
79223 +       return diff >= -2 && diff <= 2;
79224  }
79225
79226  /* s3c24xx_i2c_clockrate
79227 @@ -655,7 +628,7 @@ static inline int freq_acceptable(unsign
79228
79229  static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
79230  {
79231 -       struct s3c2410_platform_i2c *pdata;
79232 +       struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
79233         unsigned long clkin = clk_get_rate(i2c->clk);
79234         unsigned int divs, div1;
79235         u32 iiccon;
79236 @@ -663,10 +636,8 @@ static int s3c24xx_i2c_clockrate(struct
79237         int start, end;
79238
79239         i2c->clkrate = clkin;
79240 -
79241 -       pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
79242         clkin /= 1000;          /* clkin now in KHz */
79243 -
79244 +
79245         dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
79246                  pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
79247
79248 @@ -774,7 +745,7 @@ static inline void s3c24xx_i2c_deregiste
79249
79250  /* s3c24xx_i2c_init
79251   *
79252 - * initialise the controller, set the IO lines and frequency
79253 + * initialise the controller, set the IO lines and frequency
79254  */
79255
79256  static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
79257 @@ -785,15 +756,15 @@ static int s3c24xx_i2c_init(struct s3c24
79258
79259         /* get the plafrom data */
79260
79261 -       pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
79262 +       pdata = i2c->dev->platform_data;
79263
79264         /* inititalise the gpio */
79265
79266 -       s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
79267 -       s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
79268 +       if (pdata->cfg_gpio)
79269 +               pdata->cfg_gpio(to_platform_device(i2c->dev));
79270
79271         /* write slave address */
79272 -
79273 +
79274         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
79275
79276         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
79277 @@ -831,12 +802,32 @@ static int s3c24xx_i2c_init(struct s3c24
79278
79279  static int s3c24xx_i2c_probe(struct platform_device *pdev)
79280  {
79281 -       struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
79282 +       struct s3c24xx_i2c *i2c;
79283         struct s3c2410_platform_i2c *pdata;
79284         struct resource *res;
79285         int ret;
79286
79287 -       pdata = s3c24xx_i2c_get_platformdata(&pdev->dev);
79288 +       pdata = pdev->dev.platform_data;
79289 +       if (!pdata) {
79290 +               dev_err(&pdev->dev, "no platform data\n");
79291 +               return -EINVAL;
79292 +       }
79293 +
79294 +       i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
79295 +       if (!i2c) {
79296 +               dev_err(&pdev->dev, "no memory for state\n");
79297 +               return -ENOMEM;
79298 +       }
79299 +
79300 +       strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
79301 +       i2c->adap.owner   = THIS_MODULE;
79302 +       i2c->adap.algo    = &s3c24xx_i2c_algorithm;
79303 +       i2c->adap.retries = 2;
79304 +       i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
79305 +       i2c->tx_setup     = 50;
79306 +
79307 +       spin_lock_init(&i2c->lock);
79308 +       init_waitqueue_head(&i2c->wait);
79309
79310         /* find the clock and enable it */
79311
79312 @@ -878,7 +869,8 @@ static int s3c24xx_i2c_probe(struct plat
79313                 goto err_ioarea;
79314         }
79315
79316 -       dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
79317 +       dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
79318 +               i2c->regs, i2c->ioarea, res);
79319
79320         /* setup info block for the i2c core */
79321
79322 @@ -892,29 +884,23 @@ static int s3c24xx_i2c_probe(struct plat
79323                 goto err_iomap;
79324
79325         /* find the IRQ for this unit (note, this relies on the init call to
79326 -        * ensure no current IRQs pending
79327 +        * ensure no current IRQs pending
79328          */
79329
79330 -       res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
79331 -       if (res == NULL) {
79332 +       i2c->irq = ret = platform_get_irq(pdev, 0);
79333 +       if (ret <= 0) {
79334                 dev_err(&pdev->dev, "cannot find IRQ\n");
79335 -               ret = -ENOENT;
79336                 goto err_iomap;
79337         }
79338
79339 -       ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
79340 -                         pdev->name, i2c);
79341 +       ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
79342 +                         dev_name(&pdev->dev), i2c);
79343
79344         if (ret != 0) {
79345 -               dev_err(&pdev->dev, "cannot claim IRQ\n");
79346 +               dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
79347                 goto err_iomap;
79348         }
79349
79350 -       i2c->irq = res;
79351 -
79352 -       dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
79353 -               (unsigned long)res->start);
79354 -
79355         ret = s3c24xx_i2c_register_cpufreq(i2c);
79356         if (ret < 0) {
79357                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
79358 @@ -944,7 +930,7 @@ static int s3c24xx_i2c_probe(struct plat
79359         s3c24xx_i2c_deregister_cpufreq(i2c);
79360
79361   err_irq:
79362 -       free_irq(i2c->irq->start, i2c);
79363 +       free_irq(i2c->irq, i2c);
79364
79365   err_iomap:
79366         iounmap(i2c->regs);
79367 @@ -958,6 +944,7 @@ static int s3c24xx_i2c_probe(struct plat
79368         clk_put(i2c->clk);
79369
79370   err_noclk:
79371 +       kfree(i2c);
79372         return ret;
79373  }
79374
79375 @@ -973,7 +960,7 @@ static int s3c24xx_i2c_remove(struct pla
79376         s3c24xx_i2c_deregister_cpufreq(i2c);
79377
79378         i2c_del_adapter(&i2c->adap);
79379 -       free_irq(i2c->irq->start, i2c);
79380 +       free_irq(i2c->irq, i2c);
79381
79382         clk_disable(i2c->clk);
79383         clk_put(i2c->clk);
79384 @@ -982,6 +969,7 @@ static int s3c24xx_i2c_remove(struct pla
79385
79386         release_resource(i2c->ioarea);
79387         kfree(i2c->ioarea);
79388 +       kfree(i2c);
79389
79390         return 0;
79391  }
79392 --- a/drivers/i2c/busses/Kconfig
79393 +++ b/drivers/i2c/busses/Kconfig
79394 @@ -455,11 +455,12 @@ config I2C_PXA_SLAVE
79395           I2C bus.
79396
79397  config I2C_S3C2410
79398 -       tristate "S3C2410 I2C Driver"
79399 -       depends on ARCH_S3C2410
79400 +       tristate "Samsung SoC I2C Driver (S3C24XX and S3C64XX series)"
79401 +       depends on ARCH_S3C2410 || ARCH_S3C64XX
79402         help
79403           Say Y here to include support for I2C controller in the
79404 -         Samsung S3C2410 based System-on-Chip devices.
79405 +         Samsung S3C based System-on-Chip devices such as the S3C2410,
79406 +         S3C2440, S3C2442, S3C2443 and S3C6410.
79407
79408  config I2C_SH7760
79409         tristate "Renesas SH7760 I2C Controller"
79410 --- a/drivers/i2c/chips/Kconfig
79411 +++ b/drivers/i2c/chips/Kconfig
79412 @@ -53,6 +53,26 @@ config SENSORS_EEPROM
79413           This driver can also be built as a module.  If so, the module
79414           will be called eeprom.
79415
79416 +config SENSORS_PCF50606
79417 +       tristate "Philips/NXP PCF50606"
79418 +       depends on I2C
79419 +       help
79420 +         If you say yes here you get support for Philips/NXP PCF50606
79421 +         PMU (Power Management Unit) chips.
79422 +
79423 +         This driver can also be built as a module.  If so, the module
79424 +         will be called pcf50606.
79425 +
79426 +config SENSORS_PCF50633
79427 +       tristate "Philips PCF50633"
79428 +       depends on I2C
79429 +       help
79430 +         If you say yes here you get support for Philips PCF50633
79431 +         PMU (Power Management Unit) chips.
79432 +
79433 +         This driver can also be built as a module.  If so, the module
79434 +         will be called pcf50633.
79435 +
79436  config SENSORS_PCF8574
79437         tristate "Philips PCF8574 and PCF8574A (DEPRECATED)"
79438         depends on EXPERIMENTAL && GPIO_PCF857X = "n"
79439 @@ -185,4 +205,23 @@ config MCU_MPC8349EMITX
79440           also register MCU GPIOs with the generic GPIO API, so you'll able
79441           to use MCU pins as GPIOs.
79442
79443 +config SENSORS_TSL256X
79444 +       tristate "Texas TSL256X Ambient Light Sensor"
79445 +       depends on I2C
79446 +       help
79447 +         If you say yes here you get support for the Texas TSL256X
79448 +         ambient light sensor chip.
79449 +
79450 +         This driver can also be built as a module.  If so, the module
79451 +         will be called tsl256x.
79452 +
79453 +config PCA9632
79454 +       tristate "Philips/NXP PCA9632 low power LED driver"
79455 +       depends on I2C
79456 +       help
79457 +         If you say yes here you get support for the Philips/NXP PCA9632
79458 +         LED driver.
79459 +
79460 +         This driver can also be built as a module.  If so, the module
79461 +         will be called pca9632.
79462  endmenu
79463 --- a/drivers/i2c/chips/Makefile
79464 +++ b/drivers/i2c/chips/Makefile
79465 @@ -15,6 +15,8 @@ obj-$(CONFIG_AT24)            += at24.o
79466  obj-$(CONFIG_SENSORS_EEPROM)   += eeprom.o
79467  obj-$(CONFIG_SENSORS_MAX6875)  += max6875.o
79468  obj-$(CONFIG_SENSORS_PCA9539)  += pca9539.o
79469 +obj-$(CONFIG_SENSORS_PCF50606) += pcf50606.o
79470 +obj-$(CONFIG_SENSORS_PCF50633) += pcf50633.o
79471  obj-$(CONFIG_SENSORS_PCF8574)  += pcf8574.o
79472  obj-$(CONFIG_PCF8575)          += pcf8575.o
79473  obj-$(CONFIG_SENSORS_PCF8591)  += pcf8591.o
79474 @@ -23,6 +25,8 @@ obj-$(CONFIG_TPS65010)                += tps65010.o
79475  obj-$(CONFIG_MENELAUS)         += menelaus.o
79476  obj-$(CONFIG_SENSORS_TSL2550)  += tsl2550.o
79477  obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mpc8349emitx.o
79478 +obj-$(CONFIG_SENSORS_TSL256X)  += tsl256x.o
79479 +obj-$(CONFIG_PCA9632)          += pca9632.o
79480
79481  ifeq ($(CONFIG_I2C_DEBUG_CHIP),y)
79482  EXTRA_CFLAGS += -DDEBUG
79483 --- /dev/null
79484 +++ b/drivers/i2c/chips/pca9632.c
79485 @@ -0,0 +1,551 @@
79486 +/*
79487 + *  Philips/NXP PCA9632 low power LED driver.
79488 + *  Copyright (C) 2008 Matt Hsu <matt_hsu@openmoko.org>
79489 + *
79490 + *  low_level implementation are based on pcf50606 driver
79491 + *
79492 + *  This program is free software; you can redistribute it and/or modify
79493 + *  it under the terms of the GNU General Public License as published by
79494 + *  the Free Software Foundation; version 2 of the License.
79495 + *
79496 + *  TODO:
79497 + *  - attach ledclass??
79498 + *  - add platform data
79499 + *
79500 + */
79501 +
79502 +#include <linux/module.h>
79503 +#include <linux/init.h>
79504 +#include <linux/i2c.h>
79505 +#include <linux/platform_device.h>
79506 +
79507 +#include "pca9632.h"
79508 +
79509 +/* Addresses to scan */
79510 +static unsigned short normal_i2c[] = { 0x62, I2C_CLIENT_END };
79511 +
79512 +/* Insmod parameters */
79513 +I2C_CLIENT_INSMOD_1(pca9632);
79514 +
79515 +enum pca9632_pwr_state {
79516 +       PCA9632_NORMAL,
79517 +       PCA9632_SLEEP,
79518 +};
79519 +
79520 +enum pca9632_led_output {
79521 +       PCA9632_OFF,
79522 +       PCA9632_ON,
79523 +       PCA9632_CTRL_BY_PWM,
79524 +       PCA9632_CTRL_BY_PWM_GRPPWM,
79525 +};
79526 +
79527 +static const char *led_output_name[] = {
79528 +       [PCA9632_OFF]                   = "off",
79529 +       [PCA9632_ON]                    = "fully-on",
79530 +       [PCA9632_CTRL_BY_PWM]           = "ctrl-by-pwm",
79531 +       [PCA9632_CTRL_BY_PWM_GRPPWM]    = "ctrl-by-pwm-grppwm",
79532 +};
79533 +
79534 +struct pca9632_data {
79535 +       struct i2c_client client;
79536 +       struct mutex lock;
79537 +};
79538 +
79539 +static struct i2c_driver pca9632_driver;
79540 +static struct platform_device *pca9632_pdev;
79541 +
79542 +static int pca9632_attach_adapter(struct i2c_adapter *adapter);
79543 +static int pca9632_detach_client(struct i2c_client *client);
79544 +
79545 +static int __reg_write(struct pca9632_data *pca, u_int8_t reg, u_int8_t val)
79546 +{
79547 +       return i2c_smbus_write_byte_data(&pca->client, reg, val);
79548 +}
79549 +
79550 +static int reg_write(struct pca9632_data *pca, u_int8_t reg, u_int8_t val)
79551 +{
79552 +       int ret;
79553 +
79554 +       mutex_lock(&pca->lock);
79555 +       ret = __reg_write(pca, reg, val);
79556 +       mutex_unlock(&pca->lock);
79557 +
79558 +       return ret;
79559 +}
79560 +
79561 +static int32_t __reg_read(struct pca9632_data *pca, u_int8_t reg)
79562 +{
79563 +       int32_t ret;
79564 +
79565 +       ret = i2c_smbus_read_byte_data(&pca->client, reg);
79566 +
79567 +       return ret;
79568 +}
79569 +
79570 +static u_int8_t reg_read(struct pca9632_data *pca, u_int8_t reg)
79571 +{
79572 +       int32_t ret;
79573 +
79574 +       mutex_lock(&pca->lock);
79575 +       ret = __reg_read(pca, reg);
79576 +       mutex_unlock(&pca->lock);
79577 +
79578 +       return ret & 0xff;
79579 +}
79580 +
79581 +static int reg_set_bit_mask(struct pca9632_data *pca,
79582 +                           u_int8_t reg, u_int8_t mask, u_int8_t val)
79583 +{
79584 +       int ret;
79585 +       u_int8_t tmp;
79586 +
79587 +       val &= mask;
79588 +
79589 +       mutex_lock(&pca->lock);
79590 +
79591 +       tmp = __reg_read(pca, reg);
79592 +       tmp &= ~mask;
79593 +       tmp |= val;
79594 +       ret = __reg_write(pca, reg, tmp);
79595 +
79596 +       mutex_unlock(&pca->lock);
79597 +
79598 +       return ret;
79599 +}
79600 +
79601 +static inline int calc_dc(uint8_t idc)
79602 +{
79603 +       return (idc * 100) / 256;
79604 +}
79605 +
79606 +/*
79607 + * Software reset
79608 + */
79609 +static int software_rst(struct i2c_adapter *adapter)
79610 +{
79611 +       u8 buf[] = { 0xa5, 0x5a };
79612 +
79613 +       struct i2c_msg msg[] = {
79614 +               {
79615 +                       .addr = 0x3,
79616 +                       .flags = 0,
79617 +                       .buf = &buf,
79618 +                       .len = sizeof(buf)
79619 +               }
79620 +       };
79621 +
79622 +       return i2c_transfer(adapter, msg, 1);
79623 +}
79624 +
79625 +/*
79626 + * Group dmblnk control
79627 + */
79628 +static void config_group_dmblnk(struct pca9632_data *pca, int group_dmblnk_mode)
79629 +{
79630 +       reg_set_bit_mask(pca, PCA9632_REG_MODE2, 0x20,
79631 +                       group_dmblnk_mode << PCA9632_DMBLNK_SHIFT);
79632 +}
79633 +
79634 +static int get_group_dmblnk(struct pca9632_data *pca)
79635 +{
79636 +       return reg_read(pca, PCA9632_REG_MODE2) >> PCA9632_DMBLNK_SHIFT;
79637 +}
79638 +
79639 +static ssize_t show_group_dmblnk(struct device *dev, struct device_attribute
79640 +                                       *attr, char *buf)
79641 +{
79642 +       struct i2c_client *client = to_i2c_client(dev);
79643 +       struct pca9632_data *pca = i2c_get_clientdata(client);
79644 +
79645 +       if (get_group_dmblnk(pca))
79646 +               return sprintf(buf, "blinking\n");
79647 +       else
79648 +               return sprintf(buf, "dimming\n");
79649 +}
79650 +
79651 +static ssize_t set_group_dmblnk(struct device *dev, struct device_attribute
79652 +                                       *attr, const char *buf, size_t count)
79653 +{
79654 +       struct i2c_client *client = to_i2c_client(dev);
79655 +       struct pca9632_data *pca = i2c_get_clientdata(client);
79656 +       unsigned int mode = simple_strtoul(buf, NULL, 10);
79657 +
79658 +       if (mode)
79659 +               dev_info(&pca->client.dev, "blinking\n");
79660 +       else
79661 +               dev_info(&pca->client.dev, "dimming\n");
79662 +
79663 +       config_group_dmblnk(pca, mode);
79664 +
79665 +       return count;
79666 +}
79667 +
79668 +static DEVICE_ATTR(group_dmblnk, S_IRUGO | S_IWUSR, show_group_dmblnk,
79669 +                                                       set_group_dmblnk);
79670 +
79671 +static int reg_id_by_name(const char *name)
79672 +{
79673 +       int reg_id = -1;
79674 +
79675 +       if (!strncmp(name, "led0", 4))
79676 +               reg_id = PCA9632_REG_PWM0;
79677 +       else if (!strncmp(name, "led1", 4))
79678 +               reg_id = PCA9632_REG_PWM1;
79679 +       else if (!strncmp(name, "led2", 4))
79680 +               reg_id = PCA9632_REG_PWM2;
79681 +       else if (!strncmp(name, "led3", 4))
79682 +               reg_id = PCA9632_REG_PWM3;
79683 +
79684 +       return reg_id;
79685 +}
79686 +
79687 +static int get_led_output(struct pca9632_data *pca, int ldrx)
79688 +{
79689 +       u_int8_t led_state;
79690 +
79691 +       ldrx = ldrx - 2;
79692 +       led_state = reg_read(pca, PCA9632_REG_LEDOUT);
79693 +       led_state = (led_state >> (2 * ldrx)) & 0x03;
79694 +
79695 +       return led_state;
79696 +}
79697 +
79698 +static void config_led_output(struct pca9632_data *pca, int ldrx,
79699 +                                       enum pca9632_led_output led_output)
79700 +{
79701 +       u_int8_t mask;
79702 +       int tmp;
79703 +
79704 +       ldrx = ldrx - 2;
79705 +       mask = 0x03 << (2 * ldrx);
79706 +       tmp = reg_set_bit_mask(pca, PCA9632_REG_LEDOUT,
79707 +                                       mask, led_output << (2 * ldrx));
79708 +}
79709 +
79710 +/*
79711 + * Individual brightness control
79712 + */
79713 +static ssize_t show_brightness(struct device *dev, struct device_attribute
79714 +                                       *attr, char *buf)
79715 +{
79716 +       struct i2c_client *client = to_i2c_client(dev);
79717 +       struct pca9632_data *pca = i2c_get_clientdata(client);
79718 +       int ldrx;
79719 +
79720 +       ldrx = reg_id_by_name(attr->attr.name);
79721 +
79722 +       switch (get_led_output(pca, ldrx)) {
79723 +
79724 +       case PCA9632_OFF:
79725 +       case PCA9632_ON:
79726 +               return sprintf(buf, "%s",
79727 +                       led_output_name[get_led_output(pca, ldrx)]);
79728 +
79729 +       case PCA9632_CTRL_BY_PWM:
79730 +               return sprintf(buf, "%d%% \n", calc_dc(reg_read(pca, ldrx)));
79731 +
79732 +       case PCA9632_CTRL_BY_PWM_GRPPWM:
79733 +               /* check group dmblnk */
79734 +               if (get_group_dmblnk(pca))
79735 +                       return sprintf(buf, "%d%% \n",
79736 +                               calc_dc(reg_read(pca, ldrx)));
79737 +               return sprintf(buf, "%d%% \n",
79738 +                                        calc_dc((reg_read(pca, ldrx) & 0xfc)));
79739 +       default:
79740 +               break;
79741 +       }
79742 +
79743 +       return sprintf(buf, "invalid argument\n");
79744 +}
79745 +
79746 +static ssize_t set_brightness(struct device *dev, struct device_attribute *attr,
79747 +                       const char *buf, size_t count)
79748 +{
79749 +       struct i2c_client *client = to_i2c_client(dev);
79750 +       struct pca9632_data *pca = i2c_get_clientdata(client);
79751 +       unsigned int pwm = simple_strtoul(buf, NULL, 10);
79752 +       int ldrx;
79753 +
79754 +       ldrx = reg_id_by_name(attr->attr.name);
79755 +       reg_set_bit_mask(pca, ldrx, 0xff, pwm);
79756 +
79757 +       return count;
79758 +}
79759 +
79760 +static
79761 +DEVICE_ATTR(led0_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
79762 +static
79763 +DEVICE_ATTR(led1_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
79764 +static
79765 +DEVICE_ATTR(led2_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
79766 +static
79767 +DEVICE_ATTR(led3_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
79768 +
79769 +/*
79770 + * Group frequency control
79771 + */
79772 +static ssize_t show_group_freq(struct device *dev, struct device_attribute
79773 +                               *attr, char *buf)
79774 +{
79775 +       uint32_t period;
79776 +       struct i2c_client *client = to_i2c_client(dev);
79777 +       struct pca9632_data *pca = i2c_get_clientdata(client);
79778 +
79779 +       period = ((reg_read(pca, PCA9632_REG_GRPFREQ) + 1) * 1000) / 24;
79780 +
79781 +       return sprintf(buf, "%d ms\n", period);
79782 +}
79783 +
79784 +static ssize_t set_group_freq(struct device *dev, struct device_attribute *attr,
79785 +                       const char *buf, size_t count)
79786 +{
79787 +       struct i2c_client *client = to_i2c_client(dev);
79788 +       struct pca9632_data *pca = i2c_get_clientdata(client);
79789 +
79790 +       unsigned int freq = simple_strtoul(buf, NULL, 10);
79791 +       reg_write(pca, PCA9632_REG_GRPFREQ, freq);
79792 +       return count;
79793 +}
79794 +
79795 +static
79796 +DEVICE_ATTR(group_freq, S_IRUGO | S_IWUSR, show_group_freq, set_group_freq);
79797 +
79798 +/*
79799 + * Group duty cycle tonrol*
79800 + */
79801 +static ssize_t show_group_dc(struct device *dev, struct device_attribute *attr,
79802 +                            char *buf)
79803 +{
79804 +       struct i2c_client *client = to_i2c_client(dev);
79805 +       struct pca9632_data *pca = i2c_get_clientdata(client);
79806 +
79807 +       if (get_group_dmblnk(pca)) {
79808 +
79809 +               if (reg_read(pca, PCA9632_REG_GRPFREQ) <= 0x03)
79810 +                       return sprintf(buf, "%d%% \n",
79811 +                            calc_dc(reg_read(pca, PCA9632_REG_GRPPWM) & 0xfc));
79812 +
79813 +               return sprintf(buf, "%d%% \n", calc_dc(reg_read(pca,
79814 +                                                         PCA9632_REG_GRPPWM)));
79815 +       }
79816 +
79817 +       return sprintf(buf, "%d%% \n", calc_dc(reg_read(pca,
79818 +                                                  PCA9632_REG_GRPPWM) & 0xf0));
79819 +}
79820 +
79821 +static ssize_t set_group_dc(struct device *dev, struct device_attribute *attr,
79822 +                       const char *buf, size_t count)
79823 +{
79824 +       struct i2c_client *client = to_i2c_client(dev);
79825 +       struct pca9632_data *pca = i2c_get_clientdata(client);
79826 +
79827 +       unsigned int dc = simple_strtoul(buf, NULL, 10);
79828 +
79829 +       reg_set_bit_mask(pca, PCA9632_REG_GRPPWM, 0xff, dc);
79830 +
79831 +       return count;
79832 +}
79833 +
79834 +static DEVICE_ATTR(group_dc, S_IRUGO | S_IWUSR, show_group_dc, set_group_dc);
79835 +
79836 +/*
79837 + * LED driver output
79838 + */
79839 +static ssize_t show_led_output(struct device *dev, struct device_attribute
79840 +                                       *attr, char *buf)
79841 +{
79842 +       struct i2c_client *client = to_i2c_client(dev);
79843 +       struct pca9632_data *pca = i2c_get_clientdata(client);
79844 +       int ldrx;
79845 +
79846 +       ldrx = reg_id_by_name(attr->attr.name);
79847 +
79848 +       return sprintf(buf, "%s \n",
79849 +                                   led_output_name[get_led_output(pca, ldrx)]);
79850 +
79851 +}
79852 +static ssize_t set_led_output(struct device *dev, struct device_attribute *attr,
79853 +                       const char *buf, size_t count)
79854 +{
79855 +       struct i2c_client *client = to_i2c_client(dev);
79856 +       struct pca9632_data *pca = i2c_get_clientdata(client);
79857 +       enum pca9632_led_output led_output;
79858 +       int ldrx;
79859 +
79860 +       led_output = simple_strtoul(buf, NULL, 10);
79861 +       ldrx = reg_id_by_name(attr->attr.name);
79862 +       config_led_output(pca, ldrx, led_output);
79863 +
79864 +       return count;
79865 +}
79866 +
79867 +static
79868 +DEVICE_ATTR(led0_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
79869 +static
79870 +DEVICE_ATTR(led1_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
79871 +static
79872 +DEVICE_ATTR(led2_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
79873 +static
79874 +DEVICE_ATTR(led3_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
79875 +
79876 +static struct attribute *pca_sysfs_entries[] = {
79877 +       &dev_attr_group_dmblnk.attr,
79878 +       &dev_attr_led0_pwm.attr,
79879 +       &dev_attr_led1_pwm.attr,
79880 +       &dev_attr_led2_pwm.attr,
79881 +       &dev_attr_led3_pwm.attr,
79882 +       &dev_attr_group_dc.attr,
79883 +       &dev_attr_group_freq.attr,
79884 +       &dev_attr_led0_output.attr,
79885 +       &dev_attr_led1_output.attr,
79886 +       &dev_attr_led2_output.attr,
79887 +       &dev_attr_led3_output.attr,
79888 +       NULL
79889 +};
79890 +
79891 +static struct attribute_group pca_attr_group = {
79892 +       .name   = NULL,                 /* put in device directory */
79893 +       .attrs  = pca_sysfs_entries,
79894 +};
79895 +
79896 +#ifdef CONFIG_PM
79897 +static int pca9632_suspend(struct device *dev, pm_message_t state)
79898 +{
79899 +       /* FIXME: Not implemented */
79900 +       return 0;
79901 +}
79902 +
79903 +static int pca9632_resume(struct device *dev)
79904 +{
79905 +       /* FIXME: Not implemented */
79906 +       return 0;
79907 +}
79908 +#else
79909 +#define pca9632_suspend NULL
79910 +#define pca9632_resume NULL
79911 +#endif
79912 +
79913 +static struct i2c_driver pca9632_driver = {
79914 +       .driver = {
79915 +               .name    = "pca9632",
79916 +               .suspend = pca9632_suspend,
79917 +               .resume  = pca9632_resume,
79918 +       },
79919 +       .id             = I2C_DRIVERID_PCA9632,
79920 +       .attach_adapter = pca9632_attach_adapter,
79921 +       .detach_client  = pca9632_detach_client,
79922 +};
79923 +
79924 +static int pca9632_detect(struct i2c_adapter *adapter, int address, int kind)
79925 +{
79926 +       struct i2c_client *new_client;
79927 +       struct pca9632_data *pca;
79928 +       int err;
79929 +
79930 +       pca = kzalloc(sizeof(struct pca9632_data), GFP_KERNEL);
79931 +       if (!pca)
79932 +               return -ENOMEM;
79933 +
79934 +       mutex_init(&pca->lock);
79935 +
79936 +       new_client = &pca->client;
79937 +       i2c_set_clientdata(new_client, pca);
79938 +       new_client->addr = address;
79939 +       new_client->adapter = adapter;
79940 +       new_client->driver = &pca9632_driver;
79941 +       new_client->flags = 0;
79942 +
79943 +       strlcpy(new_client->name, "pca9632", I2C_NAME_SIZE);
79944 +
79945 +       /* register with i2c core */
79946 +       err = i2c_attach_client(new_client);
79947 +       if (err)
79948 +               goto exit_kfree;
79949 +
79950 +       err = sysfs_create_group(&new_client->dev.kobj, &pca_attr_group);
79951 +       if (err)
79952 +               goto exit_detach;
79953 +
79954 +       /* software reset */
79955 +       if (!software_rst(adapter))
79956 +               dev_info(&pca->client.dev, "pca9632 sw-rst done\n");
79957 +
79958 +       /* enter normal mode */
79959 +       reg_set_bit_mask(pca, PCA9632_REG_MODE1, 0x10, PCA9632_NORMAL);
79960 +
79961 +       return 0;
79962 +
79963 +exit_detach:
79964 +       i2c_detach_client(new_client);
79965 +exit_kfree:
79966 +       kfree(pca);
79967 +
79968 +       return err;
79969 +}
79970 +
79971 +static int pca9632_attach_adapter(struct i2c_adapter *adapter)
79972 +{
79973 +       return i2c_probe(adapter, &addr_data, pca9632_detect);
79974 +}
79975 +
79976 +static int pca9632_detach_client(struct i2c_client *client)
79977 +{
79978 +       int err;
79979 +
79980 +       sysfs_remove_group(&client->dev.kobj, &pca_attr_group);
79981 +       err = i2c_detach_client(client);
79982 +
79983 +       if (err)
79984 +               return err;
79985 +
79986 +       kfree(i2c_get_clientdata(client));
79987 +
79988 +       return 0;
79989 +}
79990 +
79991 +static int __init pca9632_plat_probe(struct platform_device *pdev)
79992 +{
79993 +       /* FIXME: platform data should be attached here */
79994 +       pca9632_pdev = pdev;
79995 +
79996 +       return 0;
79997 +}
79998 +
79999 +static int pca9632_plat_remove(struct platform_device *pdev)
80000 +{
80001 +       return 0;
80002 +}
80003 +
80004 +static struct platform_driver pca9632_plat_driver = {
80005 +       .probe  = pca9632_plat_probe,
80006 +       .remove = pca9632_plat_remove,
80007 +       .driver = {
80008 +               .owner  = THIS_MODULE,
80009 +               .name   = "pca9632",
80010 +       },
80011 +};
80012 +
80013 +static int __init pca9632_init(void)
80014 +{
80015 +       int rc;
80016 +
80017 +       rc = platform_driver_register(&pca9632_plat_driver);
80018 +       if (!rc)
80019 +               i2c_add_driver(&pca9632_driver);
80020 +
80021 +       return rc;
80022 +}
80023 +
80024 +static void __exit pca9632_exit(void)
80025 +{
80026 +       i2c_del_driver(&pca9632_driver);
80027 +
80028 +       platform_driver_unregister(&pca9632_plat_driver);
80029 +}
80030 +
80031 +MODULE_AUTHOR("Matt Hsu <matt_hsu@openmoko.org>");
80032 +MODULE_DESCRIPTION("NXP PCA9632 driver");
80033 +MODULE_LICENSE("GPL");
80034 +
80035 +module_init(pca9632_init);
80036 +module_exit(pca9632_exit);
80037 --- /dev/null
80038 +++ b/drivers/i2c/chips/pca9632.h
80039 @@ -0,0 +1,24 @@
80040 +#ifndef _PCA9632_H
80041 +#define _PCA9632_H
80042 +
80043 +
80044 +enum pca9632_regs{
80045 +
80046 +       PCA9632_REG_MODE1       = 0x00,
80047 +       PCA9632_REG_MODE2       = 0x01,
80048 +       PCA9632_REG_PWM0        = 0x02,
80049 +       PCA9632_REG_PWM1        = 0x03,
80050 +       PCA9632_REG_PWM2        = 0x04,
80051 +       PCA9632_REG_PWM3        = 0x05,
80052 +       PCA9632_REG_GRPPWM      = 0x06,
80053 +       PCA9632_REG_GRPFREQ     = 0x07,
80054 +       PCA9632_REG_LEDOUT      = 0x08,
80055 +       PCA9632_REG_SUBADDR1    = 0x09,
80056 +       PCA9632_REG_SUBADDR2    = 0x0a,
80057 +       PCA9632_REG_SUBADDR3    = 0x0b,
80058 +       PCA9632_REG_ALLCALLADR1 = 0x0c,
80059 +};
80060 +
80061 +#define PCA9632_DMBLNK_SHIFT   5
80062 +
80063 +#endif /* _PCA9632_H */
80064 --- /dev/null
80065 +++ b/drivers/i2c/chips/pcf50606.c
80066 @@ -0,0 +1,2193 @@
80067 +/* Philips/NXP PCF50606 Power Management Unit (PMU) driver
80068 + *
80069 + * (C) 2006-2007 by Openmoko, Inc.
80070 + * Authors: Harald Welte <laforge@openmoko.org>,
80071 + *         Matt Hsu <matt@openmoko.org>
80072 + * All rights reserved.
80073 + *
80074 + * This program is free software; you can redistribute it and/or
80075 + * modify it under the terms of the GNU General Public License as
80076 + * published by the Free Software Foundation; either version 2 of
80077 + * the License, or (at your option) any later version.
80078 + *
80079 + * This program is distributed in the hope that it will be useful,
80080 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
80081 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
80082 + * GNU General Public License for more details.
80083 + *
80084 + * You should have received a copy of the GNU General Public License
80085 + * along with this program; if not, write to the Free Software
80086 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
80087 + * MA 02111-1307 USA
80088 + *
80089 + * This driver is a monster ;) It provides the following features
80090 + * - voltage control for a dozen different voltage domains
80091 + * - charging control for main and backup battery
80092 + * - rtc / alarm
80093 + * - watchdog
80094 + * - adc driver (hw_sensors like)
80095 + * - pwm driver
80096 + * - backlight
80097 + *
80098 + */
80099 +
80100 +#include <linux/module.h>
80101 +#include <linux/init.h>
80102 +#include <linux/i2c.h>
80103 +#include <linux/types.h>
80104 +#include <linux/interrupt.h>
80105 +#include <linux/irq.h>
80106 +#include <linux/workqueue.h>
80107 +#include <linux/delay.h>
80108 +#include <linux/rtc.h>
80109 +#include <linux/bcd.h>
80110 +#include <linux/watchdog.h>
80111 +#include <linux/miscdevice.h>
80112 +#include <linux/input.h>
80113 +#include <linux/fb.h>
80114 +#include <linux/backlight.h>
80115 +#include <linux/sched.h>
80116 +#include <linux/platform_device.h>
80117 +#include <linux/pcf50606.h>
80118 +#include <linux/apm-emulation.h>
80119 +
80120 +#include <asm/mach-types.h>
80121 +#include <mach/gta01.h>
80122 +
80123 +#include "pcf50606.h"
80124 +
80125 +/* we use dev_dbg() throughout the code, but sometimes don't want to
80126 + * write an entire line of debug related information.  This DEBUGPC
80127 + * macro is a continuation for dev_dbg() */
80128 +#ifdef DEBUG
80129 +#define DEBUGPC(x, args ...) printk(x, ## args)
80130 +#else
80131 +#define DEBUGPC(x, args ...)
80132 +#endif
80133 +
80134 +/***********************************************************************
80135 + * Static data / structures
80136 + ***********************************************************************/
80137 +
80138 +static unsigned short normal_i2c[] = { 0x08, I2C_CLIENT_END };
80139 +
80140 +I2C_CLIENT_INSMOD_1(pcf50606);
80141 +
80142 +#define PCF50606_B_CHG_FAST    0       /* Charger Fast allowed */
80143 +#define PCF50606_B_CHG_PRESENT 1       /* Charger present */
80144 +#define PCF50606_B_CHG_FOK     2       /* Fast OK for battery */
80145 +#define PCF50606_B_CHG_ERR     3       /* Charger Error */
80146 +#define PCF50606_B_CHG_PROT    4       /* Charger Protection */
80147 +#define PCF50606_B_CHG_READY   5       /* Charging completed */
80148 +
80149 +#define PCF50606_F_CHG_FAST    (1<<PCF50606_B_CHG_FAST)
80150 +#define PCF50606_F_CHG_PRESENT (1<<PCF50606_B_CHG_PRESENT)
80151 +#define PCF50606_F_CHG_FOK     (1<<PCF50606_B_CHG_FOK)
80152 +#define PCF50606_F_CHG_ERR     (1<<PCF50606_B_CHG_ERR)
80153 +#define PCF50606_F_CHG_PROT    (1<<PCF50606_B_CHG_PROT)
80154 +#define PCF50606_F_CHG_READY   (1<<PCF50606_B_CHG_READY)
80155 +#define PCF50606_F_CHG_MASK    0x000000fc
80156 +
80157 +#define PCF50606_F_PWR_PRESSED 0x00000100
80158 +#define PCF50606_F_RTC_SECOND  0x00000200
80159 +
80160 +enum close_state {
80161 +       CLOSE_STATE_NOT,
80162 +       CLOSE_STATE_ALLOW = 0x2342,
80163 +};
80164 +
80165 +enum pcf50606_suspend_states {
80166 +       PCF50606_SS_RUNNING,
80167 +       PCF50606_SS_STARTING_SUSPEND,
80168 +       PCF50606_SS_COMPLETED_SUSPEND,
80169 +       PCF50606_SS_RESUMING_BUT_NOT_US_YET,
80170 +       PCF50606_SS_STARTING_RESUME,
80171 +       PCF50606_SS_COMPLETED_RESUME,
80172 +};
80173 +
80174 +struct pcf50606_data {
80175 +       struct i2c_client client;
80176 +       struct pcf50606_platform_data *pdata;
80177 +       struct backlight_device *backlight;
80178 +       struct mutex lock;
80179 +       unsigned int flags;
80180 +       unsigned int working;
80181 +       struct mutex working_lock;
80182 +       struct work_struct work;
80183 +       struct rtc_device *rtc;
80184 +       struct input_dev *input_dev;
80185 +       int allow_close;
80186 +       int onkey_seconds;
80187 +       int irq;
80188 +       int coldplug_done;
80189 +       int suppress_onkey_events;
80190 +       enum pcf50606_suspend_states suspend_state;
80191 +#ifdef CONFIG_PM
80192 +       struct {
80193 +               u_int8_t dcdc1, dcdc2;
80194 +               u_int8_t dcdec1;
80195 +               u_int8_t dcudc1;
80196 +               u_int8_t ioregc;
80197 +               u_int8_t d1regc1;
80198 +               u_int8_t d2regc1;
80199 +               u_int8_t d3regc1;
80200 +               u_int8_t lpregc1;
80201 +               u_int8_t adcc1, adcc2;
80202 +               u_int8_t pwmc1;
80203 +               u_int8_t int1m, int2m, int3m;
80204 +       } standby_regs;
80205 +#endif
80206 +};
80207 +
80208 +static struct i2c_driver pcf50606_driver;
80209 +
80210 +/* This is an ugly construct on how to access the (currently single/global)
80211 + * pcf50606 handle from other code in the kernel.  I didn't really come up with
80212 + * a more decent method of dynamically resolving this */
80213 +struct pcf50606_data *pcf50606_global;
80214 +EXPORT_SYMBOL_GPL(pcf50606_global);
80215 +
80216 +static struct platform_device *pcf50606_pdev;
80217 +
80218 +/* This is a 10k, B=3370 NTC Thermistor -10..79 centigrade */
80219 +/* Table entries are offset by +0.5C so a properly rounded value is generated */
80220 +static const u_int16_t ntc_table_10k_3370B[] = {
80221 +       /* -10 */
80222 +       43888, 41819, 39862, 38010, 36257, 34596, 33024, 31534, 30121, 28781,
80223 +       27510, 26304, 25159, 24071, 23038, 22056, 21122, 20234, 19390, 18586,
80224 +       17821, 17093, 16399, 15738, 15107, 14506, 13933, 13387, 12865, 12367,
80225 +       11891, 11437, 11003, 10588, 10192, 9813, 9450, 9103, 8771, 8453,
80226 +       8149, 7857, 7578, 7310, 7054, 6808, 6572, 6346, 6129, 5920,
80227 +       5720, 5528, 5344, 5167, 4996, 4833, 4675, 4524, 4379, 4239,
80228 +       4104, 3975, 3850, 3730, 3614, 3503, 3396, 3292, 3193, 3097,
80229 +       3004, 2915, 2829, 2745, 2665, 2588, 2513, 2441, 2371, 2304,
80230 +       2239, 2176, 2116, 2057, 2000, 1945, 1892, 1841, 1791, 1743,
80231 +};
80232 +
80233 +
80234 +/***********************************************************************
80235 + * Low-Level routines
80236 + ***********************************************************************/
80237 +
80238 +static inline int __reg_write(struct pcf50606_data *pcf, u_int8_t reg,
80239 +                             u_int8_t val)
80240 +{
80241 +       if (pcf->suspend_state == PCF50606_SS_COMPLETED_SUSPEND) {
80242 +               dev_err(&pcf->client.dev, "__reg_write while suspended.\n");
80243 +               dump_stack();
80244 +       }
80245 +       return i2c_smbus_write_byte_data(&pcf->client, reg, val);
80246 +}
80247 +
80248 +static int reg_write(struct pcf50606_data *pcf, u_int8_t reg, u_int8_t val)
80249 +{
80250 +       int ret;
80251 +
80252 +       mutex_lock(&pcf->lock);
80253 +       ret = __reg_write(pcf, reg, val);
80254 +       mutex_unlock(&pcf->lock);
80255 +
80256 +       return ret;
80257 +}
80258 +
80259 +static inline int32_t __reg_read(struct pcf50606_data *pcf, u_int8_t reg)
80260 +{
80261 +       int32_t ret;
80262 +
80263 +       if (pcf->suspend_state == PCF50606_SS_COMPLETED_SUSPEND) {
80264 +               dev_err(&pcf->client.dev, "__reg_read while suspended.\n");
80265 +               dump_stack();
80266 +       }
80267 +       ret = i2c_smbus_read_byte_data(&pcf->client, reg);
80268 +
80269 +       return ret;
80270 +}
80271 +
80272 +static u_int8_t reg_read(struct pcf50606_data *pcf, u_int8_t reg)
80273 +{
80274 +       int32_t ret;
80275 +
80276 +       mutex_lock(&pcf->lock);
80277 +       ret = __reg_read(pcf, reg);
80278 +       mutex_unlock(&pcf->lock);
80279 +
80280 +       return ret & 0xff;
80281 +}
80282 +
80283 +static int reg_set_bit_mask(struct pcf50606_data *pcf,
80284 +                           u_int8_t reg, u_int8_t mask, u_int8_t val)
80285 +{
80286 +       int ret;
80287 +       u_int8_t tmp;
80288 +
80289 +       val &= mask;
80290 +
80291 +       mutex_lock(&pcf->lock);
80292 +
80293 +       tmp = __reg_read(pcf, reg);
80294 +       tmp &= ~mask;
80295 +       tmp |= val;
80296 +       ret = __reg_write(pcf, reg, tmp);
80297 +
80298 +       mutex_unlock(&pcf->lock);
80299 +
80300 +       return ret;
80301 +}
80302 +
80303 +static int reg_clear_bits(struct pcf50606_data *pcf, u_int8_t reg, u_int8_t val)
80304 +{
80305 +       int ret;
80306 +       u_int8_t tmp;
80307 +
80308 +       mutex_lock(&pcf->lock);
80309 +
80310 +       tmp = __reg_read(pcf, reg);
80311 +       tmp &= ~val;
80312 +       ret = __reg_write(pcf, reg, tmp);
80313 +
80314 +       mutex_unlock(&pcf->lock);
80315 +
80316 +       return ret;
80317 +}
80318 +
80319 +/* synchronously read one ADC channel (busy-wait for result to be complete) */
80320 +static u_int16_t adc_read(struct pcf50606_data *pcf,  int channel,
80321 +                         u_int16_t *data2)
80322 +{
80323 +       u_int8_t adcs2, adcs1;
80324 +       u_int16_t ret;
80325 +
80326 +       dev_dbg(&pcf->client.dev, "entering (pcf=%p, channel=%u, data2=%p)\n",
80327 +               pcf, channel, data2);
80328 +
80329 +       channel &= PCF50606_ADCC2_ADCMUX_MASK;
80330 +
80331 +       mutex_lock(&pcf->lock);
80332 +
80333 +       /* start ADC conversion of selected channel */
80334 +       __reg_write(pcf, PCF50606_REG_ADCC2, channel |
80335 +                   PCF50606_ADCC2_ADCSTART | PCF50606_ADCC2_RES_10BIT);
80336 +
80337 +       do {
80338 +               adcs2 = __reg_read(pcf, PCF50606_REG_ADCS2);
80339 +       } while (!(adcs2 & PCF50606_ADCS2_ADCRDY));
80340 +
80341 +       adcs1 = __reg_read(pcf, PCF50606_REG_ADCS1);
80342 +       ret = (adcs1 << 2) | (adcs2 & 0x03);
80343 +
80344 +       if (data2) {
80345 +               adcs1 = __reg_read(pcf, PCF50606_REG_ADCS3);
80346 +               *data2 = (adcs1 << 2) | ((adcs2 & 0x0c) >> 2);
80347 +       }
80348 +
80349 +       mutex_unlock(&pcf->lock);
80350 +
80351 +       dev_dbg(&pcf->client.dev, "returning %u %u\n", ret,
80352 +               data2 ? *data2 : 0);
80353 +
80354 +       return ret;
80355 +}
80356 +
80357 +/***********************************************************************
80358 + * Voltage / ADC
80359 + ***********************************************************************/
80360 +
80361 +static u_int8_t dcudc_voltage(unsigned int millivolts)
80362 +{
80363 +       if (millivolts < 900)
80364 +               return 0;
80365 +       if (millivolts > 5500)
80366 +               return 0x1f;
80367 +       if (millivolts <= 3300) {
80368 +               millivolts -= 900;
80369 +               return millivolts/300;
80370 +       }
80371 +       if (millivolts < 4000)
80372 +               return 0x0f;
80373 +       else {
80374 +               millivolts -= 4000;
80375 +               return millivolts/100;
80376 +       }
80377 +}
80378 +
80379 +static unsigned int dcudc_2voltage(u_int8_t bits)
80380 +{
80381 +       bits &= 0x1f;
80382 +       if (bits < 0x08)
80383 +               return 900 + bits * 300;
80384 +       else if (bits < 0x10)
80385 +               return 3300;
80386 +       else
80387 +               return 4000 + bits * 100;
80388 +}
80389 +
80390 +static u_int8_t dcdec_voltage(unsigned int millivolts)
80391 +{
80392 +       if (millivolts < 900)
80393 +               return 0;
80394 +       else if (millivolts > 3300)
80395 +               return 0x0f;
80396 +
80397 +       millivolts -= 900;
80398 +       return millivolts/300;
80399 +}
80400 +
80401 +static unsigned int dcdec_2voltage(u_int8_t bits)
80402 +{
80403 +       bits &= 0x0f;
80404 +       return 900 + bits*300;
80405 +}
80406 +
80407 +static u_int8_t dcdc_voltage(unsigned int millivolts)
80408 +{
80409 +       if (millivolts < 900)
80410 +               return 0;
80411 +       else if (millivolts > 3600)
80412 +               return 0x1f;
80413 +
80414 +       if (millivolts < 1500) {
80415 +               millivolts -= 900;
80416 +               return millivolts/25;
80417 +       } else {
80418 +               millivolts -= 1500;
80419 +               return 0x18 + millivolts/300;
80420 +       }
80421 +}
80422 +
80423 +static unsigned int dcdc_2voltage(u_int8_t bits)
80424 +{
80425 +       bits &= 0x1f;
80426 +       if ((bits & 0x18) == 0x18)
80427 +               return 1500 + ((bits & 0x7) * 300);
80428 +       else
80429 +               return 900 + (bits * 25);
80430 +}
80431 +
80432 +static u_int8_t dx_voltage(unsigned int millivolts)
80433 +{
80434 +       if (millivolts < 900)
80435 +               return 0;
80436 +       else if (millivolts > 3300)
80437 +               return 0x18;
80438 +
80439 +       millivolts -= 900;
80440 +       return millivolts/100;
80441 +}
80442 +
80443 +static unsigned int dx_2voltage(u_int8_t bits)
80444 +{
80445 +       bits &= 0x1f;
80446 +       return 900 + (bits * 100);
80447 +}
80448 +
80449 +static const u_int8_t regulator_registers[__NUM_PCF50606_REGULATORS] = {
80450 +       [PCF50606_REGULATOR_DCD]        = PCF50606_REG_DCDC1,
80451 +       [PCF50606_REGULATOR_DCDE]       = PCF50606_REG_DCDEC1,
80452 +       [PCF50606_REGULATOR_DCUD]       = PCF50606_REG_DCUDC1,
80453 +       [PCF50606_REGULATOR_D1REG]      = PCF50606_REG_D1REGC1,
80454 +       [PCF50606_REGULATOR_D2REG]      = PCF50606_REG_D2REGC1,
80455 +       [PCF50606_REGULATOR_D3REG]      = PCF50606_REG_D3REGC1,
80456 +       [PCF50606_REGULATOR_LPREG]      = PCF50606_REG_LPREGC1,
80457 +       [PCF50606_REGULATOR_IOREG]      = PCF50606_REG_IOREGC,
80458 +};
80459 +
80460 +int pcf50606_onoff_set(struct pcf50606_data *pcf,
80461 +                      enum pcf50606_regulator_id reg, int on)
80462 +{
80463 +       u_int8_t addr;
80464 +
80465 +       if (reg >= __NUM_PCF50606_REGULATORS)
80466 +               return -EINVAL;
80467 +
80468 +       /* IOREG cannot be powered off since it powers the PMU I2C */
80469 +       if (reg == PCF50606_REGULATOR_IOREG)
80470 +               return -EIO;
80471 +
80472 +       addr = regulator_registers[reg];
80473 +
80474 +       if (on == 0)
80475 +               reg_set_bit_mask(pcf, addr, 0xe0, 0x00);
80476 +       else
80477 +               reg_set_bit_mask(pcf, addr, 0xe0, 0xe0);
80478 +
80479 +       return 0;
80480 +}
80481 +EXPORT_SYMBOL_GPL(pcf50606_onoff_set);
80482 +
80483 +int pcf50606_onoff_get(struct pcf50606_data *pcf,
80484 +                      enum pcf50606_regulator_id reg)
80485 +{
80486 +       u_int8_t val, addr;
80487 +
80488 +       if (reg >= __NUM_PCF50606_REGULATORS)
80489 +               return -EINVAL;
80490 +
80491 +       addr = regulator_registers[reg];
80492 +       val = (reg_read(pcf, addr) & 0xe0) >> 5;
80493 +
80494 +       /* PWREN1 = 1, PWREN2 = 1, see table 16 of datasheet */
80495 +       switch (val) {
80496 +       case 0:
80497 +       case 5:
80498 +               return 0;
80499 +       default:
80500 +               return 1;
80501 +       }
80502 +}
80503 +EXPORT_SYMBOL_GPL(pcf50606_onoff_get);
80504 +
80505 +int pcf50606_voltage_set(struct pcf50606_data *pcf,
80506 +                        enum pcf50606_regulator_id reg,
80507 +                        unsigned int millivolts)
80508 +{
80509 +       u_int8_t volt_bits;
80510 +       u_int8_t regnr;
80511 +       int rc;
80512 +
80513 +       dev_dbg(&pcf->client.dev, "pcf=%p, reg=%d, mvolts=%d\n", pcf, reg,
80514 +               millivolts);
80515 +
80516 +       if (reg >= __NUM_PCF50606_REGULATORS)
80517 +               return -EINVAL;
80518 +
80519 +       if (millivolts > pcf->pdata->rails[reg].voltage.max)
80520 +               return -EINVAL;
80521 +
80522 +       switch (reg) {
80523 +       case PCF50606_REGULATOR_DCD:
80524 +               volt_bits = dcdc_voltage(millivolts);
80525 +               rc = reg_set_bit_mask(pcf, PCF50606_REG_DCDC1, 0x1f,
80526 +                                     volt_bits);
80527 +               break;
80528 +       case PCF50606_REGULATOR_DCDE:
80529 +               volt_bits = dcdec_voltage(millivolts);
80530 +               rc = reg_set_bit_mask(pcf, PCF50606_REG_DCDEC1, 0x0f,
80531 +                                     volt_bits);
80532 +               break;
80533 +       case PCF50606_REGULATOR_DCUD:
80534 +               volt_bits = dcudc_voltage(millivolts);
80535 +               rc = reg_set_bit_mask(pcf, PCF50606_REG_DCUDC1, 0x1f,
80536 +                                     volt_bits);
80537 +               break;
80538 +       case PCF50606_REGULATOR_D1REG:
80539 +       case PCF50606_REGULATOR_D2REG:
80540 +       case PCF50606_REGULATOR_D3REG:
80541 +               regnr = PCF50606_REG_D1REGC1 + (reg - PCF50606_REGULATOR_D1REG);
80542 +               volt_bits = dx_voltage(millivolts);
80543 +               rc = reg_set_bit_mask(pcf, regnr, 0x1f, volt_bits);
80544 +               break;
80545 +       case PCF50606_REGULATOR_LPREG:
80546 +               volt_bits = dx_voltage(millivolts);
80547 +               rc = reg_set_bit_mask(pcf, PCF50606_REG_LPREGC1, 0x1f,
80548 +                                     volt_bits);
80549 +               break;
80550 +       case PCF50606_REGULATOR_IOREG:
80551 +               if (millivolts < 1800)
80552 +                       return -EINVAL;
80553 +               volt_bits = dx_voltage(millivolts);
80554 +               rc = reg_set_bit_mask(pcf, PCF50606_REG_IOREGC, 0x1f,
80555 +                                     volt_bits);
80556 +               break;
80557 +       default:
80558 +               return -EINVAL;
80559 +       }
80560 +
80561 +       return rc;
80562 +}
80563 +EXPORT_SYMBOL_GPL(pcf50606_voltage_set);
80564 +
80565 +unsigned int pcf50606_voltage_get(struct pcf50606_data *pcf,
80566 +                        enum pcf50606_regulator_id reg)
80567 +{
80568 +       u_int8_t volt_bits;
80569 +       u_int8_t regnr;
80570 +       unsigned int rc = 0;
80571 +
80572 +       if (reg >= __NUM_PCF50606_REGULATORS)
80573 +               return -EINVAL;
80574 +
80575 +       switch (reg) {
80576 +       case PCF50606_REGULATOR_DCD:
80577 +               volt_bits = reg_read(pcf, PCF50606_REG_DCDC1) & 0x1f;
80578 +               rc = dcdc_2voltage(volt_bits);
80579 +               break;
80580 +       case PCF50606_REGULATOR_DCDE:
80581 +               volt_bits = reg_read(pcf, PCF50606_REG_DCDEC1) & 0x0f;
80582 +               rc = dcdec_2voltage(volt_bits);
80583 +               break;
80584 +       case PCF50606_REGULATOR_DCUD:
80585 +               volt_bits = reg_read(pcf, PCF50606_REG_DCUDC1) & 0x1f;
80586 +               rc = dcudc_2voltage(volt_bits);
80587 +               break;
80588 +       case PCF50606_REGULATOR_D1REG:
80589 +       case PCF50606_REGULATOR_D2REG:
80590 +       case PCF50606_REGULATOR_D3REG:
80591 +               regnr = PCF50606_REG_D1REGC1 + (reg - PCF50606_REGULATOR_D1REG);
80592 +               volt_bits = reg_read(pcf, regnr) & 0x1f;
80593 +               if (volt_bits > 0x18)
80594 +                       volt_bits = 0x18;
80595 +               rc = dx_2voltage(volt_bits);
80596 +               break;
80597 +       case PCF50606_REGULATOR_LPREG:
80598 +               volt_bits = reg_read(pcf, PCF50606_REG_LPREGC1) & 0x1f;
80599 +               if (volt_bits > 0x18)
80600 +                       volt_bits = 0x18;
80601 +               rc = dx_2voltage(volt_bits);
80602 +               break;
80603 +       case PCF50606_REGULATOR_IOREG:
80604 +               volt_bits = reg_read(pcf, PCF50606_REG_IOREGC) & 0x1f;
80605 +               if (volt_bits > 0x18)
80606 +                       volt_bits = 0x18;
80607 +               rc = dx_2voltage(volt_bits);
80608 +               break;
80609 +       default:
80610 +               return -EINVAL;
80611 +       }
80612 +
80613 +       return rc;
80614 +}
80615 +EXPORT_SYMBOL_GPL(pcf50606_voltage_get);
80616 +
80617 +/* go into 'STANDBY' mode, i.e. power off the main CPU and peripherals */
80618 +void pcf50606_go_standby(void)
80619 +{
80620 +       reg_write(pcf50606_global, PCF50606_REG_OOCC1,
80621 +                 PCF50606_OOCC1_GOSTDBY);
80622 +}
80623 +EXPORT_SYMBOL_GPL(pcf50606_go_standby);
80624 +
80625 +void pcf50606_gpo0_set(struct pcf50606_data *pcf, int on)
80626 +{
80627 +       u_int8_t val;
80628 +
80629 +       if (on)
80630 +               val = 0x07;
80631 +       else
80632 +               val = 0x0f;
80633 +
80634 +       reg_set_bit_mask(pcf, PCF50606_REG_GPOC1, 0x0f, val);
80635 +}
80636 +EXPORT_SYMBOL_GPL(pcf50606_gpo0_set);
80637 +
80638 +int pcf50606_gpo0_get(struct pcf50606_data *pcf)
80639 +{
80640 +       u_int8_t reg = reg_read(pcf, PCF50606_REG_GPOC1) & 0x0f;
80641 +
80642 +       if (reg == 0x07 || reg == 0x08)
80643 +               return 1;
80644 +
80645 +       return 0;
80646 +}
80647 +EXPORT_SYMBOL_GPL(pcf50606_gpo0_get);
80648 +
80649 +static void pcf50606_work(struct work_struct *work)
80650 +{
80651 +       struct pcf50606_data *pcf =
80652 +                       container_of(work, struct pcf50606_data, work);
80653 +       u_int8_t pcfirq[3];
80654 +       int ret;
80655 +
80656 +       mutex_lock(&pcf->working_lock);
80657 +       pcf->working = 1;
80658 +
80659 +       /* sanity */
80660 +       if (!&pcf->client.dev)
80661 +               goto bail;
80662 +
80663 +       /*
80664 +        * if we are presently suspending, we are not in a position to deal
80665 +        * with pcf50606 interrupts at all.
80666 +        *
80667 +        * Because we didn't clear the int pending registers, there will be
80668 +        * no edge / interrupt waiting for us when we wake.  But it is OK
80669 +        * because at the end of our resume, we call this workqueue function
80670 +        * gratuitously, clearing the pending register and re-enabling
80671 +        * servicing this interrupt.
80672 +        */
80673 +
80674 +       if ((pcf->suspend_state == PCF50606_SS_STARTING_SUSPEND) ||
80675 +           (pcf->suspend_state == PCF50606_SS_COMPLETED_SUSPEND))
80676 +               goto bail;
80677 +
80678 +       /*
80679 +        * If we are inside suspend -> resume completion time we don't attempt
80680 +        * service until we have fully resumed.  Although we could talk to the
80681 +        * device as soon as I2C is up, the regs in the device which we might
80682 +        * choose to modify as part of the service action have not been
80683 +        * reloaded with their pre-suspend states yet.  Therefore we will
80684 +        * defer our service if we are called like that until our resume has
80685 +        * completed.
80686 +        *
80687 +        * This shouldn't happen any more because we disable servicing this
80688 +        * interrupt in suspend and don't re-enable it until resume is
80689 +        * completed.
80690 +        */
80691 +
80692 +       if (pcf->suspend_state &&
80693 +               (pcf->suspend_state != PCF50606_SS_COMPLETED_RESUME))
80694 +               goto reschedule;
80695 +
80696 +       /* this is the case early in resume! Sanity check! */
80697 +       if (i2c_get_clientdata(&pcf->client) == NULL)
80698 +               goto reschedule;
80699 +
80700 +       /*
80701 +        * p35 pcf50606 datasheet rev 2.2:
80702 +        * ''The system controller shall read all interrupt registers in
80703 +        *   one I2C read action''
80704 +        * because if you don't INT# gets stuck asserted forever after a
80705 +        * while
80706 +        */
80707 +       ret = i2c_smbus_read_i2c_block_data(&pcf->client, PCF50606_REG_INT1,
80708 +                                           sizeof(pcfirq), pcfirq);
80709 +       if (ret != sizeof(pcfirq)) {
80710 +               DEBUGPC("Oh crap PMU IRQ register read failed %d\n", ret);
80711 +               /*
80712 +                * it shouldn't fail, we no longer attempt to use
80713 +                * I2C while it can be suspended.  But we don't have
80714 +                * much option but to retry if if it ever did fail,
80715 +                * because if we don't service the interrupt to clear
80716 +                * it, we will never see another PMU interrupt edge.
80717 +                */
80718 +               goto reschedule;
80719 +       }
80720 +
80721 +       /* hey did we just resume? (because we don't get here unless we are
80722 +        * running normally or the first call after resumption)
80723 +        *
80724 +        * pcf50606 resume is really really over now then.
80725 +        */
80726 +       if (pcf->suspend_state != PCF50606_SS_RUNNING) {
80727 +               pcf->suspend_state = PCF50606_SS_RUNNING;
80728 +
80729 +               /* peek at the IRQ reason, if power button then set a flag
80730 +                * so that we do not signal the event to userspace
80731 +                */
80732 +               if (pcfirq[0] & (PCF50606_INT1_ONKEYF | PCF50606_INT1_ONKEYR)) {
80733 +                       pcf->suppress_onkey_events = 1;
80734 +                       dev_dbg(&pcf->client.dev,
80735 +                               "Wake by ONKEY, suppressing ONKEY events");
80736 +               } else {
80737 +                       pcf->suppress_onkey_events = 0;
80738 +               }
80739 +       }
80740 +
80741 +       if (!pcf->coldplug_done) {
80742 +               DEBUGPC("PMU Coldplug init\n");
80743 +
80744 +               /* we used SECOND to kick ourselves started -- turn it off */
80745 +               pcfirq[0] &= ~PCF50606_INT1_SECOND;
80746 +               reg_set_bit_mask(pcf, PCF50606_REG_INT1M, PCF50606_INT1_SECOND,
80747 +                                PCF50606_INT1_SECOND);
80748 +
80749 +               /* coldplug the USB if present */
80750 +               if (__reg_read(pcf, PCF50606_REG_OOCS) & PCF50606_OOCS_EXTON) {
80751 +                       /* Charger inserted */
80752 +                       DEBUGPC("COLD CHGINS ");
80753 +                       input_report_key(pcf->input_dev, KEY_BATTERY, 1);
80754 +                       apm_queue_event(APM_POWER_STATUS_CHANGE);
80755 +                       pcf->flags |= PCF50606_F_CHG_PRESENT;
80756 +                       if (pcf->pdata->cb)
80757 +                               pcf->pdata->cb(&pcf->client.dev,
80758 +                                               PCF50606_FEAT_MBC,
80759 +                                               PMU_EVT_INSERT);
80760 +               }
80761 +
80762 +               pcf->coldplug_done = 1;
80763 +       }
80764 +
80765 +
80766 +       dev_dbg(&pcf->client.dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x:",
80767 +               pcfirq[0], pcfirq[1], pcfirq[2]);
80768 +
80769 +       if (pcfirq[0] & PCF50606_INT1_ONKEYF) {
80770 +               /* ONKEY falling edge (start of button press) */
80771 +               pcf->flags |= PCF50606_F_PWR_PRESSED;
80772 +               if (!pcf->suppress_onkey_events) {
80773 +                       DEBUGPC("ONKEYF ");
80774 +                       input_report_key(pcf->input_dev, KEY_POWER, 1);
80775 +               } else {
80776 +                       DEBUGPC("ONKEYF(unreported) ");
80777 +               }
80778 +       }
80779 +       if (pcfirq[0] & PCF50606_INT1_ONKEY1S) {
80780 +               /* ONKEY pressed for more than 1 second */
80781 +               pcf->onkey_seconds = 0;
80782 +               DEBUGPC("ONKEY1S ");
80783 +               /* Tell PMU we are taking care of this */
80784 +               reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
80785 +                                PCF50606_OOCC1_TOTRST,
80786 +                                PCF50606_OOCC1_TOTRST);
80787 +               /* enable SECOND interrupt (hz tick) */
80788 +               reg_clear_bits(pcf, PCF50606_REG_INT1M, PCF50606_INT1_SECOND);
80789 +       }
80790 +       if (pcfirq[0] & PCF50606_INT1_ONKEYR) {
80791 +               /* ONKEY rising edge (end of button press) */
80792 +               pcf->flags &= ~PCF50606_F_PWR_PRESSED;
80793 +               pcf->onkey_seconds = -1;
80794 +               if (!pcf->suppress_onkey_events) {
80795 +                       DEBUGPC("ONKEYR ");
80796 +                       input_report_key(pcf->input_dev, KEY_POWER, 0);
80797 +               } else {
80798 +                       DEBUGPC("ONKEYR(suppressed) ");
80799 +                       /* don't suppress any more power button events */
80800 +                       pcf->suppress_onkey_events = 0;
80801 +               }
80802 +               /* disable SECOND interrupt in case RTC didn't
80803 +                * request it */
80804 +               if (!(pcf->flags & PCF50606_F_RTC_SECOND))
80805 +                       reg_set_bit_mask(pcf, PCF50606_REG_INT1M,
80806 +                                        PCF50606_INT1_SECOND,
80807 +                                        PCF50606_INT1_SECOND);
80808 +       }
80809 +       if (pcfirq[0] & PCF50606_INT1_EXTONR) {
80810 +               DEBUGPC("EXTONR ");
80811 +               input_report_key(pcf->input_dev, KEY_POWER2, 1);
80812 +       }
80813 +       if (pcfirq[0] & PCF50606_INT1_EXTONF) {
80814 +               DEBUGPC("EXTONF ");
80815 +               input_report_key(pcf->input_dev, KEY_POWER2, 0);
80816 +       }
80817 +       if (pcfirq[0] & PCF50606_INT1_SECOND) {
80818 +               DEBUGPC("SECOND ");
80819 +               if (pcf->flags & PCF50606_F_RTC_SECOND)
80820 +                       rtc_update_irq(pcf->rtc, 1,
80821 +                                      RTC_PF | RTC_IRQF);
80822 +
80823 +               if (pcf->onkey_seconds >= 0 &&
80824 +                   pcf->flags & PCF50606_F_PWR_PRESSED) {
80825 +                       DEBUGPC("ONKEY_SECONDS(%u, OOCC1=0x%02x) ",
80826 +                               pcf->onkey_seconds,
80827 +                               reg_read(pcf, PCF50606_REG_OOCC1));
80828 +                       pcf->onkey_seconds++;
80829 +                       if (pcf->onkey_seconds >=
80830 +                           pcf->pdata->onkey_seconds_required) {
80831 +                               /* Ask init to do 'ctrlaltdel' */
80832 +                               /*
80833 +                                * currently Linux reacts badly to issuing a
80834 +                                * signal to PID #1 before init is started.
80835 +                                * What happens is that the next kernel thread
80836 +                                * to start, which is the JFFS2 Garbage
80837 +                                * collector in our case, gets the signal
80838 +                                * instead and proceeds to fail to fork --
80839 +                                * which is very bad.  Therefore we confirm
80840 +                                * PID #1 exists before issuing the signal
80841 +                                */
80842 +                               if (find_task_by_pid_ns(1, &init_pid_ns)) {
80843 +                                       kill_pid(task_pid(find_task_by_pid_ns(1,
80844 +                                                       &init_pid_ns)), SIGINT, 1);
80845 +                                       DEBUGPC("SIGINT(init) ");
80846 +                               }
80847 +                               /* FIXME: what to do if userspace doesn't
80848 +                                * shut down? Do we want to force it? */
80849 +                       }
80850 +               }
80851 +       }
80852 +       if (pcfirq[0] & PCF50606_INT1_ALARM) {
80853 +               DEBUGPC("ALARM ");
80854 +               if (pcf->pdata->used_features & PCF50606_FEAT_RTC)
80855 +                       rtc_update_irq(pcf->rtc, 1,
80856 +                                      RTC_AF | RTC_IRQF);
80857 +       }
80858 +
80859 +       if (pcfirq[1] & PCF50606_INT2_CHGINS) {
80860 +               /* Charger inserted */
80861 +               DEBUGPC("CHGINS ");
80862 +               input_report_key(pcf->input_dev, KEY_BATTERY, 1);
80863 +               apm_queue_event(APM_POWER_STATUS_CHANGE);
80864 +               pcf->flags |= PCF50606_F_CHG_PRESENT;
80865 +               if (pcf->pdata->cb)
80866 +                       pcf->pdata->cb(&pcf->client.dev,
80867 +                                      PCF50606_FEAT_MBC, PMU_EVT_INSERT);
80868 +               /* FIXME: how to signal this to userspace */
80869 +       }
80870 +       if (pcfirq[1] & PCF50606_INT2_CHGRM) {
80871 +               /* Charger removed */
80872 +               DEBUGPC("CHGRM ");
80873 +               input_report_key(pcf->input_dev, KEY_BATTERY, 0);
80874 +               apm_queue_event(APM_POWER_STATUS_CHANGE);
80875 +               pcf->flags &= ~(PCF50606_F_CHG_MASK|PCF50606_F_CHG_PRESENT);
80876 +               if (pcf->pdata->cb)
80877 +                       pcf->pdata->cb(&pcf->client.dev,
80878 +                                      PCF50606_FEAT_MBC, PMU_EVT_INSERT);
80879 +               /* FIXME: how signal this to userspace */
80880 +       }
80881 +       if (pcfirq[1] & PCF50606_INT2_CHGFOK) {
80882 +               /* Battery ready for fast charging */
80883 +               DEBUGPC("CHGFOK ");
80884 +               pcf->flags |= PCF50606_F_CHG_FOK;
80885 +               /* FIXME: how to signal this to userspace */
80886 +       }
80887 +       if (pcfirq[1] & PCF50606_INT2_CHGERR) {
80888 +               /* Error in charge mode */
80889 +               DEBUGPC("CHGERR ");
80890 +               pcf->flags |= PCF50606_F_CHG_ERR;
80891 +               pcf->flags &= ~(PCF50606_F_CHG_FOK|PCF50606_F_CHG_READY);
80892 +               /* FIXME: how to signal this to userspace */
80893 +       }
80894 +       if (pcfirq[1] & PCF50606_INT2_CHGFRDY) {
80895 +               /* Fast charge completed */
80896 +               DEBUGPC("CHGFRDY ");
80897 +               pcf->flags |= PCF50606_F_CHG_READY;
80898 +               pcf->flags &= ~PCF50606_F_CHG_FOK;
80899 +               /* FIXME: how to signal this to userspace */
80900 +       }
80901 +       if (pcfirq[1] & PCF50606_INT2_CHGPROT) {
80902 +               /* Charging protection interrupt */
80903 +               DEBUGPC("CHGPROT ");
80904 +               pcf->flags &= ~(PCF50606_F_CHG_FOK|PCF50606_F_CHG_READY);
80905 +               /* FIXME: signal this to userspace */
80906 +       }
80907 +       if (pcfirq[1] & PCF50606_INT2_CHGWD10S) {
80908 +               /* Charger watchdog will expire in 10 seconds */
80909 +               DEBUGPC("CHGWD10S ");
80910 +               reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
80911 +                                PCF50606_OOCC1_WDTRST,
80912 +                                PCF50606_OOCC1_WDTRST);
80913 +       }
80914 +       if (pcfirq[1] & PCF50606_INT2_CHGWDEXP) {
80915 +               /* Charger watchdog expires */
80916 +               DEBUGPC("CHGWDEXP ");
80917 +               /* FIXME: how to signal this to userspace */
80918 +       }
80919 +
80920 +       if (pcfirq[2] & PCF50606_INT3_ADCRDY) {
80921 +               /* ADC result ready */
80922 +               DEBUGPC("ADCRDY ");
80923 +       }
80924 +       if (pcfirq[2] & PCF50606_INT3_ACDINS) {
80925 +               /* Accessory insertion detected */
80926 +               DEBUGPC("ACDINS ");
80927 +               if (pcf->pdata->cb)
80928 +                       pcf->pdata->cb(&pcf->client.dev,
80929 +                                      PCF50606_FEAT_ACD, PMU_EVT_INSERT);
80930 +       }
80931 +       if (pcfirq[2] & PCF50606_INT3_ACDREM) {
80932 +               /* Accessory removal detected */
80933 +               DEBUGPC("ACDREM ");
80934 +               if (pcf->pdata->cb)
80935 +                       pcf->pdata->cb(&pcf->client.dev,
80936 +                                      PCF50606_FEAT_ACD, PMU_EVT_REMOVE);
80937 +       }
80938 +       /* FIXME: TSCPRES */
80939 +       if (pcfirq[2] & PCF50606_INT3_LOWBAT) {
80940 +               if (__reg_read(pcf, PCF50606_REG_OOCS) & PCF50606_OOCS_EXTON) {
80941 +                       /*
80942 +                        * hey no need to freak out, we have some kind of
80943 +                        * valid charger power
80944 +                        */
80945 +                       DEBUGPC("(NO)BAT ");
80946 +               } else {
80947 +                       /* Really low battery voltage, we have 8 seconds left */
80948 +                       DEBUGPC("LOWBAT ");
80949 +                       /*
80950 +                        * currently Linux reacts badly to issuing a signal to
80951 +                        * PID #1 before init is started.  What happens is that
80952 +                        * the next kernel thread to start, which is the JFFS2
80953 +                        * Garbage collector in our case, gets the signal
80954 +                        * instead and proceeds to fail to fork -- which is
80955 +                        * very bad.  Therefore we confirm PID #1 exists
80956 +                        * before issuing SPIGPWR
80957 +                        */
80958 +                       if (find_task_by_pid_ns(1, &init_pid_ns)) {
80959 +                               apm_queue_event(APM_LOW_BATTERY);
80960 +                               DEBUGPC("SIGPWR(init) ");
80961 +                               kill_pid(task_pid(find_task_by_pid_ns(1, &init_pid_ns)), SIGPWR, 1);
80962 +                       } else
80963 +                               /*
80964 +                                * well, our situation is like this:  we do not
80965 +                                * have any external power, we have a low
80966 +                                * battery and since PID #1 doesn't exist yet,
80967 +                                * we are early in the boot, likely before
80968 +                                * rootfs mount.  We should just call it a day
80969 +                                */
80970 +                               apm_queue_event(APM_CRITICAL_SUSPEND);
80971 +               }
80972 +               /* Tell PMU we are taking care of this */
80973 +               reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
80974 +                                PCF50606_OOCC1_TOTRST,
80975 +                                PCF50606_OOCC1_TOTRST);
80976 +       }
80977 +       if (pcfirq[2] & PCF50606_INT3_HIGHTMP) {
80978 +               /* High temperature */
80979 +               DEBUGPC("HIGHTMP ");
80980 +               apm_queue_event(APM_CRITICAL_SUSPEND);
80981 +       }
80982 +
80983 +       DEBUGPC("\n");
80984 +
80985 +bail:
80986 +       pcf->working = 0;
80987 +       input_sync(pcf->input_dev);
80988 +       put_device(&pcf->client.dev);
80989 +       mutex_unlock(&pcf->working_lock);
80990 +
80991 +       return;
80992 +
80993 +reschedule:
80994 +
80995 +       if ((pcf->suspend_state != PCF50606_SS_STARTING_SUSPEND) &&
80996 +           (pcf->suspend_state != PCF50606_SS_COMPLETED_SUSPEND)) {
80997 +               msleep(10);
80998 +               dev_info(&pcf->client.dev, "rescheduling interrupt service\n");
80999 +       }
81000 +       if (!schedule_work(&pcf->work))
81001 +               dev_err(&pcf->client.dev, "int service reschedule failed\n");
81002 +
81003 +       /* we don't put the device here, hold it for next time */
81004 +       mutex_unlock(&pcf->working_lock);
81005 +}
81006 +
81007 +static irqreturn_t pcf50606_irq(int irq, void *_pcf)
81008 +{
81009 +       struct pcf50606_data *pcf = _pcf;
81010 +
81011 +       dev_dbg(&pcf->client.dev, "entering(irq=%u, pcf=%p): scheduling work\n",
81012 +               irq, _pcf);
81013 +       get_device(&pcf->client.dev);
81014 +       if (!schedule_work(&pcf->work) && !pcf->working)
81015 +               dev_err(&pcf->client.dev, "pcf irq work already queued.\n");
81016 +
81017 +       return IRQ_HANDLED;
81018 +}
81019 +
81020 +static u_int16_t adc_to_batt_millivolts(u_int16_t adc)
81021 +{
81022 +       u_int16_t mvolts;
81023 +
81024 +       mvolts = (adc * 6000) / 1024;
81025 +
81026 +       return mvolts;
81027 +}
81028 +
81029 +#define BATTVOLT_SCALE_START 2800
81030 +#define BATTVOLT_SCALE_END 4200
81031 +#define BATTVOLT_SCALE_DIVIDER ((BATTVOLT_SCALE_END - BATTVOLT_SCALE_START)/100)
81032 +
81033 +static u_int8_t battvolt_scale(u_int16_t battvolt)
81034 +{
81035 +       /* FIXME: this linear scale is completely bogus */
81036 +       u_int16_t battvolt_relative = battvolt - BATTVOLT_SCALE_START;
81037 +       unsigned int percent = battvolt_relative / BATTVOLT_SCALE_DIVIDER;
81038 +
81039 +       return percent;
81040 +}
81041 +
81042 +u_int16_t pcf50606_battvolt(struct pcf50606_data *pcf)
81043 +{
81044 +       u_int16_t adc;
81045 +       adc = adc_read(pcf, PCF50606_ADCMUX_BATVOLT_RES, NULL);
81046 +
81047 +       return adc_to_batt_millivolts(adc);
81048 +}
81049 +EXPORT_SYMBOL_GPL(pcf50606_battvolt);
81050 +
81051 +static ssize_t show_battvolt(struct device *dev, struct device_attribute *attr,
81052 +                            char *buf)
81053 +{
81054 +       struct i2c_client *client = to_i2c_client(dev);
81055 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81056 +
81057 +       return sprintf(buf, "%u\n", pcf50606_battvolt(pcf));
81058 +}
81059 +static DEVICE_ATTR(battvolt, S_IRUGO | S_IWUSR, show_battvolt, NULL);
81060 +
81061 +static int reg_id_by_name(const char *name)
81062 +{
81063 +       int reg_id;
81064 +
81065 +       if (!strcmp(name, "voltage_dcd"))
81066 +               reg_id = PCF50606_REGULATOR_DCD;
81067 +       else if (!strcmp(name, "voltage_dcde"))
81068 +               reg_id = PCF50606_REGULATOR_DCDE;
81069 +       else if (!strcmp(name, "voltage_dcud"))
81070 +               reg_id = PCF50606_REGULATOR_DCUD;
81071 +       else if (!strcmp(name, "voltage_d1reg"))
81072 +               reg_id = PCF50606_REGULATOR_D1REG;
81073 +       else if (!strcmp(name, "voltage_d2reg"))
81074 +               reg_id = PCF50606_REGULATOR_D2REG;
81075 +       else if (!strcmp(name, "voltage_d3reg"))
81076 +               reg_id = PCF50606_REGULATOR_D3REG;
81077 +       else if (!strcmp(name, "voltage_lpreg"))
81078 +               reg_id = PCF50606_REGULATOR_LPREG;
81079 +       else if (!strcmp(name, "voltage_ioreg"))
81080 +               reg_id = PCF50606_REGULATOR_IOREG;
81081 +       else
81082 +               reg_id = -1;
81083 +
81084 +       return reg_id;
81085 +}
81086 +
81087 +static ssize_t show_vreg(struct device *dev, struct device_attribute *attr,
81088 +                        char *buf)
81089 +{
81090 +       struct i2c_client *client = to_i2c_client(dev);
81091 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81092 +       unsigned int reg_id;
81093 +
81094 +       reg_id = reg_id_by_name(attr->attr.name);
81095 +       if (reg_id < 0)
81096 +               return 0;
81097 +
81098 +       if (pcf50606_onoff_get(pcf, reg_id) > 0)
81099 +               return sprintf(buf, "%u\n", pcf50606_voltage_get(pcf, reg_id));
81100 +       else
81101 +               return strlcpy(buf, "0\n", PAGE_SIZE);
81102 +}
81103 +
81104 +static ssize_t set_vreg(struct device *dev, struct device_attribute *attr,
81105 +                       const char *buf, size_t count)
81106 +{
81107 +       struct i2c_client *client = to_i2c_client(dev);
81108 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81109 +       unsigned long mvolts = simple_strtoul(buf, NULL, 10);
81110 +       unsigned int reg_id;
81111 +
81112 +       reg_id = reg_id_by_name(attr->attr.name);
81113 +       if (reg_id < 0)
81114 +               return -EIO;
81115 +
81116 +       dev_dbg(dev, "attempting to set %s(%d) to %lu mvolts\n",
81117 +               attr->attr.name, reg_id, mvolts);
81118 +
81119 +       if (mvolts == 0) {
81120 +               pcf50606_onoff_set(pcf, reg_id, 0);
81121 +       } else {
81122 +               if (pcf50606_voltage_set(pcf, reg_id, mvolts) < 0) {
81123 +                       dev_warn(dev, "refusing to set %s(%d) to %lu mvolts "
81124 +                                "(max=%u)\n", attr->attr.name, reg_id, mvolts,
81125 +                                pcf->pdata->rails[reg_id].voltage.max);
81126 +                       return -EINVAL;
81127 +               }
81128 +               pcf50606_onoff_set(pcf, reg_id, 1);
81129 +       }
81130 +
81131 +       return count;
81132 +}
81133 +
81134 +static DEVICE_ATTR(voltage_dcd, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81135 +static DEVICE_ATTR(voltage_dcde, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81136 +static DEVICE_ATTR(voltage_dcud, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81137 +static DEVICE_ATTR(voltage_d1reg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81138 +static DEVICE_ATTR(voltage_d2reg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81139 +static DEVICE_ATTR(voltage_d3reg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81140 +static DEVICE_ATTR(voltage_lpreg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81141 +static DEVICE_ATTR(voltage_ioreg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81142 +
81143 +/***********************************************************************
81144 + * Charger Control
81145 + ***********************************************************************/
81146 +
81147 +/* Enable/disable fast charging (500mA in the GTA01) */
81148 +void pcf50606_charge_fast(struct pcf50606_data *pcf, int on)
81149 +{
81150 +       if (!(pcf->pdata->used_features & PCF50606_FEAT_MBC))
81151 +               return;
81152 +
81153 +       if (on) {
81154 +               /* We can allow PCF to automatically charge
81155 +                * using Ifast */
81156 +               pcf->flags |= PCF50606_F_CHG_FAST;
81157 +               reg_set_bit_mask(pcf, PCF50606_REG_MBCC1,
81158 +                                PCF50606_MBCC1_AUTOFST,
81159 +                                PCF50606_MBCC1_AUTOFST);
81160 +       } else {
81161 +               pcf->flags &= ~PCF50606_F_CHG_FAST;
81162 +               /* disable automatic fast-charge */
81163 +               reg_clear_bits(pcf, PCF50606_REG_MBCC1,
81164 +                               PCF50606_MBCC1_AUTOFST);
81165 +               /* switch to idle mode to abort existing charge
81166 +                * process */
81167 +               reg_set_bit_mask(pcf, PCF50606_REG_MBCC1,
81168 +                                PCF50606_MBCC1_CHGMOD_MASK,
81169 +                                PCF50606_MBCC1_CHGMOD_IDLE);
81170 +       }
81171 +}
81172 +EXPORT_SYMBOL_GPL(pcf50606_charge_fast);
81173 +
81174 +static inline u_int16_t adc_to_rntc(struct pcf50606_data *pcf, u_int16_t adc)
81175 +{
81176 +       u_int32_t r_ntc = (adc * (u_int32_t)pcf->pdata->r_fix_batt)
81177 +               / (1023 - adc);
81178 +
81179 +       return r_ntc;
81180 +}
81181 +
81182 +static inline int16_t rntc_to_temp(u_int16_t rntc)
81183 +{
81184 +       int i;
81185 +
81186 +       for (i = 0; i < ARRAY_SIZE(ntc_table_10k_3370B); i++) {
81187 +               if (rntc > ntc_table_10k_3370B[i])
81188 +                       return i - 10;  /* First element is -10 */
81189 +       }
81190 +       return -99;     /* Below our range */
81191 +}
81192 +
81193 +static ssize_t show_battemp(struct device *dev, struct device_attribute *attr,
81194 +                           char *buf)
81195 +{
81196 +       struct i2c_client *client = to_i2c_client(dev);
81197 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81198 +       u_int16_t adc;
81199 +
81200 +       adc = adc_read(pcf, PCF50606_ADCMUX_BATTEMP, NULL);
81201 +
81202 +       return sprintf(buf, "%d\n", rntc_to_temp(adc_to_rntc(pcf, adc)));
81203 +}
81204 +static DEVICE_ATTR(battemp, S_IRUGO | S_IWUSR, show_battemp, NULL);
81205 +
81206 +static inline int16_t adc_to_chg_milliamps(struct pcf50606_data *pcf,
81207 +                                            u_int16_t adc_adcin1,
81208 +                                            u_int16_t adc_batvolt)
81209 +{
81210 +       int32_t res = (adc_adcin1 - adc_batvolt) * 2400;
81211 +       return (res * 1000) / (pcf->pdata->r_sense_milli * 1024);
81212 +}
81213 +
81214 +static ssize_t show_chgcur(struct device *dev, struct device_attribute *attr,
81215 +                          char *buf)
81216 +{
81217 +       struct i2c_client *client = to_i2c_client(dev);
81218 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81219 +       u_int16_t adc_batvolt, adc_adcin1;
81220 +       int16_t ma;
81221 +
81222 +       adc_batvolt = adc_read(pcf, PCF50606_ADCMUX_BATVOLT_ADCIN1,
81223 +                              &adc_adcin1);
81224 +       ma = adc_to_chg_milliamps(pcf, adc_adcin1, adc_batvolt);
81225 +
81226 +       return sprintf(buf, "%d\n", ma);
81227 +}
81228 +static DEVICE_ATTR(chgcur, S_IRUGO | S_IWUSR, show_chgcur, NULL);
81229 +
81230 +static const char *chgmode_names[] = {
81231 +       [PCF50606_MBCC1_CHGMOD_QUAL]            = "qualification",
81232 +       [PCF50606_MBCC1_CHGMOD_PRE]             = "pre",
81233 +       [PCF50606_MBCC1_CHGMOD_TRICKLE]         = "trickle",
81234 +       [PCF50606_MBCC1_CHGMOD_FAST_CCCV]       = "fast_cccv",
81235 +       [PCF50606_MBCC1_CHGMOD_FAST_NOCC]       = "fast_nocc",
81236 +       [PCF50606_MBCC1_CHGMOD_FAST_NOCV]       = "fast_nocv",
81237 +       [PCF50606_MBCC1_CHGMOD_FAST_SW]         = "fast_switch",
81238 +       [PCF50606_MBCC1_CHGMOD_IDLE]            = "idle",
81239 +};
81240 +
81241 +static ssize_t show_chgmode(struct device *dev, struct device_attribute *attr,
81242 +                           char *buf)
81243 +{
81244 +       struct i2c_client *client = to_i2c_client(dev);
81245 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81246 +       u_int8_t mbcc1 = reg_read(pcf, PCF50606_REG_MBCC1);
81247 +       u_int8_t chgmod = (mbcc1 & PCF50606_MBCC1_CHGMOD_MASK);
81248 +
81249 +       return sprintf(buf, "%s\n", chgmode_names[chgmod]);
81250 +}
81251 +
81252 +static ssize_t set_chgmode(struct device *dev, struct device_attribute *attr,
81253 +                          const char *buf, size_t count)
81254 +{
81255 +       struct i2c_client *client = to_i2c_client(dev);
81256 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81257 +       u_int8_t mbcc1 = reg_read(pcf, PCF50606_REG_MBCC1);
81258 +
81259 +       mbcc1 &= ~PCF50606_MBCC1_CHGMOD_MASK;
81260 +
81261 +       if (!strcmp(buf, "qualification"))
81262 +               mbcc1 |= PCF50606_MBCC1_CHGMOD_QUAL;
81263 +       else if (!strcmp(buf, "pre"))
81264 +               mbcc1 |= PCF50606_MBCC1_CHGMOD_PRE;
81265 +       else if (!strcmp(buf, "trickle"))
81266 +               mbcc1 |= PCF50606_MBCC1_CHGMOD_TRICKLE;
81267 +       else if (!strcmp(buf, "fast_cccv"))
81268 +               mbcc1 |= PCF50606_MBCC1_CHGMOD_FAST_CCCV;
81269 +       /* We don't allow the other fast modes for security reasons */
81270 +       else if (!strcmp(buf, "idle"))
81271 +               mbcc1 |= PCF50606_MBCC1_CHGMOD_IDLE;
81272 +       else
81273 +               return -EINVAL;
81274 +
81275 +       reg_write(pcf, PCF50606_REG_MBCC1, mbcc1);
81276 +
81277 +       return count;
81278 +}
81279 +
81280 +static DEVICE_ATTR(chgmode, S_IRUGO | S_IWUSR, show_chgmode, set_chgmode);
81281 +
81282 +static const char *chgstate_names[] = {
81283 +       [PCF50606_B_CHG_FAST]                   = "fast_enabled",
81284 +       [PCF50606_B_CHG_PRESENT]                = "present",
81285 +       [PCF50606_B_CHG_FOK]                    = "fast_ok",
81286 +       [PCF50606_B_CHG_ERR]                    = "error",
81287 +       [PCF50606_B_CHG_PROT]                   = "protection",
81288 +       [PCF50606_B_CHG_READY]                  = "ready",
81289 +};
81290 +
81291 +static ssize_t show_chgstate(struct device *dev, struct device_attribute *attr,
81292 +                           char *buf)
81293 +{
81294 +       struct i2c_client *client = to_i2c_client(dev);
81295 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81296 +       char *b = buf;
81297 +       int i;
81298 +
81299 +       for (i = 0; i < 32; i++)
81300 +               if (pcf->flags & (1 << i) && i < ARRAY_SIZE(chgstate_names))
81301 +                       b += sprintf(b, "%s ", chgstate_names[i]);
81302 +
81303 +       if (b > buf)
81304 +               b += sprintf(b, "\n");
81305 +
81306 +       return b - buf;
81307 +}
81308 +static DEVICE_ATTR(chgstate, S_IRUGO | S_IWUSR, show_chgstate, NULL);
81309 +
81310 +/***********************************************************************
81311 + * APM emulation
81312 + ***********************************************************************/
81313 +
81314 +static void pcf50606_get_power_status(struct apm_power_info *info)
81315 +{
81316 +       struct pcf50606_data *pcf = pcf50606_global;
81317 +       u_int8_t mbcc1 = reg_read(pcf, PCF50606_REG_MBCC1);
81318 +       u_int8_t chgmod = mbcc1 & PCF50606_MBCC1_CHGMOD_MASK;
81319 +       u_int16_t battvolt = pcf50606_battvolt(pcf);
81320 +
81321 +       if (reg_read(pcf, PCF50606_REG_OOCS) & PCF50606_OOCS_EXTON)
81322 +               info->ac_line_status = APM_AC_ONLINE;
81323 +       else
81324 +               info->ac_line_status = APM_AC_OFFLINE;
81325 +
81326 +       switch (chgmod) {
81327 +       case PCF50606_MBCC1_CHGMOD_QUAL:
81328 +       case PCF50606_MBCC1_CHGMOD_PRE:
81329 +       case PCF50606_MBCC1_CHGMOD_IDLE:
81330 +               info->battery_life = battvolt_scale(battvolt);
81331 +               break;
81332 +       default:
81333 +               info->battery_status = APM_BATTERY_STATUS_CHARGING;
81334 +               info->battery_flag = APM_BATTERY_FLAG_CHARGING;
81335 +               break;
81336 +       }
81337 +}
81338 +
81339 +/***********************************************************************
81340 + * RTC
81341 + ***********************************************************************/
81342 +
81343 +struct pcf50606_time {
81344 +       u_int8_t sec;
81345 +       u_int8_t min;
81346 +       u_int8_t hour;
81347 +       u_int8_t wkday;
81348 +       u_int8_t day;
81349 +       u_int8_t month;
81350 +       u_int8_t year;
81351 +};
81352 +
81353 +static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50606_time *pcf)
81354 +{
81355 +       rtc->tm_sec = bcd2bin(pcf->sec);
81356 +       rtc->tm_min = bcd2bin(pcf->min);
81357 +       rtc->tm_hour = bcd2bin(pcf->hour);
81358 +       rtc->tm_wday = bcd2bin(pcf->wkday);
81359 +       rtc->tm_mday = bcd2bin(pcf->day);
81360 +       rtc->tm_mon = bcd2bin(pcf->month);
81361 +       rtc->tm_year = bcd2bin(pcf->year) + 100;
81362 +}
81363 +
81364 +static void rtc2pcf_time(struct pcf50606_time *pcf, struct rtc_time *rtc)
81365 +{
81366 +       pcf->sec = bin2bcd(rtc->tm_sec);
81367 +       pcf->min = bin2bcd(rtc->tm_min);
81368 +       pcf->hour = bin2bcd(rtc->tm_hour);
81369 +       pcf->wkday = bin2bcd(rtc->tm_wday);
81370 +       pcf->day = bin2bcd(rtc->tm_mday);
81371 +       pcf->month = bin2bcd(rtc->tm_mon);
81372 +       pcf->year = bin2bcd(rtc->tm_year - 100);
81373 +}
81374 +
81375 +static int pcf50606_rtc_ioctl(struct device *dev, unsigned int cmd,
81376 +                             unsigned long arg)
81377 +{
81378 +       struct i2c_client *client = to_i2c_client(dev);
81379 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81380 +
81381 +       switch (cmd) {
81382 +       case RTC_AIE_OFF:
81383 +               /* disable the alarm interrupt */
81384 +               reg_set_bit_mask(pcf, PCF50606_REG_INT1M,
81385 +                                PCF50606_INT1_ALARM, PCF50606_INT1_ALARM);
81386 +               return 0;
81387 +       case RTC_AIE_ON:
81388 +               /* enable the alarm interrupt */
81389 +               reg_clear_bits(pcf, PCF50606_REG_INT1M, PCF50606_INT1_ALARM);
81390 +               return 0;
81391 +       case RTC_PIE_OFF:
81392 +               /* disable periodic interrupt (hz tick) */
81393 +               pcf->flags &= ~PCF50606_F_RTC_SECOND;
81394 +               reg_set_bit_mask(pcf, PCF50606_REG_INT1M,
81395 +                                PCF50606_INT1_SECOND, PCF50606_INT1_SECOND);
81396 +               return 0;
81397 +       case RTC_PIE_ON:
81398 +               /* ensable periodic interrupt (hz tick) */
81399 +               pcf->flags |= PCF50606_F_RTC_SECOND;
81400 +               reg_clear_bits(pcf, PCF50606_REG_INT1M, PCF50606_INT1_SECOND);
81401 +               return 0;
81402 +       }
81403 +       return -ENOIOCTLCMD;
81404 +}
81405 +
81406 +static int pcf50606_rtc_read_time(struct device *dev, struct rtc_time *tm)
81407 +{
81408 +       struct i2c_client *client = to_i2c_client(dev);
81409 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81410 +       struct pcf50606_time pcf_tm;
81411 +
81412 +       mutex_lock(&pcf->lock);
81413 +       pcf_tm.sec = __reg_read(pcf, PCF50606_REG_RTCSC);
81414 +       pcf_tm.min = __reg_read(pcf, PCF50606_REG_RTCMN);
81415 +       pcf_tm.hour = __reg_read(pcf, PCF50606_REG_RTCHR);
81416 +       pcf_tm.wkday = __reg_read(pcf, PCF50606_REG_RTCWD);
81417 +       pcf_tm.day = __reg_read(pcf, PCF50606_REG_RTCDT);
81418 +       pcf_tm.month = __reg_read(pcf, PCF50606_REG_RTCMT);
81419 +       pcf_tm.year = __reg_read(pcf, PCF50606_REG_RTCYR);
81420 +       mutex_unlock(&pcf->lock);
81421 +
81422 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
81423 +               pcf_tm.day, pcf_tm.month, pcf_tm.year,
81424 +               pcf_tm.hour, pcf_tm.min, pcf_tm.sec);
81425 +
81426 +       pcf2rtc_time(tm, &pcf_tm);
81427 +
81428 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
81429 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
81430 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
81431 +
81432 +       return 0;
81433 +}
81434 +
81435 +static int pcf50606_rtc_set_time(struct device *dev, struct rtc_time *tm)
81436 +{
81437 +       struct i2c_client *client = to_i2c_client(dev);
81438 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81439 +       struct pcf50606_time pcf_tm;
81440 +       u_int8_t int1m;
81441 +
81442 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
81443 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
81444 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
81445 +       rtc2pcf_time(&pcf_tm, tm);
81446 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
81447 +               pcf_tm.day, pcf_tm.month, pcf_tm.year,
81448 +               pcf_tm.hour, pcf_tm.min, pcf_tm.sec);
81449 +
81450 +       mutex_lock(&pcf->lock);
81451 +
81452 +       /* disable SECOND interrupt */
81453 +       int1m = __reg_read(pcf, PCF50606_REG_INT1M);
81454 +       __reg_write(pcf, PCF50606_REG_INT1M, int1m | PCF50606_INT1_SECOND);
81455 +
81456 +       __reg_write(pcf, PCF50606_REG_RTCSC, pcf_tm.sec);
81457 +       __reg_write(pcf, PCF50606_REG_RTCMN, pcf_tm.min);
81458 +       __reg_write(pcf, PCF50606_REG_RTCHR, pcf_tm.hour);
81459 +       __reg_write(pcf, PCF50606_REG_RTCWD, pcf_tm.wkday);
81460 +       __reg_write(pcf, PCF50606_REG_RTCDT, pcf_tm.day);
81461 +       __reg_write(pcf, PCF50606_REG_RTCMT, pcf_tm.month);
81462 +       __reg_write(pcf, PCF50606_REG_RTCYR, pcf_tm.year);
81463 +
81464 +       /* restore INT1M, potentially re-enable SECOND interrupt */
81465 +       __reg_write(pcf, PCF50606_REG_INT1M, int1m);
81466 +
81467 +       mutex_unlock(&pcf->lock);
81468 +
81469 +       return 0;
81470 +}
81471 +
81472 +static int pcf50606_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
81473 +{
81474 +       struct i2c_client *client = to_i2c_client(dev);
81475 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81476 +       struct pcf50606_time pcf_tm;
81477 +
81478 +       mutex_lock(&pcf->lock);
81479 +       alrm->enabled =
81480 +               __reg_read(pcf, PCF50606_REG_INT1M) & PCF50606_INT1_ALARM
81481 +               ? 0 : 1;
81482 +       pcf_tm.sec = __reg_read(pcf, PCF50606_REG_RTCSCA);
81483 +       pcf_tm.min = __reg_read(pcf, PCF50606_REG_RTCMNA);
81484 +       pcf_tm.hour = __reg_read(pcf, PCF50606_REG_RTCHRA);
81485 +       pcf_tm.wkday = __reg_read(pcf, PCF50606_REG_RTCWDA);
81486 +       pcf_tm.day = __reg_read(pcf, PCF50606_REG_RTCDTA);
81487 +       pcf_tm.month = __reg_read(pcf, PCF50606_REG_RTCMTA);
81488 +       pcf_tm.year = __reg_read(pcf, PCF50606_REG_RTCYRA);
81489 +       mutex_unlock(&pcf->lock);
81490 +
81491 +       pcf2rtc_time(&alrm->time, &pcf_tm);
81492 +
81493 +       return 0;
81494 +}
81495 +
81496 +static int pcf50606_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
81497 +{
81498 +       struct i2c_client *client = to_i2c_client(dev);
81499 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81500 +       struct pcf50606_time pcf_tm;
81501 +       u_int8_t irqmask;
81502 +
81503 +       rtc2pcf_time(&pcf_tm, &alrm->time);
81504 +
81505 +       mutex_lock(&pcf->lock);
81506 +
81507 +       /* disable alarm interrupt */
81508 +       irqmask = __reg_read(pcf, PCF50606_REG_INT1M);
81509 +       irqmask |= PCF50606_INT1_ALARM;
81510 +       __reg_write(pcf, PCF50606_REG_INT1M, irqmask);
81511 +
81512 +       __reg_write(pcf, PCF50606_REG_RTCSCA, pcf_tm.sec);
81513 +       __reg_write(pcf, PCF50606_REG_RTCMNA, pcf_tm.min);
81514 +       __reg_write(pcf, PCF50606_REG_RTCHRA, pcf_tm.hour);
81515 +       __reg_write(pcf, PCF50606_REG_RTCWDA, pcf_tm.wkday);
81516 +       __reg_write(pcf, PCF50606_REG_RTCDTA, pcf_tm.day);
81517 +       __reg_write(pcf, PCF50606_REG_RTCMTA, pcf_tm.month);
81518 +       __reg_write(pcf, PCF50606_REG_RTCYRA, pcf_tm.year);
81519 +
81520 +       if (alrm->enabled) {
81521 +               /* (re-)enaable alarm interrupt */
81522 +               irqmask = __reg_read(pcf, PCF50606_REG_INT1M);
81523 +               irqmask &= ~PCF50606_INT1_ALARM;
81524 +               __reg_write(pcf, PCF50606_REG_INT1M, irqmask);
81525 +       }
81526 +
81527 +       mutex_unlock(&pcf->lock);
81528 +
81529 +       /* FIXME */
81530 +       return 0;
81531 +}
81532 +
81533 +static struct rtc_class_ops pcf50606_rtc_ops = {
81534 +       .ioctl          = pcf50606_rtc_ioctl,
81535 +       .read_time      = pcf50606_rtc_read_time,
81536 +       .set_time       = pcf50606_rtc_set_time,
81537 +       .read_alarm     = pcf50606_rtc_read_alarm,
81538 +       .set_alarm      = pcf50606_rtc_set_alarm,
81539 +};
81540 +
81541 +/***********************************************************************
81542 + * Watchdog
81543 + ***********************************************************************/
81544 +
81545 +static void pcf50606_wdt_start(struct pcf50606_data *pcf)
81546 +{
81547 +       reg_set_bit_mask(pcf, PCF50606_REG_OOCC1, PCF50606_OOCC1_WDTRST,
81548 +                        PCF50606_OOCC1_WDTRST);
81549 +}
81550 +
81551 +static void pcf50606_wdt_stop(struct pcf50606_data *pcf)
81552 +{
81553 +       reg_clear_bits(pcf, PCF50606_REG_OOCS, PCF50606_OOCS_WDTEXP);
81554 +}
81555 +
81556 +static void pcf50606_wdt_keepalive(struct pcf50606_data *pcf)
81557 +{
81558 +       pcf50606_wdt_start(pcf);
81559 +}
81560 +
81561 +static int pcf50606_wdt_open(struct inode *inode, struct file *file)
81562 +{
81563 +       struct pcf50606_data *pcf = pcf50606_global;
81564 +
81565 +       file->private_data = pcf;
81566 +
81567 +       /* start the timer */
81568 +       pcf50606_wdt_start(pcf);
81569 +
81570 +       return nonseekable_open(inode, file);
81571 +}
81572 +
81573 +static int pcf50606_wdt_release(struct inode *inode, struct file *file)
81574 +{
81575 +       struct pcf50606_data *pcf = file->private_data;
81576 +
81577 +       if (pcf->allow_close == CLOSE_STATE_ALLOW)
81578 +               pcf50606_wdt_stop(pcf);
81579 +       else {
81580 +               printk(KERN_CRIT "Unexpected close, not stopping watchdog!\n");
81581 +               pcf50606_wdt_keepalive(pcf);
81582 +       }
81583 +
81584 +       pcf->allow_close = CLOSE_STATE_NOT;
81585 +
81586 +       return 0;
81587 +}
81588 +
81589 +static ssize_t pcf50606_wdt_write(struct file *file, const char __user *data,
81590 +                                 size_t len, loff_t *ppos)
81591 +{
81592 +       struct pcf50606_data *pcf = file->private_data;
81593 +       if (len) {
81594 +               size_t i;
81595 +
81596 +               for (i = 0; i != len; i++) {
81597 +                       char c;
81598 +                       if (get_user(c, data + i))
81599 +                               return -EFAULT;
81600 +                       if (c == 'V')
81601 +                               pcf->allow_close = CLOSE_STATE_ALLOW;
81602 +               }
81603 +               pcf50606_wdt_keepalive(pcf);
81604 +       }
81605 +
81606 +       return len;
81607 +}
81608 +
81609 +static struct watchdog_info pcf50606_wdt_ident = {
81610 +       .options        = WDIOF_MAGICCLOSE,
81611 +       .firmware_version = 0,
81612 +       .identity       = "PCF50606 Watchdog",
81613 +};
81614 +
81615 +static int pcf50606_wdt_ioctl(struct inode *inode, struct file *file,
81616 +                             unsigned int cmd, unsigned long arg)
81617 +{
81618 +       struct pcf50606_data *pcf = file->private_data;
81619 +       void __user *argp = (void __user *)arg;
81620 +       int __user *p = argp;
81621 +
81622 +       switch (cmd) {
81623 +       case WDIOC_GETSUPPORT:
81624 +               return copy_to_user(argp, &pcf50606_wdt_ident,
81625 +                                   sizeof(pcf50606_wdt_ident)) ? -EFAULT : 0;
81626 +               break;
81627 +       case WDIOC_GETSTATUS:
81628 +       case WDIOC_GETBOOTSTATUS:
81629 +               return put_user(0, p);
81630 +       case WDIOC_KEEPALIVE:
81631 +               pcf50606_wdt_keepalive(pcf);
81632 +               return 0;
81633 +       case WDIOC_GETTIMEOUT:
81634 +               return put_user(8, p);
81635 +       default:
81636 +               return -ENOIOCTLCMD;
81637 +       }
81638 +}
81639 +
81640 +static struct file_operations pcf50606_wdt_fops = {
81641 +       .owner          = THIS_MODULE,
81642 +       .llseek         = no_llseek,
81643 +       .write          = &pcf50606_wdt_write,
81644 +       .ioctl          = &pcf50606_wdt_ioctl,
81645 +       .open           = &pcf50606_wdt_open,
81646 +       .release        = &pcf50606_wdt_release,
81647 +};
81648 +
81649 +static struct miscdevice pcf50606_wdt_miscdev = {
81650 +       .minor          = WATCHDOG_MINOR,
81651 +       .name           = "watchdog",
81652 +       .fops           = &pcf50606_wdt_fops,
81653 +};
81654 +
81655 +/***********************************************************************
81656 + * PWM
81657 + ***********************************************************************/
81658 +
81659 +static const char *pwm_dc_table[] = {
81660 +       "0/16", "1/16", "2/16", "3/16",
81661 +       "4/16", "5/16", "6/16", "7/16",
81662 +       "8/16", "9/16", "10/16", "11/16",
81663 +       "12/16", "13/16", "14/16", "15/16",
81664 +};
81665 +
81666 +static ssize_t show_pwm_dc(struct device *dev, struct device_attribute *attr,
81667 +                          char *buf)
81668 +{
81669 +       struct i2c_client *client = to_i2c_client(dev);
81670 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81671 +       u_int8_t val;
81672 +
81673 +       val = reg_read(pcf, PCF50606_REG_PWMC1) >> PCF50606_PWMC1_DC_SHIFT;
81674 +       val &= 0xf;
81675 +
81676 +       return sprintf(buf, "%s\n", pwm_dc_table[val]);
81677 +}
81678 +
81679 +static ssize_t set_pwm_dc(struct device *dev, struct device_attribute *attr,
81680 +                         const char *buf, size_t count)
81681 +{
81682 +       struct i2c_client *client = to_i2c_client(dev);
81683 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81684 +       u_int8_t i;
81685 +
81686 +       for (i = 0; i < ARRAY_SIZE(pwm_dc_table); i++) {
81687 +               if (!strncmp(buf, pwm_dc_table[i], strlen(pwm_dc_table[i]))) {
81688 +                       dev_dbg(dev, "setting pwm dc %s\n\r", pwm_dc_table[i]);
81689 +                       reg_set_bit_mask(pcf, PCF50606_REG_PWMC1, 0x1e,
81690 +                                        (i << PCF50606_PWMC1_DC_SHIFT));
81691 +               }
81692 +       }
81693 +       return count;
81694 +}
81695 +
81696 +static DEVICE_ATTR(pwm_dc, S_IRUGO | S_IWUSR, show_pwm_dc, set_pwm_dc);
81697 +
81698 +static const char *pwm_clk_table[] = {
81699 +       "512", "256", "128", "64",
81700 +       "56300", "28100", "14100", "7000",
81701 +};
81702 +
81703 +static ssize_t show_pwm_clk(struct device *dev, struct device_attribute *attr,
81704 +                           char *buf)
81705 +{
81706 +       struct i2c_client *client = to_i2c_client(dev);
81707 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81708 +       u_int8_t val;
81709 +
81710 +       val = reg_read(pcf, PCF50606_REG_PWMC1) >> PCF50606_PWMC1_CLK_SHIFT;
81711 +       val &= 0x7;
81712 +
81713 +       return sprintf(buf, "%s\n", pwm_clk_table[val]);
81714 +}
81715 +
81716 +static ssize_t set_pwm_clk(struct device *dev, struct device_attribute *attr,
81717 +                          const char *buf, size_t count)
81718 +{
81719 +       struct i2c_client *client = to_i2c_client(dev);
81720 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81721 +       u_int8_t i;
81722 +
81723 +       for (i = 0; i < ARRAY_SIZE(pwm_clk_table); i++) {
81724 +               if (!strncmp(buf, pwm_clk_table[i], strlen(pwm_clk_table[i]))) {
81725 +                       dev_dbg(dev, "setting pwm clk %s\n\r",
81726 +                               pwm_clk_table[i]);
81727 +                       reg_set_bit_mask(pcf, PCF50606_REG_PWMC1, 0xe0,
81728 +                                        (i << PCF50606_PWMC1_CLK_SHIFT));
81729 +               }
81730 +       }
81731 +       return count;
81732 +}
81733 +
81734 +static DEVICE_ATTR(pwm_clk, S_IRUGO | S_IWUSR, show_pwm_clk, set_pwm_clk);
81735 +
81736 +static int pcf50606bl_get_intensity(struct backlight_device *bd)
81737 +{
81738 +       struct pcf50606_data *pcf = bl_get_data(bd);
81739 +       int intensity = reg_read(pcf, PCF50606_REG_PWMC1);
81740 +       intensity = (intensity >> PCF50606_PWMC1_DC_SHIFT);
81741 +
81742 +       return intensity & 0xf;
81743 +}
81744 +
81745 +static int pcf50606bl_set_intensity(struct backlight_device *bd)
81746 +{
81747 +       struct pcf50606_data *pcf = bl_get_data(bd);
81748 +       int intensity = bd->props.brightness;
81749 +
81750 +       if (bd->props.power != FB_BLANK_UNBLANK)
81751 +               intensity = 0;
81752 +       if (bd->props.fb_blank != FB_BLANK_UNBLANK)
81753 +               intensity = 0;
81754 +
81755 +       return reg_set_bit_mask(pcf, PCF50606_REG_PWMC1, 0x1e,
81756 +                               (intensity << PCF50606_PWMC1_DC_SHIFT));
81757 +}
81758 +
81759 +static struct backlight_ops pcf50606bl_ops = {
81760 +       .get_brightness = pcf50606bl_get_intensity,
81761 +       .update_status  = pcf50606bl_set_intensity,
81762 +};
81763 +
81764 +/***********************************************************************
81765 + * Driver initialization
81766 + ***********************************************************************/
81767 +
81768 +#ifdef CONFIG_MACH_NEO1973_GTA01
81769 +/* We currently place those platform devices here to make sure the device
81770 + * suspend/resume order is correct */
81771 +static struct platform_device gta01_pm_gps_dev = {
81772 +       .name           = "neo1973-pm-gps",
81773 +};
81774 +
81775 +static struct platform_device gta01_pm_bt_dev = {
81776 +       .name           = "neo1973-pm-bt",
81777 +};
81778 +#endif
81779 +
81780 +static struct attribute *pcf_sysfs_entries[16] = {
81781 +       &dev_attr_voltage_dcd.attr,
81782 +       &dev_attr_voltage_dcde.attr,
81783 +       &dev_attr_voltage_dcud.attr,
81784 +       &dev_attr_voltage_d1reg.attr,
81785 +       &dev_attr_voltage_d2reg.attr,
81786 +       &dev_attr_voltage_d3reg.attr,
81787 +       &dev_attr_voltage_lpreg.attr,
81788 +       &dev_attr_voltage_ioreg.attr,
81789 +       NULL
81790 +};
81791 +
81792 +static struct attribute_group pcf_attr_group = {
81793 +       .name   = NULL,                 /* put in device directory */
81794 +       .attrs  = pcf_sysfs_entries,
81795 +};
81796 +
81797 +static void populate_sysfs_group(struct pcf50606_data *pcf)
81798 +{
81799 +       int i = 0;
81800 +       struct attribute **attr;
81801 +
81802 +       for (attr = pcf_sysfs_entries; *attr; attr++)
81803 +               i++;
81804 +
81805 +       if (pcf->pdata->used_features & PCF50606_FEAT_MBC) {
81806 +               pcf_sysfs_entries[i++] = &dev_attr_chgstate.attr;
81807 +               pcf_sysfs_entries[i++] = &dev_attr_chgmode.attr;
81808 +       }
81809 +
81810 +       if (pcf->pdata->used_features & PCF50606_FEAT_CHGCUR)
81811 +               pcf_sysfs_entries[i++] = &dev_attr_chgcur.attr;
81812 +
81813 +       if (pcf->pdata->used_features & PCF50606_FEAT_BATVOLT)
81814 +               pcf_sysfs_entries[i++] = &dev_attr_battvolt.attr;
81815 +
81816 +       if (pcf->pdata->used_features & PCF50606_FEAT_BATTEMP)
81817 +               pcf_sysfs_entries[i++] = &dev_attr_battemp.attr;
81818 +
81819 +       if (pcf->pdata->used_features & PCF50606_FEAT_PWM) {
81820 +               pcf_sysfs_entries[i++] = &dev_attr_pwm_dc.attr;
81821 +               pcf_sysfs_entries[i++] = &dev_attr_pwm_clk.attr;
81822 +       }
81823 +}
81824 +
81825 +static int pcf50606_detect(struct i2c_adapter *adapter, int address, int kind)
81826 +{
81827 +       struct i2c_client *new_client;
81828 +       struct pcf50606_data *data;
81829 +       int err = 0;
81830 +       int irq;
81831 +
81832 +       if (!pcf50606_pdev) {
81833 +               printk(KERN_ERR "pcf50606: driver needs a platform_device!\n");
81834 +               return -EIO;
81835 +       }
81836 +
81837 +       irq = platform_get_irq(pcf50606_pdev, 0);
81838 +       if (irq < 0) {
81839 +               dev_err(&pcf50606_pdev->dev, "no irq in platform resources!\n");
81840 +               return -EIO;
81841 +       }
81842 +
81843 +       /* At the moment, we only support one PCF50606 in a system */
81844 +       if (pcf50606_global) {
81845 +               dev_err(&pcf50606_pdev->dev,
81846 +                       "currently only one chip supported\n");
81847 +               return -EBUSY;
81848 +       }
81849 +
81850 +       data = kzalloc(sizeof(*data), GFP_KERNEL);
81851 +       if (!data)
81852 +               return -ENOMEM;
81853 +
81854 +       mutex_init(&data->lock);
81855 +       mutex_init(&data->working_lock);
81856 +       INIT_WORK(&data->work, pcf50606_work);
81857 +       data->irq = irq;
81858 +       data->working = 0;
81859 +       data->suppress_onkey_events = 0;
81860 +       data->onkey_seconds = -1;
81861 +       data->pdata = pcf50606_pdev->dev.platform_data;
81862 +
81863 +       new_client = &data->client;
81864 +       i2c_set_clientdata(new_client, data);
81865 +       new_client->addr = address;
81866 +       new_client->adapter = adapter;
81867 +       new_client->driver = &pcf50606_driver;
81868 +       new_client->flags = 0;
81869 +       strlcpy(new_client->name, "pcf50606", I2C_NAME_SIZE);
81870 +
81871 +       /* now we try to detect the chip */
81872 +
81873 +       /* register with i2c core */
81874 +       err = i2c_attach_client(new_client);
81875 +       if (err) {
81876 +               dev_err(&new_client->dev,
81877 +                       "error during i2c_attach_client()\n");
81878 +               goto exit_free;
81879 +       }
81880 +
81881 +       populate_sysfs_group(data);
81882 +
81883 +       err = sysfs_create_group(&new_client->dev.kobj, &pcf_attr_group);
81884 +       if (err) {
81885 +               dev_err(&new_client->dev, "error creating sysfs group\n");
81886 +               goto exit_detach;
81887 +       }
81888 +
81889 +       /* create virtual charger 'device' */
81890 +
81891 +       /* input device registration */
81892 +       data->input_dev = input_allocate_device();
81893 +       if (!data->input_dev)
81894 +               goto exit_sysfs;
81895 +
81896 +       data->input_dev->name = "FIC Neo1973 PMU events";
81897 +       data->input_dev->phys = "I2C";
81898 +       data->input_dev->id.bustype = BUS_I2C;
81899 +
81900 +       data->input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
81901 +       set_bit(KEY_POWER, data->input_dev->keybit);
81902 +       set_bit(KEY_POWER2, data->input_dev->keybit);
81903 +       set_bit(KEY_BATTERY, data->input_dev->keybit);
81904 +
81905 +       err = input_register_device(data->input_dev);
81906 +       if (err)
81907 +               goto exit_sysfs;
81908 +
81909 +       /* register power off handler with core power management */
81910 +       pm_power_off = &pcf50606_go_standby;
81911 +
81912 +       /* configure interrupt mask */
81913 +       /* we don't mask SECOND here, because we want one to do coldplug with */
81914 +       reg_write(data, PCF50606_REG_INT1M, 0x00);
81915 +       reg_write(data, PCF50606_REG_INT2M, 0x00);
81916 +       reg_write(data, PCF50606_REG_INT3M, PCF50606_INT3_TSCPRES);
81917 +
81918 +       err = request_irq(irq, pcf50606_irq, IRQF_TRIGGER_FALLING,
81919 +                         "pcf50606", data);
81920 +       if (err < 0)
81921 +               goto exit_input;
81922 +
81923 +       if (enable_irq_wake(irq) < 0)
81924 +               dev_err(&new_client->dev, "IRQ %u cannot be enabled as wake-up"
81925 +                       "source in this hardware revision!", irq);
81926 +
81927 +       pcf50606_global = data;
81928 +
81929 +       if (data->pdata->used_features & PCF50606_FEAT_RTC) {
81930 +               data->rtc = rtc_device_register("pcf50606", &new_client->dev,
81931 +                                               &pcf50606_rtc_ops, THIS_MODULE);
81932 +               if (IS_ERR(data->rtc)) {
81933 +                       err = PTR_ERR(data->rtc);
81934 +                       goto exit_irq;
81935 +               }
81936 +       }
81937 +
81938 +       if (data->pdata->used_features & PCF50606_FEAT_WDT) {
81939 +               err = misc_register(&pcf50606_wdt_miscdev);
81940 +               if (err) {
81941 +                       dev_err(&new_client->dev, "cannot register miscdev on "
81942 +                              "minor=%d (%d)\n", WATCHDOG_MINOR, err);
81943 +                       goto exit_rtc;
81944 +               }
81945 +       }
81946 +
81947 +       if (data->pdata->used_features & PCF50606_FEAT_PWM) {
81948 +               /* enable PWM controller */
81949 +               reg_set_bit_mask(data, PCF50606_REG_PWMC1,
81950 +                                PCF50606_PWMC1_ACTSET,
81951 +                                PCF50606_PWMC1_ACTSET);
81952 +       }
81953 +
81954 +       if (data->pdata->used_features & PCF50606_FEAT_PWM_BL) {
81955 +               data->backlight = backlight_device_register("pcf50606-bl",
81956 +                                                           &new_client->dev,
81957 +                                                           data,
81958 +                                                           &pcf50606bl_ops);
81959 +               if (!data->backlight)
81960 +                       goto exit_misc;
81961 +               data->backlight->props.max_brightness = 16;
81962 +               data->backlight->props.power = FB_BLANK_UNBLANK;
81963 +               data->backlight->props.brightness =
81964 +                                       data->pdata->init_brightness;
81965 +               backlight_update_status(data->backlight);
81966 +       }
81967 +
81968 +       apm_get_power_status = pcf50606_get_power_status;
81969 +
81970 +#ifdef CONFIG_MACH_NEO1973_GTA01
81971 +       if (machine_is_neo1973_gta01()) {
81972 +               gta01_pm_gps_dev.dev.parent = &new_client->dev;
81973 +               switch (system_rev) {
81974 +               case GTA01Bv2_SYSTEM_REV:
81975 +               case GTA01Bv3_SYSTEM_REV:
81976 +               case GTA01Bv4_SYSTEM_REV:
81977 +                       gta01_pm_bt_dev.dev.parent = &new_client->dev;
81978 +                       platform_device_register(&gta01_pm_bt_dev);
81979 +                       break;
81980 +               }
81981 +               platform_device_register(&gta01_pm_gps_dev);
81982 +               /* a link for gllin compatibility */
81983 +               err = bus_create_device_link(&platform_bus_type,
81984 +                       &gta01_pm_gps_dev.dev.kobj, "gta01-pm-gps.0");
81985 +               if (err)
81986 +                       printk(KERN_ERR
81987 +                           "sysfs_create_link (gta01-pm-gps.0): %d\n", err);
81988 +       }
81989 +#endif
81990 +
81991 +       if (data->pdata->used_features & PCF50606_FEAT_ACD)
81992 +               reg_set_bit_mask(data, PCF50606_REG_ACDC1,
81993 +                                PCF50606_ACDC1_ACDAPE, PCF50606_ACDC1_ACDAPE);
81994 +       else
81995 +               reg_clear_bits(data, PCF50606_REG_ACDC1,
81996 +                              PCF50606_ACDC1_ACDAPE);
81997 +
81998 +       return 0;
81999 +
82000 +exit_misc:
82001 +       if (data->pdata->used_features & PCF50606_FEAT_WDT)
82002 +               misc_deregister(&pcf50606_wdt_miscdev);
82003 +exit_rtc:
82004 +       if (data->pdata->used_features & PCF50606_FEAT_RTC)
82005 +               rtc_device_unregister(pcf50606_global->rtc);
82006 +exit_irq:
82007 +       free_irq(pcf50606_global->irq, pcf50606_global);
82008 +       pcf50606_global = NULL;
82009 +exit_input:
82010 +       pm_power_off = NULL;
82011 +       input_unregister_device(data->input_dev);
82012 +exit_sysfs:
82013 +       sysfs_remove_group(&new_client->dev.kobj, &pcf_attr_group);
82014 +exit_detach:
82015 +       i2c_detach_client(new_client);
82016 +exit_free:
82017 +       kfree(data);
82018 +       return err;
82019 +}
82020 +
82021 +static int pcf50606_attach_adapter(struct i2c_adapter *adapter)
82022 +{
82023 +       return i2c_probe(adapter, &addr_data, &pcf50606_detect);
82024 +}
82025 +
82026 +static int pcf50606_detach_client(struct i2c_client *client)
82027 +{
82028 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82029 +
82030 +       apm_get_power_status = NULL;
82031 +       input_unregister_device(pcf->input_dev);
82032 +
82033 +       if (pcf->pdata->used_features & PCF50606_FEAT_PWM_BL)
82034 +               backlight_device_unregister(pcf->backlight);
82035 +
82036 +       if (pcf->pdata->used_features & PCF50606_FEAT_WDT)
82037 +               misc_deregister(&pcf50606_wdt_miscdev);
82038 +
82039 +       if (pcf->pdata->used_features & PCF50606_FEAT_RTC)
82040 +               rtc_device_unregister(pcf->rtc);
82041 +
82042 +       free_irq(pcf->irq, pcf);
82043 +
82044 +       sysfs_remove_group(&client->dev.kobj, &pcf_attr_group);
82045 +
82046 +       pm_power_off = NULL;
82047 +
82048 +       kfree(pcf);
82049 +
82050 +       return 0;
82051 +}
82052 +
82053 +#ifdef CONFIG_PM
82054 +#define INT1M_RESUMERS (PCF50606_INT1_ALARM | \
82055 +                        PCF50606_INT1_ONKEYF | \
82056 +                        PCF50606_INT1_EXTONR)
82057 +#define INT2M_RESUMERS (PCF50606_INT2_CHGWD10S | \
82058 +                        PCF50606_INT2_CHGPROT | \
82059 +                        PCF50606_INT2_CHGERR)
82060 +#define INT3M_RESUMERS (PCF50606_INT3_LOWBAT | \
82061 +                        PCF50606_INT3_HIGHTMP | \
82062 +                        PCF50606_INT3_ACDINS)
82063 +static int pcf50606_suspend(struct device *dev, pm_message_t state)
82064 +{
82065 +       struct i2c_client *client = to_i2c_client(dev);
82066 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82067 +       int i;
82068 +
82069 +       /* we suspend once (!) as late as possible in the suspend sequencing */
82070 +
82071 +       if ((state.event != PM_EVENT_SUSPEND) ||
82072 +           (pcf->suspend_state != PCF50606_SS_RUNNING))
82073 +               return -EBUSY;
82074 +
82075 +       /* The general idea is to power down all unused power supplies,
82076 +        * and then mask all PCF50606 interrup sources but EXTONR, ONKEYF
82077 +        * and ALARM */
82078 +
82079 +       mutex_lock(&pcf->lock);
82080 +
82081 +       pcf->suspend_state = PCF50606_SS_STARTING_SUSPEND;
82082 +
82083 +       /* we are not going to service any further interrupts until we
82084 +        * resume.  If the IRQ workqueue is still pending in the background,
82085 +        * it will bail when it sees we set suspend state above.
82086 +        */
82087 +
82088 +       disable_irq(pcf->irq);
82089 +
82090 +       /* Save all registers that don't "survive" standby state */
82091 +       pcf->standby_regs.dcdc1 = __reg_read(pcf, PCF50606_REG_DCDC1);
82092 +       pcf->standby_regs.dcdc2 = __reg_read(pcf, PCF50606_REG_DCDC2);
82093 +       pcf->standby_regs.dcdec1 = __reg_read(pcf, PCF50606_REG_DCDEC1);
82094 +       pcf->standby_regs.dcudc1 = __reg_read(pcf, PCF50606_REG_DCUDC1);
82095 +       pcf->standby_regs.ioregc = __reg_read(pcf, PCF50606_REG_IOREGC);
82096 +       pcf->standby_regs.d1regc1 = __reg_read(pcf, PCF50606_REG_D1REGC1);
82097 +       pcf->standby_regs.d2regc1 = __reg_read(pcf, PCF50606_REG_D2REGC1);
82098 +       pcf->standby_regs.d3regc1 = __reg_read(pcf, PCF50606_REG_D3REGC1);
82099 +       pcf->standby_regs.lpregc1 = __reg_read(pcf, PCF50606_REG_LPREGC1);
82100 +       pcf->standby_regs.adcc1 = __reg_read(pcf, PCF50606_REG_ADCC1);
82101 +       pcf->standby_regs.adcc2 = __reg_read(pcf, PCF50606_REG_ADCC2);
82102 +       pcf->standby_regs.pwmc1 = __reg_read(pcf, PCF50606_REG_PWMC1);
82103 +
82104 +       /* switch off power supplies that are not needed during suspend */
82105 +       for (i = 0; i < __NUM_PCF50606_REGULATORS; i++) {
82106 +               if (!(pcf->pdata->rails[i].flags & PMU_VRAIL_F_SUSPEND_ON)) {
82107 +                       u_int8_t tmp;
82108 +
82109 +                       /* IOREG powers the I@C interface so we cannot switch
82110 +                        * it off */
82111 +                       if (i == PCF50606_REGULATOR_IOREG)
82112 +                               continue;
82113 +
82114 +                       dev_dbg(dev, "disabling pcf50606 regulator %u\n", i);
82115 +                       /* we cannot use pcf50606_onoff_set() because we're
82116 +                        * already under the mutex */
82117 +                       tmp = __reg_read(pcf, regulator_registers[i]);
82118 +                       tmp &= 0x1f;
82119 +                       __reg_write(pcf, regulator_registers[i], tmp);
82120 +               }
82121 +       }
82122 +
82123 +       pcf->standby_regs.int1m = __reg_read(pcf, PCF50606_REG_INT1M);
82124 +       pcf->standby_regs.int2m = __reg_read(pcf, PCF50606_REG_INT2M);
82125 +       pcf->standby_regs.int3m = __reg_read(pcf, PCF50606_REG_INT3M);
82126 +       __reg_write(pcf, PCF50606_REG_INT1M, ~INT1M_RESUMERS & 0xff);
82127 +       __reg_write(pcf, PCF50606_REG_INT2M, ~INT2M_RESUMERS & 0xff);
82128 +       __reg_write(pcf, PCF50606_REG_INT3M, ~INT3M_RESUMERS & 0xff);
82129 +
82130 +       pcf->suspend_state = PCF50606_SS_COMPLETED_SUSPEND;
82131 +
82132 +       mutex_unlock(&pcf->lock);
82133 +
82134 +       return 0;
82135 +}
82136 +
82137 +static int pcf50606_resume(struct device *dev)
82138 +{
82139 +       struct i2c_client *client = to_i2c_client(dev);
82140 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82141 +
82142 +       mutex_lock(&pcf->lock);
82143 +
82144 +       pcf->suspend_state = PCF50606_SS_STARTING_RESUME;
82145 +
82146 +       /* Resume all saved registers that don't "survive" standby state */
82147 +       __reg_write(pcf, PCF50606_REG_INT1M, pcf->standby_regs.int1m);
82148 +       __reg_write(pcf, PCF50606_REG_INT2M, pcf->standby_regs.int2m);
82149 +       __reg_write(pcf, PCF50606_REG_INT3M, pcf->standby_regs.int3m);
82150 +
82151 +       __reg_write(pcf, PCF50606_REG_DCDC1, pcf->standby_regs.dcdc1);
82152 +       __reg_write(pcf, PCF50606_REG_DCDC2, pcf->standby_regs.dcdc2);
82153 +       __reg_write(pcf, PCF50606_REG_DCDEC1, pcf->standby_regs.dcdec1);
82154 +       __reg_write(pcf, PCF50606_REG_DCUDC1, pcf->standby_regs.dcudc1);
82155 +       __reg_write(pcf, PCF50606_REG_IOREGC, pcf->standby_regs.ioregc);
82156 +       __reg_write(pcf, PCF50606_REG_D1REGC1, pcf->standby_regs.d1regc1);
82157 +       __reg_write(pcf, PCF50606_REG_D2REGC1, pcf->standby_regs.d2regc1);
82158 +       __reg_write(pcf, PCF50606_REG_D3REGC1, pcf->standby_regs.d3regc1);
82159 +       __reg_write(pcf, PCF50606_REG_LPREGC1, pcf->standby_regs.lpregc1);
82160 +       __reg_write(pcf, PCF50606_REG_ADCC1, pcf->standby_regs.adcc1);
82161 +       __reg_write(pcf, PCF50606_REG_ADCC2, pcf->standby_regs.adcc2);
82162 +       __reg_write(pcf, PCF50606_REG_PWMC1, pcf->standby_regs.pwmc1);
82163 +
82164 +       pcf->suspend_state = PCF50606_SS_COMPLETED_RESUME;
82165 +
82166 +       enable_irq(pcf->irq);
82167 +
82168 +       mutex_unlock(&pcf->lock);
82169 +
82170 +       /* Call PCF work function; this fixes an issue on the gta01 where
82171 +        * the power button "goes away" if it is used to wake the device.
82172 +        */
82173 +       get_device(&pcf->client.dev);
82174 +       pcf50606_work(&pcf->work);
82175 +
82176 +       return 0;
82177 +}
82178 +#else
82179 +#define pcf50606_suspend NULL
82180 +#define pcf50606_resume NULL
82181 +#endif
82182 +
82183 +static struct i2c_driver pcf50606_driver = {
82184 +       .driver = {
82185 +               .name    = "pcf50606",
82186 +               .suspend = pcf50606_suspend,
82187 +               .resume  = pcf50606_resume,
82188 +       },
82189 +       .id             = I2C_DRIVERID_PCF50606,
82190 +       .attach_adapter = pcf50606_attach_adapter,
82191 +       .detach_client  = pcf50606_detach_client,
82192 +};
82193 +
82194 +/* platform driver, since i2c devices don't have platform_data */
82195 +static int __init pcf50606_plat_probe(struct platform_device *pdev)
82196 +{
82197 +       struct pcf50606_platform_data *pdata = pdev->dev.platform_data;
82198 +
82199 +       if (!pdata)
82200 +               return -ENODEV;
82201 +
82202 +       pcf50606_pdev = pdev;
82203 +
82204 +       return 0;
82205 +}
82206 +
82207 +static int pcf50606_plat_remove(struct platform_device *pdev)
82208 +{
82209 +       return 0;
82210 +}
82211 +
82212 +/* We have this purely to capture an early indication that we are coming out
82213 + * of suspend, before our device resume got called; async interrupt service is
82214 + * interested in this.
82215 + */
82216 +
82217 +static int pcf50606_plat_resume(struct platform_device *pdev)
82218 +{
82219 +       /* i2c_get_clientdata(to_i2c_client(&pdev->dev)) returns NULL at this
82220 +        * early resume time so we have to use pcf50606_global
82221 +        */
82222 +       pcf50606_global->suspend_state = PCF50606_SS_RESUMING_BUT_NOT_US_YET;
82223 +
82224 +       return 0;
82225 +}
82226 +
82227 +static struct platform_driver pcf50606_plat_driver = {
82228 +       .probe  = pcf50606_plat_probe,
82229 +       .remove = pcf50606_plat_remove,
82230 +       .resume_early = pcf50606_plat_resume,
82231 +       .driver = {
82232 +               .owner  = THIS_MODULE,
82233 +               .name   = "pcf50606",
82234 +       },
82235 +};
82236 +
82237 +static int __init pcf50606_init(void)
82238 +{
82239 +       int rc;
82240 +
82241 +       rc = platform_driver_register(&pcf50606_plat_driver);
82242 +       if (!rc)
82243 +               rc = i2c_add_driver(&pcf50606_driver);
82244 +
82245 +       return rc;
82246 +}
82247 +
82248 +static void pcf50606_exit(void)
82249 +{
82250 +       i2c_del_driver(&pcf50606_driver);
82251 +       platform_driver_unregister(&pcf50606_plat_driver);
82252 +}
82253 +
82254 +MODULE_DESCRIPTION("I2C chip driver for NXP PCF50606 power management unit");
82255 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
82256 +MODULE_LICENSE("GPL");
82257 +
82258 +module_init(pcf50606_init);
82259 +module_exit(pcf50606_exit);
82260 --- /dev/null
82261 +++ b/drivers/i2c/chips/pcf50606.h
82262 @@ -0,0 +1,302 @@
82263 +#ifndef _PCF50606_H
82264 +#define _PCF50606_H
82265 +
82266 +/* Philips PCF50606 Power Managemnt Unit (PMU) driver
82267 + * (C) 2006-2007 by Openmoko, Inc.
82268 + * Author: Harald Welte <laforge@openmoko.org>
82269 + *
82270 + */
82271 +
82272 +enum pfc50606_regs {
82273 +       PCF50606_REG_ID         = 0x00,
82274 +       PCF50606_REG_OOCS       = 0x01,
82275 +       PCF50606_REG_INT1       = 0x02, /* Interrupt Status */
82276 +       PCF50606_REG_INT2       = 0x03, /* Interrupt Status */
82277 +       PCF50606_REG_INT3       = 0x04, /* Interrupt Status */
82278 +       PCF50606_REG_INT1M      = 0x05, /* Interrupt Mask */
82279 +       PCF50606_REG_INT2M      = 0x06, /* Interrupt Mask */
82280 +       PCF50606_REG_INT3M      = 0x07, /* Interrupt Mask */
82281 +       PCF50606_REG_OOCC1      = 0x08,
82282 +       PCF50606_REG_OOCC2      = 0x09,
82283 +       PCF50606_REG_RTCSC      = 0x0a, /* Second */
82284 +       PCF50606_REG_RTCMN      = 0x0b, /* Minute */
82285 +       PCF50606_REG_RTCHR      = 0x0c, /* Hour */
82286 +       PCF50606_REG_RTCWD      = 0x0d, /* Weekday */
82287 +       PCF50606_REG_RTCDT      = 0x0e, /* Day */
82288 +       PCF50606_REG_RTCMT      = 0x0f, /* Month */
82289 +       PCF50606_REG_RTCYR      = 0x10, /* Year */
82290 +       PCF50606_REG_RTCSCA     = 0x11, /* Alarm Second */
82291 +       PCF50606_REG_RTCMNA     = 0x12, /* Alarm Minute */
82292 +       PCF50606_REG_RTCHRA     = 0x13, /* Alarm Hour */
82293 +       PCF50606_REG_RTCWDA     = 0x14, /* Alarm Weekday */
82294 +       PCF50606_REG_RTCDTA     = 0x15, /* Alarm Day */
82295 +       PCF50606_REG_RTCMTA     = 0x16, /* Alarm Month */
82296 +       PCF50606_REG_RTCYRA     = 0x17, /* Alarm Year */
82297 +       PCF50606_REG_PSSC       = 0x18, /* Power sequencing */
82298 +       PCF50606_REG_PWROKM     = 0x19, /* PWROK mask */
82299 +       PCF50606_REG_PWROKS     = 0x1a, /* PWROK status */
82300 +       PCF50606_REG_DCDC1      = 0x1b,
82301 +       PCF50606_REG_DCDC2      = 0x1c,
82302 +       PCF50606_REG_DCDC3      = 0x1d,
82303 +       PCF50606_REG_DCDC4      = 0x1e,
82304 +       PCF50606_REG_DCDEC1     = 0x1f,
82305 +       PCF50606_REG_DCDEC2     = 0x20,
82306 +       PCF50606_REG_DCUDC1     = 0x21,
82307 +       PCF50606_REG_DCUDC2     = 0x22,
82308 +       PCF50606_REG_IOREGC     = 0x23,
82309 +       PCF50606_REG_D1REGC1    = 0x24,
82310 +       PCF50606_REG_D2REGC1    = 0x25,
82311 +       PCF50606_REG_D3REGC1    = 0x26,
82312 +       PCF50606_REG_LPREGC1    = 0x27,
82313 +       PCF50606_REG_LPREGC2    = 0x28,
82314 +       PCF50606_REG_MBCC1      = 0x29,
82315 +       PCF50606_REG_MBCC2      = 0x2a,
82316 +       PCF50606_REG_MBCC3      = 0x2b,
82317 +       PCF50606_REG_MBCS1      = 0x2c,
82318 +       PCF50606_REG_BBCC       = 0x2d,
82319 +       PCF50606_REG_ADCC1      = 0x2e,
82320 +       PCF50606_REG_ADCC2      = 0x2f,
82321 +       PCF50606_REG_ADCS1      = 0x30,
82322 +       PCF50606_REG_ADCS2      = 0x31,
82323 +       PCF50606_REG_ADCS3      = 0x32,
82324 +       PCF50606_REG_ACDC1      = 0x33,
82325 +       PCF50606_REG_BVMC       = 0x34,
82326 +       PCF50606_REG_PWMC1      = 0x35,
82327 +       PCF50606_REG_LEDC1      = 0x36,
82328 +       PCF50606_REG_LEDC2      = 0x37,
82329 +       PCF50606_REG_GPOC1      = 0x38,
82330 +       PCF50606_REG_GPOC2      = 0x39,
82331 +       PCF50606_REG_GPOC3      = 0x3a,
82332 +       PCF50606_REG_GPOC4      = 0x3b,
82333 +       PCF50606_REG_GPOC5      = 0x3c,
82334 +       __NUM_PCF50606_REGS
82335 +};
82336 +
82337 +enum pcf50606_reg_oocs {
82338 +       PFC50606_OOCS_ONKEY     = 0x01,
82339 +       PCF50606_OOCS_EXTON     = 0x02,
82340 +       PCF50606_OOCS_PWROKRST  = 0x04,
82341 +       PCF50606_OOCS_BATOK     = 0x08,
82342 +       PCF50606_OOCS_BACKOK    = 0x10,
82343 +       PCF50606_OOCS_CHGOK     = 0x20,
82344 +       PCF50606_OOCS_TEMPOK    = 0x40,
82345 +       PCF50606_OOCS_WDTEXP    = 0x80,
82346 +};
82347 +
82348 +enum pcf50606_reg_oocc1 {
82349 +       PCF50606_OOCC1_GOSTDBY  = 0x01,
82350 +       PCF50606_OOCC1_TOTRST   = 0x02,
82351 +       PCF50606_OOCC1_CLK32ON  = 0x04,
82352 +       PCF50606_OOCC1_WDTRST   = 0x08,
82353 +       PCF50606_OOCC1_RTCWAK   = 0x10,
82354 +       PCF50606_OOCC1_CHGWAK   = 0x20,
82355 +       PCF50606_OOCC1_EXTONWAK_HIGH    = 0x40,
82356 +       PCF50606_OOCC1_EXTONWAK_LOW     = 0x80,
82357 +};
82358 +
82359 +enum pcf50606_reg_oocc2 {
82360 +       PCF50606_OOCC2_ONKEYDB_NONE     = 0x00,
82361 +       PCF50606_OOCC2_ONKEYDB_14ms     = 0x01,
82362 +       PCF50606_OOCC2_ONKEYDB_62ms     = 0x02,
82363 +       PCF50606_OOCC2_ONKEYDB_500ms    = 0x03,
82364 +       PCF50606_OOCC2_EXTONDB_NONE     = 0x00,
82365 +       PCF50606_OOCC2_EXTONDB_14ms     = 0x04,
82366 +       PCF50606_OOCC2_EXTONDB_62ms     = 0x08,
82367 +       PCF50606_OOCC2_EXTONDB_500ms    = 0x0c,
82368 +};
82369 +
82370 +enum pcf50606_reg_int1 {
82371 +       PCF50606_INT1_ONKEYR    = 0x01, /* ONKEY rising edge */
82372 +       PCF50606_INT1_ONKEYF    = 0x02, /* ONKEY falling edge */
82373 +       PCF50606_INT1_ONKEY1S   = 0x04, /* OMKEY at least 1sec low */
82374 +       PCF50606_INT1_EXTONR    = 0x08, /* EXTON rising edge */
82375 +       PCF50606_INT1_EXTONF    = 0x10, /* EXTON falling edge */
82376 +       PCF50606_INT1_SECOND    = 0x40, /* RTC periodic second interrupt */
82377 +       PCF50606_INT1_ALARM     = 0x80, /* RTC alarm time is reached */
82378 +};
82379 +
82380 +enum pcf50606_reg_int2 {
82381 +       PCF50606_INT2_CHGINS    = 0x01, /* Charger inserted */
82382 +       PCF50606_INT2_CHGRM     = 0x02, /* Charger removed */
82383 +       PCF50606_INT2_CHGFOK    = 0x04, /* Fast charging OK */
82384 +       PCF50606_INT2_CHGERR    = 0x08, /* Error in charging mode */
82385 +       PCF50606_INT2_CHGFRDY   = 0x10, /* Fast charge completed */
82386 +       PCF50606_INT2_CHGPROT   = 0x20, /* Charging protection interrupt */
82387 +       PCF50606_INT2_CHGWD10S  = 0x40, /* Charger watchdig expires in 10s */
82388 +       PCF50606_INT2_CHGWDEXP  = 0x80, /* Charger watchdog expires */
82389 +};
82390 +
82391 +enum pcf50606_reg_int3 {
82392 +       PCF50606_INT3_ADCRDY    = 0x01, /* ADC conversion finished */
82393 +       PCF50606_INT3_ACDINS    = 0x02, /* Accessory inserted */
82394 +       PCF50606_INT3_ACDREM    = 0x04, /* Accessory removed */
82395 +       PCF50606_INT3_TSCPRES   = 0x08, /* Touch screen pressed */
82396 +       PCF50606_INT3_LOWBAT    = 0x40, /* Low battery voltage */
82397 +       PCF50606_INT3_HIGHTMP   = 0x80, /* High temperature */
82398 +};
82399 +
82400 +/* used by PSSC, PWROKM, PWROKS, */
82401 +enum pcf50606_regu {
82402 +       PCF50606_REGU_DCD       = 0x01, /* DCD in phase 2 */
82403 +       PCF50606_REGU_DCDE      = 0x02, /* DCDE in phase 2 */
82404 +       PCF50606_REGU_DCUD      = 0x04, /* DCDU in phase 2 */
82405 +       PCF50606_REGU_IO        = 0x08, /* IO in phase 2 */
82406 +       PCF50606_REGU_D1        = 0x10, /* D1 in phase 2 */
82407 +       PCF50606_REGU_D2        = 0x20, /* D2 in phase 2 */
82408 +       PCF50606_REGU_D3        = 0x40, /* D3 in phase 2 */
82409 +       PCF50606_REGU_LP        = 0x80, /* LP in phase 2 */
82410 +};
82411 +
82412 +enum pcf50606_reg_dcdc4 {
82413 +       PCF50606_DCDC4_MODE_AUTO        = 0x00,
82414 +       PCF50606_DCDC4_MODE_PWM         = 0x01,
82415 +       PCF50606_DCDC4_MODE_PCF         = 0x02,
82416 +       PCF50606_DCDC4_OFF_FLOAT        = 0x00,
82417 +       PCF50606_DCDC4_OFF_BYPASS       = 0x04,
82418 +       PCF50606_DCDC4_OFF_PULLDOWN     = 0x08,
82419 +       PCF50606_DCDC4_CURLIM_500mA     = 0x00,
82420 +       PCF50606_DCDC4_CURLIM_750mA     = 0x10,
82421 +       PCF50606_DCDC4_CURLIM_1000mA    = 0x20,
82422 +       PCF50606_DCDC4_CURLIM_1250mA    = 0x30,
82423 +       PCF50606_DCDC4_TOGGLE           = 0x40,
82424 +       PCF50606_DCDC4_REGSEL_DCDC2     = 0x80,
82425 +};
82426 +
82427 +enum pcf50606_reg_dcdec2 {
82428 +       PCF50606_DCDEC2_MODE_AUTO       = 0x00,
82429 +       PCF50606_DCDEC2_MODE_PWM        = 0x01,
82430 +       PCF50606_DCDEC2_MODE_PCF        = 0x02,
82431 +       PCF50606_DCDEC2_OFF_FLOAT       = 0x00,
82432 +       PCF50606_DCDEC2_OFF_BYPASS      = 0x04,
82433 +};
82434 +
82435 +enum pcf50606_reg_dcudc2 {
82436 +       PCF50606_DCUDC2_MODE_AUTO       = 0x00,
82437 +       PCF50606_DCUDC2_MODE_PWM        = 0x01,
82438 +       PCF50606_DCUDC2_MODE_PCF        = 0x02,
82439 +       PCF50606_DCUDC2_OFF_FLOAT       = 0x00,
82440 +       PCF50606_DCUDC2_OFF_BYPASS      = 0x04,
82441 +};
82442 +
82443 +enum pcf50606_reg_adcc1 {
82444 +       PCF50606_ADCC1_TSCMODACT        = 0x01,
82445 +       PCF50606_ADCC1_TSCMODSTB        = 0x02,
82446 +       PCF50606_ADCC1_TRATSET          = 0x04,
82447 +       PCF50606_ADCC1_NTCSWAPE         = 0x08,
82448 +       PCF50606_ADCC1_NTCSWAOFF        = 0x10,
82449 +       PCF50606_ADCC1_EXTSYNCBREAK     = 0x20,
82450 +       /* reserved */
82451 +       PCF50606_ADCC1_TSCINT           = 0x80,
82452 +};
82453 +
82454 +enum pcf50606_reg_adcc2 {
82455 +       PCF50606_ADCC2_ADCSTART         = 0x01,
82456 +       /* see enum pcf50606_adcc2_adcmux */
82457 +       PCF50606_ADCC2_SYNC_NONE        = 0x00,
82458 +       PCF50606_ADCC2_SYNC_TXON        = 0x20,
82459 +       PCF50606_ADCC2_SYNC_PWREN1      = 0x40,
82460 +       PCF50606_ADCC2_SYNC_PWREN2      = 0x60,
82461 +       PCF50606_ADCC2_RES_10BIT        = 0x00,
82462 +       PCF50606_ADCC2_RES_8BIT         = 0x80,
82463 +};
82464 +
82465 +#define PCF50606_ADCC2_ADCMUX_MASK     (0xf << 1)
82466 +
82467 +#define ADCMUX_SHIFT   1
82468 +enum pcf50606_adcc2_adcmux {
82469 +       PCF50606_ADCMUX_BATVOLT_RES     = 0x0 << ADCMUX_SHIFT,
82470 +       PCF50606_ADCMUX_BATVOLT_SUBTR   = 0x1 << ADCMUX_SHIFT,
82471 +       PCF50606_ADCMUX_ADCIN1_RES      = 0x2 << ADCMUX_SHIFT,
82472 +       PCF50606_ADCMUX_ADCIN1_SUBTR    = 0x3 << ADCMUX_SHIFT,
82473 +       PCF50606_ADCMUX_BATTEMP         = 0x4 << ADCMUX_SHIFT,
82474 +       PCF50606_ADCMUX_ADCIN2          = 0x5 << ADCMUX_SHIFT,
82475 +       PCF50606_ADCMUX_ADCIN3          = 0x6 << ADCMUX_SHIFT,
82476 +       PCF50606_ADCMUX_ADCIN3_RATIO    = 0x7 << ADCMUX_SHIFT,
82477 +       PCF50606_ADCMUX_XPOS            = 0x8 << ADCMUX_SHIFT,
82478 +       PCF50606_ADCMUX_YPOS            = 0x9 << ADCMUX_SHIFT,
82479 +       PCF50606_ADCMUX_P1              = 0xa << ADCMUX_SHIFT,
82480 +       PCF50606_ADCMUX_P2              = 0xb << ADCMUX_SHIFT,
82481 +       PCF50606_ADCMUX_BATVOLT_ADCIN1  = 0xc << ADCMUX_SHIFT,
82482 +       PCF50606_ADCMUX_XY_SEQUENCE     = 0xe << ADCMUX_SHIFT,
82483 +       PCF50606_P1_P2_RESISTANCE       = 0xf << ADCMUX_SHIFT,
82484 +};
82485 +
82486 +enum pcf50606_adcs2 {
82487 +       PCF50606_ADCS2_ADCRDY           = 0x80,
82488 +};
82489 +
82490 +enum pcf50606_reg_mbcc1 {
82491 +       PCF50606_MBCC1_CHGAPE           = 0x01,
82492 +       PCF50606_MBCC1_AUTOFST          = 0x02,
82493 +#define        PCF50606_MBCC1_CHGMOD_MASK        0x1c
82494 +#define        PCF50606_MBCC1_CHGMOD_SHIFT       2
82495 +       PCF50606_MBCC1_CHGMOD_QUAL      = 0x00,
82496 +       PCF50606_MBCC1_CHGMOD_PRE       = 0x04,
82497 +       PCF50606_MBCC1_CHGMOD_TRICKLE   = 0x08,
82498 +       PCF50606_MBCC1_CHGMOD_FAST_CCCV = 0x0c,
82499 +       PCF50606_MBCC1_CHGMOD_FAST_NOCC = 0x10,
82500 +       PCF50606_MBCC1_CHGMOD_FAST_NOCV = 0x14,
82501 +       PCF50606_MBCC1_CHGMOD_FAST_SW   = 0x18,
82502 +       PCF50606_MBCC1_CHGMOD_IDLE      = 0x1c,
82503 +       PCF50606_MBCC1_DETMOD_LOWCHG    = 0x20,
82504 +       PCF50606_MBCC1_DETMOD_WDRST     = 0x40,
82505 +};
82506 +
82507 +enum pcf50606_reg_acdc1 {
82508 +       PCF50606_ACDC1_ACDDET           = 0x01,
82509 +       PCF50606_ACDC1_THRSHLD_1V0      = 0x00,
82510 +       PCF50606_ACDC1_THRSHLD_1V2      = 0x02,
82511 +       PCF50606_ACDC1_THRSHLD_1V4      = 0x04,
82512 +       PCF50606_ACDC1_THRSHLD_1V6      = 0x06,
82513 +       PCF50606_ACDC1_THRSHLD_1V8      = 0x08,
82514 +       PCF50606_ACDC1_THRSHLD_2V0      = 0x0a,
82515 +       PCF50606_ACDC1_THRSHLD_2V2      = 0x0c,
82516 +       PCF50606_ACDC1_THRSHLD_2V4      = 0x0e,
82517 +       PCF50606_ACDC1_DISDB            = 0x10,
82518 +       PCF50606_ACDC1_ACDAPE           = 0x80,
82519 +};
82520 +
82521 +enum pcf50606_reg_bvmc {
82522 +       PCF50606_BVMC_LOWBAT            = 0x01,
82523 +       PCF50606_BVMC_THRSHLD_NULL      = 0x00,
82524 +       PCF50606_BVMC_THRSHLD_2V8       = 0x02,
82525 +       PCF50606_BVMC_THRSHLD_2V9       = 0x04,
82526 +       PCF50606_BVMC_THRSHLD_3V        = 0x08,
82527 +       PCF50606_BVMC_THRSHLD_3V1       = 0x08,
82528 +       PCF50606_BVMC_THRSHLD_3V2       = 0x0a,
82529 +       PCF50606_BVMC_THRSHLD_3V3       = 0x0c,
82530 +       PCF50606_BVMC_THRSHLD_3V4       = 0x0e,
82531 +       PCF50606_BVMC_DISDB             = 0x10,
82532 +};
82533 +
82534 +enum pcf50606_reg_pwmc1 {
82535 +       PCF50606_PWMC1_ACTSET           = 0x01,
82536 +       PCF50606_PWMC1_PWMDC_0_16       = 0x00,
82537 +       PCF50606_PWMC1_PWMDC_1_16       = 0x02,
82538 +       PCF50606_PWMC1_PWMDC_2_16       = 0x04,
82539 +       PCF50606_PWMC1_PWMDC_3_16       = 0x06,
82540 +       PCF50606_PWMC1_PWMDC_4_16       = 0x08,
82541 +       PCF50606_PWMC1_PWMDC_5_16       = 0x0a,
82542 +       PCF50606_PWMC1_PWMDC_6_16       = 0x0c,
82543 +       PCF50606_PWMC1_PWMDC_7_16       = 0x0e,
82544 +       PCF50606_PWMC1_PWMDC_8_16       = 0x10,
82545 +       PCF50606_PWMC1_PWMDC_9_16       = 0x12,
82546 +       PCF50606_PWMC1_PWMDC_10_16      = 0x14,
82547 +       PCF50606_PWMC1_PWMDC_11_16      = 0x16,
82548 +       PCF50606_PWMC1_PWMDC_12_16      = 0x18,
82549 +       PCF50606_PWMC1_PWMDC_13_16      = 0x1a,
82550 +       PCF50606_PWMC1_PWMDC_14_16      = 0x1c,
82551 +       PCF50606_PWMC1_PWMDC_15_16      = 0x1e,
82552 +       PCF50606_PWMC1_PRESC_512Hz      = 0x20,
82553 +       PCF50606_PWMC1_PRESC_256Hz      = 0x40,
82554 +       PCF50606_PWMC1_PRESC_64Hz       = 0x60,
82555 +       PCF50606_PWMC1_PRESC_56kHz      = 0x80,
82556 +       PCF50606_PWMC1_PRESC_28kHz      = 0xa0,
82557 +       PCF50606_PWMC1_PRESC_14kHz      = 0xc0,
82558 +       PCF50606_PWMC1_PRESC_7kHz       = 0xe0,
82559 +};
82560 +#define PCF50606_PWMC1_CLK_SHIFT       5
82561 +#define PCF50606_PWMC1_DC_SHIFT                1
82562 +
82563 +#endif /* _PCF50606_H */
82564 +
82565 --- /dev/null
82566 +++ b/drivers/i2c/chips/pcf50633.c
82567 @@ -0,0 +1,1883 @@
82568 +/* Philips PCF50633 Power Management Unit (PMU) driver
82569 + *
82570 + * (C) 2006-2007 by Openmoko, Inc.
82571 + * Author: Harald Welte <laforge@openmoko.org>
82572 + * All rights reserved.
82573 + *
82574 + * This program is free software; you can redistribute it and/or
82575 + * modify it under the terms of the GNU General Public License as
82576 + * published by the Free Software Foundation; either version 2 of
82577 + * the License, or (at your option) any later version.
82578 + *
82579 + * This program is distributed in the hope that it will be useful,
82580 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
82581 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
82582 + * GNU General Public License for more details.
82583 + *
82584 + * You should have received a copy of the GNU General Public License
82585 + * along with this program; if not, write to the Free Software
82586 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
82587 + * MA 02111-1307 USA
82588 + *
82589 + * This driver is a monster ;) It provides the following features
82590 + * - voltage control for a dozen different voltage domains
82591 + * - charging control for main and backup battery
82592 + * - adc driver (hw_sensors like)
82593 + *
82594 + */
82595 +
82596 +#include <linux/module.h>
82597 +#include <linux/init.h>
82598 +#include <linux/i2c.h>
82599 +#include <linux/types.h>
82600 +#include <linux/interrupt.h>
82601 +#include <linux/irq.h>
82602 +#include <linux/workqueue.h>
82603 +#include <linux/delay.h>
82604 +#include <linux/rtc.h>
82605 +#include <linux/bcd.h>
82606 +#include <linux/watchdog.h>
82607 +#include <linux/miscdevice.h>
82608 +#include <linux/input.h>
82609 +#include <linux/fb.h>
82610 +#include <linux/sched.h>
82611 +#include <linux/platform_device.h>
82612 +#include <linux/pcf50633.h>
82613 +#include <linux/apm-emulation.h>
82614 +#include <linux/jiffies.h>
82615 +
82616 +#include <asm/mach-types.h>
82617 +
82618 +#include <linux/pcf50633.h>
82619 +#include <linux/regulator/pcf50633.h>
82620 +#include <linux/rtc/pcf50633.h>
82621 +
82622 +#if 0
82623 +#define DEBUGP(x, args ...) printk("%s: " x, __FUNCTION__, ## args)
82624 +#define DEBUGPC(x, args ...) printk(x, ## args)
82625 +#else
82626 +#define DEBUGP(x, args ...)
82627 +#define DEBUGPC(x, args ...)
82628 +#endif
82629 +
82630 +/***********************************************************************
82631 + * Static data / structures
82632 + ***********************************************************************/
82633 +
82634 +static unsigned short normal_i2c[] = { 0x73, I2C_CLIENT_END };
82635 +
82636 +I2C_CLIENT_INSMOD_1(pcf50633);
82637 +
82638 +enum close_state {
82639 +       CLOSE_STATE_NOT,
82640 +       CLOSE_STATE_ALLOW = 0x2342,
82641 +};
82642 +
82643 +static struct i2c_driver pcf50633_driver;
82644 +
82645 +static void pcf50633_usb_curlim_set(struct pcf50633_data *pcf, int ma);
82646 +static void pcf50633_charge_enable(struct pcf50633_data *pcf, int on);
82647 +
82648 +
82649 +/***********************************************************************
82650 + * Low-Level routines
82651 + ***********************************************************************/
82652 +
82653 +/* Read a block of upto 32 regs
82654 + *
82655 + * Locks assumed to be held by caller
82656 + */
82657 +int pcf50633_read(struct pcf50633_data *pcf, u_int8_t reg, int nr_regs, u_int8_t *data)
82658 +{
82659 +       return i2c_smbus_read_i2c_block_data(pcf->client, reg, nr_regs, data);
82660 +}
82661 +EXPORT_SYMBOL(pcf50633_read);
82662 +
82663 +/* Read a block of upto 32 regs
82664 + *
82665 + * Locks assumed to be held by caller
82666 + */
82667 +int pcf50633_write(struct pcf50633_data *pcf, u_int8_t reg, int nr_regs, u_int8_t *data)
82668 +{
82669 +       return i2c_smbus_write_i2c_block_data(pcf->client, reg, nr_regs, data);
82670 +}
82671 +EXPORT_SYMBOL(pcf50633_write);
82672 +
82673 +static int __reg_write(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val)
82674 +{
82675 +       if (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND) {
82676 +               dev_err(&pcf->client->dev, "__reg_write while suspended\n");
82677 +               dump_stack();
82678 +       }
82679 +       return i2c_smbus_write_byte_data(pcf->client, reg, val);
82680 +}
82681 +
82682 +int pcf50633_reg_write(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val)
82683 +{
82684 +       int ret;
82685 +
82686 +       mutex_lock(&pcf->lock);
82687 +       ret = __reg_write(pcf, reg, val);
82688 +       mutex_unlock(&pcf->lock);
82689 +
82690 +       return ret;
82691 +}
82692 +EXPORT_SYMBOL(pcf50633_reg_write);
82693 +
82694 +static int32_t __reg_read(struct pcf50633_data *pcf, u_int8_t reg)
82695 +{
82696 +       int32_t ret;
82697 +
82698 +       if (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND) {
82699 +               dev_err(&pcf->client->dev, "__reg_read while suspended\n");
82700 +               dump_stack();
82701 +       }
82702 +       ret = i2c_smbus_read_byte_data(pcf->client, reg);
82703 +
82704 +       return ret;
82705 +}
82706 +
82707 +u_int8_t pcf50633_reg_read(struct pcf50633_data *pcf, u_int8_t reg)
82708 +{
82709 +       int32_t ret;
82710 +
82711 +       mutex_lock(&pcf->lock);
82712 +       ret = __reg_read(pcf, reg);
82713 +       mutex_unlock(&pcf->lock);
82714 +
82715 +       return ret & 0xff;
82716 +}
82717 +EXPORT_SYMBOL(pcf50633_reg_read);
82718 +
82719 +int pcf50633_reg_set_bit_mask(struct pcf50633_data *pcf,
82720 +                           u_int8_t reg, u_int8_t mask, u_int8_t val)
82721 +{
82722 +       int ret;
82723 +       u_int8_t tmp;
82724 +
82725 +       val &= mask;
82726 +
82727 +       mutex_lock(&pcf->lock);
82728 +
82729 +       tmp = __reg_read(pcf, reg);
82730 +       tmp &= ~mask;
82731 +       tmp |= val;
82732 +       ret = __reg_write(pcf, reg, tmp);
82733 +
82734 +       mutex_unlock(&pcf->lock);
82735 +
82736 +       return ret;
82737 +}
82738 +EXPORT_SYMBOL(pcf50633_reg_set_bit_mask);
82739 +
82740 +int pcf50633_reg_clear_bits(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val)
82741 +{
82742 +       int ret;
82743 +       u_int8_t tmp;
82744 +
82745 +       mutex_lock(&pcf->lock);
82746 +
82747 +       tmp = __reg_read(pcf, reg);
82748 +       tmp &= ~val;
82749 +       ret = __reg_write(pcf, reg, tmp);
82750 +
82751 +       mutex_unlock(&pcf->lock);
82752 +
82753 +       return ret;
82754 +}
82755 +EXPORT_SYMBOL(pcf50633_reg_clear_bits);
82756 +
82757 +/* asynchronously setup reading one ADC channel */
82758 +static void async_adc_read_setup(struct pcf50633_data *pcf,
82759 +                                int channel, int avg)
82760 +{
82761 +       channel &= PCF50633_ADCC1_ADCMUX_MASK;
82762 +
82763 +       /* kill ratiometric, but enable ACCSW biasing */
82764 +       __reg_write(pcf, PCF50633_REG_ADCC2, 0x00);
82765 +       __reg_write(pcf, PCF50633_REG_ADCC3, 0x01);
82766 +
82767 +       /* start ADC conversion of selected channel */
82768 +       __reg_write(pcf, PCF50633_REG_ADCC1, channel | avg |
82769 +                   PCF50633_ADCC1_ADCSTART | PCF50633_ADCC1_RES_10BIT);
82770 +
82771 +}
82772 +
82773 +static u_int16_t adc_read_result(struct pcf50633_data *pcf)
82774 +{
82775 +       u_int16_t ret = (__reg_read(pcf, PCF50633_REG_ADCS1) << 2) |
82776 +                       (__reg_read(pcf, PCF50633_REG_ADCS3) &
82777 +                                                 PCF50633_ADCS3_ADCDAT1L_MASK);
82778 +
82779 +       DEBUGPC("adc result = %d\n", ret);
82780 +
82781 +       return ret;
82782 +}
82783 +
82784 +/* go into 'STANDBY' mode, i.e. power off the main CPU and peripherals */
82785 +void pcf50633_go_standby(struct pcf50633_data *pcf)
82786 +{
82787 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_OOCSHDWN,
82788 +                 PCF50633_OOCSHDWN_GOSTDBY, PCF50633_OOCSHDWN_GOSTDBY);
82789 +}
82790 +EXPORT_SYMBOL_GPL(pcf50633_go_standby);
82791 +
82792 +void pcf50633_gpio_set(struct pcf50633_data *pcf, enum pcf50633_gpio gpio,
82793 +                       int on)
82794 +{
82795 +       u_int8_t reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
82796 +
82797 +       if (on)
82798 +               pcf50633_reg_set_bit_mask(pcf, reg, 0x0f, 0x07);
82799 +       else
82800 +               pcf50633_reg_set_bit_mask(pcf, reg, 0x0f, 0x00);
82801 +}
82802 +EXPORT_SYMBOL_GPL(pcf50633_gpio_set);
82803 +
82804 +int pcf50633_gpio_get(struct pcf50633_data *pcf, enum pcf50633_gpio gpio)
82805 +{
82806 +       u_int8_t reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
82807 +       u_int8_t val = pcf50633_reg_read(pcf, reg) & 0x0f;
82808 +
82809 +       if (val == PCF50633_GPOCFG_GPOSEL_1 ||
82810 +           val == (PCF50633_GPOCFG_GPOSEL_0|PCF50633_GPOCFG_GPOSEL_INVERSE))
82811 +               return 1;
82812 +
82813 +       return 0;
82814 +}
82815 +EXPORT_SYMBOL_GPL(pcf50633_gpio_get);
82816 +
82817 +static int interpret_charger_type_from_adc(struct pcf50633_data *pcf,
82818 +                                          int sample)
82819 +{
82820 +       /* 1A capable charger? */
82821 +
82822 +       if (sample < ((ADC_NOM_CHG_DETECT_NONE + ADC_NOM_CHG_DETECT_1A) / 2))
82823 +               return CHARGER_TYPE_1A;
82824 +
82825 +       /* well then, nothing in the USB hole, or USB host / unk adapter */
82826 +
82827 +       if (pcf->flags & PCF50633_F_USB_PRESENT) /* ooh power is in there */
82828 +               return CHARGER_TYPE_HOSTUSB; /* HOSTUSB is the catchall */
82829 +
82830 +       return CHARGER_TYPE_NONE; /* no really -- nothing in there */
82831 +}
82832 +
82833 +
82834 +
82835 +static void
82836 +configure_pmu_for_charger(struct pcf50633_data *pcf,
82837 +                                       void *unused, int adc_result_raw)
82838 +{
82839 +       int type;
82840 +
82841 +       type = interpret_charger_type_from_adc(
82842 +                                            pcf, adc_result_raw);
82843 +       switch (type) {
82844 +       case CHARGER_TYPE_NONE:
82845 +               pcf50633_usb_curlim_set(pcf, 0);
82846 +               break;
82847 +       /*
82848 +        * the PCF50633 has a feature that it will supply only excess current
82849 +        * from the charger that is not used to power the device.  So this
82850 +        * 500mA setting is "up to 500mA" according to that.
82851 +        */
82852 +       case CHARGER_TYPE_HOSTUSB:
82853 +               /* USB subsystem should call pcf50633_usb_curlim_set to set
82854 +                * what was negotiated with the host when it is enumerated
82855 +                * successfully.  If we get called again after a good
82856 +                * negotiation, we keep what was negotiated.  (Removal of
82857 +                * USB plug destroys pcf->last_curlim_set to 0)
82858 +                */
82859 +               if (pcf->last_curlim_set > 100)
82860 +                       pcf50633_usb_curlim_set(pcf, pcf->last_curlim_set);
82861 +               else
82862 +                       pcf50633_usb_curlim_set(pcf, 100);
82863 +               break;
82864 +       case CHARGER_TYPE_1A:
82865 +               pcf50633_usb_curlim_set(pcf, 1000);
82866 +               /*
82867 +                * stop GPO / EN_HOSTUSB power driving out on the same
82868 +                * USB power pins we have a 1A charger on right now!
82869 +                */
82870 +               dev_dbg(&pcf->client->dev, "Charger -> CHARGER_TYPE_1A\n");
82871 +               __reg_write(pcf, PCF50633_GPO - PCF50633_GPIO1 +
82872 +                                PCF50633_REG_GPIO1CFG,
82873 +                                __reg_read(pcf, PCF50633_GPO - PCF50633_GPIO1 +
82874 +                                                PCF50633_REG_GPIO1CFG) & 0xf0);
82875 +               break;
82876 +       }
82877 +
82878 +       /* max out USB fast charge current -- actual current drawn is
82879 +        * additionally limited by USB limit so no worries
82880 +        */
82881 +       __reg_write(pcf, PCF50633_REG_MBCC5, 0xff);
82882 +
82883 +}
82884 +
82885 +static void trigger_next_adc_job_if_any(struct pcf50633_data *pcf)
82886 +{
82887 +       if (pcf->adc_queue_head == pcf->adc_queue_tail)
82888 +               return;
82889 +       async_adc_read_setup(pcf,
82890 +                            pcf->adc_queue[pcf->adc_queue_tail]->mux,
82891 +                            pcf->adc_queue[pcf->adc_queue_tail]->avg);
82892 +}
82893 +
82894 +
82895 +static void
82896 +adc_add_request_to_queue(struct pcf50633_data *pcf, struct adc_request *req)
82897 +{
82898 +       int old_head = pcf->adc_queue_head;
82899 +       pcf->adc_queue[pcf->adc_queue_head] = req;
82900 +
82901 +       pcf->adc_queue_head = (pcf->adc_queue_head + 1) &
82902 +                             (MAX_ADC_FIFO_DEPTH - 1);
82903 +
82904 +       /* it was idle before we just added this?  we need to kick it then */
82905 +       if (old_head == pcf->adc_queue_tail)
82906 +               trigger_next_adc_job_if_any(pcf);
82907 +}
82908 +
82909 +static void
82910 +__pcf50633_adc_sync_read_callback(struct pcf50633_data *pcf, void *param, int result)
82911 +{
82912 +       struct adc_request *req;
82913 +
82914 +       /*We know here that the passed param is an adc_request object */
82915 +       req = (struct adc_request *)param;
82916 +
82917 +       req->result = result;
82918 +       complete(&req->completion);
82919 +}
82920 +
82921 +int pcf50633_adc_sync_read(struct pcf50633_data *pcf, int mux, int avg)
82922 +{
82923 +
82924 +       struct adc_request *req;
82925 +       int result;
82926 +
82927 +       /* req is freed when the result is ready, in pcf50633_work*/
82928 +       req = kmalloc(sizeof(*req), GFP_KERNEL);
82929 +       if (!req)
82930 +               return -ENOMEM;
82931 +
82932 +       req->mux = mux;
82933 +       req->avg = avg;
82934 +       req->callback =  __pcf50633_adc_sync_read_callback;
82935 +       req->callback_param = req;
82936 +       init_completion(&req->completion);
82937 +
82938 +       adc_add_request_to_queue(pcf, req);
82939 +
82940 +       wait_for_completion(&req->completion);
82941 +       result = req->result;
82942 +
82943 +       return result;
82944 +}
82945 +
82946 +int pcf50633_adc_async_read(struct pcf50633_data *pcf, int mux, int avg,
82947 +                            void (*callback)(struct pcf50633_data *, void *,int),
82948 +                            void *callback_param)
82949 +{
82950 +       struct adc_request *req;
82951 +
82952 +       /* req is freed when the result is ready, in pcf50633_work*/
82953 +       req = kmalloc(sizeof(*req), GFP_KERNEL);
82954 +       if (!req)
82955 +               return -ENOMEM;
82956 +
82957 +       req->mux = mux;
82958 +       req->avg = avg;
82959 +       req->callback = callback;
82960 +       req->callback_param = callback_param;
82961 +
82962 +       adc_add_request_to_queue(pcf, req);
82963 +
82964 +       return 0;
82965 +}
82966 +
82967 +/*
82968 + * we get run to handle servicing the async notification from USB stack that
82969 + * we got enumerated and allowed to draw a particular amount of current
82970 + */
82971 +
82972 +static void pcf50633_work_usbcurlim(struct work_struct *work)
82973 +{
82974 +       struct pcf50633_data *pcf =
82975 +                   container_of(work, struct pcf50633_data, work_usb_curlimit);
82976 +
82977 +       mutex_lock(&pcf->working_lock_usb_curlimit);
82978 +
82979 +       /* just can't cope with it if we are suspending, don't reschedule */
82980 +       if ((pcf->suspend_state == PCF50633_SS_STARTING_SUSPEND) ||
82981 +           (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND))
82982 +               goto bail;
82983 +
82984 +       dev_dbg(&pcf->client->dev, "pcf50633_work_usbcurlim\n");
82985 +
82986 +       if (!pcf->probe_completed)
82987 +               goto reschedule;
82988 +
82989 +       /* we got a notification from USB stack before we completed resume...
82990 +        * that can only make trouble, reschedule for a retry
82991 +        */
82992 +       if (pcf->suspend_state &&
82993 +                    (pcf->suspend_state < PCF50633_SS_COMPLETED_RESUME))
82994 +               goto reschedule;
82995 +
82996 +       /*
82997 +        * did he pull USB before we managed to set the limit?
82998 +        */
82999 +       if (pcf->usb_removal_count_usb_curlimit != pcf->usb_removal_count)
83000 +               goto bail;
83001 +
83002 +       /* OK let's set the requested limit and finish */
83003 +
83004 +       dev_dbg(&pcf->client->dev, "pcf50633_work_usbcurlim setting %dmA\n",
83005 +                                                        pcf->pending_curlimit);
83006 +       pcf50633_usb_curlim_set(pcf, pcf->pending_curlimit);
83007 +
83008 +bail:
83009 +       mutex_unlock(&pcf->working_lock_usb_curlimit);
83010 +       return;
83011 +
83012 +reschedule:
83013 +       dev_dbg(&pcf->client->dev, "pcf50633_work_usbcurlim rescheduling\n");
83014 +       if (!schedule_work(&pcf->work_usb_curlimit))
83015 +               dev_err(&pcf->client->dev, "curlim reschedule work "
83016 +                                                           "already queued\n");
83017 +
83018 +       mutex_unlock(&pcf->working_lock_usb_curlimit);
83019 +       /* don't spew, delaying whatever else is happening */
83020 +       msleep(1);
83021 +}
83022 +
83023 +
83024 +/* this is an export to allow machine to set USB current limit according to
83025 + * notifications of USB stack about enumeration state.  We spawn a work
83026 + * function to handle the actual setting, because suspend / resume and such
83027 + * can be in a bad state since this gets called externally asychronous to
83028 + * anything else going on in pcf50633.
83029 + */
83030 +
83031 +int pcf50633_notify_usb_current_limit_change(struct pcf50633_data *pcf,
83032 +                                                               unsigned int ma)
83033 +{
83034 +       /* can happen if he calls before probe
83035 +        * have to bail with error since we can't even schedule the work
83036 +        */
83037 +       if (!pcf) {
83038 +               printk(KERN_ERR "pcf50633_notify_usb_current_limit called with NULL pcf\n");
83039 +               return -EBUSY;
83040 +       }
83041 +
83042 +       dev_dbg(&pcf->client->dev,
83043 +                "pcf50633_notify_usb_current_limit_change %dmA\n", ma);
83044 +
83045 +       /* prepare to detect USB power removal before we complete */
83046 +       pcf->usb_removal_count_usb_curlimit = pcf->usb_removal_count;
83047 +
83048 +       pcf->pending_curlimit = ma;
83049 +
83050 +       if (!schedule_work(&pcf->work_usb_curlimit))
83051 +               dev_err(&pcf->client->dev, "curlim work item already queued\n");
83052 +
83053 +       return 0;
83054 +}
83055 +EXPORT_SYMBOL_GPL(pcf50633_notify_usb_current_limit_change);
83056 +
83057 +
83058 +/* we are run when we see a NOBAT situation, because there is no interrupt
83059 + * source in pcf50633 that triggers on resuming charging.  It watches to see
83060 + * if charging resumes, it reassesses the charging source if it does.  If the
83061 + * USB power disappears, it is also a sign there must be a battery and it is
83062 + * NOT being charged, so it exits since the next move must be USB insertion for
83063 + * change of charger state
83064 + */
83065 +
83066 +static void pcf50633_work_nobat(struct work_struct *work)
83067 +{
83068 +       struct pcf50633_data *pcf =
83069 +                       container_of(work, struct pcf50633_data, work_nobat);
83070 +
83071 +       mutex_lock(&pcf->working_lock_nobat);
83072 +       pcf->working_nobat = 1;
83073 +       mutex_unlock(&pcf->working_lock_nobat);
83074 +
83075 +       while (1) {
83076 +               msleep(1000);
83077 +
83078 +               if (pcf->suspend_state != PCF50633_SS_RUNNING)
83079 +                       continue;
83080 +
83081 +               /* there's a battery in there now? */
83082 +               if (pcf50633_reg_read(pcf, PCF50633_REG_MBCS3) & 0x40) {
83083 +
83084 +                       pcf->jiffies_last_bat_ins = jiffies;
83085 +
83086 +                       /* figure out our charging stance */
83087 +                       (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
83088 +                                                    PCF50633_ADCC1_AVERAGE_16,
83089 +                                                    configure_pmu_for_charger,
83090 +                                                    NULL);
83091 +                       goto bail;
83092 +               }
83093 +
83094 +               /* he pulled USB cable since we were started?  exit then */
83095 +               if (pcf->usb_removal_count_nobat != pcf->usb_removal_count)
83096 +                       goto bail;
83097 +       }
83098 +
83099 +bail:
83100 +       mutex_lock(&pcf->working_lock_nobat);
83101 +       pcf->working_nobat = 0;
83102 +       mutex_unlock(&pcf->working_lock_nobat);
83103 +}
83104 +
83105 +
83106 +static void pcf50633_work(struct work_struct *work)
83107 +{
83108 +       struct pcf50633_data *pcf =
83109 +                       container_of(work, struct pcf50633_data, work);
83110 +       u_int8_t pcfirq[5];
83111 +       int ret;
83112 +       int tail;
83113 +       struct adc_request *req;
83114 +
83115 +       mutex_lock(&pcf->working_lock);
83116 +       pcf->working = 1;
83117 +
83118 +       /* sanity */
83119 +       if (!&pcf->client->dev)
83120 +               goto bail;
83121 +
83122 +       /*
83123 +        * if we are presently suspending, we are not in a position to deal
83124 +        * with pcf50633 interrupts at all.
83125 +        *
83126 +        * Because we didn't clear the int pending registers, there will be
83127 +        * no edge / interrupt waiting for us when we wake.  But it is OK
83128 +        * because at the end of our resume, we call this workqueue function
83129 +        * gratuitously, clearing the pending register and re-enabling
83130 +        * servicing this interrupt.
83131 +        */
83132 +
83133 +       if ((pcf->suspend_state == PCF50633_SS_STARTING_SUSPEND) ||
83134 +           (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND))
83135 +               goto bail;
83136 +
83137 +       /*
83138 +        * If we are inside suspend -> resume completion time we don't attempt
83139 +        * service until we have fully resumed.  Although we could talk to the
83140 +        * device as soon as I2C is up, the regs in the device which we might
83141 +        * choose to modify as part of the service action have not been
83142 +        * reloaded with their pre-suspend states yet.  Therefore we will
83143 +        * defer our service if we are called like that until our resume has
83144 +        * completed.
83145 +        *
83146 +        * This shouldn't happen any more because we disable servicing this
83147 +        * interrupt in suspend and don't re-enable it until resume is
83148 +        * completed.
83149 +        */
83150 +
83151 +       if (pcf->suspend_state &&
83152 +               (pcf->suspend_state != PCF50633_SS_COMPLETED_RESUME))
83153 +               goto reschedule;
83154 +
83155 +       /* this is the case early in resume! Sanity check! */
83156 +       if (i2c_get_clientdata(pcf->client) == NULL)
83157 +               goto reschedule;
83158 +
83159 +       /*
83160 +       * datasheet says we have to read the five IRQ
83161 +       * status regs in one transaction
83162 +       */
83163 +       ret = pcf50633_read(pcf, PCF50633_REG_INT1,
83164 +                                               sizeof(pcfirq), pcfirq);
83165 +       if (ret != sizeof(pcfirq)) {
83166 +               dev_info(&pcf->client->dev,
83167 +                        "Oh crap PMU IRQ register read failed -- "
83168 +                        "retrying later %d\n", ret);
83169 +               /*
83170 +                * it shouldn't fail, we no longer attempt to use
83171 +                * I2C while it can be suspended.  But we don't have
83172 +                * much option but to retry if if it ever did fail,
83173 +                * because if we don't service the interrupt to clear
83174 +                * it, we will never see another PMU interrupt edge.
83175 +                */
83176 +               goto reschedule;
83177 +       }
83178 +
83179 +       /* hey did we just resume? (because we don't get here unless we are
83180 +        * running normally or the first call after resumption)
83181 +        */
83182 +
83183 +       if (pcf->suspend_state != PCF50633_SS_RUNNING) {
83184 +               /*
83185 +               * grab a copy of resume interrupt reasons
83186 +               * from pcf50633 POV
83187 +               */
83188 +               memcpy(pcf->pcfirq_resume, pcfirq, sizeof(pcf->pcfirq_resume));
83189 +
83190 +               /* pcf50633 resume is really really over now then */
83191 +               pcf->suspend_state = PCF50633_SS_RUNNING;
83192 +
83193 +               /* peek at the IRQ reason, if power button then set a flag
83194 +                * so that we do not signal the event to userspace
83195 +                */
83196 +               if (pcfirq[1] & (PCF50633_INT2_ONKEYF | PCF50633_INT2_ONKEYR)) {
83197 +                       pcf->suppress_onkey_events = 1;
83198 +                       DEBUGP("Wake by ONKEY, suppressing ONKEY event");
83199 +               } else {
83200 +                       pcf->suppress_onkey_events = 0;
83201 +               }
83202 +       }
83203 +
83204 +       if (!pcf->coldplug_done) {
83205 +               DEBUGP("PMU Coldplug init\n");
83206 +
83207 +               /* we used SECOND to kick ourselves started -- turn it off */
83208 +               pcfirq[0] &= ~PCF50633_INT1_SECOND;
83209 +               pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_INT1M,
83210 +                                       PCF50633_INT1_SECOND,
83211 +                                       PCF50633_INT1_SECOND);
83212 +
83213 +               /* coldplug the USB if present */
83214 +               if ((__reg_read(pcf, PCF50633_REG_MBCS1) &
83215 +                   (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) ==
83216 +                   (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) {
83217 +                       DEBUGPC("COLD USBINS\n");
83218 +                       input_report_key(pcf->input_dev, KEY_POWER2, 1);
83219 +                       apm_queue_event(APM_POWER_STATUS_CHANGE);
83220 +                       pcf->flags |= PCF50633_F_USB_PRESENT;
83221 +                       if (pcf->pdata->cb)
83222 +                               pcf->pdata->cb(&pcf->client->dev,
83223 +                                       PCF50633_FEAT_MBC, PMU_EVT_USB_INSERT);
83224 +               }
83225 +
83226 +               /* figure out our initial charging stance */
83227 +               (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
83228 +                                             PCF50633_ADCC1_AVERAGE_16,
83229 +                                            configure_pmu_for_charger, NULL);
83230 +
83231 +               pcf->coldplug_done = 1;
83232 +       }
83233 +
83234 +       DEBUGP("INT1=0x%02x INT2=0x%02x INT3=0x%02x INT4=0x%02x INT5=0x%02x\n",
83235 +               pcfirq[0], pcfirq[1], pcfirq[2], pcfirq[3], pcfirq[4]);
83236 +
83237 +       if (pcfirq[0] & PCF50633_INT1_ADPINS) {
83238 +               /* Charger inserted */
83239 +               DEBUGPC("ADPINS ");
83240 +               input_report_key(pcf->input_dev, KEY_BATTERY, 1);
83241 +               apm_queue_event(APM_POWER_STATUS_CHANGE);
83242 +               pcf->flags |= PCF50633_F_CHG_PRESENT;
83243 +               if (pcf->pdata->cb)
83244 +                       pcf->pdata->cb(&pcf->client->dev,
83245 +                                      PCF50633_FEAT_MBC, PMU_EVT_INSERT);
83246 +       }
83247 +       if (pcfirq[0] & PCF50633_INT1_ADPREM) {
83248 +               /* Charger removed */
83249 +               DEBUGPC("ADPREM ");
83250 +               input_report_key(pcf->input_dev, KEY_BATTERY, 0);
83251 +               apm_queue_event(APM_POWER_STATUS_CHANGE);
83252 +               pcf->flags &= ~PCF50633_F_CHG_PRESENT;
83253 +               if (pcf->pdata->cb)
83254 +                       pcf->pdata->cb(&pcf->client->dev,
83255 +                                      PCF50633_FEAT_MBC, PMU_EVT_REMOVE);
83256 +       }
83257 +       if (pcfirq[0] & PCF50633_INT1_USBINS) {
83258 +               DEBUGPC("USBINS ");
83259 +               input_report_key(pcf->input_dev, KEY_POWER2, 1);
83260 +               apm_queue_event(APM_POWER_STATUS_CHANGE);
83261 +               pcf->flags |= PCF50633_F_USB_PRESENT;
83262 +               if (pcf->pdata->cb)
83263 +                       pcf->pdata->cb(&pcf->client->dev,
83264 +                                      PCF50633_FEAT_MBC, PMU_EVT_USB_INSERT);
83265 +               msleep(500); /* debounce, allow to see any ID resistor */
83266 +               /* completion irq will figure out our charging stance */
83267 +               (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
83268 +                                    PCF50633_ADCC1_AVERAGE_16,
83269 +                                    configure_pmu_for_charger, NULL);
83270 +       }
83271 +       if (pcfirq[0] & PCF50633_INT1_USBREM &&
83272 +                               !(pcfirq[0] & PCF50633_INT1_USBINS)) {
83273 +               /* the occurrence of USBINS and USBREM
83274 +                * should be exclusive in one schedule work
83275 +                */
83276 +               DEBUGPC("USBREM ");
83277 +
83278 +               pcf->usb_removal_count++;
83279 +
83280 +               /* only deal if we had understood it was in */
83281 +               if (pcf->flags & PCF50633_F_USB_PRESENT) {
83282 +                       input_report_key(pcf->input_dev, KEY_POWER2, 0);
83283 +                       apm_queue_event(APM_POWER_STATUS_CHANGE);
83284 +                       pcf->flags &= ~PCF50633_F_USB_PRESENT;
83285 +
83286 +                       if (pcf->pdata->cb)
83287 +                               pcf->pdata->cb(&pcf->client->dev,
83288 +                                       PCF50633_FEAT_MBC, PMU_EVT_USB_REMOVE);
83289 +
83290 +                       /* destroy any memory of grant of power from host */
83291 +                       pcf->last_curlim_set = 0;
83292 +
83293 +                       /* completion irq will figure out our charging stance */
83294 +                       (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
83295 +                                       PCF50633_ADCC1_AVERAGE_16,
83296 +                                       configure_pmu_for_charger, NULL);
83297 +               }
83298 +       }
83299 +       if (pcfirq[0] & PCF50633_INT1_ALARM) {
83300 +               DEBUGPC("ALARM ");
83301 +               if (pcf->pdata->used_features & PCF50633_FEAT_RTC)
83302 +                       pcf50633_rtc_handle_event(pcf,
83303 +                                       PCF50633_RTC_EVENT_ALARM);
83304 +       }
83305 +       if (pcfirq[0] & PCF50633_INT1_SECOND) {
83306 +               DEBUGPC("SECOND ");
83307 +               if (pcf->flags & PCF50633_F_RTC_SECOND)
83308 +                       pcf50633_rtc_handle_event(pcf,
83309 +                                       PCF50633_RTC_EVENT_SECOND);
83310 +
83311 +               if (pcf->onkey_seconds >= 0 &&
83312 +                   pcf->flags & PCF50633_F_PWR_PRESSED) {
83313 +                       DEBUGP("ONKEY_SECONDS(%u, OOCSTAT=0x%02x) ",
83314 +                               pcf->onkey_seconds,
83315 +                               pcf50633_reg_read(pcf, PCF50633_REG_OOCSTAT));
83316 +                       pcf->onkey_seconds++;
83317 +                       if (pcf->onkey_seconds >=
83318 +                           pcf->pdata->onkey_seconds_sig_init) {
83319 +                               /* Ask init to do 'ctrlaltdel' */
83320 +                               /*
83321 +                                * currently Linux reacts badly to issuing a
83322 +                                * signal to PID #1 before init is started.
83323 +                                * What happens is that the next kernel thread
83324 +                                * to start, which is the JFFS2 Garbage
83325 +                                * collector in our case, gets the signal
83326 +                                * instead and proceeds to fail to fork --
83327 +                                * which is very bad.  Therefore we confirm
83328 +                                * PID #1 exists before issuing the signal
83329 +                                */
83330 +                               if (find_task_by_pid_ns(1, &init_pid_ns)) {
83331 +                                       kill_pid(task_pid(find_task_by_pid_ns(1,
83332 +                                                       &init_pid_ns)), SIGPWR, 1);
83333 +                                       DEBUGPC("SIGINT(init) ");
83334 +                               }
83335 +                               /* FIXME: what if userspace doesn't shut down? */
83336 +                       }
83337 +                       if (pcf->onkey_seconds >=
83338 +                               pcf->pdata->onkey_seconds_shutdown) {
83339 +                               DEBUGPC("Power Off ");
83340 +                               pcf50633_go_standby(pcf);
83341 +                       }
83342 +               }
83343 +       }
83344 +
83345 +       if (pcfirq[1] & PCF50633_INT2_ONKEYF) {
83346 +               /* ONKEY falling edge (start of button press) */
83347 +               pcf->flags |= PCF50633_F_PWR_PRESSED;
83348 +               if (!pcf->suppress_onkey_events) {
83349 +                       DEBUGPC("ONKEYF ");
83350 +                       input_report_key(pcf->input_dev, KEY_POWER, 1);
83351 +               } else {
83352 +                       DEBUGPC("ONKEYF(unreported) ");
83353 +               }
83354 +       }
83355 +       if (pcfirq[1] & PCF50633_INT2_ONKEYR) {
83356 +               /* ONKEY rising edge (end of button press) */
83357 +               pcf->flags &= ~PCF50633_F_PWR_PRESSED;
83358 +               pcf->onkey_seconds = -1;
83359 +               if (!pcf->suppress_onkey_events) {
83360 +                       DEBUGPC("ONKEYR ");
83361 +                       input_report_key(pcf->input_dev, KEY_POWER, 0);
83362 +               } else {
83363 +                       DEBUGPC("ONKEYR(unreported) ");
83364 +                       /* don't suppress any more power button events */
83365 +                       pcf->suppress_onkey_events = 0;
83366 +               }
83367 +               /* disable SECOND interrupt in case RTC didn't
83368 +                * request it */
83369 +               if (!(pcf->flags & PCF50633_F_RTC_SECOND))
83370 +                       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_INT1M,
83371 +                                        PCF50633_INT1_SECOND,
83372 +                                        PCF50633_INT1_SECOND);
83373 +       }
83374 +       /* FIXME: we don't use EXTON1/2/3. thats why we skip it */
83375 +
83376 +       if (pcfirq[2] & PCF50633_INT3_BATFULL) {
83377 +               DEBUGPC("BATFULL ");
83378 +
83379 +               /* the problem is, we get a false BATFULL if we inserted battery
83380 +                * while USB powered.  Defeat BATFULL if we recently inserted
83381 +                * battery
83382 +                */
83383 +
83384 +               if ((jiffies - pcf->jiffies_last_bat_ins) < (HZ * 2)) {
83385 +
83386 +                       DEBUGPC("*** Ignoring BATFULL ***\n");
83387 +
83388 +                       ret = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
83389 +                                       PCF56033_MBCC7_USB_MASK;
83390 +
83391 +
83392 +                       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7,
83393 +                                        PCF56033_MBCC7_USB_MASK,
83394 +                                        PCF50633_MBCC7_USB_SUSPEND);
83395 +
83396 +                       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7,
83397 +                                        PCF56033_MBCC7_USB_MASK,
83398 +                                        ret);
83399 +               } else {
83400 +                       if (pcf->pdata->cb)
83401 +                               pcf->pdata->cb(&pcf->client->dev,
83402 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_IDLE);
83403 +               }
83404 +
83405 +               /* FIXME: signal this to userspace */
83406 +       }
83407 +       if (pcfirq[2] & PCF50633_INT3_CHGHALT) {
83408 +               DEBUGPC("CHGHALT ");
83409 +               /*
83410 +                * this is really "battery not pulling current" -- it can
83411 +                * appear with no battery attached
83412 +                */
83413 +               if (pcf->pdata->cb)
83414 +                       pcf->pdata->cb(&pcf->client->dev,
83415 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
83416 +       }
83417 +       if (pcfirq[2] & PCF50633_INT3_THLIMON) {
83418 +               DEBUGPC("THLIMON ");
83419 +               pcf->flags |= PCF50633_F_CHG_PROT;
83420 +               if (pcf->pdata->cb)
83421 +                       pcf->pdata->cb(&pcf->client->dev,
83422 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
83423 +       }
83424 +       if (pcfirq[2] & PCF50633_INT3_THLIMOFF) {
83425 +               DEBUGPC("THLIMOFF ");
83426 +               pcf->flags &= ~PCF50633_F_CHG_PROT;
83427 +               if (pcf->pdata->cb)
83428 +                       pcf->pdata->cb(&pcf->client->dev,
83429 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
83430 +       }
83431 +       if (pcfirq[2] & PCF50633_INT3_USBLIMON) {
83432 +               DEBUGPC("USBLIMON ");
83433 +               if (pcf->pdata->cb)
83434 +                       pcf->pdata->cb(&pcf->client->dev,
83435 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
83436 +       }
83437 +       if (pcfirq[2] & PCF50633_INT3_USBLIMOFF) {
83438 +               DEBUGPC("USBLIMOFF ");
83439 +               if (pcf->pdata->cb)
83440 +                       pcf->pdata->cb(&pcf->client->dev,
83441 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
83442 +       }
83443 +       if (pcfirq[2] & PCF50633_INT3_ADCRDY) {
83444 +               /* ADC result ready */
83445 +               DEBUGPC("ADCRDY ");
83446 +               tail = pcf->adc_queue_tail;
83447 +               pcf->adc_queue_tail = (pcf->adc_queue_tail + 1) &
83448 +                                     (MAX_ADC_FIFO_DEPTH - 1);
83449 +               req = pcf->adc_queue[tail];
83450 +               req->callback(pcf, req->callback_param,
83451 +                                       adc_read_result(pcf));
83452 +               kfree(req);
83453 +
83454 +               trigger_next_adc_job_if_any(pcf);
83455 +       }
83456 +       if (pcfirq[2] & PCF50633_INT3_ONKEY1S) {
83457 +               /* ONKEY pressed for more than 1 second */
83458 +               pcf->onkey_seconds = 0;
83459 +               DEBUGPC("ONKEY1S ");
83460 +               /* Tell PMU we are taking care of this */
83461 +               pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_OOCSHDWN,
83462 +                                PCF50633_OOCSHDWN_TOTRST,
83463 +                                PCF50633_OOCSHDWN_TOTRST);
83464 +               /* enable SECOND interrupt (hz tick) */
83465 +               pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M, PCF50633_INT1_SECOND);
83466 +       }
83467 +
83468 +       if (pcfirq[3] & (PCF50633_INT4_LOWBAT|PCF50633_INT4_LOWSYS)) {
83469 +               if ((__reg_read(pcf, PCF50633_REG_MBCS1) &
83470 +                   (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) ==
83471 +                   (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) {
83472 +                       /*
83473 +                        * hey no need to freak out, we have some kind of
83474 +                        * valid charger power to keep us going -- but note that
83475 +                        * we are not actually charging anything
83476 +                        */
83477 +                       if (pcf->pdata->cb)
83478 +                               pcf->pdata->cb(&pcf->client->dev,
83479 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_IDLE);
83480 +
83481 +                       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
83482 +                                       PCF50633_MBCC1_RESUME,
83483 +                                       PCF50633_MBCC1_RESUME);
83484 +
83485 +                       /*
83486 +                        * Well, we are not charging anything right this second
83487 +                        * ... however in the next ~30s before we get the next
83488 +                        * NOBAT, he might insert a battery.  So we schedule a
83489 +                        * work function checking to see if
83490 +                        * we started charging something during that time.
83491 +                        * USB removal as well as charging terminates the work
83492 +                        * function so we can't get terminally confused
83493 +                        */
83494 +                       mutex_lock(&pcf->working_lock_nobat);
83495 +                       if (!pcf->working_nobat) {
83496 +                               pcf->usb_removal_count_nobat =
83497 +                                                       pcf->usb_removal_count;
83498 +
83499 +                               if (!schedule_work(&pcf->work_nobat))
83500 +                                       DEBUGPC("failed to schedule nobat\n");
83501 +                       }
83502 +                       mutex_unlock(&pcf->working_lock_nobat);
83503 +
83504 +
83505 +                       DEBUGPC("(NO)BAT ");
83506 +               } else {
83507 +                       /* Really low battery voltage, we have 8 seconds left */
83508 +                       DEBUGPC("LOWBAT ");
83509 +                       /*
83510 +                        * currently Linux reacts badly to issuing a signal to
83511 +                        * PID #1 before init is started.  What happens is that
83512 +                        * the next kernel thread to start, which is the JFFS2
83513 +                        * Garbage collector in our case, gets the signal
83514 +                        * instead and proceeds to fail to fork -- which is
83515 +                        * very bad.  Therefore we confirm PID #1 exists
83516 +                        * before issuing SPIGPWR
83517 +                        */
83518 +
83519 +                        if (find_task_by_pid_ns(1, &init_pid_ns)) {
83520 +                                apm_queue_event(APM_LOW_BATTERY);
83521 +                                DEBUGPC("SIGPWR(init) ");
83522 +                                kill_pid(task_pid(find_task_by_pid_ns(1, &init_pid_ns)), SIGPWR, 1);
83523 +                       } else
83524 +                               /*
83525 +                                * well, our situation is like this:  we do not
83526 +                                * have any external power, we have a low
83527 +                                * battery and since PID #1 doesn't exist yet,
83528 +                                * we are early in the boot, likely before
83529 +                                * rootfs mount.  We should just call it a day
83530 +                                */
83531 +                               apm_queue_event(APM_CRITICAL_SUSPEND);
83532 +               }
83533 +
83534 +               /* Tell PMU we are taking care of this */
83535 +               pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_OOCSHDWN,
83536 +                                PCF50633_OOCSHDWN_TOTRST,
83537 +                                PCF50633_OOCSHDWN_TOTRST);
83538 +       }
83539 +       if (pcfirq[3] & PCF50633_INT4_HIGHTMP) {
83540 +               /* High temperature */
83541 +               DEBUGPC("HIGHTMP ");
83542 +               apm_queue_event(APM_CRITICAL_SUSPEND);
83543 +       }
83544 +       if (pcfirq[3] & PCF50633_INT4_AUTOPWRFAIL) {
83545 +               DEBUGPC("PCF50633_INT4_AUTOPWRFAIL ");
83546 +               /* FIXME: deal with this */
83547 +       }
83548 +       if (pcfirq[3] & PCF50633_INT4_DWN1PWRFAIL) {
83549 +               DEBUGPC("PCF50633_INT4_DWN1PWRFAIL ");
83550 +               /* FIXME: deal with this */
83551 +       }
83552 +       if (pcfirq[3] & PCF50633_INT4_DWN2PWRFAIL) {
83553 +               DEBUGPC("PCF50633_INT4_DWN2PWRFAIL ");
83554 +               /* FIXME: deal with this */
83555 +       }
83556 +       if (pcfirq[3] & PCF50633_INT4_LEDPWRFAIL) {
83557 +               DEBUGPC("PCF50633_INT4_LEDPWRFAIL ");
83558 +               /* FIXME: deal with this */
83559 +       }
83560 +       if (pcfirq[3] & PCF50633_INT4_LEDOVP) {
83561 +               DEBUGPC("PCF50633_INT4_LEDOVP ");
83562 +               /* FIXME: deal with this */
83563 +       }
83564 +
83565 +       DEBUGPC("\n");
83566 +
83567 +bail:
83568 +       pcf->working = 0;
83569 +       input_sync(pcf->input_dev);
83570 +       put_device(&pcf->client->dev);
83571 +       mutex_unlock(&pcf->working_lock);
83572 +
83573 +       return;
83574 +
83575 +reschedule:
83576 +       /* don't spew, delaying whatever else is happening */
83577 +       /* EXCEPTION: if we are in the middle of suspending, we don't have
83578 +        * time to hang around since we may be turned off core 1V3 already
83579 +        */
83580 +       if ((pcf->suspend_state != PCF50633_SS_STARTING_SUSPEND) &&
83581 +           (pcf->suspend_state != PCF50633_SS_COMPLETED_SUSPEND)) {
83582 +               msleep(10);
83583 +               dev_dbg(&pcf->client->dev, "rescheduling interrupt service\n");
83584 +       }
83585 +       if (!schedule_work(&pcf->work))
83586 +               dev_err(&pcf->client->dev, "int service reschedule failed\n");
83587 +
83588 +       /* we don't put the device here, hold it for next time */
83589 +       mutex_unlock(&pcf->working_lock);
83590 +}
83591 +
83592 +static irqreturn_t pcf50633_irq(int irq, void *_pcf)
83593 +{
83594 +       struct pcf50633_data *pcf = _pcf;
83595 +
83596 +       DEBUGP("entering(irq=%u, pcf=%p): scheduling work\n", irq, _pcf);
83597 +       dev_dbg(&pcf->client->dev, "pcf50633_irq scheduling work\n");
83598 +
83599 +       get_device(&pcf->client->dev);
83600 +       if (!schedule_work(&pcf->work) && !pcf->working)
83601 +               dev_err(&pcf->client->dev, "pcf irq work already queued\n");
83602 +
83603 +       return IRQ_HANDLED;
83604 +}
83605 +
83606 +static u_int16_t adc_to_batt_millivolts(u_int16_t adc)
83607 +{
83608 +       u_int16_t mvolts;
83609 +
83610 +       mvolts = (adc * 6000) / 1024;
83611 +
83612 +       return mvolts;
83613 +}
83614 +
83615 +#define BATTVOLT_SCALE_START 2800
83616 +#define BATTVOLT_SCALE_END 4200
83617 +#define BATTVOLT_SCALE_DIVIDER ((BATTVOLT_SCALE_END - BATTVOLT_SCALE_START)/100)
83618 +
83619 +static u_int8_t battvolt_scale(u_int16_t battvolt)
83620 +{
83621 +       /* FIXME: this linear scale is completely bogus */
83622 +       u_int16_t battvolt_relative = battvolt - BATTVOLT_SCALE_START;
83623 +       unsigned int percent = battvolt_relative / BATTVOLT_SCALE_DIVIDER;
83624 +
83625 +       return percent;
83626 +}
83627 +
83628 +u_int16_t pcf50633_battvolt(struct pcf50633_data *pcf)
83629 +{
83630 +       int ret;
83631 +
83632 +       ret = pcf50633_adc_sync_read(pcf, PCF50633_ADCC1_MUX_BATSNS_RES,
83633 +                                     PCF50633_ADCC1_AVERAGE_16);
83634 +
83635 +       if (ret < 0)
83636 +               return ret;
83637 +
83638 +       return adc_to_batt_millivolts(ret);
83639 +}
83640 +
83641 +EXPORT_SYMBOL_GPL(pcf50633_battvolt);
83642 +
83643 +static ssize_t show_battvolt(struct device *dev, struct device_attribute *attr,
83644 +                            char *buf)
83645 +{
83646 +       struct i2c_client *client = to_i2c_client(dev);
83647 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
83648 +
83649 +       return sprintf(buf, "%u\n", pcf50633_battvolt(pcf));
83650 +}
83651 +static DEVICE_ATTR(battvolt, S_IRUGO | S_IWUSR, show_battvolt, NULL);
83652 +
83653 +/***********************************************************************
83654 + * Charger Control
83655 + ***********************************************************************/
83656 +
83657 +/* Set maximum USB current limit */
83658 +static void pcf50633_usb_curlim_set(struct pcf50633_data *pcf, int ma)
83659 +{
83660 +       u_int8_t bits;
83661 +       int active = 0;
83662 +
83663 +       pcf->last_curlim_set = ma;
83664 +
83665 +       dev_dbg(&pcf->client->dev, "setting usb current limit to %d ma", ma);
83666 +
83667 +       if (ma >= 1000) {
83668 +               bits = PCF50633_MBCC7_USB_1000mA;
83669 +       }
83670 +       else if (ma >= 500)
83671 +               bits = PCF50633_MBCC7_USB_500mA;
83672 +       else if (ma >= 100)
83673 +               bits = PCF50633_MBCC7_USB_100mA;
83674 +       else
83675 +               bits = PCF50633_MBCC7_USB_SUSPEND;
83676 +
83677 +       /* set the nearest charging limit */
83678 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7, PCF56033_MBCC7_USB_MASK,
83679 +                        bits);
83680 +
83681 +       /* with this charging limit, is charging actually meaningful? */
83682 +       switch (bits) {
83683 +       case PCF50633_MBCC7_USB_500mA:
83684 +       case PCF50633_MBCC7_USB_1000mA:
83685 +               /* yes with this charging limit, we can do real charging */
83686 +               active = 1;
83687 +               break;
83688 +       default: /* right charging context that if there is power, we charge */
83689 +               if (pcf->flags & PCF50633_F_USB_PRESENT)
83690 +                       pcf->pdata->cb(&pcf->client->dev,
83691 +                              PCF50633_FEAT_MBC, PMU_EVT_CHARGER_ACTIVE);
83692 +               break;
83693 +       }
83694 +       /*
83695 +        * enable or disable charging according to current limit -- this will
83696 +        * also throw a platform notification callback about it
83697 +        */
83698 +       pcf50633_charge_enable(pcf, active);
83699 +
83700 +       /* clear batfull */
83701 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
83702 +                               PCF50633_MBCC1_AUTORES,
83703 +                               0);
83704 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
83705 +                               PCF50633_MBCC1_RESUME,
83706 +                               PCF50633_MBCC1_RESUME);
83707 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
83708 +                               PCF50633_MBCC1_AUTORES,
83709 +                               PCF50633_MBCC1_AUTORES);
83710 +
83711 +}
83712 +
83713 +static ssize_t show_usblim(struct device *dev, struct device_attribute *attr,
83714 +                          char *buf)
83715 +{
83716 +       struct i2c_client *client = to_i2c_client(dev);
83717 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
83718 +       u_int8_t usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
83719 +                                               PCF56033_MBCC7_USB_MASK;
83720 +       unsigned int ma;
83721 +
83722 +       if (usblim == PCF50633_MBCC7_USB_1000mA)
83723 +               ma = 1000;
83724 +       else if (usblim == PCF50633_MBCC7_USB_500mA)
83725 +               ma = 500;
83726 +       else if (usblim == PCF50633_MBCC7_USB_100mA)
83727 +               ma = 100;
83728 +       else
83729 +               ma = 0;
83730 +
83731 +       return sprintf(buf, "%u\n", ma);
83732 +}
83733 +static DEVICE_ATTR(usb_curlim, S_IRUGO | S_IWUSR, show_usblim, NULL);
83734 +
83735 +/* Enable/disable charging */
83736 +static void pcf50633_charge_enable(struct pcf50633_data *pcf, int on)
83737 +{
83738 +       u_int8_t bits;
83739 +       u_int8_t usblim;
83740 +
83741 +       if (!(pcf->pdata->used_features & PCF50633_FEAT_MBC))
83742 +               return;
83743 +
83744 +       DEBUGPC("pcf50633_charge_enable %d\n", on);
83745 +
83746 +       if (on) {
83747 +               pcf->flags |= PCF50633_F_CHG_ENABLED;
83748 +               bits = PCF50633_MBCC1_CHGENA;
83749 +               usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
83750 +                                                       PCF56033_MBCC7_USB_MASK;
83751 +               switch (usblim) {
83752 +               case PCF50633_MBCC7_USB_1000mA:
83753 +               case PCF50633_MBCC7_USB_500mA:
83754 +                       if (pcf->flags & PCF50633_F_USB_PRESENT)
83755 +                               if (pcf->pdata->cb)
83756 +                                       pcf->pdata->cb(&pcf->client->dev,
83757 +                                                      PCF50633_FEAT_MBC,
83758 +                                                      PMU_EVT_CHARGER_ACTIVE);
83759 +                       break;
83760 +               default:
83761 +                       break;
83762 +               }
83763 +       } else {
83764 +               pcf->flags &= ~PCF50633_F_CHG_ENABLED;
83765 +               bits = 0;
83766 +               if (pcf->pdata->cb)
83767 +                       pcf->pdata->cb(&pcf->client->dev,
83768 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_IDLE);
83769 +       }
83770 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1, PCF50633_MBCC1_CHGENA,
83771 +                        bits);
83772 +}
83773 +
83774 +#if 0
83775 +#define ONE                    1000000
83776 +static u_int16_t adc_to_rntc(struct pcf50633_data *pcf, u_int16_t adc)
83777 +{
83778 +       u_int32_t r_batt = (adc * pcf->pdata->r_fix_batt) / (1023 - adc);
83779 +       u_int16_t r_ntc;
83780 +
83781 +       /* The battery NTC has a parallell 10kOhms resistor */
83782 +       r_ntc = ONE / ((ONE/r_batt) - (ONE/pcf->pdata->r_fix_batt_par));
83783 +
83784 +       return r_ntc;
83785 +}
83786 +#endif
83787 +static ssize_t show_battemp(struct device *dev, struct device_attribute *attr,
83788 +                           char *buf)
83789 +{
83790 +       return sprintf(buf, "\n");
83791 +}
83792 +static DEVICE_ATTR(battemp, S_IRUGO | S_IWUSR, show_battemp, NULL);
83793 +#if 0
83794 +static u_int16_t adc_to_chg_milliamps(struct pcf50633_data *pcf,
83795 +                                            u_int16_t adc_adcin1,
83796 +                                            u_int16_t adc_batvolt)
83797 +{
83798 +       u_int32_t res = ((adc_adcin1 - adc_batvolt) * 6000);
83799 +       return res / (pcf->pdata->r_sense_milli * 1024 / 1000);
83800 +}
83801 +#endif
83802 +static ssize_t show_chgcur(struct device *dev, struct device_attribute *attr,
83803 +                          char *buf)
83804 +{
83805 +       return sprintf(buf, "\n");
83806 +}
83807 +static DEVICE_ATTR(chgcur, S_IRUGO | S_IWUSR, show_chgcur, NULL);
83808 +
83809 +static const char *chgmode_names[] = {
83810 +       [PCF50633_MBCS2_MBC_PLAY]               = "play-only",
83811 +       [PCF50633_MBCS2_MBC_USB_PRE]            = "pre",
83812 +       [PCF50633_MBCS2_MBC_ADP_PRE]            = "pre",
83813 +       [PCF50633_MBCS2_MBC_USB_PRE_WAIT]       = "pre-wait",
83814 +       [PCF50633_MBCS2_MBC_ADP_PRE_WAIT]       = "pre-wait",
83815 +       [PCF50633_MBCS2_MBC_USB_FAST]           = "fast",
83816 +       [PCF50633_MBCS2_MBC_ADP_FAST]           = "fast",
83817 +       [PCF50633_MBCS2_MBC_USB_FAST_WAIT]      = "fast-wait",
83818 +       [PCF50633_MBCS2_MBC_ADP_FAST_WAIT]      = "fast-wait",
83819 +       [PCF50633_MBCS2_MBC_ADP_FAST_WAIT]      = "bat-full",
83820 +};
83821 +
83822 +static ssize_t show_chgmode(struct device *dev, struct device_attribute *attr,
83823 +                           char *buf)
83824 +{
83825 +       struct i2c_client *client = to_i2c_client(dev);
83826 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
83827 +       u_int8_t mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
83828 +       u_int8_t chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
83829 +
83830 +       return sprintf(buf, "%s\n", chgmode_names[chgmod]);
83831 +}
83832 +
83833 +static ssize_t set_chgmode(struct device *dev, struct device_attribute *attr,
83834 +                          const char *buf, size_t count)
83835 +{
83836 +       struct i2c_client *client = to_i2c_client(dev);
83837 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
83838 +
83839 +       /* As opposed to the PCF50606, we can only enable or disable
83840 +        * charging and not directly jump into a certain mode! */
83841 +
83842 +       if (!strcmp(buf, "0\n"))
83843 +               pcf50633_charge_enable(pcf, 0);
83844 +       else
83845 +               pcf50633_charge_enable(pcf, 1);
83846 +
83847 +       return count;
83848 +}
83849 +
83850 +static DEVICE_ATTR(chgmode, S_IRUGO | S_IWUSR, show_chgmode, set_chgmode);
83851 +
83852 +static const char *chgstate_names[] = {
83853 +       [PCF50633_FIDX_CHG_ENABLED]             = "enabled",
83854 +       [PCF50633_FIDX_CHG_PRESENT]             = "charger_present",
83855 +       [PCF50633_FIDX_USB_PRESENT]             = "usb_present",
83856 +       [PCF50633_FIDX_CHG_ERR]                 = "error",
83857 +       [PCF50633_FIDX_CHG_PROT]                = "protection",
83858 +       [PCF50633_FIDX_CHG_READY]               = "ready",
83859 +};
83860 +
83861 +static ssize_t show_chgstate(struct device *dev, struct device_attribute *attr,
83862 +                           char *buf)
83863 +{
83864 +       struct i2c_client *client = to_i2c_client(dev);
83865 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
83866 +
83867 +       char *b = buf;
83868 +       int i;
83869 +
83870 +       for (i = 0; i < 32; i++)
83871 +               if (pcf->flags & (1 << i) && i < ARRAY_SIZE(chgstate_names))
83872 +                       b += sprintf(b, "%s ", chgstate_names[i]);
83873 +
83874 +       if (b > buf)
83875 +               b += sprintf(b, "\n");
83876 +
83877 +       return b - buf;
83878 +}
83879 +static DEVICE_ATTR(chgstate, S_IRUGO | S_IWUSR, show_chgstate, NULL);
83880 +
83881 +/*
83882 + * Charger type
83883 + */
83884 +
83885 +static ssize_t show_charger_type(struct device *dev,
83886 +                                struct device_attribute *attr, char *buf)
83887 +{
83888 +       struct i2c_client *client = to_i2c_client(dev);
83889 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
83890 +       int adc_raw_result, charger_type;
83891 +
83892 +       static const char *names_charger_type[] = {
83893 +               [CHARGER_TYPE_NONE]     = "none",
83894 +               [CHARGER_TYPE_HOSTUSB]  = "host/500mA usb",
83895 +               [CHARGER_TYPE_1A]       = "charger 1A",
83896 +       };
83897 +       static const char *names_charger_modes[] = {
83898 +               [PCF50633_MBCC7_USB_1000mA]     = "1A",
83899 +               [PCF50633_MBCC7_USB_500mA]      = "500mA",
83900 +               [PCF50633_MBCC7_USB_100mA]      = "100mA",
83901 +               [PCF50633_MBCC7_USB_SUSPEND]    = "suspend",
83902 +       };
83903 +       int mode = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) & PCF56033_MBCC7_USB_MASK;
83904 +
83905 +       adc_raw_result = pcf50633_adc_sync_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
83906 +                                                    PCF50633_ADCC1_AVERAGE_16);
83907 +       charger_type = interpret_charger_type_from_adc(pcf, adc_raw_result);
83908 +       return sprintf(buf, "%s mode %s\n",
83909 +                           names_charger_type[charger_type],
83910 +                           names_charger_modes[mode]);
83911 +}
83912 +
83913 +static DEVICE_ATTR(charger_type, 0444, show_charger_type, NULL);
83914 +
83915 +static ssize_t force_usb_limit_dangerous(struct device *dev,
83916 +                  struct device_attribute *attr, const char *buf, size_t count)
83917 +{
83918 +       struct i2c_client *client = to_i2c_client(dev);
83919 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
83920 +       int ma = simple_strtoul(buf, NULL, 10);
83921 +
83922 +       pcf50633_usb_curlim_set(pcf, ma);
83923 +       return count;
83924 +}
83925 +
83926 +static DEVICE_ATTR(force_usb_limit_dangerous, 0600,
83927 +                                              NULL, force_usb_limit_dangerous);
83928 +
83929 +/*
83930 + * Charger adc
83931 + */
83932 +
83933 +static ssize_t show_charger_adc(struct device *dev,
83934 +                               struct device_attribute *attr, char *buf)
83935 +{
83936 +       struct i2c_client *client = to_i2c_client(dev);
83937 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
83938 +       int result;
83939 +
83940 +       result = pcf50633_adc_sync_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
83941 +                                            PCF50633_ADCC1_AVERAGE_16);
83942 +       if (result < 0)
83943 +               return result;
83944 +
83945 +       return sprintf(buf, "%d\n", result);
83946 +}
83947 +
83948 +static DEVICE_ATTR(charger_adc, 0444, show_charger_adc, NULL);
83949 +
83950 +/*
83951 + * Dump regs
83952 + */
83953 +
83954 +static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr,
83955 +                           char *buf)
83956 +{
83957 +       struct i2c_client *client = to_i2c_client(dev);
83958 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
83959 +       u8 dump[16];
83960 +       int n, n1, idx = 0;
83961 +       char *buf1 = buf;
83962 +       static u8 address_no_read[] = { /* must be ascending */
83963 +               PCF50633_REG_INT1,
83964 +               PCF50633_REG_INT2,
83965 +               PCF50633_REG_INT3,
83966 +               PCF50633_REG_INT4,
83967 +               PCF50633_REG_INT5,
83968 +               0 /* terminator */
83969 +       };
83970 +
83971 +       for (n = 0; n < 256; n += sizeof(dump)) {
83972 +
83973 +               for (n1 = 0; n1 < sizeof(dump); n1++)
83974 +                       if (n == address_no_read[idx]) {
83975 +                               idx++;
83976 +                               dump[n1] = 0x00;
83977 +                       } else
83978 +                               dump[n1] = pcf50633_reg_read(pcf, n + n1);
83979 +
83980 +               hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0);
83981 +               buf1 += strlen(buf1);
83982 +               *buf1++ = '\n';
83983 +               *buf1 = '\0';
83984 +       }
83985 +
83986 +       return buf1 - buf;
83987 +}
83988 +
83989 +static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL);
83990 +
83991 +
83992 +/***********************************************************************
83993 + * Driver initialization
83994 + ***********************************************************************/
83995 +
83996 +/*
83997 + * CARE!  This table is modified at runtime!
83998 + */
83999 +static struct attribute *pcf_sysfs_entries[] = {
84000 +       &dev_attr_charger_type.attr,
84001 +       &dev_attr_force_usb_limit_dangerous.attr,
84002 +       &dev_attr_charger_adc.attr,
84003 +       &dev_attr_dump_regs.attr,
84004 +       NULL, /* going to add things at this point! */
84005 +       NULL,
84006 +       NULL,
84007 +       NULL,
84008 +       NULL,
84009 +       NULL,
84010 +       NULL,
84011 +};
84012 +
84013 +static struct attribute_group pcf_attr_group = {
84014 +       .name   = NULL,                 /* put in device directory */
84015 +       .attrs  = pcf_sysfs_entries,
84016 +};
84017 +
84018 +static void populate_sysfs_group(struct pcf50633_data *pcf)
84019 +{
84020 +       int i = 0;
84021 +       struct attribute **attr;
84022 +
84023 +       for (attr = pcf_sysfs_entries; *attr; attr++)
84024 +               i++;
84025 +
84026 +       if (pcf->pdata->used_features & PCF50633_FEAT_MBC) {
84027 +               pcf_sysfs_entries[i++] = &dev_attr_chgstate.attr;
84028 +               pcf_sysfs_entries[i++] = &dev_attr_chgmode.attr;
84029 +               pcf_sysfs_entries[i++] = &dev_attr_usb_curlim.attr;
84030 +       }
84031 +
84032 +       if (pcf->pdata->used_features & PCF50633_FEAT_CHGCUR)
84033 +               pcf_sysfs_entries[i++] = &dev_attr_chgcur.attr;
84034 +
84035 +       if (pcf->pdata->used_features & PCF50633_FEAT_BATVOLT)
84036 +               pcf_sysfs_entries[i++] = &dev_attr_battvolt.attr;
84037 +
84038 +       if (pcf->pdata->used_features & PCF50633_FEAT_BATTEMP)
84039 +               pcf_sysfs_entries[i++] = &dev_attr_battemp.attr;
84040 +
84041 +}
84042 +
84043 +static struct platform_device pcf50633_rtc_pdev = {
84044 +       .name   = "pcf50633-rtc",
84045 +       .id     = -1,
84046 +};
84047 +
84048 +static int pcf50633_probe(struct i2c_client *client, const struct i2c_device_id *ids)
84049 +{
84050 +       struct pcf50633_data *pcf;
84051 +       struct pcf50633_platform_data *pdata;
84052 +       int err = 0;
84053 +       int irq;
84054 +       int i;
84055 +
84056 +       DEBUGP("entering probe\n");
84057 +
84058 +       pdata = client->dev.platform_data;
84059 +
84060 +       pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
84061 +       if (!pcf)
84062 +               return -ENOMEM;
84063 +
84064 +       i2c_set_clientdata(client, pcf);
84065 +       irq = client->irq;
84066 +       mutex_init(&pcf->lock);
84067 +       mutex_init(&pcf->working_lock);
84068 +       mutex_init(&pcf->working_lock_nobat);
84069 +       mutex_init(&pcf->working_lock_usb_curlimit);
84070 +       INIT_WORK(&pcf->work, pcf50633_work);
84071 +       INIT_WORK(&pcf->work_nobat, pcf50633_work_nobat);
84072 +       INIT_WORK(&pcf->work_usb_curlimit, pcf50633_work_usbcurlim);
84073 +
84074 +       pcf->client = client;
84075 +       pcf->irq = irq;
84076 +       pcf->working = 0;
84077 +       pcf->suppress_onkey_events = 0;
84078 +       pcf->onkey_seconds = -1;
84079 +       pcf->pdata = pdata;
84080 +
84081 +       /* FIXME: now we try to detect the chip */
84082 +
84083 +       populate_sysfs_group(pcf);
84084 +
84085 +       err = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
84086 +       if (err) {
84087 +               dev_err(&client->dev, "error creating sysfs group\n");
84088 +               goto exit_free;
84089 +       }
84090 +
84091 +       /* create virtual charger 'device' */
84092 +
84093 +       /* register power off handler with core power management */
84094 +       /* FIXME : pm_power_off = &pcf50633_go_standby; */
84095 +
84096 +       pcf->input_dev = input_allocate_device();
84097 +       if (!pcf->input_dev)
84098 +               goto exit_sysfs;
84099 +
84100 +       pcf->input_dev->name = "GTA02 PMU events";
84101 +       pcf->input_dev->phys = "FIXME";
84102 +       pcf->input_dev->id.bustype = BUS_I2C;
84103 +
84104 +       pcf->input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
84105 +       set_bit(KEY_POWER, pcf->input_dev->keybit);
84106 +       set_bit(KEY_POWER2, pcf->input_dev->keybit);
84107 +       set_bit(KEY_BATTERY, pcf->input_dev->keybit);
84108 +
84109 +       err = input_register_device(pcf->input_dev);
84110 +       if (err)
84111 +               goto exit_sysfs;
84112 +
84113 +       /* configure interrupt mask */
84114 +
84115 +       /* we want SECOND to kick for the coldplug initialisation */
84116 +       pcf50633_reg_write(pcf, PCF50633_REG_INT1M, 0x00);
84117 +
84118 +       pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
84119 +       pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
84120 +       pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
84121 +       pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
84122 +
84123 +       /* force the backlight up, Qi does not do this for us */
84124 +
84125 +       /* pcf50633 manual p60
84126 +        * "led_out should never be set to 000000, as this would result
84127 +        * in a deadlock making it impossible to program another value.
84128 +        * If led_out should be inadvertently set to 000000, the
84129 +        * LEDOUT register can be reset by disabling and enabling the
84130 +        * LED converter via control bit led_on in the LEDENA register"
84131 +        */
84132 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x00);
84133 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 0x01);
84134 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x01);
84135 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDOUT, 0x3f);
84136 +
84137 +       err = request_irq(irq, pcf50633_irq, IRQF_TRIGGER_FALLING,
84138 +                         "pcf50633", pcf);
84139 +       if (err < 0)
84140 +               goto exit_input;
84141 +
84142 +       if (enable_irq_wake(irq) < 0)
84143 +               dev_err(&client->dev, "IRQ %u cannot be enabled as wake-up"
84144 +                       "source in this hardware revision!\n", irq);
84145 +
84146 +       if (pcf->pdata->used_features & PCF50633_FEAT_RTC) {
84147 +               pcf50633_rtc_pdev.dev.platform_data = pcf;
84148 +
84149 +               err = platform_device_register(&pcf50633_rtc_pdev);
84150 +               if (err)
84151 +                       goto exit_irq;
84152 +       }
84153 +
84154 +       if (pcf->pdata->flag_use_apm_emulation)
84155 +               apm_get_power_status = NULL;
84156 +
84157 +       pdata->pcf = pcf;
84158 +
84159 +       /* Create platform regulator devices from the platform data */
84160 +       for (i = 0; i < __NUM_PCF50633_REGULATORS; i++) {
84161 +               struct platform_device *pdev;
84162 +
84163 +               pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
84164 +               /* FIXME : Handle failure */
84165 +
84166 +               pdev->name = "pcf50633-regltr";
84167 +               pdev->id = i;
84168 +               pdev->dev.parent = &client->dev;
84169 +               pdev->dev.platform_data = &pdata->reg_init_data[i];
84170 +               pdev->dev.driver_data = pcf;
84171 +               pcf->regulator_pdev[i] = pdev;
84172 +
84173 +               platform_device_register(pdev);
84174 +       }
84175 +
84176 +       pcf->probe_completed = 1;
84177 +
84178 +       /* if platform was interested, give him a chance to register
84179 +        * platform devices that switch power with us as the parent
84180 +        * at registration time -- ensures suspend / resume ordering
84181 +        */
84182 +       if (pcf->pdata->attach_child_devices)
84183 +               (pcf->pdata->attach_child_devices)(&client->dev);
84184 +
84185 +       dev_info(&client->dev, "probe completed\n");
84186 +
84187 +       return 0;
84188 +exit_irq:
84189 +       free_irq(pcf->irq, pcf);
84190 +exit_input:
84191 +       input_unregister_device(pcf->input_dev);
84192 +exit_sysfs:
84193 +       pm_power_off = NULL;
84194 +       sysfs_remove_group(&client->dev.kobj, &pcf_attr_group);
84195 +exit_free:
84196 +       kfree(pcf);
84197 +       return err;
84198 +}
84199 +
84200 +static int pcf50633_remove(struct i2c_client *client)
84201 +{
84202 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84203 +
84204 +       DEBUGP("entering\n");
84205 +
84206 +       apm_get_power_status = NULL;
84207 +
84208 +       free_irq(pcf->irq, pcf);
84209 +
84210 +       input_unregister_device(pcf->input_dev);
84211 +
84212 +       if (pcf->pdata->used_features & PCF50633_FEAT_RTC)
84213 +               rtc_device_unregister(pcf->rtc);
84214 +
84215 +       sysfs_remove_group(&client->dev.kobj, &pcf_attr_group);
84216 +
84217 +       pm_power_off = NULL;
84218 +
84219 +       kfree(pcf);
84220 +
84221 +       return 0;
84222 +}
84223 +
84224 +/* you're going to need >300 bytes in buf */
84225 +
84226 +int pcf50633_report_resumers(struct pcf50633_data *pcf, char *buf)
84227 +{
84228 +       static char *int_names[] = {
84229 +               "adpins",
84230 +               "adprem",
84231 +               "usbins",
84232 +               "usbrem",
84233 +               NULL,
84234 +               NULL,
84235 +               "rtcalarm",
84236 +               "second",
84237 +
84238 +               "onkeyr",
84239 +               "onkeyf",
84240 +               "exton1r",
84241 +               "exton1f",
84242 +               "exton2r",
84243 +               "exton2f",
84244 +               "exton3r",
84245 +               "exton3f",
84246 +
84247 +               "batfull",
84248 +               "chghalt",
84249 +               "thlimon",
84250 +               "thlimoff",
84251 +               "usblimon",
84252 +               "usblimoff",
84253 +               "adcrdy",
84254 +               "onkey1s",
84255 +
84256 +               "lowsys",
84257 +               "lowbat",
84258 +               "hightmp",
84259 +               "autopwrfail",
84260 +               "dwn1pwrfail",
84261 +               "dwn2pwrfail",
84262 +               "ledpwrfail",
84263 +               "ledovp",
84264 +
84265 +               "ldo1pwrfail",
84266 +               "ldo2pwrfail",
84267 +               "ldo3pwrfail",
84268 +               "ldo4pwrfail",
84269 +               "ldo5pwrfail",
84270 +               "ldo6pwrfail",
84271 +               "hcidopwrfail",
84272 +               "hcidoovl"
84273 +       };
84274 +       char *end = buf;
84275 +       int n;
84276 +
84277 +       for (n = 0; n < ARRAY_SIZE(int_names); n++)
84278 +               if (int_names[n]) {
84279 +                       if (pcf->pcfirq_resume[n >> 3] & (1 >> (n & 7)))
84280 +                               end += sprintf(end, "  * %s\n", int_names[n]);
84281 +                       else
84282 +                               end += sprintf(end, "    %s\n", int_names[n]);
84283 +               }
84284 +
84285 +       return end - buf;
84286 +}
84287 +
84288 +
84289 +#ifdef CONFIG_PM
84290 +
84291 +static int pcf50633_suspend(struct device *dev, pm_message_t state)
84292 +{
84293 +       struct i2c_client *client = to_i2c_client(dev);
84294 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84295 +       int i;
84296 +       int ret;
84297 +       u_int8_t res[5];
84298 +
84299 +       dev_err(dev, "pcf50633_suspend\n");
84300 +
84301 +       /* we suspend once (!) as late as possible in the suspend sequencing */
84302 +
84303 +       if ((state.event != PM_EVENT_SUSPEND) ||
84304 +           (pcf->suspend_state != PCF50633_SS_RUNNING))
84305 +               return -EBUSY;
84306 +
84307 +       /* The general idea is to power down all unused power supplies,
84308 +        * and then mask all PCF50633 interrupt sources but EXTONR, ONKEYF
84309 +        * and ALARM */
84310 +
84311 +       mutex_lock(&pcf->lock);
84312 +
84313 +       pcf->suspend_state = PCF50633_SS_STARTING_SUSPEND;
84314 +
84315 +       /* we are not going to service any further interrupts until we
84316 +        * resume.  If the IRQ workqueue is still pending in the background,
84317 +        * it will bail when it sees we set suspend state above
84318 +        */
84319 +
84320 +       disable_irq(pcf->irq);
84321 +
84322 +       /* set interrupt masks so only those sources we want to wake
84323 +        * us are able to
84324 +        */
84325 +       for (i = 0; i < 5; i++)
84326 +               res[i] = ~pcf->pdata->resumers[i];
84327 +
84328 +       ret = pcf50633_write(pcf, PCF50633_REG_INT1M, 5, &res[0]);
84329 +       if (ret)
84330 +               dev_err(dev, "Failed to set wake masks :-( %d\n", ret);
84331 +
84332 +       pcf->suspend_state = PCF50633_SS_COMPLETED_SUSPEND;
84333 +
84334 +       mutex_unlock(&pcf->lock);
84335 +
84336 +       return 0;
84337 +}
84338 +
84339 +
84340 +int pcf50633_ready(struct pcf50633_data *pcf)
84341 +{
84342 +       if (!pcf)
84343 +               return -EACCES;
84344 +
84345 +       /* this was seen during boot with Qi, mmc_rescan racing us */
84346 +       if (!pcf->probe_completed)
84347 +               return -EACCES;
84348 +
84349 +       if ((pcf->suspend_state != PCF50633_SS_RUNNING) &&
84350 +           (pcf->suspend_state < PCF50633_SS_COMPLETED_RESUME))
84351 +               return -EBUSY;
84352 +
84353 +       return 0;
84354 +}
84355 +EXPORT_SYMBOL_GPL(pcf50633_ready);
84356 +
84357 +int pcf50633_wait_for_ready(struct pcf50633_data *pcf, int timeout_ms,
84358 +                                                               char *name)
84359 +{
84360 +       /* so we always go once */
84361 +       timeout_ms += 5;
84362 +
84363 +       while ((timeout_ms >= 5) && (pcf50633_ready(pcf))) {
84364 +               timeout_ms -= 5; /* well, it isn't very accurate, but OK */
84365 +               msleep(5);
84366 +       }
84367 +
84368 +       if (timeout_ms < 5) {
84369 +               printk(KERN_ERR"pcf50633_wait_for_ready: "
84370 +                                       "%s BAILING on timeout\n", name);
84371 +               return -EBUSY;
84372 +       }
84373 +
84374 +       return 0;
84375 +}
84376 +EXPORT_SYMBOL_GPL(pcf50633_wait_for_ready);
84377 +
84378 +static int pcf50633_resume(struct device *dev)
84379 +{
84380 +       struct i2c_client *client = to_i2c_client(dev);
84381 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84382 +       int ret;
84383 +       u8 res[5];
84384 +
84385 +       dev_dbg(dev, "pcf50633_resume suspended on entry = %d\n",
84386 +                                                (int)pcf->suspend_state);
84387 +       mutex_lock(&pcf->lock);
84388 +
84389 +       pcf->suspend_state = PCF50633_SS_STARTING_RESUME;
84390 +
84391 +       memset(res, 0, sizeof(res));
84392 +       /* not interested in second on resume */
84393 +       res[0] = PCF50633_INT1_SECOND;
84394 +       ret = pcf50633_write(pcf, PCF50633_REG_INT1M, 5, &res[0]);
84395 +       if (ret)
84396 +               dev_err(dev, "Failed to set int masks :-( %d\n", ret);
84397 +
84398 +       pcf->suspend_state = PCF50633_SS_COMPLETED_RESUME;
84399 +
84400 +       enable_irq(pcf->irq);
84401 +
84402 +       mutex_unlock(&pcf->lock);
84403 +
84404 +       /* gratuitous call to PCF work function, in the case that the PCF
84405 +        * interrupt edge was missed during resume, this forces the pending
84406 +        * register clear and lifts the interrupt back high again.  In the
84407 +        * case nothing is waiting for service, no harm done.
84408 +        */
84409 +
84410 +       get_device(&pcf->client->dev);
84411 +       pcf50633_work(&pcf->work);
84412 +
84413 +       return 0;
84414 +}
84415 +#else
84416 +#define pcf50633_suspend NULL
84417 +#define pcf50633_resume NULL
84418 +#endif
84419 +
84420 +static struct i2c_device_id pcf50633_id_table[] = {
84421 +       {"pcf50633", 0x73},
84422 +};
84423 +
84424 +static struct i2c_driver pcf50633_driver = {
84425 +       .driver = {
84426 +               .name   = "pcf50633",
84427 +               .suspend= pcf50633_suspend,
84428 +               .resume = pcf50633_resume,
84429 +       },
84430 +       .id_table = pcf50633_id_table,
84431 +       .probe = pcf50633_probe,
84432 +       .remove = pcf50633_remove,
84433 +};
84434 +
84435 +static int __init pcf50633_init(void)
84436 +{
84437 +       return i2c_add_driver(&pcf50633_driver);
84438 +}
84439 +
84440 +static void pcf50633_exit(void)
84441 +{
84442 +       i2c_del_driver(&pcf50633_driver);
84443 +}
84444 +
84445 +MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 power management unit");
84446 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
84447 +MODULE_LICENSE("GPL");
84448 +
84449 +module_init(pcf50633_init);
84450 +module_exit(pcf50633_exit);
84451 --- a/drivers/i2c/i2c-core.c
84452 +++ b/drivers/i2c/i2c-core.c
84453 @@ -1,4 +1,3 @@
84454 -/* i2c-core.c - a device driver for the iic-bus interface                   */
84455  /* ------------------------------------------------------------------------- */
84456  /*   Copyright (C) 1995-99 Simon G. Vogl
84457
84458 @@ -158,10 +157,16 @@ static int i2c_device_suspend(struct dev
84459
84460         if (!dev->driver)
84461                 return 0;
84462 +#if 0
84463         driver = to_i2c_driver(dev->driver);
84464         if (!driver->suspend)
84465                 return 0;
84466         return driver->suspend(to_i2c_client(dev), mesg);
84467 +#else
84468 +       if (!dev->driver->suspend)
84469 +               return 0;
84470 +       return dev->driver->suspend(dev, mesg);
84471 +#endif
84472  }
84473
84474  static int i2c_device_resume(struct device * dev)
84475 @@ -170,10 +175,16 @@ static int i2c_device_resume(struct devi
84476
84477         if (!dev->driver)
84478                 return 0;
84479 +#if 0
84480         driver = to_i2c_driver(dev->driver);
84481         if (!driver->resume)
84482                 return 0;
84483         return driver->resume(to_i2c_client(dev));
84484 +#else
84485 +       if (!dev->driver->resume)
84486 +               return 0;
84487 +       return dev->driver->resume(dev);
84488 +#endif
84489  }
84490
84491  static void i2c_client_release(struct device *dev)
84492 @@ -1129,11 +1140,11 @@ static int i2c_probe_address(struct i2c_
84493         int err;
84494
84495         /* Make sure the address is valid */
84496 -       if (addr < 0x03 || addr > 0x77) {
84497 +       /*if (addr < 0x03 || addr > 0x77) {
84498                 dev_warn(&adapter->dev, "Invalid probe address 0x%02x\n",
84499                          addr);
84500                 return -EINVAL;
84501 -       }
84502 +       }*/
84503
84504         /* Skip if already in use */
84505         if (i2c_check_addr(adapter, addr))
84506 --- a/drivers/input/keyboard/gpio_keys.c
84507 +++ b/drivers/input/keyboard/gpio_keys.c
84508 @@ -23,7 +23,7 @@
84509  #include <linux/input.h>
84510  #include <linux/gpio_keys.h>
84511
84512 -#include <asm/gpio.h>
84513 +#include <mach/gpio.h>
84514
84515  struct gpio_button_data {
84516         struct gpio_keys_button *button;
84517 --- a/drivers/input/keyboard/Kconfig
84518 +++ b/drivers/input/keyboard/Kconfig
84519 @@ -323,4 +323,21 @@ config KEYBOARD_SH_KEYSC
84520
84521           To compile this driver as a module, choose M here: the
84522           module will be called sh_keysc.
84523 +config KEYBOARD_NEO1973
84524 +       tristate "FIC Neo1973 buttons"
84525 +       depends on MACH_NEO1973
84526 +       default y
84527 +       help
84528 +         Say Y here to enable the buttons on the FIC Neo1973
84529 +         GSM phone.
84530 +
84531 +         To compile this driver as a module, choose M here: the
84532 +         module will be called neo1973kbd.
84533 +
84534 +config KEYBOARD_QT2410
84535 +       tristate "QT2410 buttons"
84536 +       depends on MACH_QT2410
84537 +       default y
84538 +
84539 +
84540  endif
84541 --- a/drivers/input/keyboard/Makefile
84542 +++ b/drivers/input/keyboard/Makefile
84543 @@ -14,6 +14,8 @@ obj-$(CONFIG_KEYBOARD_LOCOMO)         += locomo
84544  obj-$(CONFIG_KEYBOARD_NEWTON)          += newtonkbd.o
84545  obj-$(CONFIG_KEYBOARD_STOWAWAY)                += stowaway.o
84546  obj-$(CONFIG_KEYBOARD_CORGI)           += corgikbd.o
84547 +obj-$(CONFIG_KEYBOARD_NEO1973)         += neo1973kbd.o
84548 +obj-$(CONFIG_KEYBOARD_QT2410)          += qt2410kbd.o
84549  obj-$(CONFIG_KEYBOARD_SPITZ)           += spitzkbd.o
84550  obj-$(CONFIG_KEYBOARD_TOSA)            += tosakbd.o
84551  obj-$(CONFIG_KEYBOARD_HIL)             += hil_kbd.o
84552 --- /dev/null
84553 +++ b/drivers/input/keyboard/neo1973kbd.c
84554 @@ -0,0 +1,465 @@
84555 +/*
84556 + * Keyboard driver for FIC Neo1973 GSM phone
84557 + *
84558 + * (C) 2006-2007 by Openmoko, Inc.
84559 + * Author: Harald Welte <laforge@openmoko.org>
84560 + * All rights reserved.
84561 + *
84562 + * inspired by corkgbd.c by Richard Purdie
84563 + *
84564 + * This program is free software; you can redistribute it and/or modify
84565 + * it under the terms of the GNU General Public License version 2 as
84566 + * published by the Free Software Foundation.
84567 + *
84568 + */
84569 +
84570 +#include <linux/delay.h>
84571 +#include <linux/platform_device.h>
84572 +#include <linux/init.h>
84573 +#include <linux/input.h>
84574 +#include <linux/interrupt.h>
84575 +#include <linux/jiffies.h>
84576 +#include <linux/module.h>
84577 +#include <linux/slab.h>
84578 +#include <linux/workqueue.h>
84579 +
84580 +#include <mach/gpio.h>
84581 +#include <asm/mach-types.h>
84582 +
84583 +extern int global_inside_suspend;
84584 +
84585 +struct neo1973kbd {
84586 +       struct platform_device *pdev;
84587 +       struct input_dev *input;
84588 +       struct device *cdev;
84589 +       struct work_struct work;
84590 +       int aux_state;
84591 +       int work_in_progress;
84592 +       int hp_irq_count_in_work;
84593 +       int hp_irq_count;
84594 +       int jack_irq;
84595 +};
84596 +
84597 +static struct class *neo1973kbd_switch_class;
84598 +
84599 +enum keys {
84600 +       NEO1973_KEY_AUX,    /* GTA01 / 02 only */
84601 +       NEO1973_KEY_HOLD,
84602 +       NEO1973_KEY_JACK,
84603 +       NEO1973_KEY_PLUS,   /* GTA03 only */
84604 +       NEO1973_KEY_MINUS,  /* GTA03 only */
84605 +};
84606 +
84607 +struct neo1973kbd_key {
84608 +       const char * name;
84609 +       irqreturn_t (*isr)(int irq, void *dev_id);
84610 +       int irq;
84611 +       int input_key;
84612 +};
84613 +
84614 +static irqreturn_t neo1973kbd_aux_irq(int irq, void *dev_id);
84615 +static irqreturn_t neo1973kbd_headphone_irq(int irq, void *dev_id);
84616 +static irqreturn_t neo1973kbd_default_key_irq(int irq, void *dev_id);
84617 +
84618 +
84619 +static struct neo1973kbd_key keys[] = {
84620 +       [NEO1973_KEY_AUX] = {
84621 +               .name = "Neo1973 AUX button",
84622 +               .isr = neo1973kbd_aux_irq,
84623 +               .input_key = KEY_PHONE,
84624 +       },
84625 +       [NEO1973_KEY_HOLD] = {
84626 +               .name = "Neo1973 HOLD button",
84627 +               .isr = neo1973kbd_default_key_irq,
84628 +               .input_key = KEY_PAUSE,
84629 +       },
84630 +       [NEO1973_KEY_JACK] = {
84631 +               .name = "Neo1973 Headphone jack",
84632 +               .isr = neo1973kbd_headphone_irq,
84633 +       },
84634 +       [NEO1973_KEY_PLUS] = {
84635 +               .name = "GTA03 PLUS button",
84636 +               .isr = neo1973kbd_default_key_irq,
84637 +               .input_key = KEY_KPPLUS,
84638 +       },
84639 +       [NEO1973_KEY_MINUS] = {
84640 +               .name = "GTA03 MINUS button",
84641 +               .isr = neo1973kbd_default_key_irq,
84642 +               .input_key = KEY_KPMINUS,
84643 +       },
84644 +};
84645 +
84646 +/* This timer section filters AUX button IRQ bouncing */
84647 +
84648 +static void aux_key_timer_f(unsigned long data);
84649 +
84650 +static struct timer_list aux_key_timer =
84651 +               TIMER_INITIALIZER(aux_key_timer_f, 0, 0);
84652 +
84653 +#define AUX_TIMER_TIMEOUT (HZ >> 7)
84654 +#define AUX_TIMER_ALLOWED_NOOP 2
84655 +#define AUX_TIMER_CONSECUTIVE_EVENTS 5
84656 +
84657 +struct neo1973kbd *timer_kbd;
84658 +
84659 +static void aux_key_timer_f(unsigned long data)
84660 +{
84661 +       static int noop_counter;
84662 +       static int last_key = -1;
84663 +       static int last_count;
84664 +       int key_pressed;
84665 +
84666 +       key_pressed =
84667 +           !gpio_get_value(timer_kbd->pdev->resource[NEO1973_KEY_AUX].start);
84668 +       if (machine_is_neo1973_gta02())
84669 +               key_pressed = !key_pressed;
84670 +
84671 +       if (likely(key_pressed == last_key))
84672 +               last_count++;
84673 +       else {
84674 +               last_count = 1;
84675 +               last_key = key_pressed;
84676 +       }
84677 +
84678 +       if (unlikely(last_count >= AUX_TIMER_CONSECUTIVE_EVENTS)) {
84679 +               if (timer_kbd->aux_state != last_key) {
84680 +                       input_report_key(timer_kbd->input, KEY_PHONE, last_key);
84681 +                       input_sync(timer_kbd->input);
84682 +
84683 +                       timer_kbd->aux_state = last_key;
84684 +                       noop_counter = 0;
84685 +               }
84686 +               last_count = 0;
84687 +               if (unlikely(++noop_counter > AUX_TIMER_ALLOWED_NOOP)) {
84688 +                       noop_counter = 0;
84689 +                       return;
84690 +               }
84691 +       }
84692 +
84693 +       mod_timer(&aux_key_timer, jiffies + AUX_TIMER_TIMEOUT);
84694 +}
84695 +
84696 +static irqreturn_t neo1973kbd_aux_irq(int irq, void *dev)
84697 +{
84698 +       int *p = NULL;
84699 +
84700 +       /* if you stall inside resume then AUX will force a panic,
84701 +          which in turn forces a dump of the pending syslog */
84702 +
84703 +       if (global_inside_suspend)
84704 +               printk(KERN_ERR "death %d\n", *p);
84705 +
84706 +       mod_timer(&aux_key_timer, jiffies + AUX_TIMER_TIMEOUT);
84707 +
84708 +       return IRQ_HANDLED;
84709 +}
84710 +
84711 +static irqreturn_t neo1973kbd_default_key_irq(int irq, void *dev_id)
84712 +{
84713 +       struct neo1973kbd *kbd = dev_id;
84714 +       int n;
84715 +
84716 +       for (n = 0; n < ARRAY_SIZE(keys); n++) {
84717 +
84718 +               if (irq != keys[n].irq)
84719 +                       continue;
84720 +
84721 +               input_report_key(kbd->input, keys[n].input_key,
84722 +                                 gpio_get_value(kbd->pdev->resource[n].start));
84723 +               input_sync(kbd->input);
84724 +       }
84725 +
84726 +       return IRQ_HANDLED;
84727 +}
84728 +
84729 +
84730 +static const char *event_array_jack[2][4] = {
84731 +       [0] = {
84732 +               "SWITCH_NAME=headset",
84733 +               "SWITCH_STATE=0",
84734 +               "EVENT=remove",
84735 +               NULL
84736 +       },
84737 +       [1] = {
84738 +               "SWITCH_NAME=headset",
84739 +               "SWITCH_STATE=1",
84740 +               "EVENT=insert",
84741 +               NULL
84742 +       },
84743 +};
84744 +
84745 +static void neo1973kbd_jack_event(struct device *dev, int num)
84746 +{
84747 +       kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, (char **)event_array_jack[!!num]);
84748 +}
84749 +
84750 +
84751 +static void neo1973kbd_debounce_jack(struct work_struct *work)
84752 +{
84753 +       struct neo1973kbd *kbd = container_of(work, struct neo1973kbd, work);
84754 +       unsigned long flags;
84755 +       int loop = 0;
84756 +       int level;
84757 +
84758 +       do {
84759 +               /*
84760 +                * we wait out any multiple interrupt
84761 +                * stuttering in 100ms lumps
84762 +                */
84763 +               do {
84764 +                       kbd->hp_irq_count_in_work = kbd->hp_irq_count;
84765 +                       msleep(100);
84766 +               } while (kbd->hp_irq_count != kbd->hp_irq_count_in_work);
84767 +               /*
84768 +                * no new interrupts on jack for 100ms...
84769 +                * ok we will report it
84770 +                */
84771 +               level = gpio_get_value(kbd->pdev->resource[NEO1973_KEY_JACK].start);
84772 +               input_report_switch(kbd->input, SW_HEADPHONE_INSERT, level);
84773 +               input_sync(kbd->input);
84774 +               neo1973kbd_jack_event(kbd->cdev, level);
84775 +               /*
84776 +                * we go around the outer loop again if we detect that more
84777 +                * interrupts came while we are servicing here.  But we have
84778 +                * to sequence it carefully with interrupts off
84779 +                */
84780 +               local_save_flags(flags);
84781 +               /* no interrupts during this work means we can exit the work */
84782 +               loop = !!(kbd->hp_irq_count != kbd->hp_irq_count_in_work);
84783 +               if (!loop)
84784 +                       kbd->work_in_progress = 0;
84785 +               local_irq_restore(flags);
84786 +               /*
84787 +                * interrupt that comes here will either queue a new work action
84788 +                * since work_in_progress is cleared now, or be dealt with
84789 +                * when we loop.
84790 +                */
84791 +       } while (loop);
84792 +}
84793 +
84794 +
84795 +static irqreturn_t neo1973kbd_headphone_irq(int irq, void *dev_id)
84796 +{
84797 +       struct neo1973kbd *neo1973kbd_data = dev_id;
84798 +
84799 +       /*
84800 +        * this interrupt is prone to bouncing and userspace doesn't like
84801 +        * to have to deal with that kind of thing.  So we do not accept
84802 +        * that a jack interrupt is equal to a jack event.  Instead we fire
84803 +        * some work on the first interrupt, and it hangs about in 100ms units
84804 +        * until no more interrupts come.  Then it accepts the state it finds
84805 +        * for jack insert and reports it once
84806 +        */
84807 +
84808 +       neo1973kbd_data->hp_irq_count++;
84809 +       /*
84810 +        * the first interrupt we see for a while, we fire the work item
84811 +        * and record the interrupt count when we did that.  If more interrupts
84812 +        * come in the meanwhile, we can tell by the difference in that
84813 +        * stored count and hp_irq_count which increments every interrupt
84814 +        */
84815 +       if (!neo1973kbd_data->work_in_progress) {
84816 +               neo1973kbd_data->jack_irq = irq;
84817 +               neo1973kbd_data->hp_irq_count_in_work =
84818 +                                               neo1973kbd_data->hp_irq_count;
84819 +               if (!schedule_work(&neo1973kbd_data->work))
84820 +                       printk(KERN_ERR
84821 +                               "Unable to schedule headphone debounce\n");
84822 +               else
84823 +                       neo1973kbd_data->work_in_progress = 1;
84824 +       }
84825 +
84826 +       return IRQ_HANDLED;
84827 +}
84828 +
84829 +#ifdef CONFIG_PM
84830 +static int neo1973kbd_suspend(struct platform_device *dev, pm_message_t state)
84831 +{
84832 +       return 0;
84833 +}
84834 +
84835 +static int neo1973kbd_resume(struct platform_device *dev)
84836 +{
84837 +       return 0;
84838 +}
84839 +#else
84840 +#define neo1973kbd_suspend     NULL
84841 +#define neo1973kbd_resume      NULL
84842 +#endif
84843 +
84844 +static ssize_t neo1973kbd_switch_name_show(struct device *dev,
84845 +                       struct device_attribute *attr, char *buf)
84846 +{
84847 +       return sprintf(buf, "%s\n", "neo1973 Headset Jack");
84848 +}
84849 +
84850 +static ssize_t neo1973kbd_switch_state_show(struct device *dev,
84851 +                       struct device_attribute *attr, char *buf)
84852 +{
84853 +       struct neo1973kbd *kbd = dev_get_drvdata(dev);
84854 +       return sprintf(buf, "%d\n",
84855 +                  gpio_get_value(kbd->pdev->resource[NEO1973_KEY_JACK].start));
84856 +}
84857 +
84858 +static DEVICE_ATTR(name, S_IRUGO , neo1973kbd_switch_name_show, NULL);
84859 +static DEVICE_ATTR(state, S_IRUGO , neo1973kbd_switch_state_show, NULL);
84860 +
84861 +static int neo1973kbd_probe(struct platform_device *pdev)
84862 +{
84863 +       struct neo1973kbd *neo1973kbd;
84864 +       struct input_dev *input_dev;
84865 +       int rc;
84866 +       int irq;
84867 +       int n;
84868 +
84869 +       neo1973kbd = kzalloc(sizeof(struct neo1973kbd), GFP_KERNEL);
84870 +       input_dev = input_allocate_device();
84871 +       if (!neo1973kbd || !input_dev) {
84872 +               kfree(neo1973kbd);
84873 +               input_free_device(input_dev);
84874 +               return -ENOMEM;
84875 +       }
84876 +
84877 +       neo1973kbd->pdev = pdev;
84878 +       timer_kbd = neo1973kbd;
84879 +
84880 +       if (pdev->resource[0].flags != 0)
84881 +               return -EINVAL;
84882 +
84883 +       platform_set_drvdata(pdev, neo1973kbd);
84884 +
84885 +       neo1973kbd->input = input_dev;
84886 +
84887 +       INIT_WORK(&neo1973kbd->work, neo1973kbd_debounce_jack);
84888 +
84889 +       input_dev->name = "Neo1973 Buttons";
84890 +       input_dev->phys = "neo1973kbd/input0";
84891 +       input_dev->id.bustype = BUS_HOST;
84892 +       input_dev->id.vendor = 0x0001;
84893 +       input_dev->id.product = 0x0001;
84894 +       input_dev->id.version = 0x0100;
84895 +       input_dev->dev.parent = &pdev->dev;
84896 +
84897 +       input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_SW);
84898 +       set_bit(SW_HEADPHONE_INSERT, input_dev->swbit);
84899 +       set_bit(KEY_PHONE, input_dev->keybit);
84900 +       set_bit(KEY_PAUSE, input_dev->keybit);
84901 +
84902 +       rc = input_register_device(neo1973kbd->input);
84903 +       if (rc)
84904 +               goto out_register;
84905 +
84906 +       neo1973kbd->cdev = device_create(neo1973kbd_switch_class,
84907 +                                         &pdev->dev, 0, neo1973kbd, "headset");
84908 +       if (unlikely(IS_ERR(neo1973kbd->cdev))) {
84909 +               rc = PTR_ERR(neo1973kbd->cdev);
84910 +               goto out_device_create;
84911 +       }
84912 +
84913 +       rc = device_create_file(neo1973kbd->cdev, &dev_attr_name);
84914 +       if(rc)
84915 +               goto out_device_create_file;
84916 +
84917 +       rc = device_create_file(neo1973kbd->cdev, &dev_attr_state);
84918 +       if(rc)
84919 +               goto out_device_create_file;
84920 +
84921 +       /* register GPIO IRQs */
84922 +
84923 +       for(n = 0; n < ARRAY_SIZE(keys); n++) {
84924 +
84925 +               if (!pdev->resource[0].start)
84926 +                       continue;
84927 +
84928 +               irq = gpio_to_irq(pdev->resource[n].start);
84929 +               if (irq < 0)
84930 +                       continue;
84931 +
84932 +               if (request_irq(irq, keys[n].isr, IRQF_DISABLED |
84933 +                               IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
84934 +                               keys[n].name, neo1973kbd)) {
84935 +                       dev_err(&pdev->dev, "Can't get IRQ %u\n", irq);
84936 +
84937 +                       /* unwind any irq registrations and fail */
84938 +
84939 +                       while (n > 0) {
84940 +                               n--;
84941 +                               free_irq(gpio_to_irq(pdev->resource[n].start),
84942 +                                                                   neo1973kbd);
84943 +                       }
84944 +                       goto out_device_create_file;
84945 +               }
84946 +
84947 +               keys[n].irq = irq;
84948 +       }
84949 +
84950 +       /*
84951 +        * GTA01 revisions before Bv4 can't be resumed by the PMU, so we use
84952 +        * resume by AUX.
84953 +        */
84954 +       if (machine_is_neo1973_gta01())
84955 +               enable_irq_wake(keys[NEO1973_KEY_AUX].irq);
84956 +
84957 +       enable_irq_wake(keys[NEO1973_KEY_JACK].irq);
84958 +
84959 +       return 0;
84960 +
84961 +out_device_create_file:
84962 +       device_unregister(neo1973kbd->cdev);
84963 +out_device_create:
84964 +       input_unregister_device(neo1973kbd->input);
84965 +out_register:
84966 +       input_free_device(neo1973kbd->input);
84967 +       platform_set_drvdata(pdev, NULL);
84968 +       kfree(neo1973kbd);
84969 +
84970 +       return -ENODEV;
84971 +}
84972 +
84973 +static int neo1973kbd_remove(struct platform_device *pdev)
84974 +{
84975 +       struct neo1973kbd *neo1973kbd = platform_get_drvdata(pdev);
84976 +
84977 +       free_irq(gpio_to_irq(pdev->resource[2].start), neo1973kbd);
84978 +       free_irq(gpio_to_irq(pdev->resource[1].start), neo1973kbd);
84979 +       free_irq(gpio_to_irq(pdev->resource[0].start), neo1973kbd);
84980 +
84981 +       device_unregister(neo1973kbd->cdev);
84982 +       input_unregister_device(neo1973kbd->input);
84983 +       input_free_device(neo1973kbd->input);
84984 +       platform_set_drvdata(pdev, NULL);
84985 +       kfree(neo1973kbd);
84986 +
84987 +       return 0;
84988 +}
84989 +
84990 +static struct platform_driver neo1973kbd_driver = {
84991 +       .probe          = neo1973kbd_probe,
84992 +       .remove         = neo1973kbd_remove,
84993 +       .suspend        = neo1973kbd_suspend,
84994 +       .resume         = neo1973kbd_resume,
84995 +       .driver         = {
84996 +               .name   = "neo1973-button",
84997 +       },
84998 +};
84999 +
85000 +static int __devinit neo1973kbd_init(void)
85001 +{
85002 +       neo1973kbd_switch_class = class_create(THIS_MODULE, "switch");
85003 +       if (IS_ERR(neo1973kbd_switch_class))
85004 +               return PTR_ERR(neo1973kbd_switch_class);
85005 +       return platform_driver_register(&neo1973kbd_driver);
85006 +}
85007 +
85008 +static void __exit neo1973kbd_exit(void)
85009 +{
85010 +       platform_driver_unregister(&neo1973kbd_driver);
85011 +       class_destroy(neo1973kbd_switch_class);
85012 +}
85013 +
85014 +module_init(neo1973kbd_init);
85015 +module_exit(neo1973kbd_exit);
85016 +
85017 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
85018 +MODULE_DESCRIPTION("FIC Neo1973 buttons input driver");
85019 +MODULE_LICENSE("GPL");
85020 --- /dev/null
85021 +++ b/drivers/input/keyboard/qt2410kbd.c
85022 @@ -0,0 +1,231 @@
85023 +/*
85024 + * Keyboard driver for Armzone QT2410
85025 + *
85026 + * (C) 2006 by Openmoko, Inc.
85027 + * Author: Harald Welte <laforge@openmoko.org>
85028 + * All rights reserved.
85029 + *
85030 + * This program is free software; you can redistribute it and/or modify
85031 + * it under the terms of the GNU General Public License version 2 as
85032 + * published by the Free Software Foundation.
85033 + *
85034 + */
85035 +
85036 +#include <linux/delay.h>
85037 +#include <linux/platform_device.h>
85038 +#include <linux/init.h>
85039 +#include <linux/input.h>
85040 +#include <linux/interrupt.h>
85041 +#include <linux/jiffies.h>
85042 +#include <linux/module.h>
85043 +#include <linux/slab.h>
85044 +
85045 +#include <mach/hardware.h>
85046 +#include <mach/gta01.h>
85047 +
85048 +struct gta01kbd {
85049 +       struct input_dev *input;
85050 +       unsigned int suspended;
85051 +       unsigned long suspend_jiffies;
85052 +};
85053 +
85054 +static irqreturn_t gta01kbd_interrupt(int irq, void *dev_id)
85055 +{
85056 +       struct gta01kbd *gta01kbd_data = dev_id;
85057 +
85058 +       /* FIXME: use GPIO from platform_dev resources */
85059 +       if (s3c2410_gpio_getpin(S3C2410_GPF0))
85060 +               input_report_key(gta01kbd_data->input, KEY_PHONE, 1);
85061 +       else
85062 +               input_report_key(gta01kbd_data->input, KEY_PHONE, 0);
85063 +
85064 +       input_sync(gta01kbd_data->input);
85065 +
85066 +       return IRQ_HANDLED;
85067 +}
85068 +
85069 +
85070 +#ifdef CONFIG_PM
85071 +static int gta01kbd_suspend(struct platform_device *dev, pm_message_t state)
85072 +{
85073 +       struct gta01kbd *gta01kbd = platform_get_drvdata(dev);
85074 +
85075 +       gta01kbd->suspended = 1;
85076 +
85077 +       return 0;
85078 +}
85079 +
85080 +static int gta01kbd_resume(struct platform_device *dev)
85081 +{
85082 +       struct gta01kbd *gta01kbd = platform_get_drvdata(dev);
85083 +
85084 +       gta01kbd->suspended = 0;
85085 +
85086 +       return 0;
85087 +}
85088 +#else
85089 +#define gta01kbd_suspend       NULL
85090 +#define gta01kbd_resume                NULL
85091 +#endif
85092 +
85093 +static int gta01kbd_probe(struct platform_device *pdev)
85094 +{
85095 +       struct gta01kbd *gta01kbd;
85096 +       struct input_dev *input_dev;
85097 +       int irq_911;
85098 +       int rc = 0;
85099 +
85100 +       gta01kbd = kzalloc(sizeof(struct gta01kbd), GFP_KERNEL);
85101 +       if (!gta01kbd) {
85102 +               rc = -ENOMEM;
85103 +               goto bail;
85104 +       }
85105 +       input_dev = input_allocate_device();
85106 +       if (!gta01kbd || !input_dev) {
85107 +               rc = -ENOMEM;
85108 +               goto bail_free;
85109 +       }
85110 +
85111 +       if (pdev->resource[0].flags != 0) {\
85112 +               rc = -EINVAL;
85113 +               goto bail_free_dev;
85114 +       }
85115 +
85116 +       irq_911 = s3c2410_gpio_getirq(pdev->resource[0].start);
85117 +       if (irq_911 < 0) {
85118 +               rc = -EINVAL;
85119 +               goto bail_free_dev;
85120 +       }
85121 +
85122 +       platform_set_drvdata(pdev, gta01kbd);
85123 +
85124 +       gta01kbd->input = input_dev;
85125 +
85126 +#if 0
85127 +       spin_lock_init(&gta01kbd->lock);
85128 +       /* Init Keyboard rescan timer */
85129 +       init_timer(&corgikbd->timer);
85130 +       corgikbd->timer.function = corgikbd_timer_callback;
85131 +       corgikbd->timer.data = (unsigned long) corgikbd;
85132 +
85133 +       /* Init Hinge Timer */
85134 +       init_timer(&corgikbd->htimer);
85135 +       corgikbd->htimer.function = corgikbd_hinge_timer;
85136 +       corgikbd->htimer.data = (unsigned long) corgikbd;
85137 +
85138 +       corgikbd->suspend_jiffies=jiffies;
85139 +
85140 +       memcpy(corgikbd->keycode, corgikbd_keycode, sizeof(corgikbd->keycode));
85141 +#endif
85142 +
85143 +       input_dev->name = "QT2410 Buttons";
85144 +       input_dev->phys = "qt2410kbd/input0";
85145 +       input_dev->id.bustype = BUS_HOST;
85146 +       input_dev->id.vendor = 0x0001;
85147 +       input_dev->id.product = 0x0001;
85148 +       input_dev->id.version = 0x0100;
85149 +
85150 +       input_dev->evbit[0] = BIT(EV_KEY);
85151 +#if 0
85152 +       input_dev->keycode = gta01kbd->keycode;
85153 +       input_dev->keycodesize = sizeof(unsigned char);
85154 +       input_dev->keycodemax = ARRAY_SIZE(corgikbd_keycode);
85155 +
85156 +       for (i = 0; i < ARRAY_SIZE(corgikbd_keycode); i++)
85157 +               set_bit(corgikbd->keycode[i], input_dev->keybit);
85158 +       clear_bit(0, input_dev->keybit);
85159 +       set_bit(SW_LID, input_dev->swbit);
85160 +       set_bit(SW_TABLET_MODE, input_dev->swbit);
85161 +       set_bit(SW_HEADPHONE_INSERT, input_dev->swbit);
85162 +#endif
85163 +
85164 +       rc = input_register_device(gta01kbd->input);
85165 +       if (rc)
85166 +               goto bail_free_dev;
85167 +
85168 +       s3c2410_gpio_cfgpin(S3C2410_GPF0, S3C2410_GPF0_EINT0);
85169 +       if (request_irq(irq_911, gta01kbd_interrupt,
85170 +                       IRQF_DISABLED | IRQF_TRIGGER_RISING |
85171 +                       IRQF_TRIGGER_FALLING, "qt2410kbd_eint0", gta01kbd))
85172 +               printk(KERN_WARNING "gta01kbd: Can't get IRQ\n");
85173 +       enable_irq_wake(irq_911);
85174 +
85175 +       /* FIXME: headphone insert */
85176 +
85177 +#if 0
85178 +       mod_timer(&corgikbd->htimer, jiffies + msecs_to_jiffies(HINGE_SCAN_INTERVAL));
85179 +
85180 +       /* Setup sense interrupts - RisingEdge Detect, sense lines as inputs */
85181 +       for (i = 0; i < CORGI_KEY_SENSE_NUM; i++) {
85182 +               pxa_gpio_mode(CORGI_GPIO_KEY_SENSE(i) | GPIO_IN);
85183 +               if (request_irq(CORGI_IRQ_GPIO_KEY_SENSE(i), corgikbd_interrupt,
85184 +                               SA_INTERRUPT | SA_TRIGGER_RISING,
85185 +                               "corgikbd", corgikbd))
85186 +                       printk(KERN_WARNING "corgikbd: Can't get IRQ: %d!\n", i);
85187 +       }
85188 +
85189 +       /* Set Strobe lines as outputs - set high */
85190 +       for (i = 0; i < CORGI_KEY_STROBE_NUM; i++)
85191 +               pxa_gpio_mode(CORGI_GPIO_KEY_STROBE(i) | GPIO_OUT | GPIO_DFLT_HIGH);
85192 +
85193 +       /* Setup the headphone jack as an input */
85194 +       pxa_gpio_mode(CORGI_GPIO_AK_INT | GPIO_IN);
85195 +#endif
85196 +
85197 +       return 0;
85198 +
85199 +bail_free_dev:
85200 +       input_free_device(input_dev);
85201 +bail_free:
85202 +       kfree(gta01kbd);
85203 +bail:
85204 +       return rc;
85205 +}
85206 +
85207 +static int gta01kbd_remove(struct platform_device *pdev)
85208 +{
85209 +       struct gta01kbd *gta01kbd = platform_get_drvdata(pdev);
85210 +
85211 +       free_irq(s3c2410_gpio_getirq(pdev->resource[0].start), gta01kbd);
85212 +#if 0
85213 +       int i;
85214 +
85215 +       for (i = 0; i < CORGI_KEY_SENSE_NUM; i++)
85216 +               free_irq(CORGI_IRQ_GPIO_KEY_SENSE(i), corgikbd);
85217 +
85218 +       del_timer_sync(&corgikbd->htimer);
85219 +       del_timer_sync(&corgikbd->timer);
85220 +#endif
85221 +       input_unregister_device(gta01kbd->input);
85222 +
85223 +       kfree(gta01kbd);
85224 +
85225 +       return 0;
85226 +}
85227 +
85228 +static struct platform_driver gta01kbd_driver = {
85229 +       .probe          = gta01kbd_probe,
85230 +       .remove         = gta01kbd_remove,
85231 +       .suspend        = gta01kbd_suspend,
85232 +       .resume         = gta01kbd_resume,
85233 +       .driver         = {
85234 +               .name   = "qt2410-button",
85235 +       },
85236 +};
85237 +
85238 +static int __devinit gta01kbd_init(void)
85239 +{
85240 +       return platform_driver_register(&gta01kbd_driver);
85241 +}
85242 +
85243 +static void __exit gta01kbd_exit(void)
85244 +{
85245 +       platform_driver_unregister(&gta01kbd_driver);
85246 +}
85247 +
85248 +module_init(gta01kbd_init);
85249 +module_exit(gta01kbd_exit);
85250 +
85251 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
85252 +MODULE_DESCRIPTION("Armzone QT2410 Buttons Driver");
85253 +MODULE_LICENSE("GPL");
85254 --- a/drivers/input/misc/Kconfig
85255 +++ b/drivers/input/misc/Kconfig
85256 @@ -236,4 +236,25 @@ config INPUT_GPIO_BUTTONS
85257           To compile this driver as a module, choose M here: the
85258           module will be called gpio-buttons.
85259
85260 +config INPUT_LIS302DL
85261 +       tristate "STmicro LIS302DL 3-axis accelerometer"
85262 +       depends on SPI_MASTER
85263 +       help
85264 +         SPI driver for the STmicro LIS302DL 3-axis accelerometer.
85265 +
85266 +         The userspece interface is a 3-axis (X/Y/Z) relative movement
85267 +         Linux input device, reporting REL_[XYZ] events.
85268 +
85269 +config INPUT_PCF50633_PMU
85270 +       tristate "PCF50633 PMU events"
85271 +       depends on MFD_PCF50633
85272 +       help
85273 +        Say Y to include support for input events on NXP PCF50633.
85274 +
85275 +config INPUT_PCF50606_PMU
85276 +       tristate "PCF50606 PMU events"
85277 +       depends on MFD_PCF50606
85278 +       help
85279 +        Say Y to include support for input events on NXP PCF50606.
85280 +
85281  endif
85282 --- /dev/null
85283 +++ b/drivers/input/misc/lis302dl.c
85284 @@ -0,0 +1,874 @@
85285 +/* Linux kernel driver for the ST LIS302D 3-axis accelerometer
85286 + *
85287 + * Copyright (C) 2007-2008 by Openmoko, Inc.
85288 + * Author: Harald Welte <laforge@openmoko.org>
85289 + *         converted to private bitbang by:
85290 + *         Andy Green <andy@openmoko.com>
85291 + *         ability to set acceleration threshold added by:
85292 + *         Simon Kagstrom <simon.kagstrom@gmail.com>
85293 + * All rights reserved.
85294 + *
85295 + * This program is free software; you can redistribute it and/or
85296 + * modify it under the terms of the GNU General Public License as
85297 + * published by the Free Software Foundation; either version 2 of
85298 + * the License, or (at your option) any later version.
85299 + *
85300 + * This program is distributed in the hope that it will be useful,
85301 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
85302 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
85303 + * GNU General Public License for more details.
85304 + *
85305 + * You should have received a copy of the GNU General Public License
85306 + * along with this program; if not, write to the Free Software
85307 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
85308 + * MA 02111-1307 USA
85309 + *
85310 + * TODO
85311 + *     * statistics for overflow events
85312 + *     * configuration interface (sysfs) for
85313 + *             * enable/disable x/y/z axis data ready
85314 + *             * enable/disable resume from freee fall / click
85315 + *             * free fall / click parameters
85316 + *             * high pass filter parameters
85317 + */
85318 +#include <linux/kernel.h>
85319 +#include <linux/types.h>
85320 +#include <linux/module.h>
85321 +#include <linux/device.h>
85322 +#include <linux/platform_device.h>
85323 +#include <linux/delay.h>
85324 +#include <linux/irq.h>
85325 +#include <linux/interrupt.h>
85326 +#include <linux/sysfs.h>
85327 +
85328 +#include <linux/lis302dl.h>
85329 +
85330 +/* Utility functions */
85331 +static u8 __reg_read(struct lis302dl_info *lis, u8 reg)
85332 +{
85333 +       return (lis->pdata->lis302dl_bitbang_reg_read)(lis, reg);
85334 +}
85335 +
85336 +static void __reg_write(struct lis302dl_info *lis, u8 reg, u8 val)
85337 +{
85338 +       (lis->pdata->lis302dl_bitbang_reg_write)(lis, reg, val);
85339 +}
85340 +
85341 +static void __reg_set_bit_mask(struct lis302dl_info *lis, u8 reg, u8 mask,
85342 +               u8 val)
85343 +{
85344 +       u_int8_t tmp;
85345 +
85346 +       val &= mask;
85347 +
85348 +       tmp = __reg_read(lis, reg);
85349 +       tmp &= ~mask;
85350 +       tmp |= val;
85351 +       __reg_write(lis, reg, tmp);
85352 +}
85353 +
85354 +static int __ms_to_duration(struct lis302dl_info *lis, int ms)
85355 +{
85356 +       /* If we have 400 ms sampling rate, the stepping is 2.5 ms,
85357 +        * on 100 ms the stepping is 10ms */
85358 +       if (lis->flags & LIS302DL_F_DR)
85359 +               return min((ms * 10) / 25, 637);
85360 +
85361 +       return min(ms / 10, 2550);
85362 +}
85363 +
85364 +static int __duration_to_ms(struct lis302dl_info *lis, int duration)
85365 +{
85366 +       if (lis->flags & LIS302DL_F_DR)
85367 +               return (duration * 25) / 10;
85368 +
85369 +       return duration * 10;
85370 +}
85371 +
85372 +static u8 __mg_to_threshold(struct lis302dl_info *lis, int mg)
85373 +{
85374 +       /* If FS is set each bit is 71mg, otherwise 18mg. The THS register
85375 +        * has 7 bits for the threshold value */
85376 +       if (lis->flags & LIS302DL_F_FS)
85377 +               return min(mg / 71, 127);
85378 +
85379 +       return min(mg / 18, 127);
85380 +}
85381 +
85382 +static int __threshold_to_mg(struct lis302dl_info *lis, u8 threshold)
85383 +{
85384 +       if (lis->flags & LIS302DL_F_FS)
85385 +               return threshold * 71;
85386 +
85387 +       return threshold * 18;
85388 +}
85389 +
85390 +/* interrupt handling related */
85391 +
85392 +enum lis302dl_intmode {
85393 +       LIS302DL_INTMODE_GND            = 0x00,
85394 +       LIS302DL_INTMODE_FF_WU_1        = 0x01,
85395 +       LIS302DL_INTMODE_FF_WU_2        = 0x02,
85396 +       LIS302DL_INTMODE_FF_WU_12       = 0x03,
85397 +       LIS302DL_INTMODE_DATA_READY     = 0x04,
85398 +       LIS302DL_INTMODE_CLICK          = 0x07,
85399 +};
85400 +
85401 +static void __lis302dl_int_mode(struct device *dev, int int_pin,
85402 +                             enum lis302dl_intmode mode)
85403 +{
85404 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85405 +
85406 +       switch (int_pin) {
85407 +       case 1:
85408 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL3, 0x07, mode);
85409 +               break;
85410 +       case 2:
85411 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL3, 0x38, mode << 3);
85412 +               break;
85413 +       default:
85414 +               BUG();
85415 +       }
85416 +}
85417 +
85418 +static void __enable_wakeup(struct lis302dl_info *lis)
85419 +{
85420 +       __reg_write(lis, LIS302DL_REG_CTRL1, 0);
85421 +
85422 +       /* First zero to get to a known state */
85423 +       __reg_write(lis, LIS302DL_REG_FF_WU_CFG_1, LIS302DL_FFWUCFG_XHIE |
85424 +                       LIS302DL_FFWUCFG_YHIE | LIS302DL_FFWUCFG_ZHIE |
85425 +                       LIS302DL_FFWUCFG_LIR);
85426 +       __reg_write(lis, LIS302DL_REG_FF_WU_THS_1,
85427 +                       __mg_to_threshold(lis, lis->wakeup.threshold));
85428 +       __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1,
85429 +                       __ms_to_duration(lis, lis->wakeup.duration));
85430 +
85431 +       /* Route the interrupt for wakeup */
85432 +       __lis302dl_int_mode(lis->dev, 1,
85433 +                       LIS302DL_INTMODE_FF_WU_1);
85434 +
85435 +       __reg_read(lis, LIS302DL_REG_HP_FILTER_RESET);
85436 +       __reg_read(lis, LIS302DL_REG_OUT_X);
85437 +       __reg_read(lis, LIS302DL_REG_OUT_Y);
85438 +       __reg_read(lis, LIS302DL_REG_OUT_Z);
85439 +       __reg_read(lis, LIS302DL_REG_STATUS);
85440 +       __reg_read(lis, LIS302DL_REG_FF_WU_SRC_1);
85441 +       __reg_read(lis, LIS302DL_REG_FF_WU_SRC_2);
85442 +       __reg_write(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_PD | 7);
85443 +}
85444 +
85445 +static void __enable_data_collection(struct lis302dl_info *lis)
85446 +{
85447 +       u_int8_t ctrl1 = LIS302DL_CTRL1_PD | LIS302DL_CTRL1_Xen |
85448 +                        LIS302DL_CTRL1_Yen | LIS302DL_CTRL1_Zen;
85449 +
85450 +       /* make sure we're powered up and generate data ready */
85451 +       __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, ctrl1, ctrl1);
85452 +
85453 +       /* If the threshold is zero, let the device generated an interrupt
85454 +        * on each datum */
85455 +       if (lis->threshold == 0) {
85456 +               __reg_write(lis, LIS302DL_REG_CTRL2, 0);
85457 +               __lis302dl_int_mode(lis->dev, 1, LIS302DL_INTMODE_DATA_READY);
85458 +               __lis302dl_int_mode(lis->dev, 2, LIS302DL_INTMODE_DATA_READY);
85459 +       } else {
85460 +               __reg_write(lis, LIS302DL_REG_CTRL2,
85461 +                               LIS302DL_CTRL2_HPFF1);
85462 +               __reg_write(lis, LIS302DL_REG_FF_WU_THS_1,
85463 +                               __mg_to_threshold(lis, lis->threshold));
85464 +               __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1,
85465 +                               __ms_to_duration(lis, lis->duration));
85466 +
85467 +               /* Clear the HP filter "starting point" */
85468 +               __reg_read(lis, LIS302DL_REG_HP_FILTER_RESET);
85469 +               __reg_write(lis, LIS302DL_REG_FF_WU_CFG_1,
85470 +                               LIS302DL_FFWUCFG_XHIE | LIS302DL_FFWUCFG_YHIE |
85471 +                               LIS302DL_FFWUCFG_ZHIE | LIS302DL_FFWUCFG_LIR);
85472 +               __lis302dl_int_mode(lis->dev, 1, LIS302DL_INTMODE_FF_WU_12);
85473 +               __lis302dl_int_mode(lis->dev, 2, LIS302DL_INTMODE_FF_WU_12);
85474 +       }
85475 +}
85476 +
85477 +#if 0
85478 +static void _report_btn_single(struct input_dev *inp, int btn)
85479 +{
85480 +       input_report_key(inp, btn, 1);
85481 +       input_sync(inp);
85482 +       input_report_key(inp, btn, 0);
85483 +}
85484 +
85485 +static void _report_btn_double(struct input_dev *inp, int btn)
85486 +{
85487 +       input_report_key(inp, btn, 1);
85488 +       input_sync(inp);
85489 +       input_report_key(inp, btn, 0);
85490 +       input_sync(inp);
85491 +       input_report_key(inp, btn, 1);
85492 +       input_sync(inp);
85493 +       input_report_key(inp, btn, 0);
85494 +}
85495 +#endif
85496 +
85497 +
85498 +static void lis302dl_bitbang_read_sample(struct lis302dl_info *lis)
85499 +{
85500 +       u8 data = 0xc0 | LIS302DL_REG_OUT_X; /* read, autoincrement */
85501 +       u8 read[5];
85502 +       unsigned long flags;
85503 +       int mg_per_sample;
85504 +
85505 +       local_irq_save(flags);
85506 +       mg_per_sample = __threshold_to_mg(lis, 1);
85507 +
85508 +       (lis->pdata->lis302dl_bitbang)(lis, &data, 1, &read[0], 5);
85509 +
85510 +       local_irq_restore(flags);
85511 +
85512 +       input_report_rel(lis->input_dev, REL_X, mg_per_sample * (s8)read[0]);
85513 +       input_report_rel(lis->input_dev, REL_Y, mg_per_sample * (s8)read[2]);
85514 +       input_report_rel(lis->input_dev, REL_Z, mg_per_sample * (s8)read[4]);
85515 +
85516 +       input_sync(lis->input_dev);
85517 +
85518 +       /* Reset the HP filter */
85519 +       __reg_read(lis, LIS302DL_REG_HP_FILTER_RESET);
85520 +       __reg_read(lis, LIS302DL_REG_FF_WU_SRC_1);
85521 +}
85522 +
85523 +static irqreturn_t lis302dl_interrupt(int irq, void *_lis)
85524 +{
85525 +       struct lis302dl_info *lis = _lis;
85526 +
85527 +       lis302dl_bitbang_read_sample(lis);
85528 +       return IRQ_HANDLED;
85529 +}
85530 +
85531 +/* sysfs */
85532 +
85533 +static ssize_t show_rate(struct device *dev, struct device_attribute *attr,
85534 +                        char *buf)
85535 +{
85536 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85537 +       u8 ctrl1;
85538 +       unsigned long flags;
85539 +
85540 +       local_irq_save(flags);
85541 +       ctrl1 = __reg_read(lis, LIS302DL_REG_CTRL1);
85542 +       local_irq_restore(flags);
85543 +
85544 +       return sprintf(buf, "%d\n", ctrl1 & LIS302DL_CTRL1_DR ? 400 : 100);
85545 +}
85546 +
85547 +static ssize_t set_rate(struct device *dev, struct device_attribute *attr,
85548 +                       const char *buf, size_t count)
85549 +{
85550 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85551 +       unsigned long flags;
85552 +
85553 +       local_irq_save(flags);
85554 +
85555 +       if (!strcmp(buf, "400\n")) {
85556 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_DR,
85557 +                                LIS302DL_CTRL1_DR);
85558 +               lis->flags |= LIS302DL_F_DR;
85559 +       } else {
85560 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_DR,
85561 +                               0);
85562 +               lis->flags &= ~LIS302DL_F_DR;
85563 +       }
85564 +       local_irq_restore(flags);
85565 +
85566 +       return count;
85567 +}
85568 +
85569 +static DEVICE_ATTR(sample_rate, S_IRUGO | S_IWUSR, show_rate, set_rate);
85570 +
85571 +static ssize_t show_scale(struct device *dev, struct device_attribute *attr,
85572 +                         char *buf)
85573 +{
85574 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85575 +       u_int8_t ctrl1;
85576 +       unsigned long flags;
85577 +
85578 +       local_irq_save(flags);
85579 +       ctrl1 = __reg_read(lis, LIS302DL_REG_CTRL1);
85580 +       local_irq_restore(flags);
85581 +
85582 +       return sprintf(buf, "%s\n", ctrl1 & LIS302DL_CTRL1_FS ? "9.2" : "2.3");
85583 +}
85584 +
85585 +static ssize_t set_scale(struct device *dev, struct device_attribute *attr,
85586 +                        const char *buf, size_t count)
85587 +{
85588 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85589 +       unsigned long flags;
85590 +
85591 +       local_irq_save(flags);
85592 +
85593 +       if (!strcmp(buf, "9.2\n")) {
85594 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_FS,
85595 +                                LIS302DL_CTRL1_FS);
85596 +               lis->flags |= LIS302DL_F_FS;
85597 +       } else {
85598 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_FS,
85599 +                               0);
85600 +               lis->flags &= ~LIS302DL_F_FS;
85601 +       }
85602 +
85603 +       if (lis->flags & LIS302DL_F_INPUT_OPEN)
85604 +               __enable_data_collection(lis);
85605 +
85606 +       local_irq_restore(flags);
85607 +
85608 +       return count;
85609 +}
85610 +
85611 +static DEVICE_ATTR(full_scale, S_IRUGO | S_IWUSR, show_scale, set_scale);
85612 +
85613 +static ssize_t show_threshold(struct device *dev, struct device_attribute *attr,
85614 +                char *buf)
85615 +{
85616 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85617 +
85618 +       /* Display the device view of the threshold setting */
85619 +       return sprintf(buf, "%d\n", __threshold_to_mg(lis,
85620 +                       __mg_to_threshold(lis, lis->threshold)));
85621 +}
85622 +
85623 +static ssize_t set_threshold(struct device *dev, struct device_attribute *attr,
85624 +                const char *buf, size_t count)
85625 +{
85626 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85627 +       unsigned int val;
85628 +
85629 +       if (sscanf(buf, "%u\n", &val) != 1)
85630 +               return -EINVAL;
85631 +       /* 8g is the maximum if FS is 1 */
85632 +       if (val > 8000)
85633 +               return -ERANGE;
85634 +
85635 +       /* Set the threshold and write it out if the device is used */
85636 +       lis->threshold = val;
85637 +
85638 +       if (lis->flags & LIS302DL_F_INPUT_OPEN) {
85639 +               unsigned long flags;
85640 +
85641 +               local_irq_save(flags);
85642 +               __enable_data_collection(lis);
85643 +               local_irq_restore(flags);
85644 +       }
85645 +
85646 +       return count;
85647 +}
85648 +
85649 +static DEVICE_ATTR(threshold, S_IRUGO | S_IWUSR, show_threshold, set_threshold);
85650 +
85651 +static ssize_t show_duration(struct device *dev, struct device_attribute *attr,
85652 +                char *buf)
85653 +{
85654 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85655 +
85656 +       return sprintf(buf, "%d\n", __duration_to_ms(lis,
85657 +                       __ms_to_duration(lis, lis->duration)));
85658 +}
85659 +
85660 +static ssize_t set_duration(struct device *dev, struct device_attribute *attr,
85661 +                const char *buf, size_t count)
85662 +{
85663 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85664 +       unsigned int val;
85665 +
85666 +       if (sscanf(buf, "%u\n", &val) != 1)
85667 +               return -EINVAL;
85668 +       if (val > 2550)
85669 +               return -ERANGE;
85670 +
85671 +       lis->duration = val;
85672 +       if (lis->flags & LIS302DL_F_INPUT_OPEN)
85673 +               __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1,
85674 +                               __ms_to_duration(lis, lis->duration));
85675 +
85676 +       return count;
85677 +}
85678 +
85679 +static DEVICE_ATTR(duration, S_IRUGO | S_IWUSR, show_duration, set_duration);
85680 +
85681 +static ssize_t lis302dl_dump(struct device *dev, struct device_attribute *attr,
85682 +                                                                     char *buf)
85683 +{
85684 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85685 +       int n = 0;
85686 +       u8 reg[0x40];
85687 +       char *end = buf;
85688 +       unsigned long flags;
85689 +
85690 +       local_irq_save(flags);
85691 +
85692 +       for (n = 0; n < sizeof(reg); n++)
85693 +               reg[n] = __reg_read(lis, n);
85694 +
85695 +       local_irq_restore(flags);
85696 +
85697 +       for (n = 0; n < sizeof(reg); n += 16) {
85698 +               hex_dump_to_buffer(reg + n, 16, 16, 1, end, 128, 0);
85699 +               end += strlen(end);
85700 +               *end++ = '\n';
85701 +               *end++ = '\0';
85702 +       }
85703 +
85704 +       return end - buf;
85705 +}
85706 +static DEVICE_ATTR(dump, S_IRUGO, lis302dl_dump, NULL);
85707 +
85708 +/* Configure freefall/wakeup interrupts */
85709 +static ssize_t set_wakeup_threshold(struct device *dev,
85710 +               struct device_attribute *attr, const char *buf, size_t count)
85711 +{
85712 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85713 +       unsigned int threshold;
85714 +
85715 +       if (sscanf(buf, "%u\n", &threshold) != 1)
85716 +               return -EINVAL;
85717 +
85718 +       if (threshold > 8000)
85719 +               return -ERANGE;
85720 +
85721 +       /* Zero turns the feature off */
85722 +       if (threshold == 0) {
85723 +               if (lis->flags & LIS302DL_F_IRQ_WAKE) {
85724 +                       disable_irq_wake(lis->pdata->interrupt);
85725 +                       lis->flags &= ~LIS302DL_F_IRQ_WAKE;
85726 +               }
85727 +
85728 +               return count;
85729 +       }
85730 +
85731 +       lis->wakeup.threshold = threshold;
85732 +
85733 +       if (!(lis->flags & LIS302DL_F_IRQ_WAKE)) {
85734 +               enable_irq_wake(lis->pdata->interrupt);
85735 +               lis->flags |= LIS302DL_F_IRQ_WAKE;
85736 +       }
85737 +
85738 +       return count;
85739 +}
85740 +
85741 +static ssize_t show_wakeup_threshold(struct device *dev,
85742 +               struct device_attribute *attr, char *buf)
85743 +{
85744 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85745 +
85746 +       /* All events off? */
85747 +       if (lis->wakeup.threshold == 0)
85748 +               return sprintf(buf, "off\n");
85749 +
85750 +       return sprintf(buf, "%u\n", lis->wakeup.threshold);
85751 +}
85752 +
85753 +static DEVICE_ATTR(wakeup_threshold, S_IRUGO | S_IWUSR, show_wakeup_threshold,
85754 +               set_wakeup_threshold);
85755 +
85756 +static ssize_t set_wakeup_duration(struct device *dev,
85757 +               struct device_attribute *attr, const char *buf, size_t count)
85758 +{
85759 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85760 +       unsigned int duration;
85761 +
85762 +       if (sscanf(buf, "%u\n", &duration) != 1)
85763 +               return -EINVAL;
85764 +
85765 +       if (duration > 2550)
85766 +               return -ERANGE;
85767 +
85768 +       lis->wakeup.duration = duration;
85769 +
85770 +       return count;
85771 +}
85772 +
85773 +static ssize_t show_wakeup_duration(struct device *dev,
85774 +               struct device_attribute *attr, char *buf)
85775 +{
85776 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
85777 +
85778 +       return sprintf(buf, "%u\n", lis->wakeup.duration);
85779 +}
85780 +
85781 +static DEVICE_ATTR(wakeup_duration, S_IRUGO | S_IWUSR, show_wakeup_duration,
85782 +               set_wakeup_duration);
85783 +
85784 +static struct attribute *lis302dl_sysfs_entries[] = {
85785 +       &dev_attr_sample_rate.attr,
85786 +       &dev_attr_full_scale.attr,
85787 +       &dev_attr_threshold.attr,
85788 +       &dev_attr_duration.attr,
85789 +       &dev_attr_dump.attr,
85790 +       &dev_attr_wakeup_threshold.attr,
85791 +       &dev_attr_wakeup_duration.attr,
85792 +       NULL
85793 +};
85794 +
85795 +static struct attribute_group lis302dl_attr_group = {
85796 +       .name   = NULL,
85797 +       .attrs  = lis302dl_sysfs_entries,
85798 +};
85799 +
85800 +/* input device handling and driver core interaction */
85801 +
85802 +static int lis302dl_input_open(struct input_dev *inp)
85803 +{
85804 +       struct lis302dl_info *lis = input_get_drvdata(inp);
85805 +       unsigned long flags;
85806 +
85807 +       local_irq_save(flags);
85808 +
85809 +       __enable_data_collection(lis);
85810 +       lis->flags |= LIS302DL_F_INPUT_OPEN;
85811 +
85812 +       local_irq_restore(flags);
85813 +
85814 +       return 0;
85815 +}
85816 +
85817 +static void lis302dl_input_close(struct input_dev *inp)
85818 +{
85819 +       struct lis302dl_info *lis = input_get_drvdata(inp);
85820 +       u_int8_t ctrl1 = LIS302DL_CTRL1_Xen | LIS302DL_CTRL1_Yen |
85821 +                        LIS302DL_CTRL1_Zen;
85822 +       unsigned long flags;
85823 +
85824 +       local_irq_save(flags);
85825 +
85826 +       /* since the input core already serializes access and makes sure we
85827 +        * only see close() for the close of the last user, we can safely
85828 +        * disable the data ready events */
85829 +       __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, ctrl1, 0x00);
85830 +       lis->flags &= ~LIS302DL_F_INPUT_OPEN;
85831 +
85832 +       /* however, don't power down the whole device if still needed */
85833 +       if (!(lis->flags & LIS302DL_F_WUP_FF ||
85834 +             lis->flags & LIS302DL_F_WUP_CLICK)) {
85835 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_PD,
85836 +                                0x00);
85837 +       }
85838 +       local_irq_restore(flags);
85839 +}
85840 +
85841 +/* get the device to reload its coefficients from EEPROM and wait for it
85842 + * to complete
85843 + */
85844 +
85845 +static int __lis302dl_reset_device(struct lis302dl_info *lis)
85846 +{
85847 +       int timeout = 10;
85848 +
85849 +       __reg_write(lis, LIS302DL_REG_CTRL2,
85850 +                       LIS302DL_CTRL2_BOOT | LIS302DL_CTRL2_FDS);
85851 +
85852 +       while ((__reg_read(lis, LIS302DL_REG_CTRL2)
85853 +                       & LIS302DL_CTRL2_BOOT) && (timeout--))
85854 +               mdelay(1);
85855 +
85856 +       return !!(timeout < 0);
85857 +}
85858 +
85859 +static int __devinit lis302dl_probe(struct platform_device *pdev)
85860 +{
85861 +       int rc;
85862 +       struct lis302dl_info *lis;
85863 +       u_int8_t wai;
85864 +       unsigned long flags;
85865 +       struct lis302dl_platform_data *pdata = pdev->dev.platform_data;
85866 +
85867 +       lis = kzalloc(sizeof(*lis), GFP_KERNEL);
85868 +       if (!lis)
85869 +               return -ENOMEM;
85870 +
85871 +       lis->dev = &pdev->dev;
85872 +
85873 +       dev_set_drvdata(lis->dev, lis);
85874 +
85875 +       lis->pdata = pdata;
85876 +
85877 +       rc = sysfs_create_group(&lis->dev->kobj, &lis302dl_attr_group);
85878 +       if (rc) {
85879 +               dev_err(lis->dev, "error creating sysfs group\n");
85880 +               goto bail_free_lis;
85881 +       }
85882 +
85883 +       /* initialize input layer details */
85884 +       lis->input_dev = input_allocate_device();
85885 +       if (!lis->input_dev) {
85886 +               dev_err(lis->dev, "Unable to allocate input device\n");
85887 +               goto bail_sysfs;
85888 +       }
85889 +
85890 +       input_set_drvdata(lis->input_dev, lis);
85891 +       lis->input_dev->name = pdata->name;
85892 +        /* SPI Bus not defined as a valid bus for input subsystem*/
85893 +       lis->input_dev->id.bustype = BUS_I2C; /* lie about it */
85894 +       lis->input_dev->open = lis302dl_input_open;
85895 +       lis->input_dev->close = lis302dl_input_close;
85896 +
85897 +       rc = input_register_device(lis->input_dev);
85898 +       if (rc) {
85899 +               dev_err(lis->dev, "error %d registering input device\n", rc);
85900 +               goto bail_inp_dev;
85901 +       }
85902 +
85903 +       local_irq_save(flags);
85904 +       /* Configure our IO */
85905 +       (lis->pdata->lis302dl_suspend_io)(lis, 1);
85906 +
85907 +       wai = __reg_read(lis, LIS302DL_REG_WHO_AM_I);
85908 +       if (wai != LIS302DL_WHO_AM_I_MAGIC) {
85909 +               dev_err(lis->dev, "unknown who_am_i signature 0x%02x\n", wai);
85910 +               dev_set_drvdata(lis->dev, NULL);
85911 +               rc = -ENODEV;
85912 +               local_irq_restore(flags);
85913 +               goto bail_inp_reg;
85914 +       }
85915 +
85916 +       set_bit(EV_REL, lis->input_dev->evbit);
85917 +       set_bit(REL_X, lis->input_dev->relbit);
85918 +       set_bit(REL_Y, lis->input_dev->relbit);
85919 +       set_bit(REL_Z, lis->input_dev->relbit);
85920 +/*     set_bit(EV_KEY, lis->input_dev->evbit);
85921 +       set_bit(BTN_X, lis->input_dev->keybit);
85922 +       set_bit(BTN_Y, lis->input_dev->keybit);
85923 +       set_bit(BTN_Z, lis->input_dev->keybit);
85924 +*/
85925 +       lis->threshold = 0;
85926 +       lis->duration = 0;
85927 +       memset(&lis->wakeup, 0, sizeof(lis->wakeup));
85928 +
85929 +       if (__lis302dl_reset_device(lis))
85930 +               dev_err(lis->dev, "device BOOT reload failed\n");
85931 +
85932 +       /* force us powered */
85933 +       __reg_write(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_PD |
85934 +                       LIS302DL_CTRL1_Xen |
85935 +                       LIS302DL_CTRL1_Yen |
85936 +                       LIS302DL_CTRL1_Zen);
85937 +       mdelay(1);
85938 +
85939 +       __reg_write(lis, LIS302DL_REG_CTRL2, 0);
85940 +       __reg_write(lis, LIS302DL_REG_CTRL3,
85941 +                       LIS302DL_CTRL3_PP_OD | LIS302DL_CTRL3_IHL);
85942 +       __reg_write(lis, LIS302DL_REG_FF_WU_THS_1, 0x0);
85943 +       __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1, 0x00);
85944 +       __reg_write(lis, LIS302DL_REG_FF_WU_CFG_1, 0x0);
85945 +
85946 +       /* start off in powered down mode; we power up when someone opens us */
85947 +       __reg_write(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_Xen |
85948 +                       LIS302DL_CTRL1_Yen | LIS302DL_CTRL1_Zen);
85949 +
85950 +       if (pdata->open_drain)
85951 +               /* switch interrupt to open collector, active-low */
85952 +               __reg_write(lis, LIS302DL_REG_CTRL3,
85953 +                               LIS302DL_CTRL3_PP_OD | LIS302DL_CTRL3_IHL);
85954 +       else
85955 +               /* push-pull, active-low */
85956 +               __reg_write(lis, LIS302DL_REG_CTRL3, LIS302DL_CTRL3_IHL);
85957 +
85958 +       __lis302dl_int_mode(lis->dev, 1, LIS302DL_INTMODE_GND);
85959 +       __lis302dl_int_mode(lis->dev, 2, LIS302DL_INTMODE_GND);
85960 +
85961 +       __reg_read(lis, LIS302DL_REG_STATUS);
85962 +       __reg_read(lis, LIS302DL_REG_FF_WU_SRC_1);
85963 +       __reg_read(lis, LIS302DL_REG_FF_WU_SRC_2);
85964 +       __reg_read(lis, LIS302DL_REG_CLICK_SRC);
85965 +       local_irq_restore(flags);
85966 +
85967 +       dev_info(lis->dev, "Found %s\n", pdata->name);
85968 +
85969 +       lis->pdata = pdata;
85970 +
85971 +       set_irq_handler(lis->pdata->interrupt, handle_level_irq);
85972 +
85973 +       rc = request_irq(lis->pdata->interrupt, lis302dl_interrupt,
85974 +                        IRQF_TRIGGER_LOW, "lis302dl", lis);
85975 +
85976 +       if (rc < 0) {
85977 +               dev_err(lis->dev, "error requesting IRQ %d\n",
85978 +                       lis->pdata->interrupt);
85979 +               goto bail_inp_reg;
85980 +       }
85981 +       return 0;
85982 +
85983 +bail_inp_reg:
85984 +       input_unregister_device(lis->input_dev);
85985 +bail_inp_dev:
85986 +       input_free_device(lis->input_dev);
85987 +bail_sysfs:
85988 +       sysfs_remove_group(&lis->dev->kobj, &lis302dl_attr_group);
85989 +bail_free_lis:
85990 +       kfree(lis);
85991 +       return rc;
85992 +}
85993 +
85994 +static int __devexit lis302dl_remove(struct platform_device *pdev)
85995 +{
85996 +       struct lis302dl_info *lis = dev_get_drvdata(&pdev->dev);
85997 +       unsigned long flags;
85998 +
85999 +       /* Disable interrupts */
86000 +       if (lis->flags & LIS302DL_F_IRQ_WAKE)
86001 +               disable_irq_wake(lis->pdata->interrupt);
86002 +       free_irq(lis->pdata->interrupt, lis);
86003 +
86004 +       /* Reset and power down the device */
86005 +       local_irq_save(flags);
86006 +       __reg_write(lis, LIS302DL_REG_CTRL3, 0x00);
86007 +       __reg_write(lis, LIS302DL_REG_CTRL2, 0x00);
86008 +       __reg_write(lis, LIS302DL_REG_CTRL1, 0x00);
86009 +       local_irq_restore(flags);
86010 +
86011 +       /* Cleanup resources */
86012 +       sysfs_remove_group(&pdev->dev.kobj, &lis302dl_attr_group);
86013 +       input_unregister_device(lis->input_dev);
86014 +       if (lis->input_dev)
86015 +               input_free_device(lis->input_dev);
86016 +       dev_set_drvdata(lis->dev, NULL);
86017 +       kfree(lis);
86018 +
86019 +       return 0;
86020 +}
86021 +
86022 +#ifdef CONFIG_PM
86023 +
86024 +static u8 regs_to_save[] = {
86025 +       LIS302DL_REG_CTRL1,
86026 +       LIS302DL_REG_CTRL2,
86027 +       LIS302DL_REG_CTRL3,
86028 +       LIS302DL_REG_FF_WU_CFG_1,
86029 +       LIS302DL_REG_FF_WU_THS_1,
86030 +       LIS302DL_REG_FF_WU_DURATION_1,
86031 +       LIS302DL_REG_FF_WU_CFG_2,
86032 +       LIS302DL_REG_FF_WU_THS_2,
86033 +       LIS302DL_REG_FF_WU_DURATION_2,
86034 +       LIS302DL_REG_CLICK_CFG,
86035 +       LIS302DL_REG_CLICK_THSY_X,
86036 +       LIS302DL_REG_CLICK_THSZ,
86037 +       LIS302DL_REG_CLICK_TIME_LIMIT,
86038 +       LIS302DL_REG_CLICK_LATENCY,
86039 +       LIS302DL_REG_CLICK_WINDOW,
86040 +
86041 +};
86042 +
86043 +static int lis302dl_suspend(struct platform_device *pdev, pm_message_t state)
86044 +{
86045 +       struct lis302dl_info *lis = dev_get_drvdata(&pdev->dev);
86046 +       unsigned long flags;
86047 +       u_int8_t tmp;
86048 +       int n;
86049 +
86050 +       /* determine if we want to wake up from the accel. */
86051 +       if (lis->flags & LIS302DL_F_WUP_CLICK)
86052 +               return 0;
86053 +
86054 +       disable_irq(lis->pdata->interrupt);
86055 +       local_irq_save(flags);
86056 +
86057 +       /*
86058 +        * When we share SPI over multiple sensors, there is a race here
86059 +        * that one or more sensors will lose.  In that case, the shared
86060 +        * SPI bus GPIO will be in sleep mode and partially pulled down.  So
86061 +        * we explicitly put our IO into "wake" mode here before the final
86062 +        * traffic to the sensor.
86063 +        */
86064 +       (lis->pdata->lis302dl_suspend_io)(lis, 1);
86065 +
86066 +       /* save registers */
86067 +       for (n = 0; n < ARRAY_SIZE(regs_to_save); n++)
86068 +               lis->regs[regs_to_save[n]] =
86069 +                       __reg_read(lis, regs_to_save[n]);
86070 +
86071 +       /* power down or enable wakeup */
86072 +
86073 +       if (lis->wakeup.threshold == 0) {
86074 +               tmp = __reg_read(lis, LIS302DL_REG_CTRL1);
86075 +               tmp &= ~LIS302DL_CTRL1_PD;
86076 +               __reg_write(lis, LIS302DL_REG_CTRL1, tmp);
86077 +       } else
86078 +               __enable_wakeup(lis);
86079 +
86080 +       /* place our IO to the device in sleep-compatible states */
86081 +       (lis->pdata->lis302dl_suspend_io)(lis, 0);
86082 +
86083 +       local_irq_restore(flags);
86084 +
86085 +       return 0;
86086 +}
86087 +
86088 +static int lis302dl_resume(struct platform_device *pdev)
86089 +{
86090 +       struct lis302dl_info *lis = dev_get_drvdata(&pdev->dev);
86091 +       unsigned long flags;
86092 +       int n;
86093 +
86094 +       if (lis->flags & LIS302DL_F_WUP_CLICK)
86095 +               return 0;
86096 +
86097 +       local_irq_save(flags);
86098 +
86099 +       /* get our IO to the device back in operational states */
86100 +       (lis->pdata->lis302dl_suspend_io)(lis, 1);
86101 +
86102 +       /* resume from powerdown first! */
86103 +       __reg_write(lis, LIS302DL_REG_CTRL1,
86104 +                       LIS302DL_CTRL1_PD |
86105 +                       LIS302DL_CTRL1_Xen |
86106 +                       LIS302DL_CTRL1_Yen |
86107 +                       LIS302DL_CTRL1_Zen);
86108 +       mdelay(1);
86109 +
86110 +       if (__lis302dl_reset_device(lis))
86111 +               dev_err(&pdev->dev, "device BOOT reload failed\n");
86112 +
86113 +       lis->regs[LIS302DL_REG_CTRL1] |=        LIS302DL_CTRL1_PD |
86114 +                                               LIS302DL_CTRL1_Xen |
86115 +                                               LIS302DL_CTRL1_Yen |
86116 +                                               LIS302DL_CTRL1_Zen;
86117 +
86118 +       /* restore registers after resume */
86119 +       for (n = 0; n < ARRAY_SIZE(regs_to_save); n++)
86120 +               __reg_write(lis, regs_to_save[n], lis->regs[regs_to_save[n]]);
86121 +
86122 +       local_irq_restore(flags);
86123 +       enable_irq(lis->pdata->interrupt);
86124 +
86125 +       return 0;
86126 +}
86127 +#else
86128 +#define lis302dl_suspend       NULL
86129 +#define lis302dl_resume                NULL
86130 +#endif
86131 +
86132 +static struct platform_driver lis302dl_driver = {
86133 +       .driver = {
86134 +               .name   = "lis302dl",
86135 +               .owner  = THIS_MODULE,
86136 +       },
86137 +
86138 +       .probe   = lis302dl_probe,
86139 +       .remove  = __devexit_p(lis302dl_remove),
86140 +       .suspend = lis302dl_suspend,
86141 +       .resume  = lis302dl_resume,
86142 +};
86143 +
86144 +static int __devinit lis302dl_init(void)
86145 +{
86146 +       return platform_driver_register(&lis302dl_driver);
86147 +}
86148 +
86149 +static void __exit lis302dl_exit(void)
86150 +{
86151 +       platform_driver_unregister(&lis302dl_driver);
86152 +}
86153 +
86154 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
86155 +MODULE_LICENSE("GPL");
86156 +
86157 +module_init(lis302dl_init);
86158 +module_exit(lis302dl_exit);
86159 --- a/drivers/input/misc/Makefile
86160 +++ b/drivers/input/misc/Makefile
86161 @@ -22,3 +22,6 @@ obj-$(CONFIG_INPUT_UINPUT)            += uinput.o
86162  obj-$(CONFIG_INPUT_APANEL)             += apanel.o
86163  obj-$(CONFIG_INPUT_SGI_BTNS)           += sgi_btns.o
86164  obj-$(CONFIG_INPUT_GPIO_BUTTONS)       += gpio_buttons.o
86165 +obj-$(CONFIG_INPUT_LIS302DL)           += lis302dl.o
86166 +obj-$(CONFIG_INPUT_PCF50633_PMU)       += pcf50633-input.o
86167 +obj-$(CONFIG_INPUT_PCF50606_PMU)       += pcf50606-input.o
86168 --- /dev/null
86169 +++ b/drivers/input/misc/pcf50606-input.c
86170 @@ -0,0 +1,123 @@
86171 +/* Philips PCF50606 Input Driver
86172 + *
86173 + * (C) 2006-2008 by Openmoko, Inc.
86174 + * Author: Balaji Rao <balajirrao@openmoko.org>
86175 + * All rights reserved.
86176 + *
86177 + * Broken down from monstrous PCF50606 driver mainly by
86178 + * Harald Welte, Matt Hsu, Andy Green and Werner Almesberger
86179 + *
86180 + * This program is free software; you can redistribute it and/or
86181 + * modify it under the terms of the GNU General Public License as
86182 + * published by the Free Software Foundation; either version 2 of
86183 + * the License, or (at your option) any later version.
86184 + *
86185 + * This program is distributed in the hope that it will be useful,
86186 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
86187 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
86188 + * GNU General Public License for more details.
86189 + *
86190 + * You should have received a copy of the GNU General Public License
86191 + * along with this program; if not, write to the Free Software
86192 + * Foundation, Inc., 59 Temple Place, Suite 060, Boston,
86193 + * MA 02111-1307 USA
86194 + */
86195 +
86196 +#include <linux/input.h>
86197 +
86198 +#include <linux/mfd/pcf50606/core.h>
86199 +#include <linux/mfd/pcf50606/input.h>
86200 +
86201 +static void
86202 +pcf50606_input_irq(struct pcf50606 *pcf, int irq, void *data)
86203 +{
86204 +       struct input_dev *input_dev = pcf->input.input_dev;
86205 +       int onkey_released;
86206 +
86207 +       /* We report only one event depending on if the key status */
86208 +       onkey_released = pcf50606_reg_read(pcf, PCF50606_REG_OOCS) &
86209 +                                       PCF50606_OOCS_ONKEY;
86210 +
86211 +       if (irq == PCF50606_IRQ_ONKEYF && !onkey_released)
86212 +               input_report_key(input_dev, KEY_POWER, 1);
86213 +       else if (irq == PCF50606_IRQ_ONKEYR && onkey_released)
86214 +               input_report_key(input_dev, KEY_POWER, 0);
86215 +
86216 +       input_sync(input_dev);
86217 +}
86218 +
86219 +int __init pcf50606_input_probe(struct platform_device *pdev)
86220 +{
86221 +       struct pcf50606 *pcf;
86222 +       struct input_dev *input_dev;
86223 +       int ret;
86224 +
86225 +       pcf = platform_get_drvdata(pdev);
86226 +
86227 +       input_dev = input_allocate_device();
86228 +       if (!input_dev)
86229 +               return -ENODEV;
86230 +
86231 +       input_dev->name = "PCF50606 PMU events";
86232 +       input_dev->id.bustype = BUS_I2C;
86233 +
86234 +       input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
86235 +       set_bit(KEY_POWER, input_dev->keybit);
86236 +       set_bit(KEY_POWER2, input_dev->keybit);
86237 +
86238 +       ret = input_register_device(input_dev);
86239 +       if (ret)
86240 +               goto out;
86241 +
86242 +       pcf->input.input_dev = input_dev;
86243 +
86244 +       /* Currently we care only about ONKEY and USBINS/USBREM
86245 +        *
86246 +        * USBINS/USBREM are told to us by mbc driver as we can't setup
86247 +        * two handlers for an IRQ
86248 +        */
86249 +       pcf->irq_handler[PCF50606_IRQ_ONKEYR].handler = pcf50606_input_irq;
86250 +
86251 +       pcf->irq_handler[PCF50606_IRQ_ONKEYF].handler = pcf50606_input_irq;
86252 +
86253 +       return 0;
86254 +
86255 +out:
86256 +       input_free_device(input_dev);
86257 +       return ret;
86258 +}
86259 +
86260 +static int __devexit pcf50606_input_remove(struct platform_device *pdev)
86261 +{
86262 +       struct pcf50606 *pcf;
86263 +
86264 +       pcf = platform_get_drvdata(pdev);
86265 +       input_unregister_device(pcf->input.input_dev);
86266 +
86267 +       return 0;
86268 +}
86269 +
86270 +struct platform_driver pcf50606_input_driver = {
86271 +       .driver = {
86272 +               .name = "pcf50606-input",
86273 +       },
86274 +       .probe = pcf50606_input_probe,
86275 +       .remove = __devexit_p(pcf50606_input_remove),
86276 +};
86277 +
86278 +static int __init pcf50606_input_init(void)
86279 +{
86280 +               return platform_driver_register(&pcf50606_input_driver);
86281 +}
86282 +module_init(pcf50606_input_init);
86283 +
86284 +static void __exit pcf50606_input_exit(void)
86285 +{
86286 +               platform_driver_unregister(&pcf50606_input_driver);
86287 +}
86288 +module_exit(pcf50606_input_exit);
86289 +
86290 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
86291 +MODULE_DESCRIPTION("PCF50606 input driver");
86292 +MODULE_LICENSE("GPL");
86293 +MODULE_ALIAS("platform:pcf50606-input");
86294 --- /dev/null
86295 +++ b/drivers/input/misc/pcf50633-input.c
86296 @@ -0,0 +1,123 @@
86297 +/* Philips PCF50633 Input Driver
86298 + *
86299 + * (C) 2006-2008 by Openmoko, Inc.
86300 + * Author: Balaji Rao <balajirrao@openmoko.org>
86301 + * All rights reserved.
86302 + *
86303 + * Broken down from monstrous PCF50633 driver mainly by
86304 + * Harald Welte, Andy Green and Werner Almesberger
86305 + *
86306 + * This program is free software; you can redistribute it and/or
86307 + * modify it under the terms of the GNU General Public License as
86308 + * published by the Free Software Foundation; either version 2 of
86309 + * the License, or (at your option) any later version.
86310 + *
86311 + * This program is distributed in the hope that it will be useful,
86312 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
86313 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
86314 + * GNU General Public License for more details.
86315 + *
86316 + * You should have received a copy of the GNU General Public License
86317 + * along with this program; if not, write to the Free Software
86318 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
86319 + * MA 02111-1307 USA
86320 + */
86321 +
86322 +#include <linux/input.h>
86323 +
86324 +#include <linux/mfd/pcf50633/core.h>
86325 +#include <linux/mfd/pcf50633/input.h>
86326 +
86327 +static void
86328 +pcf50633_input_irq(struct pcf50633 *pcf, int irq, void *data)
86329 +{
86330 +       struct input_dev *input_dev = pcf->input.input_dev;
86331 +       int onkey_released;
86332 +
86333 +       /* We report only one event depending on if the key status */
86334 +       onkey_released = pcf50633_reg_read(pcf, PCF50633_REG_OOCSTAT) &
86335 +                                       PCF50633_OOCSTAT_ONKEY;
86336 +
86337 +       if (irq == PCF50633_IRQ_ONKEYF && !onkey_released)
86338 +               input_report_key(input_dev, KEY_POWER, 1);
86339 +       else if (irq == PCF50633_IRQ_ONKEYR && onkey_released)
86340 +               input_report_key(input_dev, KEY_POWER, 0);
86341 +
86342 +       input_sync(input_dev);
86343 +}
86344 +
86345 +int __init pcf50633_input_probe(struct platform_device *pdev)
86346 +{
86347 +       struct pcf50633 *pcf;
86348 +       struct input_dev *input_dev;
86349 +       int ret;
86350 +
86351 +       pcf = platform_get_drvdata(pdev);
86352 +
86353 +       input_dev = input_allocate_device();
86354 +       if (!input_dev)
86355 +               return -ENODEV;
86356 +
86357 +       input_dev->name = "GTA02 PMU events";
86358 +       input_dev->id.bustype = BUS_I2C;
86359 +
86360 +       input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
86361 +       set_bit(KEY_POWER, input_dev->keybit);
86362 +       set_bit(KEY_POWER2, input_dev->keybit);
86363 +
86364 +       ret = input_register_device(input_dev);
86365 +       if (ret)
86366 +               goto out;
86367 +
86368 +       pcf->input.input_dev = input_dev;
86369 +
86370 +       /* Currently we care only about ONKEY and USBINS/USBREM
86371 +        *
86372 +        * USBINS/USBREM are told to us by mbc driver as we can't setup
86373 +        * two handlers for an IRQ
86374 +        */
86375 +       pcf->irq_handler[PCF50633_IRQ_ONKEYR].handler = pcf50633_input_irq;
86376 +
86377 +       pcf->irq_handler[PCF50633_IRQ_ONKEYF].handler = pcf50633_input_irq;
86378 +
86379 +       return 0;
86380 +
86381 +out:
86382 +       input_free_device(input_dev);
86383 +       return ret;
86384 +}
86385 +
86386 +static int __devexit pcf50633_input_remove(struct platform_device *pdev)
86387 +{
86388 +       struct pcf50633 *pcf;
86389 +
86390 +       pcf = platform_get_drvdata(pdev);
86391 +       input_unregister_device(pcf->input.input_dev);
86392 +
86393 +       return 0;
86394 +}
86395 +
86396 +struct platform_driver pcf50633_input_driver = {
86397 +       .driver = {
86398 +               .name = "pcf50633-input",
86399 +       },
86400 +       .probe = pcf50633_input_probe,
86401 +       .remove = __devexit_p(pcf50633_input_remove),
86402 +};
86403 +
86404 +static int __init pcf50633_input_init(void)
86405 +{
86406 +               return platform_driver_register(&pcf50633_input_driver);
86407 +}
86408 +module_init(pcf50633_input_init);
86409 +
86410 +static void __exit pcf50633_input_exit(void)
86411 +{
86412 +               platform_driver_unregister(&pcf50633_input_driver);
86413 +}
86414 +module_exit(pcf50633_input_exit);
86415 +
86416 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
86417 +MODULE_DESCRIPTION("PCF50633 input driver");
86418 +MODULE_LICENSE("GPL");
86419 +MODULE_ALIAS("platform:pcf50633-input");
86420 --- a/drivers/input/mousedev.c
86421 +++ b/drivers/input/mousedev.c
86422 @@ -1016,6 +1016,7 @@ static const struct input_device_id mous
86423                 .evbit = { BIT_MASK(EV_KEY) | BIT_MASK(EV_REL) },
86424                 .relbit = { BIT_MASK(REL_WHEEL) },
86425         },      /* A separate scrollwheel */
86426 +#if 0
86427         {
86428                 .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
86429                                 INPUT_DEVICE_ID_MATCH_KEYBIT |
86430 @@ -1025,6 +1026,7 @@ static const struct input_device_id mous
86431                 .absbit = { BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) },
86432         },      /* A tablet like device, at least touch detection,
86433                    two absolute axes */
86434 +#endif
86435         {
86436                 .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
86437                                 INPUT_DEVICE_ID_MATCH_KEYBIT |
86438 --- a/drivers/input/touchscreen/Kconfig
86439 +++ b/drivers/input/touchscreen/Kconfig
86440 @@ -11,6 +11,50 @@ menuconfig INPUT_TOUCHSCREEN
86441
86442  if INPUT_TOUCHSCREEN
86443
86444 +menuconfig TOUCHSCREEN_FILTER
86445 +       boolean "Touchscreen Filtering"
86446 +       depends on INPUT_TOUCHSCREEN
86447 +       help
86448 +         Select this to include kernel touchscreen filter support.  The filters
86449 +         can be combined in any order in your machine init and the parameters
86450 +         for them can also be set there.
86451 +
86452 +if TOUCHSCREEN_FILTER
86453 +
86454 +config TOUCHSCREEN_FILTER_GROUP
86455 +       bool "Group Touchscreen Filter"
86456 +       depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
86457 +       default Y
86458 +       help
86459 +         Say Y here if you want to use the Group touchscreen filter, it
86460 +         avoids using atypical samples.
86461 +
86462 +config TOUCHSCREEN_FILTER_MEDIAN
86463 +       bool "Median Average Touchscreen Filter"
86464 +       depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
86465 +       default Y
86466 +       help
86467 +         Say Y here if you want to use the Median touchscreen filter, it's
86468 +         highly effective if you data is noisy with occasional excursions.
86469 +
86470 +config TOUCHSCREEN_FILTER_MEAN
86471 +       bool "Mean Average Touchscreen Filter"
86472 +       depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
86473 +       default Y
86474 +       help
86475 +         Say Y here if you want to use the Mean touchscreen filter, it
86476 +         can further improve decent quality data by removing jitter
86477 +
86478 +config TOUCHSCREEN_FILTER_LINEAR
86479 +       bool "Linear Touchscreen Filter"
86480 +       depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
86481 +       default Y
86482 +       help
86483 +         Say Y here if you want to use the Mean touchscreen filter, it
86484 +         enables the use of calibration data for the touchscreen.
86485 +
86486 +endif
86487 +
86488  config TOUCHSCREEN_ADS7846
86489         tristate "ADS7846/TSC2046 and ADS7843 based touchscreens"
86490         depends on SPI_MASTER
86491 @@ -71,6 +115,25 @@ config TOUCHSCREEN_FUJITSU
86492           To compile this driver as a module, choose M here: the
86493           module will be called fujitsu-ts.
86494
86495 +config TOUCHSCREEN_S3C2410
86496 +       tristate "Samsung S3C2410 touchscreen input driver"
86497 +       depends on ARCH_S3C2410 && INPUT && INPUT_TOUCHSCREEN
86498 +       select SERIO
86499 +       select TOUCHSCREEN_FILTER
86500 +       help
86501 +         Say Y here if you have the s3c2410 touchscreen.
86502 +
86503 +         If unsure, say N.
86504 +
86505 +         To compile this driver as a module, choose M here: the
86506 +         module will be called s3c2410_ts.
86507 +
86508 +config TOUCHSCREEN_S3C2410_DEBUG
86509 +       boolean "Samsung S3C2410 touchscreen debug messages"
86510 +       depends on TOUCHSCREEN_S3C2410
86511 +       help
86512 +         Select this if you want debug messages
86513 +
86514  config TOUCHSCREEN_GUNZE
86515         tristate "Gunze AHL-51S touchscreen"
86516         select SERIO
86517 @@ -376,4 +439,15 @@ config TOUCHSCREEN_TOUCHIT213
86518           To compile this driver as a module, choose M here: the
86519           module will be called touchit213.
86520
86521 +config TOUCHSCREEN_PCAP7200
86522 +       tristate "EETI Projected capacitive touchscreen controller"
86523 +       help
86524 +         Say Y here if you have the EETI PCAP7200 touchscreen
86525 +         controller chip in your system.
86526 +
86527 +         If unsure, say N.
86528 +
86529 +         To compile this driver as a module, choose M here: the
86530 +         module will be called pcap7200.
86531  endif
86532 +
86533 --- a/drivers/input/touchscreen/Makefile
86534 +++ b/drivers/input/touchscreen/Makefile
86535 @@ -31,3 +31,10 @@ wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9705)       +
86536  wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9712) += wm9712.o
86537  wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9713) += wm9713.o
86538  obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE)     += mainstone-wm97xx.o
86539 +obj-$(CONFIG_TOUCHSCREEN_S3C2410)      += s3c2410_ts.o
86540 +obj-$(CONFIG_TOUCHSCREEN_FILTER)       += ts_filter.o
86541 +obj-$(CONFIG_TOUCHSCREEN_FILTER_GROUP) += ts_filter_group.o
86542 +obj-$(CONFIG_TOUCHSCREEN_FILTER_LINEAR)        += ts_filter_linear.o
86543 +obj-$(CONFIG_TOUCHSCREEN_FILTER_MEDIAN)        += ts_filter_median.o
86544 +obj-$(CONFIG_TOUCHSCREEN_FILTER_MEAN)  += ts_filter_mean.o
86545 +obj-$(CONFIG_TOUCHSCREEN_PCAP7200)     += pcap7200_ts.o
86546 --- /dev/null
86547 +++ b/drivers/input/touchscreen/s3c2410_ts.c
86548 @@ -0,0 +1,618 @@
86549 +/*
86550 + * This program is free software; you can redistribute it and/or modify
86551 + * it under the terms of the GNU General Public License as published by
86552 + * the Free Software Foundation; either version 2 of the License, or
86553 + * (at your option) any later version.
86554 + *
86555 + * This program is distributed in the hope that it will be useful,
86556 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
86557 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
86558 + * GNU General Public License for more details.
86559 + *
86560 + * You should have received a copy of the GNU General Public License
86561 + * along with this program; if not, write to the Free Software
86562 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
86563 + *
86564 + * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
86565 + * iPAQ H1940 touchscreen support
86566 + *
86567 + * ChangeLog
86568 + *
86569 + * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
86570 + *      - added clock (de-)allocation code
86571 + *
86572 + * 2005-03-06: Arnaud Patard <arnaud.patard@rtp-net.org>
86573 + *      - h1940_ -> s3c2410 (this driver is now also used on the n30
86574 + *        machines :P)
86575 + *      - Debug messages are now enabled with the config option
86576 + *        TOUCHSCREEN_S3C2410_DEBUG
86577 + *      - Changed the way the value are read
86578 + *      - Input subsystem should now work
86579 + *      - Use ioremap and readl/writel
86580 + *
86581 + * 2005-03-23: Arnaud Patard <arnaud.patard@rtp-net.org>
86582 + *      - Make use of some undocumented features of the touchscreen
86583 + *        controller
86584 + *
86585 + * 2007-05-23: Harald Welte <laforge@openmoko.org>
86586 + *      - Add proper support for S32440
86587 + *
86588 + * 2008-06-23: Andy Green <andy@openmoko.com>
86589 + *      - removed averaging system
86590 + *      - added generic Touchscreen filter stuff
86591 + *
86592 + * 2008-11-27: Nelson Castillo <arhuaco@freaks-unidos.net>
86593 + *      - improve interrupt handling
86594 + */
86595 +
86596 +#include <linux/errno.h>
86597 +#include <linux/kernel.h>
86598 +#include <linux/module.h>
86599 +#include <linux/slab.h>
86600 +#include <linux/input.h>
86601 +#include <linux/init.h>
86602 +#include <linux/serio.h>
86603 +#include <linux/timer.h>
86604 +#include <linux/kfifo.h>
86605 +#include <linux/delay.h>
86606 +#include <linux/platform_device.h>
86607 +#include <linux/clk.h>
86608 +#include <asm/io.h>
86609 +#include <asm/irq.h>
86610 +
86611 +#include <mach/regs-gpio.h>
86612 +#include <mach/ts.h>
86613 +
86614 +#include <plat/regs-adc.h>
86615 +
86616 +#include <linux/ts_filter.h>
86617 +
86618 +/* For ts.dev.id.version */
86619 +#define S3C2410TSVERSION       0x0101
86620 +
86621 +#define TSC_SLEEP  (S3C2410_ADCTSC_PULL_UP_DISABLE | S3C2410_ADCTSC_XY_PST(0))
86622 +
86623 +#define WAIT4INT(x)  (((x)<<8) | \
86624 +                    S3C2410_ADCTSC_YM_SEN | \
86625 +                    S3C2410_ADCTSC_YP_SEN | \
86626 +                    S3C2410_ADCTSC_XP_SEN | \
86627 +                    S3C2410_ADCTSC_XY_PST(3))
86628 +
86629 +#define AUTOPST             (S3C2410_ADCTSC_YM_SEN | \
86630 +                     S3C2410_ADCTSC_YP_SEN | \
86631 +                     S3C2410_ADCTSC_XP_SEN | \
86632 +                     S3C2410_ADCTSC_AUTO_PST | \
86633 +                     S3C2410_ADCTSC_XY_PST(0))
86634 +
86635 +#define DEBUG_LVL    KERN_DEBUG
86636 +
86637 +MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
86638 +MODULE_DESCRIPTION("s3c2410 touchscreen driver");
86639 +MODULE_LICENSE("GPL");
86640 +
86641 +/*
86642 + * Definitions & global arrays.
86643 + */
86644 +
86645 +static char *s3c2410ts_name = "s3c2410 TouchScreen";
86646 +
86647 +#define TS_RELEASE_TIMEOUT (HZ >> 4)           /* ~ 60 milliseconds */
86648 +#define TS_EVENT_FIFO_SIZE (2 << 6) /* must be a power of 2 */
86649 +
86650 +#define TS_STATE_STANDBY 0 /* initial state */
86651 +#define TS_STATE_PRESSED 1
86652 +#define TS_STATE_RELEASE_PENDING 2
86653 +#define TS_STATE_RELEASE 3
86654 +
86655 +/*
86656 + * Per-touchscreen data.
86657 + */
86658 +
86659 +struct s3c2410ts {
86660 +       struct input_dev *dev;
86661 +       struct ts_filter *tsf[MAX_TS_FILTER_CHAIN];
86662 +       int coords[2]; /* just X and Y for us */
86663 +       int is_down;
86664 +       int state;
86665 +       struct kfifo *event_fifo;
86666 +};
86667 +
86668 +static struct s3c2410ts ts;
86669 +
86670 +static void __iomem *base_addr;
86671 +
86672 +/*
86673 + * A few low level functions.
86674 + */
86675 +
86676 +static inline void s3c2410_ts_connect(void)
86677 +{
86678 +       s3c2410_gpio_cfgpin(S3C2410_GPG12, S3C2410_GPG12_XMON);
86679 +       s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPG13_nXPON);
86680 +       s3c2410_gpio_cfgpin(S3C2410_GPG14, S3C2410_GPG14_YMON);
86681 +       s3c2410_gpio_cfgpin(S3C2410_GPG15, S3C2410_GPG15_nYPON);
86682 +}
86683 +
86684 +static void s3c2410_ts_start_adc_conversion(void)
86685 +{
86686 +       writel(S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST,
86687 +              base_addr + S3C2410_ADCTSC);
86688 +       writel(readl(base_addr + S3C2410_ADCCON) | S3C2410_ADCCON_ENABLE_START,
86689 +              base_addr + S3C2410_ADCCON);
86690 +}
86691 +
86692 +/*
86693 + * Just send the input events.
86694 + */
86695 +
86696 +enum ts_input_event {IE_DOWN = 0, IE_UP};
86697 +
86698 +static void ts_input_report(int event, int coords[])
86699 +{
86700 +#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
86701 +       static char *s[] = {"down", "up"};
86702 +       struct timeval tv;
86703 +
86704 +       do_gettimeofday(&tv);
86705 +#endif
86706 +
86707 +       if (event == IE_DOWN) {
86708 +               input_report_abs(ts.dev, ABS_X, coords[0]);
86709 +               input_report_abs(ts.dev, ABS_Y, coords[1]);
86710 +               input_report_key(ts.dev, BTN_TOUCH, 1);
86711 +               input_report_abs(ts.dev, ABS_PRESSURE, 1);
86712 +
86713 +#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
86714 +               printk(DEBUG_LVL "T:%06d %6s (X:%03d, Y:%03d)\n",
86715 +                      (int)tv.tv_usec, s[event], coords[0], coords[1]);
86716 +#endif
86717 +       } else {
86718 +               input_report_key(ts.dev, BTN_TOUCH, 0);
86719 +               input_report_abs(ts.dev, ABS_PRESSURE, 0);
86720 +
86721 +#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
86722 +               printk(DEBUG_LVL "T:%06d %6s\n",
86723 +                      (int)tv.tv_usec, s[event]);
86724 +#endif
86725 +       }
86726 +
86727 +       input_sync(ts.dev);
86728 +}
86729 +
86730 +/*
86731 + * Manage the state of the touchscreen.
86732 + */
86733 +
86734 +static void event_send_timer_f(unsigned long data);
86735 +
86736 +static struct timer_list event_send_timer =
86737 +               TIMER_INITIALIZER(event_send_timer_f, 0, 0);
86738 +
86739 +static void event_send_timer_f(unsigned long data)
86740 +{
86741 +       static unsigned long running;
86742 +       static int noop_counter;
86743 +       int event_type;
86744 +
86745 +       if (unlikely(test_and_set_bit(0, &running))) {
86746 +               mod_timer(&event_send_timer,
86747 +                         jiffies + TS_RELEASE_TIMEOUT);
86748 +               return;
86749 +       }
86750 +
86751 +       while (__kfifo_get(ts.event_fifo, (unsigned char *)&event_type,
86752 +                          sizeof(int))) {
86753 +               int buf[2];
86754 +
86755 +               switch (event_type) {
86756 +               case 'D':
86757 +                       if (ts.state == TS_STATE_RELEASE_PENDING)
86758 +                               /* Ignore short UP event */
86759 +                               ts.state = TS_STATE_PRESSED;
86760 +                       break;
86761 +
86762 +               case 'U':
86763 +                       ts.state = TS_STATE_RELEASE_PENDING;
86764 +                       break;
86765 +
86766 +               case 'P':
86767 +                       if (ts.is_down) /* stylus_action needs a conversion */
86768 +                               s3c2410_ts_start_adc_conversion();
86769 +
86770 +                       if (unlikely(__kfifo_get(ts.event_fifo,
86771 +                                                (unsigned char *)buf,
86772 +                                                sizeof(int) * 2)
86773 +                                    != sizeof(int) * 2))
86774 +                               goto ts_exit_error;
86775 +
86776 +                       ts_input_report(IE_DOWN, buf);
86777 +                       ts.state = TS_STATE_PRESSED;
86778 +                       break;
86779 +
86780 +               default:
86781 +                       goto ts_exit_error;
86782 +               }
86783 +
86784 +               noop_counter = 0;
86785 +       }
86786 +
86787 +       if (noop_counter++ >= 1) {
86788 +               noop_counter = 0;
86789 +               if (ts.state == TS_STATE_RELEASE_PENDING) {
86790 +                       /* We delay the UP event for a
86791 +                        * while to avoid jitter. If we get a DOWN
86792 +                        * event we do not send it. */
86793 +
86794 +                       ts_input_report(IE_UP, NULL);
86795 +                       ts.state = TS_STATE_STANDBY;
86796 +
86797 +                       if (ts.tsf[0])
86798 +                               (ts.tsf[0]->api->clear)(ts.tsf[0]);
86799 +               }
86800 +       } else {
86801 +               mod_timer(&event_send_timer, jiffies + TS_RELEASE_TIMEOUT);
86802 +       }
86803 +
86804 +       clear_bit(0, &running);
86805 +
86806 +       return;
86807 +
86808 +ts_exit_error: /* should not happen unless we have a bug */
86809 +       printk(KERN_ERR __FILE__ ": event_send_timer_f failed\n");
86810 +}
86811 +
86812 +/*
86813 + * Manage interrupts.
86814 + */
86815 +
86816 +static irqreturn_t stylus_updown(int irq, void *dev_id)
86817 +{
86818 +       unsigned long data0;
86819 +       unsigned long data1;
86820 +       int event_type;
86821 +
86822 +       data0 = readl(base_addr+S3C2410_ADCDAT0);
86823 +       data1 = readl(base_addr+S3C2410_ADCDAT1);
86824 +
86825 +       ts.is_down = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) &&
86826 +                                           (!(data1 & S3C2410_ADCDAT0_UPDOWN));
86827 +
86828 +       event_type = ts.is_down ? 'D' : 'U';
86829 +
86830 +       if (unlikely(__kfifo_put(ts.event_fifo, (unsigned char *)&event_type,
86831 +                    sizeof(int)) != sizeof(int))) /* should not happen */
86832 +               printk(KERN_ERR __FILE__": stylus_updown lost event!\n");
86833 +
86834 +       if (ts.is_down)
86835 +               s3c2410_ts_start_adc_conversion();
86836 +       else
86837 +               writel(WAIT4INT(0), base_addr+S3C2410_ADCTSC);
86838 +
86839 +       mod_timer(&event_send_timer, jiffies + 1);
86840 +
86841 +       return IRQ_HANDLED;
86842 +}
86843 +
86844 +static irqreturn_t stylus_action(int irq, void *dev_id)
86845 +{
86846 +       int buf[3];
86847 +
86848 +       /* grab the ADC results */
86849 +       ts.coords[0] = readl(base_addr + S3C2410_ADCDAT0) &
86850 +                                                   S3C2410_ADCDAT0_XPDATA_MASK;
86851 +       ts.coords[1] = readl(base_addr + S3C2410_ADCDAT1) &
86852 +                                                   S3C2410_ADCDAT1_YPDATA_MASK;
86853 +
86854 +       if (ts.tsf[0]) { /* filtering is enabled, don't use raw directly */
86855 +               switch ((ts.tsf[0]->api->process)(ts.tsf[0], &ts.coords[0])) {
86856 +               case 0: /*
86857 +                        * no real sample came out of processing yet,
86858 +                        * get another raw result to feed it
86859 +                        */
86860 +                       s3c2410_ts_start_adc_conversion();
86861 +                       return IRQ_HANDLED;
86862 +               case 1: /* filters are ready to deliver a sample */
86863 +                       (ts.tsf[0]->api->scale)(ts.tsf[0], &ts.coords[0]);
86864 +                       break;
86865 +               case -1:
86866 +                       /* error in filters, ignore the event */
86867 +                       (ts.tsf[0]->api->clear)(ts.tsf[0]);
86868 +                       writel(WAIT4INT(1), base_addr + S3C2410_ADCTSC);
86869 +                       return IRQ_HANDLED;
86870 +               default:
86871 +                       printk(KERN_ERR":stylus_action error\n");
86872 +               }
86873 +       }
86874 +
86875 +       /* We use a buffer because want an atomic operation */
86876 +       buf[0] = 'P';
86877 +       buf[1] = ts.coords[0];
86878 +       buf[2] = ts.coords[1];
86879 +
86880 +       if (unlikely(__kfifo_put(ts.event_fifo, (unsigned char *)buf,
86881 +                    sizeof(int) * 3) != sizeof(int) * 3))
86882 +               /* should not happen */
86883 +                       printk(KERN_ERR":stylus_action error\n");
86884 +
86885 +       writel(WAIT4INT(1), base_addr + S3C2410_ADCTSC);
86886 +       mod_timer(&event_send_timer, jiffies + 1);
86887 +
86888 +       return IRQ_HANDLED;
86889 +}
86890 +
86891 +static struct clk      *adc_clock;
86892 +
86893 +/*
86894 + * The functions for inserting/removing us as a module.
86895 + */
86896 +
86897 +static int __init s3c2410ts_probe(struct platform_device *pdev)
86898 +{
86899 +       int rc;
86900 +       struct s3c2410_ts_mach_info *info;
86901 +       struct input_dev *input_dev;
86902 +       int ret = 0;
86903 +
86904 +       dev_info(&pdev->dev, "Starting\n");
86905 +
86906 +       info = (struct s3c2410_ts_mach_info *)pdev->dev.platform_data;
86907 +
86908 +       if (!info)
86909 +       {
86910 +               dev_err(&pdev->dev, "Hm... too bad: no platform data for ts\n");
86911 +               return -EINVAL;
86912 +       }
86913 +
86914 +#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
86915 +       printk(DEBUG_LVL "Entering s3c2410ts_init\n");
86916 +#endif
86917 +
86918 +       adc_clock = clk_get(NULL, "adc");
86919 +       if (!adc_clock) {
86920 +               dev_err(&pdev->dev, "failed to get adc clock source\n");
86921 +               return -ENOENT;
86922 +       }
86923 +       clk_enable(adc_clock);
86924 +
86925 +#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
86926 +       printk(DEBUG_LVL "got and enabled clock\n");
86927 +#endif
86928 +
86929 +       base_addr = ioremap(S3C2410_PA_ADC,0x20);
86930 +       if (base_addr == NULL) {
86931 +               dev_err(&pdev->dev, "Failed to remap register block\n");
86932 +               ret = -ENOMEM;
86933 +               goto bail0;
86934 +       }
86935 +
86936 +
86937 +       /* If we acutally are a S3C2410: Configure GPIOs */
86938 +       if (!strcmp(pdev->name, "s3c2410-ts"))
86939 +               s3c2410_ts_connect();
86940 +
86941 +       if ((info->presc & 0xff) > 0)
86942 +               writel(S3C2410_ADCCON_PRSCEN |
86943 +                      S3C2410_ADCCON_PRSCVL(info->presc&0xFF),
86944 +                                                   base_addr + S3C2410_ADCCON);
86945 +       else
86946 +               writel(0, base_addr+S3C2410_ADCCON);
86947 +
86948 +       /* Initialise registers */
86949 +       if ((info->delay & 0xffff) > 0)
86950 +               writel(info->delay & 0xffff,  base_addr + S3C2410_ADCDLY);
86951 +
86952 +       writel(WAIT4INT(0), base_addr + S3C2410_ADCTSC);
86953 +
86954 +       /* Initialise input stuff */
86955 +       memset(&ts, 0, sizeof(struct s3c2410ts));
86956 +       input_dev = input_allocate_device();
86957 +
86958 +       if (!input_dev) {
86959 +               dev_err(&pdev->dev, "Unable to allocate the input device\n");
86960 +               ret = -ENOMEM;
86961 +               goto bail1;
86962 +       }
86963 +
86964 +       ts.dev = input_dev;
86965 +       ts.dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) |
86966 +                          BIT_MASK(EV_ABS);
86967 +       ts.dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
86968 +       input_set_abs_params(ts.dev, ABS_X, 0, 0x3FF, 0, 0);
86969 +       input_set_abs_params(ts.dev, ABS_Y, 0, 0x3FF, 0, 0);
86970 +       input_set_abs_params(ts.dev, ABS_PRESSURE, 0, 1, 0, 0);
86971 +
86972 +       ts.dev->name = s3c2410ts_name;
86973 +       ts.dev->id.bustype = BUS_RS232;
86974 +       ts.dev->id.vendor = 0xDEAD;
86975 +       ts.dev->id.product = 0xBEEF;
86976 +       ts.dev->id.version = S3C2410TSVERSION;
86977 +       ts.state = TS_STATE_STANDBY;
86978 +       ts.event_fifo = kfifo_alloc(TS_EVENT_FIFO_SIZE, GFP_KERNEL, NULL);
86979 +       if (IS_ERR(ts.event_fifo)) {
86980 +               ret = -EIO;
86981 +               goto bail2;
86982 +       }
86983 +
86984 +       /* create the filter chain set up for the 2 coordinates we produce */
86985 +       ret = ts_filter_create_chain(
86986 +               pdev, (struct ts_filter_api **)&info->filter_sequence,
86987 +               (void *)&info->filter_config, ts.tsf, ARRAY_SIZE(ts.coords));
86988 +       if (ret)
86989 +               dev_info(&pdev->dev, "%d filter(s) initialized\n", ret);
86990 +       else /* this is OK, just means there won't be any filtering */
86991 +               dev_info(&pdev->dev, "Unfiltered output selected\n");
86992 +
86993 +       if (ts.tsf[0])
86994 +               (ts.tsf[0]->api->clear)(ts.tsf[0]);
86995 +       else
86996 +               dev_info(&pdev->dev, "No filtering\n");
86997 +
86998 +       /* Get irqs */
86999 +       if (request_irq(IRQ_ADC, stylus_action, IRQF_SAMPLE_RANDOM,
87000 +                                                   "s3c2410_action", ts.dev)) {
87001 +               dev_err(&pdev->dev, "Could not allocate ts IRQ_ADC !\n");
87002 +               iounmap(base_addr);
87003 +               ret = -EIO;
87004 +               goto bail3;
87005 +       }
87006 +       if (request_irq(IRQ_TC, stylus_updown, IRQF_SAMPLE_RANDOM,
87007 +                       "s3c2410_action", ts.dev)) {
87008 +               dev_err(&pdev->dev, "Could not allocate ts IRQ_TC !\n");
87009 +               free_irq(IRQ_ADC, ts.dev);
87010 +               iounmap(base_addr);
87011 +               ret = -EIO;
87012 +               goto bail4;
87013 +       }
87014 +
87015 +       dev_info(&pdev->dev, "successfully loaded\n");
87016 +
87017 +       /* All went ok, so register to the input system */
87018 +       rc = input_register_device(ts.dev);
87019 +       if (rc) {
87020 +               ret = -EIO;
87021 +               goto bail5;
87022 +       }
87023 +
87024 +       return 0;
87025 +
87026 +bail5:
87027 +       free_irq(IRQ_TC, ts.dev);
87028 +       free_irq(IRQ_ADC, ts.dev);
87029 +       clk_disable(adc_clock);
87030 +       iounmap(base_addr);
87031 +       disable_irq(IRQ_TC);
87032 +bail4:
87033 +       disable_irq(IRQ_ADC);
87034 +bail3:
87035 +       ts_filter_destroy_chain(pdev, ts.tsf);
87036 +       kfifo_free(ts.event_fifo);
87037 +bail2:
87038 +       input_unregister_device(ts.dev);
87039 +bail1:
87040 +       iounmap(base_addr);
87041 +bail0:
87042 +
87043 +       return ret;
87044 +}
87045 +
87046 +static int s3c2410ts_remove(struct platform_device *pdev)
87047 +{
87048 +       disable_irq(IRQ_ADC);
87049 +       disable_irq(IRQ_TC);
87050 +       free_irq(IRQ_TC,ts.dev);
87051 +       free_irq(IRQ_ADC,ts.dev);
87052 +
87053 +       if (adc_clock) {
87054 +               clk_disable(adc_clock);
87055 +               clk_put(adc_clock);
87056 +               adc_clock = NULL;
87057 +       }
87058 +
87059 +       input_unregister_device(ts.dev);
87060 +       iounmap(base_addr);
87061 +
87062 +       ts_filter_destroy_chain(pdev, ts.tsf);
87063 +
87064 +       kfifo_free(ts.event_fifo);
87065 +
87066 +       return 0;
87067 +}
87068 +
87069 +#ifdef CONFIG_PM
87070 +static int s3c2410ts_suspend(struct platform_device *pdev, pm_message_t state)
87071 +{
87072 +       writel(TSC_SLEEP, base_addr+S3C2410_ADCTSC);
87073 +       writel(readl(base_addr+S3C2410_ADCCON) | S3C2410_ADCCON_STDBM,
87074 +              base_addr+S3C2410_ADCCON);
87075 +
87076 +       disable_irq(IRQ_ADC);
87077 +       disable_irq(IRQ_TC);
87078 +
87079 +       clk_disable(adc_clock);
87080 +
87081 +       return 0;
87082 +}
87083 +
87084 +static int s3c2410ts_resume(struct platform_device *pdev)
87085 +{
87086 +       struct s3c2410_ts_mach_info *info =
87087 +               ( struct s3c2410_ts_mach_info *)pdev->dev.platform_data;
87088 +
87089 +       clk_enable(adc_clock);
87090 +       mdelay(1);
87091 +
87092 +       if (ts.tsf[0])
87093 +               (ts.tsf[0]->api->clear)(ts.tsf[0]);
87094 +
87095 +       enable_irq(IRQ_ADC);
87096 +       enable_irq(IRQ_TC);
87097 +
87098 +       if ((info->presc&0xff) > 0)
87099 +               writel(S3C2410_ADCCON_PRSCEN |
87100 +                      S3C2410_ADCCON_PRSCVL(info->presc&0xFF),
87101 +                                                     base_addr+S3C2410_ADCCON);
87102 +       else
87103 +               writel(0,base_addr+S3C2410_ADCCON);
87104 +
87105 +       /* Initialise registers */
87106 +       if ((info->delay & 0xffff) > 0)
87107 +               writel(info->delay & 0xffff,  base_addr+S3C2410_ADCDLY);
87108 +
87109 +       writel(WAIT4INT(0), base_addr+S3C2410_ADCTSC);
87110 +
87111 +       return 0;
87112 +}
87113 +
87114 +#else
87115 +#define s3c2410ts_suspend NULL
87116 +#define s3c2410ts_resume  NULL
87117 +#endif
87118 +
87119 +static struct platform_driver s3c2410ts_driver = {
87120 +       .driver         = {
87121 +              .name   = "s3c2410-ts",
87122 +              .owner  = THIS_MODULE,
87123 +       },
87124 +       .probe          = s3c2410ts_probe,
87125 +       .remove         = s3c2410ts_remove,
87126 +       .suspend        = s3c2410ts_suspend,
87127 +       .resume         = s3c2410ts_resume,
87128 +
87129 +};
87130 +
87131 +static struct platform_driver s3c2440ts_driver = {
87132 +       .driver         = {
87133 +              .name   = "s3c2440-ts",
87134 +              .owner  = THIS_MODULE,
87135 +       },
87136 +       .probe          = s3c2410ts_probe,
87137 +       .remove         = s3c2410ts_remove,
87138 +       .suspend        = s3c2410ts_suspend,
87139 +       .resume         = s3c2410ts_resume,
87140 +
87141 +};
87142 +
87143 +static int __init s3c2410ts_init(void)
87144 +{
87145 +       int rc;
87146 +
87147 +       rc = platform_driver_register(&s3c2410ts_driver);
87148 +       if (rc < 0)
87149 +               return rc;
87150 +
87151 +       rc = platform_driver_register(&s3c2440ts_driver);
87152 +       if (rc < 0)
87153 +               platform_driver_unregister(&s3c2410ts_driver);
87154 +
87155 +       return rc;
87156 +}
87157 +
87158 +static void __exit s3c2410ts_exit(void)
87159 +{
87160 +       platform_driver_unregister(&s3c2440ts_driver);
87161 +       platform_driver_unregister(&s3c2410ts_driver);
87162 +}
87163 +
87164 +module_init(s3c2410ts_init);
87165 +module_exit(s3c2410ts_exit);
87166 +
87167 --- /dev/null
87168 +++ b/drivers/input/touchscreen/ts_filter.c
87169 @@ -0,0 +1,64 @@
87170 +/*
87171 + * This program is free software; you can redistribute it and/or modify
87172 + * it under the terms of the GNU General Public License as published by
87173 + * the Free Software Foundation; either version 2 of the License, or
87174 + * (at your option) any later version.
87175 + *
87176 + * This program is distributed in the hope that it will be useful,
87177 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
87178 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
87179 + * GNU General Public License for more details.
87180 + *
87181 + * You should have received a copy of the GNU General Public License
87182 + * along with this program; if not, write to the Free Software
87183 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
87184 + *
87185 + * Copyright (c) 2008 Andy Green <andy@openmoko.com>
87186 + */
87187 +
87188 +#include <linux/kernel.h>
87189 +#include <linux/device.h>
87190 +#include <linux/ts_filter.h>
87191 +
87192 +int ts_filter_create_chain(struct platform_device *pdev,
87193 +                          struct ts_filter_api **api, void **config,
87194 +                          struct ts_filter **list, int count_coords)
87195 +{
87196 +       int count = 0;
87197 +       struct ts_filter *last = NULL;
87198 +
87199 +       if (!api)
87200 +               return 0;
87201 +
87202 +       while (*api && count < MAX_TS_FILTER_CHAIN) {
87203 +               *list = ((*api)->create)(pdev, *config++, count_coords);
87204 +               if (!*list) {
87205 +                       printk(KERN_ERR "Filter %d failed init\n", count);
87206 +                       return count;
87207 +               }
87208 +               (*list)->api = *api++;
87209 +               if (last)
87210 +                       last->next = *list;
87211 +               last = *list;
87212 +               list++;
87213 +               count++;
87214 +       }
87215 +
87216 +       return count;
87217 +}
87218 +EXPORT_SYMBOL_GPL(ts_filter_create_chain);
87219 +
87220 +void ts_filter_destroy_chain(struct platform_device *pdev,
87221 +                            struct ts_filter **list)
87222 +{
87223 +       struct ts_filter **first;
87224 +       int count = 0;
87225 +
87226 +       first = list;
87227 +       while (*list && count++ < MAX_TS_FILTER_CHAIN) {
87228 +               ((*list)->api->destroy)(pdev, *list);
87229 +               list++;
87230 +       }
87231 +       *first = NULL;
87232 +}
87233 +EXPORT_SYMBOL_GPL(ts_filter_destroy_chain);
87234 --- /dev/null
87235 +++ b/drivers/input/touchscreen/ts_filter_group.c
87236 @@ -0,0 +1,219 @@
87237 +/*
87238 + * This program is free software; you can redistribute it and/or modify
87239 + * it under the terms of the GNU General Public License as published by
87240 + * the Free Software Foundation; either version 2 of the License, or
87241 + * (at your option) any later version.
87242 + *
87243 + * This program is distributed in the hope that it will be useful,
87244 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
87245 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
87246 + * GNU General Public License for more details.
87247 + *
87248 + * You should have received a copy of the GNU General Public License
87249 + * along with this program; if not, write to the Free Software
87250 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
87251 + *
87252 + * Copyright (C) 2008 by Openmoko, Inc.
87253 + * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
87254 + * All rights reserved.
87255 + *
87256 + * This filter is useful to reject samples that are not reliable. We consider
87257 + * that a sample is not reliable if it deviates form the Majority.
87258 + *
87259 + * 1) We collect S samples.
87260 + *
87261 + * 2) For each dimension:
87262 + *
87263 + *  - We sort the points.
87264 + *  - Points that are "close enough" are considered to be in the same set.
87265 + *  - We choose the set with more elements. If more than "threshold"
87266 + *    points are in this set we use the first and the last point of the set
87267 + *    to define the valid range for this dimension [min, max], otherwise we
87268 + *    discard all the points and go to step 1.
87269 + *
87270 + * 3) We consider the unsorted S samples and try to feed them to the next
87271 + *    filter in the chain. If one of the points of each sample
87272 + *    is not in the allowed range for its dimension, we discard the sample.
87273 + *
87274 + */
87275 +
87276 +#include <linux/kernel.h>
87277 +#include <linux/slab.h>
87278 +#include <linux/sort.h>
87279 +#include <linux/ts_filter_group.h>
87280 +
87281 +static void ts_filter_group_clear_internal(struct ts_filter_group *tsfg,
87282 +                                          int attempts)
87283 +{
87284 +       tsfg->N = 0;
87285 +       tsfg->tries_left = attempts;
87286 +}
87287 +
87288 +static void ts_filter_group_clear(struct ts_filter *tsf)
87289 +{
87290 +       struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf;
87291 +
87292 +       ts_filter_group_clear_internal(tsfg, tsfg->config->attempts);
87293 +
87294 +       if (tsf->next) /* chain */
87295 +               (tsf->next->api->clear)(tsf->next);
87296 +}
87297 +
87298 +static struct ts_filter *ts_filter_group_create(struct platform_device *pdev,
87299 +                                               void *conf, int count_coords)
87300 +{
87301 +       struct ts_filter_group *tsfg;
87302 +       int i;
87303 +
87304 +       BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS));
87305 +
87306 +       tsfg = kzalloc(sizeof(struct ts_filter_group), GFP_KERNEL);
87307 +       if (!tsfg)
87308 +               return NULL;
87309 +
87310 +       tsfg->config = (struct ts_filter_group_configuration *)conf;
87311 +       tsfg->tsf.count_coords = count_coords;
87312 +
87313 +       BUG_ON(tsfg->config->attempts <= 0);
87314 +
87315 +       tsfg->samples[0] = kmalloc((2 + count_coords) * sizeof(int) *
87316 +                                  tsfg->config->extent, GFP_KERNEL);
87317 +       if (!tsfg->samples[0]) {
87318 +               kfree(tsfg);
87319 +               return NULL;
87320 +       }
87321 +       for (i = 1; i < count_coords; ++i)
87322 +               tsfg->samples[i] = tsfg->samples[0] + i * tsfg->config->extent;
87323 +       tsfg->sorted_samples = tsfg->samples[0] + count_coords *
87324 +                              tsfg->config->extent;
87325 +       tsfg->group_size = tsfg->samples[0] + (1 + count_coords) *
87326 +                              tsfg->config->extent;
87327 +
87328 +       ts_filter_group_clear_internal(tsfg, tsfg->config->attempts);
87329 +
87330 +       printk(KERN_INFO"  Created group ts filter len %d depth %d close %d "
87331 +                       "thresh %d\n", tsfg->config->extent, count_coords,
87332 +                       tsfg->config->close_enough, tsfg->config->threshold);
87333 +
87334 +       return &tsfg->tsf;
87335 +}
87336 +
87337 +static void ts_filter_group_destroy(struct platform_device *pdev,
87338 +                                   struct ts_filter *tsf)
87339 +{
87340 +       struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf;
87341 +
87342 +       kfree(tsfg->samples[0]); /* first guy has pointer from kmalloc */
87343 +       kfree(tsf);
87344 +}
87345 +
87346 +static void ts_filter_group_scale(struct ts_filter *tsf, int *coords)
87347 +{
87348 +       if (tsf->next)
87349 +               (tsf->next->api->scale)(tsf->next, coords);
87350 +}
87351 +
87352 +static int int_cmp(const void *_a, const void *_b)
87353 +{
87354 +       const int *a = _a;
87355 +       const int *b = _b;
87356 +
87357 +       if (*a > *b)
87358 +               return 1;
87359 +       if (*a < *b)
87360 +               return -1;
87361 +       return 0;
87362 +}
87363 +
87364 +static int ts_filter_group_process(struct ts_filter *tsf, int *coords)
87365 +{
87366 +       struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf;
87367 +       int n;
87368 +       int i;
87369 +       int ret = 0; /* ask for more samples by default */
87370 +
87371 +       BUG_ON(tsfg->N >= tsfg->config->extent);
87372 +
87373 +       for (n = 0; n < tsf->count_coords; n++)
87374 +               tsfg->samples[n][tsfg->N] = coords[n];
87375 +
87376 +       if (++tsfg->N < tsfg->config->extent)
87377 +               return 0;       /* we meed more samples */
87378 +
87379 +       for (n = 0; n < tsfg->tsf.count_coords; n++) {
87380 +               int *v = tsfg->sorted_samples;
87381 +               int ngroups = 0;
87382 +               int best_size;
87383 +               int best_idx = 0;
87384 +               int idx = 0;
87385 +
87386 +               memcpy(v, tsfg->samples[n], tsfg->N * sizeof(int));
87387 +               sort(v, tsfg->N, sizeof(int), int_cmp, NULL);
87388 +
87389 +               tsfg->group_size[0] = 1;
87390 +               for (i = 1; i < tsfg->N; ++i) {
87391 +                       if (v[i] - v[i - 1] <= tsfg->config->close_enough)
87392 +                               tsfg->group_size[ngroups]++;
87393 +                       else
87394 +                               tsfg->group_size[++ngroups] = 1;
87395 +               }
87396 +               ngroups++;
87397 +
87398 +               best_size = tsfg->group_size[0];
87399 +               for (i = 1; i < ngroups; i++) {
87400 +                       idx += tsfg->group_size[i - 1];
87401 +                       if (best_size < tsfg->group_size[i]) {
87402 +                               best_size = tsfg->group_size[i];
87403 +                               best_idx = idx;
87404 +                       }
87405 +               }
87406 +
87407 +               if (best_size < tsfg->config->threshold) {
87408 +                       /* this set is not good enough for us */
87409 +                       if (--tsfg->tries_left) {
87410 +                               ts_filter_group_clear_internal
87411 +                                       (tsfg, tsfg->tries_left);
87412 +                               return 0; /* ask for more samples */
87413 +                       }
87414 +                       return -1; /* we give up */
87415 +               }
87416 +
87417 +               tsfg->range_min[n] = v[best_idx];
87418 +               tsfg->range_max[n] = v[best_idx + best_size - 1];
87419 +       }
87420 +
87421 +       BUG_ON(!tsf->next);
87422 +
87423 +       for (i = 0; i < tsfg->N; ++i) {
87424 +               int r;
87425 +
87426 +               for (n = 0; n < tsfg->tsf.count_coords; ++n) {
87427 +                       coords[n] = tsfg->samples[n][i];
87428 +                       if (coords[n] < tsfg->range_min[n] ||
87429 +                           coords[n] > tsfg->range_max[n])
87430 +                               break;
87431 +               }
87432 +
87433 +               if (n != tsfg->tsf.count_coords) /* sample not OK */
87434 +                       continue;
87435 +
87436 +               r = (tsf->next->api->process)(tsf->next, coords);
87437 +               if (r)  {
87438 +                       ret = r;
87439 +                       break;
87440 +               }
87441 +       }
87442 +
87443 +       ts_filter_group_clear_internal(tsfg, tsfg->config->attempts);
87444 +
87445 +       return ret;
87446 +}
87447 +
87448 +struct ts_filter_api ts_filter_group_api = {
87449 +       .create = ts_filter_group_create,
87450 +       .destroy = ts_filter_group_destroy,
87451 +       .clear = ts_filter_group_clear,
87452 +       .process = ts_filter_group_process,
87453 +       .scale = ts_filter_group_scale,
87454 +};
87455 +
87456 --- /dev/null
87457 +++ b/drivers/input/touchscreen/ts_filter_linear.c
87458 @@ -0,0 +1,178 @@
87459 +/*
87460 + * This program is free software; you can redistribute it and/or modify
87461 + * it under the terms of the GNU General Public License as published by
87462 + * the Free Software Foundation; version 2 of the License, or
87463 + * (at your option) any later version.
87464 + *
87465 + * This program is distributed in the hope that it will be useful,
87466 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
87467 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
87468 + * GNU General Public License for more details.
87469 + *
87470 + * You should have received a copy of the GNU General Public License
87471 + * along with this program; if not, write to the Free Software
87472 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
87473 + *
87474 + * Copyright (C) 2008 by Openmoko, Inc.
87475 + * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
87476 + * All rights reserved.
87477 + *
87478 + * Linearly scale touchscreen values.
87479 + *
87480 + * Expose the TS_FILTER_LINEAR_NCONSTANTS for the linear transformation
87481 + * using sysfs.
87482 + *
87483 + */
87484 +
87485 +#include <linux/ts_filter_linear.h>
87486 +#include <linux/kernel.h>
87487 +#include <linux/slab.h>
87488 +#include <linux/string.h>
87489 +
87490 +
87491 +/*
87492 + * sysfs functions
87493 + */
87494 +
87495 +
87496 +static ssize_t const_attr_show(struct kobject *kobj,
87497 +                              struct attribute *attr,
87498 +                              char *buf)
87499 +{
87500 +       struct const_attribute *a = to_const_attr(attr);
87501 +
87502 +       return a->show(to_const_obj(kobj), a, buf);
87503 +}
87504 +
87505 +static ssize_t const_attr_store(struct kobject *kobj,
87506 +                               struct attribute *attr,
87507 +                               const char *buf, size_t len)
87508 +{
87509 +       struct const_attribute *a = to_const_attr(attr);
87510 +
87511 +       return a->store(to_const_obj(kobj), a, buf, len);
87512 +}
87513 +
87514 +static struct sysfs_ops const_sysfs_ops = {
87515 +       .show =         const_attr_show,
87516 +       .store =        const_attr_store,
87517 +};
87518 +
87519 +static void const_release(struct kobject *kobj)
87520 +{
87521 +       kfree(to_const_obj(kobj)->tsfl);
87522 +}
87523 +
87524 +static ssize_t const_show(struct const_obj *obj, struct const_attribute *attr,
87525 +                         char *buf)
87526 +{
87527 +       int who;
87528 +
87529 +       sscanf(attr->attr.name, "%d", &who);
87530 +       return sprintf(buf, "%d\n", obj->tsfl->constants[who]);
87531 +}
87532 +
87533 +static ssize_t const_store(struct const_obj *obj, struct const_attribute *attr,
87534 +                          const char *buf, size_t count)
87535 +{
87536 +       int who;
87537 +
87538 +       sscanf(attr->attr.name, "%d", &who);
87539 +       sscanf(buf, "%d", &obj->tsfl->constants[who]);
87540 +       return count;
87541 +}
87542 +
87543 +/*
87544 + * filter functions
87545 + */
87546 +
87547 +static struct ts_filter *ts_filter_linear_create(struct platform_device *pdev,
87548 +                                                void *conf, int count_coords)
87549 +{
87550 +       struct ts_filter_linear *tsfl;
87551 +       int i;
87552 +       int ret;
87553 +
87554 +       tsfl = kzalloc(sizeof(struct ts_filter_linear), GFP_KERNEL);
87555 +       if (!tsfl)
87556 +               return NULL;
87557 +
87558 +       tsfl->config = (struct ts_filter_linear_configuration *)conf;
87559 +       tsfl->tsf.count_coords = count_coords;
87560 +
87561 +       for (i = 0; i < TS_FILTER_LINEAR_NCONSTANTS; ++i) {
87562 +               tsfl->constants[i] = tsfl->config->constants[i];
87563 +
87564 +               /* sysfs */
87565 +               sprintf(tsfl->attr_names[i], "%d", i);
87566 +               tsfl->kattrs[i].attr.name = tsfl->attr_names[i];
87567 +               tsfl->kattrs[i].attr.mode = 0666;
87568 +               tsfl->kattrs[i].show = const_show;
87569 +               tsfl->kattrs[i].store = const_store;
87570 +               tsfl->attrs[i] = &tsfl->kattrs[i].attr;
87571 +       }
87572 +       tsfl->attrs[i] = NULL;
87573 +
87574 +       tsfl->const_ktype.sysfs_ops = &const_sysfs_ops;
87575 +       tsfl->const_ktype.release = const_release;
87576 +       tsfl->const_ktype.default_attrs = tsfl->attrs;
87577 +       tsfl->c_obj.tsfl = tsfl; /* kernel frees tsfl in const_release */
87578 +
87579 +       /* TODO: /sys/ts-calibration is not OK */
87580 +       ret = kobject_init_and_add(&tsfl->c_obj.kobj, &tsfl->const_ktype,
87581 +                                  &pdev->dev.kobj, "calibration");
87582 +       if (ret) {
87583 +               kobject_put(&tsfl->c_obj.kobj);
87584 +               return NULL;
87585 +       }
87586 +
87587 +       printk(KERN_INFO"  Created Linear ts filter depth %d\n", count_coords);
87588 +
87589 +       return &tsfl->tsf;
87590 +}
87591 +
87592 +static void ts_filter_linear_destroy(struct platform_device *pdev,
87593 +                                    struct ts_filter *tsf)
87594 +{
87595 +       struct ts_filter_linear *tsfl = (struct ts_filter_linear *)tsf;
87596 +
87597 +       /* kernel frees tsfl in const_release */
87598 +       kobject_put(&tsfl->c_obj.kobj);
87599 +}
87600 +
87601 +static void ts_filter_linear_clear(struct ts_filter *tsf)
87602 +{
87603 +       if (tsf->next) /* chain */
87604 +               (tsf->next->api->clear)(tsf->next);
87605 +}
87606 +
87607 +
87608 +static void ts_filter_linear_scale(struct ts_filter *tsf, int *coords)
87609 +{
87610 +       struct ts_filter_linear *tsfl = (struct ts_filter_linear *)tsf;
87611 +       int *k = tsfl->constants;
87612 +       int c0 = coords[tsfl->config->coord0];
87613 +       int c1 = coords[tsfl->config->coord1];
87614 +
87615 +       coords[tsfl->config->coord0] = (k[2] + k[0] * c0 + k[1] * c1) / k[6];
87616 +       coords[tsfl->config->coord1] = (k[5] + k[3] * c0 + k[4] * c1) / k[6];
87617 +
87618 +       if (tsf->next)
87619 +               (tsf->next->api->scale)(tsf->next, coords);
87620 +}
87621 +
87622 +static int ts_filter_linear_process(struct ts_filter *tsf, int *coords)
87623 +{
87624 +       if (tsf->next)
87625 +               return (tsf->next->api->process)(tsf->next, coords);
87626 +
87627 +       return 1;
87628 +}
87629 +
87630 +struct ts_filter_api ts_filter_linear_api = {
87631 +       .create = ts_filter_linear_create,
87632 +       .destroy = ts_filter_linear_destroy,
87633 +       .clear = ts_filter_linear_clear,
87634 +       .process = ts_filter_linear_process,
87635 +       .scale = ts_filter_linear_scale,
87636 +};
87637 --- /dev/null
87638 +++ b/drivers/input/touchscreen/ts_filter_mean.c
87639 @@ -0,0 +1,172 @@
87640 +/*
87641 + * This program is free software; you can redistribute it and/or modify
87642 + * it under the terms of the GNU General Public License as published by
87643 + * the Free Software Foundation; either version 2 of the License, or
87644 + * (at your option) any later version.
87645 + *
87646 + * This program is distributed in the hope that it will be useful,
87647 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
87648 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
87649 + * GNU General Public License for more details.
87650 + *
87651 + * You should have received a copy of the GNU General Public License
87652 + * along with this program; if not, write to the Free Software
87653 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
87654 + *
87655 + * Copyright (c) 2008 Andy Green <andy@openmoko.com>
87656 + *
87657 + *
87658 + * Mean has no effect if the samples are changing by more that the
87659 + * threshold set by averaging_threshold in the configuration.
87660 + *
87661 + * However while samples come in that don't go outside this threshold from
87662 + * the last reported sample, Mean replaces the samples with a simple mean
87663 + * of a configurable number of samples (set by bits_filter_length in config,
87664 + * which is 2^n, so 5 there makes 32 sample averaging).
87665 + *
87666 + * Mean works well if the input data is already good quality, reducing + / - 1
87667 + * sample jitter when the stylus is still, or moving very slowly, without
87668 + * introducing abrupt transitions or reducing ability to follow larger
87669 + * movements.  If you set the threshold higher than the dynamic range of the
87670 + * coordinates, you can just use it as a simple mean average.
87671 + */
87672 +
87673 +#include <linux/errno.h>
87674 +#include <linux/kernel.h>
87675 +#include <linux/slab.h>
87676 +#include <linux/ts_filter_mean.h>
87677 +
87678 +static void ts_filter_mean_clear_internal(struct ts_filter *tsf)
87679 +{
87680 +       struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf;
87681 +       int n;
87682 +
87683 +       for (n = 0; n < tsfs->tsf.count_coords; n++) {
87684 +               tsfs->fhead[n] = 0;
87685 +               tsfs->ftail[n] = 0;
87686 +               tsfs->lowpass[n] = 0;
87687 +       }
87688 +}
87689 +
87690 +static void ts_filter_mean_clear(struct ts_filter *tsf)
87691 +{
87692 +       ts_filter_mean_clear_internal(tsf);
87693 +
87694 +       if (tsf->next) /* chain */
87695 +               (tsf->next->api->clear)(tsf->next);
87696 +}
87697 +
87698 +static struct ts_filter *ts_filter_mean_create(struct platform_device *pdev,
87699 +                                              void *config, int count_coords)
87700 +{
87701 +       int *p;
87702 +       int n;
87703 +       struct ts_filter_mean *tsfs = kzalloc(
87704 +                                 sizeof(struct ts_filter_mean), GFP_KERNEL);
87705 +
87706 +       if (!tsfs)
87707 +               return NULL;
87708 +
87709 +       BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS));
87710 +       tsfs->tsf.count_coords = count_coords;
87711 +
87712 +       tsfs->config = (struct ts_filter_mean_configuration *)config;
87713 +
87714 +       tsfs->config->extent = 1 << tsfs->config->bits_filter_length;
87715 +       BUG_ON((tsfs->config->extent > 256) || (!tsfs->config->extent));
87716 +
87717 +       p = kmalloc(tsfs->config->extent * sizeof(int) * count_coords,
87718 +                                                                   GFP_KERNEL);
87719 +       if (!p)
87720 +               return NULL;
87721 +
87722 +       for (n = 0; n < count_coords; n++) {
87723 +               tsfs->fifo[n] = p;
87724 +               p += tsfs->config->extent;
87725 +       }
87726 +
87727 +       if (!tsfs->config->averaging_threshold)
87728 +               tsfs->config->averaging_threshold = 0xffff; /* always active */
87729 +
87730 +       ts_filter_mean_clear_internal(&tsfs->tsf);
87731 +
87732 +       printk(KERN_INFO"  Created Mean ts filter len %d depth %d thresh %d\n",
87733 +              tsfs->config->extent, count_coords,
87734 +              tsfs->config->averaging_threshold);
87735 +
87736 +       return &tsfs->tsf;
87737 +}
87738 +
87739 +static void ts_filter_mean_destroy(struct platform_device *pdev,
87740 +                                  struct ts_filter *tsf)
87741 +{
87742 +       struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf;
87743 +
87744 +       kfree(tsfs->fifo[0]); /* first guy has pointer from kmalloc */
87745 +       kfree(tsf);
87746 +}
87747 +
87748 +static void ts_filter_mean_scale(struct ts_filter *tsf, int *coords)
87749 +{
87750 +       if (tsf->next) /* chain */
87751 +               (tsf->next->api->scale)(tsf->next, coords);
87752 +}
87753 +
87754 +/* give us the raw sample data in x and y, and if we return 1 then you can
87755 + * get a filtered coordinate from tsm->x and tsm->y: if we return 0 you didn't
87756 + * fill the filter with samples yet.
87757 + */
87758 +
87759 +static int ts_filter_mean_process(struct ts_filter *tsf, int *coords)
87760 +{
87761 +       struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf;
87762 +       int n;
87763 +       int len;
87764 +
87765 +       for (n = 0; n < tsf->count_coords; n++) {
87766 +
87767 +               /* has he moved far enough away that we should abandon current
87768 +                * low pass filtering state?
87769 +                */
87770 +               if ((coords[n] < (tsfs->reported[n] -
87771 +                                         tsfs->config->averaging_threshold)) ||
87772 +                   (coords[n] > (tsfs->reported[n] +
87773 +                                         tsfs->config->averaging_threshold))) {
87774 +                       tsfs->fhead[n] = 0;
87775 +                       tsfs->ftail[n] = 0;
87776 +                       tsfs->lowpass[n] = 0;
87777 +               }
87778 +
87779 +               /* capture this sample into fifo and sum */
87780 +               tsfs->fifo[n][tsfs->fhead[n]++] = coords[n];
87781 +               if (tsfs->fhead[n] == tsfs->config->extent)
87782 +                       tsfs->fhead[n] = 0;
87783 +               tsfs->lowpass[n] += coords[n];
87784 +
87785 +               /* adjust the sum into an average and use that*/
87786 +               len = (tsfs->fhead[n] - tsfs->ftail[n]) &
87787 +                                                    (tsfs->config->extent - 1);
87788 +               coords[n] = (tsfs->lowpass[n] + (len >> 1)) / len;
87789 +               tsfs->reported[n] = coords[n];
87790 +
87791 +               /* remove oldest sample if we are full */
87792 +               if (len == (tsfs->config->extent - 1)) {
87793 +                       tsfs->lowpass[n] -= tsfs->fifo[n][tsfs->ftail[n]++];
87794 +                       if (tsfs->ftail[n] == tsfs->config->extent)
87795 +                               tsfs->ftail[n] = 0;
87796 +               }
87797 +       }
87798 +
87799 +       if (tsf->next) /* chain */
87800 +               return (tsf->next->api->process)(tsf->next, coords);
87801 +
87802 +       return 1;
87803 +}
87804 +
87805 +struct ts_filter_api ts_filter_mean_api = {
87806 +       .create = ts_filter_mean_create,
87807 +       .destroy = ts_filter_mean_destroy,
87808 +       .clear = ts_filter_mean_clear,
87809 +       .process = ts_filter_mean_process,
87810 +       .scale = ts_filter_mean_scale,
87811 +};
87812 --- /dev/null
87813 +++ b/drivers/input/touchscreen/ts_filter_median.c
87814 @@ -0,0 +1,215 @@
87815 +/*
87816 + * This program is free software; you can redistribute it and/or modify
87817 + * it under the terms of the GNU General Public License as published by
87818 + * the Free Software Foundation; either version 2 of the License, or
87819 + * (at your option) any later version.
87820 + *
87821 + * This program is distributed in the hope that it will be useful,
87822 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
87823 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
87824 + * GNU General Public License for more details.
87825 + *
87826 + * You should have received a copy of the GNU General Public License
87827 + * along with this program; if not, write to the Free Software
87828 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
87829 + *
87830 + * Copyright (c) 2008 Andy Green <andy@openmoko.com>
87831 + *
87832 + *
87833 + * Median averaging stuff.  We sort incoming raw samples into an array of
87834 + * MEDIAN_SIZE length, discarding the oldest sample each time once we are full.
87835 + * We then return the sum of the middle three samples for X and Y.  It means
87836 + * the final result must be divided by (3 * scaling factor) to correct for
87837 + * avoiding the repeated /3.
87838 + *
87839 + * This strongly rejects brief excursions away from a central point that is
87840 + * sticky in time compared to the excursion duration.
87841 + *
87842 + * Thanks to Dale Schumacher (who wrote some example code) and Carl-Daniel
87843 + * Halifinger who pointed out this would be a good method.
87844 + */
87845 +
87846 +#include <linux/errno.h>
87847 +#include <linux/kernel.h>
87848 +#include <linux/slab.h>
87849 +#include <linux/ts_filter_median.h>
87850 +
87851 +static void ts_filter_median_insert(int *p, int sample, int count)
87852 +{
87853 +       int n;
87854 +
87855 +       /* search through what we got so far to find where to put sample */
87856 +       for (n = 0; n < count; n++)
87857 +                /* we met somebody bigger than us? */
87858 +               if (sample < p[n]) {
87859 +                       /* starting from the end, push bigger guys down one */
87860 +                       for (count--; count >= n; count--)
87861 +                               p[count + 1] = p[count];
87862 +                       p[n] = sample; /* and put us in place of first bigger */
87863 +                       return;
87864 +               }
87865 +
87866 +       p[count] = sample; /* nobody was bigger than us, add us on the end */
87867 +}
87868 +
87869 +static void ts_filter_median_del(int *p, int value, int count)
87870 +{
87871 +       int index;
87872 +
87873 +       for (index = 0; index < count; index++)
87874 +               if (p[index] == value) {
87875 +                       for (; index < count; index++)
87876 +                               p[index] = p[index + 1];
87877 +                       return;
87878 +               }
87879 +}
87880 +
87881 +
87882 +static void ts_filter_median_clear_internal(struct ts_filter *tsf)
87883 +{
87884 +       struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf;
87885 +
87886 +       tsfm->pos = 0;
87887 +       tsfm->valid = 0;
87888 +
87889 +}
87890 +static void ts_filter_median_clear(struct ts_filter *tsf)
87891 +{
87892 +       ts_filter_median_clear_internal(tsf);
87893 +
87894 +       if (tsf->next) /* chain */
87895 +               (tsf->next->api->clear)(tsf->next);
87896 +}
87897 +
87898 +static struct ts_filter *ts_filter_median_create(struct platform_device *pdev,
87899 +                                                void *conf, int count_coords)
87900 +{
87901 +       int *p;
87902 +       int n;
87903 +       struct ts_filter_median *tsfm = kzalloc(sizeof(struct ts_filter_median),
87904 +                                                                   GFP_KERNEL);
87905 +
87906 +       if (!tsfm)
87907 +               return NULL;
87908 +
87909 +       tsfm->config = (struct ts_filter_median_configuration *)conf;
87910 +       BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS));
87911 +       tsfm->tsf.count_coords = count_coords;
87912 +
87913 +       tsfm->config->midpoint = (tsfm->config->extent >> 1) + 1;
87914 +
87915 +       p = kmalloc(2 * count_coords * sizeof(int) * (tsfm->config->extent + 1),
87916 +                                                                   GFP_KERNEL);
87917 +       if (!p) {
87918 +               kfree(tsfm);
87919 +               return NULL;
87920 +       }
87921 +
87922 +       for (n = 0; n < count_coords; n++) {
87923 +               tsfm->sort[n] = p;
87924 +               p += tsfm->config->extent + 1;
87925 +               tsfm->fifo[n] = p;
87926 +               p += tsfm->config->extent + 1;
87927 +       }
87928 +
87929 +       ts_filter_median_clear_internal(&tsfm->tsf);
87930 +
87931 +       printk(KERN_INFO"  Created Median ts filter len %d depth %d dec %d\n",
87932 +              tsfm->config->extent, count_coords,
87933 +              tsfm->config->decimation_threshold);
87934 +
87935 +       return &tsfm->tsf;
87936 +}
87937 +
87938 +static void ts_filter_median_destroy(struct platform_device *pdev,
87939 +                                    struct ts_filter *tsf)
87940 +{
87941 +       struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf;
87942 +
87943 +       kfree(tsfm->sort[0]); /* first guy has pointer from kmalloc */
87944 +       kfree(tsf);
87945 +}
87946 +
87947 +static void ts_filter_median_scale(struct ts_filter *tsf, int *coords)
87948 +{
87949 +       int n;
87950 +
87951 +       for (n = 0; n < tsf->count_coords; n++)
87952 +               coords[n] = (coords[n] + 2) / 3;
87953 +
87954 +       if (tsf->next) /* chain */
87955 +               (tsf->next->api->scale)(tsf->next, coords);
87956 +}
87957 +
87958 +/* give us the raw sample data coords, and if we return 1 then you can
87959 + * get a filtered coordinate from coords: if we return 0 you didn't
87960 + * fill all the filters with samples yet.
87961 + */
87962 +
87963 +static int ts_filter_median_process(struct ts_filter *tsf, int *coords)
87964 +{
87965 +       struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf;
87966 +       int n;
87967 +       int movement = 1;
87968 +
87969 +       for (n = 0; n < tsf->count_coords; n++) {
87970 +               /* grab copy in insertion order to remove when oldest */
87971 +               tsfm->fifo[n][tsfm->pos] = coords[n];
87972 +               /* insert these samples in sorted order in the median arrays */
87973 +               ts_filter_median_insert(tsfm->sort[n], coords[n], tsfm->valid);
87974 +       }
87975 +       /* move us on in the fifo */
87976 +       if (++tsfm->pos == (tsfm->config->extent + 1))
87977 +               tsfm->pos = 0;
87978 +
87979 +       /* we have finished a median sampling? */
87980 +       if (++tsfm->valid != tsfm->config->extent)
87981 +               return 0; /* no valid sample to use */
87982 +
87983 +       /* discard the oldest sample in median sorted array */
87984 +       tsfm->valid--;
87985 +
87986 +       /* sum the middle 3 in the median sorted arrays.  We don't divide back
87987 +        * down which increases the sum resolution by a factor of 3 until the
87988 +        * scale API is called
87989 +        */
87990 +       for (n = 0; n < tsfm->tsf.count_coords; n++)
87991 +               /* perform the deletion of the oldest sample */
87992 +               ts_filter_median_del(tsfm->sort[n], tsfm->fifo[n][tsfm->pos],
87993 +                                                                  tsfm->valid);
87994 +
87995 +       tsfm->decimation_count--;
87996 +       if (tsfm->decimation_count >= 0)
87997 +               return 0;
87998 +
87999 +       for (n = 0; n < tsfm->tsf.count_coords; n++) {
88000 +               /* give the coordinate result from summing median 3 */
88001 +               coords[n] = tsfm->sort[n][tsfm->config->midpoint - 1] +
88002 +                           tsfm->sort[n][tsfm->config->midpoint] +
88003 +                           tsfm->sort[n][tsfm->config->midpoint + 1]
88004 +                       ;
88005 +
88006 +               movement += abs(tsfm->last_issued[n] - coords[n]);
88007 +       }
88008 +
88009 +       if (movement > tsfm->config->decimation_threshold) /* fast */
88010 +               tsfm->decimation_count = tsfm->config->decimation_above;
88011 +       else
88012 +               tsfm->decimation_count = tsfm->config->decimation_below;
88013 +
88014 +       memcpy(&tsfm->last_issued[0], coords,
88015 +              tsfm->tsf.count_coords * sizeof(int));
88016 +
88017 +       if (tsf->next) /* chain */
88018 +               return (tsf->next->api->process)(tsf->next, coords);
88019 +
88020 +       return 1;
88021 +}
88022 +
88023 +struct ts_filter_api ts_filter_median_api = {
88024 +       .create = ts_filter_median_create,
88025 +       .destroy = ts_filter_median_destroy,
88026 +       .clear = ts_filter_median_clear,
88027 +       .process = ts_filter_median_process,
88028 +       .scale = ts_filter_median_scale,
88029 +};
88030 --- a/drivers/Kconfig
88031 +++ b/drivers/Kconfig
88032 @@ -107,4 +107,6 @@ source "drivers/uio/Kconfig"
88033  source "drivers/xen/Kconfig"
88034
88035  source "drivers/staging/Kconfig"
88036 +
88037 +source "drivers/android/Kconfig"
88038  endmenu
88039 --- a/drivers/leds/Kconfig
88040 +++ b/drivers/leds/Kconfig
88041 @@ -33,7 +33,7 @@ config LEDS_LOCOMO
88042
88043  config LEDS_S3C24XX
88044         tristate "LED Support for Samsung S3C24XX GPIO LEDs"
88045 -       depends on LEDS_CLASS && ARCH_S3C2410
88046 +       depends on LEDS_CLASS && ARCH_S3C2410 && S3C2410_PWM
88047         help
88048           This option enables support for LEDs connected to GPIO lines
88049           on Samsung S3C24XX series CPUs, such as the S3C2410 and S3C2440.
88050 @@ -171,6 +171,18 @@ config LEDS_DA903X
88051           This option enables support for on-chip LED drivers found
88052           on Dialog Semiconductor DA9030/DA9034 PMICs.
88053
88054 +config LEDS_NEO1973_VIBRATOR
88055 +       tristate "Vibrator Support for the FIC Neo1973 GSM phone"
88056 +       depends on LEDS_CLASS && MACH_NEO1973
88057 +       help
88058 +         This option enables support for the vibrator on the FIC Neo1973.
88059 +
88060 +config LEDS_NEO1973_GTA02
88061 +       tristate "LED Support for the FIC Neo1973 (GTA02)"
88062 +       depends on LEDS_CLASS && MACH_NEO1973_GTA02
88063 +       help
88064 +         This option enables support for the LEDs on the FIC Neo1973.
88065 +
88066  comment "LED Triggers"
88067
88068  config LEDS_TRIGGERS
88069 --- a/drivers/leds/led-class.c
88070 +++ b/drivers/leds/led-class.c
88071 @@ -56,8 +56,10 @@ static ssize_t led_brightness_store(stru
88072         if (count == size) {
88073                 ret = count;
88074
88075 +#if 0 /* This is really bad. Don't do it!!!! */
88076                 if (state == LED_OFF)
88077                         led_trigger_remove(led_cdev);
88078 +#endif
88079                 led_set_brightness(led_cdev, state);
88080         }
88081
88082 --- /dev/null
88083 +++ b/drivers/leds/leds-neo1973-gta02.c
88084 @@ -0,0 +1,179 @@
88085 +/*
88086 + * LED driver for the Openmoko GTA02 GSM phone
88087 + *
88088 + * (C) 2006-2008 by Openmoko, Inc.
88089 + * Author: Harald Welte <laforge@openmoko.org>
88090 + * All rights reserved.
88091 + *
88092 + * This program is free software; you can redistribute it and/or modify
88093 + * it under the terms of the GNU General Public License version 2 as
88094 + * published by the Free Software Foundation.
88095 + *
88096 + */
88097 +
88098 +#include <linux/kernel.h>
88099 +#include <linux/init.h>
88100 +#include <linux/platform_device.h>
88101 +#include <linux/leds.h>
88102 +#include <mach/hardware.h>
88103 +#include <asm/mach-types.h>
88104 +#include <mach/gta02.h>
88105 +#include <plat/regs-timer.h>
88106 +#include <asm/plat-s3c24xx/neo1973.h>
88107 +
88108 +#define MAX_LEDS 3
88109 +#define COUNTER 256
88110 +
88111 +struct gta02_led_priv
88112 +{
88113 +       spinlock_t lock;
88114 +       struct led_classdev cdev;
88115 +       unsigned int gpio;
88116 +};
88117 +
88118 +struct gta02_led_bundle
88119 +{
88120 +       int num_leds;
88121 +       struct gta02_led_priv led[MAX_LEDS];
88122 +};
88123 +
88124 +static inline struct gta02_led_priv *to_priv(struct led_classdev *led_cdev)
88125 +{
88126 +       return container_of(led_cdev, struct gta02_led_priv, cdev);
88127 +}
88128 +
88129 +static inline struct gta02_led_bundle *to_bundle(struct led_classdev *led_cdev)
88130 +{
88131 +       return dev_get_drvdata(led_cdev->dev->parent);
88132 +}
88133 +
88134 +static void gta02led_set(struct led_classdev *led_cdev,
88135 +                        enum led_brightness value)
88136 +{
88137 +       unsigned long flags;
88138 +       struct gta02_led_priv *lp = to_priv(led_cdev);
88139 +
88140 +       spin_lock_irqsave(&lp->lock, flags);
88141 +       neo1973_gpb_setpin(lp->gpio, value ? 1 : 0);
88142 +       spin_unlock_irqrestore(&lp->lock, flags);
88143 +}
88144 +
88145 +#ifdef CONFIG_PM
88146 +static int gta02led_suspend(struct platform_device *pdev, pm_message_t state)
88147 +{
88148 +       struct gta02_led_bundle *bundle = platform_get_drvdata(pdev);
88149 +       int i;
88150 +
88151 +       for (i = 0; i < bundle->num_leds; i++)
88152 +               led_classdev_suspend(&bundle->led[i].cdev);
88153 +
88154 +       return 0;
88155 +}
88156 +
88157 +static int gta02led_resume(struct platform_device *pdev)
88158 +{
88159 +       struct gta02_led_bundle *bundle = platform_get_drvdata(pdev);
88160 +       int i;
88161 +
88162 +       for (i = 0; i < bundle->num_leds; i++)
88163 +               led_classdev_resume(&bundle->led[i].cdev);
88164 +
88165 +       return 0;
88166 +}
88167 +#endif
88168 +
88169 +static int __init gta02led_probe(struct platform_device *pdev)
88170 +{
88171 +       int i, rc;
88172 +       struct gta02_led_bundle *bundle;
88173 +
88174 +       if (!machine_is_neo1973_gta02())
88175 +               return -EIO;
88176 +
88177 +       bundle = kzalloc(sizeof(struct gta02_led_bundle), GFP_KERNEL);
88178 +       if (!bundle)
88179 +               return -ENOMEM;
88180 +       platform_set_drvdata(pdev, bundle);
88181 +
88182 +       for (i = 0; i < pdev->num_resources; i++) {
88183 +               struct gta02_led_priv *lp;
88184 +               struct resource *r;
88185 +
88186 +               if (i >= MAX_LEDS)
88187 +                       break;
88188 +
88189 +               r = platform_get_resource(pdev, 0, i);
88190 +               if (!r || !r->start || !r->name)
88191 +                       continue;
88192 +
88193 +               lp = &bundle->led[i];
88194 +
88195 +               lp->gpio = r->start;
88196 +               lp->cdev.name = r->name;
88197 +               lp->cdev.brightness_set = gta02led_set;
88198 +
88199 +               switch (lp->gpio) {
88200 +               case S3C2410_GPB0:
88201 +               case S3C2410_GPB1:
88202 +               case S3C2410_GPB2:
88203 +                       s3c2410_gpio_cfgpin(lp->gpio, S3C2410_GPIO_OUTPUT);
88204 +                       neo1973_gpb_add_shadow_gpio(lp->gpio);
88205 +                       break;
88206 +               default:
88207 +                       break;
88208 +               }
88209 +
88210 +               spin_lock_init(&lp->lock);
88211 +               rc = led_classdev_register(&pdev->dev, &lp->cdev);
88212 +       }
88213 +
88214 +       bundle->num_leds = i;
88215 +
88216 +       return 0;
88217 +}
88218 +
88219 +static int gta02led_remove(struct platform_device *pdev)
88220 +{
88221 +       struct gta02_led_bundle *bundle = platform_get_drvdata(pdev);
88222 +       int i;
88223 +
88224 +       for (i = 0; i < bundle->num_leds; i++) {
88225 +               struct gta02_led_priv *lp = &bundle->led[i];
88226 +               gta02led_set(&lp->cdev, 0);
88227 +               led_classdev_unregister(&lp->cdev);
88228 +       }
88229 +
88230 +       platform_set_drvdata(pdev, NULL);
88231 +       kfree(bundle);
88232 +
88233 +       return 0;
88234 +}
88235 +
88236 +static struct platform_driver gta02led_driver = {
88237 +       .probe          = gta02led_probe,
88238 +       .remove         = gta02led_remove,
88239 +#ifdef CONFIG_PM
88240 +       .suspend        = gta02led_suspend,
88241 +       .resume         = gta02led_resume,
88242 +#endif
88243 +       .driver         = {
88244 +               .name           = "gta02-led",
88245 +       },
88246 +};
88247 +
88248 +static int __init gta02led_init(void)
88249 +{
88250 +       return platform_driver_register(&gta02led_driver);
88251 +}
88252 +
88253 +static void __exit gta02led_exit(void)
88254 +{
88255 +       platform_driver_unregister(&gta02led_driver);
88256 +}
88257 +
88258 +module_init(gta02led_init);
88259 +module_exit(gta02led_exit);
88260 +
88261 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
88262 +MODULE_DESCRIPTION("Openmoko GTA02 LED driver");
88263 +MODULE_LICENSE("GPL");
88264 --- /dev/null
88265 +++ b/drivers/leds/leds-neo1973-vibrator.c
88266 @@ -0,0 +1,209 @@
88267 +/*
88268 + * LED driver for the vibrator of the Openmoko GTA01/GTA02 GSM Phones
88269 + *
88270 + * (C) 2006-2008 by Openmoko, Inc.
88271 + * Author: Harald Welte <laforge@openmoko.org>
88272 + * All rights reserved.
88273 + *
88274 + * This program is free software; you can redistribute it and/or modify
88275 + * it under the terms of the GNU General Public License version 2 as
88276 + * published by the Free Software Foundation.
88277 + *
88278 + * Javi Roman <javiroman@kernel-labs.org>:
88279 + *     Implement PWM support for GTA01Bv4 and later
88280 + */
88281 +
88282 +#include <linux/kernel.h>
88283 +#include <linux/init.h>
88284 +#include <linux/platform_device.h>
88285 +#include <linux/leds.h>
88286 +#include <mach/hardware.h>
88287 +#include <asm/mach-types.h>
88288 +#include <mach/pwm.h>
88289 +#include <mach/gta01.h>
88290 +#include <plat/regs-timer.h>
88291 +
88292 +#ifdef CONFIG_MACH_NEO1973_GTA02
88293 +#include <mach/fiq_ipc_gta02.h>
88294 +#endif
88295 +#include <asm/plat-s3c24xx/neo1973.h>
88296 +
88297 +#define COUNTER 64
88298 +
88299 +struct neo1973_vib_priv {
88300 +       struct led_classdev cdev;
88301 +       unsigned int gpio;
88302 +       spinlock_t lock;
88303 +       unsigned int has_pwm;
88304 +       struct s3c2410_pwm pwm;
88305 +};
88306 +
88307 +static void neo1973_vib_vib_set(struct led_classdev *led_cdev,
88308 +                               enum led_brightness value)
88309 +{
88310 +       unsigned long flags;
88311 +       struct neo1973_vib_priv *vp = container_of(led_cdev,
88312 +                                                  struct neo1973_vib_priv,
88313 +                                                  cdev);
88314 +
88315 +#ifdef CONFIG_MACH_NEO1973_GTA02
88316 +       if (machine_is_neo1973_gta02()) { /* use FIQ to control GPIO */
88317 +               fiq_ipc.vib_pwm = value; /* set it for FIQ */
88318 +               fiq_kick(); /* start up FIQs if not already going */
88319 +               return;
88320 +       }
88321 +#endif
88322 +       /*
88323 +        * value == 255 -> 99% duty cycle (full power)
88324 +        * value == 128 -> 50% duty cycle (medium power)
88325 +        * value == 0 -> 0% duty cycle (zero power)
88326 +        */
88327 +       spin_lock_irqsave(&vp->lock, flags);
88328 +       if (vp->has_pwm) {
88329 +               s3c2410_pwm_duty_cycle(value / 4, &vp->pwm);
88330 +       }
88331 +       else {
88332 +               neo1973_gpb_setpin(vp->gpio, value ? 1 : 0);
88333 +       }
88334 +       spin_unlock_irqrestore(&vp->lock, flags);
88335 +}
88336 +
88337 +static struct neo1973_vib_priv neo1973_vib_led = {
88338 +       .cdev = {
88339 +               .name = "neo1973:vibrator",
88340 +               .brightness_set = neo1973_vib_vib_set,
88341 +       },
88342 +};
88343 +
88344 +static int neo1973_vib_init_hw(struct neo1973_vib_priv *vp)
88345 +{
88346 +       int rc;
88347 +
88348 +       rc = s3c2410_pwm_init(&vp->pwm);
88349 +       if (rc)
88350 +               return rc;
88351 +
88352 +       vp->pwm.timerid = PWM3;
88353 +       /* use same prescaler as arch/arm/plat-s3c24xx/time.c */
88354 +       vp->pwm.prescaler = (6 - 1) / 2;
88355 +       vp->pwm.divider = S3C2410_TCFG1_MUX3_DIV2;
88356 +       vp->pwm.counter = COUNTER;
88357 +       vp->pwm.comparer = COUNTER;
88358 +
88359 +       rc = s3c2410_pwm_enable(&vp->pwm);
88360 +       if (rc)
88361 +               return rc;
88362 +
88363 +       s3c2410_pwm_start(&vp->pwm);
88364 +
88365 +       return 0;
88366 +}
88367 +
88368 +#ifdef CONFIG_PM
88369 +static int neo1973_vib_suspend(struct platform_device *dev, pm_message_t state)
88370 +{
88371 +       led_classdev_suspend(&neo1973_vib_led.cdev);
88372 +       return 0;
88373 +}
88374 +
88375 +static int neo1973_vib_resume(struct platform_device *dev)
88376 +{
88377 +       struct neo1973_vib_priv *vp = platform_get_drvdata(dev);
88378 +
88379 +       if (vp->has_pwm)
88380 +               neo1973_vib_init_hw(vp);
88381 +
88382 +       led_classdev_resume(&neo1973_vib_led.cdev);
88383 +
88384 +       return 0;
88385 +}
88386 +#endif /* CONFIG_PM */
88387 +
88388 +static int __init neo1973_vib_probe(struct platform_device *pdev)
88389 +{
88390 +       struct resource *r;
88391 +       int rc;
88392 +
88393 +       if (!machine_is_neo1973_gta01() && !machine_is_neo1973_gta02())
88394 +               return -EIO;
88395 +
88396 +       r = platform_get_resource(pdev, 0, 0);
88397 +       if (!r || !r->start)
88398 +               return -EIO;
88399 +
88400 +       neo1973_vib_led.gpio = r->start;
88401 +       platform_set_drvdata(pdev, &neo1973_vib_led);
88402 +
88403 +#ifdef CONFIG_MACH_NEO1973_GTA02
88404 +       if (machine_is_neo1973_gta02()) { /* use FIQ to control GPIO */
88405 +               neo1973_gpb_setpin(neo1973_vib_led.gpio, 0); /* off */
88406 +               s3c2410_gpio_cfgpin(neo1973_vib_led.gpio, S3C2410_GPIO_OUTPUT);
88407 +               /* safe, kmalloc'd copy needed for FIQ ISR */
88408 +               fiq_ipc.vib_gpio_pin = neo1973_vib_led.gpio;
88409 +               fiq_ipc.vib_pwm = 0; /* off */
88410 +               goto configured;
88411 +       }
88412 +#endif
88413 +
88414 +       /* TOUT3 */
88415 +       if (neo1973_vib_led.gpio == S3C2410_GPB3) {
88416 +               rc = neo1973_vib_init_hw(&neo1973_vib_led);
88417 +               if (rc)
88418 +                       return rc;
88419 +
88420 +               s3c2410_pwm_duty_cycle(0, &neo1973_vib_led.pwm);
88421 +               s3c2410_gpio_cfgpin(neo1973_vib_led.gpio, S3C2410_GPB3_TOUT3);
88422 +               neo1973_vib_led.has_pwm = 1;
88423 +       }
88424 +#ifdef CONFIG_MACH_NEO1973_GTA02
88425 +configured:
88426 +#endif
88427 +       spin_lock_init(&neo1973_vib_led.lock);
88428 +
88429 +       return led_classdev_register(&pdev->dev, &neo1973_vib_led.cdev);
88430 +}
88431 +
88432 +static int neo1973_vib_remove(struct platform_device *pdev)
88433 +{
88434 +#ifdef CONFIG_MACH_NEO1973_GTA02
88435 +       if (machine_is_neo1973_gta02()) /* use FIQ to control GPIO */
88436 +               fiq_ipc.vib_pwm = 0; /* off */
88437 +       /* would only need kick if already off so no kick needed */
88438 +#endif
88439 +
88440 +       if (neo1973_vib_led.has_pwm)
88441 +               s3c2410_pwm_disable(&neo1973_vib_led.pwm);
88442 +
88443 +       led_classdev_unregister(&neo1973_vib_led.cdev);
88444 +
88445 +       return 0;
88446 +}
88447 +
88448 +static struct platform_driver neo1973_vib_driver = {
88449 +       .probe          = neo1973_vib_probe,
88450 +       .remove         = neo1973_vib_remove,
88451 +#ifdef CONFIG_PM
88452 +       .suspend        = neo1973_vib_suspend,
88453 +       .resume         = neo1973_vib_resume,
88454 +#endif
88455 +       .driver         = {
88456 +               .name           = "neo1973-vibrator",
88457 +       },
88458 +};
88459 +
88460 +static int __init neo1973_vib_init(void)
88461 +{
88462 +       return platform_driver_register(&neo1973_vib_driver);
88463 +}
88464 +
88465 +static void __exit neo1973_vib_exit(void)
88466 +{
88467 +       platform_driver_unregister(&neo1973_vib_driver);
88468 +}
88469 +
88470 +module_init(neo1973_vib_init);
88471 +module_exit(neo1973_vib_exit);
88472 +
88473 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
88474 +MODULE_DESCRIPTION("Openmoko GTA01/GTA02 vibrator driver");
88475 +MODULE_LICENSE("GPL");
88476 --- a/drivers/leds/Makefile
88477 +++ b/drivers/leds/Makefile
88478 @@ -24,6 +24,8 @@ obj-$(CONFIG_LEDS_FSG)                        += leds-fsg.o
88479  obj-$(CONFIG_LEDS_PCA955X)             += leds-pca955x.o
88480  obj-$(CONFIG_LEDS_DA903X)              += leds-da903x.o
88481  obj-$(CONFIG_LEDS_HP_DISK)             += leds-hp-disk.o
88482 +obj-$(CONFIG_LEDS_NEO1973_VIBRATOR)    += leds-neo1973-vibrator.o
88483 +obj-$(CONFIG_LEDS_NEO1973_GTA02)       += leds-neo1973-gta02.o
88484
88485  # LED Triggers
88486  obj-$(CONFIG_LEDS_TRIGGER_TIMER)       += ledtrig-timer.o
88487 --- a/drivers/Makefile
88488 +++ b/drivers/Makefile
88489 @@ -86,6 +86,7 @@ obj-$(CONFIG_CPU_IDLE)                += cpuidle/
88490  obj-y                          += idle/
88491  obj-$(CONFIG_MMC)              += mmc/
88492  obj-$(CONFIG_MEMSTICK)         += memstick/
88493 +obj-$(CONFIG_AR6000_WLAN)      += ar6000/
88494  obj-$(CONFIG_NEW_LEDS)         += leds/
88495  obj-$(CONFIG_INFINIBAND)       += infiniband/
88496  obj-$(CONFIG_SGI_SN)           += sn/
88497 @@ -98,6 +99,7 @@ obj-$(CONFIG_DCA)             += dca/
88498  obj-$(CONFIG_HID)              += hid/
88499  obj-$(CONFIG_PPC_PS3)          += ps3/
88500  obj-$(CONFIG_OF)               += of/
88501 +obj-y                          += android/
88502  obj-$(CONFIG_SSB)              += ssb/
88503  obj-$(CONFIG_VIRTIO)           += virtio/
88504  obj-$(CONFIG_REGULATOR)                += regulator/
88505 --- /dev/null
88506 +++ b/drivers/mfd/glamo/glamo-core.c
88507 @@ -0,0 +1,1399 @@
88508 +/* Smedia Glamo 336x/337x driver
88509 + *
88510 + * (C) 2007 by Openmoko, Inc.
88511 + * Author: Harald Welte <laforge@openmoko.org>
88512 + * All rights reserved.
88513 + *
88514 + * This program is free software; you can redistribute it and/or
88515 + * modify it under the terms of the GNU General Public License as
88516 + * published by the Free Software Foundation; either version 2 of
88517 + * the License, or (at your option) any later version.
88518 + *
88519 + * This program is distributed in the hope that it will be useful,
88520 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
88521 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
88522 + * GNU General Public License for more details.
88523 + *
88524 + * You should have received a copy of the GNU General Public License
88525 + * along with this program; if not, write to the Free Software
88526 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
88527 + * MA 02111-1307 USA
88528 + */
88529 +
88530 +#include <linux/module.h>
88531 +#include <linux/kernel.h>
88532 +#include <linux/errno.h>
88533 +#include <linux/string.h>
88534 +#include <linux/mm.h>
88535 +#include <linux/tty.h>
88536 +#include <linux/slab.h>
88537 +#include <linux/delay.h>
88538 +#include <linux/fb.h>
88539 +#include <linux/init.h>
88540 +#include <linux/irq.h>
88541 +#include <linux/interrupt.h>
88542 +#include <linux/workqueue.h>
88543 +#include <linux/wait.h>
88544 +#include <linux/platform_device.h>
88545 +#include <linux/kernel_stat.h>
88546 +#include <linux/spinlock.h>
88547 +#include <linux/glamofb.h>
88548 +#include <linux/mmc/mmc.h>
88549 +#include <linux/mmc/host.h>
88550 +
88551 +#include <asm/io.h>
88552 +#include <asm/uaccess.h>
88553 +#include <asm/div64.h>
88554 +
88555 +//#include <mach/regs-irq.h>
88556 +
88557 +#ifdef CONFIG_PM
88558 +#include <linux/pm.h>
88559 +#endif
88560 +
88561 +#include "glamo-regs.h"
88562 +#include "glamo-core.h"
88563 +
88564 +#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
88565 +
88566 +#define GLAMO_MEM_REFRESH_COUNT 0x100
88567 +
88568 +struct reg_range {
88569 +       int start;
88570 +       int count;
88571 +       char *name;
88572 +       char dump;
88573 +};
88574 +struct reg_range reg_range[] = {
88575 +       { 0x0000, 0x76,         "General",      1 },
88576 +       { 0x0200, 0x16,         "Host Bus",     1 },
88577 +       { 0x0300, 0x38,         "Memory",       1 },
88578 +/*     { 0x0400, 0x100,        "Sensor",       0 }, */
88579 +/*             { 0x0500, 0x300,        "ISP",          0 }, */
88580 +/*             { 0x0800, 0x400,        "JPEG",         0 }, */
88581 +/*             { 0x0c00, 0xcc,         "MPEG",         0 }, */
88582 +       { 0x1100, 0xb2,         "LCD 1",        1 },
88583 +       { 0x1200, 0x64,         "LCD 2",        1 },
88584 +       { 0x1400, 0x40,         "MMC",          1 },
88585 +/*             { 0x1500, 0x080,        "MPU 0",        0 },
88586 +       { 0x1580, 0x080,        "MPU 1",        0 },
88587 +       { 0x1600, 0x080,        "Cmd Queue",    0 },
88588 +       { 0x1680, 0x080,        "RISC CPU",     0 },
88589 +       { 0x1700, 0x400,        "2D Unit",      0 },
88590 +       { 0x1b00, 0x900,        "3D Unit",      0 }, */
88591 +};
88592 +
88593 +static struct glamo_core *glamo_handle;
88594 +
88595 +static inline void __reg_write(struct glamo_core *glamo,
88596 +                               u_int16_t reg, u_int16_t val)
88597 +{
88598 +       writew(val, glamo->base + reg);
88599 +}
88600 +
88601 +static inline u_int16_t __reg_read(struct glamo_core *glamo,
88602 +                                  u_int16_t reg)
88603 +{
88604 +       return readw(glamo->base + reg);
88605 +}
88606 +
88607 +static void __reg_set_bit_mask(struct glamo_core *glamo,
88608 +                               u_int16_t reg, u_int16_t mask,
88609 +                               u_int16_t val)
88610 +{
88611 +       u_int16_t tmp;
88612 +
88613 +       val &= mask;
88614 +
88615 +       tmp = __reg_read(glamo, reg);
88616 +       tmp &= ~mask;
88617 +       tmp |= val;
88618 +       __reg_write(glamo, reg, tmp);
88619 +}
88620 +
88621 +static void reg_set_bit_mask(struct glamo_core *glamo,
88622 +                               u_int16_t reg, u_int16_t mask,
88623 +                               u_int16_t val)
88624 +{
88625 +       spin_lock(&glamo->lock);
88626 +       __reg_set_bit_mask(glamo, reg, mask, val);
88627 +       spin_unlock(&glamo->lock);
88628 +}
88629 +
88630 +static inline void __reg_set_bit(struct glamo_core *glamo,
88631 +                                u_int16_t reg, u_int16_t bit)
88632 +{
88633 +       __reg_set_bit_mask(glamo, reg, bit, 0xffff);
88634 +}
88635 +
88636 +static inline void __reg_clear_bit(struct glamo_core *glamo,
88637 +                                  u_int16_t reg, u_int16_t bit)
88638 +{
88639 +       __reg_set_bit_mask(glamo, reg, bit, 0);
88640 +}
88641 +
88642 +static inline void glamo_vmem_write(struct glamo_core *glamo, u_int32_t addr,
88643 +                                   u_int16_t *src, int len)
88644 +{
88645 +       if (addr & 0x0001 || (unsigned long)src & 0x0001 || len & 0x0001) {
88646 +               dev_err(&glamo->pdev->dev, "unaligned write(0x%08x, 0x%p, "
88647 +                       "0x%x)!!\n", addr, src, len);
88648 +       }
88649 +
88650 +}
88651 +
88652 +static inline void glamo_vmem_read(struct glamo_core *glamo, u_int16_t *buf,
88653 +                                  u_int32_t addr, int len)
88654 +{
88655 +       if (addr & 0x0001 || (unsigned long) buf & 0x0001 || len & 0x0001) {
88656 +               dev_err(&glamo->pdev->dev, "unaligned read(0x%p, 0x08%x, "
88657 +                       "0x%x)!!\n", buf, addr, len);
88658 +       }
88659 +
88660 +
88661 +}
88662 +
88663 +/***********************************************************************
88664 + * resources of sibling devices
88665 + ***********************************************************************/
88666 +
88667 +#if 0
88668 +static struct resource glamo_core_resources[] = {
88669 +       {
88670 +               .start  = GLAMO_REGOFS_GENERIC,
88671 +               .end    = GLAMO_REGOFS_GENERIC + 0x400,
88672 +               .flags  = IORESOURCE_MEM,
88673 +       }, {
88674 +               .start  = 0,
88675 +               .end    = 0,
88676 +               .flags  = IORESOURCE_IRQ,
88677 +       },
88678 +};
88679 +
88680 +static struct platform_device glamo_core_dev = {
88681 +       .name           = "glamo-core",
88682 +       .resource       = &glamo_core_resources,
88683 +       .num_resources  = ARRAY_SIZE(glamo_core_resources),
88684 +};
88685 +#endif
88686 +
88687 +static struct resource glamo_jpeg_resources[] = {
88688 +       {
88689 +               .start  = GLAMO_REGOFS_JPEG,
88690 +               .end    = GLAMO_REGOFS_MPEG - 1,
88691 +               .flags  = IORESOURCE_MEM,
88692 +       }, {
88693 +               .start  = IRQ_GLAMO_JPEG,
88694 +               .end    = IRQ_GLAMO_JPEG,
88695 +               .flags  = IORESOURCE_IRQ,
88696 +       },
88697 +};
88698 +
88699 +static struct platform_device glamo_jpeg_dev = {
88700 +       .name           = "glamo-jpeg",
88701 +       .resource       = glamo_jpeg_resources,
88702 +       .num_resources  = ARRAY_SIZE(glamo_jpeg_resources),
88703 +};
88704 +
88705 +static struct resource glamo_mpeg_resources[] = {
88706 +       {
88707 +               .start  = GLAMO_REGOFS_MPEG,
88708 +               .end    = GLAMO_REGOFS_LCD - 1,
88709 +               .flags  = IORESOURCE_MEM,
88710 +       }, {
88711 +               .start  = IRQ_GLAMO_MPEG,
88712 +               .end    = IRQ_GLAMO_MPEG,
88713 +               .flags  = IORESOURCE_IRQ,
88714 +       },
88715 +};
88716 +
88717 +static struct platform_device glamo_mpeg_dev = {
88718 +       .name           = "glamo-mpeg",
88719 +       .resource       = glamo_mpeg_resources,
88720 +       .num_resources  = ARRAY_SIZE(glamo_mpeg_resources),
88721 +};
88722 +
88723 +static struct resource glamo_2d_resources[] = {
88724 +       {
88725 +               .start  = GLAMO_REGOFS_2D,
88726 +               .end    = GLAMO_REGOFS_3D - 1,
88727 +               .flags  = IORESOURCE_MEM,
88728 +       }, {
88729 +               .start  = IRQ_GLAMO_2D,
88730 +               .end    = IRQ_GLAMO_2D,
88731 +               .flags  = IORESOURCE_IRQ,
88732 +       },
88733 +};
88734 +
88735 +static struct platform_device glamo_2d_dev = {
88736 +       .name           = "glamo-2d",
88737 +       .resource       = glamo_2d_resources,
88738 +       .num_resources  = ARRAY_SIZE(glamo_2d_resources),
88739 +};
88740 +
88741 +static struct resource glamo_3d_resources[] = {
88742 +       {
88743 +               .start  = GLAMO_REGOFS_3D,
88744 +               .end    = GLAMO_REGOFS_END - 1,
88745 +               .flags  = IORESOURCE_MEM,
88746 +       },
88747 +};
88748 +
88749 +static struct platform_device glamo_3d_dev = {
88750 +       .name           = "glamo-3d",
88751 +       .resource       = glamo_3d_resources,
88752 +       .num_resources  = ARRAY_SIZE(glamo_3d_resources),
88753 +};
88754 +
88755 +static struct platform_device glamo_spigpio_dev = {
88756 +       .name           = "glamo-spi-gpio",
88757 +};
88758 +
88759 +static struct resource glamo_fb_resources[] = {
88760 +       /* FIXME: those need to be incremented by parent base */
88761 +       {
88762 +               .name   = "glamo-fb-regs",
88763 +               .start  = GLAMO_REGOFS_LCD,
88764 +               .end    = GLAMO_REGOFS_MMC - 1,
88765 +               .flags  = IORESOURCE_MEM,
88766 +       }, {
88767 +               .name   = "glamo-fb-mem",
88768 +               .start  = GLAMO_OFFSET_FB,
88769 +               .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
88770 +               .flags  = IORESOURCE_MEM,
88771 +       },
88772 +};
88773 +
88774 +static struct platform_device glamo_fb_dev = {
88775 +       .name           = "glamo-fb",
88776 +       .resource       = glamo_fb_resources,
88777 +       .num_resources  = ARRAY_SIZE(glamo_fb_resources),
88778 +};
88779 +
88780 +static struct resource glamo_mmc_resources[] = {
88781 +       {
88782 +               /* FIXME: those need to be incremented by parent base */
88783 +               .start  = GLAMO_REGOFS_MMC,
88784 +               .end    = GLAMO_REGOFS_MPROC0 - 1,
88785 +               .flags  = IORESOURCE_MEM
88786 +       }, {
88787 +               .start  = IRQ_GLAMO_MMC,
88788 +               .end    = IRQ_GLAMO_MMC,
88789 +               .flags  = IORESOURCE_IRQ,
88790 +       }, { /* our data buffer for MMC transfers */
88791 +               .start  = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
88792 +               .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
88793 +                                 GLAMO_MMC_BUFFER_SIZE - 1,
88794 +               .flags  = IORESOURCE_MEM
88795 +       },
88796 +};
88797 +
88798 +struct glamo_mci_pdata glamo_mci_def_pdata = {
88799 +       .gpio_detect            = 0,
88800 +       .glamo_can_set_mci_power        = NULL, /* filled in from MFD platform data */
88801 +       .ocr_avail      = MMC_VDD_20_21 |
88802 +                         MMC_VDD_21_22 |
88803 +                         MMC_VDD_22_23 |
88804 +                         MMC_VDD_23_24 |
88805 +                         MMC_VDD_24_25 |
88806 +                         MMC_VDD_25_26 |
88807 +                         MMC_VDD_26_27 |
88808 +                         MMC_VDD_27_28 |
88809 +                         MMC_VDD_28_29 |
88810 +                         MMC_VDD_29_30 |
88811 +                         MMC_VDD_30_31 |
88812 +                         MMC_VDD_32_33,
88813 +       .glamo_irq_is_wired     = NULL, /* filled in from MFD platform data */
88814 +       .mci_suspending = NULL, /* filled in from MFD platform data */
88815 +       .mci_all_dependencies_resumed = NULL, /* filled in from MFD platform data */
88816 +};
88817 +EXPORT_SYMBOL_GPL(glamo_mci_def_pdata);
88818 +
88819 +
88820 +
88821 +static void mangle_mem_resources(struct resource *res, int num_res,
88822 +                                struct resource *parent)
88823 +{
88824 +       int i;
88825 +
88826 +       for (i = 0; i < num_res; i++) {
88827 +               if (res[i].flags != IORESOURCE_MEM)
88828 +                       continue;
88829 +               res[i].start += parent->start;
88830 +               res[i].end += parent->start;
88831 +               res[i].parent = parent;
88832 +       }
88833 +}
88834 +
88835 +/***********************************************************************
88836 + * IRQ demultiplexer
88837 + ***********************************************************************/
88838 +#define irq2glamo(x)   (x - IRQ_GLAMO(0))
88839 +
88840 +static void glamo_ack_irq(unsigned int irq)
88841 +{
88842 +       /* clear interrupt source */
88843 +       __reg_write(glamo_handle, GLAMO_REG_IRQ_CLEAR,
88844 +                   1 << irq2glamo(irq));
88845 +}
88846 +
88847 +static void glamo_mask_irq(unsigned int irq)
88848 +{
88849 +       u_int16_t tmp;
88850 +
88851 +       /* clear bit in enable register */
88852 +       tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
88853 +       tmp &= ~(1 << irq2glamo(irq));
88854 +       __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
88855 +}
88856 +
88857 +static void glamo_unmask_irq(unsigned int irq)
88858 +{
88859 +       u_int16_t tmp;
88860 +
88861 +       /* set bit in enable register */
88862 +       tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
88863 +       tmp |= (1 << irq2glamo(irq));
88864 +       __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
88865 +}
88866 +
88867 +static struct irq_chip glamo_irq_chip = {
88868 +       .ack    = glamo_ack_irq,
88869 +       .mask   = glamo_mask_irq,
88870 +       .unmask = glamo_unmask_irq,
88871 +};
88872 +
88873 +static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
88874 +{
88875 +       const unsigned int cpu = smp_processor_id();
88876 +
88877 +       desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
88878 +
88879 +       if (unlikely(desc->status & IRQ_INPROGRESS)) {
88880 +               desc->status |= (IRQ_PENDING | IRQ_MASKED);
88881 +               desc->chip->mask(irq);
88882 +               desc->chip->ack(irq);
88883 +               return;
88884 +       }
88885 +
88886 +       kstat_cpu(cpu).irqs[irq]++;
88887 +       desc->chip->ack(irq);
88888 +       desc->status |= IRQ_INPROGRESS;
88889 +
88890 +       do {
88891 +               u_int16_t irqstatus;
88892 +               int i;
88893 +
88894 +               if (unlikely((desc->status &
88895 +                               (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
88896 +                               (IRQ_PENDING | IRQ_MASKED))) {
88897 +                       /* dealing with pending IRQ, unmasking */
88898 +                       desc->chip->unmask(irq);
88899 +                       desc->status &= ~IRQ_MASKED;
88900 +               }
88901 +
88902 +               desc->status &= ~IRQ_PENDING;
88903 +
88904 +               /* read IRQ status register */
88905 +               irqstatus = __reg_read(glamo_handle, GLAMO_REG_IRQ_STATUS);
88906 +               for (i = 0; i < 9; i++)
88907 +                       if (irqstatus & (1 << i))
88908 +                               desc_handle_irq(IRQ_GLAMO(i),
88909 +                                   irq_desc+IRQ_GLAMO(i));
88910 +
88911 +       } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
88912 +
88913 +       desc->status &= ~IRQ_INPROGRESS;
88914 +}
88915 +
88916 +
88917 +static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
88918 +                          const char *buf, size_t count)
88919 +{
88920 +       unsigned long reg = simple_strtoul(buf, NULL, 10);
88921 +       struct glamo_core *glamo = dev_get_drvdata(dev);
88922 +
88923 +       while (*buf && (*buf != ' '))
88924 +               buf++;
88925 +       if (*buf != ' ')
88926 +               return -EINVAL;
88927 +       while (*buf && (*buf == ' '))
88928 +               buf++;
88929 +       if (!*buf)
88930 +               return -EINVAL;
88931 +
88932 +       printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
88933 +              reg, simple_strtoul(buf, NULL, 10));
88934 +
88935 +       __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
88936 +
88937 +       return count;
88938 +}
88939 +
88940 +static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
88941 +                       char *buf)
88942 +{
88943 +       struct glamo_core *glamo = dev_get_drvdata(dev);
88944 +       int n, n1 = 0, r;
88945 +       char * end = buf;
88946 +
88947 +       spin_lock(&glamo->lock);
88948 +
88949 +       for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
88950 +               if (!reg_range[r].dump)
88951 +                       continue;
88952 +               n1 = 0;
88953 +               end += sprintf(end, "\n%s\n", reg_range[r].name);
88954 +               for (n = reg_range[r].start;
88955 +                    n < reg_range[r].start + reg_range[r].count; n += 2) {
88956 +                       if (((n1++) & 7) == 0)
88957 +                               end += sprintf(end, "\n%04X:  ", n);
88958 +                       end += sprintf(end, "%04x ", __reg_read(glamo, n));
88959 +               }
88960 +               end += sprintf(end, "\n");
88961 +               if (!attr) {
88962 +                       printk("%s", buf);
88963 +                       end = buf;
88964 +               }
88965 +       }
88966 +       spin_unlock(&glamo->lock);
88967 +
88968 +       return end - buf;
88969 +}
88970 +
88971 +static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
88972 +static struct attribute *glamo_sysfs_entries[] = {
88973 +       &dev_attr_regs.attr,
88974 +       NULL
88975 +};
88976 +static struct attribute_group glamo_attr_group = {
88977 +       .name   = NULL,
88978 +       .attrs  = glamo_sysfs_entries,
88979 +};
88980 +
88981 +
88982 +
88983 +/***********************************************************************
88984 + * 'engine' support
88985 + ***********************************************************************/
88986 +
88987 +int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
88988 +{
88989 +       switch (engine) {
88990 +       case GLAMO_ENGINE_LCD:
88991 +               __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
88992 +                                  GLAMO_HOSTBUS2_MMIO_EN_LCD,
88993 +                                  GLAMO_HOSTBUS2_MMIO_EN_LCD);
88994 +               __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
88995 +                           GLAMO_CLOCK_LCD_EN_M5CLK |
88996 +                           GLAMO_CLOCK_LCD_EN_DHCLK |
88997 +                           GLAMO_CLOCK_LCD_EN_DMCLK |
88998 +                           GLAMO_CLOCK_LCD_EN_DCLK |
88999 +                           GLAMO_CLOCK_LCD_DG_M5CLK |
89000 +                           GLAMO_CLOCK_LCD_DG_DMCLK);
89001 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
89002 +                           GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
89003 +                           GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
89004 +                           GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
89005 +               break;
89006 +       case GLAMO_ENGINE_MMC:
89007 +               __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
89008 +                                  GLAMO_HOSTBUS2_MMIO_EN_MMC,
89009 +                                  GLAMO_HOSTBUS2_MMIO_EN_MMC);
89010 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
89011 +                                  GLAMO_CLOCK_MMC_EN_M9CLK |
89012 +                                  GLAMO_CLOCK_MMC_EN_TCLK |
89013 +                                  GLAMO_CLOCK_MMC_DG_M9CLK |
89014 +                                  GLAMO_CLOCK_MMC_DG_TCLK, 0xffff);
89015 +               /* enable the TCLK divider clk input */
89016 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
89017 +                                                GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
89018 +                                                GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
89019 +               break;
89020 +       case GLAMO_ENGINE_2D:
89021 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
89022 +                                  GLAMO_CLOCK_2D_EN_M7CLK |
89023 +                                  GLAMO_CLOCK_2D_EN_GCLK |
89024 +                                  GLAMO_CLOCK_2D_DG_M7CLK |
89025 +                                  GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
89026 +               __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
89027 +                                  GLAMO_HOSTBUS2_MMIO_EN_2D,
89028 +                                  GLAMO_HOSTBUS2_MMIO_EN_2D);
89029 +               break;
89030 +       case GLAMO_ENGINE_CMDQ:
89031 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
89032 +                                  GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
89033 +               __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
89034 +                                  GLAMO_HOSTBUS2_MMIO_EN_CQ,
89035 +                                  GLAMO_HOSTBUS2_MMIO_EN_CQ);
89036 +               break;
89037 +       /* FIXME: Implementation */
89038 +       default:
89039 +               break;
89040 +       }
89041 +
89042 +       glamo->engine_enabled_bitfield |= 1 << engine;
89043 +
89044 +       return 0;
89045 +}
89046 +
89047 +int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
89048 +{
89049 +       int ret;
89050 +
89051 +       spin_lock(&glamo->lock);
89052 +
89053 +       ret = __glamo_engine_enable(glamo, engine);
89054 +
89055 +       spin_unlock(&glamo->lock);
89056 +
89057 +       return ret;
89058 +}
89059 +EXPORT_SYMBOL_GPL(glamo_engine_enable);
89060 +
89061 +int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
89062 +{
89063 +       switch (engine) {
89064 +       case GLAMO_ENGINE_LCD:
89065 +               /* remove pixel clock to LCM */
89066 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
89067 +                           GLAMO_CLOCK_LCD_EN_DCLK, 0);
89068 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
89069 +                           GLAMO_CLOCK_LCD_EN_DHCLK |
89070 +                           GLAMO_CLOCK_LCD_EN_DMCLK, 0);
89071 +               /* kill memory clock */
89072 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
89073 +                           GLAMO_CLOCK_LCD_EN_M5CLK, 0);
89074 +               /* stop dividing the clocks */
89075 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
89076 +                           GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
89077 +                           GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
89078 +                           GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
89079 +               break;
89080 +
89081 +       case GLAMO_ENGINE_MMC:
89082 +//             __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
89083 +//                                                GLAMO_CLOCK_MMC_EN_M9CLK |
89084 +//                                                GLAMO_CLOCK_MMC_EN_TCLK |
89085 +//                                                GLAMO_CLOCK_MMC_DG_M9CLK |
89086 +//                                                GLAMO_CLOCK_MMC_DG_TCLK, 0);
89087 +               /* disable the TCLK divider clk input */
89088 +//             __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
89089 +//                                     GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
89090 +
89091 +       default:
89092 +               break;
89093 +       }
89094 +
89095 +       glamo->engine_enabled_bitfield &= ~(1 << engine);
89096 +
89097 +       return 0;
89098 +}
89099 +int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
89100 +{
89101 +       int ret;
89102 +
89103 +       spin_lock(&glamo->lock);
89104 +
89105 +       ret = __glamo_engine_disable(glamo, engine);
89106 +
89107 +       spin_unlock(&glamo->lock);
89108 +
89109 +       return ret;
89110 +}
89111 +EXPORT_SYMBOL_GPL(glamo_engine_disable);
89112 +
89113 +static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
89114 +       [GLAMO_ENGINE_LCD]      = GLAMO_REG_CLOCK_LCD,
89115 +       [GLAMO_ENGINE_MMC]      = GLAMO_REG_CLOCK_MMC,
89116 +       [GLAMO_ENGINE_ISP]      = GLAMO_REG_CLOCK_ISP,
89117 +       [GLAMO_ENGINE_JPEG]     = GLAMO_REG_CLOCK_JPEG,
89118 +       [GLAMO_ENGINE_3D]       = GLAMO_REG_CLOCK_3D,
89119 +       [GLAMO_ENGINE_2D]       = GLAMO_REG_CLOCK_2D,
89120 +       [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
89121 +       [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
89122 +};
89123 +
89124 +void glamo_engine_clkreg_set(struct glamo_core *glamo,
89125 +                            enum glamo_engine engine,
89126 +                            u_int16_t mask, u_int16_t val)
89127 +{
89128 +       reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
89129 +}
89130 +EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
89131 +
89132 +u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
89133 +                                 enum glamo_engine engine)
89134 +{
89135 +       u_int16_t val;
89136 +
89137 +       spin_lock(&glamo->lock);
89138 +       val = __reg_read(glamo, engine_clock_regs[engine]);
89139 +       spin_unlock(&glamo->lock);
89140 +
89141 +       return val;
89142 +}
89143 +EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
89144 +
89145 +struct glamo_script reset_regs[] = {
89146 +       [GLAMO_ENGINE_LCD] = {
89147 +               GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
89148 +       },
89149 +#if 0
89150 +       [GLAMO_ENGINE_HOST] = {
89151 +               GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
89152 +       },
89153 +       [GLAMO_ENGINE_MEM] = {
89154 +               GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
89155 +       },
89156 +#endif
89157 +       [GLAMO_ENGINE_MMC] = {
89158 +               GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
89159 +       },
89160 +       [GLAMO_ENGINE_2D] = {
89161 +               GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
89162 +       },
89163 +       [GLAMO_ENGINE_JPEG] = {
89164 +               GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
89165 +       },
89166 +};
89167 +
89168 +void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
89169 +{
89170 +       struct glamo_script *rst;
89171 +
89172 +       if (engine >= ARRAY_SIZE(reset_regs)) {
89173 +               dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
89174 +               return;
89175 +       }
89176 +
89177 +       rst = &reset_regs[engine];
89178 +
89179 +       spin_lock(&glamo->lock);
89180 +       __reg_set_bit(glamo, rst->reg, rst->val);
89181 +       __reg_clear_bit(glamo, rst->reg, rst->val);
89182 +       spin_unlock(&glamo->lock);
89183 +}
89184 +EXPORT_SYMBOL_GPL(glamo_engine_reset);
89185 +
89186 +void glamo_lcm_reset(int level)
89187 +{
89188 +       if (!glamo_handle)
89189 +               return;
89190 +
89191 +       glamo_gpio_setpin(glamo_handle, GLAMO_GPIO4, level);
89192 +       glamo_gpio_cfgpin(glamo_handle, GLAMO_GPIO4_OUTPUT);
89193 +
89194 +}
89195 +EXPORT_SYMBOL_GPL(glamo_lcm_reset);
89196 +
89197 +enum glamo_pll {
89198 +       GLAMO_PLL1,
89199 +       GLAMO_PLL2,
89200 +};
89201 +
89202 +static int glamo_pll_rate(struct glamo_core *glamo,
89203 +                         enum glamo_pll pll)
89204 +{
89205 +       u_int16_t reg;
89206 +       unsigned int div = 512;
89207 +       /* FIXME: move osci into platform_data */
89208 +       unsigned int osci = 32768;
89209 +
89210 +       if (osci == 32768)
89211 +               div = 1;
89212 +
89213 +       switch (pll) {
89214 +       case GLAMO_PLL1:
89215 +               reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
89216 +               break;
89217 +       case GLAMO_PLL2:
89218 +               reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
89219 +               break;
89220 +       default:
89221 +               return -EINVAL;
89222 +       }
89223 +       return (osci/div)*reg;
89224 +}
89225 +
89226 +int glamo_engine_reclock(struct glamo_core *glamo,
89227 +                        enum glamo_engine engine,
89228 +                        int ps)
89229 +{
89230 +       int pll, khz;
89231 +       u_int16_t reg, mask, val = 0;
89232 +
89233 +       if (!ps)
89234 +               return 0;
89235 +
89236 +       switch (engine) {
89237 +       case GLAMO_ENGINE_LCD:
89238 +               pll = GLAMO_PLL1;
89239 +               reg = GLAMO_REG_CLOCK_GEN7;
89240 +               mask = 0xff;
89241 +               break;
89242 +       default:
89243 +               dev_warn(&glamo->pdev->dev,
89244 +                        "reclock of engine 0x%x not supported\n", engine);
89245 +               return -EINVAL;
89246 +               break;
89247 +       }
89248 +
89249 +       pll = glamo_pll_rate(glamo, pll);
89250 +       khz = 1000000000UL / ps;
89251 +
89252 +       if (khz)
89253 +               val = (pll / khz) / 1000;
89254 +
89255 +       dev_dbg(&glamo->pdev->dev,
89256 +                       "PLL %d, kHZ %d, div %d\n", pll, khz, val);
89257 +
89258 +       if (val) {
89259 +               val--;
89260 +               reg_set_bit_mask(glamo, reg, mask, val);
89261 +               mdelay(5); /* wait some time to stabilize */
89262 +
89263 +               return 0;
89264 +       } else {
89265 +               return -EINVAL;
89266 +       }
89267 +}
89268 +EXPORT_SYMBOL_GPL(glamo_engine_reclock);
89269 +
89270 +/***********************************************************************
89271 + * script support
89272 + ***********************************************************************/
89273 +
89274 +int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
89275 +                    int len, int may_sleep)
89276 +{
89277 +       int i;
89278 +
89279 +       for (i = 0; i < len; i++) {
89280 +               struct glamo_script *line = &script[i];
89281 +
89282 +               switch (line->reg) {
89283 +               case 0xffff:
89284 +                       return 0;
89285 +               case 0xfffe:
89286 +                       if (may_sleep)
89287 +                               msleep(line->val);
89288 +                       else
89289 +                               mdelay(line->val * 4);
89290 +                       break;
89291 +               case 0xfffd:
89292 +                       /* spin until PLLs lock */
89293 +                       while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
89294 +                               ;
89295 +                       break;
89296 +               default:
89297 +                       __reg_write(glamo, script[i].reg, script[i].val);
89298 +                       break;
89299 +               }
89300 +       }
89301 +
89302 +       return 0;
89303 +}
89304 +EXPORT_SYMBOL(glamo_run_script);
89305 +
89306 +static struct glamo_script glamo_init_script[] = {
89307 +       { GLAMO_REG_CLOCK_HOST,         0x1000 },
89308 +               { 0xfffe, 2 },
89309 +       { GLAMO_REG_CLOCK_MEMORY,       0x1000 },
89310 +       { GLAMO_REG_CLOCK_MEMORY,       0x2000 },
89311 +       { GLAMO_REG_CLOCK_LCD,          0x1000 },
89312 +       { GLAMO_REG_CLOCK_MMC,          0x1000 },
89313 +       { GLAMO_REG_CLOCK_ISP,          0x1000 },
89314 +       { GLAMO_REG_CLOCK_ISP,          0x3000 },
89315 +       { GLAMO_REG_CLOCK_JPEG,         0x1000 },
89316 +       { GLAMO_REG_CLOCK_3D,           0x1000 },
89317 +       { GLAMO_REG_CLOCK_3D,           0x3000 },
89318 +       { GLAMO_REG_CLOCK_2D,           0x1000 },
89319 +       { GLAMO_REG_CLOCK_2D,           0x3000 },
89320 +       { GLAMO_REG_CLOCK_RISC1,        0x1000 },
89321 +       { GLAMO_REG_CLOCK_MPEG,         0x3000 },
89322 +       { GLAMO_REG_CLOCK_MPEG,         0x3000 },
89323 +       { GLAMO_REG_CLOCK_MPROC,        0x1000 /*0x100f*/ },
89324 +               { 0xfffe, 2 },
89325 +       { GLAMO_REG_CLOCK_HOST,         0x0000 },
89326 +       { GLAMO_REG_CLOCK_MEMORY,       0x0000 },
89327 +       { GLAMO_REG_CLOCK_LCD,          0x0000 },
89328 +       { GLAMO_REG_CLOCK_MMC,          0x0000 },
89329 +#if 0
89330 +/* unused engines must be left in reset to stop MMC block read "blackouts" */
89331 +       { GLAMO_REG_CLOCK_ISP,          0x0000 },
89332 +       { GLAMO_REG_CLOCK_ISP,          0x0000 },
89333 +       { GLAMO_REG_CLOCK_JPEG,         0x0000 },
89334 +       { GLAMO_REG_CLOCK_3D,           0x0000 },
89335 +       { GLAMO_REG_CLOCK_3D,           0x0000 },
89336 +       { GLAMO_REG_CLOCK_2D,           0x0000 },
89337 +       { GLAMO_REG_CLOCK_2D,           0x0000 },
89338 +       { GLAMO_REG_CLOCK_RISC1,        0x0000 },
89339 +       { GLAMO_REG_CLOCK_MPEG,         0x0000 },
89340 +       { GLAMO_REG_CLOCK_MPEG,         0x0000 },
89341 +#endif
89342 +       { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
89343 +       { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
89344 +       { 0xfffd, 0 },
89345 +       /*
89346 +        * b9 of this register MUST be zero to get any interrupts on INT#
89347 +        * the other set bits enable all the engine interrupt sources
89348 +        */
89349 +       { GLAMO_REG_IRQ_ENABLE,         0x01ff },
89350 +       { GLAMO_REG_CLOCK_GEN6,         0x2000 },
89351 +       { GLAMO_REG_CLOCK_GEN7,         0x0101 },
89352 +       { GLAMO_REG_CLOCK_GEN8,         0x0100 },
89353 +       { GLAMO_REG_CLOCK_HOST,         0x000d },
89354 +       /*
89355 +        * b7..b4 = 0 = no wait states on read or write
89356 +        * b0 = 1 select PLL2 for Host interface, b1 = enable it
89357 +        */
89358 +       { 0x200,        0x0e03 },
89359 +       { 0x202,        0x07ff },
89360 +       { 0x212,        0x0000 },
89361 +       { 0x214,        0x4000 },
89362 +       { 0x216,        0xf00e },
89363 +
89364 +       /* S-Media recommended "set tiling mode to 512 mode for memory access
89365 +        * more efficiency when 640x480" */
89366 +       { GLAMO_REG_MEM_TYPE,           0x0c74 }, /* 8MB, 16 word pg wr+rd */
89367 +       { GLAMO_REG_MEM_GEN,            0xafaf }, /* 63 grants min + max */
89368 +
89369 +       { GLAMO_REGOFS_HOSTBUS + 2,     0xffff }, /* enable  on MMIO*/
89370 +
89371 +       { GLAMO_REG_MEM_TIMING1,        0x0108 },
89372 +       { GLAMO_REG_MEM_TIMING2,        0x0010 }, /* Taa = 3 MCLK */
89373 +       { GLAMO_REG_MEM_TIMING3,        0x0000 },
89374 +       { GLAMO_REG_MEM_TIMING4,        0x0000 }, /* CE1# delay fall/rise */
89375 +       { GLAMO_REG_MEM_TIMING5,        0x0000 }, /* UB# LB# */
89376 +       { GLAMO_REG_MEM_TIMING6,        0x0000 }, /* OE# */
89377 +       { GLAMO_REG_MEM_TIMING7,        0x0000 }, /* WE# */
89378 +       { GLAMO_REG_MEM_TIMING8,        0x1002 }, /* MCLK delay, was 0x1000 */
89379 +       { GLAMO_REG_MEM_TIMING9,        0x6006 },
89380 +       { GLAMO_REG_MEM_TIMING10,       0x00ff },
89381 +       { GLAMO_REG_MEM_TIMING11,       0x0001 },
89382 +       { GLAMO_REG_MEM_POWER1,         0x0020 },
89383 +       { GLAMO_REG_MEM_POWER2,         0x0000 },
89384 +       { GLAMO_REG_MEM_DRAM1,          0x0000 },
89385 +               { 0xfffe, 1 },
89386 +       { GLAMO_REG_MEM_DRAM1,          0xc100 },
89387 +               { 0xfffe, 1 },
89388 +       { GLAMO_REG_MEM_DRAM1,          0xe100 },
89389 +       { GLAMO_REG_MEM_DRAM2,          0x01d6 },
89390 +       { GLAMO_REG_CLOCK_MEMORY,       0x000b },
89391 +       { GLAMO_REG_GPIO_GEN1,          0x000f },
89392 +       { GLAMO_REG_GPIO_GEN2,          0x111e },
89393 +       { GLAMO_REG_GPIO_GEN3,          0xccc3 },
89394 +       { GLAMO_REG_GPIO_GEN4,          0x111e },
89395 +       { GLAMO_REG_GPIO_GEN5,          0x000f },
89396 +};
89397 +#if 0
89398 +static struct glamo_script glamo_resume_script[] = {
89399 +
89400 +       { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
89401 +       { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
89402 +       { GLAMO_REG_DFT_GEN6, 1 },
89403 +               { 0xfffe, 100 },
89404 +               { 0xfffd, 0 },
89405 +       { 0x200,        0x0e03 },
89406 +
89407 +       /*
89408 +        * b9 of this register MUST be zero to get any interrupts on INT#
89409 +        * the other set bits enable all the engine interrupt sources
89410 +        */
89411 +       { GLAMO_REG_IRQ_ENABLE,         0x01ff },
89412 +       { GLAMO_REG_CLOCK_HOST,         0x0018 },
89413 +       { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
89414 +
89415 +       { GLAMO_REG_MEM_DRAM1,          0x0000 },
89416 +               { 0xfffe, 1 },
89417 +       { GLAMO_REG_MEM_DRAM1,          0xc100 },
89418 +               { 0xfffe, 1 },
89419 +       { GLAMO_REG_MEM_DRAM1,          0xe100 },
89420 +       { GLAMO_REG_MEM_DRAM2,          0x01d6 },
89421 +       { GLAMO_REG_CLOCK_MEMORY,       0x000b },
89422 +};
89423 +#endif
89424 +
89425 +enum glamo_power {
89426 +       GLAMO_POWER_ON,
89427 +       GLAMO_POWER_SUSPEND,
89428 +};
89429 +
89430 +static void glamo_power(struct glamo_core *glamo,
89431 +                       enum glamo_power new_state)
89432 +{
89433 +       int n;
89434 +       unsigned long flags;
89435 +
89436 +       spin_lock_irqsave(&glamo->lock, flags);
89437 +
89438 +       dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
89439 +
89440 +       /*
89441 +Power management
89442 +static const REG_VALUE_MASK_TYPE reg_powerOn[] =
89443 +{
89444 +    { REG_GEN_DFT6,     REG_BIT_ALL,    REG_DATA(1u << 0)           },
89445 +    { REG_GEN_PLL3,     0u,             REG_DATA(1u << 13)          },
89446 +    { REG_GEN_MEM_CLK,  REG_BIT_ALL,    REG_BIT_EN_MOCACLK          },
89447 +    { REG_MEM_DRAM2,    0u,             REG_BIT_EN_DEEP_POWER_DOWN  },
89448 +    { REG_MEM_DRAM1,    0u,             REG_BIT_SELF_REFRESH        }
89449 +};
89450 +
89451 +static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
89452 +{
89453 +    { REG_MEM_DRAM1,    REG_BIT_ALL,    REG_BIT_SELF_REFRESH    },
89454 +    { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK      },
89455 +    { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)      },
89456 +    { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)       }
89457 +};
89458 +
89459 +static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
89460 +{
89461 +    { REG_MEM_DRAM2,    REG_BIT_ALL,    REG_BIT_EN_DEEP_POWER_DOWN  },
89462 +    { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK          },
89463 +    { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)          },
89464 +    { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)           }
89465 +};
89466 +*/
89467 +
89468 +       switch (new_state) {
89469 +       case GLAMO_POWER_ON:
89470 +
89471 +               /*
89472 +                * glamo state on resume is nondeterministic in some
89473 +                * fundamental way, it has also been observed that the
89474 +                * Glamo reset pin can get asserted by, eg, touching it with
89475 +                * a scope probe.  So the only answer is to roll with it and
89476 +                * force an external reset on the Glamo during resume.
89477 +                */
89478 +
89479 +               (glamo->pdata->glamo_external_reset)(0);
89480 +               udelay(10);
89481 +               (glamo->pdata->glamo_external_reset)(1);
89482 +               mdelay(5);
89483 +
89484 +               glamo_run_script(glamo, glamo_init_script,
89485 +                        ARRAY_SIZE(glamo_init_script), 0);
89486 +
89487 +               break;
89488 +
89489 +       case GLAMO_POWER_SUSPEND:
89490 +
89491 +               /* nuke interrupts */
89492 +               __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
89493 +
89494 +               /* stash a copy of which engines were running */
89495 +               glamo->engine_enabled_bitfield_suspend =
89496 +                                                glamo->engine_enabled_bitfield;
89497 +
89498 +               /* take down each engine before we kill mem and pll */
89499 +               for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
89500 +                       if (glamo->engine_enabled_bitfield & (1 << n))
89501 +                               __glamo_engine_disable(glamo, n);
89502 +
89503 +               /* enable self-refresh */
89504 +
89505 +               __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
89506 +                                       GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
89507 +                                       GLAMO_MEM_DRAM1_EN_GATE_CKE |
89508 +                                       GLAMO_MEM_DRAM1_SELF_REFRESH |
89509 +                                       GLAMO_MEM_REFRESH_COUNT);
89510 +               __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
89511 +                                       GLAMO_MEM_DRAM1_EN_MODEREG_SET |
89512 +                                       GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
89513 +                                       GLAMO_MEM_DRAM1_EN_GATE_CKE |
89514 +                                       GLAMO_MEM_DRAM1_SELF_REFRESH |
89515 +                                       GLAMO_MEM_REFRESH_COUNT);
89516 +
89517 +               /* force RAM into deep powerdown */
89518 +
89519 +               __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
89520 +                                       GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
89521 +                                       (7 << 6) | /* tRC */
89522 +                                       (1 << 4) | /* tRP */
89523 +                                       (1 << 2) | /* tRCD */
89524 +                                       2); /* CAS latency */
89525 +
89526 +               /* disable clocks to memory */
89527 +               __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
89528 +
89529 +               /* all dividers from OSCI */
89530 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
89531 +
89532 +               /* PLL2 into bypass */
89533 +               __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
89534 +
89535 +               __reg_write(glamo, 0x200, 0x0e00);
89536 +
89537 +
89538 +               /* kill PLLS 1 then 2 */
89539 +               __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
89540 +               __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
89541 +
89542 +               break;
89543 +       }
89544 +
89545 +       spin_unlock_irqrestore(&glamo->lock, flags);
89546 +}
89547 +
89548 +#if 0
89549 +#define MEMDETECT_RETRY        6
89550 +static unsigned int detect_memsize(struct glamo_core *glamo)
89551 +{
89552 +       int i;
89553 +
89554 +       /*static const u_int16_t pattern[] = {
89555 +               0x1111, 0x8a8a, 0x2222, 0x7a7a,
89556 +               0x3333, 0x6a6a, 0x4444, 0x5a5a,
89557 +               0x5555, 0x4a4a, 0x6666, 0x3a3a,
89558 +               0x7777, 0x2a2a, 0x8888, 0x1a1a
89559 +       }; */
89560 +
89561 +       for (i = 0; i < MEMDETECT_RETRY; i++) {
89562 +               switch (glamo->type) {
89563 +               case 3600:
89564 +                       __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
89565 +                       __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
89566 +                       break;
89567 +               case 3650:
89568 +                       switch (glamo->revision) {
89569 +                       case GLAMO_CORE_REV_A0:
89570 +                               if (i & 1)
89571 +                                       __reg_write(glamo, GLAMO_REG_MEM_TYPE,
89572 +                                                   0x097a);
89573 +                               else
89574 +                                       __reg_write(glamo, GLAMO_REG_MEM_TYPE,
89575 +                                                   0x0173);
89576 +
89577 +                               __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
89578 +                               msleep(1);
89579 +                               __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
89580 +                               break;
89581 +                       default:
89582 +                               if (i & 1)
89583 +                                       __reg_write(glamo, GLAMO_REG_MEM_TYPE,
89584 +                                                   0x0972);
89585 +                               else
89586 +                                       __reg_write(glamo, GLAMO_REG_MEM_TYPE,
89587 +                                                   0x0872);
89588 +
89589 +                               __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
89590 +                               msleep(1);
89591 +                               __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
89592 +                               break;
89593 +                       }
89594 +                       break;
89595 +               case 3700:
89596 +                       /* FIXME */
89597 +               default:
89598 +                       break;
89599 +               }
89600 +
89601 +#if 0
89602 +               /* FIXME: finish implementation */
89603 +               for (j = 0; j < 8; j++) {
89604 +                       __
89605 +#endif
89606 +       }
89607 +
89608 +       return 0;
89609 +}
89610 +#endif
89611 +
89612 +/* Find out if we can support this version of the Glamo chip */
89613 +static int glamo_supported(struct glamo_core *glamo)
89614 +{
89615 +       u_int16_t dev_id, rev_id; /*, memsize; */
89616 +
89617 +       dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
89618 +       rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
89619 +
89620 +       switch (dev_id) {
89621 +       case 0x3650:
89622 +               switch (rev_id) {
89623 +               case GLAMO_CORE_REV_A2:
89624 +                       break;
89625 +               case GLAMO_CORE_REV_A0:
89626 +               case GLAMO_CORE_REV_A1:
89627 +               case GLAMO_CORE_REV_A3:
89628 +                       dev_warn(&glamo->pdev->dev, "untested core revision "
89629 +                                "%04x, your mileage may vary\n", rev_id);
89630 +                       break;
89631 +               default:
89632 +                       dev_warn(&glamo->pdev->dev, "unknown glamo revision "
89633 +                                "%04x, your mileage may vary\n", rev_id);
89634 +                       /* maybe should abort ? */
89635 +               }
89636 +               break;
89637 +       case 0x3600:
89638 +       case 0x3700:
89639 +       default:
89640 +               dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
89641 +                       dev_id);
89642 +               return 0;
89643 +       }
89644 +
89645 +       dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
89646 +                "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
89647 +                glamo_pll_rate(glamo, GLAMO_PLL1),
89648 +                glamo_pll_rate(glamo, GLAMO_PLL2));
89649 +
89650 +       return 1;
89651 +}
89652 +
89653 +static int __init glamo_probe(struct platform_device *pdev)
89654 +{
89655 +       int rc = 0, irq;
89656 +       struct glamo_core *glamo;
89657 +       struct platform_device *glamo_mmc_dev;
89658 +
89659 +       if (glamo_handle) {
89660 +               dev_err(&pdev->dev,
89661 +                       "This driver supports only one instance\n");
89662 +               return -EBUSY;
89663 +       }
89664 +
89665 +       glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
89666 +       if (!glamo)
89667 +               return -ENOMEM;
89668 +
89669 +       spin_lock_init(&glamo->lock);
89670 +       glamo_handle = glamo;
89671 +       glamo->pdev = pdev;
89672 +       glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
89673 +       glamo->irq = platform_get_irq(pdev, 0);
89674 +       glamo->pdata = pdev->dev.platform_data;
89675 +       if (!glamo->mem || !glamo->pdata) {
89676 +               dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
89677 +               rc = -ENOENT;
89678 +               goto bail_free;
89679 +       }
89680 +
89681 +       /* register a number of sibling devices whoise IOMEM resources
89682 +        * are siblings of pdev's IOMEM resource */
89683 +#if 0
89684 +       glamo_core_dev.dev.parent = &pdev.dev;
89685 +       mangle_mem_resources(glamo_core_dev.resources,
89686 +                            glamo_core_dev.num_resources, glamo->mem);
89687 +       glamo_core_dev.resources[1].start = glamo->irq;
89688 +       glamo_core_dev.resources[1].end = glamo->irq;
89689 +       platform_device_register(&glamo_core_dev);
89690 +#endif
89691 +       /* only remap the generic, hostbus and memory controller registers */
89692 +       glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
89693 +       if (!glamo->base) {
89694 +               dev_err(&pdev->dev, "failed to ioremap() memory region\n");
89695 +               goto bail_free;
89696 +       }
89697 +
89698 +       platform_set_drvdata(pdev, glamo);
89699 +
89700 +       (glamo->pdata->glamo_external_reset)(0);
89701 +       udelay(10);
89702 +       (glamo->pdata->glamo_external_reset)(1);
89703 +       mdelay(10);
89704 +
89705 +       /*
89706 +        * finally set the mfd interrupts up
89707 +        * can't do them earlier or sibling probes blow up
89708 +        */
89709 +
89710 +       for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
89711 +               set_irq_chip(irq, &glamo_irq_chip);
89712 +               set_irq_handler(irq, handle_level_irq);
89713 +               set_irq_flags(irq, IRQF_VALID);
89714 +       }
89715 +
89716 +       if (glamo->pdata->glamo_irq_is_wired &&
89717 +           !glamo->pdata->glamo_irq_is_wired()) {
89718 +               set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
89719 +               set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
89720 +               dev_info(&pdev->dev, "Glamo interrupt registered\n");
89721 +               glamo->irq_works = 1;
89722 +       } else {
89723 +               dev_err(&pdev->dev, "Glamo interrupt not used\n");
89724 +               glamo->irq_works = 0;
89725 +       }
89726 +
89727 +
89728 +       /* confirm it isn't insane version */
89729 +       if (!glamo_supported(glamo)) {
89730 +               dev_err(&pdev->dev, "This Glamo is not supported\n");
89731 +               goto bail_irq;
89732 +       }
89733 +
89734 +       /* sysfs */
89735 +       rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
89736 +       if (rc < 0) {
89737 +               dev_err(&pdev->dev, "cannot create sysfs group\n");
89738 +               goto bail_irq;
89739 +       }
89740 +
89741 +       /* init the chip with canned register set */
89742 +
89743 +       dev_dbg(&glamo->pdev->dev, "running init script\n");
89744 +       glamo_run_script(glamo, glamo_init_script,
89745 +                        ARRAY_SIZE(glamo_init_script), 1);
89746 +
89747 +       dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
89748 +                glamo_pll_rate(glamo, GLAMO_PLL1),
89749 +                glamo_pll_rate(glamo, GLAMO_PLL2));
89750 +
89751 +       /* bring MCI specific stuff over from our MFD platform data */
89752 +       glamo_mci_def_pdata.glamo_can_set_mci_power =
89753 +                                       glamo->pdata->glamo_can_set_mci_power;
89754 +       glamo_mci_def_pdata.glamo_mci_use_slow =
89755 +                                       glamo->pdata->glamo_mci_use_slow;
89756 +       glamo_mci_def_pdata.glamo_irq_is_wired =
89757 +                                       glamo->pdata->glamo_irq_is_wired;
89758 +
89759 +       /* start creating the siblings */
89760 +
89761 +       glamo_2d_dev.dev.parent = &pdev->dev;
89762 +       mangle_mem_resources(glamo_2d_dev.resource,
89763 +                            glamo_2d_dev.num_resources, glamo->mem);
89764 +       platform_device_register(&glamo_2d_dev);
89765 +
89766 +       glamo_3d_dev.dev.parent = &pdev->dev;
89767 +       mangle_mem_resources(glamo_3d_dev.resource,
89768 +                            glamo_3d_dev.num_resources, glamo->mem);
89769 +       platform_device_register(&glamo_3d_dev);
89770 +
89771 +       glamo_jpeg_dev.dev.parent = &pdev->dev;
89772 +       mangle_mem_resources(glamo_jpeg_dev.resource,
89773 +                            glamo_jpeg_dev.num_resources, glamo->mem);
89774 +       platform_device_register(&glamo_jpeg_dev);
89775 +
89776 +       glamo_mpeg_dev.dev.parent = &pdev->dev;
89777 +       mangle_mem_resources(glamo_mpeg_dev.resource,
89778 +                            glamo_mpeg_dev.num_resources, glamo->mem);
89779 +       platform_device_register(&glamo_mpeg_dev);
89780 +
89781 +       glamo->pdata->glamo = glamo;
89782 +       glamo_fb_dev.dev.parent = &pdev->dev;
89783 +       glamo_fb_dev.dev.platform_data = glamo->pdata;
89784 +       mangle_mem_resources(glamo_fb_dev.resource,
89785 +                            glamo_fb_dev.num_resources, glamo->mem);
89786 +       platform_device_register(&glamo_fb_dev);
89787 +
89788 +       glamo->pdata->spigpio_info->glamo = glamo;
89789 +       glamo_spigpio_dev.dev.parent = &pdev->dev;
89790 +       glamo_spigpio_dev.dev.platform_data = glamo->pdata->spigpio_info;
89791 +       platform_device_register(&glamo_spigpio_dev);
89792 +
89793 +       glamo_mmc_dev = glamo->pdata->mmc_dev;
89794 +       glamo_mmc_dev->name = "glamo-mci";
89795 +       glamo_mmc_dev->dev.parent = &pdev->dev;
89796 +       glamo_mmc_dev->resource = glamo_mmc_resources;
89797 +       glamo_mmc_dev->num_resources = ARRAY_SIZE(glamo_mmc_resources);
89798 +
89799 +       /* we need it later to give to the engine enable and disable */
89800 +       glamo_mci_def_pdata.pglamo = glamo;
89801 +       mangle_mem_resources(glamo_mmc_dev->resource,
89802 +                            glamo_mmc_dev->num_resources, glamo->mem);
89803 +       platform_device_register(glamo_mmc_dev);
89804 +
89805 +       /* only request the generic, hostbus and memory controller MMIO */
89806 +       glamo->mem = request_mem_region(glamo->mem->start,
89807 +                                       GLAMO_REGOFS_VIDCAP, "glamo-core");
89808 +       if (!glamo->mem) {
89809 +               dev_err(&pdev->dev, "failed to request memory region\n");
89810 +               goto bail_irq;
89811 +       }
89812 +
89813 +       return 0;
89814 +
89815 +bail_irq:
89816 +       disable_irq(glamo->irq);
89817 +       set_irq_chained_handler(glamo->irq, NULL);
89818 +
89819 +       for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
89820 +               set_irq_flags(irq, 0);
89821 +               set_irq_chip(irq, NULL);
89822 +       }
89823 +
89824 +       iounmap(glamo->base);
89825 +bail_free:
89826 +       platform_set_drvdata(pdev, NULL);
89827 +       glamo_handle = NULL;
89828 +       kfree(glamo);
89829 +
89830 +       return rc;
89831 +}
89832 +
89833 +static int glamo_remove(struct platform_device *pdev)
89834 +{
89835 +       struct glamo_core *glamo = platform_get_drvdata(pdev);
89836 +       int irq;
89837 +
89838 +       disable_irq(glamo->irq);
89839 +       set_irq_chained_handler(glamo->irq, NULL);
89840 +
89841 +       for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
89842 +               set_irq_flags(irq, 0);
89843 +               set_irq_chip(irq, NULL);
89844 +       }
89845 +
89846 +       platform_set_drvdata(pdev, NULL);
89847 +       platform_device_unregister(&glamo_fb_dev);
89848 +       platform_device_unregister(glamo->pdata->mmc_dev);
89849 +       iounmap(glamo->base);
89850 +       release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
89851 +       glamo_handle = NULL;
89852 +       kfree(glamo);
89853 +
89854 +       return 0;
89855 +}
89856 +
89857 +#ifdef CONFIG_PM
89858 +
89859 +static int glamo_suspend(struct platform_device *pdev, pm_message_t state)
89860 +{
89861 +       glamo_handle->suspending = 1;
89862 +       glamo_power(glamo_handle, GLAMO_POWER_SUSPEND);
89863 +
89864 +       return 0;
89865 +}
89866 +
89867 +static int glamo_resume(struct platform_device *pdev)
89868 +{
89869 +       glamo_power(glamo_handle, GLAMO_POWER_ON);
89870 +       glamo_handle->suspending = 0;
89871 +
89872 +       return 0;
89873 +}
89874 +
89875 +#else
89876 +#define glamo_suspend NULL
89877 +#define glamo_resume  NULL
89878 +#endif
89879 +
89880 +static struct platform_driver glamo_driver = {
89881 +       .probe          = glamo_probe,
89882 +       .remove         = glamo_remove,
89883 +       .suspend        = glamo_suspend,
89884 +       .resume = glamo_resume,
89885 +       .driver         = {
89886 +               .name   = "glamo3362",
89887 +               .owner  = THIS_MODULE,
89888 +       },
89889 +};
89890 +
89891 +static int __devinit glamo_init(void)
89892 +{
89893 +       return platform_driver_register(&glamo_driver);
89894 +}
89895 +
89896 +static void __exit glamo_cleanup(void)
89897 +{
89898 +       platform_driver_unregister(&glamo_driver);
89899 +}
89900 +
89901 +module_init(glamo_init);
89902 +module_exit(glamo_cleanup);
89903 +
89904 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
89905 +MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
89906 +MODULE_LICENSE("GPL");
89907 --- /dev/null
89908 +++ b/drivers/mfd/glamo/glamo-core.h
89909 @@ -0,0 +1,92 @@
89910 +#ifndef __GLAMO_CORE_H
89911 +#define __GLAMO_CORE_H
89912 +
89913 +#include <asm/system.h>
89914 +
89915 +/* for the time being, we put the on-screen framebuffer into the lowest
89916 + * VRAM space.  This should make the code easily compatible with the various
89917 + * 2MB/4MB/8MB variants of the Smedia chips */
89918 +#define GLAMO_OFFSET_VRAM      0x800000
89919 +#define GLAMO_OFFSET_FB        (GLAMO_OFFSET_VRAM)
89920 +
89921 +/* we only allocate the minimum possible size for the framebuffer to make
89922 + * sure we have sufficient memory for other functions of the chip */
89923 +//#define GLAMO_FB_SIZE        (640*480*4)     /* == 0x12c000 */
89924 +#define GLAMO_INTERNAL_RAM_SIZE 0x800000
89925 +#define GLAMO_MMC_BUFFER_SIZE (64 * 1024)
89926 +#define GLAMO_FB_SIZE  (GLAMO_INTERNAL_RAM_SIZE - GLAMO_MMC_BUFFER_SIZE)
89927 +
89928 +struct glamo_core {
89929 +       int irq;
89930 +       int irq_works; /* 0 means PCB does not support Glamo IRQ */
89931 +       struct resource *mem;
89932 +       struct resource *mem_core;
89933 +       void __iomem *base;
89934 +       struct platform_device *pdev;
89935 +       struct glamofb_platform_data *pdata;
89936 +       u_int16_t type;
89937 +       u_int16_t revision;
89938 +       spinlock_t lock;
89939 +       u32 engine_enabled_bitfield;
89940 +       u32 engine_enabled_bitfield_suspend;
89941 +       int suspending;
89942 +};
89943 +
89944 +struct glamo_script {
89945 +       u_int16_t reg;
89946 +       u_int16_t val;
89947 +};
89948 +
89949 +int glamo_run_script(struct glamo_core *glamo,
89950 +                    struct glamo_script *script, int len, int may_sleep);
89951 +
89952 +enum glamo_engine {
89953 +       GLAMO_ENGINE_CAPTURE,
89954 +       GLAMO_ENGINE_ISP,
89955 +       GLAMO_ENGINE_JPEG,
89956 +       GLAMO_ENGINE_MPEG_ENC,
89957 +       GLAMO_ENGINE_MPEG_DEC,
89958 +       GLAMO_ENGINE_LCD,
89959 +       GLAMO_ENGINE_CMDQ,
89960 +       GLAMO_ENGINE_2D,
89961 +       GLAMO_ENGINE_3D,
89962 +       GLAMO_ENGINE_MMC,
89963 +       GLAMO_ENGINE_MICROP0,
89964 +       GLAMO_ENGINE_RISC,
89965 +       GLAMO_ENGINE_MICROP1_MPEG_ENC,
89966 +       GLAMO_ENGINE_MICROP1_MPEG_DEC,
89967 +#if 0
89968 +       GLAMO_ENGINE_H264_DEC,
89969 +       GLAMO_ENGINE_RISC1,
89970 +       GLAMO_ENGINE_SPI,
89971 +#endif
89972 +       __NUM_GLAMO_ENGINES
89973 +};
89974 +
89975 +struct glamo_mci_pdata {
89976 +       struct glamo_core * pglamo;
89977 +       unsigned int    gpio_detect;
89978 +       unsigned int    gpio_wprotect;
89979 +       unsigned long   ocr_avail;
89980 +       int             (*glamo_can_set_mci_power)(void);
89981 +       /* glamo-mci asking if it should use the slow clock to card */
89982 +       int             (*glamo_mci_use_slow)(void);
89983 +       int             (*glamo_irq_is_wired)(void);
89984 +       void            (*mci_suspending)(struct platform_device *dev);
89985 +       int             (*mci_all_dependencies_resumed)(struct platform_device *dev);
89986 +
89987 +};
89988 +
89989 +int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine);
89990 +int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine);
89991 +void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine);
89992 +int glamo_engine_reclock(struct glamo_core *glamo,
89993 +                        enum glamo_engine engine, int ps);
89994 +
89995 +void glamo_engine_clkreg_set(struct glamo_core *glamo,
89996 +                            enum glamo_engine engine,
89997 +                            u_int16_t mask, u_int16_t val);
89998 +
89999 +u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
90000 +                                 enum glamo_engine engine);
90001 +#endif /* __GLAMO_CORE_H */
90002 --- /dev/null
90003 +++ b/drivers/mfd/glamo/glamo-fb.c
90004 @@ -0,0 +1,1048 @@
90005 +/* Smedia Glamo 336x/337x driver
90006 + *
90007 + * (C) 2007-2008 by Openmoko, Inc.
90008 + * Author: Harald Welte <laforge@openmoko.org>
90009 + * All rights reserved.
90010 + *
90011 + * This program is free software; you can redistribute it and/or
90012 + * modify it under the terms of the GNU General Public License as
90013 + * published by the Free Software Foundation; either version 2 of
90014 + * the License, or (at your option) any later version.
90015 + *
90016 + * This program is distributed in the hope that it will be useful,
90017 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
90018 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
90019 + * GNU General Public License for more details.
90020 + *
90021 + * You should have received a copy of the GNU General Public License
90022 + * along with this program; if not, write to the Free Software
90023 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
90024 + * MA 02111-1307 USA
90025 + */
90026 +
90027 +#include <linux/module.h>
90028 +#include <linux/kernel.h>
90029 +#include <linux/errno.h>
90030 +#include <linux/string.h>
90031 +#include <linux/mm.h>
90032 +#include <linux/slab.h>
90033 +#include <linux/delay.h>
90034 +#include <linux/fb.h>
90035 +#include <linux/init.h>
90036 +#include <linux/vmalloc.h>
90037 +#include <linux/dma-mapping.h>
90038 +#include <linux/interrupt.h>
90039 +#include <linux/workqueue.h>
90040 +#include <linux/wait.h>
90041 +#include <linux/platform_device.h>
90042 +#include <linux/clk.h>
90043 +#include <linux/spinlock.h>
90044 +
90045 +#include <asm/io.h>
90046 +#include <asm/uaccess.h>
90047 +#include <asm/div64.h>
90048 +
90049 +#ifdef CONFIG_PM
90050 +#include <linux/pm.h>
90051 +#endif
90052 +
90053 +#include <linux/glamofb.h>
90054 +
90055 +#include "glamo-regs.h"
90056 +#include "glamo-core.h"
90057 +
90058 +#ifndef DEBUG
90059 +#define GLAMO_LOG(...)
90060 +#else
90061 +#define GLAMO_LOG(...) \
90062 +do { \
90063 +       printk(KERN_DEBUG "in %s:%s:%d", __FILE__, __func__, __LINE__); \
90064 +       printk(KERN_DEBUG __VA_ARGS__); \
90065 +} while (0);
90066 +#endif
90067 +
90068 +
90069 +#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
90070 +
90071 +struct glamofb_handle {
90072 +       struct fb_info *fb;
90073 +       struct device *dev;
90074 +       struct resource *reg;
90075 +       struct resource *fb_res;
90076 +       char __iomem *base;
90077 +       struct glamofb_platform_data *mach_info;
90078 +       char __iomem *cursor_addr;
90079 +       int cursor_on;
90080 +       u_int32_t pseudo_pal[16];
90081 +       spinlock_t lock_cmd;
90082 +};
90083 +
90084 +/* 'sibling' spi device for lcm init */
90085 +static struct platform_device glamo_spi_dev = {
90086 +       .name           = "glamo-lcm-spi",
90087 +};
90088 +
90089 +
90090 +static int reg_read(struct glamofb_handle *glamo,
90091 +                          u_int16_t reg)
90092 +{
90093 +       return readw(glamo->base + reg);
90094 +}
90095 +
90096 +static void reg_write(struct glamofb_handle *glamo,
90097 +                            u_int16_t reg, u_int16_t val)
90098 +{
90099 +       writew(val, glamo->base + reg);
90100 +}
90101 +
90102 +static struct glamo_script glamo_regs[] = {
90103 +       { GLAMO_REG_LCD_MODE1, 0x0020 },
90104 +       /* no display rotation, no hardware cursor, no dither, no gamma,
90105 +        * no retrace flip, vsync low-active, hsync low active,
90106 +        * no TVCLK, no partial display, hw dest color from fb,
90107 +        * no partial display mode, LCD1, software flip,  */
90108 +       { GLAMO_REG_LCD_MODE2, 0x9020 },
90109 +         /* video flip, no ptr, no ptr, dhclk off,
90110 +          * normal mode,  no cpuif,
90111 +          * res, serial msb first, single fb, no fr ctrl,
90112 +          * cpu if bits all zero, no crc
90113 +          * 0000 0000 0010  0000 */
90114 +       { GLAMO_REG_LCD_MODE3, 0x0b40 },
90115 +         /* src data rgb565, res, 18bit rgb666
90116 +          * 000 01 011 0100 0000 */
90117 +       { GLAMO_REG_LCD_POLARITY, 0x440c },
90118 +         /* DE high active, no cpu/lcd if, cs0 force low, a0 low active,
90119 +          * np cpu if, 9bit serial data, sclk rising edge latch data
90120 +          * 01 00 0 100 0 000 01 0 0 */
90121 +       /* The following values assume 640*480@16bpp */
90122 +       { GLAMO_REG_LCD_A_BASE1, 0x0000 }, /* display A base address 15:0 */
90123 +       { GLAMO_REG_LCD_A_BASE2, 0x0000 }, /* display A base address 22:16 */
90124 +       { GLAMO_REG_LCD_B_BASE1, 0x6000 }, /* display B base address 15:0 */
90125 +       { GLAMO_REG_LCD_B_BASE2, 0x0009 }, /* display B base address 22:16 */
90126 +       { GLAMO_REG_LCD_CURSOR_BASE1, 0xC000 }, /* cursor base address 15:0 */
90127 +       { GLAMO_REG_LCD_CURSOR_BASE2, 0x0012 }, /* cursor base address 22:16 */
90128 +       { GLAMO_REG_LCD_COMMAND2, 0x0000 }, /* display page A */
90129 +};
90130 +
90131 +static int glamofb_run_script(struct glamofb_handle *glamo,
90132 +                               struct glamo_script *script, int len)
90133 +{
90134 +       int i;
90135 +
90136 +       if (glamo->mach_info->glamo->suspending) {
90137 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_run_script while "
90138 +                                                                "suspended\n");
90139 +               return -EBUSY;
90140 +       }
90141 +
90142 +       for (i = 0; i < len; i++) {
90143 +               struct glamo_script *line = &script[i];
90144 +
90145 +               if (line->reg == 0xffff)
90146 +                       return 0;
90147 +               else if (line->reg == 0xfffe)
90148 +                       msleep(line->val);
90149 +               else
90150 +                       reg_write(glamo, script[i].reg, script[i].val);
90151 +       }
90152 +
90153 +       return 0;
90154 +}
90155 +
90156 +static int glamofb_check_var(struct fb_var_screeninfo *var,
90157 +                            struct fb_info *info)
90158 +{
90159 +       struct glamofb_handle *glamo = info->par;
90160 +
90161 +       if (glamo->mach_info->glamo->suspending) {
90162 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_check_var while "
90163 +                                                                "suspended\n");
90164 +               return -EBUSY;
90165 +       }
90166 +
90167 +       if (var->yres > glamo->mach_info->yres.max)
90168 +               var->yres = glamo->mach_info->yres.max;
90169 +       else if (var->yres < glamo->mach_info->yres.min)
90170 +               var->yres = glamo->mach_info->yres.min;
90171 +
90172 +       if (var->xres > glamo->mach_info->xres.max)
90173 +               var->xres = glamo->mach_info->xres.max;
90174 +       else if (var->xres < glamo->mach_info->xres.min)
90175 +               var->xres = glamo->mach_info->xres.min;
90176 +
90177 +       if (var->bits_per_pixel > glamo->mach_info->bpp.max)
90178 +               var->bits_per_pixel = glamo->mach_info->bpp.max;
90179 +       else if (var->bits_per_pixel < glamo->mach_info->bpp.min)
90180 +               var->bits_per_pixel = glamo->mach_info->bpp.min;
90181 +
90182 +       /* FIXME: set rgb positions */
90183 +       switch (var->bits_per_pixel) {
90184 +       case 16:
90185 +               switch (reg_read(glamo, GLAMO_REG_LCD_MODE3) & 0xc000) {
90186 +               case GLAMO_LCD_SRC_RGB565:
90187 +                       var->red.offset         = 11;
90188 +                       var->green.offset       = 5;
90189 +                       var->blue.offset        = 0;
90190 +                       var->red.length         = 5;
90191 +                       var->green.length       = 6;
90192 +                       var->blue.length        = 5;
90193 +                       var->transp.length      = 0;
90194 +                       break;
90195 +               case GLAMO_LCD_SRC_ARGB1555:
90196 +                       var->transp.offset      = 15;
90197 +                       var->red.offset         = 10;
90198 +                       var->green.offset       = 5;
90199 +                       var->blue.offset        = 0;
90200 +                       var->transp.length      = 1;
90201 +                       var->red.length         = 5;
90202 +                       var->green.length       = 5;
90203 +                       var->blue.length        = 5;
90204 +                       break;
90205 +               case GLAMO_LCD_SRC_ARGB4444:
90206 +                       var->transp.offset      = 12;
90207 +                       var->red.offset         = 8;
90208 +                       var->green.offset       = 4;
90209 +                       var->blue.offset        = 0;
90210 +                       var->transp.length      = 4;
90211 +                       var->red.length         = 4;
90212 +                       var->green.length       = 4;
90213 +                       var->blue.length        = 4;
90214 +                       break;
90215 +               }
90216 +               break;
90217 +       case 24:
90218 +       case 32:
90219 +       default:
90220 +               /* The Smedia Glamo doesn't support anything but 16bit color */
90221 +               printk(KERN_ERR
90222 +                      "Smedia driver does not [yet?] support 24/32bpp\n");
90223 +               return -EINVAL;
90224 +       }
90225 +
90226 +       return 0;
90227 +}
90228 +
90229 +static void reg_set_bit_mask(struct glamofb_handle *glamo,
90230 +                            u_int16_t reg, u_int16_t mask,
90231 +                            u_int16_t val)
90232 +{
90233 +       u_int16_t tmp;
90234 +
90235 +       val &= mask;
90236 +
90237 +       tmp = reg_read(glamo, reg);
90238 +       tmp &= ~mask;
90239 +       tmp |= val;
90240 +       reg_write(glamo, reg, tmp);
90241 +}
90242 +
90243 +#define GLAMO_LCD_WIDTH_MASK 0x03FF
90244 +#define GLAMO_LCD_HEIGHT_MASK 0x03FF
90245 +#define GLAMO_LCD_PITCH_MASK 0x07FE
90246 +#define GLAMO_LCD_HV_TOTAL_MASK 0x03FF
90247 +#define GLAMO_LCD_HV_RETR_START_MASK 0x03FF
90248 +#define GLAMO_LCD_HV_RETR_END_MASK 0x03FF
90249 +#define GLAMO_LCD_HV_RETR_DISP_START_MASK 0x03FF
90250 +#define GLAMO_LCD_HV_RETR_DISP_END_MASK 0x03FF
90251 +
90252 +enum orientation {
90253 +    ORIENTATION_PORTRAIT,
90254 +    ORIENTATION_LANDSCAPE
90255 +};
90256 +
90257 +
90258 +/* the caller has to enxure lock_cmd is held and we are in cmd mode */
90259 +static void __rotate_lcd(struct glamofb_handle *glamo, __u32 rotation)
90260 +{
90261 +       int glamo_rot;
90262 +
90263 +       if (glamo->mach_info->glamo->suspending) {
90264 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING rotate_lcd while "
90265 +                                                                "suspended\n");
90266 +               return;
90267 +       }
90268 +
90269 +       switch (rotation) {
90270 +               case FB_ROTATE_UR:
90271 +                       glamo_rot = GLAMO_LCD_ROT_MODE_0;
90272 +                       break;
90273 +               case FB_ROTATE_CW:
90274 +                       glamo_rot = GLAMO_LCD_ROT_MODE_90;
90275 +                       break;
90276 +               case FB_ROTATE_UD:
90277 +                       glamo_rot = GLAMO_LCD_ROT_MODE_180;
90278 +                       break;
90279 +               case FB_ROTATE_CCW:
90280 +                       glamo_rot = GLAMO_LCD_ROT_MODE_270;
90281 +                       break;
90282 +               default:
90283 +                       glamo_rot = GLAMO_LCD_ROT_MODE_0;
90284 +                       break;
90285 +       }
90286 +
90287 +       reg_set_bit_mask(glamo,
90288 +                        GLAMO_REG_LCD_WIDTH,
90289 +                        GLAMO_LCD_ROT_MODE_MASK,
90290 +                        glamo_rot);
90291 +       reg_set_bit_mask(glamo,
90292 +                        GLAMO_REG_LCD_MODE1,
90293 +                        GLAMO_LCD_MODE1_ROTATE_EN,
90294 +                        (glamo_rot != GLAMO_LCD_ROT_MODE_0)?
90295 +                                GLAMO_LCD_MODE1_ROTATE_EN : 0);
90296 +}
90297 +
90298 +static enum orientation get_orientation(struct fb_var_screeninfo *var)
90299 +{
90300 +       if (var->xres <= var->yres)
90301 +               return ORIENTATION_PORTRAIT;
90302 +
90303 +       return ORIENTATION_LANDSCAPE;
90304 +}
90305 +
90306 +static int will_orientation_change(struct fb_var_screeninfo *var)
90307 +{
90308 +       enum orientation orient = get_orientation(var);
90309 +
90310 +       switch (orient) {
90311 +               case ORIENTATION_LANDSCAPE:
90312 +                       if (var->rotate == FB_ROTATE_UR ||
90313 +                           var->rotate == FB_ROTATE_UD)
90314 +                               return 1;
90315 +                       break;
90316 +               case ORIENTATION_PORTRAIT:
90317 +                       if (var->rotate == FB_ROTATE_CW ||
90318 +                           var->rotate == FB_ROTATE_CCW)
90319 +                               return 1;
90320 +                       break;
90321 +       }
90322 +       return 0;
90323 +}
90324 +
90325 +static void glamofb_update_lcd_controller(struct glamofb_handle *glamo,
90326 +                                         struct fb_var_screeninfo *var)
90327 +{
90328 +       int sync, bp, disp, fp, total, xres, yres, pitch, orientation_changing;
90329 +       unsigned long flags;
90330 +
90331 +       if (!glamo || !var)
90332 +               return;
90333 +
90334 +       if (glamo->mach_info->glamo->suspending) {
90335 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_update_lcd_controller while "
90336 +                                                                "suspended\n");
90337 +               return;
90338 +       }
90339 +
90340 +       dev_dbg(&glamo->mach_info->glamo->pdev->dev,
90341 +                         "glamofb_update_lcd_controller spin_lock_irqsave\n");
90342 +       spin_lock_irqsave(&glamo->lock_cmd, flags);
90343 +
90344 +       if (glamofb_cmd_mode(glamo, 1))
90345 +               goto out_unlock;
90346 +
90347 +       if (var->pixclock)
90348 +               glamo_engine_reclock(glamo->mach_info->glamo,
90349 +                                    GLAMO_ENGINE_LCD,
90350 +                                    var->pixclock);
90351 +
90352 +       xres = var->xres;
90353 +       yres = var->yres;
90354 +
90355 +       /* figure out if orientation is going to change */
90356 +       orientation_changing = will_orientation_change(var);
90357 +
90358 +       /* adjust the pitch according to new orientation to come */
90359 +
90360 +       if (orientation_changing) {
90361 +               pitch = var->yres * var->bits_per_pixel / 8;
90362 +        } else {
90363 +               pitch = var->xres * var->bits_per_pixel / 8;
90364 +        }
90365 +
90366 +       /*
90367 +        * set the desired LCD geometry
90368 +        */
90369 +       reg_set_bit_mask(glamo,
90370 +                        GLAMO_REG_LCD_WIDTH,
90371 +                        GLAMO_LCD_WIDTH_MASK,
90372 +                        xres);
90373 +       reg_set_bit_mask(glamo,
90374 +                        GLAMO_REG_LCD_HEIGHT,
90375 +                        GLAMO_LCD_HEIGHT_MASK,
90376 +                        yres);
90377 +       reg_set_bit_mask(glamo,
90378 +                        GLAMO_REG_LCD_PITCH,
90379 +                        GLAMO_LCD_PITCH_MASK,
90380 +                        pitch);
90381 +
90382 +       /* honour the rotation request */
90383 +       __rotate_lcd(glamo, var->rotate);
90384 +
90385 +       /* update the reported geometry of the framebuffer. */
90386 +       if (orientation_changing) {
90387 +               var->xres_virtual = var->xres = yres;
90388 +               var->xres_virtual *= 2;
90389 +               var->yres_virtual = var->yres = xres;
90390 +       } else {
90391 +               var->xres_virtual = var->xres = xres;
90392 +               var->yres_virtual = var->yres = yres;
90393 +               var->yres_virtual *= 2;
90394 +       }
90395 +
90396 +       /* update scannout timings */
90397 +       sync = 0;
90398 +       bp = sync + var->hsync_len;
90399 +       disp = bp + var->left_margin;
90400 +       fp = disp + xres;
90401 +       total = fp + var->right_margin;
90402 +
90403 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_TOTAL,
90404 +                        GLAMO_LCD_HV_TOTAL_MASK, total);
90405 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_RETR_START,
90406 +                        GLAMO_LCD_HV_RETR_START_MASK, sync);
90407 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_RETR_END,
90408 +                        GLAMO_LCD_HV_RETR_END_MASK, bp);
90409 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_DISP_START,
90410 +                         GLAMO_LCD_HV_RETR_DISP_START_MASK, disp);
90411 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_DISP_END,
90412 +                        GLAMO_LCD_HV_RETR_DISP_END_MASK, fp);
90413 +
90414 +       sync = 0;
90415 +       bp = sync + var->vsync_len;
90416 +       disp = bp + var->upper_margin;
90417 +       fp = disp + yres;
90418 +       total = fp + var->lower_margin;
90419 +
90420 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_TOTAL,
90421 +                        GLAMO_LCD_HV_TOTAL_MASK, total);
90422 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_RETR_START,
90423 +                         GLAMO_LCD_HV_RETR_START_MASK, sync);
90424 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_RETR_END,
90425 +                        GLAMO_LCD_HV_RETR_END_MASK, bp);
90426 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_DISP_START,
90427 +                        GLAMO_LCD_HV_RETR_DISP_START_MASK, disp);
90428 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_DISP_END,
90429 +                        GLAMO_LCD_HV_RETR_DISP_END_MASK, fp);
90430 +
90431 +       glamofb_cmd_mode(glamo, 0);
90432 +
90433 +out_unlock:
90434 +       dev_dbg(&glamo->mach_info->glamo->pdev->dev,
90435 +                     "glamofb_update_lcd_controller spin_unlock_irqrestore\n");
90436 +       spin_unlock_irqrestore(&glamo->lock_cmd, flags);
90437 +}
90438 +
90439 +static int glamofb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
90440 +{
90441 +       struct glamofb_handle *glamo = info->par;
90442 +       u_int16_t page = var->yoffset / glamo->mach_info->yres.defval;
90443 +       reg_write(glamo, GLAMO_REG_LCD_COMMAND2, page);
90444 +
90445 +       return 0;
90446 +}
90447 +
90448 +static int glamofb_set_par(struct fb_info *info)
90449 +{
90450 +       struct glamofb_handle *glamo = info->par;
90451 +       struct fb_var_screeninfo *var = &info->var;
90452 +
90453 +       if (glamo->mach_info->glamo->suspending) {
90454 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_set_par while "
90455 +                                                                "suspended\n");
90456 +               return -EBUSY;
90457 +       }
90458 +
90459 +       switch (var->bits_per_pixel) {
90460 +       case 16:
90461 +               info->fix.visual = FB_VISUAL_TRUECOLOR;
90462 +               break;
90463 +       default:
90464 +               printk("Smedia driver doesn't support != 16bpp\n");
90465 +               return -EINVAL;
90466 +       }
90467 +
90468 +       info->fix.line_length = (var->xres * var->bits_per_pixel) / 8;
90469 +
90470 +       glamofb_update_lcd_controller(glamo, var);
90471 +
90472 +       return 0;
90473 +}
90474 +
90475 +
90476 +static void notify_blank(struct fb_info *info, int blank_mode)
90477 +{
90478 +       struct fb_event event;
90479 +
90480 +       event.info = info;
90481 +       event.data = &blank_mode;
90482 +       fb_notifier_call_chain(FB_EVENT_CONBLANK, &event);
90483 +}
90484 +
90485 +
90486 +static int glamofb_blank(int blank_mode, struct fb_info *info)
90487 +{
90488 +       struct glamofb_handle *gfb = info->par;
90489 +       struct glamo_core *gcore = gfb->mach_info->glamo;
90490 +
90491 +       dev_dbg(gfb->dev, "glamofb_blank(%u)\n", blank_mode);
90492 +
90493 +       switch (blank_mode) {
90494 +       case FB_BLANK_VSYNC_SUSPEND:
90495 +       case FB_BLANK_HSYNC_SUSPEND:
90496 +               /* FIXME: add pdata hook/flag to indicate whether
90497 +                * we should already switch off pixel clock here */
90498 +               break;
90499 +       case FB_BLANK_POWERDOWN:
90500 +               /* disable the pixel clock */
90501 +               glamo_engine_clkreg_set(gcore, GLAMO_ENGINE_LCD,
90502 +                                       GLAMO_CLOCK_LCD_EN_DCLK, 0);
90503 +               break;
90504 +       case FB_BLANK_UNBLANK:
90505 +       case FB_BLANK_NORMAL:
90506 +               /* enable the pixel clock */
90507 +               glamo_engine_clkreg_set(gcore, GLAMO_ENGINE_LCD,
90508 +                                       GLAMO_CLOCK_LCD_EN_DCLK,
90509 +                                       GLAMO_CLOCK_LCD_EN_DCLK);
90510 +               notify_blank(info, blank_mode);
90511 +               break;
90512 +       }
90513 +
90514 +       /* FIXME: once we have proper clock management in glamo-core,
90515 +        * we can determine if other units need MCLK1 or the PLL, and
90516 +        * disable it if not used. */
90517 +       return 0;
90518 +}
90519 +
90520 +static inline unsigned int chan_to_field(unsigned int chan,
90521 +                                        struct fb_bitfield *bf)
90522 +{
90523 +       chan &= 0xffff;
90524 +       chan >>= 16 - bf->length;
90525 +       return chan << bf->offset;
90526 +}
90527 +
90528 +static int glamofb_setcolreg(unsigned regno,
90529 +                            unsigned red, unsigned green, unsigned blue,
90530 +                            unsigned transp, struct fb_info *info)
90531 +{
90532 +       struct glamofb_handle *glamo = info->par;
90533 +       unsigned int val;
90534 +
90535 +       if (glamo->mach_info->glamo->suspending) {
90536 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_set_par while "
90537 +                                                                "suspended\n");
90538 +               return -EBUSY;
90539 +       }
90540 +
90541 +       switch (glamo->fb->fix.visual) {
90542 +       case FB_VISUAL_TRUECOLOR:
90543 +       case FB_VISUAL_DIRECTCOLOR:
90544 +               /* true-colour, use pseuo-palette */
90545 +
90546 +               if (regno < 16) {
90547 +                       u32 *pal = glamo->fb->pseudo_palette;
90548 +
90549 +                       val  = chan_to_field(red, &glamo->fb->var.red);
90550 +                       val |= chan_to_field(green, &glamo->fb->var.green);
90551 +                       val |= chan_to_field(blue, &glamo->fb->var.blue);
90552 +
90553 +                       pal[regno] = val;
90554 +               };
90555 +               break;
90556 +       default:
90557 +               return 1; /* unknown type */
90558 +       }
90559 +
90560 +       return 0;
90561 +}
90562 +
90563 +#ifdef CONFIG_MFD_GLAMO_HWACCEL
90564 +static inline void glamofb_vsync_wait(struct glamofb_handle *glamo,
90565 +               int line, int size, int range)
90566 +{
90567 +       int count[2];
90568 +
90569 +       do {
90570 +               count[0] = reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
90571 +               count[1] = reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
90572 +       } while (count[0] != count[1] ||
90573 +                       (line < count[0] + range &&
90574 +                        size > count[0] - range) ||
90575 +                       count[0] < range * 2);
90576 +}
90577 +
90578 +/*
90579 + * Enable/disable the hardware cursor mode altogether
90580 + * (for blinking and such, use glamofb_cursor()).
90581 + */
90582 +static void glamofb_cursor_onoff(struct glamofb_handle *glamo, int on)
90583 +{
90584 +       int y, size;
90585 +
90586 +       if (glamo->cursor_on) {
90587 +               y = reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_POS);
90588 +               size = reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE);
90589 +
90590 +               glamofb_vsync_wait(glamo, y, size, 30);
90591 +       }
90592 +
90593 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_MODE1,
90594 +                       GLAMO_LCD_MODE1_CURSOR_EN,
90595 +                       on ? GLAMO_LCD_MODE1_CURSOR_EN : 0);
90596 +       glamo->cursor_on = on;
90597 +
90598 +       /* Hide the cursor by default */
90599 +       reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE, 0);
90600 +}
90601 +
90602 +static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
90603 +{
90604 +       struct glamofb_handle *glamo = info->par;
90605 +       unsigned long flags;
90606 +
90607 +       spin_lock_irqsave(&glamo->lock_cmd, flags);
90608 +
90609 +       reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE,
90610 +                       cursor->enable ? cursor->image.width : 0);
90611 +
90612 +       if (cursor->set & FB_CUR_SETPOS) {
90613 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_POS,
90614 +                         cursor->image.dx);
90615 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_POS,
90616 +                         cursor->image.dy);
90617 +       }
90618 +
90619 +       if (cursor->set & FB_CUR_SETCMAP) {
90620 +               uint16_t fg = glamo->pseudo_pal[cursor->image.fg_color];
90621 +               uint16_t bg = glamo->pseudo_pal[cursor->image.bg_color];
90622 +
90623 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_FG_COLOR, fg);
90624 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_BG_COLOR, bg);
90625 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_DST_COLOR, fg);
90626 +       }
90627 +
90628 +       if (cursor->set & FB_CUR_SETHOT)
90629 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_PRESET,
90630 +                               (cursor->hot.x << 8) | cursor->hot.y);
90631 +
90632 +       if ((cursor->set & FB_CUR_SETSIZE) ||
90633 +           (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE))) {
90634 +               int x, y, pitch, op;
90635 +               const uint8_t *pcol = cursor->image.data;
90636 +               const uint8_t *pmsk = cursor->mask;
90637 +               uint8_t __iomem *dst = glamo->cursor_addr;
90638 +               uint8_t dcol = 0;
90639 +               uint8_t dmsk = 0;
90640 +               uint8_t byte = 0;
90641 +
90642 +               if (cursor->image.depth > 1) {
90643 +                       spin_unlock_irqrestore(&glamo->lock_cmd, flags);
90644 +                       return -EINVAL;
90645 +               }
90646 +
90647 +               pitch = ((cursor->image.width + 7) >> 2) & ~1;
90648 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_PITCH,
90649 +                       pitch);
90650 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE,
90651 +                       cursor->image.height);
90652 +
90653 +               for (y = 0; y < cursor->image.height; y++) {
90654 +                       byte = 0;
90655 +                       for (x = 0; x < cursor->image.width; x++) {
90656 +                               if ((x % 8) == 0) {
90657 +                                       dcol = *pcol++;
90658 +                                       dmsk = *pmsk++;
90659 +                               } else {
90660 +                                       dcol >>= 1;
90661 +                                       dmsk >>= 1;
90662 +                               }
90663 +
90664 +                               if (cursor->rop == ROP_COPY)
90665 +                                       op = (dmsk & 1) ?
90666 +                                               (dcol & 1) ? 1 : 3 : 0;
90667 +                               else
90668 +                                       op = ((dmsk & 1) << 1) |
90669 +                                               ((dcol & 1) << 0);
90670 +                               byte |= op << ((x & 3) << 1);
90671 +
90672 +                               if (x % 4 == 3) {
90673 +                                       writeb(byte, dst + x / 4);
90674 +                                       byte = 0;
90675 +                               }
90676 +                       }
90677 +                       if (x % 4) {
90678 +                               writeb(byte, dst + x / 4);
90679 +                               byte = 0;
90680 +                       }
90681 +
90682 +                       dst += pitch;
90683 +               }
90684 +       }
90685 +
90686 +       spin_unlock_irqrestore(&glamo->lock_cmd, flags);
90687 +
90688 +       return 0;
90689 +}
90690 +#endif
90691 +
90692 +static inline int glamofb_cmdq_empty(struct glamofb_handle *gfb)
90693 +{
90694 +       /* DGCMdQempty -- 1 == command queue is empty */
90695 +       return reg_read(gfb, GLAMO_REG_LCD_STATUS1) & (1 << 15);
90696 +}
90697 +
90698 +/* call holding gfb->lock_cmd  when locking, until you unlock */
90699 +int glamofb_cmd_mode(struct glamofb_handle *gfb, int on)
90700 +{
90701 +       int timeout = 2000000;
90702 +
90703 +       if (gfb->mach_info->glamo->suspending) {
90704 +               dev_err(&gfb->mach_info->glamo->pdev->dev, "IGNORING glamofb_cmd_mode while "
90705 +                                                                "suspended\n");
90706 +               return -EBUSY;
90707 +       }
90708 +
90709 +       dev_dbg(gfb->dev, "glamofb_cmd_mode(gfb=%p, on=%d)\n", gfb, on);
90710 +       if (on) {
90711 +               dev_dbg(gfb->dev, "%s: waiting for cmdq empty: ",
90712 +                       __FUNCTION__);
90713 +               while ((!glamofb_cmdq_empty(gfb)) && (timeout--))
90714 +                       /* yield() */;
90715 +               if (timeout < 0) {
90716 +                       printk(KERN_ERR"*************"
90717 +                                      "glamofb cmd_queue never got empty"
90718 +                                      "*************\n");
90719 +                       return -EIO;
90720 +               }
90721 +               dev_dbg(gfb->dev, "empty!\n");
90722 +
90723 +               /* display the entire frame then switch to command */
90724 +               reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
90725 +                         GLAMO_LCD_CMD_TYPE_DISP |
90726 +                         GLAMO_LCD_CMD_DATA_FIRE_VSYNC);
90727 +
90728 +               /* wait until lcd idle */
90729 +               dev_dbg(gfb->dev, "waiting for lcd idle: ");
90730 +               timeout = 2000000;
90731 +               while ((!reg_read(gfb, GLAMO_REG_LCD_STATUS2) & (1 << 12)) &&
90732 +                     (timeout--))
90733 +                       /* yield() */;
90734 +               if (timeout < 0) {
90735 +                       printk(KERN_ERR"*************"
90736 +                                      "glamofb lcd never idle"
90737 +                                      "*************\n");
90738 +                       return -EIO;
90739 +               }
90740 +
90741 +               mdelay(100);
90742 +
90743 +               dev_dbg(gfb->dev, "cmd mode entered\n");
90744 +
90745 +       } else {
90746 +               /* RGB interface needs vsync/hsync */
90747 +               if (reg_read(gfb, GLAMO_REG_LCD_MODE3) & GLAMO_LCD_MODE3_RGB)
90748 +                       reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
90749 +                                 GLAMO_LCD_CMD_TYPE_DISP |
90750 +                                 GLAMO_LCD_CMD_DATA_DISP_SYNC);
90751 +
90752 +               reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
90753 +                         GLAMO_LCD_CMD_TYPE_DISP |
90754 +                         GLAMO_LCD_CMD_DATA_DISP_FIRE);
90755 +       }
90756 +
90757 +       return 0;
90758 +}
90759 +EXPORT_SYMBOL_GPL(glamofb_cmd_mode);
90760 +
90761 +
90762 +int glamofb_cmd_write(struct glamofb_handle *gfb, u_int16_t val)
90763 +{
90764 +       int timeout = 200000;
90765 +
90766 +       if (gfb->mach_info->glamo->suspending) {
90767 +               dev_err(&gfb->mach_info->glamo->pdev->dev, "IGNORING glamofb_cmd_write while "
90768 +                                                                "suspended\n");
90769 +               return -EBUSY;
90770 +       }
90771 +
90772 +       dev_dbg(gfb->dev, "%s: waiting for cmdq empty\n", __FUNCTION__);
90773 +       while ((!glamofb_cmdq_empty(gfb)) && (timeout--))
90774 +               yield();
90775 +       if (timeout < 0) {
90776 +               printk(KERN_ERR"*************"
90777 +                               "glamofb cmd_queue never got empty"
90778 +                               "*************\n");
90779 +               return 1;
90780 +       }
90781 +       dev_dbg(gfb->dev, "idle, writing 0x%04x\n", val);
90782 +
90783 +       reg_write(gfb, GLAMO_REG_LCD_COMMAND1, val);
90784 +
90785 +       return 0;
90786 +}
90787 +EXPORT_SYMBOL_GPL(glamofb_cmd_write);
90788 +
90789 +static struct fb_ops glamofb_ops = {
90790 +       .owner          = THIS_MODULE,
90791 +       .fb_check_var   = glamofb_check_var,
90792 +       .fb_pan_display = glamofb_pan_display,
90793 +       .fb_set_par     = glamofb_set_par,
90794 +       .fb_blank       = glamofb_blank,
90795 +       .fb_setcolreg   = glamofb_setcolreg,
90796 +#ifdef CONFIG_MFD_GLAMO_HWACCEL
90797 +       .fb_cursor      = glamofb_cursor,
90798 +#endif
90799 +       .fb_fillrect    = cfb_fillrect,
90800 +       .fb_copyarea    = cfb_copyarea,
90801 +       .fb_imageblit   = cfb_imageblit,
90802 +};
90803 +
90804 +static int glamofb_init_regs(struct glamofb_handle *glamo)
90805 +{
90806 +       struct fb_info *info = glamo->fb;
90807 +
90808 +       glamofb_check_var(&info->var, info);
90809 +       glamofb_run_script(glamo, glamo_regs, ARRAY_SIZE(glamo_regs));
90810 +       glamofb_set_par(info);
90811 +
90812 +       return 0;
90813 +}
90814 +
90815 +static int __init glamofb_probe(struct platform_device *pdev)
90816 +{
90817 +       int rc = -EIO;
90818 +       struct fb_info *fbinfo;
90819 +       struct glamofb_handle *glamofb;
90820 +       struct glamofb_platform_data *mach_info = pdev->dev.platform_data;
90821 +
90822 +       printk(KERN_INFO "SMEDIA Glamo frame buffer driver (C) 2007 "
90823 +               "Openmoko, Inc.\n");
90824 +
90825 +       fbinfo = framebuffer_alloc(sizeof(struct glamofb_handle), &pdev->dev);
90826 +       if (!fbinfo)
90827 +               return -ENOMEM;
90828 +
90829 +       glamofb = fbinfo->par;
90830 +       glamofb->fb = fbinfo;
90831 +       glamofb->dev = &pdev->dev;
90832 +
90833 +       strcpy(fbinfo->fix.id, "SMedia Glamo");
90834 +
90835 +       glamofb->reg = platform_get_resource_byname(pdev, IORESOURCE_MEM,
90836 +                                                   "glamo-fb-regs");
90837 +       if (!glamofb->reg) {
90838 +               dev_err(&pdev->dev, "platform device with no registers?\n");
90839 +               rc = -ENOENT;
90840 +               goto out_free;
90841 +       }
90842 +
90843 +       glamofb->fb_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
90844 +                                                       "glamo-fb-mem");
90845 +       if (!glamofb->fb_res) {
90846 +               dev_err(&pdev->dev, "platform device with no memory ?\n");
90847 +               rc = -ENOENT;
90848 +               goto out_free;
90849 +       }
90850 +
90851 +       glamofb->reg = request_mem_region(glamofb->reg->start,
90852 +                                         RESSIZE(glamofb->reg), pdev->name);
90853 +       if (!glamofb->reg) {
90854 +               dev_err(&pdev->dev, "failed to request mmio region\n");
90855 +               goto out_free;
90856 +       }
90857 +
90858 +       glamofb->fb_res = request_mem_region(glamofb->fb_res->start,
90859 +                                            mach_info->fb_mem_size,
90860 +                                            pdev->name);
90861 +       if (!glamofb->fb_res) {
90862 +               dev_err(&pdev->dev, "failed to request vram region\n");
90863 +               goto out_release_reg;
90864 +       }
90865 +
90866 +       /* we want to remap only the registers required for this core
90867 +        * driver. */
90868 +       glamofb->base = ioremap(glamofb->reg->start, RESSIZE(glamofb->reg));
90869 +       if (!glamofb->base) {
90870 +               dev_err(&pdev->dev, "failed to ioremap() mmio memory\n");
90871 +               goto out_release_fb;
90872 +       }
90873 +       fbinfo->fix.smem_start = (unsigned long) glamofb->fb_res->start;
90874 +       fbinfo->fix.smem_len = mach_info->fb_mem_size;
90875 +
90876 +       fbinfo->screen_base = ioremap(glamofb->fb_res->start,
90877 +                                      RESSIZE(glamofb->fb_res));
90878 +       if (!fbinfo->screen_base) {
90879 +               dev_err(&pdev->dev, "failed to ioremap() vram memory\n");
90880 +               goto out_release_fb;
90881 +       }
90882 +       glamofb->cursor_addr = fbinfo->screen_base + 0x12C000;
90883 +
90884 +       platform_set_drvdata(pdev, glamofb);
90885 +
90886 +       glamofb->mach_info = pdev->dev.platform_data;
90887 +
90888 +       fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
90889 +       fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
90890 +       fbinfo->fix.type_aux = 0;
90891 +       fbinfo->fix.xpanstep = 0;
90892 +       fbinfo->fix.ypanstep = mach_info->yres.defval;
90893 +       fbinfo->fix.ywrapstep = 0;
90894 +       fbinfo->fix.accel = FB_ACCEL_GLAMO;
90895 +
90896 +       fbinfo->var.nonstd = 0;
90897 +       fbinfo->var.activate = FB_ACTIVATE_NOW;
90898 +       fbinfo->var.height = mach_info->height;
90899 +       fbinfo->var.width = mach_info->width;
90900 +       fbinfo->var.accel_flags = 0;    /* FIXME */
90901 +       fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
90902 +
90903 +       fbinfo->fbops = &glamofb_ops;
90904 +       fbinfo->flags = FBINFO_FLAG_DEFAULT;
90905 +       fbinfo->pseudo_palette = &glamofb->pseudo_pal;
90906 +
90907 +       fbinfo->var.xres = mach_info->xres.defval;
90908 +       fbinfo->var.xres_virtual = mach_info->xres.defval;
90909 +       fbinfo->var.yres = mach_info->yres.defval;
90910 +       fbinfo->var.yres_virtual = mach_info->yres.defval * 2;
90911 +       fbinfo->var.bits_per_pixel = mach_info->bpp.defval;
90912 +
90913 +       fbinfo->var.pixclock = mach_info->pixclock;
90914 +       fbinfo->var.left_margin = mach_info->left_margin;
90915 +       fbinfo->var.right_margin = mach_info->right_margin;
90916 +       fbinfo->var.upper_margin = mach_info->upper_margin;
90917 +       fbinfo->var.lower_margin = mach_info->lower_margin;
90918 +       fbinfo->var.hsync_len = mach_info->hsync_len;
90919 +       fbinfo->var.vsync_len = mach_info->vsync_len;
90920 +
90921 +       memset(fbinfo->screen_base, 0,
90922 +                       mach_info->xres.max *
90923 +                       mach_info->yres.max *
90924 +                       mach_info->bpp.max / 8);
90925 +
90926 +       glamo_engine_enable(mach_info->glamo, GLAMO_ENGINE_LCD);
90927 +       glamo_engine_reset(mach_info->glamo, GLAMO_ENGINE_LCD);
90928 +
90929 +       dev_info(&pdev->dev, "spin_lock_init\n");
90930 +       spin_lock_init(&glamofb->lock_cmd);
90931 +       glamofb_init_regs(glamofb);
90932 +#ifdef CONFIG_MFD_GLAMO_HWACCEL
90933 +       glamofb_cursor_onoff(glamofb, 1);
90934 +#endif
90935 +
90936 +       rc = register_framebuffer(fbinfo);
90937 +       if (rc < 0) {
90938 +               dev_err(&pdev->dev, "failed to register framebuffer\n");
90939 +               goto out_unmap_fb;
90940 +       }
90941 +
90942 +       if (mach_info->spi_info) {
90943 +               /* register the sibling spi device */
90944 +               mach_info->spi_info->glamofb_handle = glamofb;
90945 +               glamo_spi_dev.dev.parent = &pdev->dev;
90946 +               glamo_spi_dev.dev.platform_data = mach_info->spi_info;
90947 +               platform_device_register(&glamo_spi_dev);
90948 +       }
90949 +
90950 +       printk(KERN_INFO "fb%d: %s frame buffer device\n",
90951 +               fbinfo->node, fbinfo->fix.id);
90952 +
90953 +       return 0;
90954 +
90955 +out_unmap_fb:
90956 +       iounmap(fbinfo->screen_base);
90957 +       iounmap(glamofb->base);
90958 +out_release_fb:
90959 +       release_mem_region(glamofb->fb_res->start, RESSIZE(glamofb->fb_res));
90960 +out_release_reg:
90961 +       release_mem_region(glamofb->reg->start, RESSIZE(glamofb->reg));
90962 +out_free:
90963 +       framebuffer_release(fbinfo);
90964 +       return rc;
90965 +}
90966 +
90967 +static int glamofb_remove(struct platform_device *pdev)
90968 +{
90969 +       struct glamofb_handle *glamofb = platform_get_drvdata(pdev);
90970 +
90971 +       platform_set_drvdata(pdev, NULL);
90972 +       iounmap(glamofb->base);
90973 +       release_mem_region(glamofb->reg->start, RESSIZE(glamofb->reg));
90974 +       kfree(glamofb);
90975 +
90976 +       return 0;
90977 +}
90978 +
90979 +#ifdef CONFIG_PM
90980 +
90981 +static int glamofb_suspend(struct platform_device *pdev, pm_message_t state)
90982 +{
90983 +       struct glamofb_handle *gfb = platform_get_drvdata(pdev);
90984 +
90985 +       /* we need to stop anything touching our framebuffer */
90986 +//     fb_blank(gfb->fb, FB_BLANK_NORMAL);
90987 +       fb_set_suspend(gfb->fb, 1);
90988 +
90989 +       /* seriously -- nobody is allowed to touch glamo memory when we
90990 +        * are suspended or we lock on nWAIT
90991 +        */
90992 +//     iounmap(gfb->fb->screen_base);
90993 +
90994 +       return 0;
90995 +}
90996 +
90997 +static int glamofb_resume(struct platform_device *pdev)
90998 +{
90999 +       struct glamofb_handle *glamofb = platform_get_drvdata(pdev);
91000 +       struct glamofb_platform_data *mach_info = pdev->dev.platform_data;
91001 +
91002 +       /* OK let's allow framebuffer ops again */
91003 +//     gfb->fb->screen_base = ioremap(gfb->fb_res->start,
91004 +//                                    RESSIZE(gfb->fb_res));
91005 +       glamo_engine_enable(mach_info->glamo, GLAMO_ENGINE_LCD);
91006 +       glamo_engine_reset(mach_info->glamo, GLAMO_ENGINE_LCD);
91007 +
91008 +       printk(KERN_ERR"spin_lock_init\n");
91009 +       spin_lock_init(&glamofb->lock_cmd);
91010 +       glamofb_init_regs(glamofb);
91011 +#ifdef CONFIG_MFD_GLAMO_HWACCEL
91012 +       glamofb_cursor_onoff(glamofb, 1);
91013 +#endif
91014 +
91015 +
91016 +       fb_set_suspend(glamofb->fb, 0);
91017 +//     fb_blank(gfb->fb, FB_BLANK_UNBLANK);
91018 +
91019 +       return 0;
91020 +}
91021 +#else
91022 +#define glamo_suspend NULL
91023 +#define glamo_resume  NULL
91024 +#endif
91025 +
91026 +static struct platform_driver glamofb_driver = {
91027 +       .probe          = glamofb_probe,
91028 +       .remove         = glamofb_remove,
91029 +       .suspend        = glamofb_suspend,
91030 +       .resume = glamofb_resume,
91031 +       .driver         = {
91032 +               .name   = "glamo-fb",
91033 +               .owner  = THIS_MODULE,
91034 +       },
91035 +};
91036 +
91037 +static int __devinit glamofb_init(void)
91038 +{
91039 +       return platform_driver_register(&glamofb_driver);
91040 +}
91041 +
91042 +static void __exit glamofb_cleanup(void)
91043 +{
91044 +       platform_driver_unregister(&glamofb_driver);
91045 +}
91046 +
91047 +module_init(glamofb_init);
91048 +module_exit(glamofb_cleanup);
91049 +
91050 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
91051 +MODULE_DESCRIPTION("Smedia Glamo 336x/337x framebuffer driver");
91052 +MODULE_LICENSE("GPL");
91053 --- /dev/null
91054 +++ b/drivers/mfd/glamo/glamo-gpio.c
91055 @@ -0,0 +1,62 @@
91056 +
91057 +#include <linux/kernel.h>
91058 +#include <linux/module.h>
91059 +#include <linux/spinlock.h>
91060 +#include <linux/io.h>
91061 +
91062 +#include <linux/glamo-gpio.h>
91063 +
91064 +#include "glamo-core.h"
91065 +#include "glamo-regs.h"
91066 +
91067 +void glamo_gpio_setpin(struct glamo_core *glamo, unsigned int pin,
91068 +                      unsigned int value)
91069 +{
91070 +       unsigned int reg = REG_OF_GPIO(pin);
91071 +       u_int16_t tmp;
91072 +
91073 +       spin_lock(&glamo->lock);
91074 +       tmp = readw(glamo->base + reg);
91075 +       if (value)
91076 +               tmp |= OUTPUT_BIT(pin);
91077 +       else
91078 +               tmp &= ~OUTPUT_BIT(pin);
91079 +       writew(tmp, glamo->base + reg);
91080 +       spin_unlock(&glamo->lock);
91081 +}
91082 +EXPORT_SYMBOL(glamo_gpio_setpin);
91083 +
91084 +int glamo_gpio_getpin(struct glamo_core *glamo, unsigned int pin)
91085 +{
91086 +       return readw(REG_OF_GPIO(pin)) & INPUT_BIT(pin) ? 1 : 0;
91087 +}
91088 +EXPORT_SYMBOL(glamo_gpio_getpin);
91089 +
91090 +void glamo_gpio_cfgpin(struct glamo_core *glamo, unsigned int pinfunc)
91091 +{
91092 +       unsigned int reg = REG_OF_GPIO(pinfunc);
91093 +       u_int16_t tmp;
91094 +
91095 +       spin_lock(&glamo->lock);
91096 +       tmp = readw(glamo->base + reg);
91097 +
91098 +       if ((pinfunc & 0x00f0) == GLAMO_GPIO_F_FUNC) {
91099 +               /* pin is a function pin: clear gpio bit */
91100 +               tmp &= ~FUNC_BIT(pinfunc);
91101 +       } else {
91102 +               /* pin is gpio: set gpio bit */
91103 +               tmp |= FUNC_BIT(pinfunc);
91104 +
91105 +               if (pinfunc & GLAMO_GPIO_F_IN) {
91106 +                       /* gpio input: set bit to disable output mode */
91107 +                       tmp |= GPIO_OUT_BIT(pinfunc);
91108 +               } else if (pinfunc & GLAMO_GPIO_F_OUT) {
91109 +                       /* gpio output: clear bit to enable output mode */
91110 +                       tmp &= ~GPIO_OUT_BIT(pinfunc);
91111 +               }
91112 +       }
91113 +       writew(tmp, glamo->base + reg);
91114 +       spin_unlock(&glamo->lock);
91115 +}
91116 +EXPORT_SYMBOL(glamo_gpio_cfgpin);
91117 +
91118 --- /dev/null
91119 +++ b/drivers/mfd/glamo/glamo-lcm-spi.c
91120 @@ -0,0 +1,240 @@
91121 +/*
91122 + * Copyright (C) 2007 Openmoko, Inc.
91123 + * Author: Harald Welte <laforge@openmoko.org>
91124 + *
91125 + * Smedia Glamo GPIO based SPI driver
91126 + *
91127 + * This program is free software; you can redistribute it and/or modify
91128 + * it under the terms of the GNU General Public License version 2 as
91129 + * published by the Free Software Foundation.
91130 + *
91131 + * This driver currently only implements a minimum subset of the hardware
91132 + * features, esp. those features that are required to drive the jbt6k74
91133 + * LCM controller asic in the TD028TTEC1 LCM.
91134 + *
91135 +*/
91136 +
91137 +#define DEBUG
91138 +
91139 +#include <linux/kernel.h>
91140 +#include <linux/init.h>
91141 +#include <linux/delay.h>
91142 +#include <linux/device.h>
91143 +#include <linux/spinlock.h>
91144 +#include <linux/workqueue.h>
91145 +#include <linux/platform_device.h>
91146 +
91147 +#include <linux/spi/spi.h>
91148 +#include <linux/spi/spi_bitbang.h>
91149 +#include <linux/spi/glamo.h>
91150 +
91151 +#include <linux/glamofb.h>
91152 +
91153 +#include <mach/hardware.h>
91154 +
91155 +#include "glamo-core.h"
91156 +#include "glamo-regs.h"
91157 +
91158 +struct glamo_spi {
91159 +       struct spi_bitbang      bitbang;
91160 +       struct spi_master       *master;
91161 +       struct glamo_spi_info   *info;
91162 +       struct device           *dev;
91163 +};
91164 +
91165 +static inline struct glamo_spi *to_gs(struct spi_device *spi)
91166 +{
91167 +       return spi->controller_data;
91168 +}
91169 +
91170 +static int glamo_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
91171 +{
91172 +       unsigned int bpw;
91173 +
91174 +       bpw = t ? t->bits_per_word : spi->bits_per_word;
91175 +
91176 +       if (bpw != 9 && bpw != 8) {
91177 +               dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
91178 +               return -EINVAL;
91179 +       }
91180 +
91181 +       return 0;
91182 +}
91183 +
91184 +static void glamo_spi_chipsel(struct spi_device *spi, int value)
91185 +{
91186 +#if 0
91187 +       struct glamo_spi *gs = to_gs(spi);
91188 +
91189 +       dev_dbg(&spi->dev, "chipsel %d: spi=%p, gs=%p, info=%p, handle=%p\n",
91190 +               value, spi, gs, gs->info, gs->info->glamofb_handle);
91191 +
91192 +       glamofb_cmd_mode(gs->info->glamofb_handle, value);
91193 +#endif
91194 +}
91195 +
91196 +static int glamo_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
91197 +{
91198 +       struct glamo_spi *gs = to_gs(spi);
91199 +       const u_int16_t *ui16 = (const u_int16_t *) t->tx_buf;
91200 +       u_int16_t nine_bits;
91201 +       int i;
91202 +
91203 +       dev_dbg(&spi->dev, "txrx: tx %p, rx %p, bpw %d, len %d\n",
91204 +               t->tx_buf, t->rx_buf, t->bits_per_word, t->len);
91205 +
91206 +       if (spi->bits_per_word == 9)
91207 +               nine_bits = (1 << 9);
91208 +       else
91209 +               nine_bits = 0;
91210 +
91211 +       if (t->len > 3 * sizeof(u_int16_t)) {
91212 +               dev_err(&spi->dev, "this driver doesn't support "
91213 +                       "%u sized xfers\n", t->len);
91214 +               return -EINVAL;
91215 +       }
91216 +
91217 +       for (i = 0; i < t->len/sizeof(u_int16_t); i++) {
91218 +               /* actually transfer the data */
91219 +#if 1
91220 +               glamofb_cmd_write(gs->info->glamofb_handle,
91221 +                                 GLAMO_LCD_CMD_TYPE_SERIAL | nine_bits |
91222 +                                 (1 << 10) | (1 << 11) | (ui16[i] & 0x1ff));
91223 +#endif
91224 +               /* FIXME: fire ?!? */
91225 +               if (i == 0 && (ui16[i] & 0x1ff) == 0x29) {
91226 +                       dev_dbg(&spi->dev, "leaving command mode\n");
91227 +                       glamofb_cmd_mode(gs->info->glamofb_handle, 0);
91228 +               }
91229 +       }
91230 +
91231 +       return t->len;
91232 +}
91233 +
91234 +static int glamo_spi_setup(struct spi_device *spi)
91235 +{
91236 +       int ret;
91237 +
91238 +       if (!spi->bits_per_word)
91239 +               spi->bits_per_word = 9;
91240 +
91241 +       /* FIXME: hardware can do this */
91242 +       if (spi->mode & SPI_LSB_FIRST)
91243 +               return -EINVAL;
91244 +
91245 +       ret = glamo_spi_setupxfer(spi, NULL);
91246 +       if (ret < 0) {
91247 +               dev_err(&spi->dev, "setupxfer returned %d\n", ret);
91248 +               return ret;
91249 +       }
91250 +
91251 +       dev_dbg(&spi->dev, "%s: mode %d, %u bpw\n",
91252 +               __FUNCTION__, spi->mode, spi->bits_per_word);
91253 +
91254 +       return 0;
91255 +}
91256 +
91257 +static int glamo_spi_probe(struct platform_device *pdev)
91258 +{
91259 +       struct spi_master *master;
91260 +       struct glamo_spi *sp;
91261 +       int ret;
91262 +       int i;
91263 +
91264 +       master = spi_alloc_master(&pdev->dev, sizeof(struct glamo_spi));
91265 +       if (master == NULL) {
91266 +               dev_err(&pdev->dev, "failed to allocate spi master\n");
91267 +               ret = -ENOMEM;
91268 +               goto err;
91269 +       }
91270 +
91271 +       sp = spi_master_get_devdata(master);
91272 +       memset(sp, 0, sizeof(struct glamo_spi));
91273 +
91274 +       sp->master = spi_master_get(master);
91275 +       sp->info = pdev->dev.platform_data;
91276 +       if (!sp->info) {
91277 +               dev_err(&pdev->dev, "can't operate without platform data\n");
91278 +               ret = -EIO;
91279 +               goto err_no_pdev;
91280 +       }
91281 +       dev_dbg(&pdev->dev, "sp->info(pdata) = %p\n", sp->info);
91282 +
91283 +       sp->dev = &pdev->dev;
91284 +
91285 +       platform_set_drvdata(pdev, sp);
91286 +
91287 +       sp->bitbang.master = sp->master;
91288 +       sp->bitbang.setup_transfer = glamo_spi_setupxfer;
91289 +       sp->bitbang.chipselect = glamo_spi_chipsel;
91290 +       sp->bitbang.txrx_bufs = glamo_spi_txrx;
91291 +       sp->bitbang.master->setup = glamo_spi_setup;
91292 +
91293 +       ret = spi_bitbang_start(&sp->bitbang);
91294 +       if (ret)
91295 +               goto err_no_bitbang;
91296 +
91297 +       /* register the chips to go with the board */
91298 +
91299 +       glamofb_cmd_mode(sp->info->glamofb_handle, 1);
91300 +
91301 +       for (i = 0; i < sp->info->board_size; i++) {
91302 +               dev_info(&pdev->dev, "registering %p: %s\n",
91303 +                        &sp->info->board_info[i],
91304 +                        sp->info->board_info[i].modalias);
91305 +
91306 +               sp->info->board_info[i].controller_data = sp;
91307 +               spi_new_device(master, sp->info->board_info + i);
91308 +       }
91309 +
91310 +       return 0;
91311 +
91312 +err_no_bitbang:
91313 +       platform_set_drvdata(pdev, NULL);
91314 +err_no_pdev:
91315 +       spi_master_put(sp->bitbang.master);
91316 +err:
91317 +       return ret;
91318 +
91319 +}
91320 +
91321 +static int glamo_spi_remove(struct platform_device *pdev)
91322 +{
91323 +       struct glamo_spi *sp = platform_get_drvdata(pdev);
91324 +
91325 +       spi_bitbang_stop(&sp->bitbang);
91326 +       spi_master_put(sp->bitbang.master);
91327 +
91328 +       return 0;
91329 +}
91330 +
91331 +#define glamo_spi_suspend NULL
91332 +#define glamo_spi_resume NULL
91333 +
91334 +static struct platform_driver glamo_spi_drv = {
91335 +       .probe          = glamo_spi_probe,
91336 +       .remove         = glamo_spi_remove,
91337 +       .suspend        = glamo_spi_suspend,
91338 +       .resume         = glamo_spi_resume,
91339 +       .driver         = {
91340 +               .name   = "glamo-lcm-spi",
91341 +               .owner  = THIS_MODULE,
91342 +       },
91343 +};
91344 +
91345 +static int __init glamo_spi_init(void)
91346 +{
91347 +       return platform_driver_register(&glamo_spi_drv);
91348 +}
91349 +
91350 +static void __exit glamo_spi_exit(void)
91351 +{
91352 +       platform_driver_unregister(&glamo_spi_drv);
91353 +}
91354 +
91355 +module_init(glamo_spi_init);
91356 +module_exit(glamo_spi_exit);
91357 +
91358 +MODULE_DESCRIPTION("Smedia Glamo 336x/337x LCM serial command SPI Driver");
91359 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>")
91360 +MODULE_LICENSE("GPL");
91361 --- /dev/null
91362 +++ b/drivers/mfd/glamo/glamo-mci.c
91363 @@ -0,0 +1,1133 @@
91364 +/*
91365 + *  linux/drivers/mmc/host/glamo-mmc.c - Glamo MMC driver
91366 + *
91367 + *  Copyright (C) 2007 Openmoko, Inc,  Andy Green <andy@openmoko.com>
91368 + *  Based on S3C MMC driver that was:
91369 + *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
91370 + *
91371 + * This program is free software; you can redistribute it and/or modify
91372 + * it under the terms of the GNU General Public License version 2 as
91373 + * published by the Free Software Foundation.
91374 + */
91375 +
91376 +#include <linux/module.h>
91377 +#include <linux/dma-mapping.h>
91378 +#include <linux/clk.h>
91379 +#include <linux/mmc/mmc.h>
91380 +#include <linux/mmc/host.h>
91381 +#include <linux/platform_device.h>
91382 +#include <linux/irq.h>
91383 +#include <linux/pcf50633.h>
91384 +#include <linux/delay.h>
91385 +#include <linux/interrupt.h>
91386 +#include <linux/spinlock.h>
91387 +
91388 +#include <asm/dma.h>
91389 +#include <asm/dma-mapping.h>
91390 +#include <asm/io.h>
91391 +
91392 +#include "glamo-mci.h"
91393 +#include "glamo-core.h"
91394 +#include "glamo-regs.h"
91395 +
91396 +/* from glamo-core.c */
91397 +extern struct glamo_mci_pdata glamo_mci_def_pdata;
91398 +
91399 +static spinlock_t clock_lock;
91400 +
91401 +#define DRIVER_NAME "glamo-mci"
91402 +#define RESSIZE(ressource) (((ressource)->end - (ressource)->start) + 1)
91403 +
91404 +static void glamo_mci_send_request(struct mmc_host *mmc);
91405 +
91406 +/*
91407 + * Max SD clock rate
91408 + *
91409 + * held at /(3 + 1) due to concerns of 100R recommended series resistor
91410 + * allows 16MHz @ 4-bit --> 8MBytes/sec raw
91411 + *
91412 + * you can override this on kernel commandline using
91413 + *
91414 + *   glamo_mci.sd_max_clk=10000000
91415 + *
91416 + * for example
91417 + */
91418 +
91419 +static int sd_max_clk = 50000000 / 3;
91420 +module_param(sd_max_clk, int, 0644);
91421 +
91422 +/*
91423 + * Slow SD clock rate
91424 + *
91425 + * you can override this on kernel commandline using
91426 + *
91427 + *   glamo_mci.sd_slow_ratio=8
91428 + *
91429 + * for example
91430 + *
91431 + * platform callback is used to decide effective clock rate, if not
91432 + * defined then max is used, if defined and returns nonzero, rate is
91433 + * divided by this factor
91434 + */
91435 +
91436 +static int sd_slow_ratio = 8;
91437 +module_param(sd_slow_ratio, int, 0644);
91438 +
91439 +/*
91440 + * Post-power SD clock rate
91441 + *
91442 + * you can override this on kernel commandline using
91443 + *
91444 + *   glamo_mci.sd_post_power_clock=1000000
91445 + *
91446 + * for example
91447 + *
91448 + * After changing power to card, clock is held at this rate until first bulk
91449 + * transfer completes
91450 + */
91451 +
91452 +static int sd_post_power_clock = 1000000;
91453 +module_param(sd_post_power_clock, int, 0644);
91454 +
91455 +
91456 +/*
91457 + * SD Signal drive strength
91458 + *
91459 + * you can override this on kernel commandline using
91460 + *
91461 + *   glamo_mci.sd_drive=0
91462 + *
91463 + * for example
91464 + */
91465 +
91466 +static int sd_drive;
91467 +module_param(sd_drive, int, 0644);
91468 +
91469 +/*
91470 + * SD allow SD clock to run while idle
91471 + *
91472 + * you can override this on kernel commandline using
91473 + *
91474 + *   glamo_mci.sd_idleclk=0
91475 + *
91476 + * for example
91477 + */
91478 +
91479 +static int sd_idleclk = 0; /* disallow idle clock by default */
91480 +module_param(sd_idleclk, int, 0644);
91481 +
91482 +/* used to stash real idleclk state in suspend: we force it to run in there */
91483 +static int suspend_sd_idleclk;
91484 +
91485 +
91486 +unsigned char CRC7(u8 * pu8, int cnt)
91487 +{
91488 +       u8 crc = 0;
91489 +
91490 +       while (cnt--) {
91491 +               int n;
91492 +               u8 d = *pu8++;
91493 +               for (n = 0; n < 8; n++) {
91494 +                       crc <<= 1;
91495 +                       if ((d & 0x80) ^ (crc & 0x80))
91496 +                               crc ^= 0x09;
91497 +                       d <<= 1;
91498 +               }
91499 +       }
91500 +       return (crc << 1) | 1;
91501 +}
91502 +
91503 +static int get_data_buffer(struct glamo_mci_host *host,
91504 +                          volatile u32 *words, volatile u16 **pointer)
91505 +{
91506 +       struct scatterlist *sg;
91507 +
91508 +       *words = 0;
91509 +       *pointer = NULL;
91510 +
91511 +       if (host->pio_active == XFER_NONE)
91512 +               return -EINVAL;
91513 +
91514 +       if ((!host->mrq) || (!host->mrq->data))
91515 +               return -EINVAL;
91516 +
91517 +       if (host->pio_sgptr >= host->mrq->data->sg_len) {
91518 +               dev_dbg(&host->pdev->dev, "no more buffers (%i/%i)\n",
91519 +                     host->pio_sgptr, host->mrq->data->sg_len);
91520 +               return -EBUSY;
91521 +       }
91522 +       sg = &host->mrq->data->sg[host->pio_sgptr];
91523 +
91524 +       *words = sg->length >> 1; /* we are working with a 16-bit data bus */
91525 +       *pointer = page_address(sg_page(sg)) + sg->offset;
91526 +
91527 +       BUG_ON(((long)(*pointer)) & 1);
91528 +
91529 +       host->pio_sgptr++;
91530 +
91531 +       /* dev_info(&host->pdev->dev, "new buffer (%i/%i)\n",
91532 +             host->pio_sgptr, host->mrq->data->sg_len); */
91533 +       return 0;
91534 +}
91535 +
91536 +static void do_pio_read(struct glamo_mci_host *host)
91537 +{
91538 +       int res;
91539 +       u16 __iomem *from_ptr = host->base_data + (RESSIZE(host->mem_data) /
91540 +                                                             sizeof(u16) / 2);
91541 +#ifdef DEBUG
91542 +       u16 * block;
91543 +#endif
91544 +
91545 +       while (1) {
91546 +               res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
91547 +               if (res) {
91548 +                       host->pio_active = XFER_NONE;
91549 +                       host->complete_what = COMPLETION_FINALIZE;
91550 +
91551 +                       dev_dbg(&host->pdev->dev, "pio_read(): "
91552 +                               "complete (no more data).\n");
91553 +                       return;
91554 +               }
91555 +
91556 +               dev_dbg(&host->pdev->dev, "pio_read(): host->pio_words: %d\n",
91557 +                               host->pio_words);
91558 +
91559 +               host->pio_count += host->pio_words << 1;
91560 +
91561 +#ifdef DEBUG
91562 +               block = (u16 *)host->pio_ptr;
91563 +               res = host->pio_words << 1;
91564 +#endif
91565 +#if 0
91566 +               /* u16-centric memcpy */
91567 +               while (host->pio_words--)
91568 +                       *host->pio_ptr++ = *from_ptr++;
91569 +#else
91570 +               /* memcpy can be faster? */
91571 +               memcpy((void *)host->pio_ptr, from_ptr, host->pio_words << 1);
91572 +               host->pio_ptr += host->pio_words;
91573 +#endif
91574 +
91575 +#ifdef DEBUG
91576 +               print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
91577 +                              (void *)block, res, 1);
91578 +#endif
91579 +       }
91580 +}
91581 +
91582 +static int do_pio_write(struct glamo_mci_host *host)
91583 +{
91584 +       int res = 0;
91585 +       volatile u16 __iomem *to_ptr = host->base_data;
91586 +       int err = 0;
91587 +
91588 +       dev_dbg(&host->pdev->dev, "pio_write():\n");
91589 +       while (!res) {
91590 +               res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
91591 +               if (res)
91592 +                       continue;
91593 +
91594 +               dev_dbg(&host->pdev->dev, "pio_write():new source: [%i]@[%p]\n",
91595 +                       host->pio_words, host->pio_ptr);
91596 +
91597 +               host->pio_count += host->pio_words << 1;
91598 +               while (host->pio_words--)
91599 +                       writew(*host->pio_ptr++, to_ptr++);
91600 +       }
91601 +
91602 +       dev_dbg(&host->pdev->dev, "pio_write(): complete\n");
91603 +       host->pio_active = XFER_NONE;
91604 +       return err;
91605 +}
91606 +
91607 +static void __glamo_mci_fix_card_div(struct glamo_mci_host *host, int div)
91608 +{
91609 +       unsigned long flags;
91610 +
91611 +       spin_lock_irqsave(&clock_lock, flags);
91612 +
91613 +       if (div < 0) {
91614 +               /* stop clock - remove clock from divider input */
91615 +               writew(readw(glamo_mci_def_pdata.pglamo->base +
91616 +                    GLAMO_REG_CLOCK_GEN5_1) & (~GLAMO_CLOCK_GEN51_EN_DIV_TCLK),
91617 +                    glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
91618 +
91619 +               goto done;
91620 +       } else {
91621 +               /* set the nearest prescaler factor
91622 +               *
91623 +               * register shared with SCLK divisor -- no chance of race because
91624 +               * we don't use sensor interface
91625 +               */
91626 +               writew((readw(glamo_mci_def_pdata.pglamo->base +
91627 +                               GLAMO_REG_CLOCK_GEN8) & 0xff00) | div,
91628 +                      glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN8);
91629 +               /* enable clock to divider input */
91630 +               writew(readw(glamo_mci_def_pdata.pglamo->base +
91631 +                       GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
91632 +                    glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
91633 +       }
91634 +
91635 +       if (host->force_slow_during_powerup)
91636 +               div = host->clk_rate / sd_post_power_clock;
91637 +       else
91638 +               if (host->pdata->glamo_mci_use_slow)
91639 +                       if ((host->pdata->glamo_mci_use_slow)())
91640 +                               div = div * sd_slow_ratio;
91641 +
91642 +       if (div > 255)
91643 +               div = 255;
91644 +
91645 +       /*
91646 +        * set the nearest prescaler factor
91647 +        *
91648 +        * register shared with SCLK divisor -- no chance of race because
91649 +        * we don't use sensor interface
91650 +        */
91651 +       writew((readw(glamo_mci_def_pdata.pglamo->base +
91652 +                       GLAMO_REG_CLOCK_GEN8) & 0xff00) | div,
91653 +               glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN8);
91654 +       /* enable clock to divider input */
91655 +       writew(readw(glamo_mci_def_pdata.pglamo->base +
91656 +               GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
91657 +               glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
91658 +
91659 +done:
91660 +       spin_unlock_irqrestore(&clock_lock, flags);
91661 +}
91662 +
91663 +static int __glamo_mci_set_card_clock(struct glamo_mci_host *host, int freq,
91664 +                                                                 int *division)
91665 +{
91666 +       int div = 0;
91667 +       int real_rate = 0;
91668 +
91669 +       if (freq) {
91670 +               /* Set clock */
91671 +               for (div = 0; div < 256; div++) {
91672 +                       real_rate = host->clk_rate / (div + 1);
91673 +                       if (real_rate <= freq)
91674 +                               break;
91675 +               }
91676 +               if (div > 255)
91677 +                       div = 255;
91678 +
91679 +               if (division)
91680 +                       *division = div;
91681 +
91682 +               __glamo_mci_fix_card_div(host, div);
91683 +
91684 +       } else {
91685 +               /* stop clock */
91686 +               if (division)
91687 +                       *division = 0xff;
91688 +
91689 +               if (!sd_idleclk && !host->force_slow_during_powerup)
91690 +                       /* clock off */
91691 +                       __glamo_mci_fix_card_div(host, -1);
91692 +       }
91693 +
91694 +       return real_rate;
91695 +}
91696 +
91697 +static void glamo_mci_irq(unsigned int irq, struct irq_desc *desc)
91698 +{
91699 +       struct glamo_mci_host *host = (struct glamo_mci_host *)
91700 +                                     desc->handler_data;
91701 +       u16 status;
91702 +       struct mmc_command *cmd;
91703 +       unsigned long iflags;
91704 +
91705 +       if (!host)
91706 +               return;
91707 +
91708 +       if (host->suspending) { /* bad news, dangerous time */
91709 +               dev_err(&host->pdev->dev, "****glamo_mci_irq before resumed\n");
91710 +               return;
91711 +       }
91712 +
91713 +       if (!host->mrq)
91714 +               return;
91715 +       cmd = host->mrq->cmd;
91716 +       if (!cmd)
91717 +               return;
91718 +
91719 +       spin_lock_irqsave(&host->complete_lock, iflags);
91720 +
91721 +       status = readw(host->base + GLAMO_REG_MMC_RB_STAT1);
91722 +
91723 +       /* ack this interrupt source */
91724 +       writew(GLAMO_IRQ_MMC,
91725 +              glamo_mci_def_pdata.pglamo->base + GLAMO_REG_IRQ_CLEAR);
91726 +
91727 +       if (status & (GLAMO_STAT1_MMC_RTOUT |
91728 +                     GLAMO_STAT1_MMC_DTOUT))
91729 +               cmd->error = -ETIMEDOUT;
91730 +       if (status & (GLAMO_STAT1_MMC_BWERR |
91731 +                     GLAMO_STAT1_MMC_BRERR))
91732 +               cmd->error = -EILSEQ;
91733 +       if (cmd->error) {
91734 +               dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
91735 +               goto done;
91736 +       }
91737 +
91738 +       /* disable the initial slow start after first bulk transfer */
91739 +       if (host->force_slow_during_powerup)
91740 +               host->force_slow_during_powerup--;
91741 +
91742 +       if (host->pio_active == XFER_READ)
91743 +               do_pio_read(host);
91744 +
91745 +       host->mrq->data->bytes_xfered = host->pio_count;
91746 +       dev_dbg(&host->pdev->dev, "status = 0x%04x count=%d\n",
91747 +                status, host->pio_count);
91748 +
91749 +       /* issue STOP if we have been given one to use */
91750 +       if (host->mrq->stop) {
91751 +               host->cmd_is_stop = 1;
91752 +               glamo_mci_send_request(host->mmc);
91753 +               host->cmd_is_stop = 0;
91754 +       }
91755 +
91756 +       if (!sd_idleclk && !host->force_slow_during_powerup)
91757 +               /* clock off */
91758 +               __glamo_mci_fix_card_div(host, -1);
91759 +
91760 +done:
91761 +       host->complete_what = COMPLETION_NONE;
91762 +       host->mrq = NULL;
91763 +       mmc_request_done(host->mmc, cmd->mrq);
91764 +       spin_unlock_irqrestore(&host->complete_lock, iflags);
91765 +}
91766 +
91767 +static int glamo_mci_send_command(struct glamo_mci_host *host,
91768 +                                 struct mmc_command *cmd)
91769 +{
91770 +       u8 u8a[6];
91771 +       u16 fire = 0;
91772 +
91773 +       /* if we can't do it, reject as busy */
91774 +       if (!readw(host->base + GLAMO_REG_MMC_RB_STAT1) &
91775 +            GLAMO_STAT1_MMC_IDLE) {
91776 +               host->mrq = NULL;
91777 +               cmd->error = -EBUSY;
91778 +               mmc_request_done(host->mmc, host->mrq);
91779 +               return -EBUSY;
91780 +       }
91781 +
91782 +       /* create an array in wire order for CRC computation */
91783 +       u8a[0] = 0x40 | (cmd->opcode & 0x3f);
91784 +       u8a[1] = (u8)(cmd->arg >> 24);
91785 +       u8a[2] = (u8)(cmd->arg >> 16);
91786 +       u8a[3] = (u8)(cmd->arg >> 8);
91787 +       u8a[4] = (u8)cmd->arg;
91788 +       u8a[5] = CRC7(&u8a[0], 5); /* CRC7 on first 5 bytes of packet */
91789 +
91790 +       /* issue the wire-order array including CRC in register order */
91791 +       writew((u8a[4] << 8) | u8a[5], host->base + GLAMO_REG_MMC_CMD_REG1);
91792 +       writew((u8a[2] << 8) | u8a[3], host->base + GLAMO_REG_MMC_CMD_REG2);
91793 +       writew((u8a[0] << 8) | u8a[1], host->base + GLAMO_REG_MMC_CMD_REG3);
91794 +
91795 +       /* command index toggle */
91796 +       fire |= (host->ccnt & 1) << 12;
91797 +
91798 +       /* set type of command */
91799 +       switch (mmc_cmd_type(cmd)) {
91800 +       case MMC_CMD_BC:
91801 +               fire |= GLAMO_FIRE_MMC_CMDT_BNR;
91802 +               break;
91803 +       case MMC_CMD_BCR:
91804 +               fire |= GLAMO_FIRE_MMC_CMDT_BR;
91805 +               break;
91806 +       case MMC_CMD_AC:
91807 +               fire |= GLAMO_FIRE_MMC_CMDT_AND;
91808 +               break;
91809 +       case MMC_CMD_ADTC:
91810 +               fire |= GLAMO_FIRE_MMC_CMDT_AD;
91811 +               break;
91812 +       }
91813 +       /*
91814 +        * if it expects a response, set the type expected
91815 +        *
91816 +        * R1, Length  : 48bit, Normal response
91817 +        * R1b, Length : 48bit, same R1, but added card busy status
91818 +        * R2, Length  : 136bit (really 128 bits with CRC snipped)
91819 +        * R3, Length  : 48bit (OCR register value)
91820 +        * R4, Length  : 48bit, SDIO_OP_CONDITION, Reverse SDIO Card
91821 +        * R5, Length  : 48bit, IO_RW_DIRECTION, Reverse SDIO Card
91822 +        * R6, Length  : 48bit (RCA register)
91823 +        * R7, Length  : 48bit (interface condition, VHS(voltage supplied),
91824 +        *                     check pattern, CRC7)
91825 +        */
91826 +       switch (mmc_resp_type(cmd)) {
91827 +       case MMC_RSP_R6: /* same index as R7 and R1 */
91828 +               fire |= GLAMO_FIRE_MMC_RSPT_R1;
91829 +               break;
91830 +       case MMC_RSP_R1B:
91831 +               fire |= GLAMO_FIRE_MMC_RSPT_R1b;
91832 +               break;
91833 +       case MMC_RSP_R2:
91834 +               fire |= GLAMO_FIRE_MMC_RSPT_R2;
91835 +               break;
91836 +       case MMC_RSP_R3:
91837 +               fire |= GLAMO_FIRE_MMC_RSPT_R3;
91838 +               break;
91839 +       /* R4 and R5 supported by chip not defined in linux/mmc/core.h (sdio) */
91840 +       }
91841 +       /*
91842 +        * From the command index, set up the command class in the host ctrllr
91843 +        *
91844 +        * missing guys present on chip but couldn't figure out how to use yet:
91845 +        *     0x0 "stream read"
91846 +        *     0x9 "cancel running command"
91847 +        */
91848 +       switch (cmd->opcode) {
91849 +       case MMC_READ_SINGLE_BLOCK:
91850 +               fire |= GLAMO_FIRE_MMC_CC_SBR; /* single block read */
91851 +               break;
91852 +       case MMC_SWITCH: /* 64 byte payload */
91853 +       case 0x33: /* observed issued by MCI */
91854 +       case MMC_READ_MULTIPLE_BLOCK:
91855 +               /* we will get an interrupt off this */
91856 +               if (!cmd->mrq->stop)
91857 +                       /* multiblock no stop */
91858 +                       fire |= GLAMO_FIRE_MMC_CC_MBRNS;
91859 +               else
91860 +                        /* multiblock with stop */
91861 +                       fire |= GLAMO_FIRE_MMC_CC_MBRS;
91862 +               break;
91863 +       case MMC_WRITE_BLOCK:
91864 +               fire |= GLAMO_FIRE_MMC_CC_SBW; /* single block write */
91865 +               break;
91866 +       case MMC_WRITE_MULTIPLE_BLOCK:
91867 +               if (cmd->mrq->stop)
91868 +                        /* multiblock with stop */
91869 +                       fire |= GLAMO_FIRE_MMC_CC_MBWS;
91870 +               else
91871 +//                      /* multiblock NO stop-- 'RESERVED'? */
91872 +                       fire |= GLAMO_FIRE_MMC_CC_MBWNS;
91873 +               break;
91874 +       case MMC_STOP_TRANSMISSION:
91875 +               fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */
91876 +               break;
91877 +       default:
91878 +               fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */
91879 +               break;
91880 +       }
91881 +
91882 +       /* always largest timeout */
91883 +       writew(0xfff, host->base + GLAMO_REG_MMC_TIMEOUT);
91884 +
91885 +       /* Generate interrupt on txfer */
91886 +       writew((readw(host->base + GLAMO_REG_MMC_BASIC) & 0x3e) |
91887 +                  0x0800 | GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
91888 +                  GLAMO_BASIC_MMC_EN_COMPL_INT | (sd_drive << 6),
91889 +                  host->base + GLAMO_REG_MMC_BASIC);
91890 +
91891 +       /* send the command out on the wire */
91892 +       /* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
91893 +       writew(fire, host->base + GLAMO_REG_MMC_CMD_FIRE);
91894 +       cmd->error = 0;
91895 +       return 0;
91896 +}
91897 +
91898 +static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
91899 +                                struct mmc_data *data)
91900 +{
91901 +       /*
91902 +        * the S-Media-internal RAM offset for our MMC buffer
91903 +        * Read is halfway up the buffer and write is at the start
91904 +        */
91905 +       if (data->flags & MMC_DATA_READ) {
91906 +               writew((u16)(GLAMO_FB_SIZE + (RESSIZE(host->mem_data) / 2)),
91907 +                          host->base + GLAMO_REG_MMC_WDATADS1);
91908 +               writew((u16)((GLAMO_FB_SIZE +
91909 +                                       (RESSIZE(host->mem_data) / 2)) >> 16),
91910 +                          host->base + GLAMO_REG_MMC_WDATADS2);
91911 +       } else {
91912 +               writew((u16)GLAMO_FB_SIZE, host->base +
91913 +                                              GLAMO_REG_MMC_RDATADS1);
91914 +               writew((u16)(GLAMO_FB_SIZE >> 16), host->base +
91915 +                                                      GLAMO_REG_MMC_RDATADS2);
91916 +       }
91917 +
91918 +       /* set up the block info */
91919 +       writew(data->blksz, host->base + GLAMO_REG_MMC_DATBLKLEN);
91920 +       writew(data->blocks, host->base + GLAMO_REG_MMC_DATBLKCNT);
91921 +       dev_dbg(&host->pdev->dev, "(blksz=%d, count=%d)\n",
91922 +                                  data->blksz, data->blocks);
91923 +       host->pio_sgptr = 0;
91924 +       host->pio_words = 0;
91925 +       host->pio_count = 0;
91926 +       host->pio_active = 0;
91927 +       /* if write, prep the write into the shared RAM before the command */
91928 +       if (data->flags & MMC_DATA_WRITE) {
91929 +               host->pio_active = XFER_WRITE;
91930 +               return do_pio_write(host);
91931 +       }
91932 +       host->pio_active = XFER_READ;
91933 +       return 0;
91934 +}
91935 +
91936 +static void glamo_mci_send_request(struct mmc_host *mmc)
91937 +{
91938 +       struct glamo_mci_host *host = mmc_priv(mmc);
91939 +       struct mmc_request *mrq = host->mrq;
91940 +       struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
91941 +       u16 * pu16 = (u16 *)&cmd->resp[0];
91942 +       u16 * reg_resp = (u16 *)(host->base + GLAMO_REG_MMC_CMD_RSP1);
91943 +       u16 status;
91944 +       int n;
91945 +       int timeout = 1000000;
91946 +       int insanity_timeout = 1000000;
91947 +
91948 +       if (host->suspending) {
91949 +               dev_err(&host->pdev->dev, "IGNORING glamo_mci_send_request while "
91950 +                                                                "suspended\n");
91951 +               cmd->error = -EIO;
91952 +               if (cmd->data)
91953 +                       cmd->data->error = -EIO;
91954 +               mmc_request_done(mmc, mrq);
91955 +               return;
91956 +       }
91957 +
91958 +       host->ccnt++;
91959 +       /*
91960 +        * somehow 2.6.24 MCI manages to issue MMC_WRITE_BLOCK *without* the
91961 +        * MMC_DATA_WRITE flag, WTF?  Work around the madness.
91962 +        */
91963 +       if (cmd->opcode == MMC_WRITE_BLOCK)
91964 +               if (mrq->data)
91965 +                       mrq->data->flags |= MMC_DATA_WRITE;
91966 +
91967 +        /* this guy has data to read/write? */
91968 +       if ((!host->cmd_is_stop) && cmd->data) {
91969 +               int res;
91970 +               host->dcnt++;
91971 +               res = glamo_mci_prepare_pio(host, cmd->data);
91972 +               if (res) {
91973 +                       cmd->error = -EIO;
91974 +                       cmd->data->error = -EIO;
91975 +                       mmc_request_done(mmc, mrq);
91976 +                       return;
91977 +               }
91978 +       }
91979 +
91980 +       dev_dbg(&host->pdev->dev,"cmd 0x%x, "
91981 +                "arg 0x%x data=%p mrq->stop=%p flags 0x%x\n",
91982 +                cmd->opcode, cmd->arg, cmd->data, cmd->mrq->stop,
91983 +                cmd->flags);
91984 +
91985 +       /* resume requested clock rate
91986 +        * scale it down by sd_slow_ratio if platform requests it
91987 +        */
91988 +       __glamo_mci_fix_card_div(host, host->clk_div);
91989 +
91990 +       if (glamo_mci_send_command(host, cmd))
91991 +               goto bail;
91992 +
91993 +       /* we are deselecting card?  because it isn't going to ack then... */
91994 +       if ((cmd->opcode == 7) && (cmd->arg == 0))
91995 +               goto done;
91996 +
91997 +       /*
91998 +        * we must spin until response is ready or timed out
91999 +        * -- we don't get interrupts unless there is a bulk rx
92000 +        */
92001 +       do
92002 +               status = readw(host->base + GLAMO_REG_MMC_RB_STAT1);
92003 +       while (((((status >> 15) & 1) != (host->ccnt & 1)) ||
92004 +               (!(status & (GLAMO_STAT1_MMC_RB_RRDY |
92005 +                            GLAMO_STAT1_MMC_RTOUT |
92006 +                            GLAMO_STAT1_MMC_DTOUT |
92007 +                            GLAMO_STAT1_MMC_BWERR |
92008 +                            GLAMO_STAT1_MMC_BRERR)))) && (insanity_timeout--));
92009 +
92010 +       if (insanity_timeout < 0)
92011 +               dev_info(&host->pdev->dev, "command timeout, continuing\n");
92012 +
92013 +       if (status & (GLAMO_STAT1_MMC_RTOUT |
92014 +                     GLAMO_STAT1_MMC_DTOUT))
92015 +               cmd->error = -ETIMEDOUT;
92016 +       if (status & (GLAMO_STAT1_MMC_BWERR |
92017 +                     GLAMO_STAT1_MMC_BRERR))
92018 +               cmd->error = -EILSEQ;
92019 +
92020 +       if (host->cmd_is_stop)
92021 +               goto bail;
92022 +
92023 +       if (cmd->error) {
92024 +               dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
92025 +               goto done;
92026 +       }
92027 +       /*
92028 +        * mangle the response registers in two different exciting
92029 +        * undocumented ways discovered by trial and error
92030 +        */
92031 +       if (mmc_resp_type(cmd) == MMC_RSP_R2)
92032 +               /* grab the response */
92033 +               for (n = 0; n < 8; n++) /* super mangle power 1 */
92034 +                       pu16[n ^ 6] = readw(&reg_resp[n]);
92035 +       else
92036 +               for (n = 0; n < 3; n++) /* super mangle power 2 */
92037 +                       pu16[n] = (readw(&reg_resp[n]) >> 8) |
92038 +                                 (readw(&reg_resp[n + 1]) << 8);
92039 +       /*
92040 +        * if we don't have bulk data to take care of, we're done
92041 +        */
92042 +       if (!cmd->data)
92043 +               goto done;
92044 +       if (!(cmd->data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)))
92045 +               goto done;
92046 +
92047 +       /*
92048 +        * Otherwise can can use the interrupt as async completion --
92049 +        * if there is read data coming, or we wait for write data to complete,
92050 +        * exit without mmc_request_done() as the payload interrupt
92051 +        * will service it
92052 +        */
92053 +       dev_dbg(&host->pdev->dev, "Waiting for payload data\n");
92054 +       /*
92055 +        * if the glamo INT# line isn't wired (*cough* it can happen)
92056 +        * I'm afraid we have to spin on the IRQ status bit and "be
92057 +        * our own INT# line"
92058 +        */
92059 +       if (!glamo_mci_def_pdata.pglamo->irq_works) {
92060 +               /*
92061 +                * we have faith we will get an "interrupt"...
92062 +                * but something insane like suspend problems can mean
92063 +                * we spin here forever, so we timeout after a LONG time
92064 +                */
92065 +               while ((!(readw(glamo_mci_def_pdata.pglamo->base +
92066 +                        GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) &&
92067 +                      (timeout--))
92068 +                       ;
92069 +
92070 +               if (timeout < 0) {
92071 +                       if (cmd->data->error)
92072 +                               cmd->data->error = -ETIMEDOUT;
92073 +                       dev_err(&host->pdev->dev, "Payload timeout\n");
92074 +                       goto bail;
92075 +               }
92076 +
92077 +               /* yay we are an interrupt controller! -- call the ISR
92078 +                * it will stop clock to card
92079 +                */
92080 +               glamo_mci_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC),
92081 +                             irq_desc + IRQ_GLAMO(GLAMO_IRQIDX_MMC));
92082 +       }
92083 +       return;
92084 +
92085 +done:
92086 +       host->complete_what = COMPLETION_NONE;
92087 +       host->mrq = NULL;
92088 +       mmc_request_done(host->mmc, cmd->mrq);
92089 +bail:
92090 +       if (!sd_idleclk && !host->force_slow_during_powerup)
92091 +               /* stop the clock to card */
92092 +               __glamo_mci_fix_card_div(host, -1);
92093 +}
92094 +
92095 +static void glamo_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
92096 +{
92097 +       struct glamo_mci_host *host = mmc_priv(mmc);
92098 +
92099 +       host->cmd_is_stop = 0;
92100 +       host->mrq = mrq;
92101 +       glamo_mci_send_request(mmc);
92102 +}
92103 +
92104 +#if 1
92105 +static void glamo_mci_reset(struct glamo_mci_host *host)
92106 +{
92107 +       if (host->suspending) {
92108 +               dev_err(&host->pdev->dev, "IGNORING glamo_mci_reset while "
92109 +                                                                "suspended\n");
92110 +               return;
92111 +       }
92112 +       dev_dbg(&host->pdev->dev, "******* glamo_mci_reset\n");
92113 +       /* reset MMC controller */
92114 +       writew(GLAMO_CLOCK_MMC_RESET | GLAMO_CLOCK_MMC_DG_TCLK |
92115 +                  GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK |
92116 +                  GLAMO_CLOCK_MMC_EN_M9CLK,
92117 +                  glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_MMC);
92118 +       udelay(10);
92119 +       /* and disable reset */
92120 +       writew(GLAMO_CLOCK_MMC_DG_TCLK |
92121 +                  GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK |
92122 +                  GLAMO_CLOCK_MMC_EN_M9CLK,
92123 +                  glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_MMC);
92124 +}
92125 +#endif
92126 +static inline int glamo_mci_get_mv(int vdd)
92127 +{
92128 +       int mv = 1650;
92129 +
92130 +       if (vdd > 7)
92131 +               mv += 350 + 100 * (vdd - 8);
92132 +
92133 +       return mv;
92134 +}
92135 +
92136 +static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
92137 +{
92138 +       struct glamo_mci_host *host = mmc_priv(mmc);
92139 +       struct regulator *regulator;
92140 +       int n = 0;
92141 +       int div;
92142 +       int powering = 0;
92143 +       int mv;
92144 +
92145 +       if (host->suspending) {
92146 +               dev_err(&host->pdev->dev, "IGNORING glamo_mci_set_ios while "
92147 +                                                                "suspended\n");
92148 +               return;
92149 +       }
92150 +
92151 +       regulator = host->regulator;
92152 +
92153 +       /* Set power */
92154 +       switch(ios->power_mode) {
92155 +       case MMC_POWER_UP:
92156 +               if (host->pdata->glamo_can_set_mci_power()) {
92157 +                       mv = glamo_mci_get_mv(ios->vdd);
92158 +                       regulator_set_voltage(regulator, mv * 1000, mv * 1000);
92159 +                       regulator_enable(regulator);
92160 +               }
92161 +               break;
92162 +       case MMC_POWER_ON:
92163 +               /*
92164 +                * we should use very slow clock until first bulk
92165 +                * transfer completes OK
92166 +                */
92167 +               host->force_slow_during_powerup = 1;
92168 +
92169 +               if (host->vdd_current != ios->vdd) {
92170 +                       if (host->pdata->glamo_can_set_mci_power()) {
92171 +                               mv = glamo_mci_get_mv(ios->vdd);
92172 +                               regulator_set_voltage(regulator, mv * 1000, mv * 1000);
92173 +                               printk(KERN_INFO "SD power -> %dmV\n", mv);
92174 +                       }
92175 +                       host->vdd_current = ios->vdd;
92176 +               }
92177 +               if (host->power_mode_current == MMC_POWER_OFF) {
92178 +                       glamo_engine_enable(glamo_mci_def_pdata.pglamo,
92179 +                                                             GLAMO_ENGINE_MMC);
92180 +                       powering = 1;
92181 +               }
92182 +               break;
92183 +
92184 +       case MMC_POWER_OFF:
92185 +       default:
92186 +               if (host->power_mode_current == MMC_POWER_OFF)
92187 +                       break;
92188 +               /* never want clocking with dead card */
92189 +               __glamo_mci_fix_card_div(host, -1);
92190 +
92191 +               glamo_engine_disable(glamo_mci_def_pdata.pglamo,
92192 +                                    GLAMO_ENGINE_MMC);
92193 +               regulator_disable(regulator);
92194 +               host->vdd_current = -1;
92195 +               break;
92196 +       }
92197 +       host->power_mode_current = ios->power_mode;
92198 +
92199 +       host->real_rate = __glamo_mci_set_card_clock(host, ios->clock, &div);
92200 +       host->clk_div = div;
92201 +
92202 +       /* after power-up, we are meant to give it >= 74 clocks so it can
92203 +        * initialize itself.  Doubt any modern cards need it but anyway...
92204 +        */
92205 +       if (powering)
92206 +               mdelay(1);
92207 +
92208 +       if (!sd_idleclk && !host->force_slow_during_powerup)
92209 +               /* stop the clock to card, because we are idle until transfer */
92210 +               __glamo_mci_fix_card_div(host, -1);
92211 +
92212 +       if ((ios->power_mode == MMC_POWER_ON) ||
92213 +           (ios->power_mode == MMC_POWER_UP)) {
92214 +               dev_info(&host->pdev->dev,
92215 +                       "powered (vdd = %d) clk: %lukHz div=%d (req: %ukHz). "
92216 +                       "Bus width=%d\n",(int)ios->vdd,
92217 +                       host->real_rate / 1000, (int)host->clk_div,
92218 +                       ios->clock / 1000, (int)ios->bus_width);
92219 +       } else
92220 +               dev_info(&host->pdev->dev, "glamo_mci_set_ios: power down.\n");
92221 +
92222 +       /* set bus width */
92223 +       host->bus_width = ios->bus_width;
92224 +       if (host->bus_width == MMC_BUS_WIDTH_4)
92225 +               n = GLAMO_BASIC_MMC_EN_4BIT_DATA;
92226 +       writew((readw(host->base + GLAMO_REG_MMC_BASIC) &
92227 +                                         (~(GLAMO_BASIC_MMC_EN_4BIT_DATA |
92228 +                                            GLAMO_BASIC_MMC_EN_DR_STR0 |
92229 +                                            GLAMO_BASIC_MMC_EN_DR_STR1))) | n |
92230 +                              sd_drive << 6, host->base + GLAMO_REG_MMC_BASIC);
92231 +}
92232 +
92233 +
92234 +/*
92235 + * no physical write protect supported by us
92236 + */
92237 +static int glamo_mci_get_ro(struct mmc_host *mmc)
92238 +{
92239 +       return 0;
92240 +}
92241 +
92242 +static struct mmc_host_ops glamo_mci_ops = {
92243 +       .request        = glamo_mci_request,
92244 +       .set_ios        = glamo_mci_set_ios,
92245 +       .get_ro         = glamo_mci_get_ro,
92246 +};
92247 +
92248 +static int glamo_mci_probe(struct platform_device *pdev)
92249 +{
92250 +       struct mmc_host         *mmc;
92251 +       struct glamo_mci_host   *host;
92252 +       int ret;
92253 +
92254 +       dev_info(&pdev->dev, "glamo_mci driver (C)2007 Openmoko, Inc\n");
92255 +
92256 +       mmc = mmc_alloc_host(sizeof(struct glamo_mci_host), &pdev->dev);
92257 +       if (!mmc) {
92258 +               ret = -ENOMEM;
92259 +               goto probe_out;
92260 +       }
92261 +
92262 +       host = mmc_priv(mmc);
92263 +       host->mmc = mmc;
92264 +       host->pdev = pdev;
92265 +       host->pdata = &glamo_mci_def_pdata;
92266 +       host->power_mode_current = MMC_POWER_OFF;
92267 +
92268 +       host->complete_what = COMPLETION_NONE;
92269 +       host->pio_active = XFER_NONE;
92270 +
92271 +       spin_lock_init(&host->complete_lock);
92272 +
92273 +       host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
92274 +       if (!host->mem) {
92275 +               dev_err(&pdev->dev,
92276 +                       "failed to get io memory region resouce.\n");
92277 +
92278 +               ret = -ENOENT;
92279 +               goto probe_free_host;
92280 +       }
92281 +
92282 +       host->mem = request_mem_region(host->mem->start,
92283 +               RESSIZE(host->mem), pdev->name);
92284 +
92285 +       if (!host->mem) {
92286 +               dev_err(&pdev->dev, "failed to request io memory region.\n");
92287 +               ret = -ENOENT;
92288 +               goto probe_free_host;
92289 +       }
92290 +
92291 +       host->base = ioremap(host->mem->start, RESSIZE(host->mem));
92292 +       if (!host->base) {
92293 +               dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
92294 +               ret = -EINVAL;
92295 +               goto probe_free_mem_region;
92296 +       }
92297 +
92298 +       host->regulator = regulator_get(&pdev->dev, "SD_3V3");
92299 +       if (!host->regulator) {
92300 +               dev_err(&pdev->dev, "Cannot proceed without regulator.\n");
92301 +               return -ENODEV;
92302 +       }
92303 +
92304 +       /* set the handler for our bit of the shared chip irq register */
92305 +       set_irq_handler(IRQ_GLAMO(GLAMO_IRQIDX_MMC), glamo_mci_irq);
92306 +       /* stash host as our handler's private data */
92307 +       set_irq_data(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
92308 +
92309 +       /* Get ahold of our data buffer we use for data in and out on MMC */
92310 +       host->mem_data = platform_get_resource(pdev, IORESOURCE_MEM, 1);
92311 +       if (!host->mem_data) {
92312 +               dev_err(&pdev->dev,
92313 +                       "failed to get io memory region resource.\n");
92314 +               ret = -ENOENT;
92315 +               goto probe_iounmap;
92316 +       }
92317 +
92318 +       host->mem_data = request_mem_region(host->mem_data->start,
92319 +               RESSIZE(host->mem_data), pdev->name);
92320 +
92321 +       if (!host->mem_data) {
92322 +               dev_err(&pdev->dev, "failed to request io memory region.\n");
92323 +               ret = -ENOENT;
92324 +               goto probe_iounmap;
92325 +       }
92326 +       host->base_data = ioremap(host->mem_data->start,
92327 +                                         RESSIZE(host->mem_data));
92328 +       host->data_max_size = RESSIZE(host->mem_data);
92329 +
92330 +       if (host->base_data == 0) {
92331 +               dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
92332 +               ret = -EINVAL;
92333 +               goto probe_free_mem_region_data;
92334 +       }
92335 +
92336 +       host->vdd_current = 0;
92337 +       host->clk_rate = 50000000; /* really it's 49152000 */
92338 +       host->clk_div = 16;
92339 +
92340 +       /* explain our host controller capabilities */
92341 +       mmc->ops        = &glamo_mci_ops;
92342 +       mmc->ocr_avail  = host->pdata->ocr_avail;
92343 +       mmc->caps       = MMC_CAP_4_BIT_DATA |
92344 +                         MMC_CAP_MMC_HIGHSPEED |
92345 +                         MMC_CAP_SD_HIGHSPEED;
92346 +       mmc->f_min      = host->clk_rate / 256;
92347 +       mmc->f_max      = sd_max_clk;
92348 +
92349 +       mmc->max_blk_count      = (1 << 16) - 1; /* GLAMO_REG_MMC_RB_BLKCNT */
92350 +       mmc->max_blk_size       = (1 << 12) - 1; /* GLAMO_REG_MMC_RB_BLKLEN */
92351 +       mmc->max_req_size       = RESSIZE(host->mem_data) / 2;
92352 +       mmc->max_seg_size       = mmc->max_req_size;
92353 +       mmc->max_phys_segs      = 1; /* hw doesn't talk about segs??? */
92354 +       mmc->max_hw_segs        = 1;
92355 +
92356 +       dev_info(&host->pdev->dev, "probe: mapped mci_base:%p irq:%u.\n",
92357 +               host->base, host->irq);
92358 +
92359 +       platform_set_drvdata(pdev, mmc);
92360 +
92361 +       glamo_engine_enable(glamo_mci_def_pdata.pglamo, GLAMO_ENGINE_MMC);
92362 +       glamo_mci_reset(host);
92363 +
92364 +       if ((ret = mmc_add_host(mmc))) {
92365 +               dev_err(&pdev->dev, "failed to add mmc host.\n");
92366 +               goto probe_free_mem_region_data;
92367 +       }
92368 +
92369 +       dev_info(&pdev->dev,"initialisation done.\n");
92370 +       return 0;
92371 +
92372 + probe_free_mem_region_data:
92373 +       release_mem_region(host->mem_data->start, RESSIZE(host->mem_data));
92374 +
92375 + probe_iounmap:
92376 +       iounmap(host->base);
92377 +
92378 + probe_free_mem_region:
92379 +       release_mem_region(host->mem->start, RESSIZE(host->mem));
92380 +
92381 + probe_free_host:
92382 +       mmc_free_host(mmc);
92383 + probe_out:
92384 +       return ret;
92385 +}
92386 +
92387 +static int glamo_mci_remove(struct platform_device *pdev)
92388 +{
92389 +       struct mmc_host         *mmc  = platform_get_drvdata(pdev);
92390 +       struct glamo_mci_host   *host = mmc_priv(mmc);
92391 +       struct regulator *regulator;
92392 +
92393 +       mmc_remove_host(mmc);
92394 +       /* stop using our handler, revert it to default */
92395 +       set_irq_handler(IRQ_GLAMO(GLAMO_IRQIDX_MMC), handle_level_irq);
92396 +       iounmap(host->base);
92397 +       iounmap(host->base_data);
92398 +       release_mem_region(host->mem->start, RESSIZE(host->mem));
92399 +       release_mem_region(host->mem_data->start, RESSIZE(host->mem_data));
92400 +
92401 +       regulator = host->regulator;
92402 +       regulator_put(regulator);
92403 +
92404 +       mmc_free_host(mmc);
92405 +
92406 +       glamo_engine_disable(glamo_mci_def_pdata.pglamo, GLAMO_ENGINE_MMC);
92407 +       return 0;
92408 +}
92409 +
92410 +
92411 +#ifdef CONFIG_PM
92412 +
92413 +static int glamo_mci_suspend(struct platform_device *dev, pm_message_t state)
92414 +{
92415 +       struct mmc_host *mmc = platform_get_drvdata(dev);
92416 +       struct glamo_mci_host   *host = mmc_priv(mmc);
92417 +       int ret;
92418 +
92419 +       /*
92420 +        * possible workaround for SD corruption during suspend - resume
92421 +        * make sure the clock was running during suspend and consequently
92422 +        * resume
92423 +        */
92424 +       __glamo_mci_fix_card_div(host, host->clk_div);
92425 +
92426 +       /* we are going to do more commands to override this in
92427 +        * mmc_suspend_host(), so we need to change sd_idleclk for the
92428 +        * duration as well
92429 +        */
92430 +       suspend_sd_idleclk = sd_idleclk;
92431 +       sd_idleclk = 1;
92432 +
92433 +       ret = mmc_suspend_host(mmc, state);
92434 +
92435 +       host->suspending++;
92436 +       /* so that when we resume, we use any modified max rate */
92437 +       mmc->f_max = sd_max_clk;
92438 +
92439 +       return ret;
92440 +}
92441 +
92442 +int glamo_mci_resume(struct platform_device *dev)
92443 +{
92444 +       struct mmc_host *mmc = platform_get_drvdata(dev);
92445 +       struct glamo_mci_host   *host = mmc_priv(mmc);
92446 +       int ret;
92447 +
92448 +       sd_idleclk = 1;
92449 +
92450 +       glamo_engine_enable(host->pdata->pglamo, GLAMO_ENGINE_MMC);
92451 +       glamo_mci_reset(host);
92452 +
92453 +       host->suspending--;
92454 +
92455 +       ret = mmc_resume_host(mmc);
92456 +
92457 +       /* put sd_idleclk back to pre-suspend state */
92458 +       sd_idleclk = suspend_sd_idleclk;
92459 +
92460 +       return ret;
92461 +}
92462 +EXPORT_SYMBOL_GPL(glamo_mci_resume);
92463 +
92464 +#else /* CONFIG_PM */
92465 +#define glamo_mci_suspend NULL
92466 +#define glamo_mci_resume NULL
92467 +#endif /* CONFIG_PM */
92468 +
92469 +
92470 +static struct platform_driver glamo_mci_driver =
92471 +{
92472 +       .driver.name    = "glamo-mci",
92473 +       .probe          = glamo_mci_probe,
92474 +       .remove         = glamo_mci_remove,
92475 +       .suspend        = glamo_mci_suspend,
92476 +       .resume         = glamo_mci_resume,
92477 +};
92478 +
92479 +static int __init glamo_mci_init(void)
92480 +{
92481 +       spin_lock_init(&clock_lock);
92482 +       platform_driver_register(&glamo_mci_driver);
92483 +       return 0;
92484 +}
92485 +
92486 +static void __exit glamo_mci_exit(void)
92487 +{
92488 +       platform_driver_unregister(&glamo_mci_driver);
92489 +}
92490 +
92491 +module_init(glamo_mci_init);
92492 +module_exit(glamo_mci_exit);
92493 +
92494 +MODULE_DESCRIPTION("Glamo MMC/SD Card Interface driver");
92495 +MODULE_LICENSE("GPL");
92496 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
92497 --- /dev/null
92498 +++ b/drivers/mfd/glamo/glamo-mci.h
92499 @@ -0,0 +1,83 @@
92500 +/*
92501 + *  linux/drivers/mmc/host/glamo-mmc.h - GLAMO MCI driver
92502 + *
92503 + *  Copyright (C) 2007-2008 Openmoko, Inc, Andy Green <andy@openmoko.com>
92504 + *   based on S3C MMC driver -->
92505 + *  Copyright (C) 2004-2006 Thomas Kleffel, All Rights Reserved.
92506 + *
92507 + * This program is free software; you can redistribute it and/or modify
92508 + * it under the terms of the GNU General Public License version 2 as
92509 + * published by the Free Software Foundation.
92510 + */
92511 +
92512 +#include <linux/regulator/consumer.h>
92513 +
92514 +enum glamo_mci_waitfor {
92515 +       COMPLETION_NONE,
92516 +       COMPLETION_FINALIZE,
92517 +       COMPLETION_CMDSENT,
92518 +       COMPLETION_RSPFIN,
92519 +       COMPLETION_XFERFINISH,
92520 +       COMPLETION_XFERFINISH_RSPFIN,
92521 +};
92522 +
92523 +struct glamo_mci_host {
92524 +       struct platform_device  *pdev;
92525 +       struct glamo_mci_pdata  *pdata;
92526 +       struct mmc_host         *mmc;
92527 +       struct resource         *mem;
92528 +       struct resource         *mem_data;
92529 +       struct clk              *clk;
92530 +       void __iomem            *base;
92531 +       u16 __iomem             *base_data;
92532 +       int                     irq;
92533 +       int                     irq_cd;
92534 +       int                     dma;
92535 +       int                     data_max_size;
92536 +
92537 +       int                     suspending;
92538 +
92539 +       int                     power_mode_current;
92540 +       unsigned int            vdd_current;
92541 +
92542 +       unsigned long           clk_rate;
92543 +       unsigned long           clk_div;
92544 +       unsigned long           real_rate;
92545 +       u8                      prescaler;
92546 +
92547 +       int                     force_slow_during_powerup;
92548 +
92549 +       unsigned                sdiimsk;
92550 +       int                     dodma;
92551 +
92552 +       volatile int            dmatogo;
92553 +
92554 +       struct mmc_request      *mrq;
92555 +       int                     cmd_is_stop;
92556 +
92557 +       spinlock_t              complete_lock;
92558 +       volatile enum glamo_mci_waitfor
92559 +                               complete_what;
92560 +
92561 +       volatile int            dma_complete;
92562 +
92563 +       volatile u32            pio_sgptr;
92564 +       volatile u32            pio_words;
92565 +       volatile u32            pio_count;
92566 +       volatile u16            *pio_ptr;
92567 +#define XFER_NONE 0
92568 +#define XFER_READ 1
92569 +#define XFER_WRITE 2
92570 +       volatile u32            pio_active;
92571 +
92572 +       int                     bus_width;
92573 +
92574 +       char                    dbgmsg_cmd[301];
92575 +       char                    dbgmsg_dat[301];
92576 +       volatile char           *status;
92577 +
92578 +       unsigned int            ccnt, dcnt;
92579 +       struct tasklet_struct   pio_tasklet;
92580 +
92581 +       struct regulator        *regulator;
92582 +};
92583 --- /dev/null
92584 +++ b/drivers/mfd/glamo/glamo-regs.h
92585 @@ -0,0 +1,632 @@
92586 +#ifndef _GLAMO_REGS_H
92587 +#define _GLAMO_REGS_H
92588 +
92589 +/* Smedia Glamo 336x/337x driver
92590 + *
92591 + * (C) 2007 by Openmoko, Inc.
92592 + * Author: Harald Welte <laforge@openmoko.org>
92593 + * All rights reserved.
92594 + *
92595 + * This program is free software; you can redistribute it and/or
92596 + * modify it under the terms of the GNU General Public License as
92597 + * published by the Free Software Foundation; either version 2 of
92598 + * the License, or (at your option) any later version.
92599 + *
92600 + * This program is distributed in the hope that it will be useful,
92601 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
92602 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
92603 + * GNU General Public License for more details.
92604 + *
92605 + * You should have received a copy of the GNU General Public License
92606 + * along with this program; if not, write to the Free Software
92607 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
92608 + * MA 02111-1307 USA
92609 + */
92610 +
92611 +enum glamo_regster_offsets {
92612 +       GLAMO_REGOFS_GENERIC    = 0x0000,
92613 +       GLAMO_REGOFS_HOSTBUS    = 0x0200,
92614 +       GLAMO_REGOFS_MEMORY     = 0x0300,
92615 +       GLAMO_REGOFS_VIDCAP     = 0x0400,
92616 +       GLAMO_REGOFS_ISP        = 0x0500,
92617 +       GLAMO_REGOFS_JPEG       = 0x0800,
92618 +       GLAMO_REGOFS_MPEG       = 0x0c00,
92619 +       GLAMO_REGOFS_LCD        = 0x1100,
92620 +       GLAMO_REGOFS_MMC        = 0x1400,
92621 +       GLAMO_REGOFS_MPROC0     = 0x1500,
92622 +       GLAMO_REGOFS_MPROC1     = 0x1580,
92623 +       GLAMO_REGOFS_CMDQUEUE   = 0x1600,
92624 +       GLAMO_REGOFS_RISC       = 0x1680,
92625 +       GLAMO_REGOFS_2D         = 0x1700,
92626 +       GLAMO_REGOFS_3D         = 0x1b00,
92627 +       GLAMO_REGOFS_END        = 0x2400,
92628 +};
92629 +
92630 +
92631 +enum glamo_register_generic {
92632 +       GLAMO_REG_GCONF1        = 0x0000,
92633 +       GLAMO_REG_GCONF2        = 0x0002,
92634 +#define        GLAMO_REG_DEVICE_ID     GLAMO_REG_GCONF2
92635 +       GLAMO_REG_GCONF3        = 0x0004,
92636 +#define        GLAMO_REG_REVISION_ID   GLAMO_REG_GCONF3
92637 +       GLAMO_REG_IRQ_GEN1      = 0x0006,
92638 +#define GLAMO_REG_IRQ_ENABLE   GLAMO_REG_IRQ_GEN1
92639 +       GLAMO_REG_IRQ_GEN2      = 0x0008,
92640 +#define GLAMO_REG_IRQ_SET      GLAMO_REG_IRQ_GEN2
92641 +       GLAMO_REG_IRQ_GEN3      = 0x000a,
92642 +#define GLAMO_REG_IRQ_CLEAR    GLAMO_REG_IRQ_GEN3
92643 +       GLAMO_REG_IRQ_GEN4      = 0x000c,
92644 +#define GLAMO_REG_IRQ_STATUS   GLAMO_REG_IRQ_GEN4
92645 +       GLAMO_REG_CLOCK_HOST    = 0x0010,
92646 +       GLAMO_REG_CLOCK_MEMORY  = 0x0012,
92647 +       GLAMO_REG_CLOCK_LCD     = 0x0014,
92648 +       GLAMO_REG_CLOCK_MMC     = 0x0016,
92649 +       GLAMO_REG_CLOCK_ISP     = 0x0018,
92650 +       GLAMO_REG_CLOCK_JPEG    = 0x001a,
92651 +       GLAMO_REG_CLOCK_3D      = 0x001c,
92652 +       GLAMO_REG_CLOCK_2D      = 0x001e,
92653 +       GLAMO_REG_CLOCK_RISC1   = 0x0020,       /* 3365 only? */
92654 +       GLAMO_REG_CLOCK_RISC2   = 0x0022,       /* 3365 only? */
92655 +       GLAMO_REG_CLOCK_MPEG    = 0x0024,
92656 +       GLAMO_REG_CLOCK_MPROC   = 0x0026,
92657 +
92658 +       GLAMO_REG_CLOCK_GEN5_1  = 0x0030,
92659 +       GLAMO_REG_CLOCK_GEN5_2  = 0x0032,
92660 +       GLAMO_REG_CLOCK_GEN6    = 0x0034,
92661 +       GLAMO_REG_CLOCK_GEN7    = 0x0036,
92662 +       GLAMO_REG_CLOCK_GEN8    = 0x0038,
92663 +       GLAMO_REG_CLOCK_GEN9    = 0x003a,
92664 +       GLAMO_REG_CLOCK_GEN10   = 0x003c,
92665 +       GLAMO_REG_CLOCK_GEN11   = 0x003e,
92666 +       GLAMO_REG_PLL_GEN1      = 0x0040,
92667 +       GLAMO_REG_PLL_GEN2      = 0x0042,
92668 +       GLAMO_REG_PLL_GEN3      = 0x0044,
92669 +       GLAMO_REG_PLL_GEN4      = 0x0046,
92670 +       GLAMO_REG_PLL_GEN5      = 0x0048,
92671 +       GLAMO_REG_GPIO_GEN1     = 0x0050,
92672 +       GLAMO_REG_GPIO_GEN2     = 0x0052,
92673 +       GLAMO_REG_GPIO_GEN3     = 0x0054,
92674 +       GLAMO_REG_GPIO_GEN4     = 0x0056,
92675 +       GLAMO_REG_GPIO_GEN5     = 0x0058,
92676 +       GLAMO_REG_GPIO_GEN6     = 0x005a,
92677 +       GLAMO_REG_GPIO_GEN7     = 0x005c,
92678 +       GLAMO_REG_GPIO_GEN8     = 0x005e,
92679 +       GLAMO_REG_GPIO_GEN9     = 0x0060,
92680 +       GLAMO_REG_GPIO_GEN10    = 0x0062,
92681 +       GLAMO_REG_DFT_GEN1      = 0x0070,
92682 +       GLAMO_REG_DFT_GEN2      = 0x0072,
92683 +       GLAMO_REG_DFT_GEN3      = 0x0074,
92684 +       GLAMO_REG_DFT_GEN4      = 0x0076,
92685 +
92686 +       GLAMO_REG_DFT_GEN5      = 0x01e0,
92687 +       GLAMO_REG_DFT_GEN6      = 0x01f0,
92688 +};
92689 +
92690 +#define GLAMO_REG_HOSTBUS(x)   (GLAMO_REGOFS_HOSTBUS-2+(x*2))
92691 +
92692 +#define REG_MEM(x)             (GLAMO_REGOFS_MEMORY+(x))
92693 +#define GLAMO_REG_MEM_TIMING(x)        (GLAMO_REG_MEM_TIMING1-2+(x*2))
92694 +
92695 +enum glamo_register_mem {
92696 +       GLAMO_REG_MEM_TYPE      = REG_MEM(0x00),
92697 +       GLAMO_REG_MEM_GEN       = REG_MEM(0x02),
92698 +       GLAMO_REG_MEM_TIMING1   = REG_MEM(0x04),
92699 +       GLAMO_REG_MEM_TIMING2   = REG_MEM(0x06),
92700 +       GLAMO_REG_MEM_TIMING3   = REG_MEM(0x08),
92701 +       GLAMO_REG_MEM_TIMING4   = REG_MEM(0x0a),
92702 +       GLAMO_REG_MEM_TIMING5   = REG_MEM(0x0c),
92703 +       GLAMO_REG_MEM_TIMING6   = REG_MEM(0x0e),
92704 +       GLAMO_REG_MEM_TIMING7   = REG_MEM(0x10),
92705 +       GLAMO_REG_MEM_TIMING8   = REG_MEM(0x12),
92706 +       GLAMO_REG_MEM_TIMING9   = REG_MEM(0x14),
92707 +       GLAMO_REG_MEM_TIMING10  = REG_MEM(0x16),
92708 +       GLAMO_REG_MEM_TIMING11  = REG_MEM(0x18),
92709 +       GLAMO_REG_MEM_POWER1    = REG_MEM(0x1a),
92710 +       GLAMO_REG_MEM_POWER2    = REG_MEM(0x1c),
92711 +       GLAMO_REG_MEM_LCD_BUF1  = REG_MEM(0x1e),
92712 +       GLAMO_REG_MEM_LCD_BUF2  = REG_MEM(0x20),
92713 +       GLAMO_REG_MEM_LCD_BUF3  = REG_MEM(0x22),
92714 +       GLAMO_REG_MEM_LCD_BUF4  = REG_MEM(0x24),
92715 +       GLAMO_REG_MEM_BIST1     = REG_MEM(0x26),
92716 +       GLAMO_REG_MEM_BIST2     = REG_MEM(0x28),
92717 +       GLAMO_REG_MEM_BIST3     = REG_MEM(0x2a),
92718 +       GLAMO_REG_MEM_BIST4     = REG_MEM(0x2c),
92719 +       GLAMO_REG_MEM_BIST5     = REG_MEM(0x2e),
92720 +       GLAMO_REG_MEM_MAH1      = REG_MEM(0x30),
92721 +       GLAMO_REG_MEM_MAH2      = REG_MEM(0x32),
92722 +       GLAMO_REG_MEM_DRAM1     = REG_MEM(0x34),
92723 +       GLAMO_REG_MEM_DRAM2     = REG_MEM(0x36),
92724 +       GLAMO_REG_MEM_CRC       = REG_MEM(0x38),
92725 +};
92726 +
92727 +#define GLAMO_MEM_TYPE_MASK    0x03
92728 +
92729 +enum glamo_reg_mem_dram1 {
92730 +       /* b0 - b10 == refresh period, 1 -> 2048 clocks */
92731 +       GLAMO_MEM_DRAM1_EN_GATE_CLK     = (1 << 11),
92732 +       GLAMO_MEM_DRAM1_SELF_REFRESH    = (1 << 12),
92733 +       GLAMO_MEM_DRAM1_EN_GATE_CKE     = (1 << 13),
92734 +       GLAMO_MEM_DRAM1_EN_DRAM_REFRESH = (1 << 14),
92735 +       GLAMO_MEM_DRAM1_EN_MODEREG_SET  = (1 << 15),
92736 +};
92737 +
92738 +enum glamo_reg_mem_dram2 {
92739 +       GLAMO_MEM_DRAM2_DEEP_PWRDOWN    = (1 << 12),
92740 +};
92741 +
92742 +enum glamo_irq_index {
92743 +       GLAMO_IRQIDX_HOSTBUS    = 0,
92744 +       GLAMO_IRQIDX_JPEG       = 1,
92745 +       GLAMO_IRQIDX_MPEG       = 2,
92746 +       GLAMO_IRQIDX_MPROC1     = 3,
92747 +       GLAMO_IRQIDX_MPROC0     = 4,
92748 +       GLAMO_IRQIDX_CMDQUEUE   = 5,
92749 +       GLAMO_IRQIDX_2D         = 6,
92750 +       GLAMO_IRQIDX_MMC        = 7,
92751 +       GLAMO_IRQIDX_RISC       = 8,
92752 +};
92753 +
92754 +enum glamo_irq {
92755 +       GLAMO_IRQ_HOSTBUS       = (1 << GLAMO_IRQIDX_HOSTBUS),
92756 +       GLAMO_IRQ_JPEG          = (1 << GLAMO_IRQIDX_JPEG),
92757 +       GLAMO_IRQ_MPEG          = (1 << GLAMO_IRQIDX_MPEG),
92758 +       GLAMO_IRQ_MPROC1        = (1 << GLAMO_IRQIDX_MPROC1),
92759 +       GLAMO_IRQ_MPROC0        = (1 << GLAMO_IRQIDX_MPROC0),
92760 +       GLAMO_IRQ_CMDQUEUE      = (1 << GLAMO_IRQIDX_CMDQUEUE),
92761 +       GLAMO_IRQ_2D            = (1 << GLAMO_IRQIDX_2D),
92762 +       GLAMO_IRQ_MMC           = (1 << GLAMO_IRQIDX_MMC),
92763 +       GLAMO_IRQ_RISC          = (1 << GLAMO_IRQIDX_RISC),
92764 +};
92765 +
92766 +enum glamo_reg_clock_host {
92767 +       GLAMO_CLOCK_HOST_DG_BCLK        = 0x0001,
92768 +       GLAMO_CLOCK_HOST_DG_M0CLK       = 0x0004,
92769 +       GLAMO_CLOCK_HOST_RESET          = 0x1000,
92770 +};
92771 +
92772 +enum glamo_reg_clock_mem {
92773 +       GLAMO_CLOCK_MEM_DG_M1CLK        = 0x0001,
92774 +       GLAMO_CLOCK_MEM_EN_M1CLK        = 0x0002,
92775 +       GLAMO_CLOCK_MEM_DG_MOCACLK      = 0x0004,
92776 +       GLAMO_CLOCK_MEM_EN_MOCACLK      = 0x0008,
92777 +       GLAMO_CLOCK_MEM_RESET           = 0x1000,
92778 +       GLAMO_CLOCK_MOCA_RESET          = 0x2000,
92779 +};
92780 +
92781 +enum glamo_reg_clock_lcd {
92782 +       GLAMO_CLOCK_LCD_DG_DCLK         = 0x0001,
92783 +       GLAMO_CLOCK_LCD_EN_DCLK         = 0x0002,
92784 +       GLAMO_CLOCK_LCD_DG_DMCLK        = 0x0004,
92785 +       GLAMO_CLOCK_LCD_EN_DMCLK        = 0x0008,
92786 +       //
92787 +       GLAMO_CLOCK_LCD_EN_DHCLK        = 0x0020,
92788 +       GLAMO_CLOCK_LCD_DG_M5CLK        = 0x0040,
92789 +       GLAMO_CLOCK_LCD_EN_M5CLK        = 0x0080,
92790 +       GLAMO_CLOCK_LCD_RESET           = 0x1000,
92791 +};
92792 +
92793 +enum glamo_reg_clock_mmc {
92794 +       GLAMO_CLOCK_MMC_DG_TCLK         = 0x0001,
92795 +       GLAMO_CLOCK_MMC_EN_TCLK         = 0x0002,
92796 +       GLAMO_CLOCK_MMC_DG_M9CLK        = 0x0004,
92797 +       GLAMO_CLOCK_MMC_EN_M9CLK        = 0x0008,
92798 +       GLAMO_CLOCK_MMC_RESET           = 0x1000,
92799 +};
92800 +
92801 +enum glamo_reg_basic_mmc {
92802 +       /* set to disable CRC error rejection */
92803 +       GLAMO_BASIC_MMC_DISABLE_CRC     = 0x0001,
92804 +       /* enable completion interrupt */
92805 +       GLAMO_BASIC_MMC_EN_COMPL_INT    = 0x0002,
92806 +       /* stop MMC clock while enforced idle waiting for data from card */
92807 +       GLAMO_BASIC_MMC_NO_CLK_RD_WAIT  = 0x0004,
92808 +       /* 0 = 1-bit bus to card, 1 = use 4-bit bus (has to be negotiated) */
92809 +       GLAMO_BASIC_MMC_EN_4BIT_DATA    = 0x0008,
92810 +       /* enable 75K pullups on D3..D0 */
92811 +       GLAMO_BASIC_MMC_EN_DATA_PUPS    = 0x0010,
92812 +       /* enable 75K pullup on CMD */
92813 +       GLAMO_BASIC_MMC_EN_CMD_PUP      = 0x0020,
92814 +       /* IO drive strength 00=weak -> 11=strongest */
92815 +       GLAMO_BASIC_MMC_EN_DR_STR0      = 0x0040,
92816 +       GLAMO_BASIC_MMC_EN_DR_STR1      = 0x0080,
92817 +       /* TCLK delay stage A, 0000 = 500ps --> 1111 = 8ns */
92818 +       GLAMO_BASIC_MMC_EN_TCLK_DLYA0   = 0x0100,
92819 +       GLAMO_BASIC_MMC_EN_TCLK_DLYA1   = 0x0200,
92820 +       GLAMO_BASIC_MMC_EN_TCLK_DLYA2   = 0x0400,
92821 +       GLAMO_BASIC_MMC_EN_TCLK_DLYA3   = 0x0800,
92822 +       /* TCLK delay stage B (cumulative), 0000 = 500ps --> 1111 = 8ns */
92823 +       GLAMO_BASIC_MMC_EN_TCLK_DLYB0   = 0x1000,
92824 +       GLAMO_BASIC_MMC_EN_TCLK_DLYB1   = 0x2000,
92825 +       GLAMO_BASIC_MMC_EN_TCLK_DLYB2   = 0x4000,
92826 +       GLAMO_BASIC_MMC_EN_TCLK_DLYB3   = 0x8000,
92827 +};
92828 +
92829 +enum glamo_reg_stat1_mmc {
92830 +       /* command "counter" (really: toggle) */
92831 +       GLAMO_STAT1_MMC_CMD_CTR = 0x8000,
92832 +       /* engine is idle */
92833 +       GLAMO_STAT1_MMC_IDLE    = 0x4000,
92834 +       /* readback response is ready */
92835 +       GLAMO_STAT1_MMC_RB_RRDY = 0x0200,
92836 +       /* readback data is ready */
92837 +       GLAMO_STAT1_MMC_RB_DRDY = 0x0100,
92838 +       /* no response timeout */
92839 +       GLAMO_STAT1_MMC_RTOUT   = 0x0020,
92840 +       /* no data timeout */
92841 +       GLAMO_STAT1_MMC_DTOUT   = 0x0010,
92842 +       /* CRC error on block write */
92843 +       GLAMO_STAT1_MMC_BWERR   = 0x0004,
92844 +       /* CRC error on block read */
92845 +       GLAMO_STAT1_MMC_BRERR   = 0x0002
92846 +};
92847 +
92848 +enum glamo_reg_fire_mmc {
92849 +       /* command "counter" (really: toggle)
92850 +        * the STAT1 register reflects this so you can ensure you don't look
92851 +        * at status for previous command
92852 +        */
92853 +       GLAMO_FIRE_MMC_CMD_CTR  = 0x8000,
92854 +       /* sets kind of response expected */
92855 +       GLAMO_FIRE_MMC_RES_MASK = 0x0700,
92856 +       /* sets command type */
92857 +       GLAMO_FIRE_MMC_TYP_MASK = 0x00C0,
92858 +       /* sets command class */
92859 +       GLAMO_FIRE_MMC_CLS_MASK = 0x000F,
92860 +};
92861 +
92862 +enum glamo_fire_mmc_response_types {
92863 +       GLAMO_FIRE_MMC_RSPT_R1  = 0x0000,
92864 +       GLAMO_FIRE_MMC_RSPT_R1b = 0x0100,
92865 +       GLAMO_FIRE_MMC_RSPT_R2  = 0x0200,
92866 +       GLAMO_FIRE_MMC_RSPT_R3  = 0x0300,
92867 +       GLAMO_FIRE_MMC_RSPT_R4  = 0x0400,
92868 +       GLAMO_FIRE_MMC_RSPT_R5  = 0x0500,
92869 +};
92870 +
92871 +enum glamo_fire_mmc_command_types {
92872 +       /* broadcast, no response */
92873 +       GLAMO_FIRE_MMC_CMDT_BNR = 0x0000,
92874 +       /* broadcast, with response */
92875 +       GLAMO_FIRE_MMC_CMDT_BR  = 0x0040,
92876 +       /* addressed, no data */
92877 +       GLAMO_FIRE_MMC_CMDT_AND = 0x0080,
92878 +       /* addressed, with data */
92879 +       GLAMO_FIRE_MMC_CMDT_AD  = 0x00C0,
92880 +};
92881 +
92882 +enum glamo_fire_mmc_command_class {
92883 +       /* "Stream Read" */
92884 +       GLAMO_FIRE_MMC_CC_STRR  = 0x0000,
92885 +       /* Single Block Read */
92886 +       GLAMO_FIRE_MMC_CC_SBR   = 0x0001,
92887 +       /* Multiple Block Read With Stop */
92888 +       GLAMO_FIRE_MMC_CC_MBRS  = 0x0002,
92889 +       /* Multiple Block Read No Stop */
92890 +       GLAMO_FIRE_MMC_CC_MBRNS = 0x0003,
92891 +       /* RESERVED for "Stream Write" */
92892 +       GLAMO_FIRE_MMC_CC_STRW  = 0x0004,
92893 +       /* "Stream Write" */
92894 +       GLAMO_FIRE_MMC_CC_SBW   = 0x0005,
92895 +       /* RESERVED for Multiple Block Write With Stop */
92896 +       GLAMO_FIRE_MMC_CC_MBWS  = 0x0006,
92897 +       /* Multiple Block Write No Stop */
92898 +       GLAMO_FIRE_MMC_CC_MBWNS = 0x0007,
92899 +       /* STOP command */
92900 +       GLAMO_FIRE_MMC_CC_STOP  = 0x0008,
92901 +       /* Cancel on Running Command */
92902 +       GLAMO_FIRE_MMC_CC_CANCL = 0x0009,
92903 +       /* "Basic Command" */
92904 +       GLAMO_FIRE_MMC_CC_BASIC = 0x000a,
92905 +};
92906 +
92907 +/* these are offsets from the start of the MMC register region */
92908 +enum glamo_register_mmc {
92909 +       /* MMC command, b15..8 = cmd arg b7..0; b7..1 = CRC; b0 = end bit */
92910 +       GLAMO_REG_MMC_CMD_REG1  = 0x00,
92911 +       /* MMC command, b15..0 = cmd arg b23 .. 8 */
92912 +       GLAMO_REG_MMC_CMD_REG2  = 0x02,
92913 +       /* MMC command, b15=start, b14=transmission,
92914 +        * b13..8=cmd idx, b7..0=cmd arg b31..24
92915 +        */
92916 +       GLAMO_REG_MMC_CMD_REG3  = 0x04,
92917 +       GLAMO_REG_MMC_CMD_FIRE  = 0x06,
92918 +       GLAMO_REG_MMC_CMD_RSP1  = 0x10,
92919 +       GLAMO_REG_MMC_CMD_RSP2  = 0x12,
92920 +       GLAMO_REG_MMC_CMD_RSP3  = 0x14,
92921 +       GLAMO_REG_MMC_CMD_RSP4  = 0x16,
92922 +       GLAMO_REG_MMC_CMD_RSP5  = 0x18,
92923 +       GLAMO_REG_MMC_CMD_RSP6  = 0x1a,
92924 +       GLAMO_REG_MMC_CMD_RSP7  = 0x1c,
92925 +       GLAMO_REG_MMC_CMD_RSP8  = 0x1e,
92926 +       GLAMO_REG_MMC_RB_STAT1  = 0x20,
92927 +       GLAMO_REG_MMC_RB_BLKCNT = 0x22,
92928 +       GLAMO_REG_MMC_RB_BLKLEN = 0x24,
92929 +       GLAMO_REG_MMC_BASIC     = 0x30,
92930 +       GLAMO_REG_MMC_RDATADS1  = 0x34,
92931 +       GLAMO_REG_MMC_RDATADS2  = 0x36,
92932 +       GLAMO_REG_MMC_WDATADS1  = 0x38,
92933 +       GLAMO_REG_MMC_WDATADS2  = 0x3a,
92934 +       GLAMO_REG_MMC_DATBLKCNT = 0x3c,
92935 +       GLAMO_REG_MMC_DATBLKLEN = 0x3e,
92936 +       GLAMO_REG_MMC_TIMEOUT   = 0x40,
92937 +
92938 +};
92939 +
92940 +enum glamo_reg_clock_isp {
92941 +       GLAMO_CLOCK_ISP_DG_I1CLK        = 0x0001,
92942 +       GLAMO_CLOCK_ISP_EN_I1CLK        = 0x0002,
92943 +       GLAMO_CLOCK_ISP_DG_CCLK         = 0x0004,
92944 +       GLAMO_CLOCK_ISP_EN_CCLK         = 0x0008,
92945 +       //
92946 +       GLAMO_CLOCK_ISP_EN_SCLK         = 0x0020,
92947 +       GLAMO_CLOCK_ISP_DG_M2CLK        = 0x0040,
92948 +       GLAMO_CLOCK_ISP_EN_M2CLK        = 0x0080,
92949 +       GLAMO_CLOCK_ISP_DG_M15CLK       = 0x0100,
92950 +       GLAMO_CLOCK_ISP_EN_M15CLK       = 0x0200,
92951 +       GLAMO_CLOCK_ISP1_RESET          = 0x1000,
92952 +       GLAMO_CLOCK_ISP2_RESET          = 0x2000,
92953 +};
92954 +
92955 +enum glamo_reg_clock_jpeg {
92956 +       GLAMO_CLOCK_JPEG_DG_JCLK        = 0x0001,
92957 +       GLAMO_CLOCK_JPEG_EN_JCLK        = 0x0002,
92958 +       GLAMO_CLOCK_JPEG_DG_M3CLK       = 0x0004,
92959 +       GLAMO_CLOCK_JPEG_EN_M3CLK       = 0x0008,
92960 +       GLAMO_CLOCK_JPEG_RESET          = 0x1000,
92961 +};
92962 +
92963 +enum glamo_reg_clock_2d {
92964 +       GLAMO_CLOCK_2D_DG_GCLK          = 0x0001,
92965 +       GLAMO_CLOCK_2D_EN_GCLK          = 0x0002,
92966 +       GLAMO_CLOCK_2D_DG_M7CLK         = 0x0004,
92967 +       GLAMO_CLOCK_2D_EN_M7CLK         = 0x0008,
92968 +       GLAMO_CLOCK_2D_DG_M6CLK         = 0x0010,
92969 +       GLAMO_CLOCK_2D_EN_M6CLK         = 0x0020,
92970 +       GLAMO_CLOCK_2D_RESET            = 0x1000,
92971 +       GLAMO_CLOCK_2D_CQ_RESET         = 0x2000,
92972 +};
92973 +
92974 +enum glamo_reg_clock_3d {
92975 +       GLAMO_CLOCK_3D_DG_ECLK          = 0x0001,
92976 +       GLAMO_CLOCK_3D_EN_ECLK          = 0x0002,
92977 +       GLAMO_CLOCK_3D_DG_RCLK          = 0x0004,
92978 +       GLAMO_CLOCK_3D_EN_RCLK          = 0x0008,
92979 +       GLAMO_CLOCK_3D_DG_M8CLK         = 0x0010,
92980 +       GLAMO_CLOCK_3D_EN_M8CLK         = 0x0020,
92981 +       GLAMO_CLOCK_3D_BACK_RESET       = 0x1000,
92982 +       GLAMO_CLOCK_3D_FRONT_RESET      = 0x2000,
92983 +};
92984 +
92985 +enum glamo_reg_clock_mpeg {
92986 +       GLAMO_CLOCK_MPEG_DG_X0CLK       = 0x0001,
92987 +       GLAMO_CLOCK_MPEG_EN_X0CLK       = 0x0002,
92988 +       GLAMO_CLOCK_MPEG_DG_X1CLK       = 0x0004,
92989 +       GLAMO_CLOCK_MPEG_EN_X1CLK       = 0x0008,
92990 +       GLAMO_CLOCK_MPEG_DG_X2CLK       = 0x0010,
92991 +       GLAMO_CLOCK_MPEG_EN_X2CLK       = 0x0020,
92992 +       GLAMO_CLOCK_MPEG_DG_X3CLK       = 0x0040,
92993 +       GLAMO_CLOCK_MPEG_EN_X3CLK       = 0x0080,
92994 +       GLAMO_CLOCK_MPEG_DG_X4CLK       = 0x0100,
92995 +       GLAMO_CLOCK_MPEG_EN_X4CLK       = 0x0200,
92996 +       GLAMO_CLOCK_MPEG_DG_X6CLK       = 0x0400,
92997 +       GLAMO_CLOCK_MPEG_EN_X6CLK       = 0x0800,
92998 +       GLAMO_CLOCK_MPEG_ENC_RESET      = 0x1000,
92999 +       GLAMO_CLOCK_MPEG_DEC_RESET      = 0x2000,
93000 +};
93001 +
93002 +enum glamo_reg_clock51 {
93003 +       GLAMO_CLOCK_GEN51_EN_DIV_MCLK   = 0x0001,
93004 +       GLAMO_CLOCK_GEN51_EN_DIV_SCLK   = 0x0002,
93005 +       GLAMO_CLOCK_GEN51_EN_DIV_JCLK   = 0x0004,
93006 +       GLAMO_CLOCK_GEN51_EN_DIV_DCLK   = 0x0008,
93007 +       GLAMO_CLOCK_GEN51_EN_DIV_DMCLK  = 0x0010,
93008 +       GLAMO_CLOCK_GEN51_EN_DIV_DHCLK  = 0x0020,
93009 +       GLAMO_CLOCK_GEN51_EN_DIV_GCLK   = 0x0040,
93010 +       GLAMO_CLOCK_GEN51_EN_DIV_TCLK   = 0x0080,
93011 +       /* FIXME: higher bits */
93012 +};
93013 +
93014 +enum glamo_reg_hostbus2 {
93015 +       GLAMO_HOSTBUS2_MMIO_EN_ISP      = 0x0001,
93016 +       GLAMO_HOSTBUS2_MMIO_EN_JPEG     = 0x0002,
93017 +       GLAMO_HOSTBUS2_MMIO_EN_MPEG     = 0x0004,
93018 +       GLAMO_HOSTBUS2_MMIO_EN_LCD      = 0x0008,
93019 +       GLAMO_HOSTBUS2_MMIO_EN_MMC      = 0x0010,
93020 +       GLAMO_HOSTBUS2_MMIO_EN_MICROP0  = 0x0020,
93021 +       GLAMO_HOSTBUS2_MMIO_EN_MICROP1  = 0x0040,
93022 +       GLAMO_HOSTBUS2_MMIO_EN_CQ       = 0x0080,
93023 +       GLAMO_HOSTBUS2_MMIO_EN_RISC     = 0x0100,
93024 +       GLAMO_HOSTBUS2_MMIO_EN_2D       = 0x0200,
93025 +       GLAMO_HOSTBUS2_MMIO_EN_3D       = 0x0400,
93026 +};
93027 +
93028 +/* LCD Controller */
93029 +
93030 +#define REG_LCD(x)     (x)
93031 +enum glamo_reg_lcd {
93032 +       GLAMO_REG_LCD_MODE1             = REG_LCD(0x00),
93033 +       GLAMO_REG_LCD_MODE2             = REG_LCD(0x02),
93034 +       GLAMO_REG_LCD_MODE3             = REG_LCD(0x04),
93035 +       GLAMO_REG_LCD_WIDTH             = REG_LCD(0x06),
93036 +       GLAMO_REG_LCD_HEIGHT            = REG_LCD(0x08),
93037 +       GLAMO_REG_LCD_POLARITY          = REG_LCD(0x0a),
93038 +       GLAMO_REG_LCD_A_BASE1           = REG_LCD(0x0c),
93039 +       GLAMO_REG_LCD_A_BASE2           = REG_LCD(0x0e),
93040 +       GLAMO_REG_LCD_B_BASE1           = REG_LCD(0x10),
93041 +       GLAMO_REG_LCD_B_BASE2           = REG_LCD(0x12),
93042 +       GLAMO_REG_LCD_C_BASE1           = REG_LCD(0x14),
93043 +       GLAMO_REG_LCD_C_BASE2           = REG_LCD(0x16),
93044 +       GLAMO_REG_LCD_PITCH             = REG_LCD(0x18),
93045 +       /* RES */
93046 +       GLAMO_REG_LCD_HORIZ_TOTAL       = REG_LCD(0x1c),
93047 +       /* RES */
93048 +       GLAMO_REG_LCD_HORIZ_RETR_START  = REG_LCD(0x20),
93049 +       /* RES */
93050 +       GLAMO_REG_LCD_HORIZ_RETR_END    = REG_LCD(0x24),
93051 +       /* RES */
93052 +       GLAMO_REG_LCD_HORIZ_DISP_START  = REG_LCD(0x28),
93053 +       /* RES */
93054 +       GLAMO_REG_LCD_HORIZ_DISP_END    = REG_LCD(0x2c),
93055 +       /* RES */
93056 +       GLAMO_REG_LCD_VERT_TOTAL        = REG_LCD(0x30),
93057 +       /* RES */
93058 +       GLAMO_REG_LCD_VERT_RETR_START   = REG_LCD(0x34),
93059 +       /* RES */
93060 +       GLAMO_REG_LCD_VERT_RETR_END     = REG_LCD(0x38),
93061 +       /* RES */
93062 +       GLAMO_REG_LCD_VERT_DISP_START   = REG_LCD(0x3c),
93063 +       /* RES */
93064 +       GLAMO_REG_LCD_VERT_DISP_END     = REG_LCD(0x40),
93065 +       /* RES */
93066 +       GLAMO_REG_LCD_POL               = REG_LCD(0x44),
93067 +       GLAMO_REG_LCD_DATA_START        = REG_LCD(0x46),
93068 +       GLAMO_REG_LCD_FRATE_CONTRO      = REG_LCD(0x48),
93069 +       GLAMO_REG_LCD_DATA_CMD_HDR      = REG_LCD(0x4a),
93070 +       GLAMO_REG_LCD_SP_START          = REG_LCD(0x4c),
93071 +       GLAMO_REG_LCD_SP_END            = REG_LCD(0x4e),
93072 +       GLAMO_REG_LCD_CURSOR_BASE1      = REG_LCD(0x50),
93073 +       GLAMO_REG_LCD_CURSOR_BASE2      = REG_LCD(0x52),
93074 +       GLAMO_REG_LCD_CURSOR_PITCH      = REG_LCD(0x54),
93075 +       GLAMO_REG_LCD_CURSOR_X_SIZE     = REG_LCD(0x56),
93076 +       GLAMO_REG_LCD_CURSOR_Y_SIZE     = REG_LCD(0x58),
93077 +       GLAMO_REG_LCD_CURSOR_X_POS      = REG_LCD(0x5a),
93078 +       GLAMO_REG_LCD_CURSOR_Y_POS      = REG_LCD(0x5c),
93079 +       GLAMO_REG_LCD_CURSOR_PRESET     = REG_LCD(0x5e),
93080 +       GLAMO_REG_LCD_CURSOR_FG_COLOR   = REG_LCD(0x60),
93081 +       /* RES */
93082 +       GLAMO_REG_LCD_CURSOR_BG_COLOR   = REG_LCD(0x64),
93083 +       /* RES */
93084 +       GLAMO_REG_LCD_CURSOR_DST_COLOR  = REG_LCD(0x68),
93085 +       /* RES */
93086 +       GLAMO_REG_LCD_STATUS1           = REG_LCD(0x80),
93087 +       GLAMO_REG_LCD_STATUS2           = REG_LCD(0x82),
93088 +       GLAMO_REG_LCD_STATUS3           = REG_LCD(0x84),
93089 +       GLAMO_REG_LCD_STATUS4           = REG_LCD(0x86),
93090 +       /* RES */
93091 +       GLAMO_REG_LCD_COMMAND1          = REG_LCD(0xa0),
93092 +       GLAMO_REG_LCD_COMMAND2          = REG_LCD(0xa2),
93093 +       /* RES */
93094 +       GLAMO_REG_LCD_WFORM_DELAY1      = REG_LCD(0xb0),
93095 +       GLAMO_REG_LCD_WFORM_DELAY2      = REG_LCD(0xb2),
93096 +       /* RES */
93097 +       GLAMO_REG_LCD_GAMMA_CORR        = REG_LCD(0x100),
93098 +       /* RES */
93099 +       GLAMO_REG_LCD_GAMMA_R_ENTRY01   = REG_LCD(0x110),
93100 +       GLAMO_REG_LCD_GAMMA_R_ENTRY23   = REG_LCD(0x112),
93101 +       GLAMO_REG_LCD_GAMMA_R_ENTRY45   = REG_LCD(0x114),
93102 +       GLAMO_REG_LCD_GAMMA_R_ENTRY67   = REG_LCD(0x116),
93103 +       GLAMO_REG_LCD_GAMMA_R_ENTRY8    = REG_LCD(0x118),
93104 +       /* RES */
93105 +       GLAMO_REG_LCD_GAMMA_G_ENTRY01   = REG_LCD(0x130),
93106 +       GLAMO_REG_LCD_GAMMA_G_ENTRY23   = REG_LCD(0x132),
93107 +       GLAMO_REG_LCD_GAMMA_G_ENTRY45   = REG_LCD(0x134),
93108 +       GLAMO_REG_LCD_GAMMA_G_ENTRY67   = REG_LCD(0x136),
93109 +       GLAMO_REG_LCD_GAMMA_G_ENTRY8    = REG_LCD(0x138),
93110 +       /* RES */
93111 +       GLAMO_REG_LCD_GAMMA_B_ENTRY01   = REG_LCD(0x150),
93112 +       GLAMO_REG_LCD_GAMMA_B_ENTRY23   = REG_LCD(0x152),
93113 +       GLAMO_REG_LCD_GAMMA_B_ENTRY45   = REG_LCD(0x154),
93114 +       GLAMO_REG_LCD_GAMMA_B_ENTRY67   = REG_LCD(0x156),
93115 +       GLAMO_REG_LCD_GAMMA_B_ENTRY8    = REG_LCD(0x158),
93116 +       /* RES */
93117 +       GLAMO_REG_LCD_SRAM_DRIVING1     = REG_LCD(0x160),
93118 +       GLAMO_REG_LCD_SRAM_DRIVING2     = REG_LCD(0x162),
93119 +       GLAMO_REG_LCD_SRAM_DRIVING3     = REG_LCD(0x164),
93120 +};
93121 +
93122 +enum glamo_reg_lcd_mode1 {
93123 +       GLAMO_LCD_MODE1_PWRSAVE         = 0x0001,
93124 +       GLAMO_LCD_MODE1_PARTIAL_PRT     = 0x0002,
93125 +       GLAMO_LCD_MODE1_HWFLIP          = 0x0004,
93126 +       GLAMO_LCD_MODE1_LCD2            = 0x0008,
93127 +       /* RES */
93128 +       GLAMO_LCD_MODE1_PARTIAL_MODE    = 0x0020,
93129 +       GLAMO_LCD_MODE1_CURSOR_DSTCOLOR = 0x0040,
93130 +       GLAMO_LCD_MODE1_PARTIAL_ENABLE  = 0x0080,
93131 +       GLAMO_LCD_MODE1_TVCLK_IN_ENABLE = 0x0100,
93132 +       GLAMO_LCD_MODE1_HSYNC_HIGH_ACT  = 0x0200,
93133 +       GLAMO_LCD_MODE1_VSYNC_HIGH_ACT  = 0x0400,
93134 +       GLAMO_LCD_MODE1_HSYNC_FLIP      = 0x0800,
93135 +       GLAMO_LCD_MODE1_GAMMA_COR_EN    = 0x1000,
93136 +       GLAMO_LCD_MODE1_DITHER_EN       = 0x2000,
93137 +       GLAMO_LCD_MODE1_CURSOR_EN       = 0x4000,
93138 +       GLAMO_LCD_MODE1_ROTATE_EN       = 0x8000,
93139 +};
93140 +
93141 +enum glamo_reg_lcd_mode2 {
93142 +       GLAMO_LCD_MODE2_CRC_CHECK_EN    = 0x0001,
93143 +       GLAMO_LCD_MODE2_DCMD_PER_LINE   = 0x0002,
93144 +       GLAMO_LCD_MODE2_NOUSE_BDEF      = 0x0004,
93145 +       GLAMO_LCD_MODE2_OUT_POS_MODE    = 0x0008,
93146 +       GLAMO_LCD_MODE2_FRATE_CTRL_EN   = 0x0010,
93147 +       GLAMO_LCD_MODE2_SINGLE_BUFFER   = 0x0020,
93148 +       GLAMO_LCD_MODE2_SER_LSB_TO_MSB  = 0x0040,
93149 +       /* FIXME */
93150 +};
93151 +
93152 +enum glamo_reg_lcd_mode3 {
93153 +       /* LCD color source data format */
93154 +       GLAMO_LCD_SRC_RGB565            = 0x0000,
93155 +       GLAMO_LCD_SRC_ARGB1555          = 0x4000,
93156 +       GLAMO_LCD_SRC_ARGB4444          = 0x8000,
93157 +       /* interface type */
93158 +       GLAMO_LCD_MODE3_LCD             = 0x1000,
93159 +       GLAMO_LCD_MODE3_RGB             = 0x0800,
93160 +       GLAMO_LCD_MODE3_CPU             = 0x0000,
93161 +       /* mode */
93162 +       GLAMO_LCD_MODE3_RGB332          = 0x0000,
93163 +       GLAMO_LCD_MODE3_RGB444          = 0x0100,
93164 +       GLAMO_LCD_MODE3_RGB565          = 0x0200,
93165 +       GLAMO_LCD_MODE3_RGB666          = 0x0300,
93166 +       /* depth */
93167 +       GLAMO_LCD_MODE3_6BITS           = 0x0000,
93168 +       GLAMO_LCD_MODE3_8BITS           = 0x0010,
93169 +       GLAMO_LCD_MODE3_9BITS           = 0x0020,
93170 +       GLAMO_LCD_MODE3_16BITS          = 0x0030,
93171 +       GLAMO_LCD_MODE3_18BITS          = 0x0040,
93172 +};
93173 +
93174 +enum glamo_lcd_rot_mode {
93175 +        GLAMO_LCD_ROT_MODE_0            = 0x0000,
93176 +        GLAMO_LCD_ROT_MODE_180          = 0x2000,
93177 +        GLAMO_LCD_ROT_MODE_MIRROR       = 0x4000,
93178 +        GLAMO_LCD_ROT_MODE_FLIP         = 0x6000,
93179 +        GLAMO_LCD_ROT_MODE_90           = 0x8000,
93180 +        GLAMO_LCD_ROT_MODE_270          = 0xa000,
93181 +};
93182 +#define GLAMO_LCD_ROT_MODE_MASK         0xe000
93183 +
93184 +enum glamo_lcd_cmd_type {
93185 +       GLAMO_LCD_CMD_TYPE_DISP         = 0x0000,
93186 +       GLAMO_LCD_CMD_TYPE_PARALLEL     = 0x4000,
93187 +       GLAMO_LCD_CMD_TYPE_SERIAL       = 0x8000,
93188 +       GLAMO_LCD_CMD_TYPE_SERIAL_DIRECT= 0xc000,
93189 +};
93190 +#define GLAMO_LCD_CMD_TYPE_MASK                0xc000
93191 +
93192 +enum glamo_lcd_cmds {
93193 +       GLAMO_LCD_CMD_DATA_DISP_FIRE    = 0x00,
93194 +       GLAMO_LCD_CMD_DATA_DISP_SYNC    = 0x01,         /* RGB only */
93195 +       /* switch to command mode, no display */
93196 +       GLAMO_LCD_CMD_DATA_FIRE_NO_DISP = 0x02,
93197 +       /* display until VSYNC, switch to command */
93198 +       GLAMO_LCD_CMD_DATA_FIRE_VSYNC   = 0x11,
93199 +       /* display until HSYNC, switch to command */
93200 +       GLAMO_LCD_CMD_DATA_FIRE_HSYNC   = 0x12,
93201 +       /* display until VSYNC, 1 black frame, VSYNC, switch to command */
93202 +       GLAMO_LCD_CMD_DATA_FIRE_VSYNC_B = 0x13,
93203 +       /* don't care about display and switch to command */
93204 +       GLAMO_LCD_CMD_DATA_FIRE_FREE    = 0x14,         /* RGB only */
93205 +       /* don't care about display, keep data display but disable data,
93206 +        * and switch to command */
93207 +       GLAMO_LCD_CMD_DATA_FIRE_FREE_D  = 0x15,         /* RGB only */
93208 +};
93209 +
93210 +enum glamo_core_revisions {
93211 +       GLAMO_CORE_REV_A0               = 0x0000,
93212 +       GLAMO_CORE_REV_A1               = 0x0001,
93213 +       GLAMO_CORE_REV_A2               = 0x0002,
93214 +       GLAMO_CORE_REV_A3               = 0x0003,
93215 +};
93216 +
93217 +#endif /* _GLAMO_REGS_H */
93218 --- /dev/null
93219 +++ b/drivers/mfd/glamo/glamo-spi-gpio.c
93220 @@ -0,0 +1,288 @@
93221 +/*
93222 + * Copyright (C) 2007 Openmoko, Inc.
93223 + * Author: Harald Welte <laforge@openmoko.org>
93224 + *
93225 + * Smedia Glamo GPIO based SPI driver
93226 + *
93227 + * This program is free software; you can redistribute it and/or modify
93228 + * it under the terms of the GNU General Public License version 2 as
93229 + * published by the Free Software Foundation.
93230 + *
93231 + * This driver currently only implements a minimum subset of the hardware
93232 + * features, esp. those features that are required to drive the jbt6k74
93233 + * LCM controller asic in the TD028TTEC1 LCM.
93234 + *
93235 +*/
93236 +
93237 +#define DEBUG
93238 +
93239 +#include <linux/kernel.h>
93240 +#include <linux/init.h>
93241 +#include <linux/delay.h>
93242 +#include <linux/device.h>
93243 +#include <linux/spinlock.h>
93244 +#include <linux/workqueue.h>
93245 +#include <linux/platform_device.h>
93246 +
93247 +#include <linux/spi/spi.h>
93248 +#include <linux/spi/spi_bitbang.h>
93249 +#include <linux/spi/glamo.h>
93250 +
93251 +#include <linux/glamofb.h>
93252 +
93253 +#include <mach/hardware.h>
93254 +
93255 +#include "glamo-core.h"
93256 +#include "glamo-regs.h"
93257 +
93258 +struct glamo_spigpio {
93259 +       struct spi_bitbang              bitbang;
93260 +       struct spi_master               *master;
93261 +       struct glamo_spigpio_info       *info;
93262 +       struct glamo_core               *glamo;
93263 +};
93264 +
93265 +static inline struct glamo_spigpio *to_sg(struct spi_device *spi)
93266 +{
93267 +       return spi->controller_data;
93268 +}
93269 +
93270 +static inline void setsck(struct spi_device *dev, int on)
93271 +{
93272 +       struct glamo_spigpio *sg = to_sg(dev);
93273 +       glamo_gpio_setpin(sg->glamo, sg->info->pin_clk, on ? 1 : 0);
93274 +}
93275 +
93276 +static inline void setmosi(struct spi_device *dev, int on)
93277 +{
93278 +       struct glamo_spigpio *sg = to_sg(dev);
93279 +       glamo_gpio_setpin(sg->glamo, sg->info->pin_mosi, on ? 1 : 0);
93280 +}
93281 +
93282 +static inline u32 getmiso(struct spi_device *dev)
93283 +{
93284 +       struct glamo_spigpio *sg = to_sg(dev);
93285 +       if (sg->info->pin_miso)
93286 +               return glamo_gpio_getpin(sg->glamo, sg->info->pin_miso) ? 1 : 0;
93287 +       else
93288 +               return 0;
93289 +}
93290 +
93291 +#define spidelay(x) ndelay(x)
93292 +
93293 +#define EXPAND_BITBANG_TXRX
93294 +#include <linux/spi/spi_bitbang.h>
93295 +
93296 +static u32 glamo_spigpio_txrx_mode0(struct spi_device *spi,
93297 +                                   unsigned nsecs, u32 word, u8 bits)
93298 +{
93299 +       return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits);
93300 +}
93301 +
93302 +static u32 glamo_spigpio_txrx_mode1(struct spi_device *spi,
93303 +                                   unsigned nsecs, u32 word, u8 bits)
93304 +{
93305 +       return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, bits);
93306 +}
93307 +
93308 +static u32 glamo_spigpio_txrx_mode2(struct spi_device *spi,
93309 +                                   unsigned nsecs, u32 word, u8 bits)
93310 +{
93311 +       return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, bits);
93312 +}
93313 +
93314 +static u32 glamo_spigpio_txrx_mode3(struct spi_device *spi,
93315 +                                   unsigned nsecs, u32 word, u8 bits)
93316 +{
93317 +       return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, bits);
93318 +}
93319 +
93320 +
93321 +#if 0
93322 +static int glamo_spigpio_setupxfer(struct spi_device *spi,
93323 +                                  struct spi_transfer *t)
93324 +{
93325 +       struct glamo_spi *gs = to_sg(spi);
93326 +       unsigned int bpw;
93327 +
93328 +       bpw = t ? t->bits_per_word : spi->bits_per_word;
93329 +
93330 +       if (bpw != 9 && bpw != 8) {
93331 +               dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
93332 +               return -EINVAL;
93333 +       }
93334 +
93335 +       return 0;
93336 +}
93337 +#endif
93338 +
93339 +static void glamo_spigpio_chipsel(struct spi_device *spi, int value)
93340 +{
93341 +       struct glamo_spigpio *gs = to_sg(spi);
93342 +#if 0
93343 +       dev_dbg(&spi->dev, "chipsel %d: spi=%p, gs=%p, info=%p, handle=%p\n",
93344 +               value, spi, gs, gs->info, gs->info->glamo);
93345 +#endif
93346 +       glamo_gpio_setpin(gs->glamo, gs->info->pin_cs, value ? 0 : 1);
93347 +}
93348 +
93349 +
93350 +static int glamo_spigpio_probe(struct platform_device *pdev)
93351 +{
93352 +       struct spi_master *master;
93353 +       struct glamo_spigpio *sp;
93354 +       int ret;
93355 +       int i;
93356 +
93357 +       master = spi_alloc_master(&pdev->dev, sizeof(struct glamo_spigpio));
93358 +       if (master == NULL) {
93359 +               dev_err(&pdev->dev, "failed to allocate spi master\n");
93360 +               ret = -ENOMEM;
93361 +               goto err;
93362 +       }
93363 +
93364 +       sp = spi_master_get_devdata(master);
93365 +       platform_set_drvdata(pdev, sp);
93366 +       sp->info = pdev->dev.platform_data;
93367 +       if (!sp->info) {
93368 +               dev_err(&pdev->dev, "can't operate without platform data\n");
93369 +               ret = -EIO;
93370 +               goto err_no_pdev;
93371 +       }
93372 +
93373 +       master->num_chipselect = 1;
93374 +       master->bus_num = 2; /* FIXME: use dynamic number */
93375 +
93376 +       sp->master = spi_master_get(master);
93377 +       sp->glamo = sp->info->glamo;
93378 +
93379 +       sp->bitbang.master = sp->master;
93380 +       sp->bitbang.chipselect = glamo_spigpio_chipsel;
93381 +       sp->bitbang.txrx_word[SPI_MODE_0] = glamo_spigpio_txrx_mode0;
93382 +       sp->bitbang.txrx_word[SPI_MODE_1] = glamo_spigpio_txrx_mode1;
93383 +       sp->bitbang.txrx_word[SPI_MODE_2] = glamo_spigpio_txrx_mode2;
93384 +       sp->bitbang.txrx_word[SPI_MODE_3] = glamo_spigpio_txrx_mode3;
93385 +
93386 +       /* set state of spi pins */
93387 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_clk, 0);
93388 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_mosi, 0);
93389 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_cs, 1);
93390 +
93391 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_clk);
93392 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_mosi);
93393 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_cs);
93394 +       if (sp->info->pin_miso)
93395 +               glamo_gpio_cfgpin(sp->glamo, sp->info->pin_miso);
93396 +
93397 +       /* bring the LCM panel out of reset if it isn't already */
93398 +
93399 +       glamo_gpio_setpin(sp->glamo, GLAMO_GPIO4, 1);
93400 +       glamo_gpio_cfgpin(sp->glamo, GLAMO_GPIO4_OUTPUT);
93401 +       msleep(90);
93402 +
93403 +#if 0
93404 +       sp->dev = &pdev->dev;
93405 +
93406 +       sp->bitbang.setup_transfer = glamo_spi_setupxfer;
93407 +       sp->bitbang.txrx_bufs = glamo_spi_txrx;
93408 +       sp->bitbang.master->setup = glamo_spi_setup;
93409 +#endif
93410 +
93411 +       ret = spi_bitbang_start(&sp->bitbang);
93412 +       if (ret)
93413 +               goto err_no_bitbang;
93414 +
93415 +       /* register the chips to go with the board */
93416 +
93417 +       for (i = 0; i < sp->info->board_size; i++) {
93418 +               dev_info(&pdev->dev, "registering %p: %s\n",
93419 +                        &sp->info->board_info[i],
93420 +                        sp->info->board_info[i].modalias);
93421 +
93422 +               sp->info->board_info[i].controller_data = sp;
93423 +               spi_new_device(master, sp->info->board_info + i);
93424 +       }
93425 +
93426 +       return 0;
93427 +
93428 +err_no_bitbang:
93429 +       platform_set_drvdata(pdev, NULL);
93430 +err_no_pdev:
93431 +       spi_master_put(sp->bitbang.master);
93432 +err:
93433 +       return ret;
93434 +
93435 +}
93436 +
93437 +static int glamo_spigpio_remove(struct platform_device *pdev)
93438 +{
93439 +       struct glamo_spigpio *sp = platform_get_drvdata(pdev);
93440 +
93441 +       spi_bitbang_stop(&sp->bitbang);
93442 +       spi_master_put(sp->bitbang.master);
93443 +
93444 +       return 0;
93445 +}
93446 +
93447 +/*#define glamo_spigpio_suspend NULL
93448 +#define glamo_spigpio_resume NULL
93449 +*/
93450 +
93451 +
93452 +#ifdef CONFIG_PM
93453 +static int glamo_spigpio_suspend(struct platform_device *pdev, pm_message_t state)
93454 +{
93455 +       return 0;
93456 +}
93457 +
93458 +static int glamo_spigpio_resume(struct platform_device *pdev)
93459 +{
93460 +       struct glamo_spigpio *sp = platform_get_drvdata(pdev);
93461 +
93462 +       if (!sp)
93463 +               return 0;
93464 +
93465 +       /* set state of spi pins */
93466 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_clk, 0);
93467 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_mosi, 0);
93468 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_cs, 1);
93469 +
93470 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_clk);
93471 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_mosi);
93472 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_cs);
93473 +       if (sp->info->pin_miso)
93474 +               glamo_gpio_cfgpin(sp->glamo, sp->info->pin_miso);
93475 +
93476 +       return 0;
93477 +}
93478 +#endif
93479 +
93480 +static struct platform_driver glamo_spi_drv = {
93481 +       .probe          = glamo_spigpio_probe,
93482 +       .remove         = glamo_spigpio_remove,
93483 +#ifdef CONFIG_PM
93484 +       .suspend_late   = glamo_spigpio_suspend,
93485 +       .resume_early   = glamo_spigpio_resume,
93486 +#endif
93487 +       .driver         = {
93488 +               .name   = "glamo-spi-gpio",
93489 +               .owner  = THIS_MODULE,
93490 +       },
93491 +};
93492 +
93493 +static int __init glamo_spi_init(void)
93494 +{
93495 +       return platform_driver_register(&glamo_spi_drv);
93496 +}
93497 +
93498 +static void __exit glamo_spi_exit(void)
93499 +{
93500 +       platform_driver_unregister(&glamo_spi_drv);
93501 +}
93502 +
93503 +module_init(glamo_spi_init);
93504 +module_exit(glamo_spi_exit);
93505 +
93506 +MODULE_DESCRIPTION("Smedia Glamo 336x/337x LCM serial command SPI Driver");
93507 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>")
93508 +MODULE_LICENSE("GPL");
93509 --- /dev/null
93510 +++ b/drivers/mfd/glamo/Kconfig
93511 @@ -0,0 +1,44 @@
93512 +config MFD_GLAMO
93513 +       bool "Smedia Glamo 336x/337x support"
93514 +       help
93515 +         This enables the core driver for the Smedia Glamo 336x/337x
93516 +         multi-function device.  It includes irq_chip demultiplex as
93517 +         well as clock / power management and GPIO support.
93518 +
93519 +config MFD_GLAMO_FB
93520 +       tristate "Smedia Glamo 336x/337x framebuffer support"
93521 +       depends on FB && MFD_GLAMO
93522 +       help
93523 +         Frame buffer driver for the LCD controller in the Smedia Glamo
93524 +         336x/337x.
93525 +
93526 +         This driver is also available as a module ( = code which can be
93527 +         inserted and removed from the running kernel whenever you want). The
93528 +         module will be called glamofb. If you want to compile it as a module,
93529 +         say M here and read <file:Documentation/modules.txt>.
93530 +
93531 +         If unsure, say N.
93532 +
93533 +config MFD_GLAMO_SPI_GPIO
93534 +       tristate "Glamo GPIO SPI bitbang support"
93535 +       depends on MFD_GLAMO
93536 +       help
93537 +         Enable a bitbanging SPI adapter driver for the Smedia Glamo.
93538 +
93539 +config MFD_GLAMO_SPI_FB
93540 +       tristate "Glamo LCM control channel SPI support"
93541 +       depends on MFD_GLAMO_FB
93542 +       help
93543 +         Enable a bitbanging SPI adapter driver for the Smedia Glamo LCM
93544 +        control channel.  This SPI interface is frequently used to
93545 +        interconnect the LCM control interface.
93546 +
93547 +config MFD_GLAMO_MCI
93548 +       tristate "Glamo S3C SD/MMC Card Interface support"
93549 +       depends on MFD_GLAMO && MMC
93550 +       help
93551 +         This selects a driver for the MCI interface found in
93552 +         the S-Media GLAMO chip, as used in Openmoko
93553 +         neo1973 GTA-02.
93554 +
93555 +         If unsure, say N.
93556 \ No newline at end of file
93557 --- /dev/null
93558 +++ b/drivers/mfd/glamo/Makefile
93559 @@ -0,0 +1,12 @@
93560 +#
93561 +# Makefile for the Smedia Glamo framebuffer driver
93562 +#
93563 +
93564 +obj-$(CONFIG_MFD_GLAMO)                        += glamo-core.o glamo-gpio.o
93565 +obj-$(CONFIG_MFD_GLAMO_SPI)            += glamo-spi.o
93566 +obj-$(CONFIG_MFD_GLAMO_SPI_GPIO)       += glamo-spi-gpio.o
93567 +
93568 +obj-$(CONFIG_MFD_GLAMO_FB)             += glamo-fb.o
93569 +obj-$(CONFIG_MFD_GLAMO_SPI_FB)         += glamo-lcm-spi.o
93570 +obj-$(CONFIG_MFD_GLAMO_MCI)            += glamo-mci.o
93571 +
93572 --- a/drivers/mfd/Kconfig
93573 +++ b/drivers/mfd/Kconfig
93574 @@ -153,6 +153,55 @@ config MFD_WM8350_I2C
93575           I2C as the control interface.  Additional options must be
93576           selected to enable support for the functionality of the chip.
93577
93578 +config MFD_PCF50633
93579 +       tristate "Support for NXP PCF50633"
93580 +       depends on I2C
93581 +       help
93582 +         Say yes here if you have NXP PCF50633 chip on your board.
93583 +         This core driver provides register access and IRQ handling
93584 +         facilities, and registers devices for the various functions
93585 +         so that function-specific drivers can bind to them.
93586 +
93587 +
93588 +config PCF50633_ADC
93589 +       tristate "Support for NXP PCF50633 ADC"
93590 +       depends on MFD_PCF50633
93591 +       help
93592 +        Say yes here if you want to include support for ADC in the
93593 +        NXP PCF50633 chip.
93594 +
93595 +config PCF50633_GPIO
93596 +       tristate "Support for NXP PCF50633 GPIO"
93597 +       depends on MFD_PCF50633
93598 +       help
93599 +        Say yes here if you want to include support GPIO for pins on
93600 +        the PCF50633 chip.
93601 +
93602 +config MFD_PCF50606
93603 +       tristate "Support for NXP PCF50606"
93604 +       depends on I2C
93605 +       help
93606 +         Say yes here if you have NXP PCF50606 chip on your board.
93607 +         This core driver provides register access and IRQ handling
93608 +         facilities, and registers devices for the various functions
93609 +         so that function-specific drivers can bind to them.
93610 +
93611 +config PCF50606_ADC
93612 +       tristate "Support for NXP PCF50606 ADC"
93613 +       depends on MFD_PCF50606
93614 +       help
93615 +        Say yes here if you want to include support for ADC in the
93616 +        NXP PCF50606 chip.
93617 +
93618 +config PCF50606_GPO
93619 +       tristate "Support for NXP PCF50606 GPO"
93620 +       depends on MFD_PCF50606
93621 +       help
93622 +        Say yes here if you want to include support GPO for pins on
93623 +        the PCF50606 chip.
93624 +
93625 +source "drivers/mfd/glamo/Kconfig"
93626 +
93627  endmenu
93628
93629  menu "Multimedia Capabilities Port drivers"
93630 --- a/drivers/mfd/Makefile
93631 +++ b/drivers/mfd/Makefile
93632 @@ -4,6 +4,7 @@
93633
93634  obj-$(CONFIG_MFD_SM501)                += sm501.o
93635  obj-$(CONFIG_MFD_ASIC3)                += asic3.o
93636 +obj-$(CONFIG_MFD_GLAMO)                += glamo/
93637
93638  obj-$(CONFIG_HTC_EGPIO)                += htc-egpio.o
93639  obj-$(CONFIG_HTC_PASIC3)       += htc-pasic3.o
93640 @@ -31,4 +32,13 @@ obj-$(CONFIG_MCP_UCB1200)    += ucb1x00-ass
93641  endif
93642  obj-$(CONFIG_UCB1400_CORE)     += ucb1400_core.o
93643
93644 -obj-$(CONFIG_PMIC_DA903X)      += da903x.o
93645 \ No newline at end of file
93646 +obj-$(CONFIG_PMIC_DA903X)      += da903x.o
93647 +
93648 +obj-$(CONFIG_MFD_PCF50633)     += pcf50633-core.o
93649 +obj-$(CONFIG_PCF50633_ADC)     += pcf50633-adc.o
93650 +obj-$(CONFIG_PCF50633_GPIO)    += pcf50633-gpio.o
93651 +
93652 +obj-$(CONFIG_MFD_PCF50606)     += pcf50606-core.o
93653 +obj-$(CONFIG_PCF50606_ADC)     += pcf50606-adc.o
93654 +obj-$(CONFIG_PCF50606_GPO)     += pcf50606-gpo.o
93655 +
93656 --- /dev/null
93657 +++ b/drivers/mfd/pcf50606-adc.c
93658 @@ -0,0 +1,239 @@
93659 +/* Philips PCF50606 ADC Driver
93660 + *
93661 + * (C) 2006-2008 by Openmoko, Inc.
93662 + * Author: Balaji Rao <balajirrao@openmoko.org>
93663 + * All rights reserved.
93664 + *
93665 + * Broken down from monstrous PCF50606 driver mainly by
93666 + * Harald Welte, Andy Green and Werner Almesberger
93667 + *
93668 + * This program is free software; you can redistribute it and/or
93669 + * modify it under the terms of the GNU General Public License as
93670 + * published by the Free Software Foundation; either version 2 of
93671 + * the License, or (at your option) any later version.
93672 + *
93673 + * This program is distributed in the hope that it will be useful,
93674 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
93675 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
93676 + * GNU General Public License for more details.
93677 + *
93678 + * You should have received a copy of the GNU General Public License
93679 + * along with this program; if not, write to the Free Software
93680 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
93681 + * MA 02111-1307 USA
93682 + */
93683 +
93684 +#include <linux/mfd/pcf50606/core.h>
93685 +#include <linux/mfd/pcf50606/adc.h>
93686 +
93687 +struct pcf50606_adc_request {
93688 +       int mux;
93689 +       int avg;
93690 +       int result;
93691 +       void (*callback)(struct pcf50606 *, void *, int);
93692 +       void *callback_param;
93693 +
93694 +       /* Used in case of sync requests */
93695 +       struct completion completion;
93696 +
93697 +};
93698 +
93699 +static void adc_read_setup(struct pcf50606 *pcf,
93700 +                                int channel, int avg)
93701 +{
93702 +       channel &= PCF50606_ADCC2_ADCMUX_MASK;
93703 +
93704 +       /* start ADC conversion of selected channel */
93705 +       pcf50606_reg_write(pcf, PCF50606_REG_ADCC2, channel |
93706 +                   PCF50606_ADCC2_ADCSTART | PCF50606_ADCC2_RES_10BIT);
93707 +
93708 +}
93709 +
93710 +static void trigger_next_adc_job_if_any(struct pcf50606 *pcf)
93711 +{
93712 +       int head, tail;
93713 +
93714 +       mutex_lock(&pcf->adc.queue_mutex);
93715 +
93716 +       head = pcf->adc.queue_head;
93717 +       tail = pcf->adc.queue_tail;
93718 +
93719 +       if (!pcf->adc.queue[head])
93720 +               goto out;
93721 +
93722 +       adc_read_setup(pcf, pcf->adc.queue[head]->mux,
93723 +                               pcf->adc.queue[head]->avg);
93724 +out:
93725 +       mutex_unlock(&pcf->adc.queue_mutex);
93726 +}
93727 +
93728 +static int
93729 +adc_enqueue_request(struct pcf50606 *pcf, struct pcf50606_adc_request *req)
93730 +{
93731 +       int head, tail;
93732 +
93733 +       mutex_lock(&pcf->adc.queue_mutex);
93734 +       head = pcf->adc.queue_head;
93735 +       tail = pcf->adc.queue_tail;
93736 +
93737 +       if (pcf->adc.queue[tail]) {
93738 +               mutex_unlock(&pcf->adc.queue_mutex);
93739 +               return -EBUSY;
93740 +       }
93741 +
93742 +       pcf->adc.queue[tail] = req;
93743 +
93744 +       pcf->adc.queue_tail =
93745 +               (tail + 1) & (PCF50606_MAX_ADC_FIFO_DEPTH - 1);
93746 +
93747 +       mutex_unlock(&pcf->adc.queue_mutex);
93748 +
93749 +       trigger_next_adc_job_if_any(pcf);
93750 +
93751 +       return 0;
93752 +}
93753 +
93754 +static void
93755 +pcf50606_adc_sync_read_callback(struct pcf50606 *pcf, void *param, int result)
93756 +{
93757 +       struct pcf50606_adc_request *req;
93758 +
93759 +       /*We know here that the passed param is an adc_request object */
93760 +       req = (struct pcf50606_adc_request *)param;
93761 +
93762 +       req->result = result;
93763 +       complete(&req->completion);
93764 +}
93765 +
93766 +int pcf50606_adc_sync_read(struct pcf50606 *pcf, int mux, int avg)
93767 +{
93768 +
93769 +       struct pcf50606_adc_request *req;
93770 +       int result;
93771 +
93772 +       /* req is freed when the result is ready, in pcf50606_work*/
93773 +       req = kzalloc(sizeof(*req), GFP_KERNEL);
93774 +       if (!req)
93775 +               return -ENOMEM;
93776 +
93777 +       req->mux = mux;
93778 +       req->avg = avg;
93779 +       req->callback =  pcf50606_adc_sync_read_callback;
93780 +       req->callback_param = req;
93781 +       init_completion(&req->completion);
93782 +
93783 +       adc_enqueue_request(pcf, req);
93784 +
93785 +       wait_for_completion(&req->completion);
93786 +       result = req->result;
93787 +
93788 +       return result;
93789 +}
93790 +EXPORT_SYMBOL_GPL(pcf50606_adc_sync_read);
93791 +
93792 +int pcf50606_adc_async_read(struct pcf50606 *pcf, int mux, int avg,
93793 +                            void (*callback)(struct pcf50606 *, void *, int),
93794 +                            void *callback_param)
93795 +{
93796 +       struct pcf50606_adc_request *req;
93797 +
93798 +       /* req is freed when the result is ready, in pcf50606_work*/
93799 +       req = kmalloc(sizeof(*req), GFP_KERNEL);
93800 +       if (!req)
93801 +               return -ENOMEM;
93802 +
93803 +       req->mux = mux;
93804 +       req->avg = avg;
93805 +       req->callback = callback;
93806 +       req->callback_param = callback_param;
93807 +
93808 +       adc_enqueue_request(pcf, req);
93809 +
93810 +       return 0;
93811 +}
93812 +EXPORT_SYMBOL_GPL(pcf50606_adc_async_read);
93813 +
93814 +static int adc_result(struct pcf50606 *pcf)
93815 +{
93816 +       u16 ret = (pcf50606_reg_read(pcf, PCF50606_REG_ADCS1) << 2) |
93817 +                       (pcf50606_reg_read(pcf, PCF50606_REG_ADCS2) & 0x03);
93818 +
93819 +       dev_info(pcf->dev, "adc result = %d\n", ret);
93820 +
93821 +       return ret;
93822 +}
93823 +
93824 +static void pcf50606_adc_irq(struct pcf50606 *pcf, int irq, void *unused)
93825 +{
93826 +       struct pcf50606_adc_request *req;
93827 +       int head;
93828 +
93829 +       mutex_lock(&pcf->adc.queue_mutex);
93830 +       head = pcf->adc.queue_head;
93831 +
93832 +       req = pcf->adc.queue[head];
93833 +       if (!req) {
93834 +               dev_err(pcf->dev, "ADC queue empty\n");
93835 +               mutex_unlock(&pcf->adc.queue_mutex);
93836 +               return;
93837 +       }
93838 +       pcf->adc.queue[head] = NULL;
93839 +       pcf->adc.queue_head = (head + 1) &
93840 +                                     (PCF50606_MAX_ADC_FIFO_DEPTH - 1);
93841 +
93842 +       mutex_unlock(&pcf->adc.queue_mutex);
93843 +       req->callback(pcf, req->callback_param, adc_result(pcf));
93844 +
93845 +       kfree(req);
93846 +
93847 +       trigger_next_adc_job_if_any(pcf);
93848 +}
93849 +
93850 +int __init pcf50606_adc_probe(struct platform_device *pdev)
93851 +{
93852 +       struct pcf50606 *pcf;
93853 +
93854 +       pcf = platform_get_drvdata(pdev);
93855 +
93856 +       /* Set up IRQ handlers */
93857 +       pcf->irq_handler[PCF50606_IRQ_ADCRDY].handler = pcf50606_adc_irq;
93858 +
93859 +       mutex_init(&pcf->adc.queue_mutex);
93860 +       return 0;
93861 +}
93862 +
93863 +static int __devexit pcf50606_adc_remove(struct platform_device *pdev)
93864 +{
93865 +       struct pcf50606 *pcf;
93866 +
93867 +       pcf = platform_get_drvdata(pdev);
93868 +       pcf->irq_handler[PCF50606_IRQ_ADCRDY].handler = NULL;
93869 +
93870 +       return 0;
93871 +}
93872 +
93873 +struct platform_driver pcf50606_adc_driver = {
93874 +       .driver = {
93875 +               .name = "pcf50606-adc",
93876 +       },
93877 +       .probe = pcf50606_adc_probe,
93878 +       .remove = __devexit_p(pcf50606_adc_remove),
93879 +};
93880 +
93881 +static int __init pcf50606_adc_init(void)
93882 +{
93883 +               return platform_driver_register(&pcf50606_adc_driver);
93884 +}
93885 +module_init(pcf50606_adc_init);
93886 +
93887 +static void __exit pcf50606_adc_exit(void)
93888 +{
93889 +               platform_driver_unregister(&pcf50606_adc_driver);
93890 +}
93891 +module_exit(pcf50606_adc_exit);
93892 +
93893 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
93894 +MODULE_DESCRIPTION("PCF50606 adc driver");
93895 +MODULE_LICENSE("GPL");
93896 +MODULE_ALIAS("platform:pcf50606-adc");
93897 +
93898 --- /dev/null
93899 +++ b/drivers/mfd/pcf50606-core.c
93900 @@ -0,0 +1,580 @@
93901 +/* Philips PCF50606 Power Management Unit (PMU) driver
93902 + *
93903 + * (C) 2006-2008 by Openmoko, Inc.
93904 + * Author: Harald Welte <laforge@openmoko.org>
93905 + *         Matt Hsu <matt@openmoko.org>
93906 + * All rights reserved.
93907 + *
93908 + * This program is free software; you can redistribute it and/or
93909 + * modify it under the terms of the GNU General Public License as
93910 + * published by the Free Software Foundation; either version 2 of
93911 + * the License, or (at your option) any later version.
93912 + *
93913 + * This program is distributed in the hope that it will be useful,
93914 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
93915 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
93916 + * GNU General Public License for more details.
93917 + *
93918 + * You should have received a copy of the GNU General Public License
93919 + * along with this program; if not, write to the Free Software
93920 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
93921 + * MA 02111-1307 USA
93922 + *
93923 + */
93924 +#include <linux/i2c.h>
93925 +#include <linux/irq.h>
93926 +#include <linux/device.h>
93927 +#include <linux/module.h>
93928 +#include <linux/reboot.h>
93929 +#include <linux/interrupt.h>
93930 +#include <linux/workqueue.h>
93931 +#include <linux/platform_device.h>
93932 +
93933 +#include <linux/mfd/pcf50606/core.h>
93934 +
93935 +/* Read a block of upto 32 regs  */
93936 +int pcf50606_read_block(struct pcf50606 *pcf , u8 reg,
93937 +                                       int nr_regs, u8 *data)
93938 +{
93939 +       int ret;
93940 +
93941 +       mutex_lock(&pcf->lock);
93942 +       ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg,
93943 +                                                       nr_regs, data);
93944 +       mutex_unlock(&pcf->lock);
93945 +
93946 +       return ret;
93947 +}
93948 +EXPORT_SYMBOL_GPL(pcf50606_read_block);
93949 +
93950 +/* Write a block of upto 32 regs  */
93951 +int pcf50606_write_block(struct pcf50606 *pcf , u8 reg,
93952 +                                       int nr_regs, u8 *data)
93953 +{
93954 +       int ret;
93955 +
93956 +       mutex_lock(&pcf->lock);
93957 +       ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg,
93958 +                                                       nr_regs, data);
93959 +       mutex_unlock(&pcf->lock);
93960 +
93961 +       return ret;
93962 +}
93963 +EXPORT_SYMBOL_GPL(pcf50606_write_block);
93964 +
93965 +u8 pcf50606_reg_read(struct pcf50606 *pcf, u8 reg)
93966 +{
93967 +       int ret;
93968 +
93969 +       mutex_lock(&pcf->lock);
93970 +       ret = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
93971 +       mutex_unlock(&pcf->lock);
93972 +
93973 +       return ret;
93974 +}
93975 +EXPORT_SYMBOL_GPL(pcf50606_reg_read);
93976 +
93977 +int pcf50606_reg_write(struct pcf50606 *pcf, u8 reg, u8 val)
93978 +{
93979 +       int ret;
93980 +       mutex_lock(&pcf->lock);
93981 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, val);
93982 +       mutex_unlock(&pcf->lock);
93983 +
93984 +       return ret;
93985 +}
93986 +EXPORT_SYMBOL_GPL(pcf50606_reg_write);
93987 +
93988 +int pcf50606_reg_set_bit_mask(struct pcf50606 *pcf, u8 reg, u8 mask, u8 val)
93989 +{
93990 +       int ret;
93991 +       u8 tmp;
93992 +
93993 +       val &= mask;
93994 +
93995 +       mutex_lock(&pcf->lock);
93996 +
93997 +       tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
93998 +       tmp &= ~mask;
93999 +       tmp |= val;
94000 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
94001 +
94002 +       mutex_unlock(&pcf->lock);
94003 +
94004 +       return ret;
94005 +}
94006 +EXPORT_SYMBOL_GPL(pcf50606_reg_set_bit_mask);
94007 +
94008 +int pcf50606_reg_clear_bits(struct pcf50606 *pcf, u8 reg, u8 val)
94009 +{
94010 +       int ret;
94011 +       u8 tmp;
94012 +
94013 +       mutex_lock(&pcf->lock);
94014 +
94015 +       tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94016 +       tmp &= ~val;
94017 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
94018 +
94019 +       mutex_unlock(&pcf->lock);
94020 +
94021 +       return ret;
94022 +}
94023 +EXPORT_SYMBOL_GPL(pcf50606_reg_clear_bits);
94024 +
94025 +static ssize_t show_resume_reason(struct device *dev,
94026 +                               struct device_attribute *attr, char *buf)
94027 +{
94028 +       struct pcf50606 *pcf = dev_get_drvdata(dev);
94029 +       int n;
94030 +
94031 +       n = sprintf(buf, "%02x%02x%02x%02x%02x\n",
94032 +                               pcf->resume_reason[0],
94033 +                               pcf->resume_reason[1],
94034 +                               pcf->resume_reason[2],
94035 +                               pcf->resume_reason[3],
94036 +                               pcf->resume_reason[4]);
94037 +
94038 +       return n;
94039 +}
94040 +static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL);
94041 +
94042 +static struct attribute *pcf_sysfs_entries[] = {
94043 +       &dev_attr_resume_reason.attr,
94044 +       NULL,
94045 +};
94046 +
94047 +static struct attribute_group pcf_attr_group = {
94048 +       .name   = NULL,                 /* put in device directory */
94049 +       .attrs  = pcf_sysfs_entries,
94050 +};
94051 +
94052 +
94053 +static int pcf50606_irq_mask_set(struct pcf50606 *pcf, int irq, int mask)
94054 +{
94055 +       u8 reg, bits, tmp;
94056 +       int ret = 0, idx;
94057 +
94058 +       idx = irq / 8;
94059 +       reg =  PCF50606_REG_INT1M + idx;
94060 +       bits = 1 << (irq % 8);
94061 +
94062 +       mutex_lock(&pcf->lock);
94063 +
94064 +       if (mask) {
94065 +               tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94066 +               tmp |= bits;
94067 +               ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
94068 +
94069 +               pcf->mask_regs[idx] &= ~bits;
94070 +               pcf->mask_regs[idx] |= bits;
94071 +       } else {
94072 +               tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94073 +               tmp &= ~bits;
94074 +               ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
94075 +
94076 +               pcf->mask_regs[idx] &= ~bits;
94077 +       }
94078 +
94079 +       mutex_unlock(&pcf->lock);
94080 +
94081 +       return 0;
94082 +}
94083 +
94084 +int pcf50606_irq_mask(struct pcf50606 *pcf, int irq)
94085 +{
94086 +       dev_info(pcf->dev, "Masking IRQ %d\n", irq);
94087 +
94088 +       return pcf50606_irq_mask_set(pcf, irq, 1);
94089 +}
94090 +EXPORT_SYMBOL_GPL(pcf50606_irq_mask);
94091 +
94092 +int pcf50606_irq_unmask(struct pcf50606 *pcf, int irq)
94093 +{
94094 +       dev_info(pcf->dev, "Unmasking IRQ %d\n", irq);
94095 +
94096 +       return pcf50606_irq_mask_set(pcf, irq, 0);
94097 +}
94098 +EXPORT_SYMBOL_GPL(pcf50606_irq_unmask);
94099 +
94100 +int pcf50606_irq_mask_get(struct pcf50606 *pcf, int irq)
94101 +{
94102 +       u8 reg, bits;
94103 +
94104 +       reg =  (irq / 8);
94105 +       bits = (1 << (irq % 8));
94106 +
94107 +       return pcf->mask_regs[reg] & bits;
94108 +}
94109 +EXPORT_SYMBOL_GPL(pcf50606_irq_mask_get);
94110 +
94111 +static void pcf50606_irq_call_handler(struct pcf50606 *pcf,
94112 +                                       int irq)
94113 +{
94114 +       if (pcf->irq_handler[irq].handler)
94115 +               pcf->irq_handler[irq].handler(pcf, irq,
94116 +                                       pcf->irq_handler[irq].data);
94117 +}
94118 +
94119 +#define PCF50606_ONKEY1S_TIMEOUT 8
94120 +
94121 +static void pcf50606_irq_worker(struct work_struct *work)
94122 +{
94123 +       struct pcf50606 *pcf;
94124 +       int ret, i, j;
94125 +       u8 pcf_int[3], chgstat;
94126 +
94127 +       pcf = container_of(work, struct pcf50606, irq_work);
94128 +
94129 +       /* Read the 3 INT regs in one transaction */
94130 +       ret = pcf50606_read_block(pcf, PCF50606_REG_INT1,
94131 +                                               sizeof(pcf_int), pcf_int);
94132 +       if (ret != sizeof(pcf_int)) {
94133 +               dev_info(pcf->dev, "Error reading INT registers\n");
94134 +
94135 +               /* We don't have an option but to retry. Because if
94136 +                * we don't, there won't be another interrupt edge.
94137 +                */
94138 +               goto reschedule;
94139 +       }
94140 +
94141 +       /* We immediately read the usb and adapter status. We thus make sure
94142 +        * only of CHGINS/CHGRM handlers are called */
94143 +       if (pcf_int[1] & (PCF50606_INT2_CHGINS | PCF50606_INT2_CHGRM)) {
94144 +               chgstat = pcf50606_reg_read(pcf, PCF50606_REG_MBCS1);
94145 +               if (chgstat & (0x1 << 4))
94146 +                       pcf_int[1] &= ~(1 << PCF50606_INT2_CHGRM);
94147 +               else
94148 +                       pcf_int[1] &= ~(1 << PCF50606_INT2_CHGINS);
94149 +       }
94150 +
94151 +       dev_info(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x",
94152 +                               pcf_int[0], pcf_int[1], pcf_int[2]);
94153 +
94154 +       /* Some revisions of the chip don't have a 8s standby mode on
94155 +        * ONKEY1S press. We try to manually do it in such cases. */
94156 +
94157 +       if (pcf_int[0] & PCF50606_INT1_SECOND && pcf->onkey1s_held) {
94158 +               dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
94159 +                                                       pcf->onkey1s_held);
94160 +               if (pcf->onkey1s_held++ == PCF50606_ONKEY1S_TIMEOUT)
94161 +                       if (pcf->pdata->force_shutdown)
94162 +                               pcf->pdata->force_shutdown(pcf);
94163 +       }
94164 +
94165 +       if (pcf_int[0] & PCF50606_INT1_ONKEY1S) {
94166 +               dev_info(pcf->dev, "ONKEY1S held\n");
94167 +               pcf->onkey1s_held = 1 ;
94168 +
94169 +               /* Unmask IRQ_SECOND */
94170 +               pcf50606_reg_clear_bits(pcf, PCF50606_REG_INT1M,
94171 +                                               PCF50606_INT1_SECOND);
94172 +
94173 +               /* Unmask IRQ_ONKEYF */
94174 +               pcf50606_reg_clear_bits(pcf, PCF50606_REG_INT1M,
94175 +                                               PCF50606_INT1_ONKEYF);
94176 +       }
94177 +
94178 +       if ((pcf_int[0] & PCF50606_INT1_ONKEYR) && pcf->onkey1s_held) {
94179 +               pcf->onkey1s_held = 0;
94180 +
94181 +               /* Mask SECOND and ONKEYF interrupts */
94182 +               if (pcf->mask_regs[0] & PCF50606_INT1_SECOND)
94183 +                       pcf50606_reg_set_bit_mask(pcf,
94184 +                                       PCF50606_REG_INT1M,
94185 +                                       PCF50606_INT1_SECOND,
94186 +                                       PCF50606_INT1_SECOND);
94187 +
94188 +               if (pcf->mask_regs[0] & PCF50606_INT1_ONKEYF)
94189 +                       pcf50606_reg_set_bit_mask(pcf,
94190 +                                       PCF50606_REG_INT1M,
94191 +                                       PCF50606_INT1_ONKEYF,
94192 +                                       PCF50606_INT1_ONKEYF);
94193 +       }
94194 +
94195 +       /* Have we just resumed ? */
94196 +       if (pcf->is_suspended) {
94197 +
94198 +               pcf->is_suspended = 0;
94199 +
94200 +               /* Set the resume reason filtering out non resumers */
94201 +               for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
94202 +                       pcf->resume_reason[i] = pcf_int[i] &
94203 +                                               pcf->pdata->resumers[i];
94204 +
94205 +               /* Make sure we don't pass on any input events to
94206 +                * userspace now */
94207 +               pcf_int[0] &= ~(PCF50606_INT1_SECOND | PCF50606_INT1_ALARM);
94208 +       }
94209 +
94210 +       /* Unset masked interrupts */
94211 +       for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
94212 +               pcf_int[i] &= ~pcf->mask_regs[i];
94213 +
94214 +       for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
94215 +               for (j = 0; j < 8 ; j++)
94216 +                       if (pcf_int[i] & (1 << j))
94217 +                               pcf50606_irq_call_handler(pcf, (i * 8) + j);
94218 +
94219 +       put_device(pcf->dev);
94220 +
94221 +       return;
94222 +reschedule:
94223 +       schedule_work(&pcf->irq_work);
94224 +
94225 +       /* Don't put_device here. Will be used when we are rescheduled */
94226 +
94227 +       return;
94228 +}
94229 +
94230 +static irqreturn_t pcf50606_irq(int irq, void *data)
94231 +{
94232 +       struct pcf50606 *pcf = data;
94233 +
94234 +       get_device(pcf->dev);
94235 +       schedule_work(&pcf->irq_work);
94236 +
94237 +       return IRQ_HANDLED;
94238 +}
94239 +
94240 +static void
94241 +pcf50606_client_dev_register(struct pcf50606 *pcf, const char *name,
94242 +                                               struct platform_device **pdev)
94243 +{
94244 +       int ret;
94245 +
94246 +       *pdev = platform_device_alloc(name, -1);
94247 +
94248 +       if (!pdev) {
94249 +               dev_err(pcf->dev, "Falied to allocate %s\n", name);
94250 +               return;
94251 +       }
94252 +
94253 +       (*pdev)->dev.parent = pcf->dev;
94254 +       platform_set_drvdata(*pdev, pcf);
94255 +
94256 +       ret = platform_device_add(*pdev);
94257 +       if (ret != 0) {
94258 +               dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret);
94259 +               platform_device_put(*pdev);
94260 +               *pdev = NULL;
94261 +       }
94262 +}
94263 +
94264 +#ifdef CONFIG_PM
94265 +static int pcf50606_suspend(struct device *dev, pm_message_t state)
94266 +{
94267 +       struct pcf50606 *pcf;
94268 +       int ret, i;
94269 +       u8 res[3];
94270 +
94271 +       pcf = dev_get_drvdata(dev);
94272 +
94273 +       /* Make sure our interrupt handlers are not called
94274 +        * henceforth */
94275 +       disable_irq(pcf->irq);
94276 +
94277 +       /* Make sure that an IRQ worker has quit */
94278 +       cancel_work_sync(&pcf->irq_work);
94279 +
94280 +       /* Save the masks */
94281 +       ret = pcf50606_read_block(pcf, PCF50606_REG_INT1M,
94282 +                               ARRAY_SIZE(pcf->suspend_irq_masks),
94283 +                                               pcf->suspend_irq_masks);
94284 +       if (ret < 0)
94285 +               dev_err(pcf->dev, "error saving irq masks\n");
94286 +
94287 +       /* Set interrupt masks. So that only those sources we want to wake
94288 +        * us up can
94289 +        */
94290 +       for (i = 0; i < ARRAY_SIZE(res); i++)
94291 +               res[i] = ~pcf->pdata->resumers[i];
94292 +
94293 +       pcf50606_write_block(pcf, PCF50606_REG_INT1M,
94294 +                                       ARRAY_SIZE(res), &res[0]);
94295 +
94296 +       pcf->is_suspended = 1;
94297 +
94298 +       return 0;
94299 +}
94300 +
94301 +static int pcf50606_resume(struct device *dev)
94302 +{
94303 +       struct pcf50606 *pcf;
94304 +
94305 +       pcf = dev_get_drvdata(dev);
94306 +
94307 +       /* Write the saved mask registers */
94308 +       pcf50606_write_block(pcf, PCF50606_REG_INT1M,
94309 +                       ARRAY_SIZE(pcf->suspend_irq_masks),
94310 +                                       pcf->suspend_irq_masks);
94311 +
94312 +       /* Clear any pending interrupts and set resume reason if any */
94313 +       pcf50606_irq_worker(&pcf->irq_work);
94314 +
94315 +       enable_irq(pcf->irq);
94316 +
94317 +       return 0;
94318 +}
94319 +#else
94320 +#define pcf50606_suspend NULL
94321 +#define pcf50606_resume NULL
94322 +#endif
94323 +
94324 +static int pcf50606_probe(struct i2c_client *client,
94325 +                               const struct i2c_device_id *ids)
94326 +{
94327 +       struct pcf50606 *pcf;
94328 +       struct pcf50606_platform_data *pdata;
94329 +       int i, ret = 0;
94330 +       int version, variant;
94331 +       u8 mbcs1;
94332 +
94333 +       pdata = client->dev.platform_data;
94334 +
94335 +       pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
94336 +       if (!pcf)
94337 +               return -ENOMEM;
94338 +
94339 +       pcf->pdata = pdata;
94340 +       pdata->pcf = pcf;
94341 +
94342 +       mutex_init(&pcf->lock);
94343 +
94344 +       i2c_set_clientdata(client, pcf);
94345 +       pcf->dev = &client->dev;
94346 +       pcf->i2c_client = client;
94347 +
94348 +       INIT_WORK(&pcf->irq_work, pcf50606_irq_worker);
94349 +
94350 +       version = pcf50606_reg_read(pcf, 0);
94351 +       if (version < 0) {
94352 +               dev_err(pcf->dev, "Unable to probe pcf50606\n");
94353 +               kfree(pcf);
94354 +               return -ENODEV;
94355 +       }
94356 +
94357 +       variant = pcf50606_reg_read(pcf, 1);
94358 +       if (version < 0) {
94359 +               dev_err(pcf->dev, "Unable to probe pcf50606\n");
94360 +               kfree(pcf);
94361 +               return -ENODEV;
94362 +       }
94363 +
94364 +       dev_info(pcf->dev, "Probed device version %d variant %d\n",
94365 +                                                       version, variant);
94366 +
94367 +       /* Enable all inteerupts except RTC SECOND */
94368 +       pcf->mask_regs[0] = 0x80;
94369 +       pcf50606_reg_write(pcf, PCF50606_REG_INT1M, 0x80);
94370 +
94371 +       pcf50606_reg_write(pcf, PCF50606_REG_INT2M, 0x00);
94372 +       pcf50606_reg_write(pcf, PCF50606_REG_INT3M, 0x00);
94373 +
94374 +       pcf50606_client_dev_register(pcf, "pcf50606-input",
94375 +                                               &pcf->input.pdev);
94376 +       pcf50606_client_dev_register(pcf, "pcf50606-rtc",
94377 +                                               &pcf->rtc.pdev);
94378 +       pcf50606_client_dev_register(pcf, "pcf50606-mbc",
94379 +                                               &pcf->mbc.pdev);
94380 +       pcf50606_client_dev_register(pcf, "pcf50606-adc",
94381 +                                               &pcf->adc.pdev);
94382 +       pcf50606_client_dev_register(pcf, "pcf50606-wdt",
94383 +                                               &pcf->wdt.pdev);
94384 +       for (i = 0; i < PCF50606_NUM_REGULATORS; i++) {
94385 +               struct platform_device *pdev;
94386 +
94387 +               pdev = platform_device_alloc("pcf50606-regltr", i);
94388 +               if (!pdev) {
94389 +                       dev_err(pcf->dev, "Cannot create regulator\n");
94390 +                       continue;
94391 +               }
94392 +
94393 +               pdev->dev.parent = pcf->dev;
94394 +               pdev->dev.platform_data = &pdata->reg_init_data[i];
94395 +               pdev->dev.driver_data = pcf;
94396 +               pcf->pmic.pdev[i] = pdev;
94397 +
94398 +               platform_device_add(pdev);
94399 +       }
94400 +
94401 +       pcf->irq = client->irq;
94402 +
94403 +       if (client->irq) {
94404 +               ret = request_irq(client->irq, pcf50606_irq,
94405 +                               IRQF_TRIGGER_FALLING, "pcf50606", pcf);
94406 +
94407 +               if (ret) {
94408 +                       dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
94409 +                       goto err;
94410 +               }
94411 +       } else {
94412 +               dev_err(pcf->dev, "No IRQ configured\n");
94413 +               goto err;
94414 +       }
94415 +
94416 +       if (enable_irq_wake(client->irq) < 0)
94417 +               dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source"
94418 +                       "in this hardware revision", client->irq);
94419 +
94420 +       /* Cold Intialization */
94421 +       mbcs1 = pcf50606_reg_read(pcf, PCF50606_REG_MBCS1);
94422 +
94423 +       if (mbcs1 & (0x01 << 4)) /* Charger present ? */
94424 +               pcf50606_irq_call_handler(pcf, PCF50606_IRQ_CHGINS);
94425 +
94426 +       ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
94427 +       if (ret)
94428 +               dev_err(pcf->dev, "error creating sysfs entries\n");
94429 +
94430 +       if (pdata->probe_done)
94431 +               pdata->probe_done(pcf);
94432 +
94433 +       return 0;
94434 +
94435 +err:
94436 +       kfree(pcf);
94437 +       return ret;
94438 +}
94439 +
94440 +static int pcf50606_remove(struct i2c_client *client)
94441 +{
94442 +       struct pcf50606 *pcf = i2c_get_clientdata(client);
94443 +
94444 +       free_irq(pcf->irq, pcf);
94445 +       kfree(pcf);
94446 +
94447 +       return 0;
94448 +}
94449 +
94450 +static struct i2c_device_id pcf50606_id_table[] = {
94451 +       {"pcf50606", 0x73},
94452 +};
94453 +
94454 +static struct i2c_driver pcf50606_driver = {
94455 +       .driver = {
94456 +               .name   = "pcf50606",
94457 +               .suspend = pcf50606_suspend,
94458 +               .resume = pcf50606_resume,
94459 +       },
94460 +       .id_table = pcf50606_id_table,
94461 +       .probe = pcf50606_probe,
94462 +       .remove = pcf50606_remove,
94463 +};
94464 +
94465 +static int __init pcf50606_init(void)
94466 +{
94467 +       return i2c_add_driver(&pcf50606_driver);
94468 +}
94469 +
94470 +static void pcf50606_exit(void)
94471 +{
94472 +       i2c_del_driver(&pcf50606_driver);
94473 +}
94474 +
94475 +MODULE_DESCRIPTION("I2C chip driver for NXP PCF50606 PMU");
94476 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
94477 +MODULE_LICENSE("GPL");
94478 +
94479 +module_init(pcf50606_init);
94480 +module_exit(pcf50606_exit);
94481 --- /dev/null
94482 +++ b/drivers/mfd/pcf50606-gpo.c
94483 @@ -0,0 +1,128 @@
94484 +/* Philips PCF50606 GPO Driver
94485 + *
94486 + * (C) 2006-2008 by Openmoko, Inc.
94487 + * Author: Balaji Rao <balajirrao@openmoko.org>
94488 + * All rights reserved.
94489 + *
94490 + * Broken down from monstrous PCF50606 driver mainly by
94491 + * Harald Welte, Andy Green and Werner Almesberger
94492 + *
94493 + * This program is free software; you can redistribute it and/or
94494 + * modify it under the terms of the GNU General Public License as
94495 + * published by the Free Software Foundation; either version 2 of
94496 + * the License, or (at your option) any later version.
94497 + *
94498 + * This program is distributed in the hope that it will be useful,
94499 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
94500 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
94501 + * GNU General Public License for more details.
94502 + *
94503 + * You should have received a copy of the GNU General Public License
94504 + * along with this program; if not, write to the Free Software
94505 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
94506 + * MA 02111-1307 USA
94507 + */
94508 +
94509 +#include <linux/mfd/pcf50606/core.h>
94510 +#include <linux/mfd/pcf50606/gpo.h>
94511 +#include <linux/mfd/pcf50606/pmic.h>
94512 +
94513 +void pcf50606_gpo_set_active(struct pcf50606 *pcf, int gpo, int val)
94514 +{
94515 +       u8 reg, value, mask;
94516 +
94517 +       reg = gpo;
94518 +       value = val;
94519 +       mask = 0x07;
94520 +
94521 +       if (gpo == PCF50606_GPO2) {
94522 +               value = val << 4;
94523 +               mask = 0x07 << 4;
94524 +       }
94525 +       pcf50606_reg_set_bit_mask(pcf, reg, mask, value);
94526 +}
94527 +EXPORT_SYMBOL_GPL(pcf50606_gpo_set_active);
94528 +
94529 +int pcf50606_gpo_get_active(struct pcf50606 *pcf, int gpo)
94530 +{
94531 +       u8 reg, value, shift = 0;
94532 +
94533 +       reg = gpo;
94534 +       if (gpo == PCF50606_GPO2)
94535 +               shift = 4;
94536 +
94537 +       value = pcf50606_reg_read(pcf, reg);
94538 +
94539 +       return (value >> shift) & 0x07;
94540 +}
94541 +EXPORT_SYMBOL_GPL(pcf50606_gpo_get_active);
94542 +
94543 +void pcf50606_gpo_set_standby(struct pcf50606 *pcf, int gpo, int val)
94544 +{
94545 +       u8 reg;
94546 +
94547 +       if (gpo == PCF50606_GPO1 || gpo == PCF50606_GPO2) {
94548 +               dev_err(pcf->dev, "Can't set standby settings for GPO[12]n");
94549 +               return;
94550 +       }
94551 +
94552 +       reg = gpo;
94553 +
94554 +       pcf50606_reg_set_bit_mask(pcf, gpo, 0x07 << 3, val);
94555 +}
94556 +EXPORT_SYMBOL_GPL(pcf50606_gpo_set_standby);
94557 +
94558 +int pcf50606_gpo_get_standby(struct pcf50606 *pcf, int gpo)
94559 +{
94560 +       u8 reg, value;
94561 +
94562 +       if (gpo == PCF50606_GPO1 || gpo == PCF50606_GPO2) {
94563 +               dev_err(pcf->dev, "Can't get standby settings for GPO[12]n");
94564 +               return -EINVAL;
94565 +       }
94566 +
94567 +       reg = gpo;
94568 +       value = pcf50606_reg_read(pcf, reg);
94569 +
94570 +       return (value >> 3) & 0x07;
94571 +}
94572 +EXPORT_SYMBOL_GPL(pcf50606_gpo_get_standby);
94573 +
94574 +void pcf50606_gpo_invert_set(struct pcf50606 *pcf, int gpo, int invert)
94575 +{
94576 +       u8 reg, value, mask;
94577 +
94578 +       reg = gpo;
94579 +       value = !!invert << 6;
94580 +       mask = 0x01 << 6;
94581 +
94582 +       if (gpo == PCF50606_GPO1) {
94583 +               mask = 0x01 << 4;
94584 +               value = !!invert << 4;
94585 +       }
94586 +       else if (gpo == PCF50606_GPO2) {
94587 +               mask = 0x01 << 7;
94588 +               value = !!invert << 7;
94589 +       }
94590 +
94591 +       pcf50606_reg_set_bit_mask(pcf, reg, mask, value);
94592 +}
94593 +EXPORT_SYMBOL_GPL(pcf50606_gpo_invert_set);
94594 +
94595 +int pcf50606_gpo_invert_get(struct pcf50606 *pcf, int gpo)
94596 +{
94597 +       u8 reg, value, shift;
94598 +
94599 +       reg = gpo;
94600 +       shift = 6;
94601 +
94602 +       if (gpo == PCF50606_GPO1)
94603 +               shift = 4;
94604 +       else if (gpo == PCF50606_GPO2)
94605 +               shift = 7;
94606 +
94607 +       value =  pcf50606_reg_read(pcf, reg);
94608 +
94609 +       return (value >> shift) & 0x01;
94610 +}
94611 +EXPORT_SYMBOL_GPL(pcf50606_gpo_invert_get);
94612 --- /dev/null
94613 +++ b/drivers/mfd/pcf50633-adc.c
94614 @@ -0,0 +1,252 @@
94615 +/* Philips PCF50633 ADC Driver
94616 + *
94617 + * (C) 2006-2008 by Openmoko, Inc.
94618 + * Author: Balaji Rao <balajirrao@openmoko.org>
94619 + * All rights reserved.
94620 + *
94621 + * Broken down from monstrous PCF50633 driver mainly by
94622 + * Harald Welte, Andy Green and Werner Almesberger
94623 + *
94624 + * This program is free software; you can redistribute it and/or
94625 + * modify it under the terms of the GNU General Public License as
94626 + * published by the Free Software Foundation; either version 2 of
94627 + * the License, or (at your option) any later version.
94628 + *
94629 + * This program is distributed in the hope that it will be useful,
94630 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
94631 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
94632 + * GNU General Public License for more details.
94633 + *
94634 + * You should have received a copy of the GNU General Public License
94635 + * along with this program; if not, write to the Free Software
94636 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
94637 + * MA 02111-1307 USA
94638 + */
94639 +
94640 +/*
94641 + * NOTE: This driver does not yet support subtractive ADC mode, which means
94642 + * you can do only one measurement per read request.
94643 + */
94644 +
94645 +#include <linux/mfd/pcf50633/core.h>
94646 +#include <linux/mfd/pcf50633/adc.h>
94647 +
94648 +struct pcf50633_adc_request {
94649 +       int mux;
94650 +       int avg;
94651 +       int result;
94652 +       void (*callback)(struct pcf50633 *, void *, int);
94653 +       void *callback_param;
94654 +
94655 +       /* Used in case of sync requests */
94656 +       struct completion completion;
94657 +
94658 +};
94659 +
94660 +static void adc_read_setup(struct pcf50633 *pcf,
94661 +                                int channel, int avg)
94662 +{
94663 +       channel &= PCF50633_ADCC1_ADCMUX_MASK;
94664 +
94665 +       /* kill ratiometric, but enable ACCSW biasing */
94666 +       pcf50633_reg_write(pcf, PCF50633_REG_ADCC2, 0x00);
94667 +       pcf50633_reg_write(pcf, PCF50633_REG_ADCC3, 0x01);
94668 +
94669 +       /* start ADC conversion on selected channel */
94670 +       pcf50633_reg_write(pcf, PCF50633_REG_ADCC1, channel | avg |
94671 +                   PCF50633_ADCC1_ADCSTART | PCF50633_ADCC1_RES_10BIT);
94672 +
94673 +}
94674 +
94675 +static void trigger_next_adc_job_if_any(struct pcf50633 *pcf)
94676 +{
94677 +       int head, tail;
94678 +
94679 +       mutex_lock(&pcf->adc.queue_mutex);
94680 +
94681 +       head = pcf->adc.queue_head;
94682 +       tail = pcf->adc.queue_tail;
94683 +
94684 +       if (!pcf->adc.queue[head])
94685 +               goto out;
94686 +
94687 +       adc_read_setup(pcf, pcf->adc.queue[head]->mux,
94688 +                               pcf->adc.queue[head]->avg);
94689 +out:
94690 +       mutex_unlock(&pcf->adc.queue_mutex);
94691 +}
94692 +
94693 +static int
94694 +adc_enqueue_request(struct pcf50633 *pcf, struct pcf50633_adc_request *req)
94695 +{
94696 +       int head, tail;
94697 +
94698 +       mutex_lock(&pcf->adc.queue_mutex);
94699 +       head = pcf->adc.queue_head;
94700 +       tail = pcf->adc.queue_tail;
94701 +
94702 +       if (pcf->adc.queue[tail]) {
94703 +               mutex_unlock(&pcf->adc.queue_mutex);
94704 +               return -EBUSY;
94705 +       }
94706 +
94707 +       pcf->adc.queue[tail] = req;
94708 +
94709 +       pcf->adc.queue_tail =
94710 +               (tail + 1) & (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
94711 +
94712 +       mutex_unlock(&pcf->adc.queue_mutex);
94713 +
94714 +       trigger_next_adc_job_if_any(pcf);
94715 +
94716 +       return 0;
94717 +}
94718 +
94719 +static void
94720 +pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param, int result)
94721 +{
94722 +       struct pcf50633_adc_request *req;
94723 +
94724 +       /*We know here that the passed param is an adc_request object */
94725 +       req = (struct pcf50633_adc_request *)param;
94726 +
94727 +       req->result = result;
94728 +       complete(&req->completion);
94729 +}
94730 +
94731 +int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg)
94732 +{
94733 +
94734 +       struct pcf50633_adc_request *req;
94735 +       int result;
94736 +
94737 +       /* req is freed when the result is ready, in interrupt handler */
94738 +       req = kzalloc(sizeof(*req), GFP_KERNEL);
94739 +       if (!req)
94740 +               return -ENOMEM;
94741 +
94742 +       req->mux = mux;
94743 +       req->avg = avg;
94744 +       req->callback =  pcf50633_adc_sync_read_callback;
94745 +       req->callback_param = req;
94746 +       init_completion(&req->completion);
94747 +
94748 +       adc_enqueue_request(pcf, req);
94749 +
94750 +       wait_for_completion(&req->completion);
94751 +       result = req->result;
94752 +
94753 +       return result;
94754 +}
94755 +EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read);
94756 +
94757 +int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
94758 +                            void (*callback)(struct pcf50633 *, void *, int),
94759 +                            void *callback_param)
94760 +{
94761 +       struct pcf50633_adc_request *req;
94762 +
94763 +       /* req is freed when the result is ready, in interrupt handler */
94764 +       req = kmalloc(sizeof(*req), GFP_KERNEL);
94765 +       if (!req)
94766 +               return -ENOMEM;
94767 +
94768 +       req->mux = mux;
94769 +       req->avg = avg;
94770 +       req->callback = callback;
94771 +       req->callback_param = callback_param;
94772 +
94773 +       adc_enqueue_request(pcf, req);
94774 +
94775 +       return 0;
94776 +}
94777 +EXPORT_SYMBOL_GPL(pcf50633_adc_async_read);
94778 +
94779 +static int adc_result(struct pcf50633 *pcf)
94780 +{
94781 +       u8 adcs1, adcs3;
94782 +       u16 result;
94783 +
94784 +       adcs1 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS1);
94785 +       adcs3 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS3);
94786 +       result = (adcs1 << 2) | (adcs3 & PCF50633_ADCS3_ADCDAT1L_MASK);
94787 +
94788 +       dev_info(pcf->dev, "adc result = %d\n", result);
94789 +
94790 +       return result;
94791 +}
94792 +
94793 +static void pcf50633_adc_irq(struct pcf50633 *pcf, int irq, void *unused)
94794 +{
94795 +       struct pcf50633_adc_request *req;
94796 +       int head;
94797 +
94798 +       mutex_lock(&pcf->adc.queue_mutex);
94799 +       head = pcf->adc.queue_head;
94800 +
94801 +       req = pcf->adc.queue[head];
94802 +       if (!req) {
94803 +               dev_err(pcf->dev, "ADC queue empty\n");
94804 +               mutex_unlock(&pcf->adc.queue_mutex);
94805 +               return;
94806 +       }
94807 +       pcf->adc.queue[head] = NULL;
94808 +       pcf->adc.queue_head = (head + 1) &
94809 +                                     (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
94810 +
94811 +       mutex_unlock(&pcf->adc.queue_mutex);
94812 +       req->callback(pcf, req->callback_param, adc_result(pcf));
94813 +
94814 +       kfree(req);
94815 +
94816 +       trigger_next_adc_job_if_any(pcf);
94817 +}
94818 +
94819 +int __init pcf50633_adc_probe(struct platform_device *pdev)
94820 +{
94821 +       struct pcf50633 *pcf;
94822 +
94823 +       pcf = platform_get_drvdata(pdev);
94824 +
94825 +       /* Set up IRQ handlers */
94826 +       pcf->irq_handler[PCF50633_IRQ_ADCRDY].handler = pcf50633_adc_irq;
94827 +
94828 +       mutex_init(&pcf->adc.queue_mutex);
94829 +       return 0;
94830 +}
94831 +
94832 +static int __devexit pcf50633_adc_remove(struct platform_device *pdev)
94833 +{
94834 +       struct pcf50633 *pcf;
94835 +
94836 +       pcf = platform_get_drvdata(pdev);
94837 +       pcf->irq_handler[PCF50633_IRQ_ADCRDY].handler = NULL;
94838 +
94839 +       return 0;
94840 +}
94841 +
94842 +struct platform_driver pcf50633_adc_driver = {
94843 +       .driver = {
94844 +               .name = "pcf50633-adc",
94845 +       },
94846 +       .probe = pcf50633_adc_probe,
94847 +       .remove = __devexit_p(pcf50633_adc_remove),
94848 +};
94849 +
94850 +static int __init pcf50633_adc_init(void)
94851 +{
94852 +               return platform_driver_register(&pcf50633_adc_driver);
94853 +}
94854 +module_init(pcf50633_adc_init);
94855 +
94856 +static void __exit pcf50633_adc_exit(void)
94857 +{
94858 +               platform_driver_unregister(&pcf50633_adc_driver);
94859 +}
94860 +module_exit(pcf50633_adc_exit);
94861 +
94862 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
94863 +MODULE_DESCRIPTION("PCF50633 adc driver");
94864 +MODULE_LICENSE("GPL");
94865 +MODULE_ALIAS("platform:pcf50633-adc");
94866 +
94867 --- /dev/null
94868 +++ b/drivers/mfd/pcf50633-core.c
94869 @@ -0,0 +1,627 @@
94870 +/* Philips PCF50633 Power Management Unit (PMU) driver
94871 + *
94872 + * (C) 2006-2008 by Openmoko, Inc.
94873 + * Author: Harald Welte <laforge@openmoko.org>
94874 + * All rights reserved.
94875 + *
94876 + * This program is free software; you can redistribute it and/or
94877 + * modify it under the terms of the GNU General Public License as
94878 + * published by the Free Software Foundation; either version 2 of
94879 + * the License, or (at your option) any later version.
94880 + *
94881 + * This program is distributed in the hope that it will be useful,
94882 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
94883 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
94884 + * GNU General Public License for more details.
94885 + *
94886 + * You should have received a copy of the GNU General Public License
94887 + * along with this program; if not, write to the Free Software
94888 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
94889 + * MA 02111-1307 USA
94890 + *
94891 + */
94892 +#include <linux/i2c.h>
94893 +#include <linux/irq.h>
94894 +#include <linux/device.h>
94895 +#include <linux/module.h>
94896 +#include <linux/reboot.h>
94897 +#include <linux/interrupt.h>
94898 +#include <linux/workqueue.h>
94899 +#include <linux/platform_device.h>
94900 +
94901 +#include <linux/mfd/pcf50633/core.h>
94902 +
94903 +/* Read a block of upto 32 regs  */
94904 +int pcf50633_read_block(struct pcf50633 *pcf , u8 reg,
94905 +                                       int nr_regs, u8 *data)
94906 +{
94907 +       int ret;
94908 +
94909 +       mutex_lock(&pcf->lock);
94910 +       ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg,
94911 +                                                       nr_regs, data);
94912 +       mutex_unlock(&pcf->lock);
94913 +
94914 +       return ret;
94915 +}
94916 +EXPORT_SYMBOL_GPL(pcf50633_read_block);
94917 +
94918 +/* Write a block of upto 32 regs  */
94919 +int pcf50633_write_block(struct pcf50633 *pcf , u8 reg,
94920 +                                       int nr_regs, u8 *data)
94921 +{
94922 +       int ret;
94923 +
94924 +       mutex_lock(&pcf->lock);
94925 +       ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg,
94926 +                                                       nr_regs, data);
94927 +       mutex_unlock(&pcf->lock);
94928 +
94929 +       return ret;
94930 +}
94931 +EXPORT_SYMBOL_GPL(pcf50633_write_block);
94932 +
94933 +u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg)
94934 +{
94935 +       int ret;
94936 +
94937 +       mutex_lock(&pcf->lock);
94938 +       ret = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94939 +       mutex_unlock(&pcf->lock);
94940 +
94941 +       return ret;
94942 +}
94943 +EXPORT_SYMBOL_GPL(pcf50633_reg_read);
94944 +
94945 +int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val)
94946 +{
94947 +       int ret;
94948 +       mutex_lock(&pcf->lock);
94949 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, val);
94950 +       mutex_unlock(&pcf->lock);
94951 +
94952 +       return ret;
94953 +}
94954 +EXPORT_SYMBOL_GPL(pcf50633_reg_write);
94955 +
94956 +int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val)
94957 +{
94958 +       int ret;
94959 +       u8 tmp;
94960 +
94961 +       val &= mask;
94962 +
94963 +       mutex_lock(&pcf->lock);
94964 +
94965 +       tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94966 +       tmp &= ~mask;
94967 +       tmp |= val;
94968 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
94969 +
94970 +       mutex_unlock(&pcf->lock);
94971 +
94972 +       return ret;
94973 +}
94974 +EXPORT_SYMBOL_GPL(pcf50633_reg_set_bit_mask);
94975 +
94976 +int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val)
94977 +{
94978 +       int ret;
94979 +       u8 tmp;
94980 +
94981 +       mutex_lock(&pcf->lock);
94982 +
94983 +       tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94984 +       tmp &= ~val;
94985 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
94986 +
94987 +       mutex_unlock(&pcf->lock);
94988 +
94989 +       return ret;
94990 +}
94991 +EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits);
94992 +
94993 +/* sysfs attributes */
94994 +static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr,
94995 +                           char *buf)
94996 +{
94997 +       struct pcf50633 *pcf = dev_get_drvdata(dev);
94998 +       u8 dump[16];
94999 +       int n, n1, idx = 0;
95000 +       char *buf1 = buf;
95001 +       static u8 address_no_read[] = { /* must be ascending */
95002 +               PCF50633_REG_INT1,
95003 +               PCF50633_REG_INT2,
95004 +               PCF50633_REG_INT3,
95005 +               PCF50633_REG_INT4,
95006 +               PCF50633_REG_INT5,
95007 +               0 /* terminator */
95008 +       };
95009 +
95010 +       for (n = 0; n < 256; n += sizeof(dump)) {
95011 +               for (n1 = 0; n1 < sizeof(dump); n1++)
95012 +                       if (n == address_no_read[idx]) {
95013 +                               idx++;
95014 +                               dump[n1] = 0x00;
95015 +                       } else
95016 +                               dump[n1] = pcf50633_reg_read(pcf, n + n1);
95017 +
95018 +               hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0);
95019 +               buf1 += strlen(buf1);
95020 +               *buf1++ = '\n';
95021 +               *buf1 = '\0';
95022 +       }
95023 +
95024 +       return buf1 - buf;
95025 +}
95026 +static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL);
95027 +
95028 +static ssize_t show_resume_reason(struct device *dev,
95029 +                               struct device_attribute *attr, char *buf)
95030 +{
95031 +       struct pcf50633 *pcf = dev_get_drvdata(dev);
95032 +       int n;
95033 +
95034 +       n = sprintf(buf, "%02x%02x%02x%02x%02x\n",
95035 +                               pcf->resume_reason[0],
95036 +                               pcf->resume_reason[1],
95037 +                               pcf->resume_reason[2],
95038 +                               pcf->resume_reason[3],
95039 +                               pcf->resume_reason[4]);
95040 +
95041 +       return n;
95042 +}
95043 +static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL);
95044 +
95045 +static struct attribute *pcf_sysfs_entries[] = {
95046 +       &dev_attr_dump_regs.attr,
95047 +       &dev_attr_resume_reason.attr,
95048 +       NULL,
95049 +};
95050 +
95051 +static struct attribute_group pcf_attr_group = {
95052 +       .name   = NULL,                 /* put in device directory */
95053 +       .attrs  = pcf_sysfs_entries,
95054 +};
95055 +
95056 +
95057 +static int pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, int mask)
95058 +{
95059 +       u8 reg, bits, tmp;
95060 +       int ret = 0, idx;
95061 +
95062 +       idx = irq / 8;
95063 +       reg =  PCF50633_REG_INT1M + idx;
95064 +       bits = 1 << (irq % 8);
95065 +
95066 +       mutex_lock(&pcf->lock);
95067 +
95068 +       if (mask) {
95069 +               tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
95070 +               tmp |= bits;
95071 +               ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
95072 +
95073 +               pcf->mask_regs[idx] &= ~bits;
95074 +               pcf->mask_regs[idx] |= bits;
95075 +       } else {
95076 +               tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
95077 +               tmp &= ~bits;
95078 +               ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
95079 +
95080 +               pcf->mask_regs[idx] &= ~bits;
95081 +       }
95082 +
95083 +       mutex_unlock(&pcf->lock);
95084 +
95085 +       return 0;
95086 +}
95087 +
95088 +int pcf50633_irq_mask(struct pcf50633 *pcf, int irq)
95089 +{
95090 +       dev_info(pcf->dev, "Masking IRQ %d\n", irq);
95091 +
95092 +       return pcf50633_irq_mask_set(pcf, irq, 1);
95093 +}
95094 +EXPORT_SYMBOL_GPL(pcf50633_irq_mask);
95095 +
95096 +int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq)
95097 +{
95098 +       dev_info(pcf->dev, "Unmasking IRQ %d\n", irq);
95099 +
95100 +       return pcf50633_irq_mask_set(pcf, irq, 0);
95101 +}
95102 +EXPORT_SYMBOL_GPL(pcf50633_irq_unmask);
95103 +
95104 +int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq)
95105 +{
95106 +       u8 reg, bits;
95107 +
95108 +       reg =  (irq / 8);
95109 +       bits = (1 << (irq % 8));
95110 +
95111 +       return pcf->mask_regs[reg] & bits;
95112 +}
95113 +EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get);
95114 +
95115 +static void pcf50633_irq_call_handler(struct pcf50633 *pcf,
95116 +                                       int irq)
95117 +{
95118 +       if (pcf->irq_handler[irq].handler) {
95119 +               pcf->irq_handler[irq].handler(pcf, irq,
95120 +                                       pcf->irq_handler[irq].data);
95121 +       }
95122 +}
95123 +
95124 +#define PCF50633_ONKEY1S_TIMEOUT 8
95125 +
95126 +static void pcf50633_irq_worker(struct work_struct *work)
95127 +{
95128 +       struct pcf50633 *pcf;
95129 +       int ret, i, j;
95130 +       u8 pcf_int[5], chgstat;
95131 +
95132 +       pcf = container_of(work, struct pcf50633, irq_work);
95133 +
95134 +       /* Read the 5 INT regs in one transaction */
95135 +       ret = pcf50633_read_block(pcf, PCF50633_REG_INT1,
95136 +                                               sizeof(pcf_int), pcf_int);
95137 +       if (ret != sizeof(pcf_int)) {
95138 +               dev_info(pcf->dev, "Error reading INT registers\n");
95139 +
95140 +               /* We don't have an option but to retry. Because if
95141 +                * we don't, there won't be another interrupt edge.
95142 +                */
95143 +               goto reschedule;
95144 +       }
95145 +
95146 +       pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN,  0x04 );  /* defeat 8s death from lowsys on A5 */
95147 +
95148 +       /* We immediately read the usb and adapter status. We thus make sure
95149 +        * only of USBINS/USBREM and ADAPINS/ADPREM IRQ handlers are called */
95150 +       if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) {
95151 +               chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
95152 +               if (chgstat & (0x3 << 4))
95153 +                       pcf_int[0] &= ~(1 << PCF50633_INT1_USBREM);
95154 +               else
95155 +                       pcf_int[0] &= ~(1 << PCF50633_INT1_USBINS);
95156 +       }
95157 +
95158 +       if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) {
95159 +               chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
95160 +               if (chgstat & (0x3 << 4))
95161 +                       pcf_int[0] &= ~(1 << PCF50633_INT1_ADPREM);
95162 +               else
95163 +                       pcf_int[0] &= ~(1 << PCF50633_INT1_ADPINS);
95164 +       }
95165 +
95166 +       dev_info(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x "
95167 +                       "INT4=0x%02x INT5=0x%02x\n", pcf_int[0],
95168 +                       pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]);
95169 +
95170 +       /* Some revisions of the chip don't have a 8s standby mode on
95171 +        * ONKEY1S press. We try to manually do it in such cases. */
95172 +
95173 +       if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) {
95174 +               dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
95175 +                                                       pcf->onkey1s_held);
95176 +               if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT)
95177 +                       if (pcf->pdata->force_shutdown)
95178 +                               pcf->pdata->force_shutdown(pcf);
95179 +       }
95180 +
95181 +       if (pcf_int[2] & PCF50633_INT3_ONKEY1S) {
95182 +               dev_info(pcf->dev, "ONKEY1S held\n");
95183 +               pcf->onkey1s_held = 1 ;
95184 +
95185 +               /* Unmask IRQ_SECOND */
95186 +               pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M,
95187 +                                               PCF50633_INT1_SECOND);
95188 +
95189 +               /* Unmask IRQ_ONKEYR */
95190 +               pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M,
95191 +                                               PCF50633_INT2_ONKEYR);
95192 +       }
95193 +
95194 +       if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) {
95195 +               pcf->onkey1s_held = 0;
95196 +
95197 +               /* Mask SECOND and ONKEYR interrupts */
95198 +               if (pcf->mask_regs[0] & PCF50633_INT1_SECOND)
95199 +                       pcf50633_reg_set_bit_mask(pcf,
95200 +                                       PCF50633_REG_INT1M,
95201 +                                       PCF50633_INT1_SECOND,
95202 +                                       PCF50633_INT1_SECOND);
95203 +
95204 +               if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR)
95205 +                       pcf50633_reg_set_bit_mask(pcf,
95206 +                                       PCF50633_REG_INT2M,
95207 +                                       PCF50633_INT2_ONKEYR,
95208 +                                       PCF50633_INT2_ONKEYR);
95209 +       }
95210 +
95211 +       /* Have we just resumed ? */
95212 +       if (pcf->is_suspended) {
95213 +
95214 +               pcf->is_suspended = 0;
95215 +
95216 +               /* Set the resume reason filtering out non resumers */
95217 +               for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
95218 +                       pcf->resume_reason[i] = pcf_int[i] &
95219 +                                               pcf->pdata->resumers[i];
95220 +
95221 +               /* Make sure we don't pass on any ONKEY events to
95222 +                * userspace now */
95223 +               pcf_int[1] &= ~ (PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF);
95224 +       }
95225 +
95226 +       /* Unset masked interrupts */
95227 +       for (i = 0; i < ARRAY_SIZE(pcf_int); i++) {
95228 +               pcf_int[i] &= ~pcf->mask_regs[i];
95229 +               for (j = 0; j < 8 ; j++)
95230 +                       if (pcf_int[i] & (1 << j))
95231 +                               pcf50633_irq_call_handler(pcf, (i * 8) + j);
95232 +       }
95233 +
95234 +       put_device(pcf->dev);
95235 +
95236 +       enable_irq(pcf->irq);
95237 +
95238 +       return;
95239 +reschedule:
95240 +       schedule_work(&pcf->irq_work);
95241 +
95242 +       /* Don't put_device here. Will be used when we are rescheduled */
95243 +
95244 +       return;
95245 +}
95246 +
95247 +static irqreturn_t pcf50633_irq(int irq, void *data)
95248 +{
95249 +       struct pcf50633 *pcf = data;
95250 +
95251 +       get_device(pcf->dev);
95252 +
95253 +       disable_irq(pcf->irq);
95254 +
95255 +       schedule_work(&pcf->irq_work);
95256 +
95257 +       return IRQ_HANDLED;
95258 +}
95259 +
95260 +static void
95261 +pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name,
95262 +                                               struct platform_device **pdev)
95263 +{
95264 +       int ret;
95265 +
95266 +       *pdev = platform_device_alloc(name, -1);
95267 +
95268 +       if (!pdev) {
95269 +               dev_err(pcf->dev, "Falied to allocate %s\n", name);
95270 +               return;
95271 +       }
95272 +
95273 +       (*pdev)->dev.parent = pcf->dev;
95274 +       platform_set_drvdata(*pdev, pcf);
95275 +
95276 +       ret = platform_device_add(*pdev);
95277 +       if (ret != 0) {
95278 +               dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret);
95279 +               platform_device_put(*pdev);
95280 +               *pdev = NULL;
95281 +       }
95282 +}
95283 +
95284 +#ifdef CONFIG_PM
95285 +static int pcf50633_suspend(struct device *dev, pm_message_t state)
95286 +{
95287 +       struct pcf50633 *pcf;
95288 +       int ret, i;
95289 +       u8 res[5];
95290 +
95291 +       pcf = dev_get_drvdata(dev);
95292 +
95293 +       /* Make sure our interrupt handlers are not called
95294 +        * henceforth */
95295 +       disable_irq(pcf->irq);
95296 +
95297 +       /* Make sure that an IRQ worker has quit */
95298 +       cancel_work_sync(&pcf->irq_work);
95299 +
95300 +       /* Save the masks */
95301 +       ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M,
95302 +                               ARRAY_SIZE(pcf->suspend_irq_masks),
95303 +                                       pcf->suspend_irq_masks);
95304 +       if (ret < 0)
95305 +               dev_err(pcf->dev, "error saving irq masks\n");
95306 +
95307 +       /* Set interrupt masks. So that only those sources we want to wake
95308 +        * us up can
95309 +        */
95310 +       for (i = 0; i < ARRAY_SIZE(res); i++)
95311 +               res[i] = ~pcf->pdata->resumers[i];
95312 +
95313 +       pcf50633_write_block(pcf, PCF50633_REG_INT1M, ARRAY_SIZE(res), &res[0]);
95314 +
95315 +       pcf->is_suspended = 1;
95316 +
95317 +       return 0;
95318 +}
95319 +
95320 +static int pcf50633_resume(struct device *dev)
95321 +{
95322 +       struct pcf50633 *pcf;
95323 +
95324 +       pcf = dev_get_drvdata(dev);
95325 +
95326 +       /* Write the saved mask registers */
95327 +       pcf50633_write_block(pcf, PCF50633_REG_INT1M,
95328 +                               ARRAY_SIZE(pcf->suspend_irq_masks),
95329 +                                       pcf->suspend_irq_masks);
95330 +
95331 +       get_device(pcf->dev);
95332 +
95333 +       /*
95334 +        * Clear any pending interrupts and set resume reason if any.
95335 +        * This will leave with enable_irq()
95336 +        */
95337 +       pcf50633_irq_worker(&pcf->irq_work);
95338 +
95339 +       return 0;
95340 +}
95341 +#else
95342 +#define pcf50633_suspend NULL
95343 +#define pcf50633_resume NULL
95344 +#endif
95345 +
95346 +static int pcf50633_probe(struct i2c_client *client,
95347 +                               const struct i2c_device_id *ids)
95348 +{
95349 +       struct pcf50633 *pcf;
95350 +       struct pcf50633_platform_data *pdata;
95351 +       int i, ret = 0;
95352 +       int version;
95353 +       int variant;
95354 +
95355 +       pdata = client->dev.platform_data;
95356 +
95357 +       pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
95358 +       if (!pcf)
95359 +               return -ENOMEM;
95360 +
95361 +       pcf->pdata = pdata;
95362 +       pdata->pcf = pcf;
95363 +
95364 +       mutex_init(&pcf->lock);
95365 +
95366 +       i2c_set_clientdata(client, pcf);
95367 +       pcf->dev = &client->dev;
95368 +       pcf->i2c_client = client;
95369 +
95370 +       INIT_WORK(&pcf->irq_work, pcf50633_irq_worker);
95371 +
95372 +       version = pcf50633_reg_read(pcf, 0);
95373 +       if (version < 0) {
95374 +               dev_err(pcf->dev, "Unable to probe pcf50633\n");
95375 +               kfree(pcf);
95376 +               return -ENODEV;
95377 +       }
95378 +
95379 +       variant = pcf50633_reg_read(pcf, 1);
95380 +       if (variant < 0) {
95381 +               dev_err(pcf->dev, "Unable to probe pcf50633\n");
95382 +               kfree(pcf);
95383 +               return -ENODEV;
95384 +       }
95385 +
95386 +       dev_info(pcf->dev, "Probed device version %d variant %d\n",
95387 +                                                       version, variant);
95388 +
95389 +       /* Enable all inteerupts except RTC SECOND */
95390 +       pcf->mask_regs[0] = 0x80;
95391 +       pcf50633_reg_write(pcf, PCF50633_REG_INT1M, 0x80);
95392 +
95393 +       pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
95394 +       pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
95395 +       pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
95396 +       pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
95397 +
95398 +       pcf50633_client_dev_register(pcf, "pcf50633-input",
95399 +                                               &pcf->input.pdev);
95400 +       pcf50633_client_dev_register(pcf, "pcf50633-rtc",
95401 +                                               &pcf->rtc.pdev);
95402 +       pcf50633_client_dev_register(pcf, "pcf50633-mbc",
95403 +                                               &pcf->mbc.pdev);
95404 +       pcf50633_client_dev_register(pcf, "pcf50633-adc",
95405 +                                               &pcf->adc.pdev);
95406 +       for (i = 0; i < PCF50633_NUM_REGULATORS; i++) {
95407 +               struct platform_device *pdev;
95408 +
95409 +               pdev = platform_device_alloc("pcf50633-regltr", i);
95410 +               if (!pdev) {
95411 +                       dev_err(pcf->dev, "Cannot create regulator\n");
95412 +                       continue;
95413 +               }
95414 +
95415 +               pdev->dev.parent = pcf->dev;
95416 +               pdev->dev.platform_data = &pdata->reg_init_data[i];
95417 +               pdev->dev.driver_data = pcf;
95418 +               pcf->pmic.pdev[i] = pdev;
95419 +
95420 +               platform_device_add(pdev);
95421 +       }
95422 +
95423 +       pcf->irq = client->irq;
95424 +
95425 +       if (client->irq) {
95426 +               ret = request_irq(client->irq, pcf50633_irq,
95427 +                               IRQF_TRIGGER_LOW, "pcf50633", pcf);
95428 +
95429 +               if (ret) {
95430 +                       dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
95431 +                       goto err;
95432 +               }
95433 +       } else {
95434 +               dev_err(pcf->dev, "No IRQ configured\n");
95435 +               goto err;
95436 +       }
95437 +
95438 +       if (enable_irq_wake(client->irq) < 0)
95439 +               dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up "
95440 +                       "source in this hardware revision\n", client->irq);
95441 +
95442 +       ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
95443 +       if (ret)
95444 +               dev_err(pcf->dev, "error creating sysfs entries\n");
95445 +
95446 +       if (pdata->probe_done)
95447 +               pdata->probe_done(pcf);
95448 +
95449 +       return 0;
95450 +
95451 +err:
95452 +       kfree(pcf);
95453 +       return ret;
95454 +}
95455 +
95456 +static int pcf50633_remove(struct i2c_client *client)
95457 +{
95458 +       struct pcf50633 *pcf = i2c_get_clientdata(client);
95459 +
95460 +       free_irq(pcf->irq, pcf);
95461 +       kfree(pcf);
95462 +
95463 +       return 0;
95464 +}
95465 +
95466 +static struct i2c_device_id pcf50633_id_table[] = {
95467 +       {"pcf50633", 0x73},
95468 +};
95469 +
95470 +static struct i2c_driver pcf50633_driver = {
95471 +       .driver = {
95472 +               .name   = "pcf50633",
95473 +               .suspend = pcf50633_suspend,
95474 +               .resume = pcf50633_resume,
95475 +       },
95476 +       .id_table = pcf50633_id_table,
95477 +       .probe = pcf50633_probe,
95478 +       .remove = pcf50633_remove,
95479 +};
95480 +
95481 +static int __init pcf50633_init(void)
95482 +{
95483 +       return i2c_add_driver(&pcf50633_driver);
95484 +}
95485 +
95486 +static void pcf50633_exit(void)
95487 +{
95488 +       i2c_del_driver(&pcf50633_driver);
95489 +}
95490 +
95491 +MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU");
95492 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
95493 +MODULE_LICENSE("GPL");
95494 +
95495 +module_init(pcf50633_init);
95496 +module_exit(pcf50633_exit);
95497 --- /dev/null
95498 +++ b/drivers/mfd/pcf50633-gpio.c
95499 @@ -0,0 +1,100 @@
95500 +/* Philips PCF50633 GPIO Driver
95501 + *
95502 + * (C) 2006-2008 by Openmoko, Inc.
95503 + * Author: Balaji Rao <balajirrao@openmoko.org>
95504 + * All rights reserved.
95505 + *
95506 + * Broken down from monstrous PCF50633 driver mainly by
95507 + * Harald Welte, Andy Green and Werner Almesberger
95508 + *
95509 + * This program is free software; you can redistribute it and/or
95510 + * modify it under the terms of the GNU General Public License as
95511 + * published by the Free Software Foundation; either version 2 of
95512 + * the License, or (at your option) any later version.
95513 + *
95514 + * This program is distributed in the hope that it will be useful,
95515 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
95516 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
95517 + * GNU General Public License for more details.
95518 + *
95519 + * You should have received a copy of the GNU General Public License
95520 + * along with this program; if not, write to the Free Software
95521 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
95522 + * MA 02111-1307 USA
95523 + */
95524 +
95525 +#include <linux/mfd/pcf50633/core.h>
95526 +#include <linux/mfd/pcf50633/gpio.h>
95527 +#include <linux/mfd/pcf50633/pmic.h>
95528 +
95529 +void pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, int val)
95530 +{
95531 +       u8 reg;
95532 +
95533 +       reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
95534 +
95535 +       pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val);
95536 +}
95537 +EXPORT_SYMBOL_GPL(pcf50633_gpio_set);
95538 +
95539 +int pcf50633_gpio_get(struct pcf50633 *pcf, int gpio)
95540 +{
95541 +       u8 reg, val;
95542 +
95543 +       reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
95544 +       val = pcf50633_reg_read(pcf, reg) & 0x07;
95545 +
95546 +       return val;
95547 +}
95548 +EXPORT_SYMBOL_GPL(pcf50633_gpio_get);
95549 +
95550 +void pcf50633_gpio_invert_set(struct pcf50633 *pcf, int gpio, int invert)
95551 +{
95552 +       u8 val, reg;
95553 +
95554 +       reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
95555 +       val = !!invert << 3;
95556 +
95557 +       pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val);
95558 +}
95559 +EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_set);
95560 +
95561 +int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio)
95562 +{
95563 +       u8 reg, val;
95564 +
95565 +       reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
95566 +       val = pcf50633_reg_read(pcf, reg);
95567 +
95568 +       return val & (1 << 3);
95569 +}
95570 +EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_get);
95571 +
95572 +static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = {
95573 +       [PCF50633_REGULATOR_AUTO]       = PCF50633_REG_AUTOOUT,
95574 +       [PCF50633_REGULATOR_DOWN1]      = PCF50633_REG_DOWN1OUT,
95575 +       [PCF50633_REGULATOR_DOWN2]      = PCF50633_REG_DOWN2OUT,
95576 +       [PCF50633_REGULATOR_MEMLDO]     = PCF50633_REG_MEMLDOOUT,
95577 +       [PCF50633_REGULATOR_LDO1]       = PCF50633_REG_LDO1OUT,
95578 +       [PCF50633_REGULATOR_LDO2]       = PCF50633_REG_LDO2OUT,
95579 +       [PCF50633_REGULATOR_LDO3]       = PCF50633_REG_LDO3OUT,
95580 +       [PCF50633_REGULATOR_LDO4]       = PCF50633_REG_LDO4OUT,
95581 +       [PCF50633_REGULATOR_LDO5]       = PCF50633_REG_LDO5OUT,
95582 +       [PCF50633_REGULATOR_LDO6]       = PCF50633_REG_LDO6OUT,
95583 +       [PCF50633_REGULATOR_HCLDO]      = PCF50633_REG_HCLDOOUT,
95584 +};
95585 +
95586 +void pcf50633_gpio_power_supply_set(struct pcf50633 *pcf,
95587 +                                       int gpio, int regulator, int on)
95588 +{
95589 +       u8 reg, val, mask;
95590 +
95591 +       /* the *ENA register is always one after the *OUT register */
95592 +       reg = pcf50633_regulator_registers[regulator] + 1;
95593 +
95594 +       val = (!!on << (gpio - PCF50633_GPIO1));
95595 +       mask = (1 << (gpio - PCF50633_GPIO1));
95596 +
95597 +       pcf50633_reg_set_bit_mask(pcf, reg, mask, val);
95598 +}
95599 +EXPORT_SYMBOL_GPL(pcf50633_gpio_power_supply_set);
95600 --- /dev/null
95601 +++ b/drivers/mfd/pcf50633-i2c.c
95602 @@ -0,0 +1,3 @@
95603 +
95604 +};
95605 +
95606 --- a/drivers/misc/Kconfig
95607 +++ b/drivers/misc/Kconfig
95608 @@ -401,6 +401,11 @@ config THINKPAD_ACPI_HOTKEY_POLL
95609           If you are not sure, say Y here.  The driver enables polling only if
95610           it is strictly necessary to do so.
95611
95612 +config LOW_MEMORY_KILLER
95613 +    tristate "Low Memory Killer"
95614 +         ---help---
95615 +         Register processes to be killed when memory is low.
95616 +
95617  config ATMEL_SSC
95618         tristate "Device driver for Atmel SSC peripheral"
95619         depends on AVR32 || ARCH_AT91
95620 @@ -500,4 +505,9 @@ config SGI_GRU_DEBUG
95621
95622  source "drivers/misc/c2port/Kconfig"
95623
95624 +config MACH_NEO1973
95625 +       bool
95626 +       help
95627 +         Common machine code for Openmoko GTAxx hardware
95628 +
95629  endif # MISC_DEVICES
95630 --- /dev/null
95631 +++ b/drivers/misc/lowmemorykiller.c
95632 @@ -0,0 +1,119 @@
95633 +/* drivers/misc/lowmemorykiller.c
95634 + *
95635 + * Copyright (C) 2007-2008 Google, Inc.
95636 + *
95637 + * This software is licensed under the terms of the GNU General Public
95638 + * License version 2, as published by the Free Software Foundation, and
95639 + * may be copied, distributed, and modified under those terms.
95640 + *
95641 + * This program is distributed in the hope that it will be useful,
95642 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
95643 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
95644 + * GNU General Public License for more details.
95645 + *
95646 + */
95647 +
95648 +#include <linux/module.h>
95649 +#include <linux/kernel.h>
95650 +#include <linux/mm.h>
95651 +#include <linux/oom.h>
95652 +#include <linux/sched.h>
95653 +
95654 +static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask);
95655 +
95656 +static struct shrinker lowmem_shrinker = {
95657 +       .shrink = lowmem_shrink,
95658 +       .seeks = DEFAULT_SEEKS * 16
95659 +};
95660 +static uint32_t lowmem_debug_level = 2;
95661 +static int lowmem_adj[6] = {
95662 +       0,
95663 +       1,
95664 +       6,
95665 +       12,
95666 +};
95667 +static int lowmem_adj_size = 4;
95668 +static size_t lowmem_minfree[6] = {
95669 +       3*512, // 6MB
95670 +       2*1024, // 8MB
95671 +       4*1024, // 16MB
95672 +       16*1024, // 64MB
95673 +};
95674 +static int lowmem_minfree_size = 4;
95675 +
95676 +#define lowmem_print(level, x...) do { if(lowmem_debug_level >= (level)) printk(x); } while(0)
95677 +
95678 +module_param_named(cost, lowmem_shrinker.seeks, int, S_IRUGO | S_IWUSR);
95679 +module_param_array_named(adj, lowmem_adj, int, &lowmem_adj_size, S_IRUGO | S_IWUSR);
95680 +module_param_array_named(minfree, lowmem_minfree, uint, &lowmem_minfree_size, S_IRUGO | S_IWUSR);
95681 +module_param_named(debug_level, lowmem_debug_level, uint, S_IRUGO | S_IWUSR);
95682 +
95683 +static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask)
95684 +{
95685 +       struct task_struct *p;
95686 +       struct task_struct *selected = NULL;
95687 +       int rem = 0;
95688 +       int tasksize;
95689 +       int i;
95690 +       int min_adj = OOM_ADJUST_MAX + 1;
95691 +       int selected_tasksize = 0;
95692 +       int array_size = ARRAY_SIZE(lowmem_adj);
95693 +       int other_free = global_page_state(NR_FREE_PAGES) + global_page_state(NR_FILE_PAGES);
95694 +       if(lowmem_adj_size < array_size)
95695 +               array_size = lowmem_adj_size;
95696 +       if(lowmem_minfree_size < array_size)
95697 +               array_size = lowmem_minfree_size;
95698 +       for(i = 0; i < array_size; i++) {
95699 +               if(other_free < lowmem_minfree[i]) {
95700 +                       min_adj = lowmem_adj[i];
95701 +                       break;
95702 +               }
95703 +       }
95704 +       if(nr_to_scan > 0)
95705 +               lowmem_print(3, "lowmem_shrink %d, %x, ofree %d, ma %d\n", nr_to_scan, gfp_mask, other_free, min_adj);
95706 +       read_lock(&tasklist_lock);
95707 +       for_each_process(p) {
95708 +               if(p->oomkilladj >= 0 && p->mm) {
95709 +                       tasksize = get_mm_rss(p->mm);
95710 +                       if(nr_to_scan > 0 && tasksize > 0 && p->oomkilladj >= min_adj) {
95711 +                               if(selected == NULL ||
95712 +                                  p->oomkilladj > selected->oomkilladj ||
95713 +                                  (p->oomkilladj == selected->oomkilladj &&
95714 +                                   tasksize > selected_tasksize)) {
95715 +                                       selected = p;
95716 +                                       selected_tasksize = tasksize;
95717 +                                       lowmem_print(2, "select %d (%s), adj %d, size %d, to kill\n",
95718 +                                                    p->pid, p->comm, p->oomkilladj, tasksize);
95719 +                               }
95720 +                       }
95721 +                       rem += tasksize;
95722 +               }
95723 +       }
95724 +       if(selected != NULL) {
95725 +               lowmem_print(1, "send sigkill to %d (%s), adj %d, size %d\n",
95726 +                            selected->pid, selected->comm,
95727 +                            selected->oomkilladj, selected_tasksize);
95728 +               force_sig(SIGKILL, selected);
95729 +               rem -= selected_tasksize;
95730 +       }
95731 +       lowmem_print(4, "lowmem_shrink %d, %x, return %d\n", nr_to_scan, gfp_mask, rem);
95732 +       read_unlock(&tasklist_lock);
95733 +       return rem;
95734 +}
95735 +
95736 +static int __init lowmem_init(void)
95737 +{
95738 +       register_shrinker(&lowmem_shrinker);
95739 +       return 0;
95740 +}
95741 +
95742 +static void __exit lowmem_exit(void)
95743 +{
95744 +       unregister_shrinker(&lowmem_shrinker);
95745 +}
95746 +
95747 +module_init(lowmem_init);
95748 +module_exit(lowmem_exit);
95749 +
95750 +MODULE_LICENSE("GPL");
95751 +
95752 --- a/drivers/misc/Makefile
95753 +++ b/drivers/misc/Makefile
95754 @@ -33,3 +33,8 @@ obj-$(CONFIG_SGI_XP)          += sgi-xp/
95755  obj-$(CONFIG_SGI_GRU)          += sgi-gru/
95756  obj-$(CONFIG_HP_ILO)           += hpilo.o
95757  obj-$(CONFIG_C2PORT)           += c2port/
95758 +obj-$(CONFIG_MACH_SMDK6410)    += smdk6410-sleeptest.o
95759 +obj-$(CONFIG_LOW_MEMORY_KILLER)        += lowmemorykiller.o
95760 +obj-$(CONFIG_MACH_NEO1973)      += neo1973_version.o \
95761 +                                   neo1973_pm_host.o \
95762 +                                   neo1973_pm_resume_reason.o
95763 --- /dev/null
95764 +++ b/drivers/misc/neo1973_pm_charging_led.c
95765 @@ -0,0 +1,106 @@
95766 +/*
95767 + * Charging LED sysfs for the FIC Neo1973 GSM Phone
95768 + * (currently only implemented in GTA02 but ready for GTA01 implementation)
95769 + *
95770 + * (C) 2008 by Openmoko Inc.
95771 + * Author: Andy Green <andy@openmoko.com>
95772 + * All rights reserved.
95773 + *
95774 + * This program is free software; you can redistribute it and/or modify
95775 + * it under the terms of the GNU General Public License charging_led 2 as
95776 + * published by the Free Software Foundation
95777 + *
95778 + */
95779 +
95780 +#include <linux/module.h>
95781 +#include <linux/init.h>
95782 +#include <linux/kernel.h>
95783 +#include <linux/platform_device.h>
95784 +
95785 +#include <asm/hardware.h>
95786 +#include <asm/mach-types.h>
95787 +
95788 +#ifdef CONFIG_MACH_NEO1973_GTA02
95789 +#include <asm/arch/gta02.h>
95790 +
95791 +static enum neo1973_charging_led_modes charging_mode;
95792 +
95793 +static char *charging_led_mode_names[] = {
95794 +       "Disabled",
95795 +       "Aux LED",
95796 +       "Power LED"
95797 +};
95798 +
95799 +static ssize_t charging_led_read(struct device *dev,
95800 +                                struct device_attribute *attr, char *buf)
95801 +{
95802 +       return sprintf(buf, "0x%03X\n", gta02_get_pcb_revision());
95803 +}
95804 +
95805 +static ssize_t charging_led_read(struct device *dev,
95806 +                                struct device_attribute *attr, char *buf)
95807 +{
95808 +       return sprintf(buf, "0x%03X\n", gta02_get_pcb_revision());
95809 +}
95810 +
95811 +
95812 +static DEVICE_ATTR(pcb, 0644, charging_led_read, charging_led_write);
95813 +
95814 +static struct attribute *neo1973_charging_led_sysfs_entries[] = {
95815 +       &dev_attr_pcb.attr,
95816 +       NULL
95817 +};
95818 +
95819 +static struct attribute_group neo1973_charging_led_attr_group = {
95820 +       .name   = NULL,
95821 +       .attrs  = neo1973_charging_led_sysfs_entries,
95822 +};
95823 +
95824 +static int __init neo1973_charging_led_probe(struct platform_device *pdev)
95825 +{
95826 +       dev_info(&pdev->dev, "starting\n");
95827 +
95828 +       switch (machine_arch_type) {
95829 +#ifdef CONFIG_MACH_NEO1973_GTA01
95830 +       case MACH_TYPE_NEO1973_GTA01:
95831 +               return -EINVAL;
95832 +#endif /* CONFIG_MACH_NEO1973_GTA01 */
95833 +       default:
95834 +               break;
95835 +       }
95836 +
95837 +       return sysfs_create_group(&pdev->dev.kobj,
95838 +                                            &neo1973_charging_led_attr_group);
95839 +}
95840 +
95841 +static int neo1973_charging_led_remove(struct platform_device *pdev)
95842 +{
95843 +       sysfs_remove_group(&pdev->dev.kobj, &neo1973_charging_led_attr_group);
95844 +       return 0;
95845 +}
95846 +
95847 +static struct platform_driver neo1973_charging_led_driver = {
95848 +       .probe          = neo1973_charging_led_probe,
95849 +       .remove         = neo1973_charging_led_remove,
95850 +       .driver         = {
95851 +               .name           = "neo1973-charging-led",
95852 +       },
95853 +};
95854 +
95855 +static int __devinit neo1973_charging_led_init(void)
95856 +{
95857 +       return platform_driver_register(&neo1973_charging_led_driver);
95858 +}
95859 +
95860 +static void neo1973_charging_led_exit(void)
95861 +{
95862 +       platform_driver_unregister(&neo1973_charging_led_driver);
95863 +}
95864 +
95865 +module_init(neo1973_charging_led_init);
95866 +module_exit(neo1973_charging_led_exit);
95867 +
95868 +MODULE_LICENSE("GPL");
95869 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
95870 +MODULE_DESCRIPTION("Neo1973 PCB charging_led");
95871 +#endif
95872 --- /dev/null
95873 +++ b/drivers/misc/neo1973_pm_host.c
95874 @@ -0,0 +1,109 @@
95875 +/*
95876 + * Bluetooth PM code for the FIC Neo1973 GSM Phone
95877 + *
95878 + * (C) 2007 by Openmoko Inc.
95879 + * Author: Harald Welte <laforge@openmoko.org>
95880 + * All rights reserved.
95881 + *
95882 + * This program is free software; you can redistribute it and/or modify
95883 + * it under the terms of the GNU General Public License version 2 as
95884 + * published by the Free Software Foundation
95885 + *
95886 + */
95887 +
95888 +#include <linux/module.h>
95889 +#include <linux/init.h>
95890 +#include <linux/kernel.h>
95891 +#include <linux/platform_device.h>
95892 +
95893 +#include <mach/hardware.h>
95894 +#include <asm/mach-types.h>
95895 +
95896 +#ifdef CONFIG_MACH_NEO1973_GTA02
95897 +#include <mach/gta02.h>
95898 +#include <linux/mfd/pcf50633/gpio.h>
95899 +
95900 +static ssize_t pm_host_read(struct device *dev, struct device_attribute *attr,
95901 +                           char *buf)
95902 +{
95903 +       return sprintf(buf, "%d\n",
95904 +                      pcf50633_gpio_get(gta02_pcf_pdata.pcf, PCF50633_GPO)
95905 +                                               == PCF50633_GPOCFG_GPOSEL_1);
95906 +}
95907 +
95908 +static ssize_t pm_host_write(struct device *dev, struct device_attribute *attr,
95909 +                            const char *buf, size_t count)
95910 +{
95911 +       unsigned long on = simple_strtoul(buf, NULL, 10);
95912 +       u8 val;
95913 +
95914 +       if (on)
95915 +               val = PCF50633_GPOCFG_GPOSEL_1;
95916 +       else
95917 +               val = PCF50633_GPOCFG_GPOSEL_0;
95918 +
95919 +
95920 +       pcf50633_gpio_set(gta02_pcf_pdata.pcf, PCF50633_GPO, val);
95921 +
95922 +       return count;
95923 +}
95924 +
95925 +static DEVICE_ATTR(hostmode, 0644, pm_host_read, pm_host_write);
95926 +
95927 +static struct attribute *neo1973_pm_host_sysfs_entries[] = {
95928 +       &dev_attr_hostmode.attr,
95929 +       NULL
95930 +};
95931 +
95932 +static struct attribute_group neo1973_pm_host_attr_group = {
95933 +       .name   = NULL,
95934 +       .attrs  = neo1973_pm_host_sysfs_entries,
95935 +};
95936 +
95937 +static int __init neo1973_pm_host_probe(struct platform_device *pdev)
95938 +{
95939 +       dev_info(&pdev->dev, "starting\n");
95940 +
95941 +       switch (machine_arch_type) {
95942 +#ifdef CONFIG_MACH_NEO1973_GTA01
95943 +       case MACH_TYPE_NEO1973_GTA01:
95944 +               return -EINVAL;
95945 +#endif /* CONFIG_MACH_NEO1973_GTA01 */
95946 +       default:
95947 +               break;
95948 +       }
95949 +
95950 +       return sysfs_create_group(&pdev->dev.kobj, &neo1973_pm_host_attr_group);
95951 +}
95952 +
95953 +static int neo1973_pm_host_remove(struct platform_device *pdev)
95954 +{
95955 +       sysfs_remove_group(&pdev->dev.kobj, &neo1973_pm_host_attr_group);
95956 +       return 0;
95957 +}
95958 +
95959 +static struct platform_driver neo1973_pm_host_driver = {
95960 +       .probe          = neo1973_pm_host_probe,
95961 +       .remove         = neo1973_pm_host_remove,
95962 +       .driver         = {
95963 +               .name           = "neo1973-pm-host",
95964 +       },
95965 +};
95966 +
95967 +static int __devinit neo1973_pm_host_init(void)
95968 +{
95969 +       return platform_driver_register(&neo1973_pm_host_driver);
95970 +}
95971 +
95972 +static void neo1973_pm_host_exit(void)
95973 +{
95974 +       platform_driver_unregister(&neo1973_pm_host_driver);
95975 +}
95976 +
95977 +module_init(neo1973_pm_host_init);
95978 +module_exit(neo1973_pm_host_exit);
95979 +
95980 +MODULE_LICENSE("GPL");
95981 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
95982 +MODULE_DESCRIPTION("Neo1973 USB Host Power Management");
95983 +#endif
95984 --- /dev/null
95985 +++ b/drivers/misc/neo1973_pm_resume_reason.c
95986 @@ -0,0 +1,147 @@
95987 +/*
95988 + * Resume reason sysfs for the FIC Neo1973 GSM Phone
95989 + *
95990 + * (C) 2008 by Openmoko Inc.
95991 + * Author: Andy Green <andy@openmoko.com>
95992 + * All rights reserved.
95993 + *
95994 + * This program is free software; you can redistribute it and/or modify
95995 + * it under the terms of the GNU General Public License resume_reason 2 as
95996 + * published by the Free Software Foundation
95997 + *
95998 + */
95999 +
96000 +#include <linux/module.h>
96001 +#include <linux/init.h>
96002 +#include <linux/kernel.h>
96003 +#include <linux/platform_device.h>
96004 +#include <linux/io.h>
96005 +
96006 +#include <mach/hardware.h>
96007 +#include <asm/mach-types.h>
96008 +
96009 +#ifdef CONFIG_MACH_NEO1973_GTA02
96010 +#include <mach/gta02.h>
96011 +#include <linux/mfd/pcf50633/core.h>
96012 +#endif
96013 +
96014 +static unsigned int *gstatus4_mapped;
96015 +static char *resume_reasons[][17] = { { /* GTA01 */
96016 +       "EINT00_NULL",
96017 +       "EINT01_GSM",
96018 +       "EINT02_NULL",
96019 +       "EINT03_NULL",
96020 +       "EINT04_JACK",
96021 +       "EINT05_SDCARD",
96022 +       "EINT06_AUXKEY",
96023 +       "EINT07_HOLDKEY",
96024 +       "EINT08_NULL",
96025 +       "EINT09_NULL",
96026 +       "EINT10_NULL",
96027 +       "EINT11_NULL",
96028 +       "EINT12_NULL",
96029 +       "EINT13_NULL",
96030 +       "EINT14_NULL",
96031 +       "EINT15_NULL",
96032 +       NULL
96033 +}, { /* GTA02 */
96034 +       "EINT00_ACCEL1",
96035 +       "EINT01_GSM",
96036 +       "EINT02_BLUETOOTH",
96037 +       "EINT03_DEBUGBRD",
96038 +       "EINT04_JACK",
96039 +       "EINT05_WLAN",
96040 +       "EINT06_AUXKEY",
96041 +       "EINT07_HOLDKEY",
96042 +       "EINT08_ACCEL2",
96043 +       "EINT09_PMU",
96044 +       "EINT10_NULL",
96045 +       "EINT11_NULL",
96046 +       "EINT12_GLAMO",
96047 +       "EINT13_NULL",
96048 +       "EINT14_NULL",
96049 +       "EINT15_NULL",
96050 +       NULL
96051 +} };
96052 +
96053 +static ssize_t resume_reason_read(struct device *dev,
96054 +                                 struct device_attribute *attr,
96055 +                                 char *buf)
96056 +{
96057 +       int bit = 0;
96058 +       char *end = buf;
96059 +       int gta = !!machine_is_neo1973_gta02();
96060 +
96061 +       for (bit = 0; resume_reasons[gta][bit]; bit++) {
96062 +               if ((*gstatus4_mapped) & (1 << bit))
96063 +                       end += sprintf(end, "* %s\n", resume_reasons[gta][bit]);
96064 +               else
96065 +                       end += sprintf(end, "  %s\n", resume_reasons[gta][bit]);
96066 +
96067 +#ifdef CONFIG_MACH_NEO1973_GTA02
96068 +               if ((gta) && (bit == 9)); /* PMU */
96069 +//                     end += pcf50633_report_resumers(gta02_pcf_pdata.pcf, end);
96070 +#endif
96071 +       }
96072 +
96073 +       return end - buf;
96074 +}
96075 +
96076 +
96077 +static DEVICE_ATTR(resume_reason, 0644, resume_reason_read, NULL);
96078 +
96079 +static struct attribute *neo1973_resume_reason_sysfs_entries[] = {
96080 +       &dev_attr_resume_reason.attr,
96081 +       NULL
96082 +};
96083 +
96084 +static struct attribute_group neo1973_resume_reason_attr_group = {
96085 +       .name   = NULL,
96086 +       .attrs  = neo1973_resume_reason_sysfs_entries,
96087 +};
96088 +
96089 +static int __init neo1973_resume_reason_probe(struct platform_device *pdev)
96090 +{
96091 +       dev_info(&pdev->dev, "starting\n");
96092 +
96093 +       gstatus4_mapped = ioremap(0x560000BC /* GSTATUS4 */, 0x4);
96094 +       if (!gstatus4_mapped) {
96095 +               dev_err(&pdev->dev, "failed to ioremap() memory region\n");
96096 +               return -EINVAL;
96097 +       }
96098 +
96099 +       return sysfs_create_group(&pdev->dev.kobj,
96100 +                                           &neo1973_resume_reason_attr_group);
96101 +}
96102 +
96103 +static int neo1973_resume_reason_remove(struct platform_device *pdev)
96104 +{
96105 +       sysfs_remove_group(&pdev->dev.kobj, &neo1973_resume_reason_attr_group);
96106 +       iounmap(gstatus4_mapped);
96107 +       return 0;
96108 +}
96109 +
96110 +static struct platform_driver neo1973_resume_reason_driver = {
96111 +       .probe          = neo1973_resume_reason_probe,
96112 +       .remove         = neo1973_resume_reason_remove,
96113 +       .driver         = {
96114 +               .name           = "neo1973-resume",
96115 +       },
96116 +};
96117 +
96118 +static int __devinit neo1973_resume_reason_init(void)
96119 +{
96120 +       return platform_driver_register(&neo1973_resume_reason_driver);
96121 +}
96122 +
96123 +static void neo1973_resume_reason_exit(void)
96124 +{
96125 +       platform_driver_unregister(&neo1973_resume_reason_driver);
96126 +}
96127 +
96128 +module_init(neo1973_resume_reason_init);
96129 +module_exit(neo1973_resume_reason_exit);
96130 +
96131 +MODULE_LICENSE("GPL");
96132 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
96133 +MODULE_DESCRIPTION("Neo1973 resume_reason");
96134 --- /dev/null
96135 +++ b/drivers/misc/neo1973_pm_usbhost.c
96136 @@ -0,0 +1,132 @@
96137 +/*
96138 + * Bluetooth PM code for the FIC Neo1973 GSM Phone
96139 + *
96140 + * (C) 2007 by OpenMoko Inc.
96141 + * Author: Harald Welte <laforge@openmoko.org>
96142 + * All rights reserved.
96143 + *
96144 + * This program is free software; you can redistribute it and/or modify
96145 + * it under the terms of the GNU General Public License version 2 as
96146 + * published by the Free Software Foundation
96147 + *
96148 + */
96149 +
96150 +#include <linux/module.h>
96151 +#include <linux/init.h>
96152 +#include <linux/kernel.h>
96153 +#include <linux/platform_device.h>
96154 +
96155 +#include <asm/hardware.h>
96156 +#include <asm/mach-types.h>
96157 +
96158 +#ifdef CONFIG_MACH_NEO1973_GTA02
96159 +#include <asm/arch/gta02.h>
96160 +#include <linux/pcf50633.h>
96161 +#endif
96162 +
96163 +static ssize_t pm_usbhost_read(struct device *dev, struct device_attribute *attr,
96164 +                      char *buf)
96165 +{
96166 +       return sprintf(buf, "%d\n",
96167 +                      pcf50633_gpio_get(pcf50633_global, PCF50633_GPO));
96168 +}
96169 +
96170 +static ssize_t pm_usbhost_write(struct device *dev, struct device_attribute *attr,
96171 +                       const char *buf, size_t count)
96172 +{
96173 +       unsigned long on = simple_strtoul(buf, NULL, 10);
96174 +
96175 +       pcf50633_gpio_set(pcf50633_global, PCF50633_GPO, on);
96176 +
96177 +       return count;
96178 +}
96179 +
96180 +static DEVICE_ATTR(hostmode, 0644, pm_usbhost_read, pm_usbhost_write);
96181 +
96182 +#ifdef CONFIG_PM
96183 +static int neo1973_usbhost_suspend(struct platform_device *pdev, pm_message_t state)
96184 +{
96185 +       dev_dbg(&pdev->dev, "suspending\n");
96186 +       /* FIXME: The PMU should save the PMU status, and the GPIO code should
96187 +        * preserve the GPIO level, so there shouldn't be anything left to do
96188 +        * for us, should there? */
96189 +
96190 +       return 0;
96191 +}
96192 +
96193 +static int neo1973_usbhost_resume(struct platform_device *pdev)
96194 +{
96195 +       dev_dbg(&pdev->dev, "resuming\n");
96196 +
96197 +       return 0;
96198 +}
96199 +#else
96200 +#define neo1973_usbhost_suspend        NULL
96201 +#define neo1973_usbhost_resume NULL
96202 +#endif
96203 +
96204 +static struct attribute *neo1973_usbhost_sysfs_entries[] = {
96205 +       &dev_attr_hostmode.attr,
96206 +       NULL
96207 +};
96208 +
96209 +static struct attribute_group neo1973_usbhost_attr_group = {
96210 +       .name   = NULL,
96211 +       .attrs  = neo1973_usbhost_sysfs_entries,
96212 +};
96213 +
96214 +static int __init neo1973_usbhost_probe(struct platform_device *pdev)
96215 +{
96216 +       dev_info(&pdev->dev, "starting\n");
96217 +
96218 +       switch (machine_arch_type) {
96219 +
96220 +#ifdef CONFIG_MACH_NEO1973_GTA01
96221 +       case MACH_TYPE_NEO1973_GTA01:
96222 +               return -EINVAL;
96223 +#endif /* CONFIG_MACH_NEO1973_GTA01 */
96224 +
96225 +#ifdef CONFIG_MACH_NEO1973_GTA02
96226 +       case MACH_TYPE_NEO1973_GTA02:
96227 +/* race */
96228 +/*             pcf50633_gpio_set(pcf50633_global, PCF50633_GPO, 0); */
96229 +               break;
96230 +#endif /* CONFIG_MACH_NEO1973_GTA02 */
96231 +       }
96232 +
96233 +       return sysfs_create_group(&pdev->dev.kobj, &neo1973_usbhost_attr_group);
96234 +}
96235 +
96236 +static int neo1973_usbhost_remove(struct platform_device *pdev)
96237 +{
96238 +       sysfs_remove_group(&pdev->dev.kobj, &neo1973_usbhost_attr_group);
96239 +
96240 +       return 0;
96241 +}
96242 +
96243 +static struct platform_driver neo1973_usbhost_driver = {
96244 +       .probe          = neo1973_usbhost_probe,
96245 +       .remove         = neo1973_usbhost_remove,
96246 +       .suspend        = neo1973_usbhost_suspend,
96247 +       .resume         = neo1973_usbhost_resume,
96248 +       .driver         = {
96249 +               .name           = "neo1973-pm-host",
96250 +       },
96251 +};
96252 +
96253 +static int __devinit neo1973_usbhost_init(void)
96254 +{
96255 +       return platform_driver_register(&neo1973_usbhost_driver);
96256 +}
96257 +
96258 +static void neo1973_usbhost_exit(void)
96259 +{
96260 +       platform_driver_unregister(&neo1973_usbhost_driver);
96261 +}
96262 +
96263 +module_init(neo1973_usbhost_init);
96264 +module_exit(neo1973_usbhost_exit);
96265 +
96266 +MODULE_LICENSE("GPL");
96267 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
96268 +MODULE_DESCRIPTION("Neo1973 USB Host Power Management");
96269 --- /dev/null
96270 +++ b/drivers/misc/neo1973_version.c
96271 @@ -0,0 +1,90 @@
96272 +/*
96273 + * PCB version sysfs for the FIC Neo1973 GSM Phone
96274 + *
96275 + * (C) 2007 by Openmoko Inc.
96276 + * Author: Andy Green <andy@openmoko.com>
96277 + * All rights reserved.
96278 + *
96279 + * This program is free software; you can redistribute it and/or modify
96280 + * it under the terms of the GNU General Public License version 2 as
96281 + * published by the Free Software Foundation
96282 + *
96283 + */
96284 +
96285 +#include <linux/module.h>
96286 +#include <linux/init.h>
96287 +#include <linux/kernel.h>
96288 +#include <linux/platform_device.h>
96289 +
96290 +#include <mach/hardware.h>
96291 +#include <asm/mach-types.h>
96292 +
96293 +#ifdef CONFIG_MACH_NEO1973_GTA02
96294 +#include <mach/gta02.h>
96295 +
96296 +static ssize_t version_read(struct device *dev, struct device_attribute *attr,
96297 +                           char *buf)
96298 +{
96299 +       return sprintf(buf, "0x%03X\n", gta02_get_pcb_revision());
96300 +}
96301 +
96302 +
96303 +static DEVICE_ATTR(pcb, 0644, version_read, NULL);
96304 +
96305 +static struct attribute *neo1973_version_sysfs_entries[] = {
96306 +       &dev_attr_pcb.attr,
96307 +       NULL
96308 +};
96309 +
96310 +static struct attribute_group neo1973_version_attr_group = {
96311 +       .name   = NULL,
96312 +       .attrs  = neo1973_version_sysfs_entries,
96313 +};
96314 +
96315 +static int __init neo1973_version_probe(struct platform_device *pdev)
96316 +{
96317 +       dev_info(&pdev->dev, "starting\n");
96318 +
96319 +       switch (machine_arch_type) {
96320 +#ifdef CONFIG_MACH_NEO1973_GTA01
96321 +       case MACH_TYPE_NEO1973_GTA01:
96322 +               return -EINVAL;
96323 +#endif /* CONFIG_MACH_NEO1973_GTA01 */
96324 +       default:
96325 +               break;
96326 +       }
96327 +
96328 +       return sysfs_create_group(&pdev->dev.kobj, &neo1973_version_attr_group);
96329 +}
96330 +
96331 +static int neo1973_version_remove(struct platform_device *pdev)
96332 +{
96333 +       sysfs_remove_group(&pdev->dev.kobj, &neo1973_version_attr_group);
96334 +       return 0;
96335 +}
96336 +
96337 +static struct platform_driver neo1973_version_driver = {
96338 +       .probe          = neo1973_version_probe,
96339 +       .remove         = neo1973_version_remove,
96340 +       .driver         = {
96341 +               .name           = "neo1973-version",
96342 +       },
96343 +};
96344 +
96345 +static int __devinit neo1973_version_init(void)
96346 +{
96347 +       return platform_driver_register(&neo1973_version_driver);
96348 +}
96349 +
96350 +static void neo1973_version_exit(void)
96351 +{
96352 +       platform_driver_unregister(&neo1973_version_driver);
96353 +}
96354 +
96355 +module_init(neo1973_version_init);
96356 +module_exit(neo1973_version_exit);
96357 +
96358 +MODULE_LICENSE("GPL");
96359 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
96360 +MODULE_DESCRIPTION("Neo1973 PCB version");
96361 +#endif
96362 --- /dev/null
96363 +++ b/drivers/misc/smdk6410-sleeptest.c
96364 @@ -0,0 +1,65 @@
96365 +/* linux/drivers/misc/smdk6410-sleeptest.c
96366 + *
96367 + * Copyright 2008 Simtec Electronics
96368 + *     Ben Dooks <ben@simtec.co.uk>
96369 + *     http://armlinux.simtec.co.uk/
96370 + *
96371 + * This program is free software; you can redistribute it and/or modify
96372 + * it under the terms of the GNU General Public License version 2 as
96373 + * published by the Free Software Foundation.
96374 +*/
96375 +
96376 +#include <linux/init.h>
96377 +#include <linux/kernel.h>
96378 +#include <linux/module.h>
96379 +#include <linux/init.h>
96380 +#include <linux/gpio.h>
96381 +#include <linux/err.h>
96382 +#include <linux/interrupt.h>
96383 +
96384 +#include <plat/gpio-cfg.h>
96385 +
96386 +static irqreturn_t sleep_action(int irq, void *pw)
96387 +{
96388 +       printk(KERN_INFO "%s: irq %d\n", __func__, irq);
96389 +       return IRQ_HANDLED;
96390 +}
96391 +
96392 +static void sleep_setup(unsigned int irq, unsigned int gpio)
96393 +{
96394 +       int ret;
96395 +
96396 +       WARN_ON(s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)) < 0);
96397 +       WARN_ON(s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP) < 0);
96398 +
96399 +       ret = request_irq(irq, sleep_action, IRQF_TRIGGER_FALLING,
96400 +                         "sleep", NULL);
96401 +       if (ret < 0)
96402 +               printk(KERN_ERR "%s: request_irq() failed\n", __func__);
96403 +
96404 +       ret = set_irq_wake(irq, 1);
96405 +       if (ret < 0)
96406 +               printk(KERN_ERR "%s: set_irq_wake() failed\n", __func__);
96407 +}
96408 +
96409 +static void sleep_led(unsigned int gpio)
96410 +{
96411 +       gpio_request(gpio, "sleep led");
96412 +       gpio_direction_output(gpio, 0);
96413 +}
96414 +
96415 +static __init int smdk6410_sleeptest_init(void)
96416 +{
96417 +       sleep_setup(IRQ_EINT(10), S3C64XX_GPN(10));
96418 +       sleep_led(S3C64XX_GPN(15));
96419 +       sleep_led(S3C64XX_GPN(14));
96420 +       sleep_led(S3C64XX_GPN(13));
96421 +       sleep_led(S3C64XX_GPN(12));
96422 +
96423 +       return 0;
96424 +}
96425 +
96426 +module_init(smdk6410_sleeptest_init);
96427 +
96428 +MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
96429 +MODULE_LICENSE("GPL");
96430 --- a/drivers/mmc/core/core.c
96431 +++ b/drivers/mmc/core/core.c
96432 @@ -57,10 +57,11 @@ static int mmc_schedule_delayed_work(str
96433  /*
96434   * Internal function. Flush all scheduled work from the MMC work queue.
96435   */
96436 -static void mmc_flush_scheduled_work(void)
96437 +void mmc_flush_scheduled_work(void)
96438  {
96439         flush_workqueue(workqueue);
96440  }
96441 +EXPORT_SYMBOL_GPL(mmc_flush_scheduled_work);
96442
96443  /**
96444   *     mmc_request_done - finish processing an MMC request
96445 @@ -495,7 +496,13 @@ void mmc_set_timing(struct mmc_host *hos
96446   */
96447  static void mmc_power_up(struct mmc_host *host)
96448  {
96449 -       int bit = fls(host->ocr_avail) - 1;
96450 +       int bit;
96451 +
96452 +       /* If ocr is set, we use it */
96453 +       if (host->ocr)
96454 +               bit = ffs(host->ocr) - 1;
96455 +       else
96456 +               bit = fls(host->ocr_avail) - 1;
96457
96458         host->ios.vdd = bit;
96459         if (mmc_host_is_spi(host)) {
96460 --- a/drivers/mmc/host/Kconfig
96461 +++ b/drivers/mmc/host/Kconfig
96462 @@ -48,6 +48,18 @@ config MMC_SDHCI_PCI
96463
96464           If unsure, say N.
96465
96466 +config MMC_SDHCI_S3C
96467 +       tristate "SDHCI support on Samsung S3C SoC"
96468 +       depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX)
96469 +       help
96470 +         This selects the Secure Digital Host Controller Interface (SDHCI)
96471 +         often referrered to as the HSMMC block in some of the Samsung S3C
96472 +         range of SoC.
96473 +
96474 +         If you have a controller with this interface, say Y or M here.
96475 +
96476 +         If unsure, say N.
96477 +
96478  config MMC_RICOH_MMC
96479         tristate "Ricoh MMC Controller Disabler  (EXPERIMENTAL)"
96480         depends on MMC_SDHCI_PCI
96481 --- a/drivers/mmc/host/Makefile
96482 +++ b/drivers/mmc/host/Makefile
96483 @@ -11,6 +11,7 @@ obj-$(CONFIG_MMC_PXA)         += pxamci.o
96484  obj-$(CONFIG_MMC_IMX)          += imxmmc.o
96485  obj-$(CONFIG_MMC_SDHCI)                += sdhci.o
96486  obj-$(CONFIG_MMC_SDHCI_PCI)    += sdhci-pci.o
96487 +obj-$(CONFIG_MMC_SDHCI_S3C)    += sdhci-s3c.o
96488  obj-$(CONFIG_MMC_RICOH_MMC)    += ricoh_mmc.o
96489  obj-$(CONFIG_MMC_WBSD)         += wbsd.o
96490  obj-$(CONFIG_MMC_AU1X)         += au1xmmc.o
96491 --- a/drivers/mmc/host/s3cmci.c
96492 +++ b/drivers/mmc/host/s3cmci.c
96493 @@ -2,6 +2,7 @@
96494   *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
96495   *
96496   *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
96497 + *  Copyright (C) 2007 Harald Welte <laforge@gnumonks.org>
96498   *
96499   * Current driver maintained by Ben Dooks and Simtec Electronics
96500   *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
96501 @@ -25,7 +26,15 @@
96502  #include <mach/regs-sdi.h>
96503  #include <mach/regs-gpio.h>
96504
96505 -#include <asm/plat-s3c24xx/mci.h>
96506 +#include <plat/mci.h>
96507 +
96508 +#include <asm/dma.h>
96509 +#include <asm/dma-mapping.h>
96510 +
96511 +#include <asm/io.h>
96512 +#include <mach/regs-gpio.h>
96513 +#include <mach/mci.h>
96514 +#include <mach/dma.h>
96515
96516  #include "s3cmci.h"
96517
96518 @@ -47,6 +56,9 @@ static const int dbgmap_err   = dbg_fail
96519  static const int dbgmap_info  = dbg_info | dbg_conf;
96520  static const int dbgmap_debug = dbg_err | dbg_debug;
96521
96522 +static int f_max = -1; /* override maximum frequency limit */
96523 +static int persist; /* keep interface alive across suspend/resume */
96524 +
96525  #define dbg(host, channels, args...)             \
96526         do {                                      \
96527         if (dbgmap_err & channels)                \
96528 @@ -280,8 +292,11 @@ static void do_pio_read(struct s3cmci_ho
96529                  * an even multiple of 4. */
96530                 if (fifo >= host->pio_bytes)
96531                         fifo = host->pio_bytes;
96532 -               else
96533 +               else {
96534                         fifo -= fifo & 3;
96535 +                       if (!fifo)
96536 +                               break;
96537 +               }
96538
96539                 host->pio_bytes -= fifo;
96540                 host->pio_count += fifo;
96541 @@ -353,8 +368,11 @@ static void do_pio_write(struct s3cmci_h
96542                  * words, so round down to an even multiple of 4. */
96543                 if (fifo >= host->pio_bytes)
96544                         fifo = host->pio_bytes;
96545 -               else
96546 +               else {
96547                         fifo -= fifo & 3;
96548 +                       if (!fifo)
96549 +                               break;
96550 +               }
96551
96552                 host->pio_bytes -= fifo;
96553                 host->pio_count += fifo;
96554 @@ -373,7 +391,6 @@ static void pio_tasklet(unsigned long da
96555  {
96556         struct s3cmci_host *host = (struct s3cmci_host *) data;
96557
96558 -
96559         disable_irq(host->irq);
96560
96561         if (host->pio_active == XFER_WRITE)
96562 @@ -614,7 +631,6 @@ irq_out:
96563
96564         spin_unlock_irqrestore(&host->complete_lock, iflags);
96565         return IRQ_HANDLED;
96566 -
96567  }
96568
96569  /*
96570 @@ -1027,6 +1043,7 @@ static void s3cmci_send_request(struct m
96571                         dbg(host, dbg_err, "data prepare error %d\n", res);
96572                         cmd->error = res;
96573                         cmd->data->error = res;
96574 +                       cmd->data->error = -EIO;
96575
96576                         mmc_request_done(mmc, mrq);
96577                         return;
96578 @@ -1264,10 +1281,8 @@ static int __devinit s3cmci_probe(struct
96579         host->is2440    = is2440;
96580
96581         host->pdata = pdev->dev.platform_data;
96582 -       if (!host->pdata) {
96583 -               pdev->dev.platform_data = &s3cmci_def_pdata;
96584 +       if (!host->pdata)
96585                 host->pdata = &s3cmci_def_pdata;
96586 -       }
96587
96588         spin_lock_init(&host->complete_lock);
96589         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
96590 @@ -1380,6 +1395,18 @@ static int __devinit s3cmci_probe(struct
96591         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
96592         mmc->f_max      = host->clk_rate / host->clk_div;
96593
96594 +       if (f_max >= 0) {
96595 +               unsigned f = f_max;
96596 +
96597 +               if (f < mmc->f_min)
96598 +                       f = mmc->f_min;
96599 +               if (mmc->f_max > f) {
96600 +                       dev_info(&pdev->dev, "f_max lowered from %u to %u Hz\n",
96601 +                           mmc->f_max, f);
96602 +                       mmc->f_max = f;
96603 +               }
96604 +       }
96605 +
96606         if (host->pdata->ocr_avail)
96607                 mmc->ocr_avail = host->pdata->ocr_avail;
96608
96609 @@ -1492,18 +1519,60 @@ static int __devinit s3cmci_2440_probe(s
96610
96611  #ifdef CONFIG_PM
96612
96613 +static int save_regs(struct mmc_host *mmc)
96614 +{
96615 +       struct s3cmci_host *host = mmc_priv(mmc);
96616 +       unsigned long flags;
96617 +       unsigned from;
96618 +       u32 *to = host->saved;
96619 +
96620 +       mmc_flush_scheduled_work();
96621 +
96622 +       local_irq_save(flags);
96623 +       for (from = S3C2410_SDICON; from != S3C2410_SDIIMSK+4; from += 4)
96624 +               if (from != host->sdidata)
96625 +                       *to++ = readl(host->base + from);
96626 +       BUG_ON(to-host->saved != ARRAY_SIZE(host->saved));
96627 +       local_irq_restore(flags);
96628 +
96629 +       return 0;
96630 +}
96631 +
96632 +static int restore_regs(struct mmc_host *mmc)
96633 +{
96634 +       struct s3cmci_host *host = mmc_priv(mmc);
96635 +       unsigned long flags;
96636 +       unsigned to;
96637 +       u32 *from = host->saved;
96638 +
96639 +       /*
96640 +        * Before we begin with the necromancy, make sure we don't
96641 +        * inadvertently start something we'll regret microseconds later.
96642 +        */
96643 +       from[S3C2410_SDICMDCON - S3C2410_SDICON] = 0;
96644 +
96645 +       local_irq_save(flags);
96646 +       for (to = S3C2410_SDICON; to != S3C2410_SDIIMSK+4; to += 4)
96647 +               if (to != host->sdidata)
96648 +                       writel(*from++, host->base + to);
96649 +       BUG_ON(from-host->saved != ARRAY_SIZE(host->saved));
96650 +       local_irq_restore(flags);
96651 +
96652 +       return 0;
96653 +}
96654 +
96655  static int s3cmci_suspend(struct platform_device *dev, pm_message_t state)
96656  {
96657         struct mmc_host *mmc = platform_get_drvdata(dev);
96658
96659 -       return  mmc_suspend_host(mmc, state);
96660 +       return persist ? save_regs(mmc) : mmc_suspend_host(mmc, state);
96661  }
96662
96663  static int s3cmci_resume(struct platform_device *dev)
96664  {
96665         struct mmc_host *mmc = platform_get_drvdata(dev);
96666
96667 -       return mmc_resume_host(mmc);
96668 +       return persist ? restore_regs(mmc) : mmc_resume_host(mmc);
96669  }
96670
96671  #else /* CONFIG_PM */
96672 @@ -1561,9 +1630,13 @@ static void __exit s3cmci_exit(void)
96673  module_init(s3cmci_init);
96674  module_exit(s3cmci_exit);
96675
96676 +module_param(f_max, int, 0644);
96677 +module_param(persist, int, 0644);
96678 +
96679  MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
96680  MODULE_LICENSE("GPL v2");
96681  MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
96682  MODULE_ALIAS("platform:s3c2410-sdi");
96683  MODULE_ALIAS("platform:s3c2412-sdi");
96684  MODULE_ALIAS("platform:s3c2440-sdi");
96685 +
96686 --- a/drivers/mmc/host/s3cmci.h
96687 +++ b/drivers/mmc/host/s3cmci.h
96688 @@ -8,6 +8,9 @@
96689   * published by the Free Software Foundation.
96690   */
96691
96692 +
96693 +#include <mach/regs-sdi.h>
96694 +
96695  /* FIXME: DMA Resource management ?! */
96696  #define S3CMCI_DMA 0
96697
96698 @@ -68,6 +71,13 @@ struct s3cmci_host {
96699         unsigned int            ccnt, dcnt;
96700         struct tasklet_struct   pio_tasklet;
96701
96702 +       /*
96703 +        * Here's where we save the registers during suspend. Note that we skip
96704 +        * SDIDATA, which is at different positions on 2410 and 2440, so
96705 +        * there's no "+1" in the array size.
96706 +        */
96707 +       u32                     saved[(S3C2410_SDIIMSK-S3C2410_SDICON)/4];
96708 +
96709  #ifdef CONFIG_CPU_FREQ
96710         struct notifier_block   freq_transition;
96711  #endif
96712 --- a/drivers/mmc/host/sdhci.c
96713 +++ b/drivers/mmc/host/sdhci.c
96714 @@ -73,6 +73,11 @@ static void sdhci_dumpregs(struct sdhci_
96715                 readl(host->ioaddr + SDHCI_CAPABILITIES),
96716                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
96717
96718 +       if (host->flags & SDHCI_USE_ADMA)
96719 +               printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
96720 +                      readl(host->ioaddr + SDHCI_ADMA_ERROR),
96721 +                      readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
96722 +
96723         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
96724  }
96725
96726 @@ -731,6 +736,23 @@ static void sdhci_set_transfer_mode(stru
96727         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
96728  }
96729
96730 +static void shdci_check_dma_overrun(struct sdhci_host *host, struct mmc_data *data)
96731 +{
96732 +       u32 dma_pos = readl(host->ioaddr + SDHCI_DMA_ADDRESS);
96733 +       u32 dma_start = sg_dma_address(data->sg);
96734 +       u32 dma_end = dma_start + data->sg->length;
96735 +
96736 +       /* Test whether we ended up moving more data than
96737 +        * was originally requested. */
96738 +
96739 +       if (dma_pos <= dma_end)
96740 +               return;
96741 +
96742 +       printk(KERN_ERR "%s: dma overrun, dma %08x, req %08x..%08x\n",
96743 +              mmc_hostname(host->mmc), dma_pos,
96744 +              dma_start, dma_end);
96745 +}
96746 +
96747  static void sdhci_finish_data(struct sdhci_host *host)
96748  {
96749         struct mmc_data *data;
96750 @@ -744,6 +766,8 @@ static void sdhci_finish_data(struct sdh
96751                 if (host->flags & SDHCI_USE_ADMA)
96752                         sdhci_adma_table_post(host, data);
96753                 else {
96754 +                       shdci_check_dma_overrun(host, data);
96755 +
96756                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
96757                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
96758                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
96759 @@ -883,13 +907,18 @@ static void sdhci_finish_command(struct
96760
96761  static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
96762  {
96763 +       if (clock == host->clock)
96764 +               return;
96765 +
96766 +       host->ops->change_clock(host, clock);
96767 +}
96768 +
96769 +void sdhci_change_clock(struct sdhci_host *host, unsigned int clock)
96770 +{
96771         int div;
96772         u16 clk;
96773         unsigned long timeout;
96774
96775 -       if (clock == host->clock)
96776 -               return;
96777 -
96778         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
96779
96780         if (clock == 0)
96781 @@ -926,6 +955,8 @@ out:
96782         host->clock = clock;
96783  }
96784
96785 +EXPORT_SYMBOL_GPL(sdhci_set_clock);
96786 +
96787  static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
96788  {
96789         u8 pwr;
96790 @@ -999,12 +1030,13 @@ static void sdhci_request(struct mmc_hos
96791  #endif
96792
96793         host->mrq = mrq;
96794 -
96795 +/*
96796         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
96797                 || (host->flags & SDHCI_DEVICE_DEAD)) {
96798                 host->mrq->cmd->error = -ENOMEDIUM;
96799                 tasklet_schedule(&host->finish_tasklet);
96800         } else
96801 +*/
96802                 sdhci_send_command(host, mrq->cmd);
96803
96804         mmiowb();
96805 @@ -1033,6 +1065,9 @@ static void sdhci_set_ios(struct mmc_hos
96806                 sdhci_init(host);
96807         }
96808
96809 +       if (host->ops->set_ios)
96810 +               host->ops->set_ios(host, ios);
96811 +
96812         sdhci_set_clock(host, ios->clock);
96813
96814         if (ios->power_mode == MMC_POWER_OFF)
96815 @@ -1136,7 +1171,7 @@ static void sdhci_tasklet_card(unsigned
96816         host = (struct sdhci_host*)param;
96817
96818         spin_lock_irqsave(&host->lock, flags);
96819 -
96820 +/*
96821         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
96822                 if (host->mrq) {
96823                         printk(KERN_ERR "%s: Card removed during transfer!\n",
96824 @@ -1151,7 +1186,7 @@ static void sdhci_tasklet_card(unsigned
96825                         tasklet_schedule(&host->finish_tasklet);
96826                 }
96827         }
96828 -
96829 +*/
96830         spin_unlock_irqrestore(&host->lock, flags);
96831
96832         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
96833 @@ -1283,11 +1318,24 @@ static void sdhci_cmd_irq(struct sdhci_h
96834          *       controllers.
96835          */
96836         if (host->cmd->flags & MMC_RSP_BUSY) {
96837 +               u32 present;
96838 +
96839                 if (host->cmd->data)
96840                         DBG("Cannot wait for busy signal when also "
96841                                 "doing a data transfer");
96842 -               else
96843 +               else if (!(host->quirks & SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY))
96844                         return;
96845 +
96846 +               /* The Samsung SDHCI does not seem to provide an INT_DATA_END
96847 +                * when the system goes non-busy, so check the state of the
96848 +                * transfer by reading SDHCI_PRESENT_STATE to see if the
96849 +                * controller is ready
96850 +                */
96851 +
96852 +               present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
96853 +               DBG("busy? present %08x, intstat %08x\n", present, intmask);
96854 +
96855 +               /* fall through and take the SDHCI_INT_RESPONSE */
96856         }
96857
96858         if (intmask & SDHCI_INT_RESPONSE)
96859 @@ -1604,17 +1652,23 @@ int sdhci_add_host(struct sdhci_host *ho
96860                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
96861         }
96862
96863 -       host->max_clk =
96864 -               (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
96865 +       if (host->ops->get_max_clock)
96866 +               host->max_clk = host->ops->get_max_clock(host);
96867 +       else {
96868 +               host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
96869 +               host->max_clk *= 1000000;
96870 +       }
96871         if (host->max_clk == 0) {
96872                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
96873                         "frequency.\n", mmc_hostname(mmc));
96874                 return -ENODEV;
96875         }
96876 -       host->max_clk *= 1000000;
96877
96878 -       host->timeout_clk =
96879 -               (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
96880 +       if (host->ops->get_timeout_clock)
96881 +               host->timeout_clk = host->ops->get_timeout_clock(host);
96882 +       else
96883 +               host->timeout_clk =
96884 +                       (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
96885         if (host->timeout_clk == 0) {
96886                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
96887                         "frequency.\n", mmc_hostname(mmc));
96888 --- a/drivers/mmc/host/sdhci.h
96889 +++ b/drivers/mmc/host/sdhci.h
96890 @@ -57,6 +57,7 @@
96891  #define  SDHCI_DATA_AVAILABLE  0x00000800
96892  #define  SDHCI_CARD_PRESENT    0x00010000
96893  #define  SDHCI_WRITE_PROTECT   0x00080000
96894 +#define  SDHCI_DATA_BIT(x)     (1 << ((x) + 20))
96895
96896  #define SDHCI_HOST_CONTROL     0x28
96897  #define  SDHCI_CTRL_LED                0x01
96898 @@ -210,6 +211,8 @@ struct sdhci_host {
96899  #define SDHCI_QUIRK_BROKEN_SMALL_PIO                   (1<<13)
96900  /* Controller supports high speed but doesn't have the caps bit set */
96901  #define SDHCI_QUIRK_FORCE_HIGHSPEED                    (1<<14)
96902 +/* Controller does not provide transfer-complete interrupt when not busy */
96903 +#define SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY               (1<<15)
96904
96905         int                     irq;            /* Device IRQ */
96906         void __iomem *          ioaddr;         /* Mapped address */
96907 @@ -267,6 +270,14 @@ struct sdhci_host {
96908
96909  struct sdhci_ops {
96910         int             (*enable_dma)(struct sdhci_host *host);
96911 +       unsigned int    (*get_max_clock)(struct sdhci_host *host);
96912 +       unsigned int    (*get_timeout_clock)(struct sdhci_host *host);
96913 +
96914 +       void            (*change_clock)(struct sdhci_host *host,
96915 +                                       unsigned int clock);
96916 +
96917 +       void            (*set_ios)(struct sdhci_host *host,
96918 +                                  struct mmc_ios *ios);
96919  };
96920
96921
96922 @@ -274,6 +285,8 @@ extern struct sdhci_host *sdhci_alloc_ho
96923         size_t priv_size);
96924  extern void sdhci_free_host(struct sdhci_host *host);
96925
96926 +extern void sdhci_change_clock(struct sdhci_host *host, unsigned int clock);
96927 +
96928  static inline void *sdhci_priv(struct sdhci_host *host)
96929  {
96930         return (void *)host->private;
96931 --- a/drivers/mmc/host/sdhci-pci.c
96932 +++ b/drivers/mmc/host/sdhci-pci.c
96933 @@ -391,6 +391,7 @@ static int sdhci_pci_enable_dma(struct s
96934
96935  static struct sdhci_ops sdhci_pci_ops = {
96936         .enable_dma     = sdhci_pci_enable_dma,
96937 +       .change_clock   = sdhci_change_clock,
96938  };
96939
96940  /*****************************************************************************\
96941 --- /dev/null
96942 +++ b/drivers/mmc/host/sdhci-s3c.c
96943 @@ -0,0 +1,419 @@
96944 +/* linux/drivers/mmc/host/sdhci-s3c.c
96945 + *
96946 + * Copyright 2008 Openmoko Inc.
96947 + * Copyright 2008 Simtec Electronics
96948 + *      Ben Dooks <ben@simtec.co.uk>
96949 + *      http://armlinux.simtec.co.uk/
96950 + *
96951 + * SDHCI (HSMMC) support for Samsung SoC
96952 + *
96953 + * This program is free software; you can redistribute it and/or modify
96954 + * it under the terms of the GNU General Public License version 2 as
96955 + * published by the Free Software Foundation.
96956 + */
96957 +
96958 +#include <linux/delay.h>
96959 +#include <linux/dma-mapping.h>
96960 +#include <linux/platform_device.h>
96961 +#include <linux/clk.h>
96962 +#include <linux/io.h>
96963 +
96964 +#include <linux/mmc/host.h>
96965 +
96966 +#include <plat/regs-sdhci.h>
96967 +#include <plat/sdhci.h>
96968 +
96969 +#include "sdhci.h"
96970 +
96971 +#define MAX_BUS_CLK    (4)
96972 +
96973 +struct sdhci_s3c {
96974 +       struct sdhci_host       *host;
96975 +       struct platform_device  *pdev;
96976 +       struct resource         *ioarea;
96977 +       struct s3c_sdhci_platdata *pdata;
96978 +       unsigned int            cur_clk;
96979 +
96980 +       struct clk              *clk_io;        /* clock for io bus */
96981 +       struct clk              *clk_bus[MAX_BUS_CLK];
96982 +};
96983 +
96984 +static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
96985 +{
96986 +       return sdhci_priv(host);
96987 +}
96988 +
96989 +static u32 get_curclk(u32 ctrl2)
96990 +{
96991 +       ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
96992 +       ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
96993 +
96994 +       return ctrl2;
96995 +}
96996 +
96997 +static void sdhci_s3c_check_sclk(struct sdhci_host *host)
96998 +{
96999 +       struct sdhci_s3c *ourhost = to_s3c(host);
97000 +       u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
97001 +
97002 +       if (get_curclk(tmp) != ourhost->cur_clk) {
97003 +               dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
97004 +
97005 +               tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
97006 +               tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
97007 +               writel(tmp, host->ioaddr + 0x80);
97008 +       }
97009 +}
97010 +
97011 +static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
97012 +{
97013 +       struct sdhci_s3c *ourhost = to_s3c(host);
97014 +       struct clk *busclk;
97015 +       unsigned int rate, max;
97016 +       int clk;
97017 +
97018 +       /* note, a reset will reset the clock source */
97019 +
97020 +       sdhci_s3c_check_sclk(host);
97021 +
97022 +       for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
97023 +               busclk = ourhost->clk_bus[clk];
97024 +               if (!busclk)
97025 +                       continue;
97026 +
97027 +               rate = clk_get_rate(busclk);
97028 +               if (rate > max)
97029 +                       max = rate;
97030 +       }
97031 +
97032 +       return max;
97033 +}
97034 +
97035 +static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
97036 +{
97037 +       return sdhci_s3c_get_max_clk(host) / 1000000;
97038 +}
97039 +
97040 +static void sdhci_s3c_set_ios(struct sdhci_host *host,
97041 +                             struct mmc_ios *ios)
97042 +{
97043 +       struct sdhci_s3c *ourhost = to_s3c(host);
97044 +       struct s3c_sdhci_platdata *pdata = ourhost->pdata;
97045 +       int width;
97046 +
97047 +       sdhci_s3c_check_sclk(host);
97048 +
97049 +       if (ios->power_mode != MMC_POWER_OFF) {
97050 +               switch (ios->bus_width) {
97051 +               case MMC_BUS_WIDTH_4:
97052 +                       width = 4;
97053 +                       break;
97054 +               case MMC_BUS_WIDTH_1:
97055 +                       width = 1;
97056 +                       break;
97057 +               default:
97058 +                       BUG();
97059 +               }
97060 +
97061 +               if (pdata->cfg_gpio)
97062 +                       pdata->cfg_gpio(ourhost->pdev, width);
97063 +       }
97064 +
97065 +       if (pdata->cfg_card)
97066 +               pdata->cfg_card(ourhost->pdev, host->ioaddr,
97067 +                               ios, host->mmc->card);
97068 +}
97069 +
97070 +static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
97071 +                                            unsigned int src,
97072 +                                            unsigned int wanted)
97073 +{
97074 +       unsigned long rate;
97075 +       struct clk *clksrc = ourhost->clk_bus[src];
97076 +       int div;
97077 +
97078 +       if (!clksrc)
97079 +               return UINT_MAX;
97080 +
97081 +       rate = clk_get_rate(clksrc);
97082 +
97083 +       for (div = 1; div < 256; div *= 2) {
97084 +               if ((rate / div) <= wanted)
97085 +                       break;
97086 +       }
97087 +
97088 +       dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
97089 +               src, rate, wanted, rate / div);
97090 +
97091 +       return (wanted - (rate / div));
97092 +}
97093 +
97094 +static void sdhci_s3c_change_clock(struct sdhci_host *host, unsigned int clock)
97095 +{
97096 +       struct sdhci_s3c *ourhost = to_s3c(host);
97097 +       unsigned int best = UINT_MAX;
97098 +       unsigned int delta;
97099 +       int best_src = 0;
97100 +       int src;
97101 +       u32 ctrl;
97102 +
97103 +       for (src = 0; src < MAX_BUS_CLK; src++) {
97104 +               delta = sdhci_s3c_consider_clock(ourhost, src, clock);
97105 +               if (delta < best) {
97106 +                       best = delta;
97107 +                       best_src = src;
97108 +               }
97109 +       }
97110 +
97111 +       dev_dbg(&ourhost->pdev->dev,
97112 +               "selected source %d, clock %d, delta %d\n",
97113 +                best_src, clock, best);
97114 +
97115 +       /* turn clock off to card before changing clock source */
97116 +       writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
97117 +
97118 +       /* select the new clock source */
97119 +
97120 +       if (ourhost->cur_clk != best_src) {
97121 +               struct clk *clk = ourhost->clk_bus[best_src];
97122 +
97123 +               ourhost->cur_clk = best_src;
97124 +               host->max_clk = clk_get_rate(clk);
97125 +               host->timeout_clk = host->max_clk / 1000000;
97126 +
97127 +               ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
97128 +               ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
97129 +               ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
97130 +               writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
97131 +       }
97132 +
97133 +       sdhci_change_clock(host, clock);
97134 +}
97135 +
97136 +static struct sdhci_ops sdhci_s3c_ops = {
97137 +       .get_max_clock          = sdhci_s3c_get_max_clk,
97138 +       .get_timeout_clock      = sdhci_s3c_get_timeout_clk,
97139 +       .change_clock           = sdhci_s3c_change_clock,
97140 +       .set_ios                = sdhci_s3c_set_ios,
97141 +};
97142 +
97143 +/*
97144 + * call this when you need sd stack to recognize insertion or removal of card
97145 + * that can't be told by SDHCI regs
97146 + */
97147 +
97148 +void sdhci_s3c_force_presence_change(struct platform_device *pdev)
97149 +{
97150 +       struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
97151 +
97152 +       dev_info(&pdev->dev, "sdhci_s3c_force_presence_change called\n");
97153 +       mmc_detect_change(pdata->sdhci_host->mmc, msecs_to_jiffies(200));
97154 +}
97155 +EXPORT_SYMBOL_GPL(sdhci_s3c_force_presence_change);
97156 +
97157 +
97158 +static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
97159 +{
97160 +       struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
97161 +       struct device *dev = &pdev->dev;
97162 +       struct sdhci_host *host;
97163 +       struct sdhci_s3c *sc;
97164 +       struct resource *res;
97165 +       int ret, irq, ptr, clks;
97166 +
97167 +       if (!pdata) {
97168 +               dev_err(dev, "no device data specified\n");
97169 +               return -ENOENT;
97170 +       }
97171 +
97172 +       irq = platform_get_irq(pdev, 0);
97173 +       if (irq < 0) {
97174 +               dev_err(dev, "no irq specified\n");
97175 +               return irq;
97176 +       }
97177 +
97178 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
97179 +       if (!res) {
97180 +               dev_err(dev, "no memory specified\n");
97181 +               return -ENOENT;
97182 +       }
97183 +
97184 +       host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
97185 +       if (IS_ERR(host)) {
97186 +               dev_err(dev, "sdhci_alloc_host() failed\n");
97187 +               return PTR_ERR(host);
97188 +       }
97189 +
97190 +       pdata->sdhci_host = host;
97191 +
97192 +       sc = sdhci_priv(host);
97193 +
97194 +       sc->host = host;
97195 +       sc->pdev = pdev;
97196 +       sc->pdata = pdata;
97197 +
97198 +       platform_set_drvdata(pdev, host);
97199 +
97200 +       sc->clk_io = clk_get(dev, "hsmmc");
97201 +       if (IS_ERR(sc->clk_io)) {
97202 +               dev_err(dev, "failed to get io clock\n");
97203 +               ret = PTR_ERR(sc->clk_io);
97204 +               goto err_io_clk;
97205 +       }
97206 +
97207 +       /* enable the local io clock and keep it running for the moment. */
97208 +       clk_enable(sc->clk_io);
97209 +
97210 +       for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
97211 +               struct clk *clk;
97212 +               char *name = pdata->clocks[ptr];
97213 +
97214 +               if (name == NULL)
97215 +                       continue;
97216 +
97217 +               clk = clk_get(dev, name);
97218 +               if (IS_ERR(clk)) {
97219 +                       dev_err(dev, "failed to get clock %s\n", name);
97220 +                       continue;
97221 +               }
97222 +
97223 +               clks++;
97224 +               sc->clk_bus[ptr] = clk;
97225 +               clk_enable(clk);
97226 +
97227 +               dev_info(dev, "clock source %d: %s (%ld Hz)\n",
97228 +                        ptr, name, clk_get_rate(clk));
97229 +       }
97230 +
97231 +       if (clks == 0) {
97232 +               dev_err(dev, "failed to find any bus clocks\n");
97233 +               ret = -ENOENT;
97234 +               goto err_no_busclks;
97235 +       }
97236 +
97237 +       sc->ioarea = request_mem_region(res->start, resource_size(res),
97238 +                                       mmc_hostname(host->mmc));
97239 +       if (!sc->ioarea) {
97240 +               dev_err(dev, "failed to reserve register area\n");
97241 +               ret = -ENXIO;
97242 +               goto err_req_regs;
97243 +       }
97244 +
97245 +       host->ioaddr = ioremap_nocache(res->start, resource_size(res));
97246 +       if (!host->ioaddr) {
97247 +               dev_err(dev, "failed to map registers\n");
97248 +               ret = -ENXIO;
97249 +               goto err_req_regs;
97250 +       }
97251 +
97252 +       /* Ensure we have minimal gpio selected CMD/CLK/Detect */
97253 +       if (pdata->cfg_gpio)
97254 +               pdata->cfg_gpio(pdev, 0);
97255 +
97256 +       sdhci_s3c_check_sclk(host);
97257 +
97258 +       host->hw_name = "samsung-hsmmc";
97259 +       host->ops = &sdhci_s3c_ops;
97260 +       host->quirks = 0;
97261 +       host->irq = irq;
97262 +
97263 +       /* Setup quirks for the controller */
97264 +
97265 +       /* Currently with ADMA enabled we are getting some length
97266 +        * interrupts that are not being dealt with, do disable
97267 +        * ADMA until this is sorted out. */
97268 +       host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
97269 +       host->quirks |= SDHCI_QUIRK_32BIT_ADMA_SIZE;
97270 +
97271 +       /* It seems we do not get an DATA transfer complete on non-busy
97272 +        * transfers, not sure if this is a problem with this specific
97273 +        * SDHCI block, or a missing configuration that needs to be set. */
97274 +       host->quirks |= SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY;
97275 +
97276 +       host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
97277 +                        SDHCI_QUIRK_32BIT_DMA_SIZE);
97278 +
97279 +       ret = sdhci_add_host(host);
97280 +       if (ret) {
97281 +               dev_err(dev, "sdhci_add_host() failed\n");
97282 +               goto err_add_host;
97283 +       }
97284 +
97285 +       return 0;
97286 +
97287 + err_add_host:
97288 +       release_resource(sc->ioarea);
97289 +       kfree(sc->ioarea);
97290 +
97291 + err_req_regs:
97292 +       for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
97293 +               clk_disable(sc->clk_bus[ptr]);
97294 +               clk_put(sc->clk_bus[ptr]);
97295 +       }
97296 +
97297 + err_no_busclks:
97298 +       clk_disable(sc->clk_io);
97299 +       clk_put(sc->clk_io);
97300 +
97301 + err_io_clk:
97302 +       sdhci_free_host(host);
97303 +
97304 +       return ret;
97305 +}
97306 +
97307 +static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
97308 +{
97309 +       return 0;
97310 +}
97311 +
97312 +#ifdef CONFIG_PM
97313 +
97314 +static int sdhci_s3c_suspend(struct platform_device *dev, pm_message_t pm)
97315 +{
97316 +       struct sdhci_host *host = platform_get_drvdata(dev);
97317 +
97318 +       sdhci_suspend_host(host, pm);
97319 +       return 0;
97320 +}
97321 +
97322 +static int sdhci_s3c_resume(struct platform_device *dev)
97323 +{
97324 +       struct sdhci_host *host = platform_get_drvdata(dev);
97325 +
97326 +       sdhci_resume_host(host);
97327 +       return 0;
97328 +}
97329 +
97330 +#else
97331 +#define sdhci_s3c_suspend NULL
97332 +#define sdhci_s3c_resume NULL
97333 +#endif
97334 +
97335 +static struct platform_driver sdhci_s3c_driver = {
97336 +       .probe          = sdhci_s3c_probe,
97337 +       .remove         = __devexit_p(sdhci_s3c_remove),
97338 +       .suspend        = sdhci_s3c_suspend,
97339 +       .resume         = sdhci_s3c_resume,
97340 +       .driver         = {
97341 +               .owner  = THIS_MODULE,
97342 +               .name   = "s3c-sdhci",
97343 +       },
97344 +};
97345 +
97346 +static int __init sdhci_s3c_init(void)
97347 +{
97348 +       return platform_driver_register(&sdhci_s3c_driver);
97349 +}
97350 +
97351 +static void __exit sdhci_s3c_exit(void)
97352 +{
97353 +       platform_driver_unregister(&sdhci_s3c_driver);
97354 +}
97355 +
97356 +module_init(sdhci_s3c_init);
97357 +module_exit(sdhci_s3c_exit);
97358 +
97359 +MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
97360 +MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
97361 +MODULE_LICENSE("GPL v2");
97362 +MODULE_ALIAS("platform:s3c-sdhci");
97363 --- a/drivers/mtd/nand/s3c2410.c
97364 +++ b/drivers/mtd/nand/s3c2410.c
97365 @@ -45,8 +45,8 @@
97366
97367  #include <asm/io.h>
97368
97369 -#include <asm/plat-s3c/regs-nand.h>
97370 -#include <asm/plat-s3c/nand.h>
97371 +#include <plat/regs-nand.h>
97372 +#include <plat/nand.h>
97373
97374  #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
97375  static int hardware_ecc = 1;
97376 @@ -231,8 +231,6 @@ static int s3c2410_nand_setrate(struct s
97377                 BUG();
97378         }
97379
97380 -       dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
97381 -
97382         local_irq_save(flags);
97383
97384         cfg = readl(info->regs + S3C2410_NFCONF);
97385 @@ -240,6 +238,8 @@ static int s3c2410_nand_setrate(struct s
97386         cfg |= set;
97387         writel(cfg, info->regs + S3C2410_NFCONF);
97388
97389 +       dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
97390 +
97391         local_irq_restore(flags);
97392
97393         return 0;
97394 @@ -438,7 +438,7 @@ static int s3c2410_nand_correct_data(str
97395         if ((diff0 & ~(1<<fls(diff0))) == 0)
97396                 return 1;
97397
97398 -       return -1;
97399 +       return -EBADMSG;
97400  }
97401
97402  /* ECC functions
97403 @@ -530,7 +530,12 @@ static void s3c2410_nand_read_buf(struct
97404  static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
97405  {
97406         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
97407 +       u8 *ptr = buf + (len & ~3);
97408 +       int i;
97409 +
97410         readsl(info->regs + S3C2440_NFDATA, buf, len / 4);
97411 +       for (i = 0; i != (len & 3); i++)
97412 +               ptr[i] = readb(info->regs + S3C2440_NFDATA);
97413  }
97414
97415  static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
97416 @@ -645,17 +650,31 @@ static int s3c2410_nand_remove(struct pl
97417  }
97418
97419  #ifdef CONFIG_MTD_PARTITIONS
97420 +const char *part_probes[] = { "cmdlinepart", NULL };
97421  static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
97422                                       struct s3c2410_nand_mtd *mtd,
97423                                       struct s3c2410_nand_set *set)
97424  {
97425 +       struct mtd_partition *part_info;
97426 +       int nr_part = 0;
97427 +
97428         if (set == NULL)
97429                 return add_mtd_device(&mtd->mtd);
97430
97431 -       if (set->nr_partitions > 0 && set->partitions != NULL) {
97432 -               return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
97433 +       if (set->nr_partitions == 0) {
97434 +               mtd->mtd.name = set->name;
97435 +               nr_part = parse_mtd_partitions(&mtd->mtd, part_probes,
97436 +                                               &part_info, 0);
97437 +       } else {
97438 +               if (set->nr_partitions > 0 && set->partitions != NULL) {
97439 +                       nr_part = set->nr_partitions;
97440 +                       part_info = set->partitions;
97441 +               }
97442         }
97443
97444 +       if (nr_part > 0 && part_info)
97445 +               return add_mtd_partitions(&mtd->mtd, part_info, nr_part);
97446 +
97447         return add_mtd_device(&mtd->mtd);
97448  }
97449  #else
97450 @@ -684,9 +703,13 @@ static void s3c2410_nand_init_chip(struc
97451         chip->select_chip  = s3c2410_nand_select_chip;
97452         chip->chip_delay   = 50;
97453         chip->priv         = nmtd;
97454 -       chip->options      = 0;
97455         chip->controller   = &info->controller;
97456
97457 +       if (set->flags & S3C2410_NAND_BBT)
97458 +               chip->options      = NAND_USE_FLASH_BBT;
97459 +       else
97460 +               chip->options      = 0;
97461 +
97462         switch (info->cpu_type) {
97463         case TYPE_S3C2410:
97464                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
97465 @@ -726,7 +749,7 @@ static void s3c2410_nand_init_chip(struc
97466         nmtd->mtd.owner    = THIS_MODULE;
97467         nmtd->set          = set;
97468
97469 -       if (hardware_ecc) {
97470 +       if (!info->platform->software_ecc && hardware_ecc) {
97471                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
97472                 chip->ecc.correct   = s3c2410_nand_correct_data;
97473                 chip->ecc.mode      = NAND_ECC_HW;
97474 --- a/drivers/net/wireless/libertas/if_sdio.c
97475 +++ b/drivers/net/wireless/libertas/if_sdio.c
97476 @@ -48,6 +48,7 @@ module_param_named(fw_name, lbs_fw_name,
97477
97478  static const struct sdio_device_id if_sdio_ids[] = {
97479         { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_LIBERTAS) },
97480 +       { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_88W8688) },
97481         { /* end: all zeroes */                                         },
97482  };
97483
97484 @@ -72,7 +73,12 @@ static struct if_sdio_model if_sdio_mode
97485                 .helper = "sd8686_helper.bin",
97486                 .firmware = "sd8686.bin",
97487         },
97488 -};
97489 +       {
97490 +               /* 8688 */
97491 +               .model = 0x10,
97492 +               .helper = "sd8688_helper.bin",
97493 +               .firmware = "sd8688.bin",
97494 +       },};
97495
97496  struct if_sdio_packet {
97497         struct if_sdio_packet   *next;
97498 --- a/drivers/pnp/Kconfig
97499 +++ b/drivers/pnp/Kconfig
97500 @@ -5,7 +5,7 @@
97501  menuconfig PNP
97502         bool "Plug and Play support"
97503         depends on HAS_IOMEM
97504 -       depends on ISA || ACPI
97505 +       depends on ISA || ACPI || SDIO
97506         ---help---
97507           Plug and Play (PnP) is a standard for peripherals which allows those
97508           peripherals to be configured by software, e.g. assign IRQ's or other
97509 --- a/drivers/pnp/resource.c
97510 +++ b/drivers/pnp/resource.c
97511 @@ -436,6 +436,7 @@ int pnp_check_dma(struct pnp_dev *dev, s
97512                 }
97513         }
97514
97515 +#if 0
97516         /* check if the resource is already in use, skip if the
97517          * device is active because it itself may be in use */
97518         if (!dev->active) {
97519 @@ -443,6 +444,7 @@ int pnp_check_dma(struct pnp_dev *dev, s
97520                         return 0;
97521                 free_dma(*dma);
97522         }
97523 +#endif
97524
97525         /* check for conflicts with other pnp devices */
97526         pnp_for_each_dev(tdev) {
97527 --- /dev/null
97528 +++ b/drivers/power/bq27000_battery.c
97529 @@ -0,0 +1,463 @@
97530 +/*
97531 + * Driver for batteries with bq27000 chips inside via HDQ
97532 + *
97533 + * Copyright 2008 Openmoko, Inc
97534 + * Andy Green <andy@openmoko.com>
97535 + *
97536 + * based on ds2760 driver, original copyright notice for that --->
97537 + *
97538 + * Copyright © 2007 Anton Vorontsov
97539 + *            2004-2007 Matt Reimer
97540 + *            2004 Szabolcs Gyurko
97541 + *
97542 + * Use consistent with the GNU GPL is permitted,
97543 + * provided that this copyright notice is
97544 + * preserved in its entirety in all copies and derived works.
97545 + *
97546 + * Author:  Anton Vorontsov <cbou@mail.ru>
97547 + *         February 2007
97548 + *
97549 + *         Matt Reimer <mreimer@vpop.net>
97550 + *         April 2004, 2005, 2007
97551 + *
97552 + *         Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
97553 + *         September 2004
97554 + */
97555 +
97556 +#include <linux/module.h>
97557 +#include <linux/param.h>
97558 +#include <linux/jiffies.h>
97559 +#include <linux/delay.h>
97560 +#include <linux/pm.h>
97561 +#include <linux/workqueue.h>
97562 +#include <linux/platform_device.h>
97563 +#include <linux/power_supply.h>
97564 +#include <linux/bq27000_battery.h>
97565 +
97566 +enum bq27000_regs {
97567 +       /* RAM regs */
97568 +               /* read-write after this */
97569 +       BQ27000_CTRL = 0, /* Device Control Register */
97570 +       BQ27000_MODE, /* Device Mode Register */
97571 +       BQ27000_AR_L, /* At-Rate H L */
97572 +       BQ27000_AR_H,
97573 +               /* read-only after this */
97574 +       BQ27000_ARTTE_L, /* At-Rate Time To Empty H L */
97575 +       BQ27000_ARTTE_H,
97576 +       BQ27000_TEMP_L, /* Reported Temperature H L */
97577 +       BQ27000_TEMP_H,
97578 +       BQ27000_VOLT_L, /* Reported Voltage H L */
97579 +       BQ27000_VOLT_H,
97580 +       BQ27000_FLAGS, /* Status Flags */
97581 +       BQ27000_RSOC, /* Relative State of Charge */
97582 +       BQ27000_NAC_L, /* Nominal Available Capacity H L */
97583 +       BQ27000_NAC_H,
97584 +       BQ27000_CACD_L, /* Discharge Compensated H L */
97585 +       BQ27000_CACD_H,
97586 +       BQ27000_CACT_L, /* Temperature Compensated H L */
97587 +       BQ27000_CACT_H,
97588 +       BQ27000_LMD_L, /* Last measured discharge H L */
97589 +       BQ27000_LMD_H,
97590 +       BQ27000_AI_L, /* Average Current H L */
97591 +       BQ27000_AI_H,
97592 +       BQ27000_TTE_L, /* Time to Empty H L */
97593 +       BQ27000_TTE_H,
97594 +       BQ27000_TTF_L, /* Time to Full H L */
97595 +       BQ27000_TTF_H,
97596 +       BQ27000_SI_L, /* Standby Current H L */
97597 +       BQ27000_SI_H,
97598 +       BQ27000_STTE_L, /* Standby Time To Empty H L */
97599 +       BQ27000_STTE_H,
97600 +       BQ27000_MLI_L, /* Max Load Current H L */
97601 +       BQ27000_MLI_H,
97602 +       BQ27000_MLTTE_L, /* Max Load Time To Empty H L */
97603 +       BQ27000_MLTTE_H,
97604 +       BQ27000_SAE_L, /* Available Energy H L */
97605 +       BQ27000_SAE_H,
97606 +       BQ27000_AP_L, /* Available Power H L */
97607 +       BQ27000_AP_H,
97608 +       BQ27000_TTECP_L, /* Time to Empty at Constant Power H L */
97609 +       BQ27000_TTECP_H,
97610 +       BQ27000_CYCL_L, /* Cycle count since learning cycle H L */
97611 +       BQ27000_CYCL_H,
97612 +       BQ27000_CYCT_L, /* Cycle Count Total H L */
97613 +       BQ27000_CYCT_H,
97614 +       BQ27000_CSOC, /* Compensated State Of Charge */
97615 +       /* EEPROM regs */
97616 +               /* read-write after this */
97617 +       BQ27000_EE_EE_EN = 0x6e, /* EEPROM Program Enable */
97618 +       BQ27000_EE_ILMD = 0x76, /* Initial Last Measured Discharge High Byte */
97619 +       BQ27000_EE_SEDVF, /* Scaled EDVF Threshold */
97620 +       BQ27000_EE_SEDV1, /* Scaled EDV1 Threshold */
97621 +       BQ27000_EE_ISLC, /* Initial Standby Load Current */
97622 +       BQ27000_EE_DMFSD, /* Digital Magnitude Filter and Self Discharge */
97623 +       BQ27000_EE_TAPER, /* Aging Estimate Enable, Charge Termination Taper */
97624 +       BQ27000_EE_PKCFG, /* Pack Configuration Values */
97625 +       BQ27000_EE_IMLC, /* Initial Max Load Current or ID #3 */
97626 +       BQ27000_EE_DCOMP, /* Discharge rate compensation constants or ID #2 */
97627 +       BQ27000_EE_TCOMP, /* Temperature Compensation constants or ID #1 */
97628 +};
97629 +
97630 +enum bq27000_status_flags {
97631 +       BQ27000_STATUS_CHGS = 0x80, /* 1 = being charged */
97632 +       BQ27000_STATUS_NOACT = 0x40, /* 1 = no activity */
97633 +       BQ27000_STATUS_IMIN = 0x20, /* 1 = Lion taper current mode */
97634 +       BQ27000_STATUS_CI = 0x10, /* 1 = capacity likely  innacurate */
97635 +       BQ27000_STATUS_CALIP = 0x08, /* 1 = calibration in progress */
97636 +       BQ27000_STATUS_VDQ = 0x04, /* 1 = capacity should be accurate */
97637 +       BQ27000_STATUS_EDV1 = 0x02, /* 1 = end of discharge.. <6% left */
97638 +       BQ27000_STATUS_EDVF = 0x01, /* 1 = no, it's really empty now */
97639 +};
97640 +
97641 +#define NANOVOLTS_UNIT 3750
97642 +
97643 +struct bq27000_bat_regs {
97644 +       int             ai;
97645 +       int             flags;
97646 +       int             lmd;
97647 +       int             rsoc;
97648 +       int             temp;
97649 +       int             tte;
97650 +       int             ttf;
97651 +       int             volt;
97652 +};
97653 +
97654 +struct bq27000_device_info {
97655 +       struct device *dev;
97656 +       struct power_supply bat;
97657 +       struct delayed_work work;
97658 +       struct bq27000_platform_data *pdata;
97659 +
97660 +       struct bq27000_bat_regs regs;
97661 +};
97662 +
97663 +static unsigned int cache_time = 10000;
97664 +module_param(cache_time, uint, 0644);
97665 +MODULE_PARM_DESC(cache_time, "cache time in milliseconds");
97666 +
97667 +/*
97668 + * reading 16 bit values over HDQ has a special hazard where the
97669 + * hdq device firmware can update the 16-bit register during the time we
97670 + * read the two halves.  TI document SLUS556D recommends the algorithm here
97671 + * to avoid trouble
97672 + */
97673 +
97674 +static int hdq_read16(struct bq27000_device_info *di, int address)
97675 +{
97676 +       int acc;
97677 +       int high;
97678 +       int retries = 3;
97679 +
97680 +       while (retries--) {
97681 +
97682 +               high = (di->pdata->hdq_read)(address + 1); /* high part */
97683 +
97684 +               if (high < 0)
97685 +                       return high;
97686 +               acc = (di->pdata->hdq_read)(address);
97687 +               if (acc < 0)
97688 +                       return acc;
97689 +
97690 +               /* confirm high didn't change between reading it and low */
97691 +               if (high == (di->pdata->hdq_read)(address + 1))
97692 +                       return (high << 8) | acc;
97693 +       }
97694 +
97695 +       return -ETIME;
97696 +}
97697 +
97698 +static void bq27000_battery_external_power_changed(struct power_supply *psy)
97699 +{
97700 +       struct bq27000_device_info *di = container_of(psy, struct bq27000_device_info, bat);
97701 +
97702 +       power_supply_changed(&di->bat);
97703 +       dev_dbg(di->dev, "%s\n", __FUNCTION__);
97704 +}
97705 +
97706 +static int bq27000_battery_get_property(struct power_supply *psy,
97707 +                                      enum power_supply_property psp,
97708 +                                      union power_supply_propval *val)
97709 +{
97710 +       int n;
97711 +       struct bq27000_device_info *di = container_of(psy, struct bq27000_device_info, bat);
97712 +
97713 +       switch (psp) {
97714 +       case POWER_SUPPLY_PROP_STATUS:
97715 +               val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
97716 +
97717 +               if (!di->pdata->get_charger_online_status)
97718 +                       goto use_bat;
97719 +               if ((di->pdata->get_charger_online_status)()) {
97720 +                       /*
97721 +                        * charger is definitively present
97722 +                        * we report our state in terms of what it says it
97723 +                        * is doing
97724 +                        */
97725 +                       if (!di->pdata->get_charger_active_status)
97726 +                               goto use_bat;
97727 +
97728 +                       if ((di->pdata->get_charger_active_status)()) {
97729 +                               val->intval = POWER_SUPPLY_STATUS_CHARGING;
97730 +                               break;
97731 +                       }
97732 +                       val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
97733 +                       break;
97734 +               }
97735 +
97736 +               /*
97737 +                * platform provided definite indication of charger presence,
97738 +                * and it is telling us it isn't there... but we are on so we
97739 +                * must be running from battery --->
97740 +                */
97741 +
97742 +               val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
97743 +               break;
97744 +
97745 +use_bat:
97746 +               /*
97747 +                * either the charger is not connected, or the
97748 +                * platform doesn't give info about charger, use battery state
97749 +                * but... battery state can be out of date by 4 seconds or
97750 +                * so... use the platform callbacks if possible.
97751 +                */
97752 +
97753 +               /* no real activity on the battery */
97754 +               if (di->regs.ai < 2) {
97755 +                       if (!di->regs.ttf)
97756 +                               val->intval = POWER_SUPPLY_STATUS_FULL;
97757 +                       else
97758 +                               val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
97759 +                       break;
97760 +               }
97761 +               /* power is actually going in or out... */
97762 +               if (di->regs.flags < 0)
97763 +                       return di->regs.flags;
97764 +               if (di->regs.flags & BQ27000_STATUS_CHGS)
97765 +                       val->intval = POWER_SUPPLY_STATUS_CHARGING;
97766 +               else
97767 +                       val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
97768 +               break;
97769 +       case POWER_SUPPLY_PROP_HEALTH:
97770 +               val->intval = POWER_SUPPLY_HEALTH_UNKNOWN;
97771 +               /* Do we have accurate readings... */
97772 +               if (di->regs.flags < 0)
97773 +                       return di->regs.flags;
97774 +               if (di->regs.flags & BQ27000_STATUS_VDQ)
97775 +                       val->intval = POWER_SUPPLY_HEALTH_GOOD;
97776 +               break;
97777 +       case POWER_SUPPLY_PROP_VOLTAGE_NOW:
97778 +               if (di->regs.volt < 0)
97779 +                       return di->regs.volt;
97780 +               /* mV -> uV */
97781 +               val->intval = di->regs.volt * 1000;
97782 +               break;
97783 +       case POWER_SUPPLY_PROP_CURRENT_NOW:
97784 +               if (di->regs.flags < 0)
97785 +                       return di->regs.flags;
97786 +               if (di->regs.flags & BQ27000_STATUS_CHGS)
97787 +                       n = -NANOVOLTS_UNIT;
97788 +               else
97789 +                       n = NANOVOLTS_UNIT;
97790 +               if (di->regs.ai < 0)
97791 +                       return di->regs.ai;
97792 +               val->intval = (di->regs.ai * n) / di->pdata->rsense_mohms;
97793 +               break;
97794 +       case POWER_SUPPLY_PROP_CHARGE_FULL:
97795 +               if (di->regs.lmd < 0)
97796 +                       return di->regs.lmd;
97797 +               val->intval = (di->regs.lmd * 3570) / di->pdata->rsense_mohms;
97798 +               break;
97799 +       case POWER_SUPPLY_PROP_TEMP:
97800 +               if (di->regs.temp < 0)
97801 +                       return di->regs.temp;
97802 +               /* K (in 0.25K units) is 273.15 up from C (in 0.1C)*/
97803 +               /* 10926 = 27315 * 4 / 10 */
97804 +               val->intval = (((long)di->regs.temp * 10l) - 10926) / 4;
97805 +               break;
97806 +       case POWER_SUPPLY_PROP_TECHNOLOGY:
97807 +               val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
97808 +               break;
97809 +       case POWER_SUPPLY_PROP_CAPACITY:
97810 +               val->intval = di->regs.rsoc;
97811 +               if (val->intval < 0)
97812 +                       return val->intval;
97813 +               break;
97814 +       case POWER_SUPPLY_PROP_PRESENT:
97815 +               val->intval = !(di->regs.rsoc < 0);
97816 +               break;
97817 +       case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW:
97818 +               if (di->regs.tte < 0)
97819 +                       return di->regs.tte;
97820 +               val->intval = 60 * di->regs.tte;
97821 +               break;
97822 +       case POWER_SUPPLY_PROP_TIME_TO_FULL_NOW:
97823 +               if (di->regs.ttf < 0)
97824 +                       return di->regs.ttf;
97825 +               val->intval = 60 * di->regs.ttf;
97826 +               break;
97827 +       case POWER_SUPPLY_PROP_ONLINE:
97828 +               if (di->pdata->get_charger_online_status)
97829 +                       val->intval = (di->pdata->get_charger_online_status)();
97830 +               else
97831 +                       return -EINVAL;
97832 +               break;
97833 +       default:
97834 +               return -EINVAL;
97835 +       }
97836 +
97837 +       return 0;
97838 +}
97839 +
97840 +static void bq27000_battery_work(struct work_struct *work)
97841 +{
97842 +       struct bq27000_device_info *di =
97843 +               container_of(work, struct bq27000_device_info, work.work);
97844 +
97845 +       if ((di->pdata->hdq_initialized)()) {
97846 +               struct bq27000_bat_regs regs;
97847 +
97848 +               regs.ai    = hdq_read16(di, BQ27000_AI_L);
97849 +               regs.flags = (di->pdata->hdq_read)(BQ27000_FLAGS);
97850 +               regs.lmd   = hdq_read16(di, BQ27000_LMD_L);
97851 +               regs.rsoc  = (di->pdata->hdq_read)(BQ27000_RSOC);
97852 +               regs.temp  = hdq_read16(di, BQ27000_TEMP_L);
97853 +               regs.tte   = hdq_read16(di, BQ27000_TTE_L);
97854 +               regs.ttf   = hdq_read16(di, BQ27000_TTF_L);
97855 +               regs.volt  = hdq_read16(di, BQ27000_VOLT_L);
97856 +
97857 +               if (memcmp (&regs, &di->regs, sizeof(regs)) != 0) {
97858 +                       di->regs = regs;
97859 +                       power_supply_changed(&di->bat);
97860 +               }
97861 +       }
97862 +
97863 +       if (!schedule_delayed_work(&di->work, cache_time))
97864 +               dev_err(di->dev, "battery service reschedule failed\n");
97865 +}
97866 +
97867 +static enum power_supply_property bq27000_battery_props[] = {
97868 +       POWER_SUPPLY_PROP_STATUS,
97869 +       POWER_SUPPLY_PROP_HEALTH,
97870 +       POWER_SUPPLY_PROP_VOLTAGE_NOW,
97871 +       POWER_SUPPLY_PROP_CURRENT_NOW,
97872 +       POWER_SUPPLY_PROP_CHARGE_FULL,
97873 +       POWER_SUPPLY_PROP_TEMP,
97874 +       POWER_SUPPLY_PROP_TECHNOLOGY,
97875 +       POWER_SUPPLY_PROP_PRESENT,
97876 +       POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
97877 +       POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
97878 +       POWER_SUPPLY_PROP_CAPACITY,
97879 +       POWER_SUPPLY_PROP_ONLINE
97880 +};
97881 +
97882 +static int bq27000_battery_probe(struct platform_device *pdev)
97883 +{
97884 +       int retval = 0;
97885 +       struct bq27000_device_info *di;
97886 +       struct bq27000_platform_data *pdata;
97887 +
97888 +       dev_info(&pdev->dev, "BQ27000 Battery Driver (C) 2008 Openmoko, Inc\n");
97889 +
97890 +       di = kzalloc(sizeof(*di), GFP_KERNEL);
97891 +       if (!di) {
97892 +               retval = -ENOMEM;
97893 +               goto di_alloc_failed;
97894 +       }
97895 +
97896 +       platform_set_drvdata(pdev, di);
97897 +
97898 +       pdata = pdev->dev.platform_data;
97899 +       di->dev         = &pdev->dev;
97900 +       /* di->w1_dev        = pdev->dev.parent; */
97901 +       di->bat.name       = pdata->name;
97902 +       di->bat.type       = POWER_SUPPLY_TYPE_BATTERY;
97903 +       di->bat.properties     = bq27000_battery_props;
97904 +       di->bat.num_properties = ARRAY_SIZE(bq27000_battery_props);
97905 +       di->bat.get_property   = bq27000_battery_get_property;
97906 +       di->bat.external_power_changed =
97907 +                                 bq27000_battery_external_power_changed;
97908 +       di->bat.use_for_apm = 1;
97909 +       di->pdata = pdata;
97910 +
97911 +       retval = power_supply_register(&pdev->dev, &di->bat);
97912 +       if (retval) {
97913 +               dev_err(di->dev, "failed to register battery\n");
97914 +               goto batt_failed;
97915 +       }
97916 +
97917 +       INIT_DELAYED_WORK(&di->work, bq27000_battery_work);
97918 +
97919 +       if (!schedule_delayed_work(&di->work, 0))
97920 +               dev_err(di->dev, "failed to schedule bq27000_battery_work\n");
97921 +
97922 +       return 0;
97923 +
97924 +batt_failed:
97925 +       kfree(di);
97926 +di_alloc_failed:
97927 +       return retval;
97928 +}
97929 +
97930 +static int bq27000_battery_remove(struct platform_device *pdev)
97931 +{
97932 +       struct bq27000_device_info *di = platform_get_drvdata(pdev);
97933 +
97934 +       cancel_delayed_work(&di->work);
97935 +
97936 +       power_supply_unregister(&di->bat);
97937 +
97938 +       return 0;
97939 +}
97940 +
97941 +#ifdef CONFIG_PM
97942 +
97943 +static int bq27000_battery_suspend(struct platform_device *pdev,
97944 +                                 pm_message_t state)
97945 +{
97946 +       struct bq27000_device_info *di = platform_get_drvdata(pdev);
97947 +
97948 +       cancel_delayed_work(&di->work);
97949 +       return 0;
97950 +}
97951 +
97952 +static int bq27000_battery_resume(struct platform_device *pdev)
97953 +{
97954 +       struct bq27000_device_info *di = platform_get_drvdata(pdev);
97955 +
97956 +       schedule_delayed_work(&di->work, 0);
97957 +       return 0;
97958 +}
97959 +
97960 +#else
97961 +
97962 +#define bq27000_battery_suspend NULL
97963 +#define bq27000_battery_resume NULL
97964 +
97965 +#endif /* CONFIG_PM */
97966 +
97967 +static struct platform_driver bq27000_battery_driver = {
97968 +       .driver = {
97969 +               .name = "bq27000-battery",
97970 +       },
97971 +       .probe    = bq27000_battery_probe,
97972 +       .remove   = bq27000_battery_remove,
97973 +       .suspend  = bq27000_battery_suspend,
97974 +       .resume   = bq27000_battery_resume,
97975 +};
97976 +
97977 +static int __init bq27000_battery_init(void)
97978 +{
97979 +       return platform_driver_register(&bq27000_battery_driver);
97980 +}
97981 +
97982 +static void __exit bq27000_battery_exit(void)
97983 +{
97984 +       platform_driver_unregister(&bq27000_battery_driver);
97985 +}
97986 +
97987 +module_init(bq27000_battery_init);
97988 +module_exit(bq27000_battery_exit);
97989 +
97990 +MODULE_LICENSE("GPL");
97991 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
97992 +MODULE_DESCRIPTION("bq27000 battery driver");
97993 --- /dev/null
97994 +++ b/drivers/power/gta02_hdq.c
97995 @@ -0,0 +1,292 @@
97996 +/*
97997 + * HDQ driver for the FIC Neo1973 GTA02 GSM phone
97998 + *
97999 + * (C) 2006-2007 by Openmoko, Inc.
98000 + * Author: Andy Green <andy@openmoko.com>
98001 + * All rights reserved.
98002 + *
98003 + * This program is free software; you can redistribute it and/or modify
98004 + * it under the terms of the GNU General Public License version 2 as
98005 + * published by the Free Software Foundation.
98006 + *
98007 + */
98008 +
98009 +#include <linux/kernel.h>
98010 +#include <linux/init.h>
98011 +#include <linux/delay.h>
98012 +#include <linux/platform_device.h>
98013 +#include <mach/hardware.h>
98014 +#include <linux/gta02_hdq.h>
98015 +#include <asm/mach-types.h>
98016 +#include <mach/gta02.h>
98017 +#include <mach/fiq_ipc_gta02.h>
98018 +
98019 +
98020 +
98021 +#define HDQ_READ 0
98022 +#define HDQ_WRITE 0x80
98023 +
98024 +static int fiq_busy(void)
98025 +{
98026 +       int request = (volatile u8)fiq_ipc.hdq_request_ctr;
98027 +       int transact = (volatile u8)fiq_ipc.hdq_transaction_ctr;
98028 +
98029 +       return (request != transact);
98030 +}
98031 +
98032 +int gta02hdq_initialized(void)
98033 +{
98034 +       return fiq_ipc.hdq_probed;
98035 +}
98036 +EXPORT_SYMBOL_GPL(gta02hdq_initialized);
98037 +
98038 +int gta02hdq_read(int address)
98039 +{
98040 +       int count_sleeps = 5;
98041 +       int ret = -ETIME;
98042 +
98043 +       if (!fiq_ipc.hdq_probed)
98044 +               return -EINVAL;
98045 +
98046 +       mutex_lock(&fiq_ipc.hdq_lock);
98047 +
98048 +       fiq_ipc.hdq_error = 0;
98049 +       fiq_ipc.hdq_ads = address | HDQ_READ;
98050 +       fiq_ipc.hdq_request_ctr++;
98051 +       fiq_kick();
98052 +       /*
98053 +        * FIQ takes care of it while we block our calling process
98054 +        * But we're not spinning -- other processes run normally while
98055 +        * we wait for the result
98056 +        */
98057 +       while (count_sleeps--) {
98058 +               msleep(10); /* valid transaction always completes in < 10ms */
98059 +
98060 +               if (fiq_busy())
98061 +                       continue;
98062 +
98063 +               if (fiq_ipc.hdq_error)
98064 +                       goto done; /* didn't see a response in good time */
98065 +
98066 +               ret = fiq_ipc.hdq_rx_data;
98067 +               goto done;
98068 +       }
98069 +
98070 +done:
98071 +       mutex_unlock(&fiq_ipc.hdq_lock);
98072 +       return ret;
98073 +}
98074 +EXPORT_SYMBOL_GPL(gta02hdq_read);
98075 +
98076 +int gta02hdq_write(int address, u8 data)
98077 +{
98078 +       int count_sleeps = 5;
98079 +       int ret = -ETIME;
98080 +
98081 +       if (!fiq_ipc.hdq_probed)
98082 +               return -EINVAL;
98083 +
98084 +       mutex_lock(&fiq_ipc.hdq_lock);
98085 +
98086 +       fiq_ipc.hdq_error = 0;
98087 +       fiq_ipc.hdq_ads = address | HDQ_WRITE;
98088 +       fiq_ipc.hdq_tx_data = data;
98089 +       fiq_ipc.hdq_request_ctr++;
98090 +       fiq_kick();
98091 +       /*
98092 +        * FIQ takes care of it while we block our calling process
98093 +        * But we're not spinning -- other processes run normally while
98094 +        * we wait for the result
98095 +        */
98096 +       while (count_sleeps--) {
98097 +               msleep(10); /* valid transaction always completes in < 10ms */
98098 +
98099 +               if (fiq_busy())
98100 +                       continue; /* something bad with FIQ */
98101 +
98102 +               if (fiq_ipc.hdq_error)
98103 +                       goto done; /* didn't see a response in good time */
98104 +
98105 +               ret = 0;
98106 +               goto done;
98107 +       }
98108 +
98109 +done:
98110 +       mutex_unlock(&fiq_ipc.hdq_lock);
98111 +       return ret;
98112 +}
98113 +EXPORT_SYMBOL_GPL(gta02hdq_write);
98114 +
98115 +/* sysfs */
98116 +
98117 +static ssize_t hdq_sysfs_dump(struct device *dev, struct device_attribute *attr,
98118 +                        char *buf)
98119 +{
98120 +       int n;
98121 +       int v;
98122 +       u8 u8a[128]; /* whole address space for HDQ */
98123 +       char *end = buf;
98124 +
98125 +       if (!fiq_ipc.hdq_probed)
98126 +               return -EINVAL;
98127 +
98128 +       /* the dump does not take care about 16 bit regs, because at this
98129 +        * bus level we don't know about the chip details
98130 +        */
98131 +       for (n = 0; n < sizeof(u8a); n++) {
98132 +               v = gta02hdq_read(n);
98133 +               if (v < 0)
98134 +                       goto bail;
98135 +               u8a[n] = v;
98136 +       }
98137 +
98138 +       for (n = 0; n < sizeof(u8a); n += 16) {
98139 +               hex_dump_to_buffer(u8a + n, sizeof(u8a), 16, 1, end, 4096, 0);
98140 +               end += strlen(end);
98141 +               *end++ = '\n';
98142 +               *end = '\0';
98143 +       }
98144 +       return (end - buf);
98145 +
98146 +bail:
98147 +       return sprintf(buf, "ERROR %d\n", v);
98148 +}
98149 +
98150 +/* you write by <address> <data>, eg, "34 128" */
98151 +
98152 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
98153 +
98154 +static ssize_t hdq_sysfs_write(struct device *dev,
98155 +                              struct device_attribute *attr,
98156 +                              const char *buf, size_t count)
98157 +{
98158 +       const char *end = buf + count;
98159 +       int address = atoi(buf);
98160 +
98161 +       if (!fiq_ipc.hdq_probed)
98162 +               return -EINVAL;
98163 +
98164 +       while ((buf != end) && (*buf != ' '))
98165 +               buf++;
98166 +       if (buf >= end)
98167 +               return 0;
98168 +       while ((buf < end) && (*buf == ' '))
98169 +               buf++;
98170 +       if (buf >= end)
98171 +               return 0;
98172 +
98173 +       gta02hdq_write(address, atoi(buf));
98174 +
98175 +       return count;
98176 +}
98177 +
98178 +static DEVICE_ATTR(dump, 0400, hdq_sysfs_dump, NULL);
98179 +static DEVICE_ATTR(write, 0600, NULL, hdq_sysfs_write);
98180 +
98181 +static struct attribute *gta02hdq_sysfs_entries[] = {
98182 +       &dev_attr_dump.attr,
98183 +       &dev_attr_write.attr,
98184 +       NULL
98185 +};
98186 +
98187 +static struct attribute_group gta02hdq_attr_group = {
98188 +       .name   = "hdq",
98189 +       .attrs  = gta02hdq_sysfs_entries,
98190 +};
98191 +
98192 +
98193 +#ifdef CONFIG_PM
98194 +static int gta02hdq_suspend(struct platform_device *pdev, pm_message_t state)
98195 +{
98196 +       /* after 18s of this, the battery monitor will also go to sleep */
98197 +       s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0);
98198 +       s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
98199 +       return 0;
98200 +}
98201 +
98202 +static int gta02hdq_resume(struct platform_device *pdev)
98203 +{
98204 +       s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
98205 +       s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
98206 +       return 0;
98207 +}
98208 +#endif
98209 +
98210 +static int __init gta02hdq_probe(struct platform_device *pdev)
98211 +{
98212 +       struct resource *r = platform_get_resource(pdev, 0, 0);
98213 +       int ret;
98214 +       struct gta02_hdq_platform_data *pdata = pdev->dev.platform_data;
98215 +
98216 +       if (!machine_is_neo1973_gta02())
98217 +               return -EIO;
98218 +
98219 +       if (!r)
98220 +               return -EINVAL;
98221 +
98222 +       if (!fiq_ready) {
98223 +               printk(KERN_ERR "hdq probe fails on fiq not ready\n");
98224 +               return -EINVAL;
98225 +       }
98226 +
98227 +       platform_set_drvdata(pdev, NULL);
98228 +
98229 +       mutex_init(&fiq_ipc.hdq_lock);
98230 +
98231 +       /* set our HDQ comms pin from the platform data */
98232 +       fiq_ipc.hdq_gpio_pin = r->start;
98233 +
98234 +       s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
98235 +       s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
98236 +
98237 +       ret = sysfs_create_group(&pdev->dev.kobj, &gta02hdq_attr_group);
98238 +       if (ret)
98239 +               return ret;
98240 +
98241 +       fiq_ipc.hdq_probed = 1; /* we are ready to do stuff now */
98242 +
98243 +       /*
98244 +        * if wanted, users can defer registration of devices
98245 +        * that depend on HDQ until after we register, and can use our
98246 +        * device as parent so suspend-resume ordering is correct
98247 +        */
98248 +       if (pdata->attach_child_devices)
98249 +               (pdata->attach_child_devices)(&pdev->dev);
98250 +
98251 +       return 0;
98252 +}
98253 +
98254 +static int gta02hdq_remove(struct platform_device *pdev)
98255 +{
98256 +       sysfs_remove_group(&pdev->dev.kobj, &gta02hdq_attr_group);
98257 +       return 0;
98258 +}
98259 +
98260 +static struct platform_driver gta02hdq_driver = {
98261 +       .probe          = gta02hdq_probe,
98262 +       .remove         = gta02hdq_remove,
98263 +#ifdef CONFIG_PM
98264 +       .suspend        = gta02hdq_suspend,
98265 +       .resume         = gta02hdq_resume,
98266 +#endif
98267 +       .driver         = {
98268 +               .name           = "gta02-hdq",
98269 +       },
98270 +};
98271 +
98272 +static int __init gta02hdq_init(void)
98273 +{
98274 +       return platform_driver_register(&gta02hdq_driver);
98275 +}
98276 +
98277 +static void __exit gta02hdq_exit(void)
98278 +{
98279 +       platform_driver_unregister(&gta02hdq_driver);
98280 +}
98281 +
98282 +module_init(gta02hdq_init);
98283 +module_exit(gta02hdq_exit);
98284 +
98285 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
98286 +MODULE_DESCRIPTION("GTA02 HDQ driver");
98287 +MODULE_LICENSE("GPL");
98288 --- a/drivers/power/Kconfig
98289 +++ b/drivers/power/Kconfig
98290 @@ -68,4 +68,24 @@ config BATTERY_BQ27x00
98291         help
98292           Say Y here to enable support for batteries with BQ27200(I2C) chip.
98293
98294 +config BATTERY_BQ27000_HDQ
98295 +       tristate "BQ27000 HDQ battery monitor driver"
98296 +       help
98297 +         Say Y to enable support for the battery on the Neo Freerunner
98298 +
98299 +config GTA02_HDQ
98300 +       tristate "Neo Freerunner HDQ"
98301 +       depends on MACH_NEO1973_GTA02 && FIQ && S3C2440_C_FIQ
98302 +       help
98303 +         Say Y to enable support for communicating with an HDQ battery
98304 +         on the Neo Freerunner.  You probably want to select
98305 +         at least BATTERY_BQ27000_HDQ as well
98306 +
98307 +config CHARGER_PCF50633
98308 +       tristate "Support for NXP PCF50633 MBC"
98309 +       depends on MFD_PCF50633
98310 +       help
98311 +        Say Y to include support for NXP PCF50633 Main Battery Charger.
98312 +
98313  endif # POWER_SUPPLY
98314 +
98315 --- a/drivers/power/Makefile
98316 +++ b/drivers/power/Makefile
98317 @@ -23,3 +23,9 @@ obj-$(CONFIG_BATTERY_OLPC)    += olpc_batte
98318  obj-$(CONFIG_BATTERY_TOSA)     += tosa_battery.o
98319  obj-$(CONFIG_BATTERY_WM97XX)   += wm97xx_battery.o
98320  obj-$(CONFIG_BATTERY_BQ27x00)  += bq27x00_battery.o
98321 +obj-$(CONFIG_BATTERY_PALMTX)   += palmtx_battery.o
98322 +obj-$(CONFIG_BATTERY_BQ27000_HDQ)      += bq27000_battery.o
98323 +
98324 +obj-$(CONFIG_GTA02_HDQ)                += gta02_hdq.o
98325 +
98326 +obj-$(CONFIG_CHARGER_PCF50633) += pcf50633-charger.o
98327 --- /dev/null
98328 +++ b/drivers/power/pcf50633-charger.c
98329 @@ -0,0 +1,415 @@
98330 +/* Philips PCF50633 Main Battery Charger Driver
98331 + *
98332 + * (C) 2006-2008 by Openmoko, Inc.
98333 + * Author: Balaji Rao <balajirrao@openmoko.org>
98334 + * All rights reserved.
98335 + *
98336 + * Broken down from monstrous PCF50633 driver mainly by
98337 + * Harald Welte, Andy Green and Werner Almesberger
98338 + *
98339 + * This program is free software; you can redistribute it and/or
98340 + * modify it under the terms of the GNU General Public License as
98341 + * published by the Free Software Foundation; either version 2 of
98342 + * the License, or (at your option) any later version.
98343 + *
98344 + * This program is distributed in the hope that it will be useful,
98345 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
98346 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
98347 + * GNU General Public License for more details.
98348 + *
98349 + * You should have received a copy of the GNU General Public License
98350 + * along with this program; if not, write to the Free Software
98351 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
98352 + * MA 02111-1307 USA
98353 + */
98354 +
98355 +#include <linux/mfd/pcf50633/core.h>
98356 +#include <linux/mfd/pcf50633/mbc.h>
98357 +
98358 +void pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma)
98359 +{
98360 +       int ret;
98361 +       u8 bits;
98362 +       int charging_start = 1;
98363 +       u8 mbcs2, chgmod;
98364 +
98365 +       if (ma >= 1000)
98366 +               bits = PCF50633_MBCC7_USB_1000mA;
98367 +       else if (ma >= 500)
98368 +               bits = PCF50633_MBCC7_USB_500mA;
98369 +       else if (ma >= 100)
98370 +               bits = PCF50633_MBCC7_USB_100mA;
98371 +       else {
98372 +               bits = PCF50633_MBCC7_USB_SUSPEND;
98373 +               charging_start = 0;
98374 +       }
98375 +
98376 +       ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7,
98377 +                                       PCF50633_MBCC7_USB_MASK, bits);
98378 +       if (ret)
98379 +               dev_err(pcf->dev, "error setting usb curlim to %d mA\n", ma);
98380 +       else
98381 +               dev_info(pcf->dev, "usb curlim to %d mA\n", ma);
98382 +
98383 +       mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
98384 +       chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
98385 +
98386 +       /* If chgmod == BATFULL, setting chgena has no effect.
98387 +        * We need to set resume instead.
98388 +        */
98389 +       if (chgmod != PCF50633_MBCS2_MBC_BAT_FULL)
98390 +               pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
98391 +                               PCF50633_MBCC1_CHGENA, PCF50633_MBCC1_CHGENA);
98392 +       else
98393 +               pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
98394 +                               PCF50633_MBCC1_RESUME, PCF50633_MBCC1_RESUME);
98395 +
98396 +       pcf->mbc.usb_active = charging_start;
98397 +       power_supply_changed(&pcf->mbc.usb);
98398 +}
98399 +EXPORT_SYMBOL_GPL(pcf50633_mbc_usb_curlim_set);
98400 +
98401 +static const char *chgmode_names[] = {
98402 +       [PCF50633_MBCS2_MBC_PLAY]               = "play-only",
98403 +       [PCF50633_MBCS2_MBC_USB_PRE]            = "pre",
98404 +       [PCF50633_MBCS2_MBC_ADP_PRE]            = "pre",
98405 +       [PCF50633_MBCS2_MBC_USB_PRE_WAIT]       = "pre-wait",
98406 +       [PCF50633_MBCS2_MBC_ADP_PRE_WAIT]       = "pre-wait",
98407 +       [PCF50633_MBCS2_MBC_USB_FAST]           = "fast",
98408 +       [PCF50633_MBCS2_MBC_ADP_FAST]           = "fast",
98409 +       [PCF50633_MBCS2_MBC_USB_FAST_WAIT]      = "fast-wait",
98410 +       [PCF50633_MBCS2_MBC_ADP_FAST_WAIT]      = "fast-wait",
98411 +       [PCF50633_MBCS2_MBC_BAT_FULL]   = "bat-full",
98412 +};
98413 +
98414 +static ssize_t show_chgmode(struct device *dev, struct device_attribute *attr,
98415 +                           char *buf)
98416 +{
98417 +       struct pcf50633 *pcf = dev_get_drvdata(dev);
98418 +
98419 +       u8 mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
98420 +       u8 chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
98421 +
98422 +       return sprintf(buf, "%s %d\n", chgmode_names[chgmod], chgmod);
98423 +}
98424 +static DEVICE_ATTR(chgmode, S_IRUGO | S_IWUSR, show_chgmode, NULL);
98425 +
98426 +static ssize_t show_usblim(struct device *dev, struct device_attribute *attr,
98427 +                          char *buf)
98428 +{
98429 +       struct pcf50633 *pcf = dev_get_drvdata(dev);
98430 +       u8 usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
98431 +                                               PCF50633_MBCC7_USB_MASK;
98432 +       unsigned int ma;
98433 +
98434 +       if (usblim == PCF50633_MBCC7_USB_1000mA)
98435 +               ma = 1000;
98436 +       else if (usblim == PCF50633_MBCC7_USB_500mA)
98437 +               ma = 500;
98438 +       else if (usblim == PCF50633_MBCC7_USB_100mA)
98439 +               ma = 100;
98440 +       else
98441 +               ma = 0;
98442 +
98443 +       return sprintf(buf, "%u\n", ma);
98444 +}
98445 +static DEVICE_ATTR(usb_curlim, S_IRUGO | S_IWUSR, show_usblim, NULL);
98446 +
98447 +static ssize_t force_usb_limit_dangerous(struct device *dev,
98448 +                  struct device_attribute *attr, const char *buf, size_t count)
98449 +{
98450 +       struct pcf50633 *pcf = dev_get_drvdata(dev);
98451 +       unsigned long ma;
98452 +
98453 +       strict_strtoul(buf, 10, &ma);
98454 +
98455 +       pcf50633_mbc_usb_curlim_set(pcf, ma);
98456 +
98457 +       return count;
98458 +}
98459 +
98460 +static DEVICE_ATTR(force_usb_limit_dangerous, 0600,
98461 +                                              NULL, force_usb_limit_dangerous);
98462 +
98463 +static struct attribute *mbc_sysfs_entries[] = {
98464 +       &dev_attr_chgmode.attr,
98465 +       &dev_attr_usb_curlim.attr,
98466 +       &dev_attr_force_usb_limit_dangerous.attr,
98467 +       NULL,
98468 +};
98469 +
98470 +static struct attribute_group mbc_attr_group = {
98471 +       .name   = NULL,                 /* put in device directory */
98472 +       .attrs  = mbc_sysfs_entries,
98473 +};
98474 +
98475 +/* MBC state machine switches into charging mode when the battery voltage
98476 + * falls below 96% of a battery float voltage. But the voltage drop in Li-ion
98477 + * batteries is marginal(1~2 %) till about 80% of its capacity - which means,
98478 + * after a BATFULL, charging won't be restarted until 80%.
98479 + *
98480 + * This work_struct function restarts charging every
98481 + * CHARGING_RESTART_TIMEOUT seconds and makes sure we don't discharge too much
98482 + */
98483 +
98484 +#define CHARGING_RESTART_TIMEOUT       (900 * HZ)  /* 15 minutes */
98485 +
98486 +static void pcf50633_mbc_charging_restart(struct work_struct *work)
98487 +{
98488 +       struct pcf50633_mbc *mbc;
98489 +       struct pcf50633 *pcf;
98490 +       u8 mbcs2, chgmod;
98491 +
98492 +       mbc = container_of(work, struct pcf50633_mbc,
98493 +                               charging_restart_work.work);
98494 +       pcf = container_of(mbc, struct pcf50633, mbc);
98495 +
98496 +       mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
98497 +       chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
98498 +
98499 +       if (chgmod != PCF50633_MBCS2_MBC_BAT_FULL)
98500 +               return;
98501 +
98502 +       /* Restart charging */
98503 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1, PCF50633_MBCC1_RESUME,
98504 +                                               PCF50633_MBCC1_RESUME);
98505 +       mbc->usb_active = 1;
98506 +       power_supply_changed(&mbc->usb);
98507 +
98508 +       dev_info(pcf->dev, "Charging restarted..\n");
98509 +}
98510 +
98511 +static void pcf50633_mbc_irq_handler(struct pcf50633 *pcf, int irq, void *data)
98512 +{
98513 +       struct pcf50633_mbc *mbc;
98514 +
98515 +       mbc = &pcf->mbc;
98516 +
98517 +       /* USB */
98518 +       if (irq == PCF50633_IRQ_USBINS)
98519 +               mbc->usb_online = 1;
98520 +       else if (irq == PCF50633_IRQ_USBREM) {
98521 +               mbc->usb_online = 0;
98522 +               mbc->usb_active = 0;
98523 +               pcf50633_mbc_usb_curlim_set(pcf, 0);
98524 +               cancel_delayed_work_sync(&mbc->charging_restart_work);
98525 +       }
98526 +
98527 +       /* Adapter */
98528 +       if (irq == PCF50633_IRQ_ADPINS) {
98529 +               pcf->mbc.adapter_online = 1;
98530 +               pcf->mbc.adapter_active = 1;
98531 +       } else if (irq == PCF50633_IRQ_ADPREM) {
98532 +               mbc->adapter_online = 0;
98533 +               mbc->adapter_active = 0;
98534 +       }
98535 +
98536 +       if (irq == PCF50633_IRQ_BATFULL) {
98537 +               mbc->usb_active = 0;
98538 +               mbc->adapter_active = 0;
98539 +               schedule_delayed_work(&mbc->charging_restart_work,
98540 +                                               CHARGING_RESTART_TIMEOUT);
98541 +       } else if (irq == PCF50633_IRQ_USBLIMON)
98542 +               mbc->usb_active = 0;
98543 +       else if (irq == PCF50633_IRQ_USBLIMOFF)
98544 +               mbc->usb_active = 1;
98545 +
98546 +       power_supply_changed(&mbc->ac);
98547 +       power_supply_changed(&mbc->usb);
98548 +       power_supply_changed(&mbc->adapter);
98549 +
98550 +       if (pcf->pdata->mbc_event_callback)
98551 +               pcf->pdata->mbc_event_callback(pcf, irq);
98552 +}
98553 +
98554 +static int adapter_get_property(struct power_supply *psy,
98555 +                       enum power_supply_property psp,
98556 +                       union power_supply_propval *val)
98557 +{
98558 +       int ret = 0;
98559 +       struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, usb);
98560 +
98561 +       switch (psp) {
98562 +       case POWER_SUPPLY_PROP_ONLINE:
98563 +               val->intval =  mbc->adapter_online;
98564 +               break;
98565 +       default:
98566 +               ret = -EINVAL;
98567 +               break;
98568 +       }
98569 +       return ret;
98570 +}
98571 +
98572 +static int usb_get_property(struct power_supply *psy,
98573 +                       enum power_supply_property psp,
98574 +                       union power_supply_propval *val)
98575 +{
98576 +       int ret = 0;
98577 +       struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, usb);
98578 +       struct pcf50633 *pcf = container_of(mbc, struct pcf50633, mbc);
98579 +
98580 +       u8 usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
98581 +                                               PCF50633_MBCC7_USB_MASK;
98582 +
98583 +       switch (psp) {
98584 +       case POWER_SUPPLY_PROP_ONLINE:
98585 +               val->intval = mbc->usb_online && (usblim == PCF50633_MBCC7_USB_500mA);
98586 +               break;
98587 +       default:
98588 +               ret = -EINVAL;
98589 +               break;
98590 +       }
98591 +       return ret;
98592 +}
98593 +
98594 +static int ac_get_property(struct power_supply *psy,
98595 +                       enum power_supply_property psp,
98596 +                       union power_supply_propval *val)
98597 +{
98598 +       int ret = 0;
98599 +       struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, ac);
98600 +       struct pcf50633 *pcf = container_of(mbc, struct pcf50633, mbc);
98601 +
98602 +       u8 usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
98603 +                                               PCF50633_MBCC7_USB_MASK;
98604 +
98605 +       switch (psp) {
98606 +       case POWER_SUPPLY_PROP_ONLINE:
98607 +               val->intval = mbc->usb_online && (usblim == PCF50633_MBCC7_USB_1000mA);
98608 +               break;
98609 +       default:
98610 +               ret = -EINVAL;
98611 +               break;
98612 +       }
98613 +       return ret;
98614 +}
98615 +
98616 +static enum power_supply_property power_props[] = {
98617 +       POWER_SUPPLY_PROP_ONLINE,
98618 +};
98619 +
98620 +int __init pcf50633_mbc_probe(struct platform_device *pdev)
98621 +{
98622 +       struct pcf50633 *pcf;
98623 +       struct pcf50633_mbc *mbc;
98624 +       int ret;
98625 +       u8 mbcs1;
98626 +
98627 +       pcf = platform_get_drvdata(pdev);
98628 +       mbc = &pcf->mbc;
98629 +
98630 +       /* Set up IRQ handlers */
98631 +       pcf->irq_handler[PCF50633_IRQ_ADPINS].handler =
98632 +                                       pcf50633_mbc_irq_handler;
98633 +       pcf->irq_handler[PCF50633_IRQ_ADPREM].handler =
98634 +                                       pcf50633_mbc_irq_handler;
98635 +       pcf->irq_handler[PCF50633_IRQ_USBINS].handler =
98636 +                                       pcf50633_mbc_irq_handler;
98637 +       pcf->irq_handler[PCF50633_IRQ_USBREM].handler =
98638 +                                       pcf50633_mbc_irq_handler;
98639 +       pcf->irq_handler[PCF50633_IRQ_BATFULL].handler =
98640 +                                       pcf50633_mbc_irq_handler;
98641 +       pcf->irq_handler[PCF50633_IRQ_CHGHALT].handler =
98642 +                                       pcf50633_mbc_irq_handler;
98643 +       pcf->irq_handler[PCF50633_IRQ_THLIMON].handler =
98644 +                                       pcf50633_mbc_irq_handler;
98645 +       pcf->irq_handler[PCF50633_IRQ_THLIMOFF].handler =
98646 +                                       pcf50633_mbc_irq_handler;
98647 +       pcf->irq_handler[PCF50633_IRQ_USBLIMON].handler =
98648 +                                       pcf50633_mbc_irq_handler;
98649 +       pcf->irq_handler[PCF50633_IRQ_USBLIMOFF].handler =
98650 +                                       pcf50633_mbc_irq_handler;
98651 +       pcf->irq_handler[PCF50633_IRQ_LOWSYS].handler =
98652 +                                       pcf50633_mbc_irq_handler;
98653 +       pcf->irq_handler[PCF50633_IRQ_LOWBAT].handler =
98654 +                                       pcf50633_mbc_irq_handler;
98655 +
98656 +       /* Create power supplies */
98657 +
98658 +       mbc->adapter.name               = "adapter";
98659 +       mbc->adapter.type               = POWER_SUPPLY_TYPE_MAINS;
98660 +       mbc->adapter.properties         = power_props;
98661 +       mbc->adapter.num_properties     = ARRAY_SIZE(power_props);
98662 +       mbc->adapter.get_property       = &adapter_get_property;
98663 +       mbc->adapter.supplied_to        = pcf->pdata->batteries;
98664 +       mbc->adapter.num_supplicants    = pcf->pdata->num_batteries;
98665 +
98666 +       mbc->usb.name                   = "usb";
98667 +       mbc->usb.type                   = POWER_SUPPLY_TYPE_USB;
98668 +       mbc->usb.properties             = power_props;
98669 +       mbc->usb.num_properties         = ARRAY_SIZE(power_props);
98670 +       mbc->usb.get_property           = usb_get_property;
98671 +       mbc->usb.supplied_to            = pcf->pdata->batteries;
98672 +       mbc->usb.num_supplicants        = pcf->pdata->num_batteries;
98673 +
98674 +       mbc->ac.name                    = "ac";
98675 +       mbc->ac.type                    = POWER_SUPPLY_TYPE_MAINS;
98676 +       mbc->ac.properties              = power_props;
98677 +       mbc->ac.num_properties          = ARRAY_SIZE(power_props);
98678 +       mbc->ac.get_property            = ac_get_property;
98679 +       mbc->ac.supplied_to             = pcf->pdata->batteries;
98680 +       mbc->ac.num_supplicants         = pcf->pdata->num_batteries;
98681 +
98682 +       INIT_DELAYED_WORK(&mbc->charging_restart_work,
98683 +                               pcf50633_mbc_charging_restart);
98684 +
98685 +       ret = power_supply_register(&pdev->dev, &mbc->adapter);
98686 +       if (ret)
98687 +               dev_err(pcf->dev, "failed to register adapter\n");
98688 +
98689 +       ret = power_supply_register(&pdev->dev, &mbc->usb);
98690 +       if (ret)
98691 +               dev_err(pcf->dev, "failed to register usb\n");
98692 +
98693 +       ret = power_supply_register(&pdev->dev, &mbc->ac);
98694 +       if (ret)
98695 +               dev_err(pcf->dev, "failed to register ac\n");
98696 +
98697 +       mbcs1 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS1);
98698 +       if (mbcs1 & 0x01)
98699 +               pcf50633_mbc_irq_handler(pcf, PCF50633_IRQ_USBINS, NULL);
98700 +       if (mbcs1 & 0x04)
98701 +               pcf50633_mbc_irq_handler(pcf, PCF50633_IRQ_ADPINS, NULL);
98702 +
98703 +       /* Disable automatic charging restart. Manually setting RESUME
98704 +        * won't have effect otherwise
98705 +        */
98706 +       pcf50633_reg_clear_bits(pcf, PCF50633_REG_MBCC1,
98707 +                                       PCF50633_MBCC1_AUTORES);
98708 +
98709 +       return sysfs_create_group(&pdev->dev.kobj, &mbc_attr_group);
98710 +}
98711 +
98712 +static int __devexit pcf50633_mbc_remove(struct platform_device *pdev)
98713 +{
98714 +       struct pcf50633 *pcf;
98715 +
98716 +       pcf = platform_get_drvdata(pdev);
98717 +
98718 +       return 0;
98719 +}
98720 +
98721 +struct platform_driver pcf50633_mbc_driver = {
98722 +       .driver = {
98723 +               .name = "pcf50633-mbc",
98724 +       },
98725 +       .probe = pcf50633_mbc_probe,
98726 +       .remove = __devexit_p(pcf50633_mbc_remove),
98727 +};
98728 +
98729 +static int __init pcf50633_mbc_init(void)
98730 +{
98731 +               return platform_driver_register(&pcf50633_mbc_driver);
98732 +}
98733 +module_init(pcf50633_mbc_init);
98734 +
98735 +static void __exit pcf50633_mbc_exit(void)
98736 +{
98737 +               platform_driver_unregister(&pcf50633_mbc_driver);
98738 +}
98739 +module_exit(pcf50633_mbc_exit);
98740 +
98741 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
98742 +MODULE_DESCRIPTION("PCF50633 mbc driver");
98743 +MODULE_LICENSE("GPL");
98744 +MODULE_ALIAS("platform:pcf50633-mbc");
98745 --- a/drivers/regulator/core.c
98746 +++ b/drivers/regulator/core.c
98747 @@ -1113,6 +1113,7 @@ int regulator_disable(struct regulator *
98748         if (!regulator->enabled) {
98749                 printk(KERN_ERR "%s: not in use by this consumer\n",
98750                         __func__);
98751 +               WARN_ON(1);
98752                 return 0;
98753         }
98754
98755 --- a/drivers/regulator/Kconfig
98756 +++ b/drivers/regulator/Kconfig
98757 @@ -73,4 +73,10 @@ config REGULATOR_DA903X
98758           Say y here to support the BUCKs and LDOs regulators found on
98759           Dialog Semiconductor DA9030/DA9034 PMIC.
98760
98761 +config REGULATOR_PCF50633
98762 +       bool "PCF50633 regulator driver"
98763 +        depends on MFD_PCF50633
98764 +       help
98765 +        Say Y here to support the voltage regulators and convertors
98766 +        on PCF50633
98767  endif
98768 --- a/drivers/regulator/Makefile
98769 +++ b/drivers/regulator/Makefile
98770 @@ -11,5 +11,6 @@ obj-$(CONFIG_REGULATOR_BQ24022) += bq240
98771  obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
98772  obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
98773  obj-$(CONFIG_REGULATOR_DA903X) += da903x.o
98774 +obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
98775
98776  ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
98777 --- /dev/null
98778 +++ b/drivers/regulator/pcf50633-regulator.c
98779 @@ -0,0 +1,330 @@
98780 +/* Philips PCF50633 PMIC Driver
98781 + *
98782 + * (C) 2006-2008 by Openmoko, Inc.
98783 + * Author: Balaji Rao <balajirrao@openmoko.org>
98784 + * All rights reserved.
98785 + *
98786 + * Broken down from monstrous PCF50633 driver mainly by
98787 + * Harald Welte and Andy Green
98788 + *
98789 + * This program is free software; you can redistribute it and/or
98790 + * modify it under the terms of the GNU General Public License as
98791 + * published by the Free Software Foundation; either version 2 of
98792 + * the License, or (at your option) any later version.
98793 + *
98794 + * This program is distributed in the hope that it will be useful,
98795 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
98796 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
98797 + * GNU General Public License for more details.
98798 + *
98799 + * You should have received a copy of the GNU General Public License
98800 + * along with this program; if not, write to the Free Software
98801 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
98802 + * MA 02111-1307 USA
98803 + */
98804 +
98805 +#include <linux/regulator/driver.h>
98806 +#include <linux/platform_device.h>
98807 +#include <linux/err.h>
98808 +
98809 +#include <linux/mfd/pcf50633/core.h>
98810 +#include <linux/mfd/pcf50633/pmic.h>
98811 +
98812 +#define PCF50633_REGULATOR(_name, _id)                 \
98813 +       {                                       \
98814 +               .name = _name,                  \
98815 +               .id = _id,                      \
98816 +               .ops = &pcf50633_regulator_ops, \
98817 +               .type = REGULATOR_VOLTAGE,      \
98818 +               .owner = THIS_MODULE,           \
98819 +       }
98820 +static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = {
98821 +       [PCF50633_REGULATOR_AUTO]       = PCF50633_REG_AUTOOUT,
98822 +       [PCF50633_REGULATOR_DOWN1]      = PCF50633_REG_DOWN1OUT,
98823 +       [PCF50633_REGULATOR_DOWN2]      = PCF50633_REG_DOWN2OUT,
98824 +       [PCF50633_REGULATOR_MEMLDO]     = PCF50633_REG_MEMLDOOUT,
98825 +       [PCF50633_REGULATOR_LDO1]       = PCF50633_REG_LDO1OUT,
98826 +       [PCF50633_REGULATOR_LDO2]       = PCF50633_REG_LDO2OUT,
98827 +       [PCF50633_REGULATOR_LDO3]       = PCF50633_REG_LDO3OUT,
98828 +       [PCF50633_REGULATOR_LDO4]       = PCF50633_REG_LDO4OUT,
98829 +       [PCF50633_REGULATOR_LDO5]       = PCF50633_REG_LDO5OUT,
98830 +       [PCF50633_REGULATOR_LDO6]       = PCF50633_REG_LDO6OUT,
98831 +       [PCF50633_REGULATOR_HCLDO]      = PCF50633_REG_HCLDOOUT,
98832 +};
98833 +
98834 +/* Bits from voltage value */
98835 +static u_int8_t auto_voltage_bits(unsigned int millivolts)
98836 +{
98837 +       if (millivolts < 1800)
98838 +               return 0;
98839 +       if (millivolts > 3800)
98840 +               return 0xff;
98841 +
98842 +       millivolts -= 625;
98843 +       return millivolts/25;
98844 +}
98845 +
98846 +static u_int8_t down_voltage_bits(unsigned int millivolts)
98847 +{
98848 +       if (millivolts < 625)
98849 +               return 0;
98850 +       else if (millivolts > 3000)
98851 +               return 0xff;
98852 +
98853 +       millivolts -= 625;
98854 +       return millivolts/25;
98855 +}
98856 +
98857 +static u_int8_t ldo_voltage_bits(unsigned int millivolts)
98858 +{
98859 +       if (millivolts < 900)
98860 +               return 0;
98861 +       else if (millivolts > 3600)
98862 +               return 0x1f;
98863 +
98864 +       millivolts -= 900;
98865 +       return millivolts/100;
98866 +}
98867 +
98868 +/* Obtain voltage value from bits */
98869 +
98870 +static unsigned int auto_voltage_value(uint8_t bits)
98871 +{
98872 +       if (bits < 0x2f)
98873 +               return 0;
98874 +       return 625 + (bits * 25);
98875 +}
98876 +
98877 +
98878 +static unsigned int down_voltage_value(uint8_t bits)
98879 +{
98880 +       return 625 + (bits*25);
98881 +}
98882 +
98883 +
98884 +static unsigned int ldo_voltage_value(uint8_t bits)
98885 +{
98886 +       bits &= 0x1f;
98887 +       return 900 + (bits * 100);
98888 +}
98889 +
98890 +static int pcf50633_regulator_set_voltage(struct regulator_dev *rdev,
98891 +                       int min_uV, int max_uV)
98892 +{
98893 +       uint8_t volt_bits;
98894 +       uint8_t regnr;
98895 +       int regulator_id;
98896 +       int millivolts;
98897 +       struct pcf50633 *pcf = rdev_get_drvdata(rdev);;
98898 +
98899 +       regulator_id = rdev_get_id(rdev);
98900 +
98901 +       if (regulator_id >= PCF50633_NUM_REGULATORS)
98902 +               return -EINVAL;
98903 +
98904 +       millivolts = min_uV / 1000;
98905 +
98906 +       regnr = pcf50633_regulator_registers[regulator_id];
98907 +
98908 +       switch (regulator_id) {
98909 +       case PCF50633_REGULATOR_AUTO:
98910 +               volt_bits = auto_voltage_bits(millivolts);
98911 +               break;
98912 +       case PCF50633_REGULATOR_DOWN1:
98913 +               volt_bits = down_voltage_bits(millivolts);
98914 +               break;
98915 +       case PCF50633_REGULATOR_DOWN2:
98916 +               volt_bits = down_voltage_bits(millivolts);
98917 +               break;
98918 +       case PCF50633_REGULATOR_LDO1:
98919 +       case PCF50633_REGULATOR_LDO2:
98920 +       case PCF50633_REGULATOR_LDO3:
98921 +       case PCF50633_REGULATOR_LDO4:
98922 +       case PCF50633_REGULATOR_LDO5:
98923 +       case PCF50633_REGULATOR_LDO6:
98924 +       case PCF50633_REGULATOR_HCLDO:
98925 +               volt_bits = ldo_voltage_bits(millivolts);
98926 +               break;
98927 +       default:
98928 +               return -EINVAL;
98929 +       }
98930 +
98931 +       return pcf50633_reg_write(pcf, regnr, volt_bits);
98932 +}
98933 +
98934 +static int pcf50633_regulator_get_voltage(struct regulator_dev *rdev)
98935 +{
98936 +       uint8_t volt_bits;
98937 +       uint8_t regnr;
98938 +       unsigned int rc = 0;
98939 +       int regulator_id = rdev_get_id(rdev);
98940 +       struct pcf50633 *pcf = rdev_get_drvdata(rdev);
98941 +
98942 +       if (regulator_id >= PCF50633_NUM_REGULATORS)
98943 +               return -EINVAL;
98944 +
98945 +       regnr = pcf50633_regulator_registers[regulator_id];
98946 +       volt_bits = pcf50633_reg_read(pcf, regnr);
98947 +
98948 +       switch (regulator_id) {
98949 +       case PCF50633_REGULATOR_AUTO:
98950 +               rc = auto_voltage_value(volt_bits);
98951 +               break;
98952 +       case PCF50633_REGULATOR_DOWN1:
98953 +               rc = down_voltage_value(volt_bits);
98954 +               break;
98955 +       case PCF50633_REGULATOR_DOWN2:
98956 +               rc = down_voltage_value(volt_bits);
98957 +               break;
98958 +       case PCF50633_REGULATOR_LDO1:
98959 +       case PCF50633_REGULATOR_LDO2:
98960 +       case PCF50633_REGULATOR_LDO3:
98961 +       case PCF50633_REGULATOR_LDO4:
98962 +       case PCF50633_REGULATOR_LDO5:
98963 +       case PCF50633_REGULATOR_LDO6:
98964 +       case PCF50633_REGULATOR_HCLDO:
98965 +               rc = ldo_voltage_value(volt_bits);
98966 +               break;
98967 +       default:
98968 +               return -EINVAL;
98969 +       }
98970 +
98971 +       return rc * 1000;
98972 +}
98973 +
98974 +static int pcf50633_regulator_enable(struct regulator_dev *rdev)
98975 +{
98976 +       uint8_t regnr;
98977 +       int regulator_id = rdev_get_id(rdev);
98978 +       struct pcf50633 *pcf = rdev_get_drvdata(rdev);
98979 +
98980 +       if (regulator_id >= PCF50633_NUM_REGULATORS)
98981 +               return -EINVAL;
98982 +
98983 +       /* the *ENA register is always one after the *OUT register */
98984 +       regnr = pcf50633_regulator_registers[regulator_id] + 1;
98985 +
98986 +       pcf50633_reg_set_bit_mask(pcf, regnr, PCF50633_REGULATOR_ON,
98987 +                      PCF50633_REGULATOR_ON);
98988 +
98989 +       return 0;
98990 +}
98991 +
98992 +static int pcf50633_regulator_disable(struct regulator_dev *rdev)
98993 +{
98994 +       uint8_t regnr;
98995 +       int regulator_id = rdev_get_id(rdev);
98996 +       struct pcf50633 *pcf = rdev_get_drvdata(rdev);
98997 +
98998 +       if (regulator_id >= PCF50633_NUM_REGULATORS)
98999 +               return -EINVAL;
99000 +
99001 +       /* the *ENA register is always one after the *OUT register */
99002 +       regnr = pcf50633_regulator_registers[regulator_id] + 1;
99003 +
99004 +       pcf50633_reg_set_bit_mask(pcf, regnr, PCF50633_REGULATOR_ON, 0);
99005 +
99006 +       return 0;
99007 +}
99008 +
99009 +static int pcf50633_regulator_is_enabled(struct regulator_dev *rdev)
99010 +{
99011 +       uint8_t val, regnr;
99012 +       int regulator_id = rdev_get_id(rdev);
99013 +       struct pcf50633 *pcf = rdev_get_drvdata(rdev);
99014 +
99015 +       if (regulator_id >= PCF50633_NUM_REGULATORS)
99016 +               return -EINVAL;
99017 +
99018 +       /* the *ENA register is always one after the *OUT register */
99019 +       regnr = pcf50633_regulator_registers[regulator_id] + 1;
99020 +       val = pcf50633_reg_read(pcf, regnr) & PCF50633_REGULATOR_ON;
99021 +
99022 +       return val;
99023 +}
99024 +
99025 +struct regulator_ops pcf50633_regulator_ops = {
99026 +       .set_voltage = pcf50633_regulator_set_voltage,
99027 +       .get_voltage = pcf50633_regulator_get_voltage,
99028 +       .enable = pcf50633_regulator_enable,
99029 +       .disable = pcf50633_regulator_disable,
99030 +       .is_enabled = pcf50633_regulator_is_enabled,
99031 +       .set_suspend_enable = pcf50633_regulator_enable,
99032 +       .set_suspend_disable = pcf50633_regulator_disable,
99033 +};
99034 +
99035 +static struct regulator_desc regulators[] = {
99036 +       [PCF50633_REGULATOR_AUTO] =
99037 +               PCF50633_REGULATOR("auto", PCF50633_REGULATOR_AUTO),
99038 +       [PCF50633_REGULATOR_DOWN1] =
99039 +               PCF50633_REGULATOR("down1", PCF50633_REGULATOR_DOWN1),
99040 +       [PCF50633_REGULATOR_DOWN2] =
99041 +               PCF50633_REGULATOR("down2", PCF50633_REGULATOR_DOWN2),
99042 +       [PCF50633_REGULATOR_LDO1] =
99043 +               PCF50633_REGULATOR("ldo1", PCF50633_REGULATOR_LDO1),
99044 +       [PCF50633_REGULATOR_LDO2] =
99045 +               PCF50633_REGULATOR("ldo2", PCF50633_REGULATOR_LDO2),
99046 +       [PCF50633_REGULATOR_LDO3] =
99047 +               PCF50633_REGULATOR("ldo3", PCF50633_REGULATOR_LDO3),
99048 +       [PCF50633_REGULATOR_LDO4] =
99049 +               PCF50633_REGULATOR("ldo4", PCF50633_REGULATOR_LDO4),
99050 +       [PCF50633_REGULATOR_LDO5] =
99051 +               PCF50633_REGULATOR("ldo5", PCF50633_REGULATOR_LDO5),
99052 +       [PCF50633_REGULATOR_LDO6] =
99053 +               PCF50633_REGULATOR("ldo6", PCF50633_REGULATOR_LDO6),
99054 +       [PCF50633_REGULATOR_HCLDO] =
99055 +               PCF50633_REGULATOR("hcldo", PCF50633_REGULATOR_HCLDO),
99056 +       [PCF50633_REGULATOR_MEMLDO] =
99057 +               PCF50633_REGULATOR("memldo", PCF50633_REGULATOR_MEMLDO),
99058 +};
99059 +
99060 +int __init pcf50633_regulator_probe(struct platform_device *pdev)
99061 +{
99062 +       struct regulator_dev *rdev;
99063 +       struct pcf50633 *pcf;
99064 +
99065 +       pcf = pdev->dev.driver_data;
99066 +
99067 +       rdev = regulator_register(&regulators[pdev->id], &pdev->dev, pcf);
99068 +       if (IS_ERR(rdev))
99069 +               return PTR_ERR(rdev);
99070 +
99071 +       if (pcf->pdata->regulator_registered)
99072 +               pcf->pdata->regulator_registered(pcf, pdev->id);
99073 +
99074 +       return 0;
99075 +}
99076 +
99077 +static int __devexit pcf50633_regulator_remove(struct platform_device *pdev)
99078 +{
99079 +       struct regulator_dev *rdev = platform_get_drvdata(pdev);
99080 +
99081 +       regulator_unregister(rdev);
99082 +
99083 +       return 0;
99084 +}
99085 +
99086 +struct platform_driver pcf50633_regulator_driver = {
99087 +       .driver = {
99088 +               .name = "pcf50633-regltr",
99089 +       },
99090 +       .probe = pcf50633_regulator_probe,
99091 +       .remove = __devexit_p(pcf50633_regulator_remove),
99092 +};
99093 +
99094 +static int __init pcf50633_regulator_init(void)
99095 +{
99096 +       return platform_driver_register(&pcf50633_regulator_driver);
99097 +}
99098 +module_init(pcf50633_regulator_init);
99099 +
99100 +static void __exit pcf50633_regulator_exit(void)
99101 +{
99102 +       platform_driver_unregister(&pcf50633_regulator_driver);
99103 +}
99104 +module_exit(pcf50633_regulator_exit);
99105 +
99106 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
99107 +MODULE_DESCRIPTION("PCF50633 regulator driver");
99108 +MODULE_LICENSE("GPL");
99109 +MODULE_ALIAS("platform:pcf50633-regulator");
99110 --- a/drivers/rtc/Kconfig
99111 +++ b/drivers/rtc/Kconfig
99112 @@ -219,6 +219,18 @@ config RTC_DRV_PCF8583
99113           This driver can also be built as a module. If so, the module
99114           will be called rtc-pcf8583.
99115
99116 +config RTC_DRV_PCF50633
99117 +       tristate "Philips PCF50633"
99118 +       help
99119 +         If you say yes here you get support for the Philips PCF50633
99120 +         PMU's RTC.
99121 +
99122 +config RTC_DRV_PCF50606
99123 +       tristate "Philips PCF50606"
99124 +       help
99125 +         If you say yes here you get support for the Philips PCF50606
99126 +         PMU's RTC.
99127 +
99128  config RTC_DRV_M41T80
99129         tristate "ST M41T65/M41T80/81/82/83/84/85/87"
99130         help
99131 --- a/drivers/rtc/Makefile
99132 +++ b/drivers/rtc/Makefile
99133 @@ -50,6 +50,8 @@ obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max
99134  obj-$(CONFIG_RTC_DRV_OMAP)     += rtc-omap.o
99135  obj-$(CONFIG_RTC_DRV_PCF8563)  += rtc-pcf8563.o
99136  obj-$(CONFIG_RTC_DRV_PCF8583)  += rtc-pcf8583.o
99137 +obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o
99138 +obj-$(CONFIG_RTC_DRV_PCF50606) += rtc-pcf50606.o
99139  obj-$(CONFIG_RTC_DRV_PL030)    += rtc-pl030.o
99140  obj-$(CONFIG_RTC_DRV_PL031)    += rtc-pl031.o
99141  obj-$(CONFIG_RTC_DRV_PARISC)   += rtc-parisc.o
99142 --- /dev/null
99143 +++ b/drivers/rtc/rtc-pcf50606.c
99144 @@ -0,0 +1,300 @@
99145 +/* Philips PCF50606 RTC Driver
99146 + *
99147 + * (C) 2006-2008 by Openmoko, Inc.
99148 + * Author: Balaji Rao <balajirrao@openmoko.org>
99149 + * All rights reserved.
99150 + *
99151 + * Broken down from monstrous PCF50606 driver mainly by
99152 + * Harald Welte, Andy Green and Werner Almesberger
99153 + *
99154 + * This program is free software; you can redistribute it and/or
99155 + * modify it under the terms of the GNU General Public License as
99156 + * published by the Free Software Foundation; either version 2 of
99157 + * the License, or (at your option) any later version.
99158 + *
99159 + * This program is distributed in the hope that it will be useful,
99160 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
99161 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
99162 + * GNU General Public License for more details.
99163 + *
99164 + * You should have received a copy of the GNU General Public License
99165 + * along with this program; if not, write to the Free Software
99166 + * Foundation, Inc., 59 Temple Place, Suite 060, Boston,
99167 + * MA 02111-1307 USA
99168 + */
99169 +
99170 +#include <linux/rtc.h>
99171 +#include <linux/platform_device.h>
99172 +#include <linux/bcd.h>
99173 +
99174 +#include <linux/mfd/pcf50606/core.h>
99175 +#include <linux/mfd/pcf50606/rtc.h>
99176 +
99177 +enum pcf50606_time_indexes {
99178 +       PCF50606_TI_SEC = 0,
99179 +       PCF50606_TI_MIN,
99180 +       PCF50606_TI_HOUR,
99181 +       PCF50606_TI_WKDAY,
99182 +       PCF50606_TI_DAY,
99183 +       PCF50606_TI_MONTH,
99184 +       PCF50606_TI_YEAR,
99185 +       PCF50606_TI_EXTENT /* always last */
99186 +};
99187 +
99188 +
99189 +struct pcf50606_time {
99190 +       u_int8_t time[PCF50606_TI_EXTENT];
99191 +};
99192 +
99193 +static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50606_time *pcf)
99194 +{
99195 +       rtc->tm_sec = bcd2bin(pcf->time[PCF50606_TI_SEC]);
99196 +       rtc->tm_min = bcd2bin(pcf->time[PCF50606_TI_MIN]);
99197 +       rtc->tm_hour = bcd2bin(pcf->time[PCF50606_TI_HOUR]);
99198 +       rtc->tm_wday = bcd2bin(pcf->time[PCF50606_TI_WKDAY]);
99199 +       rtc->tm_mday = bcd2bin(pcf->time[PCF50606_TI_DAY]);
99200 +       rtc->tm_mon = bcd2bin(pcf->time[PCF50606_TI_MONTH]);
99201 +       rtc->tm_year = bcd2bin(pcf->time[PCF50606_TI_YEAR]) + 100;
99202 +}
99203 +
99204 +static void rtc2pcf_time(struct pcf50606_time *pcf, struct rtc_time *rtc)
99205 +{
99206 +       pcf->time[PCF50606_TI_SEC] = bin2bcd(rtc->tm_sec);
99207 +       pcf->time[PCF50606_TI_MIN] = bin2bcd(rtc->tm_min);
99208 +       pcf->time[PCF50606_TI_HOUR] = bin2bcd(rtc->tm_hour);
99209 +       pcf->time[PCF50606_TI_WKDAY] = bin2bcd(rtc->tm_wday);
99210 +       pcf->time[PCF50606_TI_DAY] = bin2bcd(rtc->tm_mday);
99211 +       pcf->time[PCF50606_TI_MONTH] = bin2bcd(rtc->tm_mon);
99212 +       pcf->time[PCF50606_TI_YEAR] = bin2bcd(rtc->tm_year - 100);
99213 +}
99214 +
99215 +static int pcf50606_rtc_ioctl(struct device *dev, unsigned int cmd,
99216 +                             unsigned long arg)
99217 +{
99218 +       struct pcf50606 *pcf;
99219 +
99220 +       pcf = dev_get_drvdata(dev);
99221 +
99222 +       switch (cmd) {
99223 +       case RTC_AIE_OFF:
99224 +               /* disable the alarm interrupt */
99225 +               pcf->rtc.alarm_enabled = 0;
99226 +               pcf50606_irq_mask(pcf, PCF50606_IRQ_ALARM);
99227 +               return 0;
99228 +       case RTC_AIE_ON:
99229 +               /* enable the alarm interrupt */
99230 +               pcf->rtc.alarm_enabled = 1;
99231 +               pcf50606_irq_unmask(pcf, PCF50606_IRQ_ALARM);
99232 +               return 0;
99233 +       case RTC_PIE_OFF:
99234 +               /* disable periodic interrupt (hz tick) */
99235 +               pcf->rtc.second_enabled = 0;
99236 +               pcf50606_irq_mask(pcf, PCF50606_IRQ_SECOND);
99237 +               return 0;
99238 +       case RTC_PIE_ON:
99239 +               /* ensable periodic interrupt (hz tick) */
99240 +               pcf->rtc.second_enabled = 1;
99241 +               pcf50606_irq_unmask(pcf, PCF50606_IRQ_SECOND);
99242 +               return 0;
99243 +       }
99244 +       return -ENOIOCTLCMD;
99245 +}
99246 +
99247 +static int pcf50606_rtc_read_time(struct device *dev, struct rtc_time *tm)
99248 +{
99249 +       struct pcf50606 *pcf;
99250 +       struct pcf50606_time pcf_tm;
99251 +       int ret;
99252 +
99253 +       pcf = dev_get_drvdata(dev);
99254 +
99255 +       ret = pcf50606_read_block(pcf, PCF50606_REG_RTCSC,
99256 +                                           PCF50606_TI_EXTENT,
99257 +                                           &pcf_tm.time[0]);
99258 +       if (ret != PCF50606_TI_EXTENT)
99259 +               dev_err(dev, "Failed to read time\n");
99260 +
99261 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
99262 +               pcf_tm.time[PCF50606_TI_DAY],
99263 +               pcf_tm.time[PCF50606_TI_MONTH],
99264 +               pcf_tm.time[PCF50606_TI_YEAR],
99265 +               pcf_tm.time[PCF50606_TI_HOUR],
99266 +               pcf_tm.time[PCF50606_TI_MIN],
99267 +               pcf_tm.time[PCF50606_TI_SEC]);
99268 +
99269 +       pcf2rtc_time(tm, &pcf_tm);
99270 +
99271 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
99272 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
99273 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
99274 +
99275 +       return 0;
99276 +}
99277 +
99278 +static int pcf50606_rtc_set_time(struct device *dev, struct rtc_time *tm)
99279 +{
99280 +       struct pcf50606 *pcf;
99281 +       struct pcf50606_time pcf_tm;
99282 +       int ret;
99283 +       int second_masked, alarm_masked;
99284 +
99285 +       pcf = dev_get_drvdata(dev);
99286 +
99287 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
99288 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
99289 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
99290 +       rtc2pcf_time(&pcf_tm, tm);
99291 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
99292 +               pcf_tm.time[PCF50606_TI_DAY],
99293 +               pcf_tm.time[PCF50606_TI_MONTH],
99294 +               pcf_tm.time[PCF50606_TI_YEAR],
99295 +               pcf_tm.time[PCF50606_TI_HOUR],
99296 +               pcf_tm.time[PCF50606_TI_MIN],
99297 +               pcf_tm.time[PCF50606_TI_SEC]);
99298 +
99299 +
99300 +       second_masked = pcf50606_irq_mask_get(pcf, PCF50606_IRQ_SECOND);
99301 +       alarm_masked = pcf50606_irq_mask_get(pcf, PCF50606_IRQ_ALARM);
99302 +
99303 +       if (!second_masked)
99304 +               pcf50606_irq_mask(pcf, PCF50606_IRQ_SECOND);
99305 +       if (!alarm_masked)
99306 +               pcf50606_irq_mask(pcf, PCF50606_IRQ_ALARM);
99307 +
99308 +       ret = pcf50606_write_block(pcf, PCF50606_REG_RTCSC,
99309 +                                            PCF50606_TI_EXTENT,
99310 +                                            &pcf_tm.time[0]);
99311 +       if (ret)
99312 +               dev_err(dev, "Failed to set time %d\n", ret);
99313 +
99314 +       if (!second_masked)
99315 +               pcf50606_irq_unmask(pcf, PCF50606_IRQ_SECOND);
99316 +       if (!alarm_masked)
99317 +               pcf50606_irq_unmask(pcf, PCF50606_IRQ_ALARM);
99318 +
99319 +
99320 +       return 0;
99321 +}
99322 +
99323 +static int pcf50606_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
99324 +{
99325 +       struct pcf50606 *pcf;
99326 +       struct pcf50606_time pcf_tm;
99327 +       int ret;
99328 +
99329 +       pcf = dev_get_drvdata(dev);
99330 +
99331 +       alrm->enabled = pcf->rtc.alarm_enabled;
99332 +
99333 +       ret = pcf50606_read_block(pcf, PCF50606_REG_RTCSCA,
99334 +                               PCF50606_TI_EXTENT, &pcf_tm.time[0]);
99335 +
99336 +       if (ret != PCF50606_TI_EXTENT)
99337 +               dev_err(dev, "Failed to read Alarm time :-(\n");
99338 +
99339 +       pcf2rtc_time(&alrm->time, &pcf_tm);
99340 +
99341 +       return 0;
99342 +}
99343 +
99344 +static int pcf50606_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
99345 +{
99346 +       struct pcf50606 *pcf;
99347 +       struct pcf50606_time pcf_tm;
99348 +       int ret, alarm_masked;
99349 +
99350 +       pcf = dev_get_drvdata(dev);
99351 +
99352 +       rtc2pcf_time(&pcf_tm, &alrm->time);
99353 +
99354 +       /* do like mktime does and ignore tm_wday */
99355 +       pcf_tm.time[PCF50606_TI_WKDAY] = 7;
99356 +
99357 +       alarm_masked = pcf50606_irq_mask_get(pcf, PCF50606_IRQ_ALARM);
99358 +
99359 +       /* disable alarm interrupt */
99360 +       if (!alarm_masked)
99361 +               pcf50606_irq_mask(pcf, PCF50606_IRQ_ALARM);
99362 +
99363 +       ret = pcf50606_write_block(pcf, PCF50606_REG_RTCSCA,
99364 +                                       PCF50606_TI_EXTENT, &pcf_tm.time[0]);
99365 +       if (ret)
99366 +               dev_err(dev, "Failed to write alarm time  %d\n", ret);
99367 +
99368 +       if (!alarm_masked)
99369 +               pcf50606_irq_unmask(pcf, PCF50606_IRQ_ALARM);
99370 +
99371 +       return 0;
99372 +}
99373 +static struct rtc_class_ops pcf50606_rtc_ops = {
99374 +       .ioctl          = pcf50606_rtc_ioctl,
99375 +       .read_time      = pcf50606_rtc_read_time,
99376 +       .set_time       = pcf50606_rtc_set_time,
99377 +       .read_alarm     = pcf50606_rtc_read_alarm,
99378 +       .set_alarm      = pcf50606_rtc_set_alarm,
99379 +};
99380 +
99381 +static void pcf50606_rtc_irq(struct pcf50606 *pcf, int irq, void *unused)
99382 +{
99383 +       switch (irq) {
99384 +       case PCF50606_IRQ_ALARM:
99385 +               rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_AF | RTC_IRQF);
99386 +               break;
99387 +       case PCF50606_IRQ_SECOND:
99388 +               rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_PF | RTC_IRQF);
99389 +               break;
99390 +       }
99391 +}
99392 +
99393 +static int pcf50606_rtc_probe(struct platform_device *pdev)
99394 +{
99395 +       struct rtc_device *rtc;
99396 +       struct pcf50606 *pcf;
99397 +
99398 +       rtc = rtc_device_register("pcf50606", &pdev->dev,
99399 +                                       &pcf50606_rtc_ops, THIS_MODULE);
99400 +       if (IS_ERR(rtc))
99401 +               return -ENODEV;
99402 +
99403 +       pcf = platform_get_drvdata(pdev);
99404 +
99405 +       /* Set up IRQ handlers */
99406 +       pcf->irq_handler[PCF50606_IRQ_ALARM].handler = pcf50606_rtc_irq;
99407 +       pcf->irq_handler[PCF50606_IRQ_SECOND].handler = pcf50606_rtc_irq;
99408 +
99409 +       pcf->rtc.rtc_dev = rtc;
99410 +
99411 +       return 0;
99412 +}
99413 +
99414 +static int pcf50606_rtc_remove(struct platform_device *pdev)
99415 +{
99416 +       return 0;
99417 +}
99418 +
99419 +
99420 +static struct platform_driver pcf50606_rtc_driver = {
99421 +       .driver = {
99422 +               .name = "pcf50606-rtc",
99423 +       },
99424 +       .probe = pcf50606_rtc_probe,
99425 +       .remove = __devexit_p(pcf50606_rtc_remove),
99426 +};
99427 +
99428 +static int __init pcf50606_rtc_init(void)
99429 +{
99430 +       return platform_driver_register(&pcf50606_rtc_driver);
99431 +}
99432 +module_init(pcf50606_rtc_init);
99433 +
99434 +static void __exit pcf50606_rtc_exit(void)
99435 +{
99436 +       platform_driver_unregister(&pcf50606_rtc_driver);
99437 +}
99438 +module_exit(pcf50606_rtc_exit);
99439 +
99440 +
99441 +MODULE_DESCRIPTION("RTC driver for NXP PCF50606 power management unit");
99442 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
99443 +MODULE_LICENSE("GPL");
99444 +
99445 --- /dev/null
99446 +++ b/drivers/rtc/rtc-pcf50633.c
99447 @@ -0,0 +1,300 @@
99448 +/* Philips PCF50633 RTC Driver
99449 + *
99450 + * (C) 2006-2008 by Openmoko, Inc.
99451 + * Author: Balaji Rao <balajirrao@openmoko.org>
99452 + * All rights reserved.
99453 + *
99454 + * Broken down from monstrous PCF50633 driver mainly by
99455 + * Harald Welte, Andy Green and Werner Almesberger
99456 + *
99457 + * This program is free software; you can redistribute it and/or
99458 + * modify it under the terms of the GNU General Public License as
99459 + * published by the Free Software Foundation; either version 2 of
99460 + * the License, or (at your option) any later version.
99461 + *
99462 + * This program is distributed in the hope that it will be useful,
99463 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
99464 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
99465 + * GNU General Public License for more details.
99466 + *
99467 + * You should have received a copy of the GNU General Public License
99468 + * along with this program; if not, write to the Free Software
99469 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
99470 + * MA 02111-1307 USA
99471 + */
99472 +
99473 +#include <linux/rtc.h>
99474 +#include <linux/platform_device.h>
99475 +#include <linux/bcd.h>
99476 +
99477 +#include <linux/mfd/pcf50633/core.h>
99478 +#include <linux/mfd/pcf50633/rtc.h>
99479 +
99480 +enum pcf50633_time_indexes {
99481 +       PCF50633_TI_SEC = 0,
99482 +       PCF50633_TI_MIN,
99483 +       PCF50633_TI_HOUR,
99484 +       PCF50633_TI_WKDAY,
99485 +       PCF50633_TI_DAY,
99486 +       PCF50633_TI_MONTH,
99487 +       PCF50633_TI_YEAR,
99488 +       PCF50633_TI_EXTENT /* always last */
99489 +};
99490 +
99491 +
99492 +struct pcf50633_time {
99493 +       u_int8_t time[PCF50633_TI_EXTENT];
99494 +};
99495 +
99496 +static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50633_time *pcf)
99497 +{
99498 +       rtc->tm_sec = bcd2bin(pcf->time[PCF50633_TI_SEC]);
99499 +       rtc->tm_min = bcd2bin(pcf->time[PCF50633_TI_MIN]);
99500 +       rtc->tm_hour = bcd2bin(pcf->time[PCF50633_TI_HOUR]);
99501 +       rtc->tm_wday = bcd2bin(pcf->time[PCF50633_TI_WKDAY]);
99502 +       rtc->tm_mday = bcd2bin(pcf->time[PCF50633_TI_DAY]);
99503 +       rtc->tm_mon = bcd2bin(pcf->time[PCF50633_TI_MONTH]);
99504 +       rtc->tm_year = bcd2bin(pcf->time[PCF50633_TI_YEAR]) + 100;
99505 +}
99506 +
99507 +static void rtc2pcf_time(struct pcf50633_time *pcf, struct rtc_time *rtc)
99508 +{
99509 +       pcf->time[PCF50633_TI_SEC] = bin2bcd(rtc->tm_sec);
99510 +       pcf->time[PCF50633_TI_MIN] = bin2bcd(rtc->tm_min);
99511 +       pcf->time[PCF50633_TI_HOUR] = bin2bcd(rtc->tm_hour);
99512 +       pcf->time[PCF50633_TI_WKDAY] = bin2bcd(rtc->tm_wday);
99513 +       pcf->time[PCF50633_TI_DAY] = bin2bcd(rtc->tm_mday);
99514 +       pcf->time[PCF50633_TI_MONTH] = bin2bcd(rtc->tm_mon);
99515 +       pcf->time[PCF50633_TI_YEAR] = bin2bcd(rtc->tm_year - 100);
99516 +}
99517 +
99518 +static int pcf50633_rtc_ioctl(struct device *dev, unsigned int cmd,
99519 +                             unsigned long arg)
99520 +{
99521 +       struct pcf50633 *pcf;
99522 +
99523 +       pcf = dev_get_drvdata(dev);
99524 +
99525 +       switch (cmd) {
99526 +       case RTC_AIE_OFF:
99527 +               /* disable the alarm interrupt */
99528 +               pcf->rtc.alarm_enabled = 0;
99529 +               pcf50633_irq_mask(pcf, PCF50633_IRQ_ALARM);
99530 +               return 0;
99531 +       case RTC_AIE_ON:
99532 +               /* enable the alarm interrupt */
99533 +               pcf->rtc.alarm_enabled = 1;
99534 +               pcf50633_irq_unmask(pcf, PCF50633_IRQ_ALARM);
99535 +               return 0;
99536 +       case RTC_PIE_OFF:
99537 +               /* disable periodic interrupt (hz tick) */
99538 +               pcf->rtc.second_enabled = 0;
99539 +               pcf50633_irq_mask(pcf, PCF50633_IRQ_SECOND);
99540 +               return 0;
99541 +       case RTC_PIE_ON:
99542 +               /* ensable periodic interrupt (hz tick) */
99543 +               pcf->rtc.second_enabled = 1;
99544 +               pcf50633_irq_unmask(pcf, PCF50633_IRQ_SECOND);
99545 +               return 0;
99546 +       }
99547 +       return -ENOIOCTLCMD;
99548 +}
99549 +
99550 +static int pcf50633_rtc_read_time(struct device *dev, struct rtc_time *tm)
99551 +{
99552 +       struct pcf50633 *pcf;
99553 +       struct pcf50633_time pcf_tm;
99554 +       int ret;
99555 +
99556 +       pcf = dev_get_drvdata(dev);
99557 +
99558 +       ret = pcf50633_read_block(pcf, PCF50633_REG_RTCSC,
99559 +                                           PCF50633_TI_EXTENT,
99560 +                                           &pcf_tm.time[0]);
99561 +       if (ret != PCF50633_TI_EXTENT)
99562 +               dev_err(dev, "Failed to read time\n");
99563 +
99564 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
99565 +               pcf_tm.time[PCF50633_TI_DAY],
99566 +               pcf_tm.time[PCF50633_TI_MONTH],
99567 +               pcf_tm.time[PCF50633_TI_YEAR],
99568 +               pcf_tm.time[PCF50633_TI_HOUR],
99569 +               pcf_tm.time[PCF50633_TI_MIN],
99570 +               pcf_tm.time[PCF50633_TI_SEC]);
99571 +
99572 +       pcf2rtc_time(tm, &pcf_tm);
99573 +
99574 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
99575 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
99576 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
99577 +
99578 +       return 0;
99579 +}
99580 +
99581 +static int pcf50633_rtc_set_time(struct device *dev, struct rtc_time *tm)
99582 +{
99583 +       struct pcf50633 *pcf;
99584 +       struct pcf50633_time pcf_tm;
99585 +       int ret;
99586 +       int second_masked, alarm_masked;
99587 +
99588 +       pcf = dev_get_drvdata(dev);
99589 +
99590 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
99591 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
99592 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
99593 +       rtc2pcf_time(&pcf_tm, tm);
99594 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
99595 +               pcf_tm.time[PCF50633_TI_DAY],
99596 +               pcf_tm.time[PCF50633_TI_MONTH],
99597 +               pcf_tm.time[PCF50633_TI_YEAR],
99598 +               pcf_tm.time[PCF50633_TI_HOUR],
99599 +               pcf_tm.time[PCF50633_TI_MIN],
99600 +               pcf_tm.time[PCF50633_TI_SEC]);
99601 +
99602 +
99603 +       second_masked = pcf50633_irq_mask_get(pcf, PCF50633_IRQ_SECOND);
99604 +       alarm_masked = pcf50633_irq_mask_get(pcf, PCF50633_IRQ_ALARM);
99605 +
99606 +       if (!second_masked)
99607 +               pcf50633_irq_mask(pcf, PCF50633_IRQ_SECOND);
99608 +       if (!alarm_masked)
99609 +               pcf50633_irq_mask(pcf, PCF50633_IRQ_ALARM);
99610 +
99611 +       ret = pcf50633_write_block(pcf, PCF50633_REG_RTCSC,
99612 +                                            PCF50633_TI_EXTENT,
99613 +                                            &pcf_tm.time[0]);
99614 +       if (ret)
99615 +               dev_err(dev, "Failed to set time %d\n", ret);
99616 +
99617 +       if (!second_masked)
99618 +               pcf50633_irq_unmask(pcf, PCF50633_IRQ_SECOND);
99619 +       if (!alarm_masked)
99620 +               pcf50633_irq_unmask(pcf, PCF50633_IRQ_ALARM);
99621 +
99622 +
99623 +       return 0;
99624 +}
99625 +
99626 +static int pcf50633_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
99627 +{
99628 +       struct pcf50633 *pcf;
99629 +       struct pcf50633_time pcf_tm;
99630 +       int ret;
99631 +
99632 +       pcf = dev_get_drvdata(dev);
99633 +
99634 +       alrm->enabled = pcf->rtc.alarm_enabled;
99635 +
99636 +       ret = pcf50633_read_block(pcf, PCF50633_REG_RTCSCA,
99637 +                               PCF50633_TI_EXTENT, &pcf_tm.time[0]);
99638 +
99639 +       if (ret != PCF50633_TI_EXTENT)
99640 +               dev_err(dev, "Failed to read Alarm time :-(\n");
99641 +
99642 +       pcf2rtc_time(&alrm->time, &pcf_tm);
99643 +
99644 +       return 0;
99645 +}
99646 +
99647 +static int pcf50633_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
99648 +{
99649 +       struct pcf50633 *pcf;
99650 +       struct pcf50633_time pcf_tm;
99651 +       int ret, alarm_masked;
99652 +
99653 +       pcf = dev_get_drvdata(dev);
99654 +
99655 +       rtc2pcf_time(&pcf_tm, &alrm->time);
99656 +
99657 +       /* do like mktime does and ignore tm_wday */
99658 +       pcf_tm.time[PCF50633_TI_WKDAY] = 7;
99659 +
99660 +       alarm_masked = pcf50633_irq_mask_get(pcf, PCF50633_IRQ_ALARM);
99661 +
99662 +       /* disable alarm interrupt */
99663 +       if (!alarm_masked)
99664 +               pcf50633_irq_mask(pcf, PCF50633_IRQ_ALARM);
99665 +
99666 +       ret = pcf50633_write_block(pcf, PCF50633_REG_RTCSCA,
99667 +                                       PCF50633_TI_EXTENT, &pcf_tm.time[0]);
99668 +       if (ret)
99669 +               dev_err(dev, "Failed to write alarm time  %d\n", ret);
99670 +
99671 +       if (!alarm_masked)
99672 +               pcf50633_irq_unmask(pcf, PCF50633_IRQ_ALARM);
99673 +
99674 +       return 0;
99675 +}
99676 +static struct rtc_class_ops pcf50633_rtc_ops = {
99677 +       .ioctl          = pcf50633_rtc_ioctl,
99678 +       .read_time      = pcf50633_rtc_read_time,
99679 +       .set_time       = pcf50633_rtc_set_time,
99680 +       .read_alarm     = pcf50633_rtc_read_alarm,
99681 +       .set_alarm      = pcf50633_rtc_set_alarm,
99682 +};
99683 +
99684 +static void pcf50633_rtc_irq(struct pcf50633 *pcf, int irq, void *unused)
99685 +{
99686 +       switch (irq) {
99687 +       case PCF50633_IRQ_ALARM:
99688 +               rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_AF | RTC_IRQF);
99689 +               break;
99690 +       case PCF50633_IRQ_SECOND:
99691 +               rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_PF | RTC_IRQF);
99692 +               break;
99693 +       }
99694 +}
99695 +
99696 +static int pcf50633_rtc_probe(struct platform_device *pdev)
99697 +{
99698 +       struct rtc_device *rtc;
99699 +       struct pcf50633 *pcf;
99700 +
99701 +       rtc = rtc_device_register("pcf50633", &pdev->dev,
99702 +                                       &pcf50633_rtc_ops, THIS_MODULE);
99703 +       if (IS_ERR(rtc))
99704 +               return -ENODEV;
99705 +
99706 +       pcf = platform_get_drvdata(pdev);
99707 +
99708 +       /* Set up IRQ handlers */
99709 +       pcf->irq_handler[PCF50633_IRQ_ALARM].handler = pcf50633_rtc_irq;
99710 +       pcf->irq_handler[PCF50633_IRQ_SECOND].handler = pcf50633_rtc_irq;
99711 +
99712 +       pcf->rtc.rtc_dev = rtc;
99713 +
99714 +       return 0;
99715 +}
99716 +
99717 +static int pcf50633_rtc_remove(struct platform_device *pdev)
99718 +{
99719 +       return 0;
99720 +}
99721 +
99722 +
99723 +static struct platform_driver pcf50633_rtc_driver = {
99724 +       .driver = {
99725 +               .name = "pcf50633-rtc",
99726 +       },
99727 +       .probe = pcf50633_rtc_probe,
99728 +       .remove = __devexit_p(pcf50633_rtc_remove),
99729 +};
99730 +
99731 +static int __init pcf50633_rtc_init(void)
99732 +{
99733 +       return platform_driver_register(&pcf50633_rtc_driver);
99734 +}
99735 +module_init(pcf50633_rtc_init);
99736 +
99737 +static void __exit pcf50633_rtc_exit(void)
99738 +{
99739 +       platform_driver_unregister(&pcf50633_rtc_driver);
99740 +}
99741 +module_exit(pcf50633_rtc_exit);
99742 +
99743 +
99744 +MODULE_DESCRIPTION("RTC driver for NXP PCF50633 power management unit");
99745 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
99746 +MODULE_LICENSE("GPL");
99747 +
99748 --- a/drivers/rtc/rtc-s3c.c
99749 +++ b/drivers/rtc/rtc-s3c.c
99750 @@ -26,7 +26,7 @@
99751  #include <asm/uaccess.h>
99752  #include <asm/io.h>
99753  #include <asm/irq.h>
99754 -#include <asm/plat-s3c/regs-rtc.h>
99755 +#include <plat/regs-rtc.h>
99756
99757  /* I have yet to find an S3C implementation with more than one
99758   * of these rtc blocks in */
99759 --- a/drivers/serial/Kconfig
99760 +++ b/drivers/serial/Kconfig
99761 @@ -447,7 +447,7 @@ config SERIAL_CLPS711X_CONSOLE
99762
99763  config SERIAL_SAMSUNG
99764         tristate "Samsung SoC serial support"
99765 -       depends on ARM && PLAT_S3C24XX
99766 +       depends on ARM && PLAT_S3C
99767         select SERIAL_CORE
99768         help
99769           Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
99770 @@ -455,6 +455,16 @@ config SERIAL_SAMSUNG
99771           provide all of these ports, depending on how the serial port
99772           pins are configured.
99773
99774 +config SERIAL_SAMSUNG_UARTS
99775 +       int
99776 +       depends on SERIAL_SAMSUNG
99777 +       default 2 if ARCH_S3C2400
99778 +       default 4 if ARCH_S3C64XX || CPU_S3C2443
99779 +       default 3
99780 +       help
99781 +         Select the number of available UART ports for the Samsung S3C
99782 +         serial driver
99783 +
99784  config SERIAL_SAMSUNG_DEBUG
99785         bool "Samsung SoC serial debug"
99786         depends on SERIAL_SAMSUNG && DEBUG_LL
99787 @@ -508,7 +518,20 @@ config SERIAL_S3C2440
99788         help
99789           Serial port support for the Samsung S3C2440 and S3C2442 SoC
99790
99791 -
99792 +config SERIAL_S3C24A0
99793 +       tristate "Samsung S3C24A0 Serial port support"
99794 +       depends on SERIAL_SAMSUNG && CPU_S3C24A0
99795 +       default y if CPU_S3C24A0
99796 +       help
99797 +         Serial port support for the Samsung S3C24A0 SoC
99798 +
99799 +config SERIAL_S3C6400
99800 +       tristate "Samsung S3C6400/S3C6410 Serial port support"
99801 +       depends on SERIAL_SAMSUNG && (CPU_S3C600 || CPU_S3C6410)
99802 +       default y
99803 +       help
99804 +         Serial port support for the Samsung S3C6400 and S3C6410
99805 +         SoCs
99806
99807  config SERIAL_DZ
99808         bool "DECstation DZ serial driver"
99809 --- a/drivers/serial/Makefile
99810 +++ b/drivers/serial/Makefile
99811 @@ -41,6 +41,8 @@ obj-$(CONFIG_SERIAL_S3C2400) += s3c2400.
99812  obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
99813  obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o
99814  obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
99815 +obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
99816 +obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
99817  obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
99818  obj-$(CONFIG_SERIAL_MUX) += mux.o
99819  obj-$(CONFIG_SERIAL_68328) += 68328serial.o
99820 --- a/drivers/serial/s3c2410.c
99821 +++ b/drivers/serial/s3c2410.c
99822 @@ -19,6 +19,7 @@
99823  #include <linux/serial.h>
99824
99825  #include <asm/irq.h>
99826 +
99827  #include <mach/hardware.h>
99828
99829  #include <plat/regs-serial.h>
99830 --- /dev/null
99831 +++ b/drivers/serial/s3c24a0.c
99832 @@ -0,0 +1,118 @@
99833 +/* linux/drivers/serial/s3c24a0.c
99834 + *
99835 + * Driver for Samsung S3C24A0 SoC onboard UARTs.
99836 + *
99837 + * Based on drivers/serial/s3c2410.c
99838 + *
99839 + * Author: Sandeep Patil <sandeep.patil@azingo.com>
99840 + *
99841 + * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
99842 + *     http://armlinux.simtec.co.uk/
99843 + *
99844 + * This program is free software; you can redistribute it and/or modify
99845 + * it under the terms of the GNU General Public License version 2 as
99846 + * published by the Free Software Foundation.
99847 +*/
99848 +
99849 +#include <linux/module.h>
99850 +#include <linux/ioport.h>
99851 +#include <linux/platform_device.h>
99852 +#include <linux/init.h>
99853 +#include <linux/serial_core.h>
99854 +#include <linux/serial.h>
99855 +#include <linux/io.h>
99856 +#include <linux/irq.h>
99857 +
99858 +#include <mach/hardware.h>
99859 +
99860 +#include <plat/regs-serial.h>
99861 +#include <mach/regs-gpio.h>
99862 +
99863 +#include "samsung.h"
99864 +
99865 +static int s3c24a0_serial_setsource(struct uart_port *port,
99866 +                                   struct s3c24xx_uart_clksrc *clk)
99867 +{
99868 +       unsigned long ucon = rd_regl(port, S3C2410_UCON);
99869 +
99870 +       if (strcmp(clk->name, "uclk") == 0)
99871 +               ucon |= S3C2410_UCON_UCLK;
99872 +       else
99873 +               ucon &= ~S3C2410_UCON_UCLK;
99874 +
99875 +       wr_regl(port, S3C2410_UCON, ucon);
99876 +       return 0;
99877 +}
99878 +
99879 +static int s3c24a0_serial_getsource(struct uart_port *port,
99880 +                                   struct s3c24xx_uart_clksrc *clk)
99881 +{
99882 +       unsigned long ucon = rd_regl(port, S3C2410_UCON);
99883 +
99884 +       clk->divisor = 1;
99885 +       clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
99886 +
99887 +       return 0;
99888 +}
99889 +
99890 +static int s3c24a0_serial_resetport(struct uart_port *port,
99891 +                                   struct s3c2410_uartcfg *cfg)
99892 +{
99893 +       dbg("s3c24a0_serial_resetport: port=%p (%08lx), cfg=%p\n",
99894 +           port, port->mapbase, cfg);
99895 +
99896 +       wr_regl(port, S3C2410_UCON,  cfg->ucon);
99897 +       wr_regl(port, S3C2410_ULCON, cfg->ulcon);
99898 +
99899 +       /* reset both fifos */
99900 +
99901 +       wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
99902 +       wr_regl(port, S3C2410_UFCON, cfg->ufcon);
99903 +
99904 +       return 0;
99905 +}
99906 +
99907 +static struct s3c24xx_uart_info s3c24a0_uart_inf = {
99908 +       .name           = "Samsung S3C24A0 UART",
99909 +       .type           = PORT_S3C2410,
99910 +       .fifosize       = 16,
99911 +       .rx_fifomask    = S3C24A0_UFSTAT_RXMASK,
99912 +       .rx_fifoshift   = S3C24A0_UFSTAT_RXSHIFT,
99913 +       .rx_fifofull    = S3C24A0_UFSTAT_RXFULL,
99914 +       .tx_fifofull    = S3C24A0_UFSTAT_TXFULL,
99915 +       .tx_fifomask    = S3C24A0_UFSTAT_TXMASK,
99916 +       .tx_fifoshift   = S3C24A0_UFSTAT_TXSHIFT,
99917 +       .get_clksrc     = s3c24a0_serial_getsource,
99918 +       .set_clksrc     = s3c24a0_serial_setsource,
99919 +       .reset_port     = s3c24a0_serial_resetport,
99920 +};
99921 +
99922 +static int s3c24a0_serial_probe(struct platform_device *dev)
99923 +{
99924 +       return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf);
99925 +}
99926 +
99927 +static struct platform_driver s3c24a0_serial_drv = {
99928 +       .probe          = s3c24a0_serial_probe,
99929 +       .remove         = s3c24xx_serial_remove,
99930 +       .driver         = {
99931 +               .name   = "s3c24a0-uart",
99932 +               .owner  = THIS_MODULE,
99933 +       },
99934 +};
99935 +
99936 +s3c24xx_console_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
99937 +
99938 +static int __init s3c24a0_serial_init(void)
99939 +{
99940 +       return s3c24xx_serial_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
99941 +}
99942 +
99943 +static void __exit s3c24a0_serial_exit(void)
99944 +{
99945 +       platform_driver_unregister(&s3c24a0_serial_drv);
99946 +}
99947 +
99948 +module_init(s3c24a0_serial_init);
99949 +module_exit(s3c24a0_serial_exit);
99950 +
99951 --- /dev/null
99952 +++ b/drivers/serial/s3c6400.c
99953 @@ -0,0 +1,152 @@
99954 +/* linux/drivers/serial/s3c6400.c
99955 + *
99956 + * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
99957 + *
99958 + * Copyright 2008 Openmoko,  Inc.
99959 + * Copyright 2008 Simtec Electronics
99960 + *     Ben Dooks <ben@simtec.co.uk>
99961 + *     http://armlinux.simtec.co.uk/
99962 + *
99963 + * This program is free software; you can redistribute it and/or modify
99964 + * it under the terms of the GNU General Public License version 2 as
99965 + * published by the Free Software Foundation.
99966 +*/
99967 +
99968 +#include <linux/module.h>
99969 +#include <linux/ioport.h>
99970 +#include <linux/io.h>
99971 +#include <linux/platform_device.h>
99972 +#include <linux/init.h>
99973 +#include <linux/serial_core.h>
99974 +#include <linux/serial.h>
99975 +
99976 +#include <asm/irq.h>
99977 +#include <mach/hardware.h>
99978 +
99979 +#include <plat/regs-serial.h>
99980 +
99981 +#include "samsung.h"
99982 +
99983 +static int s3c6400_serial_setsource(struct uart_port *port,
99984 +                                   struct s3c24xx_uart_clksrc *clk)
99985 +{
99986 +       unsigned long ucon = rd_regl(port, S3C2410_UCON);
99987 +
99988 +       if (strcmp(clk->name, "uclk0") == 0) {
99989 +               ucon &= ~S3C6400_UCON_CLKMASK;
99990 +               ucon |= S3C6400_UCON_UCLK0;
99991 +       } else if (strcmp(clk->name, "uclk1") == 0)
99992 +               ucon |= S3C6400_UCON_UCLK1;
99993 +       else if (strcmp(clk->name, "pclk") == 0) {
99994 +               /* See notes about transitioning from UCLK to PCLK */
99995 +               ucon &= ~S3C6400_UCON_UCLK0;
99996 +       } else {
99997 +               printk(KERN_ERR "unknown clock source %s\n", clk->name);
99998 +               return -EINVAL;
99999 +       }
100000 +
100001 +       wr_regl(port, S3C2410_UCON, ucon);
100002 +       return 0;
100003 +}
100004 +
100005 +
100006 +static int s3c6400_serial_getsource(struct uart_port *port,
100007 +                                   struct s3c24xx_uart_clksrc *clk)
100008 +{
100009 +       u32 ucon = rd_regl(port, S3C2410_UCON);
100010 +
100011 +       clk->divisor = 1;
100012 +
100013 +       switch (ucon & S3C6400_UCON_CLKMASK) {
100014 +       case S3C6400_UCON_UCLK0:
100015 +               clk->name = "uclk0";
100016 +               break;
100017 +
100018 +       case S3C6400_UCON_UCLK1:
100019 +               clk->name = "uclk1";
100020 +               break;
100021 +
100022 +       case S3C6400_UCON_PCLK:
100023 +       case S3C6400_UCON_PCLK2:
100024 +               clk->name = "pclk";
100025 +               break;
100026 +       }
100027 +
100028 +       return 0;
100029 +}
100030 +
100031 +static int s3c6400_serial_resetport(struct uart_port *port,
100032 +                                   struct s3c2410_uartcfg *cfg)
100033 +{
100034 +       unsigned long ucon = rd_regl(port, S3C2410_UCON);
100035 +
100036 +       dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",
100037 +           port, port->mapbase, cfg);
100038 +
100039 +       /* ensure we don't change the clock settings... */
100040 +
100041 +       ucon &= S3C6400_UCON_CLKMASK;
100042 +
100043 +       wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
100044 +       wr_regl(port, S3C2410_ULCON, cfg->ulcon);
100045 +
100046 +       /* reset both fifos */
100047 +
100048 +       wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
100049 +       wr_regl(port, S3C2410_UFCON, cfg->ufcon);
100050 +
100051 +       return 0;
100052 +}
100053 +
100054 +static struct s3c24xx_uart_info s3c6400_uart_inf = {
100055 +       .name           = "Samsung S3C6400 UART",
100056 +       .type           = PORT_S3C6400,
100057 +       .fifosize       = 64,
100058 +       .has_divslot    = 1,
100059 +       .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
100060 +       .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
100061 +       .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
100062 +       .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
100063 +       .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
100064 +       .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
100065 +       .get_clksrc     = s3c6400_serial_getsource,
100066 +       .set_clksrc     = s3c6400_serial_setsource,
100067 +       .reset_port     = s3c6400_serial_resetport,
100068 +};
100069 +
100070 +/* device management */
100071 +
100072 +static int s3c6400_serial_probe(struct platform_device *dev)
100073 +{
100074 +       dbg("s3c6400_serial_probe: dev=%p\n", dev);
100075 +       return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
100076 +}
100077 +
100078 +static struct platform_driver s3c6400_serial_drv = {
100079 +       .probe          = s3c6400_serial_probe,
100080 +       .remove         = s3c24xx_serial_remove,
100081 +       .driver         = {
100082 +               .name   = "s3c6400-uart",
100083 +               .owner  = THIS_MODULE,
100084 +       },
100085 +};
100086 +
100087 +s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
100088 +
100089 +static int __init s3c6400_serial_init(void)
100090 +{
100091 +       return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
100092 +}
100093 +
100094 +static void __exit s3c6400_serial_exit(void)
100095 +{
100096 +       platform_driver_unregister(&s3c6400_serial_drv);
100097 +}
100098 +
100099 +module_init(s3c6400_serial_init);
100100 +module_exit(s3c6400_serial_exit);
100101 +
100102 +MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver");
100103 +MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
100104 +MODULE_LICENSE("GPL v2");
100105 +MODULE_ALIAS("platform:s3c6400-uart");
100106 --- a/drivers/serial/samsung.c
100107 +++ b/drivers/serial/samsung.c
100108 @@ -42,13 +42,18 @@
100109  #include <linux/serial.h>
100110  #include <linux/delay.h>
100111  #include <linux/clk.h>
100112 +#include <linux/cpufreq.h>
100113
100114  #include <asm/irq.h>
100115
100116  #include <mach/hardware.h>
100117 +#include <mach/map.h>
100118
100119  #include <plat/regs-serial.h>
100120 +#if defined(CONFIG_MACH_NEO1973) && !defined(CONFIG_CPU_S3C6410)
100121  #include <mach/regs-gpio.h>
100122 +#include <mach/regs-clock.h>
100123 +#endif
100124
100125  #include "samsung.h"
100126
100127 @@ -58,19 +63,6 @@
100128  #define S3C24XX_SERIAL_MAJOR   204
100129  #define S3C24XX_SERIAL_MINOR   64
100130
100131 -/* we can support 3 uarts, but not always use them */
100132 -
100133 -#ifdef CONFIG_CPU_S3C2400
100134 -#define NR_PORTS (2)
100135 -#else
100136 -#define NR_PORTS (3)
100137 -#endif
100138 -
100139 -/* port irq numbers */
100140 -
100141 -#define TX_IRQ(port) ((port)->irq + 1)
100142 -#define RX_IRQ(port) ((port)->irq)
100143 -
100144  /* macros to change one thing to another */
100145
100146  #define tx_enabled(port) ((port)->unused[0])
100147 @@ -136,8 +128,10 @@ static void s3c24xx_serial_rx_disable(st
100148
100149  static void s3c24xx_serial_stop_tx(struct uart_port *port)
100150  {
100151 +       struct s3c24xx_uart_port *ourport = to_ourport(port);
100152 +
100153         if (tx_enabled(port)) {
100154 -               disable_irq(TX_IRQ(port));
100155 +               disable_irq(ourport->tx_irq);
100156                 tx_enabled(port) = 0;
100157                 if (port->flags & UPF_CONS_FLOW)
100158                         s3c24xx_serial_rx_enable(port);
100159 @@ -146,11 +140,13 @@ static void s3c24xx_serial_stop_tx(struc
100160
100161  static void s3c24xx_serial_start_tx(struct uart_port *port)
100162  {
100163 +       struct s3c24xx_uart_port *ourport = to_ourport(port);
100164 +
100165         if (!tx_enabled(port)) {
100166                 if (port->flags & UPF_CONS_FLOW)
100167                         s3c24xx_serial_rx_disable(port);
100168
100169 -               enable_irq(TX_IRQ(port));
100170 +               enable_irq(ourport->tx_irq);
100171                 tx_enabled(port) = 1;
100172         }
100173  }
100174 @@ -158,9 +154,11 @@ static void s3c24xx_serial_start_tx(stru
100175
100176  static void s3c24xx_serial_stop_rx(struct uart_port *port)
100177  {
100178 +       struct s3c24xx_uart_port *ourport = to_ourport(port);
100179 +
100180         if (rx_enabled(port)) {
100181                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
100182 -               disable_irq(RX_IRQ(port));
100183 +               disable_irq(ourport->rx_irq);
100184                 rx_enabled(port) = 0;
100185         }
100186  }
100187 @@ -241,7 +239,7 @@ s3c24xx_serial_rx_chars(int irq, void *d
100188                 port->icount.rx++;
100189
100190                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
100191 -                       dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
100192 +                       printk(KERN_DEBUG "rxerr: port ch=0x%02x, rxs=0x%08x\n",
100193                             ch, uerstat);
100194
100195                         /* check for break */
100196 @@ -384,13 +382,13 @@ static void s3c24xx_serial_shutdown(stru
100197         struct s3c24xx_uart_port *ourport = to_ourport(port);
100198
100199         if (ourport->tx_claimed) {
100200 -               free_irq(TX_IRQ(port), ourport);
100201 +               free_irq(ourport->tx_irq, ourport);
100202                 tx_enabled(port) = 0;
100203                 ourport->tx_claimed = 0;
100204         }
100205
100206         if (ourport->rx_claimed) {
100207 -               free_irq(RX_IRQ(port), ourport);
100208 +               free_irq(ourport->rx_irq, ourport);
100209                 ourport->rx_claimed = 0;
100210                 rx_enabled(port) = 0;
100211         }
100212 @@ -407,12 +405,11 @@ static int s3c24xx_serial_startup(struct
100213
100214         rx_enabled(port) = 1;
100215
100216 -       ret = request_irq(RX_IRQ(port),
100217 -                         s3c24xx_serial_rx_chars, 0,
100218 +       ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
100219                           s3c24xx_serial_portname(port), ourport);
100220
100221         if (ret != 0) {
100222 -               printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
100223 +               printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
100224                 return ret;
100225         }
100226
100227 @@ -422,12 +419,11 @@ static int s3c24xx_serial_startup(struct
100228
100229         tx_enabled(port) = 1;
100230
100231 -       ret = request_irq(TX_IRQ(port),
100232 -                         s3c24xx_serial_tx_chars, 0,
100233 +       ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
100234                           s3c24xx_serial_portname(port), ourport);
100235
100236         if (ret) {
100237 -               printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
100238 +               printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
100239                 goto err;
100240         }
100241
100242 @@ -452,6 +448,8 @@ static void s3c24xx_serial_pm(struct uar
100243  {
100244         struct s3c24xx_uart_port *ourport = to_ourport(port);
100245
100246 +       ourport->pm_level = level;
100247 +
100248         switch (level) {
100249         case 3:
100250                 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
100251 @@ -514,6 +512,7 @@ s3c24xx_serial_setsource(struct uart_por
100252  struct baud_calc {
100253         struct s3c24xx_uart_clksrc      *clksrc;
100254         unsigned int                     calc;
100255 +       unsigned int                     divslot;
100256         unsigned int                     quot;
100257         struct clk                      *src;
100258  };
100259 @@ -523,6 +522,7 @@ static int s3c24xx_serial_calcbaud(struc
100260                                    struct s3c24xx_uart_clksrc *clksrc,
100261                                    unsigned int baud)
100262  {
100263 +       struct s3c24xx_uart_port *ourport = to_ourport(port);
100264         unsigned long rate;
100265
100266         calc->src = clk_get(port->dev, clksrc->name);
100267 @@ -533,8 +533,24 @@ static int s3c24xx_serial_calcbaud(struc
100268         rate /= clksrc->divisor;
100269
100270         calc->clksrc = clksrc;
100271 -       calc->quot = (rate + (8 * baud)) / (16 * baud);
100272 -       calc->calc = (rate / (calc->quot * 16));
100273 +
100274 +       if (ourport->info->has_divslot) {
100275 +               unsigned long div = rate / baud;
100276 +
100277 +               /* The UDIVSLOT register on the newer UARTs allows us to
100278 +                * get a divisor adjustment of 1/16th on the baud clock.
100279 +                *
100280 +                * We don't keep the UDIVSLOT value (the 16ths we calculated
100281 +                * by not multiplying the baud by 16) as it is easy enough
100282 +                * to recalculate.
100283 +                */
100284 +
100285 +               calc->quot = div / 16;
100286 +               calc->calc = rate / div;
100287 +       } else {
100288 +               calc->quot = (rate + (8 * baud)) / (16 * baud);
100289 +               calc->calc = (rate / (calc->quot * 16));
100290 +       }
100291
100292         calc->quot--;
100293         return 1;
100294 @@ -617,6 +633,30 @@ static unsigned int s3c24xx_serial_getcl
100295         return best->quot;
100296  }
100297
100298 +/* udivslot_table[]
100299 + *
100300 + * This table takes the fractional value of the baud divisor and gives
100301 + * the recommended setting for the UDIVSLOT register.
100302 + */
100303 +static u16 udivslot_table[16] = {
100304 +       [0] = 0x0000,
100305 +       [1] = 0x0080,
100306 +       [2] = 0x0808,
100307 +       [3] = 0x0888,
100308 +       [4] = 0x2222,
100309 +       [5] = 0x4924,
100310 +       [6] = 0x4A52,
100311 +       [7] = 0x54AA,
100312 +       [8] = 0x5555,
100313 +       [9] = 0xD555,
100314 +       [10] = 0xD5D5,
100315 +       [11] = 0xDDD5,
100316 +       [12] = 0xDDDD,
100317 +       [13] = 0xDFDD,
100318 +       [14] = 0xDFDF,
100319 +       [15] = 0xFFDF,
100320 +};
100321 +
100322  static void s3c24xx_serial_set_termios(struct uart_port *port,
100323                                        struct ktermios *termios,
100324                                        struct ktermios *old)
100325 @@ -629,6 +669,7 @@ static void s3c24xx_serial_set_termios(s
100326         unsigned int baud, quot;
100327         unsigned int ulcon;
100328         unsigned int umcon;
100329 +       unsigned int udivslot = 0;
100330
100331         /*
100332          * We don't support modem control lines.
100333 @@ -650,6 +691,7 @@ static void s3c24xx_serial_set_termios(s
100334         /* check to see if we need  to change clock source */
100335
100336         if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
100337 +               dbg("selecting clock %p\n", clk);
100338                 s3c24xx_serial_setsource(port, clksrc);
100339
100340                 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
100341 @@ -661,6 +703,14 @@ static void s3c24xx_serial_set_termios(s
100342
100343                 ourport->clksrc = clksrc;
100344                 ourport->baudclk = clk;
100345 +               ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
100346 +       }
100347 +
100348 +       if (ourport->info->has_divslot) {
100349 +               unsigned int div = ourport->baudclk_rate / baud;
100350 +
100351 +               udivslot = udivslot_table[div & 15];
100352 +               dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
100353         }
100354
100355         switch (termios->c_cflag & CSIZE) {
100356 @@ -702,12 +752,16 @@ static void s3c24xx_serial_set_termios(s
100357
100358         spin_lock_irqsave(&port->lock, flags);
100359
100360 -       dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
100361 +       dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
100362 +           ulcon, quot, udivslot);
100363
100364         wr_regl(port, S3C2410_ULCON, ulcon);
100365         wr_regl(port, S3C2410_UBRDIV, quot);
100366         wr_regl(port, S3C2410_UMCON, umcon);
100367
100368 +       if (ourport->info->has_divslot)
100369 +               wr_regl(port, S3C2443_DIVSLOT, udivslot);
100370 +
100371         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
100372             rd_regl(port, S3C2410_ULCON),
100373             rd_regl(port, S3C2410_UCON),
100374 @@ -752,6 +806,8 @@ static const char *s3c24xx_serial_type(s
100375                 return "S3C2440";
100376         case PORT_S3C2412:
100377                 return "S3C2412";
100378 +       case PORT_S3C6400:
100379 +               return "S3C6400/10";
100380         default:
100381                 return NULL;
100382         }
100383 @@ -827,14 +883,14 @@ static struct uart_ops s3c24xx_serial_op
100384  static struct uart_driver s3c24xx_uart_drv = {
100385         .owner          = THIS_MODULE,
100386         .dev_name       = "s3c2410_serial",
100387 -       .nr             = 3,
100388 +       .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
100389         .cons           = S3C24XX_SERIAL_CONSOLE,
100390         .driver_name    = S3C24XX_SERIAL_NAME,
100391         .major          = S3C24XX_SERIAL_MAJOR,
100392         .minor          = S3C24XX_SERIAL_MINOR,
100393  };
100394
100395 -static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
100396 +static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
100397         [0] = {
100398                 .port = {
100399                         .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
100400 @@ -859,7 +915,7 @@ static struct s3c24xx_uart_port s3c24xx_
100401                         .line           = 1,
100402                 }
100403         },
100404 -#if NR_PORTS > 2
100405 +#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
100406
100407         [2] = {
100408                 .port = {
100409 @@ -872,10 +928,88 @@ static struct s3c24xx_uart_port s3c24xx_
100410                         .flags          = UPF_BOOT_AUTOCONF,
100411                         .line           = 2,
100412                 }
100413 +       },
100414 +#endif
100415 +#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
100416 +       [3] = {
100417 +               .port = {
100418 +                       .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
100419 +                       .iotype         = UPIO_MEM,
100420 +                       .irq            = IRQ_S3CUART_RX3,
100421 +                       .uartclk        = 0,
100422 +                       .fifosize       = 16,
100423 +                       .ops            = &s3c24xx_serial_ops,
100424 +                       .flags          = UPF_BOOT_AUTOCONF,
100425 +                       .line           = 3,
100426 +               }
100427         }
100428  #endif
100429  };
100430
100431 +#ifdef CONFIG_MACH_NEO1973_GTA02
100432 +static void s3c24xx_serial_force_debug_port_up(void)
100433 +{
100434 +       struct s3c24xx_uart_port *ourport = &s3c24xx_serial_ports[
100435 +                                                        CONFIG_DEBUG_S3C_UART];
100436 +       struct s3c24xx_uart_clksrc *clksrc = NULL;
100437 +       struct clk *clk = NULL;
100438 +       unsigned long tmp;
100439 +
100440 +       s3c24xx_serial_getclk(&ourport->port, &clksrc, &clk, 115200);
100441 +
100442 +       tmp = __raw_readl(S3C2410_CLKCON);
100443 +
100444 +       /* re-start uart clocks */
100445 +       tmp |= S3C2410_CLKCON_UART0;
100446 +       tmp |= S3C2410_CLKCON_UART1;
100447 +       tmp |= S3C2410_CLKCON_UART2;
100448 +
100449 +       __raw_writel(tmp, S3C2410_CLKCON);
100450 +       udelay(10);
100451 +
100452 +       s3c24xx_serial_setsource(&ourport->port, clksrc);
100453 +
100454 +       if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
100455 +               clk_disable(ourport->baudclk);
100456 +               ourport->baudclk  = NULL;
100457 +       }
100458 +
100459 +       clk_enable(clk);
100460 +
100461 +       ourport->clksrc = clksrc;
100462 +       ourport->baudclk = clk;
100463 +}
100464 +
100465 +static void s3c2410_printascii(const char *sz)
100466 +{
100467 +       struct s3c24xx_uart_port *ourport = &s3c24xx_serial_ports[
100468 +                                                        CONFIG_DEBUG_S3C_UART];
100469 +       struct uart_port *port = &ourport->port;
100470 +
100471 +       /* 8 N 1 */
100472 +       wr_regl(port, S3C2410_ULCON, (rd_regl(port, S3C2410_ULCON)) | 3);
100473 +       /* polling mode */
100474 +       wr_regl(port, S3C2410_UCON, (rd_regl(port, S3C2410_UCON) & ~0xc0f) | 5);
100475 +       /* disable FIFO */
100476 +       wr_regl(port, S3C2410_UFCON, (rd_regl(port, S3C2410_UFCON) & ~0x01));
100477 +       /* fix baud rate */
100478 +       wr_regl(port, S3C2410_UBRDIV, 26);
100479 +
100480 +       while (*sz) {
100481 +               int timeout = 10000000;
100482 +
100483 +               /* spin on it being busy */
100484 +               while ((!(rd_regl(port, S3C2410_UTRSTAT) & 2)) && timeout--)
100485 +                       ;
100486 +
100487 +               /* transmit register */
100488 +               wr_regl(port, S3C2410_UTXH, *sz);
100489 +
100490 +               sz++;
100491 +       }
100492 +}
100493 +#endif
100494 +
100495  /* s3c24xx_serial_resetport
100496   *
100497   * wrapper to call the specific reset for this port (reset the fifos
100498 @@ -890,6 +1024,93 @@ static inline int s3c24xx_serial_resetpo
100499         return (info->reset_port)(port, cfg);
100500  }
100501
100502 +
100503 +#ifdef CONFIG_CPU_FREQ
100504 +
100505 +static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
100506 +                                            unsigned long val, void *data)
100507 +{
100508 +       struct s3c24xx_uart_port *port;
100509 +       struct uart_port *uport;
100510 +
100511 +       port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
100512 +       uport = &port->port;
100513 +
100514 +       /* check to see if port is enabled */
100515 +
100516 +       if (port->pm_level != 0)
100517 +               return 0;
100518 +
100519 +       /* try and work out if the baudrate is changing, we can detect
100520 +        * a change in rate, but we do not have support for detecting
100521 +        * a disturbance in the clock-rate over the change.
100522 +        */
100523 +
100524 +       if (IS_ERR(port->clk))
100525 +               goto exit;
100526 +
100527 +       if (port->baudclk_rate == clk_get_rate(port->clk))
100528 +               goto exit;
100529 +
100530 +       if (val == CPUFREQ_PRECHANGE) {
100531 +               /* we should really shut the port down whilst the
100532 +                * frequency change is in progress. */
100533 +
100534 +       } else if (val == CPUFREQ_POSTCHANGE) {
100535 +               struct ktermios *termios;
100536 +               struct tty_struct *tty;
100537 +
100538 +               if (uport->info == NULL) {
100539 +                       printk(KERN_WARNING "%s: info NULL\n", __func__);
100540 +                       goto exit;
100541 +               }
100542 +
100543 +               tty = uport->info->port.tty;
100544 +
100545 +               if (tty == NULL) {
100546 +                       printk(KERN_WARNING "%s: tty is NULL\n", __func__);
100547 +                       goto exit;
100548 +               }
100549 +
100550 +               termios = tty->termios;
100551 +
100552 +               if (termios == NULL) {
100553 +                       printk(KERN_WARNING "%s: no termios?\n", __func__);
100554 +                       goto exit;
100555 +               }
100556 +
100557 +               s3c24xx_serial_set_termios(uport, termios, NULL);
100558 +       }
100559 +
100560 + exit:
100561 +       return 0;
100562 +}
100563 +
100564 +static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
100565 +{
100566 +       port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
100567 +
100568 +       return cpufreq_register_notifier(&port->freq_transition,
100569 +                                        CPUFREQ_TRANSITION_NOTIFIER);
100570 +}
100571 +
100572 +static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
100573 +{
100574 +       cpufreq_unregister_notifier(&port->freq_transition,
100575 +                                   CPUFREQ_TRANSITION_NOTIFIER);
100576 +}
100577 +
100578 +#else
100579 +static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
100580 +{
100581 +       return 0;
100582 +}
100583 +
100584 +static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
100585 +{
100586 +}
100587 +#endif
100588 +
100589  /* s3c24xx_serial_init_port
100590   *
100591   * initialise a single serial port from the platform device given
100592 @@ -914,8 +1135,11 @@ static int s3c24xx_serial_init_port(stru
100593         if (port->mapbase != 0)
100594                 return 0;
100595
100596 -       if (cfg->hwport > 3)
100597 -               return -EINVAL;
100598 +       if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
100599 +               printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
100600 +                      cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
100601 +               return -ERANGE;
100602 +       }
100603
100604         /* setup info for port */
100605         port->dev       = &platdev->dev;
100606 @@ -943,18 +1167,26 @@ static int s3c24xx_serial_init_port(stru
100607
100608         dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
100609
100610 -       port->mapbase   = res->start;
100611 -       port->membase   = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
100612 +       port->mapbase = res->start;
100613 +       port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000);
100614         ret = platform_get_irq(platdev, 0);
100615         if (ret < 0)
100616                 port->irq = 0;
100617 -       else
100618 +       else {
100619                 port->irq = ret;
100620 +               ourport->rx_irq = ret;
100621 +               ourport->tx_irq = ret + 1;
100622 +       }
100623 +
100624 +       ret = platform_get_irq(platdev, 1);
100625 +       if (ret > 0)
100626 +               ourport->tx_irq = ret;
100627
100628         ourport->clk    = clk_get(&platdev->dev, "uart");
100629
100630 -       dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
100631 -           port->mapbase, port->membase, port->irq, port->uartclk);
100632 +       dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
100633 +           port->mapbase, port->membase, port->irq,
100634 +           ourport->rx_irq, ourport->tx_irq, port->uartclk);
100635
100636         /* reset the fifos (and setup the uart) */
100637         s3c24xx_serial_resetport(port, cfg);
100638 @@ -987,6 +1219,7 @@ int s3c24xx_serial_probe(struct platform
100639
100640         ourport = &s3c24xx_serial_ports[probe_index];
100641         probe_index++;
100642 +       init_resume_dependency_list(&ourport->resume_dependency);
100643
100644         dbg("%s: initialising port %p...\n", __func__, ourport);
100645
100646 @@ -1002,6 +1235,10 @@ int s3c24xx_serial_probe(struct platform
100647         if (ret < 0)
100648                 printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
100649
100650 +       ret = s3c24xx_serial_cpufreq_register(ourport);
100651 +       if (ret < 0)
100652 +               dev_err(&dev->dev, "failed to add cpufreq notifier\n");
100653 +
100654         return 0;
100655
100656   probe_err:
100657 @@ -1015,6 +1252,7 @@ int s3c24xx_serial_remove(struct platfor
100658         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
100659
100660         if (port) {
100661 +               s3c24xx_serial_cpufreq_deregister(to_ourport(port));
100662                 device_remove_file(&dev->dev, &dev_attr_clock_source);
100663                 uart_remove_one_port(&s3c24xx_uart_drv, port);
100664         }
100665 @@ -1038,6 +1276,16 @@ static int s3c24xx_serial_suspend(struct
100666         return 0;
100667  }
100668
100669 +void s3c24xx_serial_register_resume_dependency(struct resume_dependency *
100670 +                                             resume_dependency, int uart_index)
100671 +{
100672 +       struct s3c24xx_uart_port *ourport = &s3c24xx_serial_ports[uart_index];
100673 +
100674 +       register_resume_dependency(&ourport->resume_dependency,
100675 +                                                            resume_dependency);
100676 +}
100677 +EXPORT_SYMBOL(s3c24xx_serial_register_resume_dependency);
100678 +
100679  static int s3c24xx_serial_resume(struct platform_device *dev)
100680  {
100681         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
100682 @@ -1049,6 +1297,9 @@ static int s3c24xx_serial_resume(struct
100683                 clk_disable(ourport->clk);
100684
100685                 uart_resume_port(&s3c24xx_uart_drv, port);
100686 +
100687 +               callback_all_resume_dependencies(&ourport->resume_dependency);
100688 +
100689         }
100690
100691         return 0;
100692 @@ -1059,6 +1310,12 @@ int s3c24xx_serial_init(struct platform_
100693                         struct s3c24xx_uart_info *info)
100694  {
100695         dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
100696 +#ifdef CONFIG_MACH_NEO1973_GTA02
100697 +       /* set up the emergency debug UART functions */
100698 +
100699 +       printk_emergency_debug_spew_init = s3c24xx_serial_force_debug_port_up;
100700 +       printk_emergency_debug_spew_send_string = s3c2410_printascii;
100701 +#endif
100702
100703  #ifdef CONFIG_PM
100704         drv->suspend = s3c24xx_serial_suspend;
100705 @@ -1098,6 +1355,13 @@ module_exit(s3c24xx_serial_modexit);
100706  #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
100707
100708  static struct uart_port *cons_uart;
100709 +static int cons_silenced;
100710 +
100711 +void s3c24xx_serial_console_set_silence(int silenced)
100712 +{
100713 +       cons_silenced = silenced;
100714 +}
100715 +EXPORT_SYMBOL(s3c24xx_serial_console_set_silence);
100716
100717  static int
100718  s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
100719 @@ -1122,9 +1386,21 @@ static void
100720  s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
100721  {
100722         unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
100723 +       unsigned int umcon = rd_regl(cons_uart, S3C2410_UMCON);
100724 +
100725 +       if (cons_silenced)
100726 +               return;
100727 +
100728 +       /* If auto HW flow control enabled, temporarily turn it off */
100729 +       if (umcon & S3C2410_UMCOM_AFC)
100730 +               wr_regl(port, S3C2410_UMCON, (umcon & !S3C2410_UMCOM_AFC));
100731 +
100732         while (!s3c24xx_serial_console_txrdy(port, ufcon))
100733                 barrier();
100734         wr_regb(cons_uart, S3C2410_UTXH, ch);
100735 +
100736 +       if (umcon & S3C2410_UMCOM_AFC)
100737 +               wr_regl(port, S3C2410_UMCON, umcon);
100738  }
100739
100740  static void
100741 @@ -1219,7 +1495,7 @@ static int s3c24xx_serial_init_ports(str
100742
100743         platdev_ptr = s3c24xx_uart_devs;
100744
100745 -       for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
100746 +       for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
100747                 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
100748         }
100749
100750 @@ -1240,7 +1516,7 @@ s3c24xx_serial_console_setup(struct cons
100751
100752         /* is this a valid port */
100753
100754 -       if (co->index == -1 || co->index >= NR_PORTS)
100755 +       if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
100756                 co->index = 0;
100757
100758         port = &s3c24xx_serial_ports[co->index].port;
100759 --- a/drivers/serial/samsung.h
100760 +++ b/drivers/serial/samsung.h
100761 @@ -10,6 +10,8 @@
100762   * published by the Free Software Foundation.
100763  */
100764
100765 +#include <linux/resume-dependency.h>
100766 +
100767  struct s3c24xx_uart_info {
100768         char                    *name;
100769         unsigned int            type;
100770 @@ -21,6 +23,10 @@ struct s3c24xx_uart_info {
100771         unsigned long           tx_fifoshift;
100772         unsigned long           tx_fifofull;
100773
100774 +       /* uart port features */
100775 +
100776 +       unsigned int            has_divslot:1;
100777 +
100778         /* clock source control */
100779
100780         int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
100781 @@ -33,12 +39,23 @@ struct s3c24xx_uart_info {
100782  struct s3c24xx_uart_port {
100783         unsigned char                   rx_claimed;
100784         unsigned char                   tx_claimed;
100785 +       unsigned int                    pm_level;
100786 +       unsigned long                   baudclk_rate;
100787 +
100788 +       unsigned int                    rx_irq;
100789 +       unsigned int                    tx_irq;
100790
100791         struct s3c24xx_uart_info        *info;
100792         struct s3c24xx_uart_clksrc      *clksrc;
100793         struct clk                      *clk;
100794         struct clk                      *baudclk;
100795         struct uart_port                port;
100796 +
100797 +#ifdef CONFIG_CPU_FREQ
100798 +       struct notifier_block           freq_transition;
100799 +#endif
100800 +
100801 +       struct resume_dependency        resume_dependency;
100802  };
100803
100804  /* conversion functions */
100805 --- a/drivers/spi/spi_s3c24xx.c
100806 +++ b/drivers/spi/spi_s3c24xx.c
100807 @@ -28,7 +28,7 @@
100808  #include <mach/hardware.h>
100809
100810  #include <mach/regs-gpio.h>
100811 -#include <asm/plat-s3c24xx/regs-spi.h>
100812 +#include <plat/regs-spi.h>
100813  #include <mach/spi.h>
100814
100815  struct s3c24xx_spi {
100816 --- a/drivers/spi/spi_s3c24xx_gpio.c
100817 +++ b/drivers/spi/spi_s3c24xx_gpio.c
100818 @@ -91,7 +91,7 @@ static void s3c2410_spigpio_chipselect(s
100819         struct s3c2410_spigpio *sg = spidev_to_sg(dev);
100820
100821         if (sg->info && sg->info->chip_select)
100822 -               (sg->info->chip_select)(sg->info, value);
100823 +               (sg->info->chip_select)(sg->info, dev->chip_select, value);
100824  }
100825
100826  static int s3c2410_spigpio_probe(struct platform_device *dev)
100827 @@ -100,6 +100,7 @@ static int s3c2410_spigpio_probe(struct
100828         struct spi_master       *master;
100829         struct s3c2410_spigpio  *sp;
100830         int ret;
100831 +       int i;
100832
100833         master = spi_alloc_master(&dev->dev, sizeof(struct s3c2410_spigpio));
100834         if (master == NULL) {
100835 @@ -112,9 +113,11 @@ static int s3c2410_spigpio_probe(struct
100836
100837         platform_set_drvdata(dev, sp);
100838
100839 -       /* copy in the plkatform data */
100840 +       /* copy in the platform data */
100841         info = sp->info = dev->dev.platform_data;
100842
100843 +       master->num_chipselect = info->num_chipselect;
100844 +
100845         /* setup spi bitbang adaptor */
100846         sp->bitbang.master = spi_master_get(master);
100847         sp->bitbang.master->bus_num = info->bus_num;
100848 @@ -143,6 +146,22 @@ static int s3c2410_spigpio_probe(struct
100849         if (ret)
100850                 goto err_no_bitbang;
100851
100852 +       /* register the chips to go with the board */
100853 +
100854 +       for (i = 0; i < sp->info->board_size; i++) {
100855 +               struct spi_device *spidev;
100856 +
100857 +               dev_info(&dev->dev, "registering %p: %s\n",
100858 +                        &sp->info->board_info[i],
100859 +                        sp->info->board_info[i].modalias);
100860 +
100861 +               sp->info->board_info[i].controller_data = sp;
100862 +               spidev = spi_new_device(master, sp->info->board_info + i);
100863 +               if (spidev)
100864 +                       spidev->max_speed_hz =
100865 +                                         sp->info->board_info[i].max_speed_hz;
100866 +       }
100867 +
100868         return 0;
100869
100870   err_no_bitbang:
100871 --- a/drivers/usb/gadget/composite.c
100872 +++ b/drivers/usb/gadget/composite.c
100873 @@ -1045,7 +1045,11 @@ composite_resume(struct usb_gadget *gadg
100874  /*-------------------------------------------------------------------------*/
100875
100876  static struct usb_gadget_driver composite_driver = {
100877 +#ifdef CONFIG_USB_GADGET_DUALSPEED
100878         .speed          = USB_SPEED_HIGH,
100879 +#else
100880 +       .speed          = USB_SPEED_FULL,
100881 +#endif
100882
100883         .bind           = composite_bind,
100884         .unbind         = __exit_p(composite_unbind),
100885 --- a/drivers/usb/gadget/ether.c
100886 +++ b/drivers/usb/gadget/ether.c
100887 @@ -122,11 +122,16 @@ static inline bool has_rndis(void)
100888   * Instead:  allocate your own, using normal USB-IF procedures.
100889   */
100890
100891 +#if 0
100892  /* Thanks to NetChip Technologies for donating this product ID.
100893   * It's for devices with only CDC Ethernet configurations.
100894   */
100895  #define CDC_VENDOR_NUM         0x0525  /* NetChip */
100896  #define CDC_PRODUCT_NUM                0xa4a1  /* Linux-USB Ethernet Gadget */
100897 +#else
100898 +#define CDC_VENDOR_NUM 0x1457          /* First International Computer */
100899 +#define CDC_PRODUCT_NUM        0x5117          /* Linux-USB Ethernet Gadget */
100900 +#endif
100901
100902  /* For hardware that can't talk CDC, we use the same vendor ID that
100903   * ARM Linux has used for ethernet-over-usb, both with sa1100 and
100904 @@ -147,8 +152,8 @@ static inline bool has_rndis(void)
100905   * used with CDC Ethernet, Linux 2.4 hosts will need updates to choose
100906   * the non-RNDIS configuration.
100907   */
100908 -#define RNDIS_VENDOR_NUM       0x0525  /* NetChip */
100909 -#define RNDIS_PRODUCT_NUM      0xa4a2  /* Ethernet/RNDIS Gadget */
100910 +#define RNDIS_VENDOR_NUM       0x1457  /* NetChip */
100911 +#define RNDIS_PRODUCT_NUM      0x5122  /* Ethernet/RNDIS Gadget */
100912
100913  /*-------------------------------------------------------------------------*/
100914
100915 --- a/drivers/usb/gadget/s3c2410_udc.c
100916 +++ b/drivers/usb/gadget/s3c2410_udc.c
100917 @@ -53,8 +53,8 @@
100918  #include <mach/hardware.h>
100919  #include <mach/regs-gpio.h>
100920
100921 -#include <asm/plat-s3c24xx/regs-udc.h>
100922 -#include <asm/plat-s3c24xx/udc.h>
100923 +#include <plat/regs-udc.h>
100924 +#include <plat/udc.h>
100925
100926
100927  #include "s3c2410_udc.h"
100928 @@ -134,6 +134,8 @@ static int dprintk(int level, const char
100929         return 0;
100930  }
100931  #endif
100932 +
100933 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
100934  static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
100935  {
100936         u32 addr_reg,pwr_reg,ep_int_reg,usb_int_reg;
100937 @@ -197,6 +199,7 @@ static const struct file_operations s3c2
100938         .release        = single_release,
100939         .owner          = THIS_MODULE,
100940  };
100941 +#endif
100942
100943  /* io macros */
100944
100945 @@ -843,6 +846,7 @@ static void s3c2410_udc_handle_ep(struct
100946         u32                     ep_csr1;
100947         u32                     idx;
100948
100949 +handle_ep_again:
100950         if (likely (!list_empty(&ep->queue)))
100951                 req = list_entry(ep->queue.next,
100952                                 struct s3c2410_request, queue);
100953 @@ -882,6 +886,8 @@ static void s3c2410_udc_handle_ep(struct
100954
100955                 if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req) {
100956                         s3c2410_udc_read_fifo(ep,req);
100957 +                       if (s3c2410_udc_fifo_count_out())
100958 +                               goto handle_ep_again;
100959                 }
100960         }
100961  }
100962 @@ -1890,6 +1896,7 @@ static int s3c2410_udc_probe(struct plat
100963                 udc->vbus = 1;
100964         }
100965
100966 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
100967         if (s3c2410_udc_debugfs_root) {
100968                 udc->regs_info = debugfs_create_file("registers", S_IRUGO,
100969                                 s3c2410_udc_debugfs_root,
100970 @@ -1897,6 +1904,7 @@ static int s3c2410_udc_probe(struct plat
100971                 if (!udc->regs_info)
100972                         dev_warn(dev, "debugfs file creation failed\n");
100973         }
100974 +#endif
100975
100976         dev_dbg(dev, "probe ok\n");
100977
100978 @@ -2003,12 +2011,14 @@ static int __init udc_init(void)
100979
100980         dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
100981
100982 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
100983         s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
100984         if (IS_ERR(s3c2410_udc_debugfs_root)) {
100985                 printk(KERN_ERR "%s: debugfs dir creation failed %ld\n",
100986                         gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
100987                 s3c2410_udc_debugfs_root = NULL;
100988         }
100989 +#endif
100990
100991         retval = platform_driver_register(&udc_driver_2410);
100992         if (retval)
100993 --- a/drivers/usb/host/ohci-s3c2410.c
100994 +++ b/drivers/usb/host/ohci-s3c2410.c
100995 @@ -24,6 +24,7 @@
100996
100997  #include <mach/hardware.h>
100998  #include <mach/usb-control.h>
100999 +#include <mach/regs-gpio.h>
101000
101001  #define valid_port(idx) ((idx) == 1 || (idx) == 2)
101002
101003 @@ -308,6 +309,42 @@ static void s3c2410_hcd_oc(struct s3c241
101004         local_irq_restore(flags);
101005  }
101006
101007 +/* switching of USB pads */
101008 +static ssize_t show_usb_mode(struct device *dev, struct device_attribute *attr,
101009 +                            char *buf)
101010 +{
101011 +       if (__raw_readl(S3C24XX_MISCCR) & S3C2410_MISCCR_USBHOST)
101012 +               return sprintf(buf, "host\n");
101013 +
101014 +       return sprintf(buf, "device\n");
101015 +}
101016 +
101017 +static ssize_t set_usb_mode(struct device *dev, struct device_attribute *attr,
101018 +                           const char *buf, size_t count)
101019 +{
101020 +       if (!strncmp(buf, "host", 4)) {
101021 +               printk("s3c2410: changing usb to host\n");
101022 +               s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST,
101023 +                                     S3C2410_MISCCR_USBHOST);
101024 +               /* FIXME:
101025 +                * - call machine-specific disable-pullup function i
101026 +                * - enable +Vbus (if hardware supports it)
101027 +                */
101028 +               s3c2410_gpio_setpin(S3C2410_GPB9, 0);
101029 +       } else if (!strncmp(buf, "device", 6)) {
101030 +               printk("s3c2410: changing usb to device\n");
101031 +               s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST, 0);
101032 +               s3c2410_gpio_setpin(S3C2410_GPB9, 1);
101033 +       } else {
101034 +               printk("s3c2410: unknown mode\n");
101035 +               return -EINVAL;
101036 +       }
101037 +
101038 +       return count;
101039 +}
101040 +
101041 +static DEVICE_ATTR(usb_mode, S_IRUGO | S_IWUSR, show_usb_mode, set_usb_mode);
101042 +
101043  /* may be called without controller electrically present */
101044  /* may be called with controller, bus, and devices active */
101045
101046 @@ -325,6 +362,7 @@ static void s3c2410_hcd_oc(struct s3c241
101047  static void
101048  usb_hcd_s3c2410_remove (struct usb_hcd *hcd, struct platform_device *dev)
101049  {
101050 +       device_remove_file(&dev->dev, &dev_attr_usb_mode);
101051         usb_remove_hcd(hcd);
101052         s3c2410_stop_hc(dev);
101053         iounmap(hcd->regs);
101054 @@ -392,8 +430,15 @@ static int usb_hcd_s3c2410_probe (const
101055         if (retval != 0)
101056                 goto err_ioremap;
101057
101058 +       retval = device_create_file(&dev->dev, &dev_attr_usb_mode);
101059 +       if (retval != 0)
101060 +               goto err_hcd;
101061 +
101062         return 0;
101063
101064 + err_hcd:
101065 +       usb_remove_hcd(hcd);
101066 +
101067   err_ioremap:
101068         s3c2410_stop_hc(dev);
101069         iounmap(hcd->regs);
101070 --- /dev/null
101071 +++ b/drivers/video/backlight/gta01_bl.c
101072 @@ -0,0 +1,269 @@
101073 +/*
101074 + *  Backlight Driver for FIC GTA01 (Neo1973) GSM Phone
101075 + *
101076 + * Copyright (C) 2006-2007 by Openmoko, Inc.
101077 + * Author: Harald Welte <laforge@openmoko.org>
101078 + * All rights reserved.
101079 + *
101080 + *  based on corgi_cl.c, Copyright (c) 2004-2006 Richard Purdie
101081 + *
101082 + * This program is free software; you can redistribute it and/or
101083 + * modify it under the terms of the GNU General Public License as
101084 + * published by the Free Software Foundation, version 2.
101085 + *
101086 + * This program is distributed in the hope that it will be useful,
101087 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
101088 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
101089 + * GNU General Public License for more details.
101090 + *
101091 + * You should have received a copy of the GNU General Public License
101092 + * along with this program; if not, write to the Free Software
101093 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
101094 + * MA 02111-1307 USA
101095 + *
101096 + * Javi Roman <javiroman@kernel-labs.org>:
101097 + *     implement PWM, instead of simple on/off switching
101098 + *
101099 + */
101100 +
101101 +#include <linux/module.h>
101102 +#include <linux/kernel.h>
101103 +#include <linux/init.h>
101104 +#include <linux/platform_device.h>
101105 +#include <linux/mutex.h>
101106 +#include <linux/fb.h>
101107 +#include <linux/backlight.h>
101108 +#include <linux/clk.h>
101109 +
101110 +#include <mach/hardware.h>
101111 +#include <mach/gta01.h>
101112 +#include <mach/pwm.h>
101113 +
101114 +#include <plat/regs-timer.h>
101115 +#include <asm/plat-s3c24xx/neo1973.h>
101116 +
101117 +static struct backlight_properties gta01bl_prop;
101118 +static struct backlight_device *gta01_backlight_device;
101119 +static struct gta01bl_machinfo *bl_machinfo;
101120 +
101121 +static unsigned long gta01bl_flags;
101122 +
101123 +struct gta01bl_data {
101124 +       int intensity;
101125 +       struct mutex mutex;
101126 +       struct clk *clk;
101127 +       struct s3c2410_pwm pwm;
101128 +};
101129 +
101130 +static struct gta01bl_data gta01bl;
101131 +
101132 +static int gta01bl_defer_resume_backlight;
101133 +
101134 +#define GTA01BL_SUSPENDED     0x01
101135 +#define GTA01BL_BATTLOW       0x02
101136 +
101137 +/* On the GTA01 / Neo1973, we use a 50 or 66MHz PCLK, which gives
101138 + * us a 6.25..8.25MHz DIV8 clock, which is further divided by a
101139 + * prescaler of 4, resulting in a 1.56..2.06MHz tick.  This results in a
101140 + * minimum frequency of 24..31Hz.  At 400Hz, we need to set the count
101141 + * to something like 3906..5156, providing us a way sufficient resolution
101142 + * for display brightness adjustment. */
101143 +#define GTA01BL_COUNTER 5156
101144 +
101145 +static int gta01bl_send_intensity(struct backlight_device *bd)
101146 +{
101147 +       int intensity = bd->props.brightness;
101148 +
101149 +       if (bd->props.power != FB_BLANK_UNBLANK)
101150 +               intensity = 0;
101151 +       if (bd->props.fb_blank != FB_BLANK_UNBLANK)
101152 +               intensity = 0;
101153 +       if (gta01bl_flags & GTA01BL_SUSPENDED)
101154 +               intensity = 0;
101155 +       if (gta01bl_flags & GTA01BL_BATTLOW)
101156 +               intensity &= bl_machinfo->limit_mask;
101157 +
101158 +       mutex_lock(&gta01bl.mutex);
101159 +#ifdef GTA01_BACKLIGHT_ONOFF_ONLY
101160 +       if (intensity)
101161 +               neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 1);
101162 +       else
101163 +               neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 0);
101164 +#else
101165 +       if (intensity == bd->props.max_brightness) {
101166 +               neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 1);
101167 +               s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
101168 +       } else  {
101169 +               s3c2410_pwm_duty_cycle(intensity & 0xffff, &gta01bl.pwm);
101170 +               s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPB0_TOUT0);
101171 +       }
101172 +#endif
101173 +       mutex_unlock(&gta01bl.mutex);
101174 +
101175 +       gta01bl.intensity = intensity;
101176 +       return 0;
101177 +}
101178 +
101179 +static int gta01bl_init_hw(void)
101180 +{
101181 +       int rc;
101182 +
101183 +       rc = s3c2410_pwm_init(&gta01bl.pwm);
101184 +       if (rc)
101185 +               return rc;
101186 +
101187 +       gta01bl.pwm.timerid = PWM0;
101188 +       gta01bl.pwm.prescaler = (4 - 1);
101189 +       gta01bl.pwm.divider = S3C2410_TCFG1_MUX0_DIV8;
101190 +       gta01bl.pwm.counter = GTA01BL_COUNTER;
101191 +       gta01bl.pwm.comparer = gta01bl.pwm.counter;
101192 +
101193 +       rc = s3c2410_pwm_enable(&gta01bl.pwm);
101194 +       if (rc)
101195 +               return rc;
101196 +
101197 +       s3c2410_pwm_start(&gta01bl.pwm);
101198 +
101199 +       gta01bl_prop.max_brightness = gta01bl.pwm.counter;
101200 +
101201 +       return 0;
101202 +}
101203 +
101204 +#ifdef CONFIG_PM
101205 +static int gta01bl_suspend(struct platform_device *dev, pm_message_t state)
101206 +{
101207 +       gta01bl_flags |= GTA01BL_SUSPENDED;
101208 +       gta01bl_send_intensity(gta01_backlight_device);
101209 +       neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 0);
101210 +       s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
101211 +       return 0;
101212 +}
101213 +
101214 +void gta01bl_deferred_resume(void)
101215 +{
101216 +       mutex_lock(&gta01bl.mutex);
101217 +       gta01bl_init_hw();
101218 +       mutex_unlock(&gta01bl.mutex);
101219 +
101220 +       gta01bl_flags &= ~GTA01BL_SUSPENDED;
101221 +       gta01bl_send_intensity(gta01_backlight_device);
101222 +}
101223 +EXPORT_SYMBOL_GPL(gta01bl_deferred_resume);
101224 +
101225 +static int gta01bl_resume(struct platform_device *dev)
101226 +{
101227 +       if (!gta01bl_defer_resume_backlight)
101228 +               gta01bl_deferred_resume();
101229 +       return 0;
101230 +}
101231 +#else
101232 +#define gta01bl_suspend        NULL
101233 +#define gta01bl_resume NULL
101234 +#endif
101235 +
101236 +static int gta01bl_get_intensity(struct backlight_device *bd)
101237 +{
101238 +       return gta01bl.intensity;
101239 +}
101240 +
101241 +static int gta01bl_set_intensity(struct backlight_device *bd)
101242 +{
101243 +       gta01bl_send_intensity(gta01_backlight_device);
101244 +       return 0;
101245 +}
101246 +
101247 +/*
101248 + * Called when the battery is low to limit the backlight intensity.
101249 + * If limit==0 clear any limit, otherwise limit the intensity
101250 + */
101251 +void gta01bl_limit_intensity(int limit)
101252 +{
101253 +       if (limit)
101254 +               gta01bl_flags |= GTA01BL_BATTLOW;
101255 +       else
101256 +               gta01bl_flags &= ~GTA01BL_BATTLOW;
101257 +       gta01bl_send_intensity(gta01_backlight_device);
101258 +}
101259 +EXPORT_SYMBOL_GPL(gta01bl_limit_intensity);
101260 +
101261 +
101262 +static struct backlight_ops gta01bl_ops = {
101263 +       .get_brightness = gta01bl_get_intensity,
101264 +       .update_status  = gta01bl_set_intensity,
101265 +};
101266 +
101267 +static int __init gta01bl_probe(struct platform_device *pdev)
101268 +{
101269 +       struct gta01bl_machinfo *machinfo = pdev->dev.platform_data;
101270 +       int rc;
101271 +
101272 +#ifdef GTA01_BACKLIGHT_ONOFF_ONLY
101273 +       s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
101274 +       gta01bl_prop.max_brightness = 1;
101275 +#else
101276 +       rc = gta01bl_init_hw();
101277 +       if (rc < 0)
101278 +               return rc;
101279 +#endif
101280 +       mutex_init(&gta01bl.mutex);
101281 +
101282 +       if (!machinfo->limit_mask)
101283 +               machinfo->limit_mask = -1;
101284 +
101285 +       gta01bl_defer_resume_backlight = machinfo->defer_resume_backlight;
101286 +
101287 +       gta01_backlight_device = backlight_device_register("gta01-bl",
101288 +                                                          &pdev->dev, NULL,
101289 +                                                          &gta01bl_ops);
101290 +       if (IS_ERR(gta01_backlight_device))
101291 +               return PTR_ERR(gta01_backlight_device);
101292 +
101293 +       gta01bl_prop.power = FB_BLANK_UNBLANK;
101294 +       gta01bl_prop.brightness = gta01bl_prop.max_brightness;
101295 +       memcpy(&gta01_backlight_device->props,
101296 +              &gta01bl_prop, sizeof(gta01bl_prop));
101297 +       gta01bl_send_intensity(gta01_backlight_device);
101298 +
101299 +       return 0;
101300 +}
101301 +
101302 +static int gta01bl_remove(struct platform_device *dev)
101303 +{
101304 +#ifndef GTA01_BACKLIGHT_ONOFF_ONLY
101305 +       s3c2410_pwm_disable(&gta01bl.pwm);
101306 +#endif
101307 +       backlight_device_unregister(gta01_backlight_device);
101308 +       mutex_destroy(&gta01bl.mutex);
101309 +
101310 +       s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
101311 +       neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 1);
101312 +
101313 +       return 0;
101314 +}
101315 +
101316 +static struct platform_driver gta01bl_driver = {
101317 +       .probe          = gta01bl_probe,
101318 +       .remove         = gta01bl_remove,
101319 +       .suspend        = gta01bl_suspend,
101320 +       .resume         = gta01bl_resume,
101321 +       .driver         = {
101322 +               .name   = "gta01-bl",
101323 +       },
101324 +};
101325 +
101326 +static int __init gta01bl_init(void)
101327 +{
101328 +       return platform_driver_register(&gta01bl_driver);
101329 +}
101330 +
101331 +static void __exit gta01bl_exit(void)
101332 +{
101333 +       platform_driver_unregister(&gta01bl_driver);
101334 +}
101335 +
101336 +module_init(gta01bl_init);
101337 +module_exit(gta01bl_exit);
101338 +
101339 +MODULE_DESCRIPTION("FIC GTA01 (Neo1973) Backlight Driver");
101340 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
101341 +MODULE_LICENSE("GPL");
101342 --- a/drivers/video/backlight/Kconfig
101343 +++ b/drivers/video/backlight/Kconfig
101344 @@ -152,6 +152,13 @@ config BACKLIGHT_OMAP1
101345           the PWL module of OMAP1 processors.  Say Y if your board
101346           uses this hardware.
101347
101348 +config BACKLIGHT_GTA01
101349 +       tristate "FIC Neo1973 GTA01 Backlight Driver"
101350 +       depends on BACKLIGHT_CLASS_DEVICE && MACH_NEO1973_GTA01
101351 +       default y
101352 +       help
101353 +         If you have a FIC Neo1973 GTA01, say y to enable the backlight driver.
101354 +
101355  config BACKLIGHT_HP680
101356         tristate "HP Jornada 680 Backlight Driver"
101357         depends on BACKLIGHT_CLASS_DEVICE && SH_HP6XX
101358 --- a/drivers/video/backlight/Makefile
101359 +++ b/drivers/video/backlight/Makefile
101360 @@ -12,6 +12,7 @@ obj-$(CONFIG_LCD_TOSA)                   += tosa_lcd.o
101361  obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o
101362  obj-$(CONFIG_BACKLIGHT_ATMEL_PWM)    += atmel-pwm-bl.o
101363  obj-$(CONFIG_BACKLIGHT_CORGI)  += corgi_bl.o
101364 +obj-$(CONFIG_BACKLIGHT_GTA01)  += gta01_bl.o
101365  obj-$(CONFIG_BACKLIGHT_HP680)  += hp680_bl.o
101366  obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
101367  obj-$(CONFIG_BACKLIGHT_OMAP1)  += omap1_bl.o
101368 --- a/drivers/video/console/fbcon.c
101369 +++ b/drivers/video/console/fbcon.c
101370 @@ -401,6 +401,9 @@ static void fb_flashcursor(struct work_s
101371         int c;
101372         int mode;
101373
101374 +       if (info->state != FBINFO_STATE_RUNNING)
101375 +               return;
101376 +
101377         acquire_console_sem();
101378         if (ops && ops->currcon != -1)
101379                 vc = vc_cons[ops->currcon].d;
101380 @@ -3225,13 +3228,17 @@ static void fbcon_get_requirement(struct
101381  static int fbcon_event_notify(struct notifier_block *self,
101382                               unsigned long action, void *data)
101383  {
101384 -       struct fb_event *event = data;
101385 -       struct fb_info *info = event->info;
101386 +       struct fb_event *event;
101387 +       struct fb_info *info;
101388         struct fb_videomode *mode;
101389         struct fb_con2fbmap *con2fb;
101390         struct fb_blit_caps *caps;
101391         int ret = 0;
101392
101393 +       printk(KERN_INFO "fbcon_event_notify action=%ld, data=%p\n", action, data);
101394 +
101395 +       event = data;
101396 +       info = event->info;
101397         /*
101398          * ignore all events except driver registration and deregistration
101399          * if fbcon is not active
101400 --- /dev/null
101401 +++ b/drivers/video/display/jbt6k74.c
101402 @@ -0,0 +1,809 @@
101403 +/* Linux kernel driver for the tpo JBT6K74-AS LCM ASIC
101404 + *
101405 + * Copyright (C) 2006-2007 by Openmoko, Inc.
101406 + * Author: Harald Welte <laforge@openmoko.org>,
101407 + *        Stefan Schmidt <stefan@openmoko.org>
101408 + * Copyright (C) 2008 by Harald Welte <laforge@openmoko.org>
101409 + * All rights reserved.
101410 + *
101411 + * This program is free software; you can redistribute it and/or
101412 + * modify it under the terms of the GNU General Public License as
101413 + * published by the Free Software Foundation; either version 2 of
101414 + * the License, or (at your option) any later version.
101415 + *
101416 + * This program is distributed in the hope that it will be useful,
101417 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
101418 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
101419 + * GNU General Public License for more details.
101420 + *
101421 + * You should have received a copy of the GNU General Public License
101422 + * along with this program; if not, write to the Free Software
101423 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
101424 + * MA 02111-1307 USA
101425 + *
101426 + */
101427 +
101428 +#include <linux/kernel.h>
101429 +#include <linux/types.h>
101430 +#include <linux/module.h>
101431 +#include <linux/device.h>
101432 +#include <linux/platform_device.h>
101433 +#include <linux/delay.h>
101434 +#include <linux/jbt6k74.h>
101435 +#include <linux/fb.h>
101436 +
101437 +enum jbt_register {
101438 +       JBT_REG_SLEEP_IN                = 0x10,
101439 +       JBT_REG_SLEEP_OUT               = 0x11,
101440 +
101441 +       JBT_REG_DISPLAY_OFF             = 0x28,
101442 +       JBT_REG_DISPLAY_ON              = 0x29,
101443 +
101444 +       JBT_REG_RGB_FORMAT              = 0x3a,
101445 +       JBT_REG_QUAD_RATE               = 0x3b,
101446 +
101447 +       JBT_REG_POWER_ON_OFF            = 0xb0,
101448 +       JBT_REG_BOOSTER_OP              = 0xb1,
101449 +       JBT_REG_BOOSTER_MODE            = 0xb2,
101450 +       JBT_REG_BOOSTER_FREQ            = 0xb3,
101451 +       JBT_REG_OPAMP_SYSCLK            = 0xb4,
101452 +       JBT_REG_VSC_VOLTAGE             = 0xb5,
101453 +       JBT_REG_VCOM_VOLTAGE            = 0xb6,
101454 +       JBT_REG_EXT_DISPL               = 0xb7,
101455 +       JBT_REG_OUTPUT_CONTROL          = 0xb8,
101456 +       JBT_REG_DCCLK_DCEV              = 0xb9,
101457 +       JBT_REG_DISPLAY_MODE1           = 0xba,
101458 +       JBT_REG_DISPLAY_MODE2           = 0xbb,
101459 +       JBT_REG_DISPLAY_MODE            = 0xbc,
101460 +       JBT_REG_ASW_SLEW                = 0xbd,
101461 +       JBT_REG_DUMMY_DISPLAY           = 0xbe,
101462 +       JBT_REG_DRIVE_SYSTEM            = 0xbf,
101463 +
101464 +       JBT_REG_SLEEP_OUT_FR_A          = 0xc0,
101465 +       JBT_REG_SLEEP_OUT_FR_B          = 0xc1,
101466 +       JBT_REG_SLEEP_OUT_FR_C          = 0xc2,
101467 +       JBT_REG_SLEEP_IN_LCCNT_D        = 0xc3,
101468 +       JBT_REG_SLEEP_IN_LCCNT_E        = 0xc4,
101469 +       JBT_REG_SLEEP_IN_LCCNT_F        = 0xc5,
101470 +       JBT_REG_SLEEP_IN_LCCNT_G        = 0xc6,
101471 +
101472 +       JBT_REG_GAMMA1_FINE_1           = 0xc7,
101473 +       JBT_REG_GAMMA1_FINE_2           = 0xc8,
101474 +       JBT_REG_GAMMA1_INCLINATION      = 0xc9,
101475 +       JBT_REG_GAMMA1_BLUE_OFFSET      = 0xca,
101476 +
101477 +       /* VGA */
101478 +       JBT_REG_BLANK_CONTROL           = 0xcf,
101479 +       JBT_REG_BLANK_TH_TV             = 0xd0,
101480 +       JBT_REG_CKV_ON_OFF              = 0xd1,
101481 +       JBT_REG_CKV_1_2                 = 0xd2,
101482 +       JBT_REG_OEV_TIMING              = 0xd3,
101483 +       JBT_REG_ASW_TIMING_1            = 0xd4,
101484 +       JBT_REG_ASW_TIMING_2            = 0xd5,
101485 +
101486 +       /* QVGA */
101487 +       JBT_REG_BLANK_CONTROL_QVGA      = 0xd6,
101488 +       JBT_REG_BLANK_TH_TV_QVGA        = 0xd7,
101489 +       JBT_REG_CKV_ON_OFF_QVGA         = 0xd8,
101490 +       JBT_REG_CKV_1_2_QVGA            = 0xd9,
101491 +       JBT_REG_OEV_TIMING_QVGA         = 0xde,
101492 +       JBT_REG_ASW_TIMING_1_QVGA       = 0xdf,
101493 +       JBT_REG_ASW_TIMING_2_QVGA       = 0xe0,
101494 +
101495 +
101496 +       JBT_REG_HCLOCK_VGA              = 0xec,
101497 +       JBT_REG_HCLOCK_QVGA             = 0xed,
101498 +
101499 +};
101500 +
101501 +enum jbt_state {
101502 +       JBT_STATE_DEEP_STANDBY,
101503 +       JBT_STATE_SLEEP,
101504 +       JBT_STATE_NORMAL,
101505 +       JBT_STATE_QVGA_NORMAL,
101506 +};
101507 +
101508 +static const char *jbt_state_names[] = {
101509 +       [JBT_STATE_DEEP_STANDBY]        = "deep-standby",
101510 +       [JBT_STATE_SLEEP]               = "sleep",
101511 +       [JBT_STATE_NORMAL]              = "normal",
101512 +       [JBT_STATE_QVGA_NORMAL]         = "qvga-normal",
101513 +};
101514 +
101515 +struct jbt_info {
101516 +       enum jbt_state state, last_state;
101517 +       struct spi_device *spi_dev;
101518 +       struct mutex lock;              /* protects tx_buf and reg_cache */
101519 +       struct notifier_block fb_notif;
101520 +       u16 tx_buf[8];
101521 +       u16 reg_cache[0xEE];
101522 +       int have_resumed;
101523 +};
101524 +
101525 +#define JBT_COMMAND    0x000
101526 +#define JBT_DATA       0x100
101527 +
101528 +
101529 +static int jbt_reg_write_nodata(struct jbt_info *jbt, u8 reg)
101530 +{
101531 +       int rc;
101532 +
101533 +       mutex_lock(&jbt->lock);
101534 +
101535 +       jbt->tx_buf[0] = JBT_COMMAND | reg;
101536 +       rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
101537 +                      1*sizeof(u16));
101538 +       if (rc == 0)
101539 +               jbt->reg_cache[reg] = 0;
101540 +       else
101541 +               printk(KERN_ERR"jbt_reg_write_nodata spi_write ret %d\n",
101542 +                      rc);
101543 +
101544 +       mutex_unlock(&jbt->lock);
101545 +
101546 +       return rc;
101547 +}
101548 +
101549 +
101550 +static int jbt_reg_write(struct jbt_info *jbt, u8 reg, u8 data)
101551 +{
101552 +       int rc;
101553 +
101554 +       mutex_lock(&jbt->lock);
101555 +
101556 +       jbt->tx_buf[0] = JBT_COMMAND | reg;
101557 +       jbt->tx_buf[1] = JBT_DATA | data;
101558 +       rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
101559 +                      2*sizeof(u16));
101560 +       if (rc == 0)
101561 +               jbt->reg_cache[reg] = data;
101562 +       else
101563 +               printk(KERN_ERR"jbt_reg_write spi_write ret %d\n", rc);
101564 +
101565 +       mutex_unlock(&jbt->lock);
101566 +
101567 +       return rc;
101568 +}
101569 +
101570 +static int jbt_reg_write16(struct jbt_info *jbt, u8 reg, u16 data)
101571 +{
101572 +       int rc;
101573 +
101574 +       mutex_lock(&jbt->lock);
101575 +
101576 +       jbt->tx_buf[0] = JBT_COMMAND | reg;
101577 +       jbt->tx_buf[1] = JBT_DATA | (data >> 8);
101578 +       jbt->tx_buf[2] = JBT_DATA | (data & 0xff);
101579 +
101580 +       rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
101581 +                      3*sizeof(u16));
101582 +       if (rc == 0)
101583 +               jbt->reg_cache[reg] = data;
101584 +       else
101585 +               printk(KERN_ERR"jbt_reg_write16 spi_write ret %d\n", rc);
101586 +
101587 +       mutex_unlock(&jbt->lock);
101588 +
101589 +       return rc;
101590 +}
101591 +
101592 +static int jbt_init_regs(struct jbt_info *jbt, int qvga)
101593 +{
101594 +       int rc;
101595 +
101596 +       dev_dbg(&jbt->spi_dev->dev, "entering %cVGA mode\n", qvga ? 'Q' : ' ');
101597 +
101598 +       rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE1, 0x01);
101599 +       rc |= jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE2, 0x00);
101600 +       rc |= jbt_reg_write(jbt, JBT_REG_RGB_FORMAT, 0x60);
101601 +       rc |= jbt_reg_write(jbt, JBT_REG_DRIVE_SYSTEM, 0x10);
101602 +       rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56);
101603 +       rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33);
101604 +       rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
101605 +       rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02);
101606 +       rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b);
101607 +       rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40);
101608 +       rc |= jbt_reg_write(jbt, JBT_REG_EXT_DISPL, 0x03);
101609 +       rc |= jbt_reg_write(jbt, JBT_REG_DCCLK_DCEV, 0x04);
101610 +       /*
101611 +        * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
101612 +        * to avoid red / blue flicker
101613 +        */
101614 +       rc |= jbt_reg_write(jbt, JBT_REG_ASW_SLEW, 0x04);
101615 +       rc |= jbt_reg_write(jbt, JBT_REG_DUMMY_DISPLAY, 0x00);
101616 +
101617 +       rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_A, 0x11);
101618 +       rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_B, 0x11);
101619 +       rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_C, 0x11);
101620 +       rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
101621 +       rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
101622 +       rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
101623 +       rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
101624 +
101625 +       rc |= jbt_reg_write16(jbt, JBT_REG_GAMMA1_FINE_1, 0x5533);
101626 +       rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00);
101627 +       rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00);
101628 +       rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
101629 +
101630 +       if (!qvga) {
101631 +               rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0);
101632 +               rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02);
101633 +               rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
101634 +
101635 +               rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01);
101636 +               rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000);
101637 +
101638 +               rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING, 0x0d0e);
101639 +               rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1, 0x11a4);
101640 +               rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2, 0x0e);
101641 +       } else {
101642 +               rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
101643 +               rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL_QVGA, 0x02);
101644 +               rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV_QVGA, 0x0804);
101645 +
101646 +               rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF_QVGA, 0x01);
101647 +               rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2_QVGA, 0x0008);
101648 +
101649 +               rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING_QVGA, 0x050a);
101650 +               rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1_QVGA, 0x0a19);
101651 +               rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2_QVGA, 0x0a);
101652 +       }
101653 +
101654 +       return rc ? -EIO : 0;
101655 +}
101656 +
101657 +static int standby_to_sleep(struct jbt_info *jbt)
101658 +{
101659 +       int rc;
101660 +
101661 +       /* three times command zero */
101662 +       rc = jbt_reg_write_nodata(jbt, 0x00);
101663 +       mdelay(1);
101664 +       rc |= jbt_reg_write_nodata(jbt, 0x00);
101665 +       mdelay(1);
101666 +       rc |= jbt_reg_write_nodata(jbt, 0x00);
101667 +       mdelay(1);
101668 +
101669 +       /* deep standby out */
101670 +       rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x17);
101671 +
101672 +       return rc ? -EIO : 0;
101673 +}
101674 +
101675 +static int sleep_to_normal(struct jbt_info *jbt)
101676 +{
101677 +       int rc;
101678 +
101679 +       /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
101680 +       rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x80);
101681 +
101682 +       /* Quad mode off */
101683 +       rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x00);
101684 +
101685 +       /* AVDD on, XVDD on */
101686 +       rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
101687 +
101688 +       /* Output control */
101689 +       rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
101690 +
101691 +       /* Sleep mode off */
101692 +       rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
101693 +
101694 +       /* initialize register set */
101695 +       rc |= jbt_init_regs(jbt, 0);
101696 +
101697 +       /* Turn on display */
101698 +       rc |= jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
101699 +
101700 +       return rc ? -EIO : 0;
101701 +}
101702 +
101703 +static int sleep_to_qvga_normal(struct jbt_info *jbt)
101704 +{
101705 +       int rc;
101706 +
101707 +       /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
101708 +       rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x81);
101709 +
101710 +       /* Quad mode on */
101711 +       rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x22);
101712 +
101713 +       /* AVDD on, XVDD on */
101714 +       rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
101715 +
101716 +       /* Output control */
101717 +       rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
101718 +
101719 +       /* Sleep mode off */
101720 +       rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
101721 +
101722 +       /* initialize register set for qvga*/
101723 +       rc |= jbt_init_regs(jbt, 1);
101724 +
101725 +       /* Turn on display */
101726 +       rc |= jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
101727 +
101728 +       return rc ? -EIO : 0;
101729 +}
101730 +
101731 +static int normal_to_sleep(struct jbt_info *jbt)
101732 +{
101733 +       int rc;
101734 +
101735 +       rc = jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
101736 +       rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0x8002);
101737 +       rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_IN);
101738 +
101739 +       return rc ? -EIO : 0;
101740 +}
101741 +
101742 +static int sleep_to_standby(struct jbt_info *jbt)
101743 +{
101744 +       return jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x00);
101745 +}
101746 +
101747 +/* frontend function */
101748 +int jbt6k74_enter_state(struct jbt_info *jbt, enum jbt_state new_state)
101749 +{
101750 +       int rc = -EINVAL;
101751 +
101752 +       dev_dbg(&jbt->spi_dev->dev, "entering (old_state=%u, "
101753 +               "new_state=%u)\n", jbt->state, new_state);
101754 +
101755 +       switch (jbt->state) {
101756 +       case JBT_STATE_DEEP_STANDBY:
101757 +               switch (new_state) {
101758 +               case JBT_STATE_DEEP_STANDBY:
101759 +                       rc = 0;
101760 +                       break;
101761 +               case JBT_STATE_SLEEP:
101762 +                       rc = standby_to_sleep(jbt);
101763 +                       break;
101764 +               case JBT_STATE_NORMAL:
101765 +                       /* first transition into sleep */
101766 +                       rc = standby_to_sleep(jbt);
101767 +                       /* then transition into normal */
101768 +                       rc |= sleep_to_normal(jbt);
101769 +                       break;
101770 +               case JBT_STATE_QVGA_NORMAL:
101771 +                       /* first transition into sleep */
101772 +                       rc = standby_to_sleep(jbt);
101773 +                       /* then transition into normal */
101774 +                       rc |= sleep_to_qvga_normal(jbt);
101775 +                       break;
101776 +               }
101777 +               break;
101778 +       case JBT_STATE_SLEEP:
101779 +               switch (new_state) {
101780 +               case JBT_STATE_SLEEP:
101781 +                       rc = 0;
101782 +                       break;
101783 +               case JBT_STATE_DEEP_STANDBY:
101784 +                       rc = sleep_to_standby(jbt);
101785 +                       break;
101786 +               case JBT_STATE_NORMAL:
101787 +                       rc = sleep_to_normal(jbt);
101788 +                       break;
101789 +               case JBT_STATE_QVGA_NORMAL:
101790 +                       rc = sleep_to_qvga_normal(jbt);
101791 +                       break;
101792 +               }
101793 +               break;
101794 +       case JBT_STATE_NORMAL:
101795 +               switch (new_state) {
101796 +               case JBT_STATE_NORMAL:
101797 +                       rc = 0;
101798 +                       break;
101799 +               case JBT_STATE_DEEP_STANDBY:
101800 +                       /* first transition into sleep */
101801 +                       rc = normal_to_sleep(jbt);
101802 +                       /* then transition into deep standby */
101803 +                       rc |= sleep_to_standby(jbt);
101804 +                       break;
101805 +               case JBT_STATE_SLEEP:
101806 +                       rc = normal_to_sleep(jbt);
101807 +                       break;
101808 +               case JBT_STATE_QVGA_NORMAL:
101809 +                       /* first transition into sleep */
101810 +                       rc = normal_to_sleep(jbt);
101811 +                       /* second transition into deep standby */
101812 +                       rc |= sleep_to_standby(jbt);
101813 +                       /* third transition into sleep */
101814 +                       rc |= standby_to_sleep(jbt);
101815 +                       /* fourth transition into normal */
101816 +                       rc |= sleep_to_qvga_normal(jbt);
101817 +                       break;
101818 +               }
101819 +               break;
101820 +       case JBT_STATE_QVGA_NORMAL:
101821 +               switch (new_state) {
101822 +               case JBT_STATE_QVGA_NORMAL:
101823 +                       rc = 0;
101824 +                       break;
101825 +               case JBT_STATE_DEEP_STANDBY:
101826 +                       /* first transition into sleep */
101827 +                       rc = normal_to_sleep(jbt);
101828 +                       /* then transition into deep standby */
101829 +                       rc |= sleep_to_standby(jbt);
101830 +                       break;
101831 +               case JBT_STATE_SLEEP:
101832 +                       rc = normal_to_sleep(jbt);
101833 +                       break;
101834 +               case JBT_STATE_NORMAL:
101835 +                       /* first transition into sleep */
101836 +                       rc = normal_to_sleep(jbt);
101837 +                       /* second transition into deep standby */
101838 +                       rc |= sleep_to_standby(jbt);
101839 +                       /* third transition into sleep */
101840 +                       rc |= standby_to_sleep(jbt);
101841 +                       /* fourth transition into normal */
101842 +                       rc |= sleep_to_normal(jbt);
101843 +                       break;
101844 +               }
101845 +               break;
101846 +       }
101847 +
101848 +       if (rc == 0)
101849 +               jbt->state = new_state;
101850 +
101851 +       return rc;
101852 +}
101853 +EXPORT_SYMBOL_GPL(jbt6k74_enter_state);
101854 +
101855 +static ssize_t state_read(struct device *dev, struct device_attribute *attr,
101856 +                         char *buf)
101857 +{
101858 +       struct jbt_info *jbt = dev_get_drvdata(dev);
101859 +
101860 +       if (jbt->state >= ARRAY_SIZE(jbt_state_names))
101861 +               return -EIO;
101862 +
101863 +       return sprintf(buf, "%s\n", jbt_state_names[jbt->state]);
101864 +}
101865 +
101866 +static ssize_t state_write(struct device *dev, struct device_attribute *attr,
101867 +                          const char *buf, size_t count)
101868 +{
101869 +       struct jbt_info *jbt = dev_get_drvdata(dev);
101870 +       int i, rc;
101871 +
101872 +       for (i = 0; i < ARRAY_SIZE(jbt_state_names); i++) {
101873 +               if (!strncmp(buf, jbt_state_names[i],
101874 +                            strlen(jbt_state_names[i]))) {
101875 +                       rc = jbt6k74_enter_state(jbt, i);
101876 +                       if (rc)
101877 +                               return rc;
101878 +                       return count;
101879 +               }
101880 +       }
101881 +
101882 +       return -EINVAL;
101883 +}
101884 +
101885 +static DEVICE_ATTR(state, 0644, state_read, state_write);
101886 +
101887 +static int reg_by_string(const char *name)
101888 +{
101889 +       if (!strcmp(name, "gamma_fine1"))
101890 +               return JBT_REG_GAMMA1_FINE_1;
101891 +       else if (!strcmp(name, "gamma_fine2"))
101892 +               return JBT_REG_GAMMA1_FINE_2;
101893 +       else if (!strcmp(name, "gamma_inclination"))
101894 +               return JBT_REG_GAMMA1_INCLINATION;
101895 +       else
101896 +               return JBT_REG_GAMMA1_BLUE_OFFSET;
101897 +}
101898 +
101899 +static ssize_t gamma_read(struct device *dev, struct device_attribute *attr,
101900 +                         char *buf)
101901 +{
101902 +       struct jbt_info *jbt = dev_get_drvdata(dev);
101903 +       int reg = reg_by_string(attr->attr.name);
101904 +       u16 val;
101905 +
101906 +       mutex_lock(&jbt->lock);
101907 +       val = jbt->reg_cache[reg];
101908 +       mutex_unlock(&jbt->lock);
101909 +
101910 +       return sprintf(buf, "0x%04x\n", val);
101911 +}
101912 +
101913 +static ssize_t gamma_write(struct device *dev, struct device_attribute *attr,
101914 +                          const char *buf, size_t count)
101915 +{
101916 +       struct jbt_info *jbt = dev_get_drvdata(dev);
101917 +       int reg = reg_by_string(attr->attr.name);
101918 +       unsigned long val = simple_strtoul(buf, NULL, 10);
101919 +
101920 +       dev_info(dev, "**** jbt6k74 writing gama %lu\n", val & 0xff);
101921 +
101922 +       jbt_reg_write(jbt, reg, val & 0xff);
101923 +
101924 +       return count;
101925 +}
101926 +
101927 +static ssize_t reset_write(struct device *dev, struct device_attribute *attr,
101928 +                          const char *buf, size_t count)
101929 +{
101930 +       struct jbt_info *jbt = dev_get_drvdata(dev);
101931 +       struct jbt6k74_platform_data *jbt6k74_pdata = jbt->spi_dev->dev.platform_data;
101932 +       int rc;
101933 +
101934 +       dev_info(dev, "**** jbt6k74 reset\n");
101935 +
101936 +       /* hard reset the jbt6k74 */
101937 +
101938 +       (jbt6k74_pdata->reset)(0, 0);
101939 +       mdelay(1);
101940 +       (jbt6k74_pdata->reset)(0, 1);
101941 +       mdelay(120);
101942 +
101943 +       rc = jbt_reg_write_nodata(jbt, 0x01);
101944 +       if (rc < 0)
101945 +               dev_err(dev, "cannot soft reset\n");
101946 +
101947 +       mdelay(120);
101948 +
101949 +       jbt->state = JBT_STATE_DEEP_STANDBY;
101950 +
101951 +       switch (jbt->last_state) {
101952 +       case JBT_STATE_QVGA_NORMAL:
101953 +               jbt6k74_enter_state(jbt, JBT_STATE_QVGA_NORMAL);
101954 +               break;
101955 +       default:
101956 +               jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
101957 +               break;
101958 +       }
101959 +
101960 +       return count;
101961 +}
101962 +
101963 +static DEVICE_ATTR(gamma_fine1, 0644, gamma_read, gamma_write);
101964 +static DEVICE_ATTR(gamma_fine2, 0644, gamma_read, gamma_write);
101965 +static DEVICE_ATTR(gamma_inclination, 0644, gamma_read, gamma_write);
101966 +static DEVICE_ATTR(gamma_blue_offset, 0644, gamma_read, gamma_write);
101967 +static DEVICE_ATTR(reset, 0600, NULL, reset_write);
101968 +
101969 +static struct attribute *jbt_sysfs_entries[] = {
101970 +       &dev_attr_state.attr,
101971 +       &dev_attr_gamma_fine1.attr,
101972 +       &dev_attr_gamma_fine2.attr,
101973 +       &dev_attr_gamma_inclination.attr,
101974 +       &dev_attr_gamma_blue_offset.attr,
101975 +       &dev_attr_reset.attr,
101976 +       NULL,
101977 +};
101978 +
101979 +static struct attribute_group jbt_attr_group = {
101980 +       .name   = NULL,
101981 +       .attrs  = jbt_sysfs_entries,
101982 +};
101983 +
101984 +static int fb_notifier_callback(struct notifier_block *self,
101985 +                               unsigned long event, void *data)
101986 +{
101987 +       struct jbt_info *jbt;
101988 +       struct fb_event *evdata = data;
101989 +       int fb_blank;
101990 +
101991 +       if (event != FB_EVENT_BLANK && event != FB_EVENT_CONBLANK)
101992 +               return 0;
101993 +
101994 +       fb_blank = *(int *)evdata->data;
101995 +       jbt = container_of(self, struct jbt_info, fb_notif);
101996 +
101997 +       switch (fb_blank) {
101998 +       case FB_BLANK_UNBLANK:
101999 +               dev_info(&jbt->spi_dev->dev, "**** jbt6k74 unblank\n");
102000 +               jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
102001 +               break;
102002 +       case FB_BLANK_NORMAL:
102003 +               dev_info(&jbt->spi_dev->dev, "**** jbt6k74 normal\n");
102004 +               break;
102005 +       case FB_BLANK_VSYNC_SUSPEND:
102006 +               dev_info(&jbt->spi_dev->dev, "**** jbt6k74 vsync suspend\n");
102007 +               break;
102008 +       case FB_BLANK_HSYNC_SUSPEND:
102009 +               dev_info(&jbt->spi_dev->dev, "**** jbt6k74 hsync suspend\n");
102010 +               /* FIXME: we disable SLEEP since it would result in
102011 +                * a visible artefact (white screen) before the backlight
102012 +                * is dimmed to a dark enough level */
102013 +               /* jbt6k74_enter_state(jbt, JBT_STATE_SLEEP); */
102014 +               break;
102015 +       case FB_BLANK_POWERDOWN:
102016 +               dev_info(&jbt->spi_dev->dev, "**** jbt6k74 powerdown\n");
102017 +       /* FIXME: deep standby causes WSOD on certain devices. We use
102018 +        * sleep as workaround */
102019 +               jbt6k74_enter_state(jbt, JBT_STATE_SLEEP);
102020 +               break;
102021 +       }
102022 +
102023 +       return 0;
102024 +}
102025 +
102026 +/* linux device model infrastructure */
102027 +
102028 +static int __devinit jbt_probe(struct spi_device *spi)
102029 +{
102030 +       int rc;
102031 +       struct jbt_info *jbt;
102032 +       struct jbt6k74_platform_data *jbt6k74_pdata = spi->dev.platform_data;
102033 +
102034 +       /* the controller doesn't have a MISO pin; we can't do detection */
102035 +
102036 +       spi->mode = SPI_CPOL | SPI_CPHA;
102037 +       spi->bits_per_word = 9;
102038 +
102039 +       rc = spi_setup(spi);
102040 +       if (rc < 0) {
102041 +               dev_err(&spi->dev,
102042 +                       "error during spi_setup of jbt6k74 driver\n");
102043 +               return rc;
102044 +       }
102045 +
102046 +       jbt = kzalloc(sizeof(*jbt), GFP_KERNEL);
102047 +       if (!jbt)
102048 +               return -ENOMEM;
102049 +
102050 +       jbt->spi_dev = spi;
102051 +       jbt->state = JBT_STATE_DEEP_STANDBY;
102052 +       mutex_init(&jbt->lock);
102053 +
102054 +       dev_set_drvdata(&spi->dev, jbt);
102055 +
102056 +       /* hard reset the jbt6k74 */
102057 +
102058 +       (jbt6k74_pdata->reset)(0, 0);
102059 +       mdelay(1);
102060 +       (jbt6k74_pdata->reset)(0, 1);
102061 +       mdelay(120);
102062 +
102063 +       rc = jbt_reg_write_nodata(jbt, 0x01);
102064 +       if (rc < 0)
102065 +               dev_err(&spi->dev, "cannot soft reset\n");
102066 +
102067 +       mdelay(120);
102068 +
102069 +
102070 +       rc = jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
102071 +       if (rc < 0) {
102072 +               dev_err(&spi->dev, "cannot enter NORMAL state\n");
102073 +               goto err_free_drvdata;
102074 +       }
102075 +
102076 +       rc = sysfs_create_group(&spi->dev.kobj, &jbt_attr_group);
102077 +       if (rc < 0) {
102078 +               dev_err(&spi->dev, "cannot create sysfs group\n");
102079 +               goto err_standby;
102080 +       }
102081 +
102082 +       jbt->fb_notif.notifier_call = fb_notifier_callback;
102083 +       rc = fb_register_client(&jbt->fb_notif);
102084 +       if (rc < 0) {
102085 +               dev_err(&spi->dev, "cannot register notifier\n");
102086 +               goto err_sysfs;
102087 +       }
102088 +
102089 +       if (jbt6k74_pdata->probe_completed)
102090 +               jbt6k74_pdata->probe_completed(&spi->dev);
102091 +
102092 +       return 0;
102093 +
102094 +err_sysfs:
102095 +       sysfs_remove_group(&spi->dev.kobj, &jbt_attr_group);
102096 +err_standby:
102097 +       jbt6k74_enter_state(jbt, JBT_STATE_DEEP_STANDBY);
102098 +err_free_drvdata:
102099 +       dev_set_drvdata(&spi->dev, NULL);
102100 +       kfree(jbt);
102101 +
102102 +       return rc;
102103 +}
102104 +
102105 +static int __devexit jbt_remove(struct spi_device *spi)
102106 +{
102107 +       struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
102108 +
102109 +       /* We don't want to switch off the display in case the user
102110 +        * accidentially onloads the module (whose use count normally is 0) */
102111 +
102112 +       fb_unregister_client(&jbt->fb_notif);
102113 +       sysfs_remove_group(&spi->dev.kobj, &jbt_attr_group);
102114 +       dev_set_drvdata(&spi->dev, NULL);
102115 +       kfree(jbt);
102116 +
102117 +       return 0;
102118 +}
102119 +
102120 +#ifdef CONFIG_PM
102121 +static int jbt_suspend(struct spi_device *spi, pm_message_t state)
102122 +{
102123 +       struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
102124 +
102125 +       /* Save mode for resume */
102126 +       jbt->last_state = jbt->state;
102127 +       /* FIXME: deep standby causes WSOD on certain devices. We use
102128 +        * sleep as workaround */
102129 +       jbt6k74_enter_state(jbt, JBT_STATE_SLEEP);
102130 +
102131 +       jbt->have_resumed = 0;
102132 +
102133 +       dev_info(&spi->dev, "**** jbt6k74 suspend end\n");
102134 +
102135 +       return 0;
102136 +}
102137 +
102138 +int jbt6k74_resume(struct spi_device *spi)
102139 +{
102140 +       struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
102141 +       struct jbt6k74_platform_data *jbt6k74_pdata = spi->dev.platform_data;
102142 +       int rc;
102143 +
102144 +       dev_info(&spi->dev, "**** jbt6k74 resume start\n");
102145 +
102146 +       /* hard reset the jbt6k74 */
102147 +
102148 +       (jbt6k74_pdata->reset)(0, 0);
102149 +       mdelay(1);
102150 +       (jbt6k74_pdata->reset)(0, 1);
102151 +       mdelay(120);
102152 +
102153 +       rc = jbt_reg_write_nodata(jbt, 0x01);
102154 +       if (rc < 0)
102155 +               dev_err(&spi->dev, "cannot soft reset\n");
102156 +
102157 +       mdelay(120);
102158 +
102159 +       jbt->state = JBT_STATE_DEEP_STANDBY;
102160 +
102161 +       switch (jbt->last_state) {
102162 +       case JBT_STATE_QVGA_NORMAL:
102163 +               jbt6k74_enter_state(jbt, JBT_STATE_QVGA_NORMAL);
102164 +               break;
102165 +       default:
102166 +               jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
102167 +               break;
102168 +       }
102169 +
102170 +       if (jbt6k74_pdata->resuming)
102171 +               (jbt6k74_pdata->resuming)(0);
102172 +
102173 +       dev_info(&spi->dev, "**** jbt6k74 resume end\n");
102174 +
102175 +       return 0;
102176 +}
102177 +EXPORT_SYMBOL_GPL(jbt6k74_resume);
102178 +
102179 +#else
102180 +#define jbt_suspend    NULL
102181 +#define jbt_resume     NULL
102182 +#endif
102183 +
102184 +static struct spi_driver jbt6k74_driver = {
102185 +       .driver = {
102186 +               .name   = "jbt6k74",
102187 +               .owner  = THIS_MODULE,
102188 +       },
102189 +
102190 +       .probe   = jbt_probe,
102191 +       .remove  = __devexit_p(jbt_remove),
102192 +       .suspend = jbt_suspend,
102193 +       .resume  = jbt6k74_resume,
102194 +};
102195 +
102196 +static int __init jbt_init(void)
102197 +{
102198 +       return spi_register_driver(&jbt6k74_driver);
102199 +}
102200 +
102201 +static void __exit jbt_exit(void)
102202 +{
102203 +       spi_unregister_driver(&jbt6k74_driver);
102204 +}
102205 +
102206 +MODULE_DESCRIPTION("SPI driver for tpo JBT6K74-AS LCM control interface");
102207 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
102208 +MODULE_LICENSE("GPL");
102209 +
102210 +module_init(jbt_init);
102211 +module_exit(jbt_exit);
102212 --- a/drivers/video/display/Kconfig
102213 +++ b/drivers/video/display/Kconfig
102214 @@ -21,4 +21,15 @@ config DISPLAY_SUPPORT
102215  comment "Display hardware drivers"
102216         depends on DISPLAY_SUPPORT
102217
102218 +config DISPLAY_JBT6K74
102219 +       tristate "TPO JBT6K74-AS TFT display ASIC control interface"
102220 +       depends on SPI_MASTER && SYSFS
102221 +       help
102222 +         SPI driver for the control interface of TFT panels containing
102223 +         the TPO JBT6K74-AS controller ASIC, such as the TPO TD028TTEC1
102224 +         TFT diplay module used in the FIC/Openmoko Neo1973 GSM phones.
102225 +
102226 +         The control interface is required for display operation, as it
102227 +         controls power management, display timing and gamma calibration.
102228 +
102229  endmenu
102230 --- a/drivers/video/display/Makefile
102231 +++ b/drivers/video/display/Makefile
102232 @@ -3,4 +3,5 @@
102233  display-objs                           := display-sysfs.o
102234
102235  obj-$(CONFIG_DISPLAY_SUPPORT)          += display.o
102236 +obj-$(CONFIG_DISPLAY_JBT6K74)          += jbt6k74.o
102237
102238 --- a/drivers/video/Kconfig
102239 +++ b/drivers/video/Kconfig
102240 @@ -1918,6 +1918,30 @@ config FB_TMIO_ACCELL
102241         depends on FB_TMIO
102242         default y
102243
102244 +config FB_S3C
102245 +       tristate "Samsung S3C framebuffer support"
102246 +       depends on FB && ARCH_S3C64XX
102247 +       select FB_CFB_FILLRECT
102248 +       select FB_CFB_COPYAREA
102249 +       select FB_CFB_IMAGEBLIT
102250 +       ---help---
102251 +         Frame buffer driver for the built-in FB controller in the Samsung
102252 +         SoC line from the S3C2443 onwards, including the S3C2416, S3C2450,
102253 +         and the S3C64XX series such as the S3C6400 and S3C6410.
102254 +
102255 +         These chips all have the same basic framebuffer design with the
102256 +         actual capabilities depending on the chip. For instance the S3C6400
102257 +         and S3C6410 support 4 hardware windows whereas the S3C24XX series
102258 +         currently only have two.
102259 +
102260 +         Currently the support is only for the S3C6400 and S3C6410 SoCs.
102261 +
102262 +config FB_S3C_DEBUG_REGWRITE
102263 +       bool "Debug register writes"
102264 +       depends on FB_S3C
102265 +       ---help---
102266 +         Show all register writes via printk(KERN_DEBUG)
102267 +
102268  config FB_S3C2410
102269         tristate "S3C2410 LCD framebuffer support"
102270         depends on FB && ARCH_S3C2410
102271 --- a/drivers/video/logo/Kconfig
102272 +++ b/drivers/video/logo/Kconfig
102273 @@ -77,6 +77,11 @@ config LOGO_SUPERH_CLUT224
102274         depends on SUPERH
102275         default y
102276
102277 +config LOGO_OPENMOKO_CLUT224
102278 +       bool "224-color Openmoko Linux logo"
102279 +       depends on MACH_NEO1973_GTA01 || MACH_NEO1973_GTA02
102280 +       default y
102281 +
102282  config LOGO_M32R_CLUT224
102283         bool "224-color M32R Linux logo"
102284         depends on M32R
102285 --- a/drivers/video/logo/logo.c
102286 +++ b/drivers/video/logo/logo.c
102287 @@ -35,6 +35,7 @@ extern const struct linux_logo logo_supe
102288  extern const struct linux_logo logo_superh_vga16;
102289  extern const struct linux_logo logo_superh_clut224;
102290  extern const struct linux_logo logo_m32r_clut224;
102291 +extern const struct linux_logo logo_openmoko_clut224;
102292
102293  static int nologo;
102294  module_param(nologo, bool, 0);
102295 @@ -115,6 +116,10 @@ const struct linux_logo * __init_refok f
102296                 /* M32R Linux logo */
102297                 logo = &logo_m32r_clut224;
102298  #endif
102299 +#ifdef CONFIG_LOGO_OPENMOKO_CLUT224
102300 +               /* Openmoko Linux logo */
102301 +               logo = &logo_openmoko_clut224;
102302 +#endif
102303         }
102304         return logo;
102305  }
102306 --- /dev/null
102307 +++ b/drivers/video/logo/logo_openmoko_clut224.ppm
102308 @@ -0,0 +1,40003 @@
102309 +P3
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142237 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142238 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142239 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142240 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142241 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142242 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142243 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142244 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142245 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142246 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142247 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142248 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142249 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142250 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142251 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142252 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142253 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142254 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142255 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142256 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142257 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142258 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142259 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142260 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142261 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142262 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142263 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142264 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142265 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142266 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142267 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142268 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142269 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142270 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142271 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142272 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142273 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142274 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142275 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142276 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142277 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142278 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142279 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142280 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142281 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142282 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142283 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142284 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142285 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142286 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142287 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142288 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142289 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142290 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142291 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142292 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142293 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142294 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142295 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142296 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142297 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142298 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142299 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142300 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142301 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142302 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142303 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142304 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142305 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142306 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142307 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142308 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142309 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142310 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142311 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
142312 --- a/drivers/video/logo/Makefile
142313 +++ b/drivers/video/logo/Makefile
142314 @@ -15,6 +15,7 @@ obj-$(CONFIG_LOGO_SUPERH_MONO)                += logo_
142315  obj-$(CONFIG_LOGO_SUPERH_VGA16)                += logo_superh_vga16.o
142316  obj-$(CONFIG_LOGO_SUPERH_CLUT224)      += logo_superh_clut224.o
142317  obj-$(CONFIG_LOGO_M32R_CLUT224)                += logo_m32r_clut224.o
142318 +obj-$(CONFIG_LOGO_OPENMOKO_CLUT224)    += logo_openmoko_clut224.o
142319
142320  obj-$(CONFIG_SPU_BASE)                 += logo_spe_clut224.o
142321
142322 --- a/drivers/video/Makefile
142323 +++ b/drivers/video/Makefile
142324 @@ -109,6 +109,7 @@ obj-$(CONFIG_FB_METRONOME)        += met
142325  obj-$(CONFIG_FB_S1D13XXX)        += s1d13xxxfb.o
142326  obj-$(CONFIG_FB_SH7760)                  += sh7760fb.o
142327  obj-$(CONFIG_FB_IMX)              += imxfb.o
142328 +obj-$(CONFIG_FB_S3C)             += s3c-fb.o
142329  obj-$(CONFIG_FB_S3C2410)         += s3c2410fb.o
142330  obj-$(CONFIG_FB_FSL_DIU)         += fsl-diu-fb.o
142331  obj-$(CONFIG_FB_COBALT)           += cobalt_lcdfb.o
142332 --- a/drivers/video/s3c2410fb.c
142333 +++ b/drivers/video/s3c2410fb.c
142334 @@ -1017,6 +1017,8 @@ static int s3c2410fb_resume(struct platf
142335
142336         s3c2410fb_init_registers(fbinfo);
142337
142338 +       s3c2410fb_set_par(fbinfo);
142339 +
142340         return 0;
142341  }
142342
142343 --- /dev/null
142344 +++ b/drivers/video/s3c-fb.c
142345 @@ -0,0 +1,1036 @@
142346 +/* linux/drivers/video/s3c-fb.c
142347 + *
142348 + * Copyright 2008 Openmoko Inc.
142349 + * Copyright 2008 Simtec Electronics
142350 + *      Ben Dooks <ben@simtec.co.uk>
142351 + *      http://armlinux.simtec.co.uk/
142352 + *
142353 + * Samsung SoC Framebuffer driver
142354 + *
142355 + * This program is free software; you can redistribute it and/or modify
142356 + * it under the terms of the GNU General Public License version 2 as
142357 + * published by the Free Software Foundation.
142358 +*/
142359 +
142360 +#include <linux/kernel.h>
142361 +#include <linux/module.h>
142362 +#include <linux/platform_device.h>
142363 +#include <linux/dma-mapping.h>
142364 +#include <linux/init.h>
142365 +#include <linux/gfp.h>
142366 +#include <linux/clk.h>
142367 +#include <linux/fb.h>
142368 +#include <linux/io.h>
142369 +
142370 +#include <mach/map.h>
142371 +#include <mach/regs-fb.h>
142372 +#include <plat/fb.h>
142373 +
142374 +/* This driver will export a number of framebuffer interfaces depending
142375 + * on the configuration passed in via the platform data. Each fb instance
142376 + * maps to a hardware window. Currently there is no support for runtime
142377 + * setting of the alpha-blending functions that each window has, so only
142378 + * window 0 is actually useful.
142379 + *
142380 + * Window 0 is treated specially, it is used for the basis of the LCD
142381 + * output timings and as the control for the output power-down state.
142382 +*/
142383 +
142384 +/* note, some of the functions that get called are derived from including
142385 + * <mach/regs-fb.h> as they are specific to the architecture that the code
142386 + * is being built for.
142387 +*/
142388 +
142389 +#ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
142390 +#undef writel
142391 +#define writel(v, r) do { \
142392 +       printk(KERN_DEBUG "%s: %08x => %p\n", __func__, (unsigned int)v, r); \
142393 +       __raw_writel(v, r); } while(0)
142394 +#endif /* FB_S3C_DEBUG_REGWRITE */
142395 +
142396 +struct s3c_fb;
142397 +
142398 +/**
142399 + * struct s3c_fb_win - per window private data for each framebuffer.
142400 + * @windata: The platform data supplied for the window configuration.
142401 + * @parent: The hardware that this window is part of.
142402 + * @fbinfo: Pointer pack to the framebuffer info for this window.
142403 + * @palette_buffer: Buffer/cache to hold palette entries.
142404 + * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
142405 + * @index: The window number of this window.
142406 + * @palette: The bitfields for changing r/g/b into a hardware palette entry.
142407 + */
142408 +struct s3c_fb_win {
142409 +       struct s3c_fb_pd_win    *windata;
142410 +       struct s3c_fb           *parent;
142411 +       struct fb_info          *fbinfo;
142412 +       struct s3c_fb_palette    palette;
142413 +
142414 +       u32                     *palette_buffer;
142415 +       u32                      pseudo_palette[16];
142416 +       unsigned int             index;
142417 +};
142418 +
142419 +/**
142420 + * struct s3c_fb - overall hardware state of the hardware
142421 + * @dev: The device that we bound to, for printing, etc.
142422 + * @regs_res: The resource we claimed for the IO registers.
142423 + * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
142424 + * @regs: The mapped hardware registers.
142425 + * @enabled: A bitmask of enabled hardware windows.
142426 + * @pdata: The platform configuration data passed with the device.
142427 + * @windows: The hardware windows that have been claimed.
142428 + */
142429 +struct s3c_fb {
142430 +       struct device           *dev;
142431 +       struct resource         *regs_res;
142432 +       struct clk              *bus_clk;
142433 +       void __iomem            *regs;
142434 +
142435 +       unsigned char            enabled;
142436 +
142437 +       struct s3c_fb_platdata  *pdata;
142438 +       struct s3c_fb_win       *windows[S3C_FB_MAX_WIN];
142439 +};
142440 +
142441 +/**
142442 + * s3c_fb_win_has_palette() - determine if a mode has a palette
142443 + * @win: The window number being queried.
142444 + * @bpp: The number of bits per pixel to test.
142445 + *
142446 + * Work out if the given window supports palletised data at the specified bpp.
142447 + */
142448 +static int s3c_fb_win_has_palette(unsigned int win, unsigned int bpp)
142449 +{
142450 +       return s3c_fb_win_pal_size(win) <= (1 << bpp);
142451 +}
142452 +
142453 +/**
142454 + * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
142455 + * @var: The screen information to verify.
142456 + * @info: The framebuffer device.
142457 + *
142458 + * Framebuffer layer call to verify the given information and allow us to
142459 + * update various information depending on the hardware capabilities.
142460 + */
142461 +static int s3c_fb_check_var(struct fb_var_screeninfo *var,
142462 +                           struct fb_info *info)
142463 +{
142464 +       struct s3c_fb_win *win = info->par;
142465 +       struct s3c_fb_pd_win *windata = win->windata;
142466 +       struct s3c_fb *sfb = win->parent;
142467 +
142468 +       dev_dbg(sfb->dev, "checking parameters\n");
142469 +
142470 +       var->xres_virtual = max((unsigned int)windata->virtual_x, var->xres);
142471 +       var->yres_virtual = max((unsigned int)windata->virtual_y, var->yres);
142472 +
142473 +       if (!s3c_fb_validate_win_bpp(win->index, var->bits_per_pixel)) {
142474 +               dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
142475 +                       win->index, var->bits_per_pixel);
142476 +               return -EINVAL;
142477 +       }
142478 +
142479 +       /* always ensure these are zero, for drop through cases below */
142480 +       var->transp.offset = 0;
142481 +       var->transp.length = 0;
142482 +
142483 +       switch (var->bits_per_pixel) {
142484 +       case 1:
142485 +       case 2:
142486 +       case 4:
142487 +       case 8:
142488 +               if (!s3c_fb_win_has_palette(win->index, var->bits_per_pixel)) {
142489 +                       /* non palletised, A:1,R:2,G:3,B:2 mode */
142490 +                       var->red.offset         = 4;
142491 +                       var->green.offset       = 2;
142492 +                       var->blue.offset        = 0;
142493 +                       var->red.length         = 5;
142494 +                       var->green.length       = 3;
142495 +                       var->blue.length        = 2;
142496 +                       var->transp.offset      = 7;
142497 +                       var->transp.length      = 1;
142498 +               } else {
142499 +                       var->red.offset = 0;
142500 +                       var->red.length = var->bits_per_pixel;
142501 +                       var->green      = var->red;
142502 +                       var->blue       = var->red;
142503 +               }
142504 +               break;
142505 +
142506 +       case 19:
142507 +               /* 666 with one bit alpha/transparency */
142508 +               var->transp.offset      = 18;
142509 +               var->transp.length      = 1;
142510 +       case 18:
142511 +               var->bits_per_pixel     = 32;
142512 +
142513 +               /* 666 format */
142514 +               var->red.offset         = 12;
142515 +               var->green.offset       = 6;
142516 +               var->blue.offset        = 0;
142517 +               var->red.length         = 6;
142518 +               var->green.length       = 6;
142519 +               var->blue.length        = 6;
142520 +               break;
142521 +
142522 +       case 16:
142523 +               /* 16 bpp, 565 format */
142524 +               var->red.offset         = 11;
142525 +               var->green.offset       = 5;
142526 +               var->blue.offset        = 0;
142527 +               var->red.length         = 5;
142528 +               var->green.length       = 6;
142529 +               var->blue.length        = 5;
142530 +               break;
142531 +
142532 +       case 28:
142533 +       case 25:
142534 +               var->transp.length      = var->bits_per_pixel - 24;
142535 +               var->transp.offset      = 24;
142536 +               /* drop through */
142537 +       case 24:
142538 +               /* our 24bpp is unpacked, so 32bpp */
142539 +               var->bits_per_pixel     = 32;
142540 +       case 32:
142541 +               var->red.offset         = 16;
142542 +               var->red.length         = 8;
142543 +               var->green.offset       = 8;
142544 +               var->green.length       = 8;
142545 +               var->blue.offset        = 0;
142546 +               var->blue.length        = 8;
142547 +               break;
142548 +
142549 +       default:
142550 +               dev_err(sfb->dev, "invalid bpp\n");
142551 +       }
142552 +
142553 +       dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
142554 +       return 0;
142555 +}
142556 +
142557 +/**
142558 + * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
142559 + * @sfb: The hardware state.
142560 + * @pixclock: The pixel clock wanted, in picoseconds.
142561 + *
142562 + * Given the specified pixel clock, work out the necessary divider to get
142563 + * close to the output frequency.
142564 + */
142565 +static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
142566 +{
142567 +       unsigned long clk = clk_get_rate(sfb->bus_clk);
142568 +       unsigned long long tmp;
142569 +       unsigned int result;
142570 +
142571 +       tmp = (unsigned long long)clk;
142572 +       tmp *= pixclk;
142573 +
142574 +       do_div(tmp, 1000000000UL);
142575 +       result = (unsigned int)tmp / 1000;
142576 +
142577 +       dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
142578 +               pixclk, clk, result, clk / result);
142579 +
142580 +       return result;
142581 +}
142582 +
142583 +/**
142584 + * s3c_fb_align_word() - align pixel count to word boundary
142585 + * @bpp: The number of bits per pixel
142586 + * @pix: The value to be aligned.
142587 + *
142588 + * Align the given pixel count so that it will start on an 32bit word
142589 + * boundary.
142590 + */
142591 +static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
142592 +{
142593 +       int pix_per_word;
142594 +
142595 +       if (bpp > 16)
142596 +               return pix;
142597 +
142598 +       pix_per_word = (8 * 32) / bpp;
142599 +       return ALIGN(pix, pix_per_word);
142600 +}
142601 +
142602 +/**
142603 + * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
142604 + * @info: The framebuffer to change.
142605 + *
142606 + * Framebuffer layer request to set a new mode for the specified framebuffer
142607 + */
142608 +static int s3c_fb_set_par(struct fb_info *info)
142609 +{
142610 +       struct fb_var_screeninfo *var = &info->var;
142611 +       struct s3c_fb_win *win = info->par;
142612 +       struct s3c_fb *sfb = win->parent;
142613 +       void __iomem *regs = sfb->regs;
142614 +       int win_no = win->index;
142615 +       u32 data;
142616 +       u32 pagewidth;
142617 +       int clkdiv;
142618 +
142619 +       dev_dbg(sfb->dev, "setting framebuffer parameters\n");
142620 +
142621 +       switch (var->bits_per_pixel) {
142622 +       case 32:
142623 +       case 24:
142624 +       case 16:
142625 +       case 12:
142626 +               info->fix.visual = FB_VISUAL_TRUECOLOR;
142627 +               break;
142628 +       case 8:
142629 +               if (s3c_fb_win_has_palette(win_no, 8))
142630 +                       info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
142631 +               else
142632 +                       info->fix.visual = FB_VISUAL_TRUECOLOR;
142633 +               break;
142634 +       case 1:
142635 +               info->fix.visual = FB_VISUAL_MONO01;
142636 +               break;
142637 +       default:
142638 +               info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
142639 +               break;
142640 +       }
142641 +
142642 +       info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
142643 +
142644 +       /* disable the window whilst we update it */
142645 +       writel(0, regs + WINCON(win_no));
142646 +
142647 +       /* use window 0 as the basis for the lcd output timings */
142648 +
142649 +       if (win_no == 0) {
142650 +               clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
142651 +
142652 +               data = sfb->pdata->vidcon0;
142653 +               data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
142654 +
142655 +               if (clkdiv > 1)
142656 +                       data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
142657 +               else
142658 +                       data &= ~VIDCON0_CLKDIR;        /* 1:1 clock */
142659 +
142660 +               /* write the timing data to the panel */
142661 +
142662 +               data |= VIDCON0_ENVID | VIDCON0_ENVID_F;
142663 +               writel(data, regs + VIDCON0);
142664 +
142665 +               data = VIDTCON0_VBPD(var->upper_margin - 1) |
142666 +                      VIDTCON0_VFPD(var->lower_margin - 1) |
142667 +                      VIDTCON0_VSPW(var->vsync_len - 1);
142668 +
142669 +               writel(data, regs + VIDTCON0);
142670 +
142671 +               data = VIDTCON1_HBPD(var->left_margin - 1) |
142672 +                      VIDTCON1_HFPD(var->right_margin - 1) |
142673 +                      VIDTCON1_HSPW(var->hsync_len - 1);
142674 +
142675 +               writel(data, regs + VIDTCON1);
142676 +
142677 +               data = VIDTCON2_LINEVAL(var->yres - 1) |
142678 +                      VIDTCON2_HOZVAL(var->xres - 1);
142679 +               writel(data, regs + VIDTCON2);
142680 +       }
142681 +
142682 +       /* write the buffer address */
142683 +
142684 +       writel(info->fix.smem_start, regs + VIDW_BUF_START(win_no));
142685 +
142686 +       data = info->fix.smem_start + info->fix.line_length * var->yres;
142687 +       writel(data, regs + VIDW_BUF_END(win_no));
142688 +
142689 +       pagewidth = (var->xres * var->bits_per_pixel) >> 3;
142690 +       data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
142691 +              VIDW_BUF_SIZE_PAGEWIDTH(pagewidth);
142692 +       writel(data, regs + VIDW_BUF_SIZE(win_no));
142693 +
142694 +       /* write 'OSD' registers to control position of framebuffer */
142695 +
142696 +       data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0);
142697 +       writel(data, regs + VIDOSD_A(win_no));
142698 +
142699 +       data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
142700 +                                                    var->xres - 1)) |
142701 +              VIDOSDxB_BOTRIGHT_Y(var->yres - 1);
142702 +
142703 +       writel(data, regs + VIDOSD_B(win_no));
142704 +
142705 +       data = var->xres * var->yres;
142706 +       if (s3c_fb_has_osd_d(win_no)) {
142707 +               writel(data, regs + VIDOSD_D(win_no));
142708 +               writel(0, regs + VIDOSD_C(win_no));
142709 +       } else
142710 +               writel(data, regs + VIDOSD_C(win_no));
142711 +
142712 +       data = WINCONx_ENWIN;
142713 +
142714 +       /* note, since we have to round up the bits-per-pixel, we end up
142715 +        * relying on the bitfield information for r/g/b/a to work out
142716 +        * exactly which mode of operation is intended. */
142717 +
142718 +       switch (var->bits_per_pixel) {
142719 +       case 1:
142720 +               data |= WINCON0_BPPMODE_1BPP;
142721 +               data |= WINCONx_BITSWP;
142722 +               data |= WINCONx_BURSTLEN_4WORD;
142723 +               break;
142724 +       case 2:
142725 +               data |= WINCON0_BPPMODE_2BPP;
142726 +               data |= WINCONx_BITSWP;
142727 +               data |= WINCONx_BURSTLEN_8WORD;
142728 +               break;
142729 +       case 4:
142730 +               data |= WINCON0_BPPMODE_4BPP;
142731 +               data |= WINCONx_BITSWP;
142732 +               data |= WINCONx_BURSTLEN_8WORD;
142733 +               break;
142734 +       case 8:
142735 +               if (var->transp.length != 0)
142736 +                       data |= WINCON1_BPPMODE_8BPP_1232;
142737 +               else
142738 +                       data |= WINCON0_BPPMODE_8BPP_PALETTE;
142739 +               data |= WINCONx_BURSTLEN_8WORD;
142740 +               data |= WINCONx_BYTSWP;
142741 +               break;
142742 +       case 16:
142743 +               if (var->transp.length != 0)
142744 +                       data |= WINCON1_BPPMODE_16BPP_A1555;
142745 +               else
142746 +                       data |= WINCON0_BPPMODE_16BPP_565;
142747 +               data |= WINCONx_HAWSWP;
142748 +               data |= WINCONx_BURSTLEN_16WORD;
142749 +               break;
142750 +       case 24:
142751 +       case 32:
142752 +               if (var->red.length == 6) {
142753 +                       if (var->transp.length != 0)
142754 +                               data |= WINCON1_BPPMODE_19BPP_A1666;
142755 +                       else
142756 +                               data |= WINCON1_BPPMODE_18BPP_666;
142757 +               } else if (var->transp.length != 0)
142758 +                       data |= WINCON1_BPPMODE_25BPP_A1888;
142759 +               else
142760 +                       data |= WINCON0_BPPMODE_24BPP_888;
142761 +
142762 +               data |= WINCONx_BURSTLEN_16WORD;
142763 +               break;
142764 +       }
142765 +
142766 +       writel(data, regs + WINCON(win_no));
142767 +       writel(0x0, regs + WINxMAP(win_no));
142768 +
142769 +       return 0;
142770 +}
142771 +
142772 +/**
142773 + * s3c_fb_update_palette() - set or schedule a palette update.
142774 + * @sfb: The hardware information.
142775 + * @win: The window being updated.
142776 + * @reg: The palette index being changed.
142777 + * @value: The computed palette value.
142778 + *
142779 + * Change the value of a palette register, either by directly writing to
142780 + * the palette (this requires the palette RAM to be disconnected from the
142781 + * hardware whilst this is in progress) or schedule the update for later.
142782 + *
142783 + * At the moment, since we have no VSYNC interrupt support, we simply set
142784 + * the palette entry directly.
142785 + */
142786 +static void s3c_fb_update_palette(struct s3c_fb *sfb,
142787 +                                 struct s3c_fb_win *win,
142788 +                                 unsigned int reg,
142789 +                                 u32 value)
142790 +{
142791 +       void __iomem *palreg;
142792 +       u32 palcon;
142793 +
142794 +       palreg = sfb->regs + s3c_fb_pal_reg(win->index, reg);
142795 +
142796 +       dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
142797 +               __func__, win->index, reg, palreg, value);
142798 +
142799 +       win->palette_buffer[reg] = value;
142800 +
142801 +       palcon = readl(sfb->regs + WPALCON);
142802 +       writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
142803 +
142804 +       if (s3c_fb_pal_is16(win->index))
142805 +               writew(value, palreg);
142806 +       else
142807 +               writel(value, palreg);
142808 +
142809 +       writel(palcon, sfb->regs + WPALCON);
142810 +}
142811 +
142812 +static inline unsigned int chan_to_field(unsigned int chan,
142813 +                                        struct fb_bitfield *bf)
142814 +{
142815 +       chan &= 0xffff;
142816 +       chan >>= 16 - bf->length;
142817 +       return chan << bf->offset;
142818 +}
142819 +
142820 +/**
142821 + * s3c_fb_setcolreg() - framebuffer layer request to change palette.
142822 + * @regno: The palette index to change.
142823 + * @red: The red field for the palette data.
142824 + * @green: The green field for the palette data.
142825 + * @blue: The blue field for the palette data.
142826 + * @trans: The transparency (alpha) field for the palette data.
142827 + * @info: The framebuffer being changed.
142828 + */
142829 +static int s3c_fb_setcolreg(unsigned regno,
142830 +                           unsigned red, unsigned green, unsigned blue,
142831 +                           unsigned transp, struct fb_info *info)
142832 +{
142833 +       struct s3c_fb_win *win = info->par;
142834 +       struct s3c_fb *sfb = win->parent;
142835 +       unsigned int val;
142836 +
142837 +       dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
142838 +               __func__, win->index, regno, red, green, blue);
142839 +
142840 +       switch (info->fix.visual) {
142841 +       case FB_VISUAL_TRUECOLOR:
142842 +               /* true-colour, use pseudo-palette */
142843 +
142844 +               if (regno < 16) {
142845 +                       u32 *pal = info->pseudo_palette;
142846 +
142847 +                       val  = chan_to_field(red,   &info->var.red);
142848 +                       val |= chan_to_field(green, &info->var.green);
142849 +                       val |= chan_to_field(blue,  &info->var.blue);
142850 +
142851 +                       pal[regno] = val;
142852 +               }
142853 +               break;
142854 +
142855 +       case FB_VISUAL_PSEUDOCOLOR:
142856 +               if (regno < s3c_fb_win_pal_size(win->index)) {
142857 +                       val  = chan_to_field(red, &win->palette.r);
142858 +                       val |= chan_to_field(green, &win->palette.g);
142859 +                       val |= chan_to_field(blue, &win->palette.b);
142860 +
142861 +                       s3c_fb_update_palette(sfb, win, regno, val);
142862 +               }
142863 +
142864 +               break;
142865 +
142866 +       default:
142867 +               return 1;       /* unknown type */
142868 +       }
142869 +
142870 +       return 0;
142871 +}
142872 +
142873 +/**
142874 + * s3c_fb_enable() - Set the state of the main LCD output
142875 + * @sfb: The main framebuffer state.
142876 + * @enable: The state to set.
142877 + */
142878 +static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
142879 +{
142880 +       u32 vidcon0 = readl(sfb->regs + VIDCON0);
142881 +
142882 +       if (enable)
142883 +               vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
142884 +       else {
142885 +               /* see the note in the framebuffer datasheet about
142886 +                * why you cannot take both of these bits down at the
142887 +                * same time. */
142888 +
142889 +               if (!(vidcon0 & VIDCON0_ENVID))
142890 +                       return;
142891 +
142892 +               vidcon0 |= VIDCON0_ENVID;
142893 +               vidcon0 &= ~VIDCON0_ENVID_F;
142894 +       }
142895 +
142896 +       writel(vidcon0, sfb->regs + VIDCON0);
142897 +}
142898 +
142899 +/**
142900 + * s3c_fb_blank() - blank or unblank the given window
142901 + * @blank_mode: The blank state from FB_BLANK_*
142902 + * @info: The framebuffer to blank.
142903 + *
142904 + * Framebuffer layer request to change the power state.
142905 + */
142906 +static int s3c_fb_blank(int blank_mode, struct fb_info *info)
142907 +{
142908 +       struct s3c_fb_win *win = info->par;
142909 +       struct s3c_fb *sfb = win->parent;
142910 +       unsigned int index = win->index;
142911 +       u32 wincon;
142912 +
142913 +       dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
142914 +
142915 +       wincon = readl(sfb->regs + WINCON(index));
142916 +
142917 +       switch (blank_mode) {
142918 +       case FB_BLANK_POWERDOWN:
142919 +               wincon &= ~WINCONx_ENWIN;
142920 +               sfb->enabled &= ~(1 << index);
142921 +               /* fall through to FB_BLANK_NORMAL */
142922 +
142923 +       case FB_BLANK_NORMAL:
142924 +               /* disable the DMA and display 0x0 (black) */
142925 +               writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
142926 +                      sfb->regs + WINxMAP(index));
142927 +               break;
142928 +
142929 +       case FB_BLANK_UNBLANK:
142930 +               writel(0x0, sfb->regs + WINxMAP(index));
142931 +               wincon |= WINCONx_ENWIN;
142932 +               sfb->enabled |= (1 << index);
142933 +               break;
142934 +
142935 +       case FB_BLANK_VSYNC_SUSPEND:
142936 +       case FB_BLANK_HSYNC_SUSPEND:
142937 +       default:
142938 +               return 1;
142939 +       }
142940 +
142941 +       writel(wincon, sfb->regs + WINCON(index));
142942 +
142943 +       /* Check the enabled state to see if we need to be running the
142944 +        * main LCD interface, as if there are no active windows then
142945 +        * it is highly likely that we also do not need to output
142946 +        * anything.
142947 +        */
142948 +
142949 +       /* We could do something like the following code, but the current
142950 +        * system of using framebuffer events means that we cannot make
142951 +        * the distinction between just window 0 being inactive and all
142952 +        * the windows being down.
142953 +        *
142954 +        * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
142955 +       */
142956 +
142957 +       /* we're stuck with this until we can do something about overriding
142958 +        * the power control using the blanking event for a single fb.
142959 +        */
142960 +       if (index == 0)
142961 +               s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
142962 +
142963 +       return 0;
142964 +}
142965 +
142966 +static struct fb_ops s3c_fb_ops = {
142967 +       .owner          = THIS_MODULE,
142968 +       .fb_check_var   = s3c_fb_check_var,
142969 +       .fb_set_par     = s3c_fb_set_par,
142970 +       .fb_blank       = s3c_fb_blank,
142971 +       .fb_setcolreg   = s3c_fb_setcolreg,
142972 +       .fb_fillrect    = cfb_fillrect,
142973 +       .fb_copyarea    = cfb_copyarea,
142974 +       .fb_imageblit   = cfb_imageblit,
142975 +};
142976 +
142977 +/**
142978 + * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
142979 + * @sfb: The base resources for the hardware.
142980 + * @win: The window to initialise memory for.
142981 + *
142982 + * Allocate memory for the given framebuffer.
142983 + */
142984 +static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
142985 +                                        struct s3c_fb_win *win)
142986 +{
142987 +       struct s3c_fb_pd_win *windata = win->windata;
142988 +       unsigned int real_size, virt_size, size;
142989 +       struct fb_info *fbi = win->fbinfo;
142990 +       dma_addr_t map_dma;
142991 +
142992 +       dev_dbg(sfb->dev, "allocating memory for display\n");
142993 +
142994 +       real_size = windata->win_mode.xres * windata->win_mode.yres;
142995 +       virt_size = windata->virtual_x * windata->virtual_y;
142996 +
142997 +       dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
142998 +               real_size, windata->win_mode.xres, windata->win_mode.yres,
142999 +               virt_size, windata->virtual_x, windata->virtual_y);
143000 +
143001 +       size = (real_size > virt_size) ? real_size : virt_size;
143002 +       size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
143003 +       size /= 8;
143004 +
143005 +       fbi->fix.smem_len = size;
143006 +       size = PAGE_ALIGN(size);
143007 +
143008 +       dev_dbg(sfb->dev, "want %u bytes for window\n", size);
143009 +
143010 +       fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
143011 +                                                 &map_dma, GFP_KERNEL);
143012 +       if (!fbi->screen_base)
143013 +               return -ENOMEM;
143014 +
143015 +       dev_dbg(sfb->dev, "mapped %x to %p\n",
143016 +               (unsigned int)map_dma, fbi->screen_base);
143017 +
143018 +       memset(fbi->screen_base, 0x0, size);
143019 +       fbi->fix.smem_start = map_dma;
143020 +
143021 +       return 0;
143022 +}
143023 +
143024 +/**
143025 + * s3c_fb_free_memory() - free the display memory for the given window
143026 + * @sfb: The base resources for the hardware.
143027 + * @win: The window to free the display memory for.
143028 + *
143029 + * Free the display memory allocated by s3c_fb_alloc_memory().
143030 + */
143031 +static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
143032 +{
143033 +       struct fb_info *fbi = win->fbinfo;
143034 +
143035 +       dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
143036 +                             fbi->screen_base, fbi->fix.smem_start);
143037 +}
143038 +
143039 +/**
143040 + * s3c_fb_release_win() - release resources for a framebuffer window.
143041 + * @win: The window to cleanup the resources for.
143042 + *
143043 + * Release the resources that where claimed for the hardware window,
143044 + * such as the framebuffer instance and any memory claimed for it.
143045 + */
143046 +static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
143047 +{
143048 +       fb_dealloc_cmap(&win->fbinfo->cmap);
143049 +       unregister_framebuffer(win->fbinfo);
143050 +       s3c_fb_free_memory(sfb, win);
143051 +}
143052 +
143053 +/**
143054 + * s3c_fb_probe_win() - register an hardware window
143055 + * @sfb: The base resources for the hardware
143056 + * @res: Pointer to where to place the resultant window.
143057 + *
143058 + * Allocate and do the basic initialisation for one of the hardware's graphics
143059 + * windows.
143060 + */
143061 +static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
143062 +                                     struct s3c_fb_win **res)
143063 +{
143064 +       struct fb_var_screeninfo *var;
143065 +       struct fb_videomode *initmode;
143066 +       struct s3c_fb_pd_win *windata;
143067 +       struct s3c_fb_win *win;
143068 +       struct fb_info *fbinfo;
143069 +       int palette_size;
143070 +       int ret;
143071 +
143072 +       dev_dbg(sfb->dev, "probing window %d\n", win_no);
143073 +
143074 +       palette_size = s3c_fb_win_pal_size(win_no);
143075 +
143076 +       fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
143077 +                                  palette_size * sizeof(u32), sfb->dev);
143078 +       if (!fbinfo) {
143079 +               dev_err(sfb->dev, "failed to allocate framebuffer\n");
143080 +               return -ENOENT;
143081 +       }
143082 +
143083 +       windata = sfb->pdata->win[win_no];
143084 +       initmode = &windata->win_mode;
143085 +
143086 +       WARN_ON(windata->max_bpp == 0);
143087 +       WARN_ON(windata->win_mode.xres == 0);
143088 +       WARN_ON(windata->win_mode.yres == 0);
143089 +
143090 +       win = fbinfo->par;
143091 +       var = &fbinfo->var;
143092 +       win->fbinfo = fbinfo;
143093 +       win->parent = sfb;
143094 +       win->windata = windata;
143095 +       win->index = win_no;
143096 +       win->palette_buffer = (u32 *)(win + 1);
143097 +
143098 +       ret = s3c_fb_alloc_memory(sfb, win);
143099 +       if (ret) {
143100 +               dev_err(sfb->dev, "failed to allocate display memory\n");
143101 +               goto err_framebuffer;
143102 +       }
143103 +
143104 +       /* setup the r/b/g positions for the window's palette */
143105 +       s3c_fb_init_palette(win_no, &win->palette);
143106 +
143107 +       /* setup the initial video mode from the window */
143108 +       fb_videomode_to_var(&fbinfo->var, initmode);
143109 +
143110 +       fbinfo->fix.type        = FB_TYPE_PACKED_PIXELS;
143111 +       fbinfo->fix.accel       = FB_ACCEL_NONE;
143112 +       fbinfo->var.activate    = FB_ACTIVATE_NOW;
143113 +       fbinfo->var.vmode       = FB_VMODE_NONINTERLACED;
143114 +       fbinfo->var.bits_per_pixel = windata->default_bpp;
143115 +       fbinfo->fbops           = &s3c_fb_ops;
143116 +       fbinfo->flags           = FBINFO_FLAG_DEFAULT;
143117 +       fbinfo->pseudo_palette  = &win->pseudo_palette;
143118 +
143119 +       /* prepare to actually start the framebuffer */
143120 +
143121 +       ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
143122 +       if (ret < 0) {
143123 +               dev_err(sfb->dev, "check_var failed on initial video params\n");
143124 +               goto err_alloc_mem;
143125 +       }
143126 +
143127 +       /* create initial colour map */
143128 +
143129 +       ret = fb_alloc_cmap(&fbinfo->cmap, s3c_fb_win_pal_size(win_no), 1);
143130 +       if (ret == 0)
143131 +               fb_set_cmap(&fbinfo->cmap, fbinfo);
143132 +       else
143133 +               dev_err(sfb->dev, "failed to allocate fb cmap\n");
143134 +
143135 +       s3c_fb_set_par(fbinfo);
143136 +
143137 +       dev_dbg(sfb->dev, "about to register framebuffer\n");
143138 +
143139 +       /* run the check_var and set_par on our configuration. */
143140 +
143141 +       ret = register_framebuffer(fbinfo);
143142 +       if (ret < 0) {
143143 +               dev_err(sfb->dev, "failed to register framebuffer\n");
143144 +               goto err_alloc_mem;
143145 +       }
143146 +
143147 +       *res = win;
143148 +       dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
143149 +
143150 +       return 0;
143151 +
143152 +err_alloc_mem:
143153 +       s3c_fb_free_memory(sfb, win);
143154 +
143155 +err_framebuffer:
143156 +       unregister_framebuffer(fbinfo);
143157 +       return ret;
143158 +}
143159 +
143160 +/**
143161 + * s3c_fb_clear_win() - clear hardware window registers.
143162 + * @sfb: The base resources for the hardware.
143163 + * @win: The window to process.
143164 + *
143165 + * Reset the specific window registers to a known state.
143166 + */
143167 +static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
143168 +{
143169 +       void __iomem *regs = sfb->regs;
143170 +
143171 +       writel(0, regs + WINCON(win));
143172 +       writel(0xffffff, regs + WxKEYCONy(win, 0));
143173 +       writel(0xffffff, regs + WxKEYCONy(win, 1));
143174 +
143175 +       writel(0, regs + VIDOSD_A(win));
143176 +       writel(0, regs + VIDOSD_B(win));
143177 +       writel(0, regs + VIDOSD_C(win));
143178 +}
143179 +
143180 +static int __devinit s3c_fb_probe(struct platform_device *pdev)
143181 +{
143182 +       struct device *dev = &pdev->dev;
143183 +       struct s3c_fb_platdata *pd;
143184 +       struct s3c_fb *sfb;
143185 +       struct resource *res;
143186 +       int win;
143187 +       int ret = 0;
143188 +
143189 +       pd = pdev->dev.platform_data;
143190 +       if (!pd) {
143191 +               dev_err(dev, "no platform data specified\n");
143192 +               return -EINVAL;
143193 +       }
143194 +
143195 +       sfb = kzalloc(sizeof(struct s3c_fb), GFP_KERNEL);
143196 +       if (!sfb) {
143197 +               dev_err(dev, "no memory for framebuffers\n");
143198 +               return -ENOMEM;
143199 +       }
143200 +
143201 +       sfb->dev = dev;
143202 +       sfb->pdata = pd;
143203 +
143204 +       sfb->bus_clk = clk_get(dev, "lcd");
143205 +       if (IS_ERR(sfb->bus_clk)) {
143206 +               dev_err(dev, "failed to get bus clock\n");
143207 +               goto err_sfb;
143208 +       }
143209 +
143210 +       clk_enable(sfb->bus_clk);
143211 +
143212 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
143213 +       if (!res) {
143214 +               dev_err(dev, "failed to find registers\n");
143215 +               ret = -ENOENT;
143216 +               goto err_clk;
143217 +       }
143218 +
143219 +       sfb->regs_res = request_mem_region(res->start, resource_size(res),
143220 +                                          dev_name(dev));
143221 +       if (!sfb->regs_res) {
143222 +               dev_err(dev, "failed to claim register region\n");
143223 +               ret = -ENOENT;
143224 +               goto err_clk;
143225 +       }
143226 +
143227 +       sfb->regs = ioremap(res->start, resource_size(res));
143228 +       if (!sfb->regs) {
143229 +               dev_err(dev, "failed to map registers\n");
143230 +               ret = -ENXIO;
143231 +               goto err_req_region;
143232 +       }
143233 +
143234 +       dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
143235 +
143236 +       /* setup gpio and output polarity controls */
143237 +
143238 +       pd->setup_gpio();
143239 +
143240 +       writel(pd->vidcon1, sfb->regs + VIDCON1);
143241 +
143242 +       /* zero all windows before we do anything */
143243 +
143244 +       for (win = 0; win < S3C_FB_MAX_WIN; win++)
143245 +               s3c_fb_clear_win(sfb, win);
143246 +
143247 +       /* we have the register setup, start allocating framebuffers */
143248 +
143249 +       for (win = 0; win < S3C_FB_MAX_WIN; win++) {
143250 +               if (!pd->win[win])
143251 +                       continue;
143252 +
143253 +               ret = s3c_fb_probe_win(sfb, win, &sfb->windows[win]);
143254 +               if (ret < 0) {
143255 +                       dev_err(dev, "failed to create window %d\n", win);
143256 +                       for (; win >= 0; win--)
143257 +                               s3c_fb_release_win(sfb, sfb->windows[win]);
143258 +                       goto err_ioremap;
143259 +               }
143260 +       }
143261 +
143262 +       platform_set_drvdata(pdev, sfb);
143263 +
143264 +       return 0;
143265 +
143266 +err_ioremap:
143267 +       iounmap(sfb->regs);
143268 +
143269 +err_req_region:
143270 +       release_resource(sfb->regs_res);
143271 +       kfree(sfb->regs_res);
143272 +
143273 +err_clk:
143274 +       clk_disable(sfb->bus_clk);
143275 +       clk_put(sfb->bus_clk);
143276 +
143277 +err_sfb:
143278 +       kfree(sfb);
143279 +       return ret;
143280 +}
143281 +
143282 +/**
143283 + * s3c_fb_remove() - Cleanup on module finalisation
143284 + * @pdev: The platform device we are bound to.
143285 + *
143286 + * Shutdown and then release all the resources that the driver allocated
143287 + * on initialisation.
143288 + */
143289 +static int __devexit s3c_fb_remove(struct platform_device *pdev)
143290 +{
143291 +       struct s3c_fb *sfb = platform_get_drvdata(pdev);
143292 +       int win;
143293 +
143294 +       for (win = 0; win <= S3C_FB_MAX_WIN; win++)
143295 +               s3c_fb_release_win(sfb, sfb->windows[win]);
143296 +
143297 +       iounmap(sfb->regs);
143298 +
143299 +       clk_disable(sfb->bus_clk);
143300 +       clk_put(sfb->bus_clk);
143301 +
143302 +       release_resource(sfb->regs_res);
143303 +       kfree(sfb->regs_res);
143304 +
143305 +       kfree(sfb);
143306 +
143307 +       return 0;
143308 +}
143309 +
143310 +#ifdef CONFIG_PM
143311 +static int s3c_fb_suspend(struct platform_device *pdev, pm_message_t state)
143312 +{
143313 +       struct s3c_fb *sfb = platform_get_drvdata(pdev);
143314 +       struct s3c_fb_win *win;
143315 +       int win_no;
143316 +
143317 +       for (win_no = S3C_FB_MAX_WIN; win_no >= 0; win_no--) {
143318 +               win = sfb->windows[win_no];
143319 +               if (!win)
143320 +                       continue;
143321 +
143322 +               /* use the blank function to push into power-down */
143323 +               s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
143324 +       }
143325 +
143326 +       clk_disable(sfb->bus_clk);
143327 +       return 0;
143328 +}
143329 +
143330 +static int s3c_fb_resume(struct platform_device *pdev)
143331 +{
143332 +       struct s3c_fb *sfb = platform_get_drvdata(pdev);
143333 +       struct s3c_fb_win *win;
143334 +       int win_no;
143335 +
143336 +       clk_enable(sfb->bus_clk);
143337 +
143338 +       for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
143339 +               win = sfb->windows[win_no];
143340 +               if (!win)
143341 +                       continue;
143342 +
143343 +               dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
143344 +               s3c_fb_set_par(win->fbinfo);
143345 +       }
143346 +
143347 +       return 0;
143348 +}
143349 +#else
143350 +#define s3c_fb_suspend NULL
143351 +#define s3c_fb_resume  NULL
143352 +#endif
143353 +
143354 +static struct platform_driver s3c_fb_driver = {
143355 +       .probe          = s3c_fb_probe,
143356 +       .remove         = s3c_fb_remove,
143357 +       .suspend        = s3c_fb_suspend,
143358 +       .resume         = s3c_fb_resume,
143359 +       .driver         = {
143360 +               .name   = "s3c-fb",
143361 +               .owner  = THIS_MODULE,
143362 +       },
143363 +};
143364 +
143365 +static int __init s3c_fb_init(void)
143366 +{
143367 +       return platform_driver_register(&s3c_fb_driver);
143368 +}
143369 +
143370 +static void __exit s3c_fb_cleanup(void)
143371 +{
143372 +       platform_driver_unregister(&s3c_fb_driver);
143373 +}
143374 +
143375 +module_init(s3c_fb_init);
143376 +module_exit(s3c_fb_cleanup);
143377 +
143378 +MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
143379 +MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
143380 +MODULE_LICENSE("GPL");
143381 +MODULE_ALIAS("platform:s3c-fb");
143382 --- a/drivers/watchdog/Kconfig
143383 +++ b/drivers/watchdog/Kconfig
143384 @@ -233,6 +233,12 @@ config ORION5X_WATCHDOG
143385           To compile this driver as a module, choose M here: the
143386           module will be called orion5x_wdt.
143387
143388 +config PCF50606_WATCHDOG
143389 +       tristate "NXP PCF50606 Watchdog"
143390 +       depends on MFD_PCF50606
143391 +       help
143392 +        Say Y here to include support for NXP PCF50606 watchdog timer.
143393 +
143394  # ARM26 Architecture
143395
143396  # AVR32 Architecture
143397 @@ -784,7 +790,7 @@ config WATCHDOG_RTAS
143398         tristate "RTAS watchdog"
143399         depends on PPC_RTAS
143400         help
143401 -         This driver adds watchdog support for the RTAS watchdog.
143402 +         his driver adds watchdog support for the RTAS watchdog.
143403
143404           To compile this driver as a module, choose M here. The module
143405           will be called wdrtas.
143406 --- a/drivers/watchdog/Makefile
143407 +++ b/drivers/watchdog/Makefile
143408 @@ -41,6 +41,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx400
143409  obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
143410  obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
143411  obj-$(CONFIG_ORION5X_WATCHDOG) += orion5x_wdt.o
143412 +obj-$(CONFIG_PCF50606_WATCHDOG) += pcf50606_wdt.o
143413
143414  # ARM26 Architecture
143415
143416 --- /dev/null
143417 +++ b/drivers/watchdog/pcf50606_wdt.c
143418 @@ -0,0 +1,213 @@
143419 +/* Philips PCF50606 Watchdog Timer Driver
143420 + *
143421 + * (C) 2006-2008 by Openmoko, Inc.
143422 + * Author: Balaji Rao <balajirrao@openmoko.org>
143423 + * All rights reserved.
143424 + *
143425 + * Broken down from monstrous PCF50606 driver mainly by
143426 + * Harald Welte, Matt Hsu, Andy Green and Werner Almesberger
143427 + *
143428 + * This program is free software; you can redistribute it and/or
143429 + * modify it under the terms of the GNU General Public License as
143430 + * published by the Free Software Foundation; either version 2 of
143431 + * the License, or (at your option) any later version.
143432 + *
143433 + * This program is distributed in the hope that it will be useful,
143434 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
143435 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
143436 + * GNU General Public License for more details.
143437 + *
143438 + * You should have received a copy of the GNU General Public License
143439 + * along with this program; if not, write to the Free Software
143440 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
143441 + * MA 02111-1307 USA
143442 + */
143443 +
143444 +#include <linux/miscdevice.h>
143445 +#include <linux/watchdog.h>
143446 +
143447 +#include <linux/mfd/pcf50606/core.h>
143448 +#include <linux/mfd/pcf50606/wdt.h>
143449 +
143450 +static struct pcf50606 *pcf;
143451 +static unsigned long wdt_status;
143452 +#define WDT_IN_USE        0
143453 +#define WDT_OK_TO_CLOSE   1
143454 +#define WDT_REGION_INITED 2
143455 +#define WDT_DEVICE_INITED 3
143456 +
143457 +static int allow_close;
143458 +#define CLOSE_STATE_NOT                0x0000
143459 +#define CLOSE_STATE_ALLOW      0x2342
143460 +
143461 +static void pcf50606_wdt_start(void)
143462 +{
143463 +       pcf50606_reg_set_bit_mask(pcf, PCF50606_REG_OOCC1, PCF50606_OOCC1_WDTRST,
143464 +                        PCF50606_OOCC1_WDTRST);
143465 +}
143466 +
143467 +static void pcf50606_wdt_stop(void)
143468 +{
143469 +       pcf50606_reg_clear_bits(pcf, PCF50606_REG_OOCS, PCF50606_OOCS_WDTEXP);
143470 +}
143471 +
143472 +static void pcf50606_wdt_keepalive(void)
143473 +{
143474 +       pcf50606_wdt_start();
143475 +}
143476 +
143477 +static int pcf50606_wdt_open(struct inode *inode, struct file *file)
143478 +{
143479 +       if (test_and_set_bit(WDT_IN_USE, &wdt_status))
143480 +               return -EBUSY;
143481 +
143482 +       pcf50606_wdt_start();
143483 +
143484 +       return nonseekable_open(inode, file);
143485 +}
143486 +
143487 +static int pcf50606_wdt_release(struct inode *inode, struct file *file)
143488 +{
143489 +       if (allow_close == CLOSE_STATE_ALLOW)
143490 +               pcf50606_wdt_stop();
143491 +       else {
143492 +               printk(KERN_CRIT "Unexpected close, not stopping watchdog!\n");
143493 +               pcf50606_wdt_keepalive();
143494 +       }
143495 +
143496 +       allow_close = CLOSE_STATE_NOT;
143497 +       clear_bit(WDT_IN_USE, &wdt_status);
143498 +
143499 +       return 0;
143500 +}
143501 +
143502 +static ssize_t pcf50606_wdt_write(struct file *file, const char __user *data,
143503 +                                 size_t len, loff_t *ppos)
143504 +{
143505 +       if (len) {
143506 +               size_t i;
143507 +
143508 +               for (i = 0; i != len; i++) {
143509 +                       char c;
143510 +                       if (get_user(c, data + i))
143511 +                               return -EFAULT;
143512 +                       if (c == 'V')
143513 +                               allow_close = CLOSE_STATE_ALLOW;
143514 +               }
143515 +               pcf50606_wdt_keepalive();
143516 +       }
143517 +
143518 +       return len;
143519 +}
143520 +
143521 +static struct watchdog_info pcf50606_wdt_ident = {
143522 +       .options        = WDIOF_MAGICCLOSE,
143523 +       .firmware_version = 0,
143524 +       .identity       = "PCF50606 Watchdog",
143525 +};
143526 +
143527 +static int pcf50606_wdt_ioctl(struct inode *inode, struct file *file,
143528 +                             unsigned int cmd, unsigned long arg)
143529 +{
143530 +       void __user *argp = (void __user *)arg;
143531 +       int __user *p = argp;
143532 +
143533 +       switch (cmd) {
143534 +       case WDIOC_GETSUPPORT:
143535 +               return copy_to_user(argp, &pcf50606_wdt_ident,
143536 +                                   sizeof(pcf50606_wdt_ident)) ? -EFAULT : 0;
143537 +               break;
143538 +       case WDIOC_GETSTATUS:
143539 +       case WDIOC_GETBOOTSTATUS:
143540 +               return put_user(0, p);
143541 +       case WDIOC_KEEPALIVE:
143542 +               pcf50606_wdt_keepalive();
143543 +               return 0;
143544 +       case WDIOC_GETTIMEOUT:
143545 +               return put_user(8, p);
143546 +       default:
143547 +               return -ENOIOCTLCMD;
143548 +       }
143549 +}
143550 +
143551 +static struct file_operations pcf50606_wdt_fops = {
143552 +       .owner          = THIS_MODULE,
143553 +       .llseek         = no_llseek,
143554 +       .write          = &pcf50606_wdt_write,
143555 +       .ioctl          = &pcf50606_wdt_ioctl,
143556 +       .open           = &pcf50606_wdt_open,
143557 +       .release        = &pcf50606_wdt_release,
143558 +};
143559 +
143560 +static struct miscdevice pcf50606_wdt_miscdev = {
143561 +       .minor          = WATCHDOG_MINOR,
143562 +       .name           = "watchdog",
143563 +       .fops           = &pcf50606_wdt_fops,
143564 +};
143565 +
143566 +static void pcf50606_wdt_irq(struct pcf50606 *pcf, int irq, void *unused)
143567 +{
143568 +       pcf50606_reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
143569 +                                PCF50606_OOCC1_WDTRST,
143570 +                                PCF50606_OOCC1_WDTRST);
143571 +}
143572 +
143573 +int __init pcf50606_wdt_probe(struct platform_device *pdev)
143574 +{
143575 +       struct pcf50606 *pcf;
143576 +       int err;
143577 +
143578 +       pcf = platform_get_drvdata(pdev);
143579 +
143580 +       err = misc_register(&pcf50606_wdt_miscdev);
143581 +       if (err) {
143582 +               dev_err(&pdev->dev, "cannot register miscdev on "
143583 +                      "minor=%d (%d)\n", WATCHDOG_MINOR, err);
143584 +               return err;
143585 +       }
143586 +       set_bit(WDT_DEVICE_INITED, &wdt_status);
143587 +
143588 +       /* Set up IRQ handlers */
143589 +       pcf->irq_handler[PCF50606_IRQ_CHGWD10S].handler = pcf50606_wdt_irq;
143590 +
143591 +       return 0;
143592 +}
143593 +
143594 +static int __devexit pcf50606_wdt_remove(struct platform_device *pdev)
143595 +{
143596 +       struct pcf50606 *pcf;
143597 +
143598 +       pcf = platform_get_drvdata(pdev);
143599 +
143600 +       misc_deregister(&pcf50606_wdt_miscdev);
143601 +
143602 +       pcf->irq_handler[PCF50606_IRQ_CHGWD10S].handler = NULL;
143603 +
143604 +       return 0;
143605 +}
143606 +
143607 +struct platform_driver pcf50606_wdt_driver = {
143608 +       .driver = {
143609 +               .name = "pcf50606-wdt",
143610 +       },
143611 +       .probe = pcf50606_wdt_probe,
143612 +       .remove = __devexit_p(pcf50606_wdt_remove),
143613 +};
143614 +
143615 +static int __init pcf50606_wdt_init(void)
143616 +{
143617 +               return platform_driver_register(&pcf50606_wdt_driver);
143618 +}
143619 +module_init(pcf50606_wdt_init);
143620 +
143621 +static void __exit pcf50606_wdt_exit(void)
143622 +{
143623 +               platform_driver_unregister(&pcf50606_wdt_driver);
143624 +}
143625 +module_exit(pcf50606_wdt_exit);
143626 +
143627 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
143628 +MODULE_DESCRIPTION("PCF50606 wdt driver");
143629 +MODULE_LICENSE("GPL");
143630 +MODULE_ALIAS("platform:pcf50606-wdt");
143631 +
143632 --- a/drivers/watchdog/s3c2410_wdt.c
143633 +++ b/drivers/watchdog/s3c2410_wdt.c
143634 @@ -42,7 +42,7 @@
143635  #undef S3C_VA_WATCHDOG
143636  #define S3C_VA_WATCHDOG (0)
143637
143638 -#include <asm/plat-s3c/regs-watchdog.h>
143639 +#include <plat/regs-watchdog.h>
143640
143641  #define PFX "s3c2410-wdt: "
143642
143643 --- a/fs/jffs2/background.c
143644 +++ b/fs/jffs2/background.c
143645 @@ -95,13 +95,17 @@ static int jffs2_garbage_collect_thread(
143646                         spin_unlock(&c->erase_completion_lock);
143647
143648
143649 -               /* This thread is purely an optimisation. But if it runs when
143650 -                  other things could be running, it actually makes things a
143651 -                  lot worse. Use yield() and put it at the back of the runqueue
143652 -                  every time. Especially during boot, pulling an inode in
143653 -                  with read_inode() is much preferable to having the GC thread
143654 -                  get there first. */
143655 -               yield();
143656 +               /* Problem - immediately after bootup, the GCD spends a lot
143657 +                * of time in places like jffs2_kill_fragtree(); so much so
143658 +                * that userspace processes (like gdm and X) are starved
143659 +                * despite plenty of cond_resched()s and renicing.  Yield()
143660 +                * doesn't help, either (presumably because userspace and GCD
143661 +                * are generally competing for a higher latency resource -
143662 +                * disk).
143663 +                * This forces the GCD to slow the hell down.   Pulling an
143664 +                * inode in with read_inode() is much preferable to having
143665 +                * the GC thread get there first. */
143666 +               schedule_timeout_interruptible(msecs_to_jiffies(50));
143667
143668                 /* Put_super will send a SIGKILL and then wait on the sem.
143669                  */
143670 --- a/include/asm-arm/plat-s3c/iic.h
143671 +++ /dev/null
143672 @@ -1,33 +0,0 @@
143673 -/* arch/arm/mach-s3c2410/include/mach/iic.h
143674 - *
143675 - * Copyright (c) 2004 Simtec Electronics
143676 - *     Ben Dooks <ben@simtec.co.uk>
143677 - *
143678 - * S3C2410 - I2C Controller platfrom_device info
143679 - *
143680 - * This program is free software; you can redistribute it and/or modify
143681 - * it under the terms of the GNU General Public License version 2 as
143682 - * published by the Free Software Foundation.
143683 -*/
143684 -
143685 -#ifndef __ASM_ARCH_IIC_H
143686 -#define __ASM_ARCH_IIC_H __FILE__
143687 -
143688 -#define S3C_IICFLG_FILTER      (1<<0)  /* enable s3c2440 filter */
143689 -
143690 -/* Notes:
143691 - *     1) All frequencies are expressed in Hz
143692 - *     2) A value of zero is `do not care`
143693 -*/
143694 -
143695 -struct s3c2410_platform_i2c {
143696 -       int             bus_num;        /* bus number to use */
143697 -       unsigned int    flags;
143698 -       unsigned int    slave_addr;     /* slave address for controller */
143699 -       unsigned long   bus_freq;       /* standard bus frequency */
143700 -       unsigned long   max_freq;       /* max frequency for the bus */
143701 -       unsigned long   min_freq;       /* min frequency for the bus */
143702 -       unsigned int    sda_delay;      /* pclks (s3c2440 only) */
143703 -};
143704 -
143705 -#endif /* __ASM_ARCH_IIC_H */
143706 --- a/include/asm-arm/plat-s3c/nand.h
143707 +++ /dev/null
143708 @@ -1,50 +0,0 @@
143709 -/* arch/arm/mach-s3c2410/include/mach/nand.h
143710 - *
143711 - * Copyright (c) 2004 Simtec Electronics
143712 - *     Ben Dooks <ben@simtec.co.uk>
143713 - *
143714 - * S3C2410 - NAND device controller platfrom_device info
143715 - *
143716 - * This program is free software; you can redistribute it and/or modify
143717 - * it under the terms of the GNU General Public License version 2 as
143718 - * published by the Free Software Foundation.
143719 -*/
143720 -
143721 -/* struct s3c2410_nand_set
143722 - *
143723 - * define an set of one or more nand chips registered with an unique mtd
143724 - *
143725 - * nr_chips     = number of chips in this set
143726 - * nr_partitions = number of partitions pointed to be partitoons (or zero)
143727 - * name                 = name of set (optional)
143728 - * nr_map       = map for low-layer logical to physical chip numbers (option)
143729 - * partitions   = mtd partition list
143730 -*/
143731 -
143732 -struct s3c2410_nand_set {
143733 -       unsigned int            disable_ecc : 1;
143734 -
143735 -       int                     nr_chips;
143736 -       int                     nr_partitions;
143737 -       char                    *name;
143738 -       int                     *nr_map;
143739 -       struct mtd_partition    *partitions;
143740 -       struct nand_ecclayout   *ecc_layout;
143741 -};
143742 -
143743 -struct s3c2410_platform_nand {
143744 -       /* timing information for controller, all times in nanoseconds */
143745 -
143746 -       int     tacls;  /* time for active CLE/ALE to nWE/nOE */
143747 -       int     twrph0; /* active time for nWE/nOE */
143748 -       int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
143749 -
143750 -       unsigned int    ignore_unset_ecc : 1;
143751 -
143752 -       int                     nr_sets;
143753 -       struct s3c2410_nand_set *sets;
143754 -
143755 -       void                    (*select_chip)(struct s3c2410_nand_set *,
143756 -                                              int chip);
143757 -};
143758 -
143759 --- a/include/asm-arm/plat-s3c/regs-ac97.h
143760 +++ /dev/null
143761 @@ -1,67 +0,0 @@
143762 -/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
143763 - *
143764 - * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
143765 - *             http://www.simtec.co.uk/products/SWLINUX/
143766 - *
143767 - * This program is free software; you can redistribute it and/or modify
143768 - * it under the terms of the GNU General Public License version 2 as
143769 - * published by the Free Software Foundation.
143770 - *
143771 - * S3C2440 AC97 Controller
143772 -*/
143773 -
143774 -#ifndef __ASM_ARCH_REGS_AC97_H
143775 -#define __ASM_ARCH_REGS_AC97_H __FILE__
143776 -
143777 -#define S3C_AC97_GLBCTRL                               (0x00)
143778 -
143779 -#define S3C_AC97_GLBCTRL_CODECREADYIE                  (1<<22)
143780 -#define S3C_AC97_GLBCTRL_PCMOUTURIE                    (1<<21)
143781 -#define S3C_AC97_GLBCTRL_PCMINORIE                     (1<<20)
143782 -#define S3C_AC97_GLBCTRL_MICINORIE                     (1<<19)
143783 -#define S3C_AC97_GLBCTRL_PCMOUTTIE                     (1<<18)
143784 -#define S3C_AC97_GLBCTRL_PCMINTIE                      (1<<17)
143785 -#define S3C_AC97_GLBCTRL_MICINTIE                      (1<<16)
143786 -#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF                  (0<<12)
143787 -#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO                  (1<<12)
143788 -#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA                  (2<<12)
143789 -#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK                 (3<<12)
143790 -#define S3C_AC97_GLBCTRL_PCMINTM_OFF                   (0<<10)
143791 -#define S3C_AC97_GLBCTRL_PCMINTM_PIO                   (1<<10)
143792 -#define S3C_AC97_GLBCTRL_PCMINTM_DMA                   (2<<10)
143793 -#define S3C_AC97_GLBCTRL_PCMINTM_MASK                  (3<<10)
143794 -#define S3C_AC97_GLBCTRL_MICINTM_OFF                   (0<<8)
143795 -#define S3C_AC97_GLBCTRL_MICINTM_PIO                   (1<<8)
143796 -#define S3C_AC97_GLBCTRL_MICINTM_DMA                   (2<<8)
143797 -#define S3C_AC97_GLBCTRL_MICINTM_MASK                  (3<<8)
143798 -#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE            (1<<3)
143799 -#define S3C_AC97_GLBCTRL_ACLINKON                      (1<<2)
143800 -#define S3C_AC97_GLBCTRL_WARMRESET                     (1<<1)
143801 -#define S3C_AC97_GLBCTRL_COLDRESET                     (1<<0)
143802 -
143803 -#define S3C_AC97_GLBSTAT                               (0x04)
143804 -
143805 -#define S3C_AC97_GLBSTAT_CODECREADY                    (1<<22)
143806 -#define S3C_AC97_GLBSTAT_PCMOUTUR                      (1<<21)
143807 -#define S3C_AC97_GLBSTAT_PCMINORI                      (1<<20)
143808 -#define S3C_AC97_GLBSTAT_MICINORI                      (1<<19)
143809 -#define S3C_AC97_GLBSTAT_PCMOUTTI                      (1<<18)
143810 -#define S3C_AC97_GLBSTAT_PCMINTI                       (1<<17)
143811 -#define S3C_AC97_GLBSTAT_MICINTI                       (1<<16)
143812 -#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE                        (0<<0)
143813 -#define S3C_AC97_GLBSTAT_MAINSTATE_INIT                        (1<<0)
143814 -#define S3C_AC97_GLBSTAT_MAINSTATE_READY               (2<<0)
143815 -#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE              (3<<0)
143816 -#define S3C_AC97_GLBSTAT_MAINSTATE_LP                  (4<<0)
143817 -#define S3C_AC97_GLBSTAT_MAINSTATE_WARM                        (5<<0)
143818 -
143819 -#define S3C_AC97_CODEC_CMD                             (0x08)
143820 -
143821 -#define S3C_AC97_CODEC_CMD_READ                                (1<<23)
143822 -
143823 -#define S3C_AC97_STAT                                  (0x0c)
143824 -#define S3C_AC97_PCM_ADDR                              (0x10)
143825 -#define S3C_AC97_PCM_DATA                              (0x18)
143826 -#define S3C_AC97_MIC_DATA                              (0x1C)
143827 -
143828 -#endif /* __ASM_ARCH_REGS_AC97_H */
143829 --- a/include/asm-arm/plat-s3c/regs-iic.h
143830 +++ /dev/null
143831 @@ -1,56 +0,0 @@
143832 -/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
143833 - *
143834 - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
143835 - *             http://www.simtec.co.uk/products/SWLINUX/
143836 - *
143837 - * This program is free software; you can redistribute it and/or modify
143838 - * it under the terms of the GNU General Public License version 2 as
143839 - * published by the Free Software Foundation.
143840 - *
143841 - * S3C2410 I2C Controller
143842 -*/
143843 -
143844 -#ifndef __ASM_ARCH_REGS_IIC_H
143845 -#define __ASM_ARCH_REGS_IIC_H __FILE__
143846 -
143847 -/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
143848 -
143849 -#define S3C2410_IICREG(x) (x)
143850 -
143851 -#define S3C2410_IICCON    S3C2410_IICREG(0x00)
143852 -#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
143853 -#define S3C2410_IICADD    S3C2410_IICREG(0x08)
143854 -#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
143855 -#define S3C2440_IICLC    S3C2410_IICREG(0x10)
143856 -
143857 -#define S3C2410_IICCON_ACKEN           (1<<7)
143858 -#define S3C2410_IICCON_TXDIV_16                (0<<6)
143859 -#define S3C2410_IICCON_TXDIV_512       (1<<6)
143860 -#define S3C2410_IICCON_IRQEN           (1<<5)
143861 -#define S3C2410_IICCON_IRQPEND         (1<<4)
143862 -#define S3C2410_IICCON_SCALE(x)                ((x)&15)
143863 -#define S3C2410_IICCON_SCALEMASK       (0xf)
143864 -
143865 -#define S3C2410_IICSTAT_MASTER_RX      (2<<6)
143866 -#define S3C2410_IICSTAT_MASTER_TX      (3<<6)
143867 -#define S3C2410_IICSTAT_SLAVE_RX       (0<<6)
143868 -#define S3C2410_IICSTAT_SLAVE_TX       (1<<6)
143869 -#define S3C2410_IICSTAT_MODEMASK       (3<<6)
143870 -
143871 -#define S3C2410_IICSTAT_START          (1<<5)
143872 -#define S3C2410_IICSTAT_BUSBUSY                (1<<5)
143873 -#define S3C2410_IICSTAT_TXRXEN         (1<<4)
143874 -#define S3C2410_IICSTAT_ARBITR         (1<<3)
143875 -#define S3C2410_IICSTAT_ASSLAVE                (1<<2)
143876 -#define S3C2410_IICSTAT_ADDR0          (1<<1)
143877 -#define S3C2410_IICSTAT_LASTBIT                (1<<0)
143878 -
143879 -#define S3C2410_IICLC_SDA_DELAY0       (0 << 0)
143880 -#define S3C2410_IICLC_SDA_DELAY5       (1 << 0)
143881 -#define S3C2410_IICLC_SDA_DELAY10      (2 << 0)
143882 -#define S3C2410_IICLC_SDA_DELAY15      (3 << 0)
143883 -#define S3C2410_IICLC_SDA_DELAY_MASK   (3 << 0)
143884 -
143885 -#define S3C2410_IICLC_FILTER_ON                (1<<2)
143886 -
143887 -#endif /* __ASM_ARCH_REGS_IIC_H */
143888 --- a/include/asm-arm/plat-s3c/regs-nand.h
143889 +++ /dev/null
143890 @@ -1,123 +0,0 @@
143891 -/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
143892 - *
143893 - * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
143894 - *                   http://www.simtec.co.uk/products/SWLINUX/
143895 - *
143896 - * This program is free software; you can redistribute it and/or modify
143897 - * it under the terms of the GNU General Public License version 2 as
143898 - * published by the Free Software Foundation.
143899 - *
143900 - * S3C2410 NAND register definitions
143901 -*/
143902 -
143903 -#ifndef __ASM_ARM_REGS_NAND
143904 -#define __ASM_ARM_REGS_NAND
143905 -
143906 -
143907 -#define S3C2410_NFREG(x) (x)
143908 -
143909 -#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
143910 -#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
143911 -#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
143912 -#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
143913 -#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
143914 -#define S3C2410_NFECC   S3C2410_NFREG(0x14)
143915 -
143916 -#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
143917 -#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
143918 -#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
143919 -#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
143920 -#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
143921 -#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
143922 -#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
143923 -#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
143924 -#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
143925 -#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
143926 -#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
143927 -#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
143928 -#define S3C2440_NFSECC   S3C2410_NFREG(0x34)
143929 -#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
143930 -#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
143931 -
143932 -#define S3C2412_NFSBLK         S3C2410_NFREG(0x20)
143933 -#define S3C2412_NFEBLK         S3C2410_NFREG(0x24)
143934 -#define S3C2412_NFSTAT         S3C2410_NFREG(0x28)
143935 -#define S3C2412_NFMECC_ERR0    S3C2410_NFREG(0x2C)
143936 -#define S3C2412_NFMECC_ERR1    S3C2410_NFREG(0x30)
143937 -#define S3C2412_NFMECC0                S3C2410_NFREG(0x34)
143938 -#define S3C2412_NFMECC1                S3C2410_NFREG(0x38)
143939 -#define S3C2412_NFSECC         S3C2410_NFREG(0x3C)
143940 -
143941 -#define S3C2410_NFCONF_EN          (1<<15)
143942 -#define S3C2410_NFCONF_512BYTE     (1<<14)
143943 -#define S3C2410_NFCONF_4STEP       (1<<13)
143944 -#define S3C2410_NFCONF_INITECC     (1<<12)
143945 -#define S3C2410_NFCONF_nFCE        (1<<11)
143946 -#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
143947 -#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
143948 -#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
143949 -
143950 -#define S3C2410_NFSTAT_BUSY        (1<<0)
143951 -
143952 -#define S3C2440_NFCONF_BUSWIDTH_8      (0<<0)
143953 -#define S3C2440_NFCONF_BUSWIDTH_16     (1<<0)
143954 -#define S3C2440_NFCONF_ADVFLASH                (1<<3)
143955 -#define S3C2440_NFCONF_TACLS(x)                ((x)<<12)
143956 -#define S3C2440_NFCONF_TWRPH0(x)       ((x)<<8)
143957 -#define S3C2440_NFCONF_TWRPH1(x)       ((x)<<4)
143958 -
143959 -#define S3C2440_NFCONT_LOCKTIGHT       (1<<13)
143960 -#define S3C2440_NFCONT_SOFTLOCK                (1<<12)
143961 -#define S3C2440_NFCONT_ILLEGALACC_EN   (1<<10)
143962 -#define S3C2440_NFCONT_RNBINT_EN       (1<<9)
143963 -#define S3C2440_NFCONT_RN_FALLING      (1<<8)
143964 -#define S3C2440_NFCONT_SPARE_ECCLOCK   (1<<6)
143965 -#define S3C2440_NFCONT_MAIN_ECCLOCK    (1<<5)
143966 -#define S3C2440_NFCONT_INITECC         (1<<4)
143967 -#define S3C2440_NFCONT_nFCE            (1<<1)
143968 -#define S3C2440_NFCONT_ENABLE          (1<<0)
143969 -
143970 -#define S3C2440_NFSTAT_READY           (1<<0)
143971 -#define S3C2440_NFSTAT_nCE             (1<<1)
143972 -#define S3C2440_NFSTAT_RnB_CHANGE      (1<<2)
143973 -#define S3C2440_NFSTAT_ILLEGAL_ACCESS  (1<<3)
143974 -
143975 -#define S3C2412_NFCONF_NANDBOOT                (1<<31)
143976 -#define S3C2412_NFCONF_ECCCLKCON       (1<<30)
143977 -#define S3C2412_NFCONF_ECC_MLC         (1<<24)
143978 -#define S3C2412_NFCONF_TACLS_MASK      (7<<12) /* 1 extra bit of Tacls */
143979 -
143980 -#define S3C2412_NFCONT_ECC4_DIRWR      (1<<18)
143981 -#define S3C2412_NFCONT_LOCKTIGHT       (1<<17)
143982 -#define S3C2412_NFCONT_SOFTLOCK                (1<<16)
143983 -#define S3C2412_NFCONT_ECC4_ENCINT     (1<<13)
143984 -#define S3C2412_NFCONT_ECC4_DECINT     (1<<12)
143985 -#define S3C2412_NFCONT_MAIN_ECC_LOCK   (1<<7)
143986 -#define S3C2412_NFCONT_INIT_MAIN_ECC   (1<<5)
143987 -#define S3C2412_NFCONT_nFCE1           (1<<2)
143988 -#define S3C2412_NFCONT_nFCE0           (1<<1)
143989 -
143990 -#define S3C2412_NFSTAT_ECC_ENCDONE     (1<<7)
143991 -#define S3C2412_NFSTAT_ECC_DECDONE     (1<<6)
143992 -#define S3C2412_NFSTAT_ILLEGAL_ACCESS  (1<<5)
143993 -#define S3C2412_NFSTAT_RnB_CHANGE      (1<<4)
143994 -#define S3C2412_NFSTAT_nFCE1           (1<<3)
143995 -#define S3C2412_NFSTAT_nFCE0           (1<<2)
143996 -#define S3C2412_NFSTAT_Res1            (1<<1)
143997 -#define S3C2412_NFSTAT_READY           (1<<0)
143998 -
143999 -#define S3C2412_NFECCERR_SERRDATA(x)   (((x) >> 21) & 0xf)
144000 -#define S3C2412_NFECCERR_SERRBIT(x)    (((x) >> 18) & 0x7)
144001 -#define S3C2412_NFECCERR_MERRDATA(x)   (((x) >> 7) & 0x3ff)
144002 -#define S3C2412_NFECCERR_MERRBIT(x)    (((x) >> 4) & 0x7)
144003 -#define S3C2412_NFECCERR_SPARE_ERR(x)  (((x) >> 2) & 0x3)
144004 -#define S3C2412_NFECCERR_MAIN_ERR(x)   (((x) >> 2) & 0x3)
144005 -#define S3C2412_NFECCERR_NONE          (0)
144006 -#define S3C2412_NFECCERR_1BIT          (1)
144007 -#define S3C2412_NFECCERR_MULTIBIT      (2)
144008 -#define S3C2412_NFECCERR_ECCAREA       (3)
144009 -
144010 -
144011 -
144012 -#endif /* __ASM_ARM_REGS_NAND */
144013 -
144014 --- a/include/asm-arm/plat-s3c/regs-rtc.h
144015 +++ /dev/null
144016 @@ -1,61 +0,0 @@
144017 -/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
144018 - *
144019 - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
144020 - *                   http://www.simtec.co.uk/products/SWLINUX/
144021 - *
144022 - * This program is free software; you can redistribute it and/or modify
144023 - * it under the terms of the GNU General Public License version 2 as
144024 - * published by the Free Software Foundation.
144025 - *
144026 - * S3C2410 Internal RTC register definition
144027 -*/
144028 -
144029 -#ifndef __ASM_ARCH_REGS_RTC_H
144030 -#define __ASM_ARCH_REGS_RTC_H __FILE__
144031 -
144032 -#define S3C2410_RTCREG(x) (x)
144033 -
144034 -#define S3C2410_RTCCON       S3C2410_RTCREG(0x40)
144035 -#define S3C2410_RTCCON_RTCEN  (1<<0)
144036 -#define S3C2410_RTCCON_CLKSEL (1<<1)
144037 -#define S3C2410_RTCCON_CNTSEL (1<<2)
144038 -#define S3C2410_RTCCON_CLKRST (1<<3)
144039 -
144040 -#define S3C2410_TICNT        S3C2410_RTCREG(0x44)
144041 -#define S3C2410_TICNT_ENABLE  (1<<7)
144042 -
144043 -#define S3C2410_RTCALM       S3C2410_RTCREG(0x50)
144044 -#define S3C2410_RTCALM_ALMEN  (1<<6)
144045 -#define S3C2410_RTCALM_YEAREN (1<<5)
144046 -#define S3C2410_RTCALM_MONEN  (1<<4)
144047 -#define S3C2410_RTCALM_DAYEN  (1<<3)
144048 -#define S3C2410_RTCALM_HOUREN (1<<2)
144049 -#define S3C2410_RTCALM_MINEN  (1<<1)
144050 -#define S3C2410_RTCALM_SECEN  (1<<0)
144051 -
144052 -#define S3C2410_RTCALM_ALL \
144053 -  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
144054 -  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
144055 -  S3C2410_RTCALM_SECEN
144056 -
144057 -
144058 -#define S3C2410_ALMSEC       S3C2410_RTCREG(0x54)
144059 -#define S3C2410_ALMMIN       S3C2410_RTCREG(0x58)
144060 -#define S3C2410_ALMHOUR              S3C2410_RTCREG(0x5c)
144061 -
144062 -#define S3C2410_ALMDATE              S3C2410_RTCREG(0x60)
144063 -#define S3C2410_ALMMON       S3C2410_RTCREG(0x64)
144064 -#define S3C2410_ALMYEAR              S3C2410_RTCREG(0x68)
144065 -
144066 -#define S3C2410_RTCRST       S3C2410_RTCREG(0x6c)
144067 -
144068 -#define S3C2410_RTCSEC       S3C2410_RTCREG(0x70)
144069 -#define S3C2410_RTCMIN       S3C2410_RTCREG(0x74)
144070 -#define S3C2410_RTCHOUR              S3C2410_RTCREG(0x78)
144071 -#define S3C2410_RTCDATE              S3C2410_RTCREG(0x7c)
144072 -#define S3C2410_RTCDAY       S3C2410_RTCREG(0x80)
144073 -#define S3C2410_RTCMON       S3C2410_RTCREG(0x84)
144074 -#define S3C2410_RTCYEAR              S3C2410_RTCREG(0x88)
144075 -
144076 -
144077 -#endif /* __ASM_ARCH_REGS_RTC_H */
144078 --- a/include/asm-arm/plat-s3c/regs-watchdog.h
144079 +++ /dev/null
144080 @@ -1,41 +0,0 @@
144081 -/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
144082 - *
144083 - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
144084 - *                   http://www.simtec.co.uk/products/SWLINUX/
144085 - *
144086 - * This program is free software; you can redistribute it and/or modify
144087 - * it under the terms of the GNU General Public License version 2 as
144088 - * published by the Free Software Foundation.
144089 - *
144090 - * S3C2410 Watchdog timer control
144091 -*/
144092 -
144093 -
144094 -#ifndef __ASM_ARCH_REGS_WATCHDOG_H
144095 -#define __ASM_ARCH_REGS_WATCHDOG_H
144096 -
144097 -#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
144098 -
144099 -#define S3C2410_WTCON     S3C_WDOGREG(0x00)
144100 -#define S3C2410_WTDAT     S3C_WDOGREG(0x04)
144101 -#define S3C2410_WTCNT     S3C_WDOGREG(0x08)
144102 -
144103 -/* the watchdog can either generate a reset pulse, or an
144104 - * interrupt.
144105 - */
144106 -
144107 -#define S3C2410_WTCON_RSTEN   (0x01)
144108 -#define S3C2410_WTCON_INTEN   (1<<2)
144109 -#define S3C2410_WTCON_ENABLE  (1<<5)
144110 -
144111 -#define S3C2410_WTCON_DIV16   (0<<3)
144112 -#define S3C2410_WTCON_DIV32   (1<<3)
144113 -#define S3C2410_WTCON_DIV64   (2<<3)
144114 -#define S3C2410_WTCON_DIV128  (3<<3)
144115 -
144116 -#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
144117 -#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
144118 -
144119 -#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
144120 -
144121 -
144122 --- a/include/asm-arm/plat-s3c24xx/mci.h
144123 +++ /dev/null
144124 @@ -1,15 +0,0 @@
144125 -#ifndef _ARCH_MCI_H
144126 -#define _ARCH_MCI_H
144127 -
144128 -struct s3c24xx_mci_pdata {
144129 -       unsigned int    wprotect_invert : 1;
144130 -       unsigned int    detect_invert : 1;   /* set => detect active high. */
144131 -
144132 -       unsigned int    gpio_detect;
144133 -       unsigned int    gpio_wprotect;
144134 -       unsigned long   ocr_avail;
144135 -       void            (*set_power)(unsigned char power_mode,
144136 -                                    unsigned short vdd);
144137 -};
144138 -
144139 -#endif /* _ARCH_NCI_H */
144140 --- /dev/null
144141 +++ b/include/asm-arm/plat-s3c24xx/neo1973.h
144142 @@ -0,0 +1,33 @@
144143 +/*
144144 + * include/asm-arm/plat-s3c24xx/neo1973.h
144145 + *
144146 + * Common utility code for GTA01 and GTA02
144147 + *
144148 + * Copyright (C) 2008 by Openmoko, Inc.
144149 + * Author: Holger Hans Peter Freyther <freyther@openmoko.org>
144150 + * All rights reserved.
144151 + *
144152 + * This program is free software; you can redistribute it and/or
144153 + * modify it under the terms of the GNU General Public License as
144154 + * published by the Free Software Foundation; either version 2 of
144155 + * the License, or (at your option) any later version.
144156 + *
144157 + * This program is distributed in the hope that it will be useful,
144158 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
144159 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
144160 + * GNU General Public License for more details.
144161 + *
144162 + * You should have received a copy of the GNU General Public License
144163 + * along with this program; if not, write to the Free Software
144164 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
144165 + * MA 02111-1307 USA
144166 + *
144167 + */
144168 +
144169 +#ifndef NEO1973_H
144170 +#define NEO1973_H
144171 +
144172 +void neo1973_gpb_add_shadow_gpio(unsigned int gpio);
144173 +void neo1973_gpb_setpin(unsigned int pin, unsigned to);
144174 +
144175 +#endif
144176 --- a/include/asm-arm/plat-s3c24xx/regs-spi.h
144177 +++ /dev/null
144178 @@ -1,82 +0,0 @@
144179 -/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
144180 - *
144181 - * Copyright (c) 2004 Fetron GmbH
144182 - *
144183 - * This program is free software; you can redistribute it and/or modify
144184 - * it under the terms of the GNU General Public License version 2 as
144185 - * published by the Free Software Foundation.
144186 - *
144187 - * S3C2410 SPI register definition
144188 -*/
144189 -
144190 -#ifndef __ASM_ARCH_REGS_SPI_H
144191 -#define __ASM_ARCH_REGS_SPI_H
144192 -
144193 -#define S3C2410_SPI1   (0x20)
144194 -#define S3C2412_SPI1   (0x100)
144195 -
144196 -#define S3C2410_SPCON  (0x00)
144197 -
144198 -#define S3C2412_SPCON_RXFIFO_RB2       (0<<14)
144199 -#define S3C2412_SPCON_RXFIFO_RB4       (1<<14)
144200 -#define S3C2412_SPCON_RXFIFO_RB12      (2<<14)
144201 -#define S3C2412_SPCON_RXFIFO_RB14      (3<<14)
144202 -#define S3C2412_SPCON_TXFIFO_RB2       (0<<12)
144203 -#define S3C2412_SPCON_TXFIFO_RB4       (1<<12)
144204 -#define S3C2412_SPCON_TXFIFO_RB12      (2<<12)
144205 -#define S3C2412_SPCON_TXFIFO_RB14      (3<<12)
144206 -#define S3C2412_SPCON_RXFIFO_RESET     (1<<11) /* RxFIFO reset */
144207 -#define S3C2412_SPCON_TXFIFO_RESET     (1<<10) /* TxFIFO reset */
144208 -#define S3C2412_SPCON_RXFIFO_EN                (1<<9)  /* RxFIFO Enable */
144209 -#define S3C2412_SPCON_TXFIFO_EN                (1<<8)  /* TxFIFO Enable */
144210 -
144211 -#define S3C2412_SPCON_DIRC_RX    (1<<7)
144212 -
144213 -#define S3C2410_SPCON_SMOD_DMA   (2<<5)        /* DMA mode */
144214 -#define S3C2410_SPCON_SMOD_INT   (1<<5)        /* interrupt mode */
144215 -#define S3C2410_SPCON_SMOD_POLL   (0<<5)       /* polling mode */
144216 -#define S3C2410_SPCON_ENSCK      (1<<4)        /* Enable SCK */
144217 -#define S3C2410_SPCON_MSTR       (1<<3)        /* Master/Slave select
144218 -                                                  0: slave, 1: master */
144219 -#define S3C2410_SPCON_CPOL_HIGH          (1<<2)        /* Clock polarity select */
144220 -#define S3C2410_SPCON_CPOL_LOW   (0<<2)        /* Clock polarity select */
144221 -
144222 -#define S3C2410_SPCON_CPHA_FMTB          (1<<1)        /* Clock Phase Select */
144223 -#define S3C2410_SPCON_CPHA_FMTA          (0<<1)        /* Clock Phase Select */
144224 -
144225 -#define S3C2410_SPCON_TAGD       (1<<0)        /* Tx auto garbage data mode */
144226 -
144227 -
144228 -#define S3C2410_SPSTA   (0x04)
144229 -
144230 -#define S3C2412_SPSTA_RXFIFO_AE                (1<<11)
144231 -#define S3C2412_SPSTA_TXFIFO_AE                (1<<10)
144232 -#define S3C2412_SPSTA_RXFIFO_ERROR     (1<<9)
144233 -#define S3C2412_SPSTA_TXFIFO_ERROR     (1<<8)
144234 -#define S3C2412_SPSTA_RXFIFO_FIFO      (1<<7)
144235 -#define S3C2412_SPSTA_RXFIFO_EMPTY     (1<<6)
144236 -#define S3C2412_SPSTA_TXFIFO_NFULL     (1<<5)
144237 -#define S3C2412_SPSTA_TXFIFO_EMPTY     (1<<4)
144238 -
144239 -#define S3C2410_SPSTA_DCOL       (1<<2)        /* Data Collision Error */
144240 -#define S3C2410_SPSTA_MULD       (1<<1)        /* Multi Master Error */
144241 -#define S3C2410_SPSTA_READY      (1<<0)        /* Data Tx/Rx ready */
144242 -#define S3C2412_SPSTA_READY_ORG          (1<<3)
144243 -
144244 -#define S3C2410_SPPIN   (0x08)
144245 -
144246 -#define S3C2410_SPPIN_ENMUL      (1<<2)        /* Multi Master Error detect */
144247 -#define S3C2410_SPPIN_RESERVED   (1<<1)
144248 -#define S3C2400_SPPIN_nCS        (1<<1)        /* SPI Card Select */
144249 -#define S3C2410_SPPIN_KEEP       (1<<0)        /* Master Out keep */
144250 -
144251 -#define S3C2410_SPPRE   (0x0C)
144252 -#define S3C2410_SPTDAT  (0x10)
144253 -#define S3C2410_SPRDAT  (0x14)
144254 -
144255 -#define S3C2412_TXFIFO  (0x18)
144256 -#define S3C2412_RXFIFO  (0x18)
144257 -#define S3C2412_SPFIC   (0x24)
144258 -
144259 -
144260 -#endif /* __ASM_ARCH_REGS_SPI_H */
144261 --- a/include/asm-arm/plat-s3c24xx/regs-udc.h
144262 +++ /dev/null
144263 @@ -1,153 +0,0 @@
144264 -/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
144265 - *
144266 - * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
144267 - *
144268 - * This include file is free software; you can redistribute it and/or
144269 - * modify it under the terms of the GNU General Public License as
144270 - * published by the Free Software Foundation; either version 2 of
144271 - * the License, or (at your option) any later version.
144272 -*/
144273 -
144274 -#ifndef __ASM_ARCH_REGS_UDC_H
144275 -#define __ASM_ARCH_REGS_UDC_H
144276 -
144277 -#define S3C2410_USBDREG(x) (x)
144278 -
144279 -#define S3C2410_UDC_FUNC_ADDR_REG      S3C2410_USBDREG(0x0140)
144280 -#define S3C2410_UDC_PWR_REG            S3C2410_USBDREG(0x0144)
144281 -#define S3C2410_UDC_EP_INT_REG         S3C2410_USBDREG(0x0148)
144282 -
144283 -#define S3C2410_UDC_USB_INT_REG                S3C2410_USBDREG(0x0158)
144284 -#define S3C2410_UDC_EP_INT_EN_REG      S3C2410_USBDREG(0x015c)
144285 -
144286 -#define S3C2410_UDC_USB_INT_EN_REG     S3C2410_USBDREG(0x016c)
144287 -
144288 -#define S3C2410_UDC_FRAME_NUM1_REG     S3C2410_USBDREG(0x0170)
144289 -#define S3C2410_UDC_FRAME_NUM2_REG     S3C2410_USBDREG(0x0174)
144290 -
144291 -#define S3C2410_UDC_EP0_FIFO_REG       S3C2410_USBDREG(0x01c0)
144292 -#define S3C2410_UDC_EP1_FIFO_REG       S3C2410_USBDREG(0x01c4)
144293 -#define S3C2410_UDC_EP2_FIFO_REG       S3C2410_USBDREG(0x01c8)
144294 -#define S3C2410_UDC_EP3_FIFO_REG       S3C2410_USBDREG(0x01cc)
144295 -#define S3C2410_UDC_EP4_FIFO_REG       S3C2410_USBDREG(0x01d0)
144296 -
144297 -#define S3C2410_UDC_EP1_DMA_CON                S3C2410_USBDREG(0x0200)
144298 -#define S3C2410_UDC_EP1_DMA_UNIT       S3C2410_USBDREG(0x0204)
144299 -#define S3C2410_UDC_EP1_DMA_FIFO       S3C2410_USBDREG(0x0208)
144300 -#define S3C2410_UDC_EP1_DMA_TTC_L      S3C2410_USBDREG(0x020c)
144301 -#define S3C2410_UDC_EP1_DMA_TTC_M      S3C2410_USBDREG(0x0210)
144302 -#define S3C2410_UDC_EP1_DMA_TTC_H      S3C2410_USBDREG(0x0214)
144303 -
144304 -#define S3C2410_UDC_EP2_DMA_CON                S3C2410_USBDREG(0x0218)
144305 -#define S3C2410_UDC_EP2_DMA_UNIT       S3C2410_USBDREG(0x021c)
144306 -#define S3C2410_UDC_EP2_DMA_FIFO       S3C2410_USBDREG(0x0220)
144307 -#define S3C2410_UDC_EP2_DMA_TTC_L      S3C2410_USBDREG(0x0224)
144308 -#define S3C2410_UDC_EP2_DMA_TTC_M      S3C2410_USBDREG(0x0228)
144309 -#define S3C2410_UDC_EP2_DMA_TTC_H      S3C2410_USBDREG(0x022c)
144310 -
144311 -#define S3C2410_UDC_EP3_DMA_CON                S3C2410_USBDREG(0x0240)
144312 -#define S3C2410_UDC_EP3_DMA_UNIT       S3C2410_USBDREG(0x0244)
144313 -#define S3C2410_UDC_EP3_DMA_FIFO       S3C2410_USBDREG(0x0248)
144314 -#define S3C2410_UDC_EP3_DMA_TTC_L      S3C2410_USBDREG(0x024c)
144315 -#define S3C2410_UDC_EP3_DMA_TTC_M      S3C2410_USBDREG(0x0250)
144316 -#define S3C2410_UDC_EP3_DMA_TTC_H      S3C2410_USBDREG(0x0254)
144317 -
144318 -#define S3C2410_UDC_EP4_DMA_CON                S3C2410_USBDREG(0x0258)
144319 -#define S3C2410_UDC_EP4_DMA_UNIT       S3C2410_USBDREG(0x025c)
144320 -#define S3C2410_UDC_EP4_DMA_FIFO       S3C2410_USBDREG(0x0260)
144321 -#define S3C2410_UDC_EP4_DMA_TTC_L      S3C2410_USBDREG(0x0264)
144322 -#define S3C2410_UDC_EP4_DMA_TTC_M      S3C2410_USBDREG(0x0268)
144323 -#define S3C2410_UDC_EP4_DMA_TTC_H      S3C2410_USBDREG(0x026c)
144324 -
144325 -#define S3C2410_UDC_INDEX_REG          S3C2410_USBDREG(0x0178)
144326 -
144327 -/* indexed registers */
144328 -
144329 -#define S3C2410_UDC_MAXP_REG           S3C2410_USBDREG(0x0180)
144330 -
144331 -#define S3C2410_UDC_EP0_CSR_REG                S3C2410_USBDREG(0x0184)
144332 -
144333 -#define S3C2410_UDC_IN_CSR1_REG                S3C2410_USBDREG(0x0184)
144334 -#define S3C2410_UDC_IN_CSR2_REG                S3C2410_USBDREG(0x0188)
144335 -
144336 -#define S3C2410_UDC_OUT_CSR1_REG       S3C2410_USBDREG(0x0190)
144337 -#define S3C2410_UDC_OUT_CSR2_REG       S3C2410_USBDREG(0x0194)
144338 -#define S3C2410_UDC_OUT_FIFO_CNT1_REG  S3C2410_USBDREG(0x0198)
144339 -#define S3C2410_UDC_OUT_FIFO_CNT2_REG  S3C2410_USBDREG(0x019c)
144340 -
144341 -#define S3C2410_UDC_FUNCADDR_UPDATE    (1<<7)
144342 -
144343 -#define S3C2410_UDC_PWR_ISOUP          (1<<7) // R/W
144344 -#define S3C2410_UDC_PWR_RESET          (1<<3) // R
144345 -#define S3C2410_UDC_PWR_RESUME         (1<<2) // R/W
144346 -#define S3C2410_UDC_PWR_SUSPEND                (1<<1) // R
144347 -#define S3C2410_UDC_PWR_ENSUSPEND      (1<<0) // R/W
144348 -
144349 -#define S3C2410_UDC_PWR_DEFAULT                0x00
144350 -
144351 -#define S3C2410_UDC_INT_EP4            (1<<4) // R/W (clear only)
144352 -#define S3C2410_UDC_INT_EP3            (1<<3) // R/W (clear only)
144353 -#define S3C2410_UDC_INT_EP2            (1<<2) // R/W (clear only)
144354 -#define S3C2410_UDC_INT_EP1            (1<<1) // R/W (clear only)
144355 -#define S3C2410_UDC_INT_EP0            (1<<0) // R/W (clear only)
144356 -
144357 -#define S3C2410_UDC_USBINT_RESET       (1<<2) // R/W (clear only)
144358 -#define S3C2410_UDC_USBINT_RESUME      (1<<1) // R/W (clear only)
144359 -#define S3C2410_UDC_USBINT_SUSPEND     (1<<0) // R/W (clear only)
144360 -
144361 -#define S3C2410_UDC_INTE_EP4           (1<<4) // R/W
144362 -#define S3C2410_UDC_INTE_EP3           (1<<3) // R/W
144363 -#define S3C2410_UDC_INTE_EP2           (1<<2) // R/W
144364 -#define S3C2410_UDC_INTE_EP1           (1<<1) // R/W
144365 -#define S3C2410_UDC_INTE_EP0           (1<<0) // R/W
144366 -
144367 -#define S3C2410_UDC_USBINTE_RESET      (1<<2) // R/W
144368 -#define S3C2410_UDC_USBINTE_SUSPEND    (1<<0) // R/W
144369 -
144370 -
144371 -#define S3C2410_UDC_INDEX_EP0          (0x00)
144372 -#define S3C2410_UDC_INDEX_EP1          (0x01) // ??
144373 -#define S3C2410_UDC_INDEX_EP2          (0x02) // ??
144374 -#define S3C2410_UDC_INDEX_EP3          (0x03) // ??
144375 -#define S3C2410_UDC_INDEX_EP4          (0x04) // ??
144376 -
144377 -#define S3C2410_UDC_ICSR1_CLRDT                (1<<6) // R/W
144378 -#define S3C2410_UDC_ICSR1_SENTSTL      (1<<5) // R/W (clear only)
144379 -#define S3C2410_UDC_ICSR1_SENDSTL      (1<<4) // R/W
144380 -#define S3C2410_UDC_ICSR1_FFLUSH       (1<<3) // W   (set only)
144381 -#define S3C2410_UDC_ICSR1_UNDRUN       (1<<2) // R/W (clear only)
144382 -#define S3C2410_UDC_ICSR1_PKTRDY       (1<<0) // R/W (set only)
144383 -
144384 -#define S3C2410_UDC_ICSR2_AUTOSET      (1<<7) // R/W
144385 -#define S3C2410_UDC_ICSR2_ISO          (1<<6) // R/W
144386 -#define S3C2410_UDC_ICSR2_MODEIN       (1<<5) // R/W
144387 -#define S3C2410_UDC_ICSR2_DMAIEN       (1<<4) // R/W
144388 -
144389 -#define S3C2410_UDC_OCSR1_CLRDT                (1<<7) // R/W
144390 -#define S3C2410_UDC_OCSR1_SENTSTL      (1<<6) // R/W (clear only)
144391 -#define S3C2410_UDC_OCSR1_SENDSTL      (1<<5) // R/W
144392 -#define S3C2410_UDC_OCSR1_FFLUSH       (1<<4) // R/W
144393 -#define S3C2410_UDC_OCSR1_DERROR       (1<<3) // R
144394 -#define S3C2410_UDC_OCSR1_OVRRUN       (1<<2) // R/W (clear only)
144395 -#define S3C2410_UDC_OCSR1_PKTRDY       (1<<0) // R/W (clear only)
144396 -
144397 -#define S3C2410_UDC_OCSR2_AUTOCLR      (1<<7) // R/W
144398 -#define S3C2410_UDC_OCSR2_ISO          (1<<6) // R/W
144399 -#define S3C2410_UDC_OCSR2_DMAIEN       (1<<5) // R/W
144400 -
144401 -#define S3C2410_UDC_EP0_CSR_OPKRDY     (1<<0)
144402 -#define S3C2410_UDC_EP0_CSR_IPKRDY     (1<<1)
144403 -#define S3C2410_UDC_EP0_CSR_SENTSTL    (1<<2)
144404 -#define S3C2410_UDC_EP0_CSR_DE         (1<<3)
144405 -#define S3C2410_UDC_EP0_CSR_SE         (1<<4)
144406 -#define S3C2410_UDC_EP0_CSR_SENDSTL    (1<<5)
144407 -#define S3C2410_UDC_EP0_CSR_SOPKTRDY   (1<<6)
144408 -#define S3C2410_UDC_EP0_CSR_SSE        (1<<7)
144409 -
144410 -#define S3C2410_UDC_MAXP_8             (1<<0)
144411 -#define S3C2410_UDC_MAXP_16            (1<<1)
144412 -#define S3C2410_UDC_MAXP_32            (1<<2)
144413 -#define S3C2410_UDC_MAXP_64            (1<<3)
144414 -
144415 -
144416 -#endif
144417 --- a/include/asm-arm/plat-s3c24xx/udc.h
144418 +++ /dev/null
144419 @@ -1,36 +0,0 @@
144420 -/* arch/arm/mach-s3c2410/include/mach/udc.h
144421 - *
144422 - * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
144423 - *
144424 - *
144425 - * This program is free software; you can redistribute it and/or modify
144426 - * it under the terms of the GNU General Public License version 2 as
144427 - * published by the Free Software Foundation.
144428 - *
144429 - *
144430 - *  Changelog:
144431 - *     14-Mar-2005     RTP     Created file
144432 - *     02-Aug-2005     RTP     File rename
144433 - *     07-Sep-2005     BJD     Minor cleanups, changed cmd to enum
144434 - *     18-Jan-2007     HMW     Add per-platform vbus_draw function
144435 -*/
144436 -
144437 -#ifndef __ASM_ARM_ARCH_UDC_H
144438 -#define __ASM_ARM_ARCH_UDC_H
144439 -
144440 -enum s3c2410_udc_cmd_e {
144441 -       S3C2410_UDC_P_ENABLE    = 1,    /* Pull-up enable        */
144442 -       S3C2410_UDC_P_DISABLE   = 2,    /* Pull-up disable       */
144443 -       S3C2410_UDC_P_RESET     = 3,    /* UDC reset, in case of */
144444 -};
144445 -
144446 -struct s3c2410_udc_mach_info {
144447 -       void    (*udc_command)(enum s3c2410_udc_cmd_e);
144448 -       void    (*vbus_draw)(unsigned int ma);
144449 -       unsigned int vbus_pin;
144450 -       unsigned char vbus_pin_inverted;
144451 -};
144452 -
144453 -extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
144454 -
144455 -#endif /* __ASM_ARM_ARCH_UDC_H */
144456 --- /dev/null
144457 +++ b/include/linux/android_aid.h
144458 @@ -0,0 +1,25 @@
144459 +/* include/linux/android_aid.h
144460 + *
144461 + * Copyright (C) 2008 Google, Inc.
144462 + *
144463 + * This software is licensed under the terms of the GNU General Public
144464 + * License version 2, as published by the Free Software Foundation, and
144465 + * may be copied, distributed, and modified under those terms.
144466 + *
144467 + * This program is distributed in the hope that it will be useful,
144468 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
144469 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
144470 + * GNU General Public License for more details.
144471 + *
144472 + */
144473 +
144474 +#ifndef _LINUX_ANDROID_AID_H
144475 +#define _LINUX_ANDROID_AID_H
144476 +
144477 +/* AIDs that the kernel treats differently */
144478 +#define AID_NET_BT_ADMIN 3001
144479 +#define AID_NET_BT       3002
144480 +#define AID_INET         3003
144481 +#define AID_NET_RAW      3004
144482 +
144483 +#endif
144484 --- /dev/null
144485 +++ b/include/linux/android_alarm.h
144486 @@ -0,0 +1,59 @@
144487 +/* include/linux/android_alarm.h
144488 + *
144489 + * Copyright (C) 2006-2007 Google, Inc.
144490 + *
144491 + * This software is licensed under the terms of the GNU General Public
144492 + * License version 2, as published by the Free Software Foundation, and
144493 + * may be copied, distributed, and modified under those terms.
144494 + *
144495 + * This program is distributed in the hope that it will be useful,
144496 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
144497 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
144498 + * GNU General Public License for more details.
144499 + *
144500 + */
144501 +
144502 +#ifndef _LINUX_ANDROID_ALARM_H
144503 +#define _LINUX_ANDROID_ALARM_H
144504 +
144505 +#include <asm/ioctl.h>
144506 +#include <linux/time.h>
144507 +
144508 +typedef enum {
144509 +       /* return code bit numbers or set alarm arg */
144510 +       ANDROID_ALARM_RTC_WAKEUP,
144511 +       ANDROID_ALARM_RTC,
144512 +       ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP,
144513 +       ANDROID_ALARM_ELAPSED_REALTIME,
144514 +       ANDROID_ALARM_SYSTEMTIME,
144515 +
144516 +       ANDROID_ALARM_TYPE_COUNT,
144517 +
144518 +       /* return code bit numbers */
144519 +       /* ANDROID_ALARM_TIME_CHANGE = 16 */
144520 +} android_alarm_type_t;
144521 +
144522 +typedef enum {
144523 +       ANDROID_ALARM_RTC_WAKEUP_MASK = 1U << ANDROID_ALARM_RTC_WAKEUP,
144524 +       ANDROID_ALARM_RTC_MASK = 1U << ANDROID_ALARM_RTC,
144525 +       ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK = 1U << ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP,
144526 +       ANDROID_ALARM_ELAPSED_REALTIME_MASK = 1U << ANDROID_ALARM_ELAPSED_REALTIME,
144527 +       ANDROID_ALARM_SYSTEMTIME_MASK = 1U << ANDROID_ALARM_SYSTEMTIME,
144528 +       ANDROID_ALARM_TIME_CHANGE_MASK = 1U << 16
144529 +} android_alarm_return_flags_t;
144530 +
144531 +/* Disable alarm */
144532 +#define ANDROID_ALARM_CLEAR(type)           _IO('a', 0 | ((type) << 4))
144533 +
144534 +/* Ack last alarm and wait for next */
144535 +#define ANDROID_ALARM_WAIT                  _IO('a', 1)
144536 +
144537 +/* Set alarm */
144538 +#define ANDROID_ALARM_SET(type)             _IOW('a', 2 | ((type) << 4), struct timespec)
144539 +#define ANDROID_ALARM_SET_AND_WAIT(type)    _IOW('a', 3 | ((type) << 4), struct timespec)
144540 +#define ANDROID_ALARM_GET_TIME(type)        _IOW('a', 4 | ((type) << 4), struct timespec)
144541 +#define ANDROID_ALARM_SET_RTC               _IOW('a', 5, struct timespec)
144542 +#define ANDROID_ALARM_BASE_CMD(cmd) (cmd & ~(_IOC(0, 0, 0xf0, 0)))
144543 +#define ANDROID_ALARM_IOCTL_TO_TYPE(cmd) (_IOC_NR(cmd) >> 4)
144544 +
144545 +#endif
144546 --- /dev/null
144547 +++ b/include/linux/android_power.h
144548 @@ -0,0 +1,98 @@
144549 +/* include/linux/android_power.h
144550 + *
144551 + * Copyright (C) 2007-2008 Google, Inc.
144552 + *
144553 + * This software is licensed under the terms of the GNU General Public
144554 + * License version 2, as published by the Free Software Foundation, and
144555 + * may be copied, distributed, and modified under those terms.
144556 + *
144557 + * This program is distributed in the hope that it will be useful,
144558 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
144559 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
144560 + * GNU General Public License for more details.
144561 + *
144562 + */
144563 +
144564 +#ifndef _LINUX_ANDROID_POWER_H
144565 +#define _LINUX_ANDROID_POWER_H
144566 +
144567 +#include <linux/list.h>
144568 +#include <linux/ktime.h>
144569 +
144570 +typedef struct
144571 +{
144572 +       struct list_head    link;
144573 +       int                 flags;
144574 +       const char         *name;
144575 +       int                 expires;
144576 +#ifdef CONFIG_ANDROID_POWER_STAT
144577 +       struct {
144578 +               int             count;
144579 +               int             expire_count;
144580 +               ktime_t         total_time;
144581 +               ktime_t         max_time;
144582 +               ktime_t         last_time;
144583 +       } stat;
144584 +#endif
144585 +} android_suspend_lock_t;
144586 +
144587 +#if 0 /* none of these flags are implemented */
144588 +#define ANDROID_SUSPEND_LOCK_FLAG_COUNTED (1U << 0)
144589 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_READABLE (1U << 1)
144590 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_SET (1U << 2)
144591 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_CLEAR (1U << 3)
144592 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_INC (1U << 4)
144593 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_DEC (1U << 5)
144594 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_VISIBLE_MASK (0x1fU << 1)
144595 +#endif
144596 +#define ANDROID_SUSPEND_LOCK_AUTO_EXPIRE (1U << 6)
144597 +#define ANDROID_SUSPEND_LOCK_ACTIVE      (1U << 7)
144598 +
144599 +enum {
144600 +       ANDROID_STOPPED_DRAWING,
144601 +       ANDROID_REQUEST_STOP_DRAWING,
144602 +       ANDROID_DRAWING_OK,
144603 +};
144604 +
144605 +enum {
144606 +       ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN = 50,
144607 +       ANDROID_EARLY_SUSPEND_LEVEL_CONSOLE_SWITCH = 100,
144608 +       ANDROID_EARLY_SUSPEND_LEVEL_DISABLE_FB = 150,
144609 +};
144610 +typedef struct android_early_suspend android_early_suspend_t;
144611 +struct android_early_suspend
144612 +{
144613 +       struct list_head link;
144614 +       int level;
144615 +       void (*suspend)(android_early_suspend_t *h);
144616 +       void (*resume)(android_early_suspend_t *h);
144617 +};
144618 +
144619 +typedef enum {
144620 +       ANDROID_CHARGING_STATE_UNKNOWN,
144621 +       ANDROID_CHARGING_STATE_DISCHARGE,
144622 +       ANDROID_CHARGING_STATE_MAINTAIN, /* or trickle */
144623 +       ANDROID_CHARGING_STATE_SLOW,
144624 +       ANDROID_CHARGING_STATE_NORMAL,
144625 +       ANDROID_CHARGING_STATE_FAST,
144626 +       ANDROID_CHARGING_STATE_OVERHEAT
144627 +} android_charging_state_t;
144628 +
144629 +/* android_suspend_lock_t *android_allocate_suspend_lock(const char *debug_name); */
144630 +/* void android_free_suspend_lock(android_suspend_lock_t *lock); */
144631 +int android_init_suspend_lock(android_suspend_lock_t *lock);
144632 +void android_uninit_suspend_lock(android_suspend_lock_t *lock);
144633 +void android_lock_idle(android_suspend_lock_t *lock);
144634 +void android_lock_idle_auto_expire(android_suspend_lock_t *lock, int timeout);
144635 +void android_lock_suspend(android_suspend_lock_t *lock);
144636 +void android_lock_suspend_auto_expire(android_suspend_lock_t *lock, int timeout);
144637 +void android_unlock_suspend(android_suspend_lock_t *lock);
144638 +
144639 +int android_power_is_driver_suspended(void);
144640 +int android_power_is_low_power_idle_ok(void);
144641 +
144642 +void android_register_early_suspend(android_early_suspend_t *handler);
144643 +void android_unregister_early_suspend(android_early_suspend_t *handler);
144644 +
144645 +#endif
144646 +
144647 --- /dev/null
144648 +++ b/include/linux/android_timed_gpio.h
144649 @@ -0,0 +1,31 @@
144650 +/* include/linux/android_timed_gpio.h
144651 + *
144652 + * Copyright (C) 2008 Google, Inc.
144653 + *
144654 + * This software is licensed under the terms of the GNU General Public
144655 + * License version 2, as published by the Free Software Foundation, and
144656 + * may be copied, distributed, and modified under those terms.
144657 + *
144658 + * This program is distributed in the hope that it will be useful,
144659 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
144660 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
144661 + * GNU General Public License for more details.
144662 + *
144663 +*/
144664 +
144665 +#ifndef _LINUX_ANDROID_TIMED_GPIO_H
144666 +#define _LINUX_ANDROID_TIMED_GPIO_H
144667 +
144668 +struct timed_gpio {
144669 +       const char *name;
144670 +       unsigned        gpio;
144671 +       int     max_timeout;
144672 +       u8              active_low;
144673 +};
144674 +
144675 +struct timed_gpio_platform_data {
144676 +       int             num_gpios;
144677 +       struct timed_gpio *gpios;
144678 +};
144679 +
144680 +#endif
144681 --- /dev/null
144682 +++ b/include/linux/ashmem.h
144683 @@ -0,0 +1,48 @@
144684 +/*
144685 + * include/linux/ashmem.h
144686 + *
144687 + * Copyright 2008 Google Inc.
144688 + * Author: Robert Love
144689 + *
144690 + * This file is dual licensed.  It may be redistributed and/or modified
144691 + * under the terms of the Apache 2.0 License OR version 2 of the GNU
144692 + * General Public License.
144693 + */
144694 +
144695 +#ifndef _LINUX_ASHMEM_H
144696 +#define _LINUX_ASHMEM_H
144697 +
144698 +#include <linux/limits.h>
144699 +#include <linux/ioctl.h>
144700 +
144701 +#define ASHMEM_NAME_LEN                256
144702 +
144703 +#define ASHMEM_NAME_DEF                "dev/ashmem"
144704 +
144705 +/* Return values from ASHMEM_PIN: Was the mapping purged while unpinned? */
144706 +#define ASHMEM_NOT_PURGED      0
144707 +#define ASHMEM_WAS_PURGED      1
144708 +
144709 +/* Return values from ASHMEM_GET_PIN_STATUS: Is the mapping pinned? */
144710 +#define ASHMEM_IS_UNPINNED     0
144711 +#define ASHMEM_IS_PINNED       1
144712 +
144713 +struct ashmem_pin {
144714 +       __u32 offset;   /* offset into region, in bytes, page-aligned */
144715 +       __u32 len;      /* length forward from offset, in bytes, page-aligned */
144716 +};
144717 +
144718 +#define __ASHMEMIOC            0x77
144719 +
144720 +#define ASHMEM_SET_NAME                _IOW(__ASHMEMIOC, 1, char[ASHMEM_NAME_LEN])
144721 +#define ASHMEM_GET_NAME                _IOR(__ASHMEMIOC, 2, char[ASHMEM_NAME_LEN])
144722 +#define ASHMEM_SET_SIZE                _IOW(__ASHMEMIOC, 3, size_t)
144723 +#define ASHMEM_GET_SIZE                _IO(__ASHMEMIOC, 4)
144724 +#define ASHMEM_SET_PROT_MASK   _IOW(__ASHMEMIOC, 5, unsigned long)
144725 +#define ASHMEM_GET_PROT_MASK   _IO(__ASHMEMIOC, 6)
144726 +#define ASHMEM_PIN             _IOW(__ASHMEMIOC, 7, struct ashmem_pin)
144727 +#define ASHMEM_UNPIN           _IOW(__ASHMEMIOC, 8, struct ashmem_pin)
144728 +#define ASHMEM_GET_PIN_STATUS  _IO(__ASHMEMIOC, 9)
144729 +#define ASHMEM_PURGE_ALL_CACHES        _IO(__ASHMEMIOC, 10)
144730 +
144731 +#endif /* _LINUX_ASHMEM_H */
144732 --- /dev/null
144733 +++ b/include/linux/binder.h
144734 @@ -0,0 +1,330 @@
144735 +/*
144736 + * Copyright (C) 2008 Google, Inc.
144737 + *
144738 + * Based on, but no longer compatible with, the original
144739 + * OpenBinder.org binder driver interface, which is:
144740 + *
144741 + * Copyright (c) 2005 Palmsource, Inc.
144742 + *
144743 + * This software is licensed under the terms of the GNU General Public
144744 + * License version 2, as published by the Free Software Foundation, and
144745 + * may be copied, distributed, and modified under those terms.
144746 + *
144747 + * This program is distributed in the hope that it will be useful,
144748 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
144749 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
144750 + * GNU General Public License for more details.
144751 + *
144752 + */
144753 +
144754 +#ifndef _LINUX_BINDER_H
144755 +#define _LINUX_BINDER_H
144756 +
144757 +#include <linux/ioctl.h>
144758 +
144759 +#define B_PACK_CHARS(c1, c2, c3, c4) \
144760 +       ((((c1)<<24)) | (((c2)<<16)) | (((c3)<<8)) | (c4))
144761 +#define B_TYPE_LARGE 0x85
144762 +
144763 +enum {
144764 +       BINDER_TYPE_BINDER      = B_PACK_CHARS('s', 'b', '*', B_TYPE_LARGE),
144765 +       BINDER_TYPE_WEAK_BINDER = B_PACK_CHARS('w', 'b', '*', B_TYPE_LARGE),
144766 +       BINDER_TYPE_HANDLE      = B_PACK_CHARS('s', 'h', '*', B_TYPE_LARGE),
144767 +       BINDER_TYPE_WEAK_HANDLE = B_PACK_CHARS('w', 'h', '*', B_TYPE_LARGE),
144768 +       BINDER_TYPE_FD          = B_PACK_CHARS('f', 'd', '*', B_TYPE_LARGE),
144769 +};
144770 +
144771 +enum {
144772 +       FLAT_BINDER_FLAG_PRIORITY_MASK = 0xff,
144773 +       FLAT_BINDER_FLAG_ACCEPTS_FDS = 0x100,
144774 +};
144775 +
144776 +/*
144777 + * This is the flattened representation of a Binder object for transfer
144778 + * between processes.  The 'offsets' supplied as part of a binder transaction
144779 + * contains offsets into the data where these structures occur.  The Binder
144780 + * driver takes care of re-writing the structure type and data as it moves
144781 + * between processes.
144782 + */
144783 +struct flat_binder_object {
144784 +       /* 8 bytes for large_flat_header. */
144785 +       unsigned long           type;
144786 +       unsigned long           flags;
144787 +
144788 +       /* 8 bytes of data. */
144789 +       union {
144790 +               void            *binder;        /* local object */
144791 +               signed long     handle;         /* remote object */
144792 +       };
144793 +
144794 +       /* extra data associated with local object */
144795 +       void                    *cookie;
144796 +};
144797 +
144798 +/*
144799 + * On 64-bit platforms where user code may run in 32-bits the driver must
144800 + * translate the buffer (and local binder) addresses apropriately.
144801 + */
144802 +
144803 +struct binder_write_read {
144804 +       signed long     write_size;     /* bytes to write */
144805 +       signed long     write_consumed; /* bytes consumed by driver */
144806 +       unsigned long   write_buffer;
144807 +       signed long     read_size;      /* bytes to read */
144808 +       signed long     read_consumed;  /* bytes consumed by driver */
144809 +       unsigned long   read_buffer;
144810 +};
144811 +
144812 +/* Use with BINDER_VERSION, driver fills in fields. */
144813 +struct binder_version {
144814 +       /* driver protocol version -- increment with incompatible change */
144815 +       signed long     protocol_version;
144816 +};
144817 +
144818 +/* This is the current protocol version. */
144819 +#define BINDER_CURRENT_PROTOCOL_VERSION 7
144820 +
144821 +#define BINDER_WRITE_READ              _IOWR('b', 1, struct binder_write_read)
144822 +#define        BINDER_SET_IDLE_TIMEOUT         _IOW('b', 3, int64_t)
144823 +#define        BINDER_SET_MAX_THREADS          _IOW('b', 5, size_t)
144824 +#define        BINDER_SET_IDLE_PRIORITY        _IOW('b', 6, int)
144825 +#define        BINDER_SET_CONTEXT_MGR          _IOW('b', 7, int)
144826 +#define        BINDER_THREAD_EXIT              _IOW('b', 8, int)
144827 +#define BINDER_VERSION                 _IOWR('b', 9, struct binder_version)
144828 +
144829 +/*
144830 + * NOTE: Two special error codes you should check for when calling
144831 + * in to the driver are:
144832 + *
144833 + * EINTR -- The operation has been interupted.  This should be
144834 + * handled by retrying the ioctl() until a different error code
144835 + * is returned.
144836 + *
144837 + * ECONNREFUSED -- The driver is no longer accepting operations
144838 + * from your process.  That is, the process is being destroyed.
144839 + * You should handle this by exiting from your process.  Note
144840 + * that once this error code is returned, all further calls to
144841 + * the driver from any thread will return this same code.
144842 + */
144843 +
144844 +enum transaction_flags {
144845 +       TF_ONE_WAY      = 0x01, /* this is a one-way call: async, no return */
144846 +       TF_ROOT_OBJECT  = 0x04, /* contents are the component's root object */
144847 +       TF_STATUS_CODE  = 0x08, /* contents are a 32-bit status code */
144848 +       TF_ACCEPT_FDS   = 0x10, /* allow replies with file descriptors */
144849 +};
144850 +
144851 +struct binder_transaction_data {
144852 +       /* The first two are only used for bcTRANSACTION and brTRANSACTION,
144853 +        * identifying the target and contents of the transaction.
144854 +        */
144855 +       union {
144856 +               size_t  handle; /* target descriptor of command transaction */
144857 +               void    *ptr;   /* target descriptor of return transaction */
144858 +       } target;
144859 +       void            *cookie;        /* target object cookie */
144860 +       unsigned int    code;           /* transaction command */
144861 +
144862 +       /* General information about the transaction. */
144863 +       unsigned int    flags;
144864 +       pid_t           sender_pid;
144865 +       uid_t           sender_euid;
144866 +       size_t          data_size;      /* number of bytes of data */
144867 +       size_t          offsets_size;   /* number of bytes of offsets */
144868 +
144869 +       /* If this transaction is inline, the data immediately
144870 +        * follows here; otherwise, it ends with a pointer to
144871 +        * the data buffer.
144872 +        */
144873 +       union {
144874 +               struct {
144875 +                       /* transaction data */
144876 +                       const void      *buffer;
144877 +                       /* offsets from buffer to flat_binder_object structs */
144878 +                       const void      *offsets;
144879 +               } ptr;
144880 +               uint8_t buf[8];
144881 +       } data;
144882 +};
144883 +
144884 +struct binder_ptr_cookie {
144885 +       void *ptr;
144886 +       void *cookie;
144887 +};
144888 +
144889 +struct binder_pri_desc {
144890 +       int priority;
144891 +       int desc;
144892 +};
144893 +
144894 +struct binder_pri_ptr_cookie {
144895 +       int priority;
144896 +       void *ptr;
144897 +       void *cookie;
144898 +};
144899 +
144900 +enum BinderDriverReturnProtocol {
144901 +       BR_ERROR = _IOR('r', 0, int),
144902 +       /*
144903 +        * int: error code
144904 +        */
144905 +
144906 +       BR_OK = _IO('r', 1),
144907 +       /* No parameters! */
144908 +
144909 +       BR_TRANSACTION = _IOR('r', 2, struct binder_transaction_data),
144910 +       BR_REPLY = _IOR('r', 3, struct binder_transaction_data),
144911 +       /*
144912 +        * binder_transaction_data: the received command.
144913 +        */
144914 +
144915 +       BR_ACQUIRE_RESULT = _IOR('r', 4, int),
144916 +       /*
144917 +        * not currently supported
144918 +        * int: 0 if the last bcATTEMPT_ACQUIRE was not successful.
144919 +        * Else the remote object has acquired a primary reference.
144920 +        */
144921 +
144922 +       BR_DEAD_REPLY = _IO('r', 5),
144923 +       /*
144924 +        * The target of the last transaction (either a bcTRANSACTION or
144925 +        * a bcATTEMPT_ACQUIRE) is no longer with us.  No parameters.
144926 +        */
144927 +
144928 +       BR_TRANSACTION_COMPLETE = _IO('r', 6),
144929 +       /*
144930 +        * No parameters... always refers to the last transaction requested
144931 +        * (including replies).  Note that this will be sent even for
144932 +        * asynchronous transactions.
144933 +        */
144934 +
144935 +       BR_INCREFS = _IOR('r', 7, struct binder_ptr_cookie),
144936 +       BR_ACQUIRE = _IOR('r', 8, struct binder_ptr_cookie),
144937 +       BR_RELEASE = _IOR('r', 9, struct binder_ptr_cookie),
144938 +       BR_DECREFS = _IOR('r', 10, struct binder_ptr_cookie),
144939 +       /*
144940 +        * void *:      ptr to binder
144941 +        * void *: cookie for binder
144942 +        */
144943 +
144944 +       BR_ATTEMPT_ACQUIRE = _IOR('r', 11, struct binder_pri_ptr_cookie),
144945 +       /*
144946 +        * not currently supported
144947 +        * int: priority
144948 +        * void *: ptr to binder
144949 +        * void *: cookie for binder
144950 +        */
144951 +
144952 +       BR_NOOP = _IO('r', 12),
144953 +       /*
144954 +        * No parameters.  Do nothing and examine the next command.  It exists
144955 +        * primarily so that we can replace it with a BR_SPAWN_LOOPER command.
144956 +        */
144957 +
144958 +       BR_SPAWN_LOOPER = _IO('r', 13),
144959 +       /*
144960 +        * No parameters.  The driver has determined that a process has no
144961 +        * threads waiting to service incomming transactions.  When a process
144962 +        * receives this command, it must spawn a new service thread and
144963 +        * register it via bcENTER_LOOPER.
144964 +        */
144965 +
144966 +       BR_FINISHED = _IO('r', 14),
144967 +       /*
144968 +        * not currently supported
144969 +        * stop threadpool thread
144970 +        */
144971 +
144972 +       BR_DEAD_BINDER = _IOR('r', 15, void *),
144973 +       /*
144974 +        * void *: cookie
144975 +        */
144976 +       BR_CLEAR_DEATH_NOTIFICATION_DONE = _IOR('r', 16, void *),
144977 +       /*
144978 +        * void *: cookie
144979 +        */
144980 +
144981 +       BR_FAILED_REPLY = _IO('r', 17),
144982 +       /*
144983 +        * The the last transaction (either a bcTRANSACTION or
144984 +        * a bcATTEMPT_ACQUIRE) failed (e.g. out of memory).  No parameters.
144985 +        */
144986 +};
144987 +
144988 +enum BinderDriverCommandProtocol {
144989 +       BC_TRANSACTION = _IOW('c', 0, struct binder_transaction_data),
144990 +       BC_REPLY = _IOW('c', 1, struct binder_transaction_data),
144991 +       /*
144992 +        * binder_transaction_data: the sent command.
144993 +        */
144994 +
144995 +       BC_ACQUIRE_RESULT = _IOW('c', 2, int),
144996 +       /*
144997 +        * not currently supported
144998 +        * int:  0 if the last BR_ATTEMPT_ACQUIRE was not successful.
144999 +        * Else you have acquired a primary reference on the object.
145000 +        */
145001 +
145002 +       BC_FREE_BUFFER = _IOW('c', 3, int),
145003 +       /*
145004 +        * void *: ptr to transaction data received on a read
145005 +        */
145006 +
145007 +       BC_INCREFS = _IOW('c', 4, int),
145008 +       BC_ACQUIRE = _IOW('c', 5, int),
145009 +       BC_RELEASE = _IOW('c', 6, int),
145010 +       BC_DECREFS = _IOW('c', 7, int),
145011 +       /*
145012 +        * int: descriptor
145013 +        */
145014 +
145015 +       BC_INCREFS_DONE = _IOW('c', 8, struct binder_ptr_cookie),
145016 +       BC_ACQUIRE_DONE = _IOW('c', 9, struct binder_ptr_cookie),
145017 +       /*
145018 +        * void *: ptr to binder
145019 +        * void *: cookie for binder
145020 +        */
145021 +
145022 +       BC_ATTEMPT_ACQUIRE = _IOW('c', 10, struct binder_pri_desc),
145023 +       /*
145024 +        * not currently supported
145025 +        * int: priority
145026 +        * int: descriptor
145027 +        */
145028 +
145029 +       BC_REGISTER_LOOPER = _IO('c', 11),
145030 +       /*
145031 +        * No parameters.
145032 +        * Register a spawned looper thread with the device.
145033 +        */
145034 +
145035 +       BC_ENTER_LOOPER = _IO('c', 12),
145036 +       BC_EXIT_LOOPER = _IO('c', 13),
145037 +       /*
145038 +        * No parameters.
145039 +        * These two commands are sent as an application-level thread
145040 +        * enters and exits the binder loop, respectively.  They are
145041 +        * used so the binder can have an accurate count of the number
145042 +        * of looping threads it has available.
145043 +        */
145044 +
145045 +       BC_REQUEST_DEATH_NOTIFICATION = _IOW('c', 14, struct binder_ptr_cookie),
145046 +       /*
145047 +        * void *: ptr to binder
145048 +        * void *: cookie
145049 +        */
145050 +
145051 +       BC_CLEAR_DEATH_NOTIFICATION = _IOW('c', 15, struct binder_ptr_cookie),
145052 +       /*
145053 +        * void *: ptr to binder
145054 +        * void *: cookie
145055 +        */
145056 +
145057 +       BC_DEAD_BINDER_DONE = _IOW('c', 16, void *),
145058 +       /*
145059 +        * void *: cookie
145060 +        */
145061 +};
145062 +
145063 +#endif /* _LINUX_BINDER_H */
145064 +
145065 --- /dev/null
145066 +++ b/include/linux/bq27000_battery.h
145067 @@ -0,0 +1,14 @@
145068 +#ifndef __BQ27000_BATTERY_H__
145069 +#define __BQ27000_BATTERY_H__
145070 +
145071 +struct bq27000_platform_data {
145072 +       const char      *name;
145073 +       int             rsense_mohms;
145074 +       int (*hdq_read)(int);
145075 +       int (*hdq_write)(int, u8);
145076 +       int (*hdq_initialized)(void);
145077 +       int (*get_charger_online_status)(void);
145078 +       int (*get_charger_active_status)(void);
145079 +};
145080 +
145081 +#endif
145082 --- a/include/linux/device.h
145083 +++ b/include/linux/device.h
145084 @@ -48,6 +48,11 @@ extern int __must_check bus_create_file(
145085                                         struct bus_attribute *);
145086  extern void bus_remove_file(struct bus_type *, struct bus_attribute *);
145087
145088 +extern int __must_check bus_create_device_link(struct bus_type *bus,
145089 +                                              struct kobject *target,
145090 +                                              const char *name);
145091 +extern void bus_remove_device_link(struct bus_type *bus, const char *name);
145092 +
145093  struct bus_type {
145094         const char              *name;
145095         struct bus_attribute    *bus_attrs;
145096 --- a/include/linux/fb.h
145097 +++ b/include/linux/fb.h
145098 @@ -123,6 +123,7 @@ struct dentry;
145099  #define FB_ACCEL_TRIDENT_3DIMAGE 51    /* Trident 3DImage              */
145100  #define FB_ACCEL_TRIDENT_BLADE3D 52    /* Trident Blade3D              */
145101  #define FB_ACCEL_TRIDENT_BLADEXP 53    /* Trident BladeXP              */
145102 +#define FB_ACCEL_GLAMO         50      /* SMedia Glamo                 */
145103  #define FB_ACCEL_NEOMAGIC_NM2070 90    /* NeoMagic NM2070              */
145104  #define FB_ACCEL_NEOMAGIC_NM2090 91    /* NeoMagic NM2090              */
145105  #define FB_ACCEL_NEOMAGIC_NM2093 92    /* NeoMagic NM2093              */
145106 --- /dev/null
145107 +++ b/include/linux/glamofb.h
145108 @@ -0,0 +1,45 @@
145109 +#ifndef _LINUX_GLAMOFB_H
145110 +#define _LINUX_GLAMOFB_H
145111 +
145112 +#include <linux/spi/glamo.h>
145113 +
145114 +struct glamofb_val {
145115 +       unsigned int defval;
145116 +       unsigned int min;
145117 +       unsigned int max;
145118 +};
145119 +
145120 +struct glamo_core;
145121 +
145122 +struct glamofb_platform_data {
145123 +       int width, height;
145124 +       int pixclock;
145125 +       int left_margin, right_margin;
145126 +       int upper_margin, lower_margin;
145127 +       int hsync_len, vsync_len;
145128 +       int fb_mem_size;
145129 +
145130 +       struct glamofb_val xres;
145131 +       struct glamofb_val yres;
145132 +       struct glamofb_val bpp;
145133 +
145134 +       struct glamo_spi_info *spi_info;
145135 +       struct glamo_spigpio_info *spigpio_info;
145136 +       struct glamo_core *glamo;
145137 +
145138 +       struct platform_device *mmc_dev;
145139 +
145140 +       /* glamo mmc platform specific info */
145141 +       int             (*glamo_can_set_mci_power)(void);
145142 +
145143 +       /* glamo-mci asking if it should use the slow clock to card */
145144 +       int             (*glamo_mci_use_slow)(void);
145145 +       int             (*glamo_irq_is_wired)(void);
145146 +       void            (*glamo_external_reset)(int);
145147 +};
145148 +
145149 +int glamofb_cmd_mode(struct glamofb_handle *gfb, int on);
145150 +int glamofb_cmd_write(struct glamofb_handle *gfb, u_int16_t val);
145151 +void glamo_lcm_reset(int level);
145152 +
145153 +#endif
145154 --- /dev/null
145155 +++ b/include/linux/glamo-gpio.h
145156 @@ -0,0 +1,99 @@
145157 +#ifndef __GLAMO_GPIO_H
145158 +#define __GLAMO_GPIO_H
145159 +
145160 +struct glamo_core;
145161 +
145162 +#define GLAMO_GPIO_BANKA       0x0000
145163 +#define GLAMO_GPIO_BANKB       0x1000
145164 +#define GLAMO_GPIO_BANKC       0x2000
145165 +#define GLAMO_GPIO_BANKD       0x3000
145166 +
145167 +#define GLAMO_GPIONO(bank, pin)        ((bank & 0xf000) | ((pin & 0xf) << 8))
145168 +
145169 +#define GLAMO_GPIO_F_IN                0x0010
145170 +#define GLAMO_GPIO_F_OUT       0x0020
145171 +#define GLAMO_GPIO_F_FUNC      0x0030
145172 +
145173 +#define GLAMO_GPIO0            GLAMO_GPIONO(GLAMO_GPIO_BANKA, 0)
145174 +#define GLAMO_GPIO0_INPUT      (GLAMO_GPIO0 | GLAMO_GPIO_F_IN)
145175 +#define GLAMO_GPIO0_OUTPUT     (GLAMO_GPIO0 | GLAMO_GPIO_F_OUT)
145176 +#define GLAMO_GPIO0_HA20       (GLAMO_GPIO0 | GLAMO_GPIO_F_FUNC)
145177 +
145178 +#define GLAMO_GPIO1            GLAMO_GPIONO(GLAMO_GPIO_BANKA, 1)
145179 +#define GLAMO_GPIO1_INPUT      (GLAMO_GPIO1 | GLAMO_GPIO_F_IN)
145180 +#define GLAMO_GPIO1_OUTPUT     (GLAMO_GPIO1 | GLAMO_GPIO_F_OUT)
145181 +#define GLAMO_GPIO1_HA21       (GLAMO_GPIO1 | GLAMO_GPIO_F_FUNC)
145182 +
145183 +#define GLAMO_GPIO2            GLAMO_GPIONO(GLAMO_GPIO_BANKA, 2)
145184 +#define GLAMO_GPIO2_INPUT      (GLAMO_GPIO2 | GLAMO_GPIO_F_IN)
145185 +#define GLAMO_GPIO2_OUTPUT     (GLAMO_GPIO2 | GLAMO_GPIO_F_OUT)
145186 +#define GLAMO_GPIO2_HA22       (GLAMO_GPIO2 | GLAMO_GPIO_F_FUNC)
145187 +
145188 +#define GLAMO_GPIO3            GLAMO_GPIONO(GLAMO_GPIO_BANKA, 3)
145189 +#define GLAMO_GPIO3_INPUT      (GLAMO_GPIO3 | GLAMO_GPIO_F_IN)
145190 +#define GLAMO_GPIO3_OUTPUT     (GLAMO_GPIO3 | GLAMO_GPIO_F_OUT)
145191 +#define        GLAMO_GPIO3_HA23        (GLAMO_GPIO3 | GLAMO_GPIO_F_FUNC)
145192 +
145193 +#define GLAMO_GPIO4            GLAMO_GPIONO(GLAMO_GPIO_BANKB, 0)
145194 +#define GLAMO_GPIO4_INPUT      (GLAMO_GPIO4 | GLAMO_GPIO_F_IN)
145195 +#define GLAMO_GPIO4_OUTPUT     (GLAMO_GPIO4 | GLAMO_GPIO_F_OUT)
145196 +#define GLAMO_GPIO4_nLCS0      (GLAMO_GPIO4 | GLAMO_GPIO_F_FUNC)
145197 +
145198 +#define GLAMO_GPIO5            GLAMO_GPIONO(GLAMO_GPIO_BANKB, 1)
145199 +#define GLAMO_GPIO5_INPUT      (GLAMO_GPIO5 | GLAMO_GPIO_F_IN)
145200 +#define GLAMO_GPIO5_OUTPUT     (GLAMO_GPIO5 | GLAMO_GPIO_F_OUT)
145201 +#define GLAMO_GPIO5_nLCS1      (GLAMO_GPIO5 | GLAMO_GPIO_F_FUNC)
145202 +
145203 +#define GLAMO_GPIO6            GLAMO_GPIONO(GLAMO_GPIO_BANKB, 2)
145204 +#define GLAMO_GPIO6_INPUT      (GLAMO_GPIO6 | GLAMO_GPIO_F_IN)
145205 +#define GLAMO_GPIO6_OUTPUT     (GLAMO_GPIO6 | GLAMO_GPIO_F_OUT)
145206 +#define GLAMO_GPIO6_LDCLK      (GLAMO_GPIO6 | GLAMO_GPIO_F_FUNC)
145207 +
145208 +#define GLAMO_GPIO7            GLAMO_GPIONO(GLAMO_GPIO_BANKB, 3)
145209 +#define GLAMO_GPIO7_INPUT      (GLAMO_GPIO7 | GLAMO_GPIO_F_IN)
145210 +#define GLAMO_GPIO7_OUTPUT     (GLAMO_GPIO7 | GLAMO_GPIO_F_OUT)
145211 +#define GLAMO_GPIO7_nLDE       (GLAMO_GPIO7 | GLAMO_GPIO_F_FUNC)
145212 +
145213 +#define GLAMO_GPIO8            GLAMO_GPIONO(GLAMO_GPIO_BANKC, 0)
145214 +#define GLAMO_GPIO8_INPUT      (GLAMO_GPIO8 | GLAMO_GPIO_F_IN)
145215 +#define GLAMO_GPIO8_OUTPUT     (GLAMO_GPIO8 | GLAMO_GPIO_F_OUT)
145216 +#define GLAMO_GPIO8_LD16       (GLAMO_GPIO8 | GLAMO_GPIO_F_FUNC)
145217 +
145218 +#define GLAMO_GPIO9            GLAMO_GPIONO(GLAMO_GPIO_BANKC, 1)
145219 +#define GLAMO_GPIO9_INPUT      (GLAMO_GPIO9 | GLAMO_GPIO_F_IN)
145220 +#define GLAMO_GPIO9_OUTPUT     (GLAMO_GPIO9 | GLAMO_GPIO_F_OUT)
145221 +#define GLAMO_GPIO9_LD17       (GLAMO_GPIO9 | GLAMO_GPIO_F_FUNC)
145222 +
145223 +#define GLAMO_GPIO10           GLAMO_GPIONO(GLAMO_GPIO_BANKC, 2)
145224 +#define GLAMO_GPIO10_INPUT     (GLAMO_GPIO10 | GLAMO_GPIO_F_IN)
145225 +#define GLAMO_GPIO10_OUTPUT    (GLAMO_GPIO10 | GLAMO_GPIO_F_OUT)
145226 +#define GLAMO_GPIO10_LSCK      (GLAMO_GPIO10 | GLAMO_GPIO_F_FUNC)
145227 +
145228 +#define GLAMO_GPIO11           GLAMO_GPIONO(GLAMO_GPIO_BANKC, 3)
145229 +#define GLAMO_GPIO11_INPUT     (GLAMO_GPIO11 | GLAMO_GPIO_F_IN)
145230 +#define GLAMO_GPIO11_OUTPUT    (GLAMO_GPIO11 | GLAMO_GPIO_F_OUT)
145231 +#define GLAMO_GPIO11_LSDA      (GLAMO_GPIO11 | GLAMO_GPIO_F_FUNC)
145232 +
145233 +#define GLAMO_GPIO12           GLAMO_GPIONO(GLAMO_GPIO_BANKD, 0)
145234 +#define GLAMO_GPIO12_INPUT     (GLAMO_GPIO12 | GLAMO_GPIO_F_IN)
145235 +#define GLAMO_GPIO12_OUTPUT    (GLAMO_GPIO12 | GLAMO_GPIO_F_OUT)
145236 +#define GLAMO_GPIO12_LSA0      (GLAMO_GPIO12 | GLAMO_GPIO_F_FUNC)
145237 +
145238 +
145239 +#define REG_OF_GPIO(gpio)      (((gpio & 0xf000) >> 12)*2 \
145240 +                                               + GLAMO_REG_GPIO_GEN1)
145241 +#define NUM_OF_GPIO(gpio)      ((gpio & 0x0f00) >> 8)
145242 +#define GPIO_OUT_BIT(gpio)     (1 << (NUM_OF_GPIO(gpio) + 0))
145243 +#define OUTPUT_BIT(gpio)       (1 << (NUM_OF_GPIO(gpio) + 4))
145244 +#define INPUT_BIT(gpio)                (1 << (NUM_OF_GPIO(gpio) + 8))
145245 +#define FUNC_BIT(gpio)         (1 << (NUM_OF_GPIO(gpio) + 12))
145246 +
145247 +void glamo_gpio_setpin(struct glamo_core *glamo, unsigned int pin,
145248 +                      unsigned int value);
145249 +
145250 +int glamo_gpio_getpin(struct glamo_core *glamo, unsigned int pin);
145251 +
145252 +void glamo_gpio_cfgpin(struct glamo_core *glamo, unsigned int pinfunc);
145253 +
145254 +
145255 +#endif /* _GLAMO_GPIO */
145256 --- /dev/null
145257 +++ b/include/linux/gta02_hdq.h
145258 @@ -0,0 +1,18 @@
145259 +#ifndef __GTA02HDQ_H__
145260 +#define __GTA02HDQ_H__
145261 +
145262 +/* platform data */
145263 +
145264 +struct gta02_hdq_platform_data {
145265 +       /*
145266 +        * give an opportunity to use us as parent for
145267 +        * devices that depend on us
145268 +        */
145269 +       void (*attach_child_devices)(struct device *parent_device);
145270 +};
145271 +
145272 +int gta02hdq_read(int address);
145273 +int gta02hdq_write(int address, u8 data);
145274 +int gta02hdq_initialized(void);
145275 +
145276 +#endif
145277 --- a/include/linux/i2c-id.h
145278 +++ b/include/linux/i2c-id.h
145279 @@ -83,6 +83,9 @@
145280  #define I2C_DRIVERID_CS5345    96      /* cs5345 audio processor       */
145281
145282  #define I2C_DRIVERID_OV7670 1048       /* Omnivision 7670 camera */
145283 +#define I2C_DRIVERID_PCF50606 1049
145284 +#define I2C_DRIVERID_PCF50633 1051
145285 +#define I2C_DRIVERID_PCA9632  1052
145286
145287  /*
145288   * ---- Adapter types ----------------------------------------------------
145289 --- /dev/null
145290 +++ b/include/linux/jbt6k74.h
145291 @@ -0,0 +1,14 @@
145292 +#ifndef __JBT6K74_H__
145293 +#define __JBT6K74_H__
145294 +
145295 +#include <linux/spi/spi.h>
145296 +#include <linux/device.h>
145297 +
145298 +
145299 +struct jbt6k74_platform_data {
145300 +       void (*reset)(int devindex, int level);
145301 +       void (*resuming)(int devindex); /* called when LCM is resumed */
145302 +       void (*probe_completed)(struct device *dev);
145303 +};
145304 +
145305 +#endif
145306 --- a/include/linux/kernel.h
145307 +++ b/include/linux/kernel.h
145308 @@ -225,6 +225,8 @@ extern struct ratelimit_state printk_rat
145309  extern int printk_ratelimit(void);
145310  extern bool printk_timed_ratelimit(unsigned long *caller_jiffies,
145311                                    unsigned int interval_msec);
145312 +extern void (*printk_emergency_debug_spew_init)(void);
145313 +extern void (*printk_emergency_debug_spew_send_string)(const char *);
145314  #else
145315  static inline int vprintk(const char *s, va_list args)
145316         __attribute__ ((format (printf, 1, 0)));
145317 --- a/include/linux/kexec.h
145318 +++ b/include/linux/kexec.h
145319 @@ -1,7 +1,6 @@
145320  #ifndef LINUX_KEXEC_H
145321  #define LINUX_KEXEC_H
145322
145323 -#ifdef CONFIG_KEXEC
145324  #include <linux/types.h>
145325  #include <linux/list.h>
145326  #include <linux/linkage.h>
145327 @@ -11,6 +10,8 @@
145328  #include <linux/elf.h>
145329  #include <asm/kexec.h>
145330
145331 +#ifdef CONFIG_KEXEC
145332 +
145333  /* Verify architecture specific macros are defined */
145334
145335  #ifndef KEXEC_SOURCE_MEMORY_LIMIT
145336 --- /dev/null
145337 +++ b/include/linux/lis302dl.h
145338 @@ -0,0 +1,154 @@
145339 +#ifndef _LINUX_LIS302DL_H
145340 +#define _LINUX_LIS302DL_H
145341 +
145342 +#include <linux/types.h>
145343 +#include <linux/spi/spi.h>
145344 +#include <linux/input.h>
145345 +
145346 +
145347 +struct lis302dl_info;
145348 +
145349 +struct lis302dl_platform_data {
145350 +       char *name;
145351 +       unsigned long pin_chip_select;
145352 +       unsigned long pin_clk;
145353 +       unsigned long pin_mosi;
145354 +       unsigned long pin_miso;
145355 +       int open_drain;
145356 +       int interrupt;
145357 +       void (*lis302dl_bitbang)(struct lis302dl_info *lis, u8 *tx,
145358 +                       int tx_bytes, u8 *rx, int rx_bytes);
145359 +       void (*lis302dl_suspend_io)(struct lis302dl_info *, int resuming);
145360 +       int (*lis302dl_bitbang_reg_read)(struct lis302dl_info *, u8 reg);
145361 +       void (*lis302dl_bitbang_reg_write)(struct lis302dl_info *, u8 reg,
145362 +                                                                       u8 val);
145363 +};
145364 +
145365 +struct lis302dl_info {
145366 +       struct lis302dl_platform_data *pdata;
145367 +       struct device *dev;
145368 +       struct input_dev *input_dev;
145369 +       unsigned int flags;
145370 +       unsigned int threshold;
145371 +       unsigned int duration;
145372 +       struct {
145373 +               unsigned int threshold; /* mg */
145374 +               unsigned int duration;  /* ms */
145375 +       } wakeup;
145376 +       u_int8_t regs[0x40];
145377 +};
145378 +
145379 +enum lis302dl_reg {
145380 +       LIS302DL_REG_WHO_AM_I           = 0x0f,
145381 +       LIS302DL_REG_CTRL1              = 0x20,
145382 +       LIS302DL_REG_CTRL2              = 0x21,
145383 +       LIS302DL_REG_CTRL3              = 0x22,
145384 +       LIS302DL_REG_HP_FILTER_RESET    = 0x23,
145385 +       LIS302DL_REG_STATUS             = 0x27,
145386 +       LIS302DL_REG_OUT_X              = 0x29,
145387 +       LIS302DL_REG_OUT_Y              = 0x2b,
145388 +       LIS302DL_REG_OUT_Z              = 0x2d,
145389 +       LIS302DL_REG_FF_WU_CFG_1        = 0x30,
145390 +       LIS302DL_REG_FF_WU_SRC_1        = 0x31,
145391 +       LIS302DL_REG_FF_WU_THS_1        = 0x32,
145392 +       LIS302DL_REG_FF_WU_DURATION_1   = 0x33,
145393 +       LIS302DL_REG_FF_WU_CFG_2        = 0x34,
145394 +       LIS302DL_REG_FF_WU_SRC_2        = 0x35,
145395 +       LIS302DL_REG_FF_WU_THS_2        = 0x36,
145396 +       LIS302DL_REG_FF_WU_DURATION_2   = 0x37,
145397 +       LIS302DL_REG_CLICK_CFG          = 0x38,
145398 +       LIS302DL_REG_CLICK_SRC          = 0x39,
145399 +       LIS302DL_REG_CLICK_THSY_X       = 0x3b,
145400 +       LIS302DL_REG_CLICK_THSZ         = 0x3c,
145401 +       LIS302DL_REG_CLICK_TIME_LIMIT   = 0x3d,
145402 +       LIS302DL_REG_CLICK_LATENCY      = 0x3e,
145403 +       LIS302DL_REG_CLICK_WINDOW       = 0x3f,
145404 +};
145405 +
145406 +enum lis302dl_reg_ctrl1 {
145407 +       LIS302DL_CTRL1_Xen              = 0x01,
145408 +       LIS302DL_CTRL1_Yen              = 0x02,
145409 +       LIS302DL_CTRL1_Zen              = 0x04,
145410 +       LIS302DL_CTRL1_STM              = 0x08,
145411 +       LIS302DL_CTRL1_STP              = 0x10,
145412 +       LIS302DL_CTRL1_FS               = 0x20,
145413 +       LIS302DL_CTRL1_PD               = 0x40,
145414 +       LIS302DL_CTRL1_DR               = 0x80,
145415 +};
145416 +
145417 +enum lis302dl_reg_ctrl2 {
145418 +       LIS302DL_CTRL2_HPC1             = 0x01,
145419 +       LIS302DL_CTRL2_HPC2             = 0x02,
145420 +       LIS302DL_CTRL2_HPFF1            = 0x04,
145421 +       LIS302DL_CTRL2_HPFF2            = 0x08,
145422 +       LIS302DL_CTRL2_FDS              = 0x10,
145423 +       LIS302DL_CTRL2_BOOT             = 0x40,
145424 +       LIS302DL_CTRL2_SIM              = 0x80,
145425 +};
145426 +enum lis302dl_reg_ctrl3 {
145427 +       LIS302DL_CTRL3_PP_OD            = 0x40,
145428 +       LIS302DL_CTRL3_IHL              = 0x80,
145429 +};
145430 +
145431 +enum lis302dl_reg_status {
145432 +       LIS302DL_STATUS_XDA             = 0x01,
145433 +       LIS302DL_STATUS_YDA             = 0x02,
145434 +       LIS302DL_STATUS_ZDA             = 0x04,
145435 +       LIS302DL_STATUS_XYZDA           = 0x08,
145436 +       LIS302DL_STATUS_XOR             = 0x10,
145437 +       LIS302DL_STATUS_YOR             = 0x20,
145438 +       LIS302DL_STATUS_ZOR             = 0x40,
145439 +       LIS302DL_STATUS_XYZOR           = 0x80,
145440 +};
145441 +
145442 +/* Wakeup/freefall interrupt defs */
145443 +enum lis302dl_reg_ffwucfg {
145444 +       LIS302DL_FFWUCFG_XLIE           = 0x01,
145445 +       LIS302DL_FFWUCFG_XHIE           = 0x02,
145446 +       LIS302DL_FFWUCFG_YLIE           = 0x04,
145447 +       LIS302DL_FFWUCFG_YHIE           = 0x08,
145448 +       LIS302DL_FFWUCFG_ZLIE           = 0x10,
145449 +       LIS302DL_FFWUCFG_ZHIE           = 0x20,
145450 +       LIS302DL_FFWUCFG_LIR            = 0x40,
145451 +       LIS302DL_FFWUCFG_AOI            = 0x80,
145452 +};
145453 +
145454 +enum lis302dl_reg_ffwuths {
145455 +       LIS302DL_FFWUTHS_DCRM           = 0x80,
145456 +};
145457 +
145458 +enum lis302dl_reg_ffwusrc {
145459 +       LIS302DL_FFWUSRC_XL             = 0x01,
145460 +       LIS302DL_FFWUSRC_XH             = 0x02,
145461 +       LIS302DL_FFWUSRC_YL             = 0x04,
145462 +       LIS302DL_FFWUSRC_YH             = 0x08,
145463 +       LIS302DL_FFWUSRC_ZL             = 0x10,
145464 +       LIS302DL_FFWUSRC_ZH             = 0x20,
145465 +       LIS302DL_FFWUSRC_IA             = 0x40,
145466 +};
145467 +
145468 +enum lis302dl_reg_cloik_src {
145469 +       LIS302DL_CLICKSRC_SINGLE_X      = 0x01,
145470 +       LIS302DL_CLICKSRC_DOUBLE_X      = 0x02,
145471 +       LIS302DL_CLICKSRC_SINGLE_Y      = 0x04,
145472 +       LIS302DL_CLICKSRC_DOUBLE_Y      = 0x08,
145473 +       LIS302DL_CLICKSRC_SINGLE_Z      = 0x10,
145474 +       LIS302DL_CLICKSRC_DOUBLE_Z      = 0x20,
145475 +       LIS302DL_CLICKSRC_IA            = 0x40,
145476 +};
145477 +
145478 +#define LIS302DL_WHO_AM_I_MAGIC                0x3b
145479 +
145480 +#define LIS302DL_F_WUP_FF_1            0x0001  /* wake up from free fall */
145481 +#define LIS302DL_F_WUP_FF_2            0x0002
145482 +#define LIS302DL_F_WUP_FF              0x0003
145483 +#define LIS302DL_F_WUP_CLICK   0x0004
145484 +#define LIS302DL_F_POWER               0x0010
145485 +#define LIS302DL_F_FS                  0x0020  /* ADC full scale */
145486 +#define LIS302DL_F_INPUT_OPEN  0x0040  /* Set if input device is opened */
145487 +#define LIS302DL_F_IRQ_WAKE    0x0080  /* IRQ is setup in wake mode */
145488 +#define LIS302DL_F_DR                  0x0100  /* Data rate, 400Hz/100Hz */
145489 +
145490 +
145491 +#endif /* _LINUX_LIS302DL_H */
145492 +
145493 --- /dev/null
145494 +++ b/include/linux/logger.h
145495 @@ -0,0 +1,48 @@
145496 +/* include/linux/logger.h
145497 + *
145498 + * Copyright (C) 2007-2008 Google, Inc.
145499 + * Author: Robert Love <rlove@android.com>
145500 + *
145501 + * This software is licensed under the terms of the GNU General Public
145502 + * License version 2, as published by the Free Software Foundation, and
145503 + * may be copied, distributed, and modified under those terms.
145504 + *
145505 + * This program is distributed in the hope that it will be useful,
145506 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
145507 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
145508 + * GNU General Public License for more details.
145509 + *
145510 + */
145511 +
145512 +#ifndef _LINUX_LOGGER_H
145513 +#define _LINUX_LOGGER_H
145514 +
145515 +#include <linux/types.h>
145516 +#include <linux/ioctl.h>
145517 +
145518 +struct logger_entry {
145519 +       __u16           len;    /* length of the payload */
145520 +       __u16           __pad;  /* no matter what, we get 2 bytes of padding */
145521 +       __s32           pid;    /* generating process's pid */
145522 +       __s32           tid;    /* generating process's tid */
145523 +       __s32           sec;    /* seconds since Epoch */
145524 +       __s32           nsec;   /* nanoseconds */
145525 +       char            msg[0]; /* the entry's payload */
145526 +};
145527 +
145528 +#define LOGGER_LOG_RADIO       "log_radio"     /* radio-related messages */
145529 +#define LOGGER_LOG_EVENTS      "log_events"    /* system/hardware events */
145530 +#define LOGGER_LOG_MAIN                "log_main"      /* everything else */
145531 +
145532 +#define LOGGER_ENTRY_MAX_LEN           (4*1024)
145533 +#define LOGGER_ENTRY_MAX_PAYLOAD       \
145534 +       (LOGGER_ENTRY_MAX_LEN - sizeof(struct logger_entry))
145535 +
145536 +#define __LOGGERIO     0xAE
145537 +
145538 +#define LOGGER_GET_LOG_BUF_SIZE                _IO(__LOGGERIO, 1) /* size of log */
145539 +#define LOGGER_GET_LOG_LEN             _IO(__LOGGERIO, 2) /* used log len */
145540 +#define LOGGER_GET_NEXT_ENTRY_LEN      _IO(__LOGGERIO, 3) /* next entry len */
145541 +#define LOGGER_FLUSH_LOG               _IO(__LOGGERIO, 4) /* flush log */
145542 +
145543 +#endif /* _LINUX_LOGGER_H */
145544 --- /dev/null
145545 +++ b/include/linux/mfd/pcf50606/adc.h
145546 @@ -0,0 +1,87 @@
145547 +/*
145548 + * adc.h  -- Driver for NXP PCF50606 ADC
145549 + *
145550 + * (C) 2006-2008 by Openmoko, Inc.
145551 + * All rights reserved.
145552 + *
145553 + * This program is free software; you can redistribute  it and/or modify it
145554 + * under  the terms of  the GNU General  Public License as published by the
145555 + * Free Software Foundation;  either version 2 of the  License, or (at your
145556 + * option) any later version.
145557 + */
145558 +
145559 +#ifndef __LINUX_MFD_PCF50606_ADC_H
145560 +#define __LINUX_MFD_PCF50606_ADC_H
145561 +
145562 +#include <linux/platform_device.h>
145563 +
145564 +/* ADC Registers */
145565 +#define PCF50606_REG_ADCC1 0x2e
145566 +#define PCF50606_REG_ADCC2 0x2f
145567 +#define PCF50606_REG_ADCS1 0x30
145568 +#define PCF50606_REG_ADCS2 0x31
145569 +#define PCF50606_REG_ADCS3 0x32
145570 +
145571 +#define PCF50606_ADCC1_TSCMODACT        0x01
145572 +#define PCF50606_ADCC1_TSCMODSTB        0x02
145573 +#define PCF50606_ADCC1_TRATSET          0x04
145574 +#define PCF50606_ADCC1_NTCSWAPE                 0x08
145575 +#define PCF50606_ADCC1_NTCSWAOFF        0x10
145576 +#define PCF50606_ADCC1_EXTSYNCBREAK     0x20
145577 +       /* reserved */
145578 +#define PCF50606_ADCC1_TSCINT           0x80
145579 +
145580 +#define PCF50606_ADCC2_ADCSTART                 0x01
145581 +       /* see enum pcf50606_adcc2_adcmux */
145582 +#define PCF50606_ADCC2_SYNC_NONE        0x00
145583 +#define PCF50606_ADCC2_SYNC_TXON        0x20
145584 +#define PCF50606_ADCC2_SYNC_PWREN1      0x40
145585 +#define PCF50606_ADCC2_SYNC_PWREN2      0x60
145586 +#define PCF50606_ADCC2_RES_10BIT        0x00
145587 +#define PCF50606_ADCC2_RES_8BIT                 0x80
145588 +
145589 +#define PCF50606_ADCC2_ADCMUX_MASK     (0xf << 1)
145590 +
145591 +#define ADCMUX_SHIFT   1
145592 +#define PCF50606_ADCMUX_BATVOLT_RES     (0x0 << ADCMUX_SHIFT)
145593 +#define PCF50606_ADCMUX_BATVOLT_SUBTR   (0x1 << ADCMUX_SHIFT)
145594 +#define PCF50606_ADCMUX_ADCIN1_RES      (0x2 << ADCMUX_SHIFT)
145595 +#define PCF50606_ADCMUX_ADCIN1_SUBTR    (0x3 << ADCMUX_SHIFT)
145596 +#define PCF50606_ADCMUX_BATTEMP                 (0x4 << ADCMUX_SHIFT)
145597 +#define PCF50606_ADCMUX_ADCIN2          (0x5 << ADCMUX_SHIFT)
145598 +#define PCF50606_ADCMUX_ADCIN3          (0x6 << ADCMUX_SHIFT)
145599 +#define PCF50606_ADCMUX_ADCIN3_RATIO    (0x7 << ADCMUX_SHIFT)
145600 +#define PCF50606_ADCMUX_XPOS            (0x8 << ADCMUX_SHIFT)
145601 +#define PCF50606_ADCMUX_YPOS            (0x9 << ADCMUX_SHIFT)
145602 +#define PCF50606_ADCMUX_P1              (0xa << ADCMUX_SHIFT)
145603 +#define PCF50606_ADCMUX_P2              (0xb << ADCMUX_SHIFT)
145604 +#define PCF50606_ADCMUX_BATVOLT_ADCIN1  (0xc << ADCMUX_SHIFT)
145605 +#define PCF50606_ADCMUX_XY_SEQUENCE     (0xe << ADCMUX_SHIFT)
145606 +#define PCF50606_P1_P2_RESISTANCE       (0xf << ADCMUX_SHIFT)
145607 +
145608 +#define PCF50606_ADCS2_ADCRDY           0x80
145609 +
145610 +struct pcf50606;
145611 +
145612 +#define PCF50606_MAX_ADC_FIFO_DEPTH 8
145613 +
145614 +struct pcf50606_adc_request;
145615 +
145616 +struct pcf50606_adc {
145617 +       struct platform_device *pdev;
145618 +
145619 +       /* Private stuff */
145620 +       struct pcf50606_adc_request *queue[PCF50606_MAX_ADC_FIFO_DEPTH];
145621 +       int queue_head;
145622 +       int queue_tail;
145623 +       struct mutex queue_mutex;
145624 +};
145625 +
145626 +extern int
145627 +pcf50606_adc_async_read(struct pcf50606 *pcf, int mux, int avg,
145628 +               void (*callback)(struct pcf50606 *, void *, int),
145629 +               void *callback_param);
145630 +extern int
145631 +pcf50606_adc_sync_read(struct pcf50606 *pcf, int mux, int avg);
145632 +
145633 +#endif /* __LINUX_PCF50606_ADC_H */
145634 --- /dev/null
145635 +++ b/include/linux/mfd/pcf50606/core.h
145636 @@ -0,0 +1,163 @@
145637 +/*
145638 + * core.h  -- Core driver for NXP PCF50606
145639 + *
145640 + * (C) 2006-2008 by Openmoko, Inc.
145641 + * All rights reserved.
145642 + *
145643 + * This program is free software; you can redistribute  it and/or modify it
145644 + * under  the terms of  the GNU General  Public License as published by the
145645 + * Free Software Foundation;  either version 2 of the  License, or (at your
145646 + * option) any later version.
145647 + */
145648 +
145649 +#ifndef __LINUX_MFD_PCF50606_CORE_H
145650 +#define __LINUX_MFD_PCF50606_CORE_H
145651 +
145652 +#include <linux/i2c.h>
145653 +#include <linux/workqueue.h>
145654 +#include <linux/regulator/driver.h>
145655 +#include <linux/regulator/machine.h>
145656 +#include <linux/power_supply.h>
145657 +
145658 +#include <linux/mfd/pcf50606/pmic.h>
145659 +#include <linux/mfd/pcf50606/input.h>
145660 +#include <linux/mfd/pcf50606/mbc.h>
145661 +#include <linux/mfd/pcf50606/rtc.h>
145662 +#include <linux/mfd/pcf50606/adc.h>
145663 +#include <linux/mfd/pcf50606/wdt.h>
145664 +
145665 +struct pcf50606;
145666 +
145667 +struct pcf50606_platform_data {
145668 +       struct regulator_init_data reg_init_data[PCF50606_NUM_REGULATORS];
145669 +
145670 +       char **batteries;
145671 +       int num_batteries;
145672 +
145673 +       /* Callbacks */
145674 +       void (*probe_done)(struct pcf50606 *);
145675 +       void (*mbc_event_callback)(struct pcf50606 *, int);
145676 +       void (*regulator_registered)(struct pcf50606 *, int);
145677 +       void (*force_shutdown)(struct pcf50606 *);
145678 +
145679 +       u8 resumers[3];
145680 +
145681 +       /* Runtime data - filled by driver afer probe */
145682 +       struct pcf50606 *pcf;
145683 +};
145684 +
145685 +struct pcf50606_irq {
145686 +       void (*handler)(struct pcf50606 *, int, void *);
145687 +       void *data;
145688 +};
145689 +
145690 +int pcf50606_irq_mask(struct pcf50606 *pcf, int irq);
145691 +int pcf50606_irq_unmask(struct pcf50606 *pcf, int irq);
145692 +int pcf50606_irq_mask_get(struct pcf50606 *pcf, int irq);
145693 +
145694 +int pcf50606_read_block(struct pcf50606 *, u8 reg,
145695 +                                       int nr_regs, u8 *data);
145696 +int pcf50606_write_block(struct pcf50606 *pcf, u8 reg,
145697 +                                       int nr_regs, u8 *data);
145698 +u8 pcf50606_reg_read(struct pcf50606 *, u8 reg);
145699 +int pcf50606_reg_write(struct pcf50606 *pcf, u8 reg, u8 val);
145700 +
145701 +int pcf50606_reg_set_bit_mask(struct pcf50606 *pcf, u8 reg, u8 mask, u8 val);
145702 +int pcf50606_reg_clear_bits(struct pcf50606 *pcf, u8 reg, u8 bits);
145703 +
145704 +/* Interrupt registers */
145705 +
145706 +#define PCF50606_REG_INT1      0x02
145707 +#define        PCF50606_REG_INT2       0x03
145708 +#define        PCF50606_REG_INT3       0x04
145709 +
145710 +#define PCF50606_REG_INT1M     0x05
145711 +#define        PCF50606_REG_INT2M      0x06
145712 +#define        PCF50606_REG_INT3M      0x07
145713 +
145714 +enum {
145715 +       /* Chip IRQs */
145716 +       PCF50606_IRQ_ONKEYR,
145717 +       PCF50606_IRQ_ONKEYF,
145718 +       PCF50606_IRQ_ONKEY1S,
145719 +       PCF50606_IRQ_EXTONR,
145720 +       PCF50606_IRQ_EXTONF,
145721 +       PCF50606_IRQ_SECOND,
145722 +       PCF50606_IRQ_ALARM,
145723 +       PCF50606_IRQ_CHGINS,
145724 +       PCF50606_IRQ_CHGRM,
145725 +       PCF50606_IRQ_CHGFOK,
145726 +       PCF50606_IRQ_CHGERR,
145727 +       PCF50606_IRQ_CHGFRDY,
145728 +       PCF50606_IRQ_CHGPROT,
145729 +       PCF50606_IRQ_CHGWD10S,
145730 +       PCF50606_IRQ_CHGWDEXP,
145731 +       PCF50606_IRQ_ADCRDY,
145732 +       PCF50606_IRQ_ACDINS,
145733 +       PCF50606_IRQ_ACDREM,
145734 +       PCF50606_IRQ_TSCPRES,
145735 +       PCF50606_IRQ_LOWBAT,
145736 +       PCF50606_IRQ_HIGHTMP,
145737 +
145738 +       /* Always last */
145739 +       PCF50606_NUM_IRQ,
145740 +};
145741 +
145742 +struct pcf50606 {
145743 +       struct device *dev;
145744 +       struct i2c_client *i2c_client;
145745 +
145746 +       struct pcf50606_platform_data *pdata;
145747 +       int irq;
145748 +       struct pcf50606_irq irq_handler[PCF50606_NUM_IRQ];
145749 +       struct work_struct irq_work;
145750 +       struct mutex lock;
145751 +
145752 +       u8 mask_regs[3];
145753 +
145754 +       u8 suspend_irq_masks[3];
145755 +       u8 resume_reason[3];
145756 +       int is_suspended;
145757 +
145758 +       int onkey1s_held;
145759 +
145760 +       struct pcf50606_pmic pmic;
145761 +       struct pcf50606_input input;
145762 +       struct pcf50606_mbc mbc;
145763 +       struct pcf50606_rtc rtc;
145764 +       struct pcf50606_adc adc;
145765 +       struct pcf50606_wdt wdt;
145766 +};
145767 +
145768 +enum pcf50606_reg_int1 {
145769 +       PCF50606_INT1_ONKEYR    = 0x01, /* ONKEY rising edge */
145770 +       PCF50606_INT1_ONKEYF    = 0x02, /* ONKEY falling edge */
145771 +       PCF50606_INT1_ONKEY1S   = 0x04, /* OMKEY at least 1sec low */
145772 +       PCF50606_INT1_EXTONR    = 0x08, /* EXTON rising edge */
145773 +       PCF50606_INT1_EXTONF    = 0x10, /* EXTON falling edge */
145774 +       PCF50606_INT1_SECOND    = 0x40, /* RTC periodic second interrupt */
145775 +       PCF50606_INT1_ALARM     = 0x80, /* RTC alarm time is reached */
145776 +};
145777 +
145778 +enum pcf50606_reg_int2 {
145779 +       PCF50606_INT2_CHGINS    = 0x01, /* Charger inserted */
145780 +       PCF50606_INT2_CHGRM     = 0x02, /* Charger removed */
145781 +       PCF50606_INT2_CHGFOK    = 0x04, /* Fast charging OK */
145782 +       PCF50606_INT2_CHGERR    = 0x08, /* Error in charging mode */
145783 +       PCF50606_INT2_CHGFRDY   = 0x10, /* Fast charge completed */
145784 +       PCF50606_INT2_CHGPROT   = 0x20, /* Charging protection interrupt */
145785 +       PCF50606_INT2_CHGWD10S  = 0x40, /* Charger watchdig expires in 10s */
145786 +       PCF50606_INT2_CHGWDEXP  = 0x80, /* Charger watchdog expires */
145787 +};
145788 +
145789 +enum pcf50606_reg_int3 {
145790 +       PCF50606_INT3_ADCRDY    = 0x01, /* ADC conversion finished */
145791 +       PCF50606_INT3_ACDINS    = 0x02, /* Accessory inserted */
145792 +       PCF50606_INT3_ACDREM    = 0x04, /* Accessory removed */
145793 +       PCF50606_INT3_TSCPRES   = 0x08, /* Touch screen pressed */
145794 +       PCF50606_INT3_LOWBAT    = 0x40, /* Low battery voltage */
145795 +       PCF50606_INT3_HIGHTMP   = 0x80, /* High temperature */
145796 +};
145797 +
145798 +#endif
145799 +
145800 --- /dev/null
145801 +++ b/include/linux/mfd/pcf50606/gpo.h
145802 @@ -0,0 +1,43 @@
145803 +/*
145804 + * gpo.h -- GPO driver for NXP PCF50606
145805 + *
145806 + * (C) 2006-2008 by Openmoko, Inc.
145807 + * All rights reserved.
145808 + *
145809 + * This program is free software; you can redistribute  it and/or modify it
145810 + * under  the terms of  the GNU General  Public License as published by the
145811 + * Free Software Foundation;  either version 2 of the  License, or (at your
145812 + * option) any later version.
145813 + */
145814 +
145815 +#ifndef __LINUX_MFD_PCF50606_GPO_H
145816 +#define __LINUX_MFD_PCF50606_GPO_H
145817 +
145818 +#define PCF50606_REG_GPOC1 0x38
145819 +#define PCF50606_REG_GPOC2 0x39
145820 +#define PCF50606_REG_GPOC3 0x3a
145821 +#define PCF50606_REG_GPOC4 0x3b
145822 +#define PCF50606_REG_GPOC5 0x3c
145823 +
145824 +#define PCF50606_GPO1  PCF50606_REG_GPOC1
145825 +#define PCF50606_GPO2  PCF50606_REG_GPOC1
145826 +#define PCF50606_GPOOD1        PCF50606_REG_GPOC2
145827 +#define PCF50606_GPOOD2        PCF50606_REG_GPOC3
145828 +#define PCF50606_GPOOD3        PCF50606_REG_GPOC4
145829 +#define PCF50606_GPOOD4        PCF50606_REG_GPOC5
145830 +
145831 +#define PCF50606_GPOCFG_GPOSEL_MASK    0x07
145832 +
145833 +struct pcf50606;
145834 +
145835 +void pcf50606_gpo_set_active(struct pcf50606 *pcf, int gpo, int value);
145836 +int pcf50606_gpo_get_active(struct pcf50606 *pcf, int gpo);
145837 +void pcf50606_gpo_set_standby(struct pcf50606 *pcf, int gpo, int value);
145838 +int pcf50606_gpo_get_standby(struct pcf50606 *pcf, int gpo);
145839 +
145840 +void pcf50606_gpo_invert_set(struct pcf50606 *, int gpo, int invert);
145841 +int pcf50606_gpo_invert_get(struct pcf50606 *pcf, int gpo);
145842 +
145843 +#endif /* __LINUX_MFD_PCF50606_GPIO_H */
145844 +
145845 +
145846 --- /dev/null
145847 +++ b/include/linux/mfd/pcf50606/input.h
145848 @@ -0,0 +1,37 @@
145849 +/*
145850 + * input.h  -- Input driver for NXP PCF50606
145851 + *
145852 + * (C) 2006-2008 by Openmoko, Inc.
145853 + * All rights reserved.
145854 + *
145855 + * This program is free software; you can redistribute  it and/or modify it
145856 + * under  the terms of  the GNU General  Public License as published by the
145857 + * Free Software Foundation;  either version 2 of the  License, or (at your
145858 + * option) any later version.
145859 + */
145860 +
145861 +#ifndef __LINUX_MFD_PCF50606_INPUT_H
145862 +#define __LINUX_MFD_PCF50606_INPUT_H
145863 +
145864 +#include <linux/platform_device.h>
145865 +#include <linux/input.h>
145866 +
145867 +#define PFC50606_OOCS_ONKEY     0x01
145868 +#define PCF50606_OOCS_EXTON     0x02
145869 +
145870 +#define PCF50606_OOCC2_ONKEYDB_NONE     0x00
145871 +#define PCF50606_OOCC2_ONKEYDB_14ms     0x01
145872 +#define PCF50606_OOCC2_ONKEYDB_62ms     0x02
145873 +#define PCF50606_OOCC2_ONKEYDB_500ms    0x03
145874 +#define PCF50606_OOCC2_EXTONDB_NONE     0x00
145875 +#define PCF50606_OOCC2_EXTONDB_14ms     0x04
145876 +#define PCF50606_OOCC2_EXTONDB_62ms     0x08
145877 +#define PCF50606_OOCC2_EXTONDB_500ms    0x0c
145878 +
145879 +struct pcf50606_input {
145880 +       struct input_dev *input_dev;
145881 +       struct platform_device *pdev;
145882 +};
145883 +
145884 +#endif
145885 +
145886 --- /dev/null
145887 +++ b/include/linux/mfd/pcf50606/led.h
145888 @@ -0,0 +1,22 @@
145889 +/*
145890 + * led.h  -- LED driver for NXP PCF50606
145891 + *
145892 + * (C) 2006-2008 by Openmoko, Inc.
145893 + * All rights reserved.
145894 + *
145895 + * This program is free software; you can redistribute  it and/or modify it
145896 + * under  the terms of  the GNU General  Public License as published by the
145897 + * Free Software Foundation;  either version 2 of the  License, or (at your
145898 + * option) any later version.
145899 + */
145900 +
145901 +#ifndef __LINUX_MFD_PCF50606_LED_H
145902 +#define __LINUX_MFD_PCF50606_LED_H
145903 +
145904 +#define PCF50606_REG_LEDC1 0x36
145905 +#define PCF50606_REG_LEDC2 0x37
145906 +
145907 +#include <linux/platform_device.h>
145908 +
145909 +#endif
145910 +
145911 --- /dev/null
145912 +++ b/include/linux/mfd/pcf50606/mbc.h
145913 @@ -0,0 +1,53 @@
145914 +/*
145915 + * mbc.h  -- Driver for NXP PCF50606 Main Battery Charger
145916 + *
145917 + * (C) 2006-2008 by Openmoko, Inc.
145918 + * All rights reserved.
145919 + *
145920 + * This program is free software; you can redistribute  it and/or modify it
145921 + * under  the terms of  the GNU General  Public License as published by the
145922 + * Free Software Foundation;  either version 2 of the  License, or (at your
145923 + * option) any later version.
145924 + */
145925 +
145926 +#ifndef __LINUX_MFD_PCF50606_MBC_H
145927 +#define __LINUX_MFD_PCF50606_MBC_H
145928 +
145929 +#include <linux/platform_device.h>
145930 +
145931 +#define PCF50606_REG_MBCC1      0x29
145932 +#define PCF50606_REG_MBCC2      0x2a
145933 +#define PCF50606_REG_MBCC3      0x2b
145934 +#define PCF50606_REG_MBCS1      0x2c
145935 +
145936 +enum pcf50606_reg_mbcc1 {
145937 +       PCF50606_MBCC1_CHGAPE           = 0x01,
145938 +       PCF50606_MBCC1_AUTOFST          = 0x02,
145939 +#define        PCF50606_MBCC1_CHGMOD_MASK        0x1c
145940 +#define        PCF50606_MBCC1_CHGMOD_SHIFT       2
145941 +       PCF50606_MBCC1_CHGMOD_QUAL      = 0x00,
145942 +       PCF50606_MBCC1_CHGMOD_PRE       = 0x04,
145943 +       PCF50606_MBCC1_CHGMOD_TRICKLE   = 0x08,
145944 +       PCF50606_MBCC1_CHGMOD_FAST_CCCV = 0x0c,
145945 +       PCF50606_MBCC1_CHGMOD_FAST_NOCC = 0x10,
145946 +       PCF50606_MBCC1_CHGMOD_FAST_NOCV = 0x14,
145947 +       PCF50606_MBCC1_CHGMOD_FAST_SW   = 0x18,
145948 +       PCF50606_MBCC1_CHGMOD_IDLE      = 0x1c,
145949 +       PCF50606_MBCC1_DETMOD_LOWCHG    = 0x20,
145950 +       PCF50606_MBCC1_DETMOD_WDRST     = 0x40,
145951 +};
145952 +
145953 +struct pcf50606;
145954 +
145955 +void pcf50606_mbc_usb_curlim_set(struct pcf50606 *pcf, int ma);
145956 +
145957 +struct pcf50606_mbc {
145958 +       int charger_online;
145959 +       int charger_active;
145960 +
145961 +       struct power_supply charger;
145962 +
145963 +       struct platform_device *pdev;
145964 +};
145965 +#endif
145966 +
145967 --- /dev/null
145968 +++ b/include/linux/mfd/pcf50606/pmic.h
145969 @@ -0,0 +1,82 @@
145970 +#ifndef __LINUX_MFD_PCF50606_PMIC_H
145971 +#define __LINUX_MFD_PCF50606_PMIC_H
145972 +
145973 +#include <linux/platform_device.h>
145974 +
145975 +#define PCF50606_REG_DCDC1      0x1b
145976 +#define PCF50606_REG_DCDC2      0x1c
145977 +#define PCF50606_REG_DCDC3      0x1d
145978 +#define PCF50606_REG_DCDC4      0x1e
145979 +#define PCF50606_REG_DCDEC1     0x1f
145980 +#define PCF50606_REG_DCDEC2     0x20
145981 +#define PCF50606_REG_DCUDC1     0x21
145982 +#define PCF50606_REG_DCUDC2     0x22
145983 +#define PCF50606_REG_IOREGC     0x23
145984 +#define PCF50606_REG_D1REGC1    0x24
145985 +#define PCF50606_REG_D2REGC1    0x25
145986 +#define PCF50606_REG_D3REGC1    0x26
145987 +#define PCF50606_REG_LPREGC1    0x27
145988 +#define PCF50606_REG_LPREGC2    0x28
145989 +
145990 +/* used by PSSC, PWROKM, PWROKS, */
145991 +enum pcf50606_regu {
145992 +       PCF50606_REGU_DCD       = 0x01, /* DCD in phase 2 */
145993 +       PCF50606_REGU_DCDE      = 0x02, /* DCDE in phase 2 */
145994 +       PCF50606_REGU_DCUD      = 0x04, /* DCDU in phase 2 */
145995 +       PCF50606_REGU_IO        = 0x08, /* IO in phase 2 */
145996 +       PCF50606_REGU_D1        = 0x10, /* D1 in phase 2 */
145997 +       PCF50606_REGU_D2        = 0x20, /* D2 in phase 2 */
145998 +       PCF50606_REGU_D3        = 0x40, /* D3 in phase 2 */
145999 +       PCF50606_REGU_LP        = 0x80, /* LP in phase 2 */
146000 +};
146001 +
146002 +enum pcf50606_reg_dcdc4 {
146003 +       PCF50606_DCDC4_MODE_AUTO        = 0x00,
146004 +       PCF50606_DCDC4_MODE_PWM         = 0x01,
146005 +       PCF50606_DCDC4_MODE_PCF         = 0x02,
146006 +       PCF50606_DCDC4_OFF_FLOAT        = 0x00,
146007 +       PCF50606_DCDC4_OFF_BYPASS       = 0x04,
146008 +       PCF50606_DCDC4_OFF_PULLDOWN     = 0x08,
146009 +       PCF50606_DCDC4_CURLIM_500mA     = 0x00,
146010 +       PCF50606_DCDC4_CURLIM_750mA     = 0x10,
146011 +       PCF50606_DCDC4_CURLIM_1000mA    = 0x20,
146012 +       PCF50606_DCDC4_CURLIM_1250mA    = 0x30,
146013 +       PCF50606_DCDC4_TOGGLE           = 0x40,
146014 +       PCF50606_DCDC4_REGSEL_DCDC2     = 0x80,
146015 +};
146016 +
146017 +enum pcf50606_reg_dcdec2 {
146018 +       PCF50606_DCDEC2_MODE_AUTO       = 0x00,
146019 +       PCF50606_DCDEC2_MODE_PWM        = 0x01,
146020 +       PCF50606_DCDEC2_MODE_PCF        = 0x02,
146021 +       PCF50606_DCDEC2_OFF_FLOAT       = 0x00,
146022 +       PCF50606_DCDEC2_OFF_BYPASS      = 0x04,
146023 +};
146024 +
146025 +enum pcf50606_reg_dcudc2 {
146026 +       PCF50606_DCUDC2_MODE_AUTO       = 0x00,
146027 +       PCF50606_DCUDC2_MODE_PWM        = 0x01,
146028 +       PCF50606_DCUDC2_MODE_PCF        = 0x02,
146029 +       PCF50606_DCUDC2_OFF_FLOAT       = 0x00,
146030 +       PCF50606_DCUDC2_OFF_BYPASS      = 0x04,
146031 +};
146032 +
146033 +enum pcf50606_regulator_id {
146034 +       PCF50606_REGULATOR_DCD,
146035 +       PCF50606_REGULATOR_DCDE,
146036 +       PCF50606_REGULATOR_DCUD,
146037 +       PCF50606_REGULATOR_D1REG,
146038 +       PCF50606_REGULATOR_D2REG,
146039 +       PCF50606_REGULATOR_D3REG,
146040 +       PCF50606_REGULATOR_LPREG,
146041 +       PCF50606_REGULATOR_IOREG,
146042 +
146043 +       /* Always last */
146044 +       PCF50606_NUM_REGULATORS
146045 +};
146046 +
146047 +struct pcf50606_pmic {
146048 +       struct platform_device *pdev[PCF50606_NUM_REGULATORS];
146049 +};
146050 +#endif
146051 +
146052 --- /dev/null
146053 +++ b/include/linux/mfd/pcf50606/rtc.h
146054 @@ -0,0 +1,43 @@
146055 +/*
146056 + * rtc.h  -- RTC driver for NXP PCF50606
146057 + *
146058 + * (C) 2006-2008 by Openmoko, Inc.
146059 + * All rights reserved.
146060 + *
146061 + * This program is free software; you can redistribute  it and/or modify it
146062 + * under  the terms of  the GNU General  Public License as published by the
146063 + * Free Software Foundation;  either version 2 of the  License, or (at your
146064 + * option) any later version.
146065 + */
146066 +
146067 +#ifndef __LINUX_MFD_PCF50606_RTC_H
146068 +#define __LINUX_MFD_PCF50606_RTC_H
146069 +
146070 +#include <linux/rtc.h>
146071 +#include <linux/platform_device.h>
146072 +
146073 +#define PCF50606_REG_RTCSC      0x0a   /* Second */
146074 +#define PCF50606_REG_RTCMN      0x0b   /* Minute */
146075 +#define PCF50606_REG_RTCHR      0x0c   /* Hour */
146076 +#define PCF50606_REG_RTCWD      0x0d   /* Weekday */
146077 +#define PCF50606_REG_RTCDT      0x0e   /* Day */
146078 +#define PCF50606_REG_RTCMT      0x0f   /* Month */
146079 +#define PCF50606_REG_RTCYR      0x10   /* Year */
146080 +#define PCF50606_REG_RTCSCA     0x11 /* Alarm Second */
146081 +#define PCF50606_REG_RTCMNA     0x12 /* Alarm Minute */
146082 +#define PCF50606_REG_RTCHRA     0x13 /* Alarm Hour */
146083 +#define PCF50606_REG_RTCWDA     0x14 /* Alarm Weekday */
146084 +#define PCF50606_REG_RTCDTA     0x15 /* Alarm Day */
146085 +#define PCF50606_REG_RTCMTA     0x16 /* Alarm Month */
146086 +#define PCF50606_REG_RTCYRA     0x17 /* Alarm Year */
146087 +
146088 +struct pcf50606_rtc {
146089 +       int alarm_enabled;
146090 +       int second_enabled;
146091 +
146092 +       struct rtc_device *rtc_dev;
146093 +       struct platform_device *pdev;
146094 +};
146095 +
146096 +#endif
146097 +
146098 --- /dev/null
146099 +++ b/include/linux/mfd/pcf50606/wdt.h
146100 @@ -0,0 +1,32 @@
146101 +/*
146102 + * wdt.h -- WDT driver for NXP PCF50606
146103 + *
146104 + * (C) 2006-2008 by Openmoko, Inc.
146105 + * All rights reserved.
146106 + *
146107 + * This program is free software; you can redistribute  it and/or modify it
146108 + * under  the terms of  the GNU General  Public License as published by the
146109 + * Free Software Foundation;  either version 2 of the  License, or (at your
146110 + * option) any later version.
146111 + */
146112 +
146113 +#ifndef __LINUX_MFD_PCF50606_WDT_H
146114 +#define __LINUX_MFD_PCF50606_WDT_H
146115 +
146116 +#define PCF50606_REG_OOCC1     0x08
146117 +#define PCF50606_REG_OOCS      0x01
146118 +
146119 +#define PCF50606_OOCS_WDTEXP   0x80
146120 +#define PCF50606_OOCC1_WDTRST  0x08
146121 +
146122 +#define CLOSE_STATE_NOT                0x0000
146123 +#define CLOSE_STATE_ALLOW      0x2342
146124 +
146125 +struct pcf50606;
146126 +
146127 +struct pcf50606_wdt {
146128 +       struct platform_device *pdev;
146129 +};
146130 +#endif /* __LINUX_MFD_PCF50606_WDT_H */
146131 +
146132 +
146133 --- /dev/null
146134 +++ b/include/linux/mfd/pcf50633/adc.h
146135 @@ -0,0 +1,88 @@
146136 +/*
146137 + * adc.h  -- Driver for NXP PCF50633 ADC
146138 + *
146139 + * (C) 2006-2008 by Openmoko, Inc.
146140 + * All rights reserved.
146141 + *
146142 + * This program is free software; you can redistribute  it and/or modify it
146143 + * under  the terms of  the GNU General  Public License as published by the
146144 + * Free Software Foundation;  either version 2 of the  License, or (at your
146145 + * option) any later version.
146146 + */
146147 +
146148 +#ifndef __LINUX_MFD_PCF50633_ADC_H
146149 +#define __LINUX_MFD_PCF50633_ADC_H
146150 +
146151 +#include <linux/platform_device.h>
146152 +
146153 +/* ADC Registers */
146154 +#define        PCF50633_REG_ADCC3 0x52
146155 +#define        PCF50633_REG_ADCC2 0x53
146156 +#define        PCF50633_REG_ADCC1 0x54
146157 +#define        PCF50633_REG_ADCS1 0x55
146158 +#define        PCF50633_REG_ADCS2 0x56
146159 +#define        PCF50633_REG_ADCS3 0x57
146160 +
146161 +#define        PCF50633_ADCC1_ADCSTART         0x01
146162 +#define        PCF50633_ADCC1_RES_10BIT        0x02
146163 +#define        PCF50633_ADCC1_AVERAGE_NO       0x00
146164 +#define        PCF50633_ADCC1_AVERAGE_4        0x04
146165 +#define        PCF50633_ADCC1_AVERAGE_8        0x08
146166 +#define        PCF50633_ADCC1_AVERAGE_16       0x0c
146167 +#define        PCF50633_ADCC1_MUX_BATSNS_RES   0x00
146168 +#define        PCF50633_ADCC1_MUX_BATSNS_SUBTR 0x10
146169 +#define        PCF50633_ADCC1_MUX_ADCIN2_RES   0x20
146170 +#define        PCF50633_ADCC1_MUX_ADCIN2_SUBTR 0x30
146171 +#define        PCF50633_ADCC1_MUX_BATTEMP      0x60
146172 +#define        PCF50633_ADCC1_MUX_ADCIN1       0x70
146173 +#define PCF50633_ADCC1_AVERAGE_MASK    0x0c
146174 +#define        PCF50633_ADCC1_ADCMUX_MASK      0xf0
146175 +
146176 +#define        PCF50633_ADCC2_RATIO_NONE       0x00
146177 +#define        PCF50633_ADCC2_RATIO_BATTEMP    0x01
146178 +#define        PCF50633_ADCC2_RATIO_ADCIN1     0x02
146179 +#define        PCF50633_ADCC2_RATIO_BOTH       0x03
146180 +#define        PCF50633_ADCC2_RATIOSETTL_100US 0x04
146181 +
146182 +#define        PCF50633_ADCC3_ACCSW_EN         0x01
146183 +#define        PCF50633_ADCC3_NTCSW_EN         0x04
146184 +#define        PCF50633_ADCC3_RES_DIV_TWO      0x10
146185 +#define        PCF50633_ADCC3_RES_DIV_THREE    0x00
146186 +
146187 +#define        PCF50633_ADCS3_REF_NTCSW        0x00
146188 +#define        PCF50633_ADCS3_REF_ACCSW        0x10
146189 +#define        PCF50633_ADCS3_REF_2V0          0x20
146190 +#define        PCF50633_ADCS3_REF_VISA         0x30
146191 +#define        PCF50633_ADCS3_REF_2V0_2        0x70
146192 +#define        PCF50633_ADCS3_ADCRDY           0x80
146193 +
146194 +#define PCF50633_ADCS3_ADCDAT1L_MASK   0x03
146195 +#define PCF50633_ADCS3_ADCDAT2L_MASK   0x0c
146196 +#define PCF50633_ADCS3_ADCDAT2L_SHIFT  2
146197 +#define PCF50633_ASCS3_REF_MASK                0x70
146198 +
146199 +
146200 +struct pcf50633;
146201 +
146202 +#define PCF50633_MAX_ADC_FIFO_DEPTH 8
146203 +
146204 +struct pcf50633_adc_request;
146205 +
146206 +struct pcf50633_adc {
146207 +       struct platform_device *pdev;
146208 +
146209 +       /* Private stuff */
146210 +       struct pcf50633_adc_request *queue[PCF50633_MAX_ADC_FIFO_DEPTH];
146211 +       int queue_head;
146212 +       int queue_tail;
146213 +       struct mutex queue_mutex;
146214 +};
146215 +
146216 +extern int
146217 +pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
146218 +               void (*callback)(struct pcf50633 *, void *, int),
146219 +               void *callback_param);
146220 +extern int
146221 +pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg);
146222 +
146223 +#endif /* __LINUX_PCF50633_ADC_H */
146224 --- /dev/null
146225 +++ b/include/linux/mfd/pcf50633/core.h
146226 @@ -0,0 +1,212 @@
146227 +/*
146228 + * core.h  -- Core driver for NXP PCF50633
146229 + *
146230 + * (C) 2006-2008 by Openmoko, Inc.
146231 + * All rights reserved.
146232 + *
146233 + * This program is free software; you can redistribute  it and/or modify it
146234 + * under  the terms of  the GNU General  Public License as published by the
146235 + * Free Software Foundation;  either version 2 of the  License, or (at your
146236 + * option) any later version.
146237 + */
146238 +
146239 +#ifndef __LINUX_MFD_PCF50633_CORE_H
146240 +#define __LINUX_MFD_PCF50633_CORE_H
146241 +
146242 +#include <linux/i2c.h>
146243 +#include <linux/workqueue.h>
146244 +#include <linux/regulator/driver.h>
146245 +#include <linux/regulator/machine.h>
146246 +#include <linux/power_supply.h>
146247 +
146248 +#include <linux/mfd/pcf50633/pmic.h>
146249 +#include <linux/mfd/pcf50633/input.h>
146250 +#include <linux/mfd/pcf50633/mbc.h>
146251 +#include <linux/mfd/pcf50633/rtc.h>
146252 +#include <linux/mfd/pcf50633/adc.h>
146253 +#include <linux/mfd/pcf50633/gpio.h>
146254 +
146255 +struct pcf50633;
146256 +
146257 +struct pcf50633_platform_data {
146258 +       struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
146259 +
146260 +       char **batteries;
146261 +       int num_batteries;
146262 +
146263 +       /* Callbacks */
146264 +       void (*probe_done)(struct pcf50633 *);
146265 +       void (*mbc_event_callback)(struct pcf50633 *, int);
146266 +       void (*regulator_registered)(struct pcf50633 *, int);
146267 +       void (*force_shutdown)(struct pcf50633 *);
146268 +
146269 +       u8 resumers[5];
146270 +
146271 +       /* Runtime data - filled by driver afer probe */
146272 +       struct pcf50633 *pcf;
146273 +};
146274 +
146275 +struct pcf50633_irq {
146276 +       void (*handler)(struct pcf50633 *, int, void *);
146277 +       void *data;
146278 +};
146279 +
146280 +int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
146281 +int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
146282 +int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
146283 +
146284 +int pcf50633_read_block(struct pcf50633 *, u8 reg,
146285 +                                       int nr_regs, u8 *data);
146286 +int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
146287 +                                       int nr_regs, u8 *data);
146288 +u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
146289 +int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
146290 +
146291 +int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
146292 +int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
146293 +
146294 +/* Interrupt registers */
146295 +
146296 +#define PCF50633_REG_INT1      0x02
146297 +#define        PCF50633_REG_INT2       0x03
146298 +#define        PCF50633_REG_INT3       0x04
146299 +#define        PCF50633_REG_INT4       0x05
146300 +#define        PCF50633_REG_INT5       0x06
146301 +
146302 +#define PCF50633_REG_INT1M     0x07
146303 +#define        PCF50633_REG_INT2M      0x08
146304 +#define        PCF50633_REG_INT3M      0x09
146305 +#define        PCF50633_REG_INT4M      0x0a
146306 +#define        PCF50633_REG_INT5M      0x0b
146307 +
146308 +enum {
146309 +       /* Chip IRQs */
146310 +       PCF50633_IRQ_ADPINS = 0,
146311 +       PCF50633_IRQ_ADPREM,
146312 +       PCF50633_IRQ_USBINS,
146313 +       PCF50633_IRQ_USBREM,
146314 +       PCF50633_IRQ_RESERVED1,
146315 +       PCF50633_IRQ_RESERVED2,
146316 +       PCF50633_IRQ_ALARM,
146317 +       PCF50633_IRQ_SECOND,
146318 +       PCF50633_IRQ_ONKEYR,
146319 +       PCF50633_IRQ_ONKEYF,
146320 +       PCF50633_IRQ_EXTON1R,
146321 +       PCF50633_IRQ_EXTON1F,
146322 +       PCF50633_IRQ_EXTON2R,
146323 +       PCF50633_IRQ_EXTON2F,
146324 +       PCF50633_IRQ_EXTON3R,
146325 +       PCF50633_IRQ_EXTON3F,
146326 +       PCF50633_IRQ_BATFULL,
146327 +       PCF50633_IRQ_CHGHALT,
146328 +       PCF50633_IRQ_THLIMON,
146329 +       PCF50633_IRQ_THLIMOFF,
146330 +       PCF50633_IRQ_USBLIMON,
146331 +       PCF50633_IRQ_USBLIMOFF,
146332 +       PCF50633_IRQ_ADCRDY,
146333 +       PCF50633_IRQ_ONKEY1S,
146334 +       PCF50633_IRQ_LOWSYS,
146335 +       PCF50633_IRQ_LOWBAT,
146336 +       PCF50633_IRQ_HIGHTMP,
146337 +       PCF50633_IRQ_AUTOPWRFAIL,
146338 +       PCF50633_IRQ_DWN1PWRFAIL,
146339 +       PCF50633_IRQ_DWN2PWRFAIL,
146340 +       PCF50633_IRQ_LEDPWRFAIL,
146341 +       PCF50633_IRQ_LEDOVP,
146342 +       PCF50633_IRQ_LDO1PWRFAIL,
146343 +       PCF50633_IRQ_LDO2PWRFAIL,
146344 +       PCF50633_IRQ_LDO3PWRFAIL,
146345 +       PCF50633_IRQ_LDO4PWRFAIL,
146346 +       PCF50633_IRQ_LDO5PWRFAIL,
146347 +       PCF50633_IRQ_LDO6PWRFAIL,
146348 +       PCF50633_IRQ_HCLDOPWRFAIL,
146349 +       PCF50633_IRQ_HCLDOOVL,
146350 +
146351 +       /* Always last */
146352 +       PCF50633_NUM_IRQ,
146353 +};
146354 +
146355 +struct pcf50633 {
146356 +       struct device *dev;
146357 +       struct i2c_client *i2c_client;
146358 +
146359 +       struct pcf50633_platform_data *pdata;
146360 +       int irq;
146361 +       struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
146362 +       struct work_struct irq_work;
146363 +       struct mutex lock;
146364 +
146365 +       u8 mask_regs[5];
146366 +
146367 +       u8 suspend_irq_masks[5];
146368 +       u8 resume_reason[5];
146369 +       int is_suspended;
146370 +
146371 +       int onkey1s_held;
146372 +
146373 +       struct pcf50633_pmic pmic;
146374 +       struct pcf50633_input input;
146375 +       struct pcf50633_mbc mbc;
146376 +       struct pcf50633_rtc rtc;
146377 +       struct pcf50633_adc adc;
146378 +};
146379 +
146380 +enum pcf50633_reg_int1 {
146381 +       PCF50633_INT1_ADPINS    = 0x01, /* Adapter inserted */
146382 +       PCF50633_INT1_ADPREM    = 0x02, /* Adapter removed */
146383 +       PCF50633_INT1_USBINS    = 0x04, /* USB inserted */
146384 +       PCF50633_INT1_USBREM    = 0x08, /* USB removed */
146385 +       /* reserved */
146386 +       PCF50633_INT1_ALARM     = 0x40, /* RTC alarm time is reached */
146387 +       PCF50633_INT1_SECOND    = 0x80, /* RTC periodic second interrupt */
146388 +};
146389 +
146390 +enum pcf50633_reg_int2 {
146391 +       PCF50633_INT2_ONKEYR    = 0x01, /* ONKEY rising edge */
146392 +       PCF50633_INT2_ONKEYF    = 0x02, /* ONKEY falling edge */
146393 +       PCF50633_INT2_EXTON1R   = 0x04, /* EXTON1 rising edge */
146394 +       PCF50633_INT2_EXTON1F   = 0x08, /* EXTON1 falling edge */
146395 +       PCF50633_INT2_EXTON2R   = 0x10, /* EXTON2 rising edge */
146396 +       PCF50633_INT2_EXTON2F   = 0x20, /* EXTON2 falling edge */
146397 +       PCF50633_INT2_EXTON3R   = 0x40, /* EXTON3 rising edge */
146398 +       PCF50633_INT2_EXTON3F   = 0x80, /* EXTON3 falling edge */
146399 +};
146400 +
146401 +enum pcf50633_reg_int3 {
146402 +       PCF50633_INT3_BATFULL   = 0x01, /* Battery full */
146403 +       PCF50633_INT3_CHGHALT   = 0x02, /* Charger halt */
146404 +       PCF50633_INT3_THLIMON   = 0x04,
146405 +       PCF50633_INT3_THLIMOFF  = 0x08,
146406 +       PCF50633_INT3_USBLIMON  = 0x10,
146407 +       PCF50633_INT3_USBLIMOFF = 0x20,
146408 +       PCF50633_INT3_ADCRDY    = 0x40, /* ADC result ready */
146409 +       PCF50633_INT3_ONKEY1S   = 0x80, /* ONKEY pressed 1 second */
146410 +};
146411 +
146412 +enum pcf50633_reg_int4 {
146413 +       PCF50633_INT4_LOWSYS            = 0x01,
146414 +       PCF50633_INT4_LOWBAT            = 0x02,
146415 +       PCF50633_INT4_HIGHTMP           = 0x04,
146416 +       PCF50633_INT4_AUTOPWRFAIL       = 0x08,
146417 +       PCF50633_INT4_DWN1PWRFAIL       = 0x10,
146418 +       PCF50633_INT4_DWN2PWRFAIL       = 0x20,
146419 +       PCF50633_INT4_LEDPWRFAIL        = 0x40,
146420 +       PCF50633_INT4_LEDOVP            = 0x80,
146421 +};
146422 +
146423 +enum pcf50633_reg_int5 {
146424 +       PCF50633_INT5_LDO1PWRFAIL       = 0x01,
146425 +       PCF50633_INT5_LDO2PWRFAIL       = 0x02,
146426 +       PCF50633_INT5_LDO3PWRFAIL       = 0x04,
146427 +       PCF50633_INT5_LDO4PWRFAIL       = 0x08,
146428 +       PCF50633_INT5_LDO5PWRFAIL       = 0x10,
146429 +       PCF50633_INT5_LDO6PWRFAIL       = 0x20,
146430 +       PCF50633_INT5_HCLDOPWRFAIL      = 0x40,
146431 +       PCF50633_INT5_HCLDOOVL          = 0x80,
146432 +};
146433 +
146434 +/* misc. registers */
146435 +#define PCF50633_REG_OOCSHDWN  0x0c
146436 +
146437 +#endif
146438 +
146439 --- /dev/null
146440 +++ b/include/linux/mfd/pcf50633/gpio.h
146441 @@ -0,0 +1,51 @@
146442 +/*
146443 + * gpio.h -- GPIO driver for NXP PCF50633
146444 + *
146445 + * (C) 2006-2008 by Openmoko, Inc.
146446 + * All rights reserved.
146447 + *
146448 + * This program is free software; you can redistribute  it and/or modify it
146449 + * under  the terms of  the GNU General  Public License as published by the
146450 + * Free Software Foundation;  either version 2 of the  License, or (at your
146451 + * option) any later version.
146452 + */
146453 +
146454 +#ifndef __LINUX_MFD_PCF50633_GPIO_H
146455 +#define __LINUX_MFD_PCF50633_GPIO_H
146456 +
146457 +#define PCF50633_GPIO1 1
146458 +#define PCF50633_GPIO2 2
146459 +#define PCF50633_GPIO3 3
146460 +#define PCF50633_GPO   4
146461 +
146462 +#define PCF50633_REG_GPIO1CFG  0x14
146463 +#define PCF50633_REG_GPIO2CFG  0x15
146464 +#define PCF50633_REG_GPIO3CFG  0x16
146465 +#define PCF50633_REG_GPOCFG    0x17
146466 +
146467 +enum pcf50633_reg_gpocfg {
146468 +       PCF50633_GPOCFG_GPOSEL_0        = 0x00,
146469 +       PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01,
146470 +       PCF50633_GPOCFG_GPOSEL_SYSxOK   = 0x02,
146471 +       PCF50633_GPOCFG_GPOSEL_CLK32K   = 0x03,
146472 +       PCF50633_GPOCFG_GPOSEL_ADAPUSB  = 0x04,
146473 +       PCF50633_GPOCFG_GPOSEL_USBxOK   = 0x05,
146474 +       PCF50633_GPOCFG_GPOSEL_ACTPH4   = 0x06,
146475 +       PCF50633_GPOCFG_GPOSEL_1        = 0x07,
146476 +       PCF50633_GPOCFG_GPOSEL_INVERSE  = 0x08,
146477 +};
146478 +#define PCF50633_GPOCFG_GPOSEL_MASK    0x07
146479 +
146480 +struct pcf50633;
146481 +
146482 +void pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, int on);
146483 +int pcf50633_gpio_get(struct pcf50633 *pcf, int gpio);
146484 +
146485 +void pcf50633_gpio_invert_set(struct pcf50633 *, int gpio, int invert);
146486 +int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio);
146487 +
146488 +void pcf50633_gpio_power_supply_set(struct pcf50633 *,
146489 +                                       int gpio, int regulator, int on);
146490 +#endif /* __LINUX_MFD_PCF50633_GPIO_H */
146491 +
146492 +
146493 --- /dev/null
146494 +++ b/include/linux/mfd/pcf50633/input.h
146495 @@ -0,0 +1,29 @@
146496 +/*
146497 + * input.h  -- Input driver for NXP PCF50633
146498 + *
146499 + * (C) 2006-2008 by Openmoko, Inc.
146500 + * All rights reserved.
146501 + *
146502 + * This program is free software; you can redistribute  it and/or modify it
146503 + * under  the terms of  the GNU General  Public License as published by the
146504 + * Free Software Foundation;  either version 2 of the  License, or (at your
146505 + * option) any later version.
146506 + */
146507 +
146508 +#ifndef __LINUX_MFD_PCF50633_INPUT_H
146509 +#define __LINUX_MFD_PCF50633_INPUT_H
146510 +
146511 +#include <linux/platform_device.h>
146512 +#include <linux/input.h>
146513 +
146514 +#define PCF50633_OOCSTAT_ONKEY 0x01
146515 +#define PCF50633_REG_OOCSTAT   0x12
146516 +#define PCF50633_REG_OOCMODE   0x10
146517 +
146518 +struct pcf50633_input {
146519 +       struct input_dev *input_dev;
146520 +       struct platform_device *pdev;
146521 +};
146522 +
146523 +#endif
146524 +
146525 --- /dev/null
146526 +++ b/include/linux/mfd/pcf50633/led.h
146527 @@ -0,0 +1,24 @@
146528 +/*
146529 + * led.h  -- LED driver for NXP PCF50633
146530 + *
146531 + * (C) 2006-2008 by Openmoko, Inc.
146532 + * All rights reserved.
146533 + *
146534 + * This program is free software; you can redistribute  it and/or modify it
146535 + * under  the terms of  the GNU General  Public License as published by the
146536 + * Free Software Foundation;  either version 2 of the  License, or (at your
146537 + * option) any later version.
146538 + */
146539 +
146540 +#ifndef __LINUX_MFD_PCF50633_LED_H
146541 +#define __LINUX_MFD_PCF50633_LED_H
146542 +
146543 +#include <linux/platform_device.h>
146544 +
146545 +#define PCF50633_REG_LEDOUT 0x28
146546 +#define PCF50633_REG_LEDENA 0x29
146547 +#define PCF50633_REG_LEDCTL 0x2a
146548 +#define PCF50633_REG_LEDDIM 0x2b
146549 +
146550 +#endif
146551 +
146552 --- /dev/null
146553 +++ b/include/linux/mfd/pcf50633/mbc.h
146554 @@ -0,0 +1,140 @@
146555 +/*
146556 + * mbc.h  -- Driver for NXP PCF50633 Main Battery Charger
146557 + *
146558 + * (C) 2006-2008 by Openmoko, Inc.
146559 + * All rights reserved.
146560 + *
146561 + * This program is free software; you can redistribute  it and/or modify it
146562 + * under  the terms of  the GNU General  Public License as published by the
146563 + * Free Software Foundation;  either version 2 of the  License, or (at your
146564 + * option) any later version.
146565 + */
146566 +
146567 +#ifndef __LINUX_MFD_PCF50633_MBC_H
146568 +#define __LINUX_MFD_PCF50633_MBC_H
146569 +
146570 +#include <linux/platform_device.h>
146571 +
146572 +#define PCF50633_REG_MBCC1     0x43
146573 +#define PCF50633_REG_MBCC2     0x44
146574 +#define PCF50633_REG_MBCC3     0x45
146575 +#define PCF50633_REG_MBCC4     0x46
146576 +#define PCF50633_REG_MBCC5     0x47
146577 +#define PCF50633_REG_MBCC6     0x48
146578 +#define PCF50633_REG_MBCC7     0x49
146579 +#define PCF50633_REG_MBCC8     0x4a
146580 +#define PCF50633_REG_MBCS1     0x4b
146581 +#define PCF50633_REG_MBCS2     0x4c
146582 +#define PCF50633_REG_MBCS3     0x4d
146583 +
146584 +enum pcf50633_reg_mbcc1 {
146585 +       PCF50633_MBCC1_CHGENA           = 0x01, /* Charger enable */
146586 +       PCF50633_MBCC1_AUTOSTOP         = 0x02,
146587 +       PCF50633_MBCC1_AUTORES          = 0x04, /* automatic resume */
146588 +       PCF50633_MBCC1_RESUME           = 0x08, /* explicit resume cmd */
146589 +       PCF50633_MBCC1_RESTART          = 0x10, /* restart charging */
146590 +       PCF50633_MBCC1_PREWDTIME_60M    = 0x20, /* max. precharging time */
146591 +       PCF50633_MBCC1_WDTIME_1H        = 0x00,
146592 +       PCF50633_MBCC1_WDTIME_2H        = 0x40,
146593 +       PCF50633_MBCC1_WDTIME_4H        = 0x80,
146594 +       PCF50633_MBCC1_WDTIME_6H        = 0xc0,
146595 +};
146596 +#define PCF50633_MBCC1_WDTIME_MASK       0xc0
146597 +
146598 +enum pcf50633_reg_mbcc2 {
146599 +       PCF50633_MBCC2_VBATCOND_2V7     = 0x00,
146600 +       PCF50633_MBCC2_VBATCOND_2V85    = 0x01,
146601 +       PCF50633_MBCC2_VBATCOND_3V0     = 0x02,
146602 +       PCF50633_MBCC2_VBATCOND_3V15    = 0x03,
146603 +       PCF50633_MBCC2_VMAX_4V          = 0x00,
146604 +       PCF50633_MBCC2_VMAX_4V20        = 0x28,
146605 +       PCF50633_MBCC2_VRESDEBTIME_64S  = 0x80, /* debounce time (32/64sec) */
146606 +};
146607 +
146608 +enum pcf50633_reg_mbcc7 {
146609 +       PCF50633_MBCC7_USB_100mA        = 0x00,
146610 +       PCF50633_MBCC7_USB_500mA        = 0x01,
146611 +       PCF50633_MBCC7_USB_1000mA       = 0x02,
146612 +       PCF50633_MBCC7_USB_SUSPEND      = 0x03,
146613 +       PCF50633_MBCC7_BATTEMP_EN       = 0x04,
146614 +       PCF50633_MBCC7_BATSYSIMAX_1A6   = 0x00,
146615 +       PCF50633_MBCC7_BATSYSIMAX_1A8   = 0x40,
146616 +       PCF50633_MBCC7_BATSYSIMAX_2A0   = 0x80,
146617 +       PCF50633_MBCC7_BATSYSIMAX_2A2   = 0xc0,
146618 +};
146619 +#define PCF50633_MBCC7_USB_MASK 0x03
146620 +
146621 +enum pcf50633_reg_mbcc8 {
146622 +       PCF50633_MBCC8_USBENASUS        = 0x10,
146623 +};
146624 +
146625 +enum pcf50633_reg_mbcs1 {
146626 +       PCF50633_MBCS1_USBPRES          = 0x01,
146627 +       PCF50633_MBCS1_USBOK            = 0x02,
146628 +       PCF50633_MBCS1_ADAPTPRES        = 0x04,
146629 +       PCF50633_MBCS1_ADAPTOK          = 0x08,
146630 +       PCF50633_MBCS1_TBAT_OK          = 0x00,
146631 +       PCF50633_MBCS1_TBAT_ABOVE       = 0x10,
146632 +       PCF50633_MBCS1_TBAT_BELOW       = 0x20,
146633 +       PCF50633_MBCS1_TBAT_UNDEF       = 0x30,
146634 +       PCF50633_MBCS1_PREWDTEXP        = 0x40,
146635 +       PCF50633_MBCS1_WDTEXP           = 0x80,
146636 +};
146637 +
146638 +enum pcf50633_reg_mbcs2_mbcmod {
146639 +       PCF50633_MBCS2_MBC_PLAY         = 0x00,
146640 +       PCF50633_MBCS2_MBC_USB_PRE      = 0x01,
146641 +       PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02,
146642 +       PCF50633_MBCS2_MBC_USB_FAST     = 0x03,
146643 +       PCF50633_MBCS2_MBC_USB_FAST_WAIT = 0x04,
146644 +       PCF50633_MBCS2_MBC_USB_SUSPEND  = 0x05,
146645 +       PCF50633_MBCS2_MBC_ADP_PRE      = 0x06,
146646 +       PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07,
146647 +       PCF50633_MBCS2_MBC_ADP_FAST     = 0x08,
146648 +       PCF50633_MBCS2_MBC_ADP_FAST_WAIT = 0x09,
146649 +       PCF50633_MBCS2_MBC_BAT_FULL     = 0x0a,
146650 +       PCF50633_MBCS2_MBC_HALT         = 0x0b,
146651 +};
146652 +#define PCF50633_MBCS2_MBC_MASK                0x0f
146653 +enum pcf50633_reg_mbcs2_chgstat {
146654 +       PCF50633_MBCS2_CHGS_NONE        = 0x00,
146655 +       PCF50633_MBCS2_CHGS_ADAPTER     = 0x10,
146656 +       PCF50633_MBCS2_CHGS_USB         = 0x20,
146657 +       PCF50633_MBCS2_CHGS_BOTH        = 0x30,
146658 +};
146659 +#define PCF50633_MBCS2_RESSTAT_AUTO    0x40
146660 +
146661 +enum pcf50633_reg_mbcs3 {
146662 +       PCF50633_MBCS3_USBLIM_PLAY      = 0x01,
146663 +       PCF50633_MBCS3_USBLIM_CGH       = 0x02,
146664 +       PCF50633_MBCS3_TLIM_PLAY        = 0x04,
146665 +       PCF50633_MBCS3_TLIM_CHG         = 0x08,
146666 +       PCF50633_MBCS3_ILIM             = 0x10, /* 1: Ibat > Icutoff */
146667 +       PCF50633_MBCS3_VLIM             = 0x20, /* 1: Vbat == Vmax */
146668 +       PCF50633_MBCS3_VBATSTAT         = 0x40, /* 1: Vbat > Vbatcond */
146669 +       PCF50633_MBCS3_VRES             = 0x80, /* 1: Vbat > Vth(RES) */
146670 +};
146671 +
146672 +#define        PCF50633_MBCC2_VBATCOND_MASK      0x03
146673 +#define PCF50633_MBCC2_VMAX_MASK         0x3c
146674 +
146675 +struct pcf50633;
146676 +
146677 +void pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma);
146678 +
146679 +struct pcf50633_mbc {
146680 +       int adapter_active;
146681 +       int adapter_online;
146682 +       int usb_active;
146683 +       int usb_online;
146684 +
146685 +       struct power_supply ac;
146686 +       struct power_supply usb;
146687 +       struct power_supply adapter;
146688 +
146689 +       struct delayed_work charging_restart_work;
146690 +
146691 +       struct platform_device *pdev;
146692 +};
146693 +#endif
146694 +
146695 --- /dev/null
146696 +++ b/include/linux/mfd/pcf50633/pmic.h
146697 @@ -0,0 +1,73 @@
146698 +#ifndef __LINUX_MFD_PCF50633_PMIC_H
146699 +#define __LINUX_MFD_PCF50633_PMIC_H
146700 +
146701 +#include <linux/platform_device.h>
146702 +
146703 +#define PCF50633_REG_AUTOOUT   0x1a
146704 +#define PCF50633_REG_AUTOENA   0x1b
146705 +#define PCF50633_REG_AUTOCTL   0x1c
146706 +#define PCF50633_REG_AUTOMXC   0x1d
146707 +#define PCF50633_REG_DOWN1OUT  0x1e
146708 +#define PCF50633_REG_DOWN1ENA  0x1f
146709 +#define PCF50633_REG_DOWN1CTL  0x20
146710 +#define PCF50633_REG_DOWN1MXC  0x21
146711 +#define        PCF50633_REG_DOWN2OUT   0x22
146712 +#define PCF50633_REG_DOWN2ENA  0x23
146713 +#define PCF50633_REG_DOWN2CTL  0x24
146714 +#define PCF50633_REG_DOWN2MXC  0x25
146715 +#define PCF50633_REG_MEMLDOOUT 0x26
146716 +#define PCF50633_REG_MEMLDOENA 0x27
146717 +#define PCF50633_REG_LDO1OUT   0x2d
146718 +#define PCF50633_REG_LDO1ENA   0x2e
146719 +#define PCF50633_REG_LDO2OUT   0x2f
146720 +#define PCF50633_REG_LDO2ENA   0x30
146721 +#define        PCF50633_REG_LDO3OUT    0x31
146722 +#define        PCF50633_REG_LDO3ENA    0x32
146723 +#define        PCF50633_REG_LDO4OUT    0x33
146724 +#define        PCF50633_REG_LDO4ENA    0x34
146725 +#define        PCF50633_REG_LDO5OUT    0x35
146726 +#define        PCF50633_REG_LDO5ENA    0x36
146727 +#define        PCF50633_REG_LDO6OUT    0x37
146728 +#define        PCF50633_REG_LDO6ENA    0x38
146729 +#define        PCF50633_REG_HCLDOOUT   0x39
146730 +#define        PCF50633_REG_HCLDOENA   0x3a
146731 +#define PCF50633_REG_HCLDOOVL  0x40
146732 +
146733 +enum pcf50633_regulator_enable {
146734 +       PCF50633_REGULATOR_ON           = 0x01,
146735 +       PCF50633_REGULATOR_ON_GPIO1     = 0x02,
146736 +       PCF50633_REGULATOR_ON_GPIO2     = 0x04,
146737 +       PCF50633_REGULATOR_ON_GPIO3     = 0x08,
146738 +};
146739 +#define PCF50633_REGULATOR_ON_MASK     0x0f
146740 +
146741 +enum pcf50633_regulator_phase {
146742 +       PCF50633_REGULATOR_ACTPH1       = 0x00,
146743 +       PCF50633_REGULATOR_ACTPH2       = 0x10,
146744 +       PCF50633_REGULATOR_ACTPH3       = 0x20,
146745 +       PCF50633_REGULATOR_ACTPH4       = 0x30,
146746 +};
146747 +#define PCF50633_REGULATOR_ACTPH_MASK  0x30
146748 +
146749 +
146750 +enum pcf50633_regulator_id {
146751 +       PCF50633_REGULATOR_AUTO,
146752 +       PCF50633_REGULATOR_DOWN1,
146753 +       PCF50633_REGULATOR_DOWN2,
146754 +       PCF50633_REGULATOR_LDO1,
146755 +       PCF50633_REGULATOR_LDO2,
146756 +       PCF50633_REGULATOR_LDO3,
146757 +       PCF50633_REGULATOR_LDO4,
146758 +       PCF50633_REGULATOR_LDO5,
146759 +       PCF50633_REGULATOR_LDO6,
146760 +       PCF50633_REGULATOR_HCLDO,
146761 +       PCF50633_REGULATOR_MEMLDO,
146762 +
146763 +       PCF50633_NUM_REGULATORS
146764 +};
146765 +
146766 +struct pcf50633_pmic {
146767 +       struct platform_device *pdev[PCF50633_NUM_REGULATORS];
146768 +};
146769 +#endif
146770 +
146771 --- /dev/null
146772 +++ b/include/linux/mfd/pcf50633/rtc.h
146773 @@ -0,0 +1,43 @@
146774 +/*
146775 + * rtc.h  -- RTC driver for NXP PCF50633
146776 + *
146777 + * (C) 2006-2008 by Openmoko, Inc.
146778 + * All rights reserved.
146779 + *
146780 + * This program is free software; you can redistribute  it and/or modify it
146781 + * under  the terms of  the GNU General  Public License as published by the
146782 + * Free Software Foundation;  either version 2 of the  License, or (at your
146783 + * option) any later version.
146784 + */
146785 +
146786 +#ifndef __LINUX_MFD_PCF50633_RTC_H
146787 +#define __LINUX_MFD_PCF50633_RTC_H
146788 +
146789 +#include <linux/rtc.h>
146790 +#include <linux/platform_device.h>
146791 +
146792 +#define PCF50633_REG_RTCSC     0x59 /* Second */
146793 +#define PCF50633_REG_RTCMN     0x5a /* Minute */
146794 +#define PCF50633_REG_RTCHR     0x5b /* Hour */
146795 +#define PCF50633_REG_RTCWD     0x5c /* Weekday */
146796 +#define PCF50633_REG_RTCDT     0x5d /* Day */
146797 +#define PCF50633_REG_RTCMT     0x5e /* Month */
146798 +#define PCF50633_REG_RTCYR     0x5f /* Year */
146799 +#define PCF50633_REG_RTCSCA    0x60 /* Alarm Second */
146800 +#define PCF50633_REG_RTCMNA    0x61 /* Alarm Minute */
146801 +#define PCF50633_REG_RTCHRA    0x62 /* Alarm Hour */
146802 +#define PCF50633_REG_RTCWDA    0x63 /* Alarm Weekday */
146803 +#define PCF50633_REG_RTCDTA    0x64 /* Alarm Day */
146804 +#define PCF50633_REG_RTCMTA    0x65 /* Alarm Month */
146805 +#define PCF50633_REG_RTCYRA    0x66 /* Alarm Year */
146806 +
146807 +struct pcf50633_rtc {
146808 +       int alarm_enabled;
146809 +       int second_enabled;
146810 +
146811 +       struct rtc_device *rtc_dev;
146812 +       struct platform_device *pdev;
146813 +};
146814 +
146815 +#endif
146816 +
146817 --- a/include/linux/mmc/core.h
146818 +++ b/include/linux/mmc/core.h
146819 @@ -129,6 +129,8 @@ struct mmc_request {
146820  struct mmc_host;
146821  struct mmc_card;
146822
146823 +extern void mmc_flush_scheduled_work(void);
146824 +
146825  extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
146826  extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int);
146827  extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *,
146828 --- a/include/linux/mmc/sdio_ids.h
146829 +++ b/include/linux/mmc/sdio_ids.h
146830 @@ -25,5 +25,8 @@
146831
146832  #define SDIO_VENDOR_ID_MARVELL                 0x02df
146833  #define SDIO_DEVICE_ID_MARVELL_LIBERTAS                0x9103
146834 +#define SDIO_DEVICE_ID_MARVELL_88W8688         0x9104
146835 +#define SDIO_VENDOR_ID_ATHEROS                 0x0271
146836 +#define SDIO_DEVICE_ID_ATHEROS_AR6000          0x0100
146837
146838  #endif
146839 --- a/include/linux/mm.h
146840 +++ b/include/linux/mm.h
146841 @@ -713,7 +713,7 @@ static inline int shmem_lock(struct file
146842  }
146843  #endif
146844  struct file *shmem_file_setup(char *name, loff_t size, unsigned long flags);
146845 -
146846 +void shmem_set_file(struct vm_area_struct *, struct file *);
146847  int shmem_zero_setup(struct vm_area_struct *);
146848
146849  #ifndef CONFIG_MMU
146850 --- /dev/null
146851 +++ b/include/linux/pcf50606.h
146852 @@ -0,0 +1,91 @@
146853 +#ifndef _LINUX_PCF50606_H
146854 +#define _LINUX_PCF50606_H
146855 +
146856 +#include <linux/pcf506xx.h>
146857 +
146858 +
146859 +/* public in-kernel pcf50606 api */
146860 +enum pcf50606_regulator_id {
146861 +       PCF50606_REGULATOR_DCD,
146862 +       PCF50606_REGULATOR_DCDE,
146863 +       PCF50606_REGULATOR_DCUD,
146864 +       PCF50606_REGULATOR_D1REG,
146865 +       PCF50606_REGULATOR_D2REG,
146866 +       PCF50606_REGULATOR_D3REG,
146867 +       PCF50606_REGULATOR_LPREG,
146868 +       PCF50606_REGULATOR_IOREG,
146869 +       __NUM_PCF50606_REGULATORS
146870 +};
146871 +
146872 +struct pcf50606_data;
146873 +
146874 +/* This is an ugly construct on how to access the (currently single/global)
146875 + * pcf50606 handle from other code in the kernel.  I didn't really come up with
146876 + * a more decent method of dynamically resolving this */
146877 +extern struct pcf50606_data *pcf50606_global;
146878 +
146879 +extern void
146880 +pcf50606_go_standby(void);
146881 +
146882 +extern void
146883 +pcf50606_gpo0_set(struct pcf50606_data *pcf, int on);
146884 +
146885 +extern int
146886 +pcf50606_gpo0_get(struct pcf50606_data *pcf);
146887 +
146888 +extern int
146889 +pcf50606_voltage_set(struct pcf50606_data *pcf,
146890 +                    enum pcf50606_regulator_id reg,
146891 +                    unsigned int millivolts);
146892 +extern unsigned int
146893 +pcf50606_voltage_get(struct pcf50606_data *pcf,
146894 +                    enum pcf50606_regulator_id reg);
146895 +extern int
146896 +pcf50606_onoff_get(struct pcf50606_data *pcf,
146897 +                  enum pcf50606_regulator_id reg);
146898 +
146899 +extern int
146900 +pcf50606_onoff_set(struct pcf50606_data *pcf,
146901 +                  enum pcf50606_regulator_id reg, int on);
146902 +
146903 +extern void
146904 +pcf50606_charge_fast(struct pcf50606_data *pcf, int on);
146905 +
146906 +
146907 +#define PCF50606_FEAT_EXTON    0x00000001      /* not yet supported */
146908 +#define PCF50606_FEAT_MBC      0x00000002
146909 +#define PCF50606_FEAT_BBC      0x00000004      /* not yet supported */
146910 +#define PCF50606_FEAT_TSC      0x00000008      /* not yet supported */
146911 +#define PCF50606_FEAT_WDT      0x00000010
146912 +#define PCF50606_FEAT_ACD      0x00000020
146913 +#define PCF50606_FEAT_RTC      0x00000040
146914 +#define PCF50606_FEAT_PWM      0x00000080
146915 +#define PCF50606_FEAT_CHGCUR   0x00000100
146916 +#define PCF50606_FEAT_BATVOLT  0x00000200
146917 +#define PCF50606_FEAT_BATTEMP  0x00000400
146918 +#define PCF50606_FEAT_PWM_BL   0x00000800
146919 +
146920 +struct pcf50606_platform_data {
146921 +       /* general */
146922 +       unsigned int used_features;
146923 +       unsigned int onkey_seconds_required;
146924 +
146925 +       /* voltage regulator related */
146926 +       struct pmu_voltage_rail rails[__NUM_PCF50606_REGULATORS];
146927 +       unsigned int used_regulators;
146928 +
146929 +       /* charger related */
146930 +       unsigned int r_fix_batt;
146931 +       unsigned int r_fix_batt_par;
146932 +       unsigned int r_sense_milli;
146933 +
146934 +       /* backlight related */
146935 +       unsigned int init_brightness;
146936 +
146937 +       struct {
146938 +               u_int8_t mbcc3; /* charger voltage / current */
146939 +       } charger;
146940 +       pmu_cb cb;
146941 +};
146942 +
146943 +#endif
146944 --- /dev/null
146945 +++ b/include/linux/pcf50633.h
146946 @@ -0,0 +1,618 @@
146947 +#ifndef _LINUX_PCF50633_H
146948 +#define _LINUX_PCF50633_H
146949 +
146950 +#include <linux/pcf506xx.h>
146951 +#include <linux/regulator/machine.h>
146952 +
146953 +#define PCF50633_FIDX_CHG_ENABLED      0       /* Charger enabled */
146954 +#define PCF50633_FIDX_CHG_PRESENT      1       /* Charger present */
146955 +#define PCF50633_FIDX_CHG_ERR          3       /* Charger Error */
146956 +#define PCF50633_FIDX_CHG_PROT         4       /* Charger Protection */
146957 +#define PCF50633_FIDX_CHG_READY                5       /* Charging completed */
146958 +#define PCF50633_FIDX_PWR_PRESSED      8
146959 +#define PCF50633_FIDX_RTC_SECOND       9
146960 +#define PCF50633_FIDX_USB_PRESENT      10
146961 +
146962 +#define PCF50633_F_CHG_ENABLED (1 << PCF50633_FIDX_CHG_ENABLED)
146963 +#define PCF50633_F_CHG_PRESENT (1 << PCF50633_FIDX_CHG_PRESENT)
146964 +#define PCF50633_F_CHG_ERR     (1 << PCF50633_FIDX_CHG_ERR)
146965 +#define PCF50633_F_CHG_PROT    (1 << PCF50633_FIDX_CHG_PROT)
146966 +#define PCF50633_F_CHG_READY   (1 << PCF50633_FIDX_CHG_READY)
146967 +
146968 +#define PCF50633_F_CHG_MASK    0x000000fc
146969 +
146970 +#define PCF50633_F_PWR_PRESSED (1 << PCF50633_FIDX_PWR_PRESSED)
146971 +
146972 +#define PCF50633_F_RTC_SECOND  (1 << PCF50633_FIDX_RTC_SECOND)
146973 +#define PCF50633_F_USB_PRESENT (1 << PCF50633_FIDX_USB_PRESENT)
146974 +
146975 +/* public in-kernel pcf50633 api */
146976 +enum pcf50633_regulator_id {
146977 +       PCF50633_REGULATOR_AUTO,
146978 +       PCF50633_REGULATOR_DOWN1,
146979 +       PCF50633_REGULATOR_DOWN2,
146980 +       PCF50633_REGULATOR_LDO1,
146981 +       PCF50633_REGULATOR_LDO2,
146982 +       PCF50633_REGULATOR_LDO3,
146983 +       PCF50633_REGULATOR_LDO4,
146984 +       PCF50633_REGULATOR_LDO5,
146985 +       PCF50633_REGULATOR_LDO6,
146986 +       PCF50633_REGULATOR_HCLDO,
146987 +       PCF50633_REGULATOR_MEMLDO,
146988 +       __NUM_PCF50633_REGULATORS
146989 +};
146990 +
146991 +enum pcf50633_reg_int1 {
146992 +       PCF50633_INT1_ADPINS    = 0x01, /* Adapter inserted */
146993 +       PCF50633_INT1_ADPREM    = 0x02, /* Adapter removed */
146994 +       PCF50633_INT1_USBINS    = 0x04, /* USB inserted */
146995 +       PCF50633_INT1_USBREM    = 0x08, /* USB removed */
146996 +       /* reserved */
146997 +       PCF50633_INT1_ALARM     = 0x40, /* RTC alarm time is reached */
146998 +       PCF50633_INT1_SECOND    = 0x80, /* RTC periodic second interrupt */
146999 +};
147000 +
147001 +enum pcf50633_reg_int2 {
147002 +       PCF50633_INT2_ONKEYR    = 0x01, /* ONKEY rising edge */
147003 +       PCF50633_INT2_ONKEYF    = 0x02, /* ONKEY falling edge */
147004 +       PCF50633_INT2_EXTON1R   = 0x04, /* EXTON1 rising edge */
147005 +       PCF50633_INT2_EXTON1F   = 0x08, /* EXTON1 falling edge */
147006 +       PCF50633_INT2_EXTON2R   = 0x10, /* EXTON2 rising edge */
147007 +       PCF50633_INT2_EXTON2F   = 0x20, /* EXTON2 falling edge */
147008 +       PCF50633_INT2_EXTON3R   = 0x40, /* EXTON3 rising edge */
147009 +       PCF50633_INT2_EXTON3F   = 0x80, /* EXTON3 falling edge */
147010 +};
147011 +
147012 +enum pcf50633_reg_int3 {
147013 +       PCF50633_INT3_BATFULL   = 0x01, /* Battery full */
147014 +       PCF50633_INT3_CHGHALT   = 0x02, /* Charger halt */
147015 +       PCF50633_INT3_THLIMON   = 0x04,
147016 +       PCF50633_INT3_THLIMOFF  = 0x08,
147017 +       PCF50633_INT3_USBLIMON  = 0x10,
147018 +       PCF50633_INT3_USBLIMOFF = 0x20,
147019 +       PCF50633_INT3_ADCRDY    = 0x40, /* ADC conversion finished */
147020 +       PCF50633_INT3_ONKEY1S   = 0x80, /* ONKEY pressed 1 second */
147021 +};
147022 +
147023 +enum pcf50633_reg_int4 {
147024 +       PCF50633_INT4_LOWSYS            = 0x01,
147025 +       PCF50633_INT4_LOWBAT            = 0x02,
147026 +       PCF50633_INT4_HIGHTMP           = 0x04,
147027 +       PCF50633_INT4_AUTOPWRFAIL       = 0x08,
147028 +       PCF50633_INT4_DWN1PWRFAIL       = 0x10,
147029 +       PCF50633_INT4_DWN2PWRFAIL       = 0x20,
147030 +       PCF50633_INT4_LEDPWRFAIL        = 0x40,
147031 +       PCF50633_INT4_LEDOVP            = 0x80,
147032 +};
147033 +
147034 +enum pcf50633_reg_int5 {
147035 +       PCF50633_INT5_LDO1PWRFAIL       = 0x01,
147036 +       PCF50633_INT5_LDO2PWRFAIL       = 0x02,
147037 +       PCF50633_INT5_LDO3PWRFAIL       = 0x04,
147038 +       PCF50633_INT5_LDO4PWRFAIL       = 0x08,
147039 +       PCF50633_INT5_LDO5PWRFAIL       = 0x10,
147040 +       PCF50633_INT5_LDO6PWRFAIL       = 0x20,
147041 +       PCF50633_INT5_HCLDOPWRFAIL      = 0x40,
147042 +       PCF50633_INT5_HCLDOOVL          = 0x80,
147043 +};
147044 +
147045 +struct pcf50633_data;
147046 +
147047 +extern void
147048 +pcf50633_go_standby(struct pcf50633_data *pcf);
147049 +
147050 +enum pcf50633_gpio {
147051 +       PCF50633_GPIO1 = 1,
147052 +       PCF50633_GPIO2 = 2,
147053 +       PCF50633_GPIO3 = 3,
147054 +       PCF50633_GPO = 4,
147055 +};
147056 +
147057 +extern void
147058 +pcf50633_gpio_set(struct pcf50633_data *pcf, enum pcf50633_gpio gpio, int on);
147059 +
147060 +extern int
147061 +pcf50633_gpio_get(struct pcf50633_data *pcf, enum pcf50633_gpio gpio);
147062 +
147063 +extern int
147064 +pcf50633_adc_async_read(struct pcf50633_data *pcf, int mux, int avg,
147065 +               void (*callback)(struct pcf50633_data *, void *, int),
147066 +               void *callback_param);
147067 +
147068 +extern int
147069 +pcf50633_adc_sync_read(struct pcf50633_data *pcf, int mux, int avg);
147070 +
147071 +extern void
147072 +pcf50633_backlight_resume(struct pcf50633_data *pcf);
147073 +
147074 +extern u_int16_t
147075 +pcf50633_battvolt(struct pcf50633_data *pcf);
147076 +
147077 +extern int
147078 +pcf50633_report_resumers(struct pcf50633_data *pcf, char *buf);
147079 +
147080 +extern int
147081 +pcf50633_notify_usb_current_limit_change(struct pcf50633_data *pcf,
147082 +                                                              unsigned int ma);
147083 +extern int
147084 +pcf50633_wait_for_ready(struct pcf50633_data *pcf, int timeout_ms,
147085 +                                                               char *name);
147086 +
147087 +/* 0 = initialized and resumed and ready to roll, !=0 = either not
147088 + * initialized or not resumed yet
147089 + */
147090 +extern int
147091 +pcf50633_ready(struct pcf50633_data *pcf);
147092 +
147093 +#define PCF50633_FEAT_EXTON    0x00000001      /* not yet supported */
147094 +#define PCF50633_FEAT_MBC      0x00000002
147095 +#define PCF50633_FEAT_BBC      0x00000004      /* not yet supported */
147096 +#define PCF50633_FEAT_RTC      0x00000040
147097 +#define PCF50633_FEAT_CHGCUR   0x00000100
147098 +#define PCF50633_FEAT_BATVOLT  0x00000200
147099 +#define PCF50633_FEAT_BATTEMP  0x00000400
147100 +#define PCF50633_FEAT_PWM_BL   0x00000800
147101 +
147102 +enum charger_type {
147103 +       CHARGER_TYPE_NONE = 0,
147104 +       CHARGER_TYPE_HOSTUSB,
147105 +       CHARGER_TYPE_1A
147106 +};
147107 +
147108 +#define ADC_NOM_CHG_DETECT_1A 6
147109 +#define ADC_NOM_CHG_DETECT_NONE 43
147110 +
147111 +#define MAX_ADC_FIFO_DEPTH 8
147112 +
147113 +enum pcf50633_suspend_states {
147114 +       PCF50633_SS_RUNNING,
147115 +       PCF50633_SS_STARTING_SUSPEND,
147116 +       PCF50633_SS_COMPLETED_SUSPEND,
147117 +       PCF50633_SS_RESUMING_BUT_NOT_US_YET,
147118 +       PCF50633_SS_STARTING_RESUME,
147119 +       PCF50633_SS_COMPLETED_RESUME,
147120 +};
147121 +
147122 +struct pcf50633_data;
147123 +
147124 +struct pcf50633_platform_data {
147125 +       /* general */
147126 +       unsigned int used_features;
147127 +       unsigned int onkey_seconds_sig_init;
147128 +       unsigned int onkey_seconds_shutdown;
147129 +
147130 +       /* callback to attach platform children (to enforce suspend / resume
147131 +        * ordering */
147132 +       void (*attach_child_devices)(struct device *parent_device);
147133 +
147134 +       /* charger related */
147135 +       unsigned int r_fix_batt;
147136 +       unsigned int r_fix_batt_par;
147137 +       unsigned int r_sense_milli;
147138 +       int flag_use_apm_emulation;
147139 +
147140 +       unsigned char resumers[5];
147141 +
147142 +       struct {
147143 +               u_int8_t mbcc3; /* charger voltage / current */
147144 +       } charger;
147145 +       pmu_cb cb;
147146 +
147147 +       struct regulator_init_data reg_init_data[__NUM_PCF50633_REGULATORS];
147148 +
147149 +       /* Called when a regulator has been registered */
147150 +       void (*regulator_registered)(struct pcf50633_data *pcf, int id);
147151 +
147152 +       /* Runtime data */
147153 +       struct pcf50633_data *pcf;
147154 +};
147155 +
147156 +enum pfc50633_regs {
147157 +       PCF50633_REG_VERSION    = 0x00,
147158 +       PCF50633_REG_VARIANT    = 0x01,
147159 +       PCF50633_REG_INT1       = 0x02, /* Interrupt Status */
147160 +       PCF50633_REG_INT2       = 0x03, /* Interrupt Status */
147161 +       PCF50633_REG_INT3       = 0x04, /* Interrupt Status */
147162 +       PCF50633_REG_INT4       = 0x05, /* Interrupt Status */
147163 +       PCF50633_REG_INT5       = 0x06, /* Interrupt Status */
147164 +       PCF50633_REG_INT1M      = 0x07, /* Interrupt Mask */
147165 +       PCF50633_REG_INT2M      = 0x08, /* Interrupt Mask */
147166 +       PCF50633_REG_INT3M      = 0x09, /* Interrupt Mask */
147167 +       PCF50633_REG_INT4M      = 0x0a, /* Interrupt Mask */
147168 +       PCF50633_REG_INT5M      = 0x0b, /* Interrupt Mask */
147169 +       PCF50633_REG_OOCSHDWN   = 0x0c,
147170 +       PCF50633_REG_OOCWAKE    = 0x0d,
147171 +       PCF50633_REG_OOCTIM1    = 0x0e,
147172 +       PCF50633_REG_OOCTIM2    = 0x0f,
147173 +       PCF50633_REG_OOCMODE    = 0x10,
147174 +       PCF50633_REG_OOCCTL     = 0x11,
147175 +       PCF50633_REG_OOCSTAT    = 0x12,
147176 +       PCF50633_REG_GPIOCTL    = 0x13,
147177 +       PCF50633_REG_GPIO1CFG   = 0x14,
147178 +       PCF50633_REG_GPIO2CFG   = 0x15,
147179 +       PCF50633_REG_GPIO3CFG   = 0x16,
147180 +       PCF50633_REG_GPOCFG     = 0x17,
147181 +       PCF50633_REG_BVMCTL     = 0x18,
147182 +       PCF50633_REG_SVMCTL     = 0x19,
147183 +       PCF50633_REG_AUTOOUT    = 0x1a,
147184 +       PCF50633_REG_AUTOENA    = 0x1b,
147185 +       PCF50633_REG_AUTOCTL    = 0x1c,
147186 +       PCF50633_REG_AUTOMXC    = 0x1d,
147187 +       PCF50633_REG_DOWN1OUT   = 0x1e,
147188 +       PCF50633_REG_DOWN1ENA   = 0x1f,
147189 +       PCF50633_REG_DOWN1CTL   = 0x20,
147190 +       PCF50633_REG_DOWN1MXC   = 0x21,
147191 +       PCF50633_REG_DOWN2OUT   = 0x22,
147192 +       PCF50633_REG_DOWN2ENA   = 0x23,
147193 +       PCF50633_REG_DOWN2CTL   = 0x24,
147194 +       PCF50633_REG_DOWN2MXC   = 0x25,
147195 +       PCF50633_REG_MEMLDOOUT  = 0x26,
147196 +       PCF50633_REG_MEMLDOENA  = 0x27,
147197 +       PCF50633_REG_LEDOUT     = 0x28,
147198 +       PCF50633_REG_LEDENA     = 0x29,
147199 +       PCF50633_REG_LEDCTL     = 0x2a,
147200 +       PCF50633_REG_LEDDIM     = 0x2b,
147201 +       /* reserved */
147202 +       PCF50633_REG_LDO1OUT    = 0x2d,
147203 +       PCF50633_REG_LDO1ENA    = 0x2e,
147204 +       PCF50633_REG_LDO2OUT    = 0x2f,
147205 +       PCF50633_REG_LDO2ENA    = 0x30,
147206 +       PCF50633_REG_LDO3OUT    = 0x31,
147207 +       PCF50633_REG_LDO3ENA    = 0x32,
147208 +       PCF50633_REG_LDO4OUT    = 0x33,
147209 +       PCF50633_REG_LDO4ENA    = 0x34,
147210 +       PCF50633_REG_LDO5OUT    = 0x35,
147211 +       PCF50633_REG_LDO5ENA    = 0x36,
147212 +       PCF50633_REG_LDO6OUT    = 0x37,
147213 +       PCF50633_REG_LDO6ENA    = 0x38,
147214 +       PCF50633_REG_HCLDOOUT   = 0x39,
147215 +       PCF50633_REG_HCLDOENA   = 0x3a,
147216 +       PCF50633_REG_STBYCTL1   = 0x3b,
147217 +       PCF50633_REG_STBYCTL2   = 0x3c,
147218 +       PCF50633_REG_DEBPF1     = 0x3d,
147219 +       PCF50633_REG_DEBPF2     = 0x3e,
147220 +       PCF50633_REG_DEBPF3     = 0x3f,
147221 +       PCF50633_REG_HCLDOOVL   = 0x40,
147222 +       PCF50633_REG_DCDCSTAT   = 0x41,
147223 +       PCF50633_REG_LDOSTAT    = 0x42,
147224 +       PCF50633_REG_MBCC1      = 0x43,
147225 +       PCF50633_REG_MBCC2      = 0x44,
147226 +       PCF50633_REG_MBCC3      = 0x45,
147227 +       PCF50633_REG_MBCC4      = 0x46,
147228 +       PCF50633_REG_MBCC5      = 0x47,
147229 +       PCF50633_REG_MBCC6      = 0x48,
147230 +       PCF50633_REG_MBCC7      = 0x49,
147231 +       PCF50633_REG_MBCC8      = 0x4a,
147232 +       PCF50633_REG_MBCS1      = 0x4b,
147233 +       PCF50633_REG_MBCS2      = 0x4c,
147234 +       PCF50633_REG_MBCS3      = 0x4d,
147235 +       PCF50633_REG_BBCCTL     = 0x4e,
147236 +       PCF50633_REG_ALMGAIN    = 0x4f,
147237 +       PCF50633_REG_ALMDATA    = 0x50,
147238 +       /* reserved */
147239 +       PCF50633_REG_ADCC3      = 0x52,
147240 +       PCF50633_REG_ADCC2      = 0x53,
147241 +       PCF50633_REG_ADCC1      = 0x54,
147242 +       PCF50633_REG_ADCS1      = 0x55,
147243 +       PCF50633_REG_ADCS2      = 0x56,
147244 +       PCF50633_REG_ADCS3      = 0x57,
147245 +       /* reserved */
147246 +       PCF50633_REG_RTCSC      = 0x59, /* Second */
147247 +       PCF50633_REG_RTCMN      = 0x5a, /* Minute */
147248 +       PCF50633_REG_RTCHR      = 0x5b, /* Hour */
147249 +       PCF50633_REG_RTCWD      = 0x5c, /* Weekday */
147250 +       PCF50633_REG_RTCDT      = 0x5d, /* Day */
147251 +       PCF50633_REG_RTCMT      = 0x5e, /* Month */
147252 +       PCF50633_REG_RTCYR      = 0x5f, /* Year */
147253 +       PCF50633_REG_RTCSCA     = 0x60, /* Alarm Second */
147254 +       PCF50633_REG_RTCMNA     = 0x61, /* Alarm Minute */
147255 +       PCF50633_REG_RTCHRA     = 0x62, /* Alarm Hour */
147256 +       PCF50633_REG_RTCWDA     = 0x63, /* Alarm Weekday */
147257 +       PCF50633_REG_RTCDTA     = 0x64, /* Alarm Day */
147258 +       PCF50633_REG_RTCMTA     = 0x65, /* Alarm Month */
147259 +       PCF50633_REG_RTCYRA     = 0x66, /* Alarm Year */
147260 +
147261 +       PCF50633_REG_MEMBYTE0   = 0x67,
147262 +       PCF50633_REG_MEMBYTE1   = 0x68,
147263 +       PCF50633_REG_MEMBYTE2   = 0x69,
147264 +       PCF50633_REG_MEMBYTE3   = 0x6a,
147265 +       PCF50633_REG_MEMBYTE4   = 0x6b,
147266 +       PCF50633_REG_MEMBYTE5   = 0x6c,
147267 +       PCF50633_REG_MEMBYTE6   = 0x6d,
147268 +       PCF50633_REG_MEMBYTE7   = 0x6e,
147269 +       /* reserved */
147270 +       PCF50633_REG_DCDCPFM    = 0x84,
147271 +       __NUM_PCF50633_REGS
147272 +};
147273 +
147274 +
147275 +enum pcf50633_reg_oocshdwn {
147276 +       PCF50633_OOCSHDWN_GOSTDBY       = 0x01,
147277 +       PCF50633_OOCSHDWN_TOTRST        = 0x04,
147278 +       PCF50633_OOCSHDWN_COLDBOOT      = 0x08,
147279 +};
147280 +
147281 +enum pcf50633_reg_oocwake {
147282 +       PCF50633_OOCWAKE_ONKEY          = 0x01,
147283 +       PCF50633_OOCWAKE_EXTON1         = 0x02,
147284 +       PCF50633_OOCWAKE_EXTON2         = 0x04,
147285 +       PCF50633_OOCWAKE_EXTON3         = 0x08,
147286 +       PCF50633_OOCWAKE_RTC            = 0x10,
147287 +       /* reserved */
147288 +       PCF50633_OOCWAKE_USB            = 0x40,
147289 +       PCF50633_OOCWAKE_ADP            = 0x80,
147290 +};
147291 +
147292 +enum pcf50633_reg_mbcc1 {
147293 +       PCF50633_MBCC1_CHGENA           = 0x01, /* Charger enable */
147294 +       PCF50633_MBCC1_AUTOSTOP         = 0x02,
147295 +       PCF50633_MBCC1_AUTORES          = 0x04, /* automatic resume */
147296 +       PCF50633_MBCC1_RESUME           = 0x08, /* explicit resume cmd */
147297 +       PCF50633_MBCC1_RESTART          = 0x10, /* restart charging */
147298 +       PCF50633_MBCC1_PREWDTIME_60M    = 0x20, /* max. precharging time */
147299 +       PCF50633_MBCC1_WDTIME_1H        = 0x00,
147300 +       PCF50633_MBCC1_WDTIME_2H        = 0x40,
147301 +       PCF50633_MBCC1_WDTIME_4H        = 0x80,
147302 +       PCF50633_MBCC1_WDTIME_6H        = 0xc0,
147303 +};
147304 +#define PCF50633_MBCC1_WDTIME_MASK       0xc0
147305 +
147306 +enum pcf50633_reg_mbcc2 {
147307 +       PCF50633_MBCC2_VBATCOND_2V7     = 0x00,
147308 +       PCF50633_MBCC2_VBATCOND_2V85    = 0x01,
147309 +       PCF50633_MBCC2_VBATCOND_3V0     = 0x02,
147310 +       PCF50633_MBCC2_VBATCOND_3V15    = 0x03,
147311 +       PCF50633_MBCC2_VMAX_4V          = 0x00,
147312 +       PCF50633_MBCC2_VMAX_4V20        = 0x28,
147313 +       PCF50633_MBCC2_VRESDEBTIME_64S  = 0x80, /* debounce time (32/64sec) */
147314 +};
147315 +#define        PCF50633_MBCC2_VBATCOND_MASK      0x03
147316 +#define PCF50633_MBCC2_VMAX_MASK         0x3c
147317 +
147318 +enum pcf50633_reg_adcc1 {
147319 +       PCF50633_ADCC1_ADCSTART         = 0x01,
147320 +       PCF50633_ADCC1_RES_10BIT        = 0x02,
147321 +       PCF50633_ADCC1_AVERAGE_NO       = 0x00,
147322 +       PCF50633_ADCC1_AVERAGE_4        = 0x04,
147323 +       PCF50633_ADCC1_AVERAGE_8        = 0x08,
147324 +       PCF50633_ADCC1_AVERAGE_16       = 0x0c,
147325 +
147326 +       PCF50633_ADCC1_MUX_BATSNS_RES   = 0x00,
147327 +       PCF50633_ADCC1_MUX_BATSNS_SUBTR = 0x10,
147328 +       PCF50633_ADCC1_MUX_ADCIN2_RES   = 0x20,
147329 +       PCF50633_ADCC1_MUX_ADCIN2_SUBTR = 0x30,
147330 +       PCF50633_ADCC1_MUX_BATTEMP      = 0x60,
147331 +       PCF50633_ADCC1_MUX_ADCIN1       = 0x70,
147332 +};
147333 +#define PCF50633_ADCC1_AVERAGE_MASK    0x0c
147334 +#define        PCF50633_ADCC1_ADCMUX_MASK      0xf0
147335 +
147336 +enum pcf50633_reg_adcc2 {
147337 +       PCF50633_ADCC2_RATIO_NONE       = 0x00,
147338 +       PCF50633_ADCC2_RATIO_BATTEMP    = 0x01,
147339 +       PCF50633_ADCC2_RATIO_ADCIN1     = 0x02,
147340 +       PCF50633_ADCC2_RATIO_BOTH       = 0x03,
147341 +       PCF50633_ADCC2_RATIOSETTL_100US = 0x04,
147342 +};
147343 +#define PCF50633_ADCC2_RATIO_MASK      0x03
147344 +
147345 +enum pcf50633_reg_adcc3 {
147346 +       PCF50633_ADCC3_ACCSW_EN         = 0x01,
147347 +       PCF50633_ADCC3_NTCSW_EN         = 0x04,
147348 +       PCF50633_ADCC3_RES_DIV_TWO      = 0x10,
147349 +       PCF50633_ADCC3_RES_DIV_THREE    = 0x00,
147350 +};
147351 +
147352 +enum pcf50633_reg_adcs3 {
147353 +       PCF50633_ADCS3_REF_NTCSW        = 0x00,
147354 +       PCF50633_ADCS3_REF_ACCSW        = 0x10,
147355 +       PCF50633_ADCS3_REF_2V0          = 0x20,
147356 +       PCF50633_ADCS3_REF_VISA         = 0x30,
147357 +       PCF50633_ADCS3_REF_2V0_2        = 0x70,
147358 +       PCF50633_ADCS3_ADCRDY           = 0x80,
147359 +};
147360 +#define PCF50633_ADCS3_ADCDAT1L_MASK   0x03
147361 +#define PCF50633_ADCS3_ADCDAT2L_MASK   0x0c
147362 +#define PCF50633_ADCS3_ADCDAT2L_SHIFT  2
147363 +#define PCF50633_ASCS3_REF_MASK                0x70
147364 +
147365 +enum pcf50633_regulator_enable {
147366 +       PCF50633_REGULATOR_ON           = 0x01,
147367 +       PCF50633_REGULATOR_ON_GPIO1     = 0x02,
147368 +       PCF50633_REGULATOR_ON_GPIO2     = 0x04,
147369 +       PCF50633_REGULATOR_ON_GPIO3     = 0x08,
147370 +};
147371 +#define PCF50633_REGULATOR_ON_MASK     0x0f
147372 +
147373 +enum pcf50633_regulator_phase {
147374 +       PCF50633_REGULATOR_ACTPH1       = 0x00,
147375 +       PCF50633_REGULATOR_ACTPH2       = 0x10,
147376 +       PCF50633_REGULATOR_ACTPH3       = 0x20,
147377 +       PCF50633_REGULATOR_ACTPH4       = 0x30,
147378 +};
147379 +#define PCF50633_REGULATOR_ACTPH_MASK  0x30
147380 +
147381 +enum pcf50633_reg_gpocfg {
147382 +       PCF50633_GPOCFG_GPOSEL_0        = 0x00,
147383 +       PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01,
147384 +       PCF50633_GPOCFG_GPOSEL_SYSxOK   = 0x02,
147385 +       PCF50633_GPOCFG_GPOSEL_CLK32K   = 0x03,
147386 +       PCF50633_GPOCFG_GPOSEL_ADAPUSB  = 0x04,
147387 +       PCF50633_GPOCFG_GPOSEL_USBxOK   = 0x05,
147388 +       PCF50633_GPOCFG_GPOSEL_ACTPH4   = 0x06,
147389 +       PCF50633_GPOCFG_GPOSEL_1        = 0x07,
147390 +       PCF50633_GPOCFG_GPOSEL_INVERSE  = 0x08,
147391 +};
147392 +#define PCF50633_GPOCFG_GPOSEL_MASK    0x07
147393 +
147394 +#if 0
147395 +enum pcf50633_reg_mbcc1 {
147396 +       PCF50633_MBCC1_CHGENA           = 0x01,
147397 +       PCF50633_MBCC1_AUTOSTOP         = 0x02,
147398 +       PCF50633_MBCC1_AUTORES          = 0x04,
147399 +       PCF50633_MBCC1_RESUME           = 0x08,
147400 +       PCF50633_MBCC1_RESTART          = 0x10,
147401 +       PCF50633_MBCC1_PREWDTIME_30MIN  = 0x00,
147402 +       PCF50633_MBCC1_PREWDTIME_60MIN  = 0x20,
147403 +       PCF50633_MBCC1_WDTIME_2HRS      = 0x40,
147404 +       PCF50633_MBCC1_WDTIME_4HRS      = 0x80,
147405 +       PCF50633_MBCC1_WDTIME_6HRS      = 0xc0,
147406 +};
147407 +
147408 +enum pcf50633_reg_mbcc2 {
147409 +       PCF50633_MBCC2_VBATCOND_2V7     = 0x00,
147410 +       PCF50633_MBCC2_VBATCOND_2V85    = 0x01,
147411 +       PCF50633_MBCC2_VBATCOND_3V0     = 0x02,
147412 +       PCF50633_MBCC2_VBATCOND_3V15    = 0x03,
147413 +       PCF50633_MBCC2_VRESDEBTIME_64S  = 0x80,
147414 +};
147415 +#define PCF50633_MBCC2_VMAX_MASK       0x3c
147416 +#endif
147417 +
147418 +enum pcf50633_reg_mbcc7 {
147419 +       PCF50633_MBCC7_USB_100mA        = 0x00,
147420 +       PCF50633_MBCC7_USB_500mA        = 0x01,
147421 +       PCF50633_MBCC7_USB_1000mA       = 0x02,
147422 +       PCF50633_MBCC7_USB_SUSPEND      = 0x03,
147423 +       PCF50633_MBCC7_BATTEMP_EN       = 0x04,
147424 +       PCF50633_MBCC7_BATSYSIMAX_1A6   = 0x00,
147425 +       PCF50633_MBCC7_BATSYSIMAX_1A8   = 0x40,
147426 +       PCF50633_MBCC7_BATSYSIMAX_2A0   = 0x80,
147427 +       PCF50633_MBCC7_BATSYSIMAX_2A2   = 0xc0,
147428 +};
147429 +#define PCF56033_MBCC7_USB_MASK                0x03
147430 +
147431 +enum pcf50633_reg_mbcc8 {
147432 +       PCF50633_MBCC8_USBENASUS        = 0x10,
147433 +};
147434 +
147435 +enum pcf50633_reg_mbcs1 {
147436 +       PCF50633_MBCS1_USBPRES          = 0x01,
147437 +       PCF50633_MBCS1_USBOK            = 0x02,
147438 +       PCF50633_MBCS1_ADAPTPRES        = 0x04,
147439 +       PCF50633_MBCS1_ADAPTOK          = 0x08,
147440 +       PCF50633_MBCS1_TBAT_OK          = 0x00,
147441 +       PCF50633_MBCS1_TBAT_ABOVE       = 0x10,
147442 +       PCF50633_MBCS1_TBAT_BELOW       = 0x20,
147443 +       PCF50633_MBCS1_TBAT_UNDEF       = 0x30,
147444 +       PCF50633_MBCS1_PREWDTEXP        = 0x40,
147445 +       PCF50633_MBCS1_WDTEXP           = 0x80,
147446 +};
147447 +
147448 +enum pcf50633_reg_mbcs2_mbcmod {
147449 +       PCF50633_MBCS2_MBC_PLAY         = 0x00,
147450 +       PCF50633_MBCS2_MBC_USB_PRE      = 0x01,
147451 +       PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02,
147452 +       PCF50633_MBCS2_MBC_USB_FAST     = 0x03,
147453 +       PCF50633_MBCS2_MBC_USB_FAST_WAIT= 0x04,
147454 +       PCF50633_MBCS2_MBC_USB_SUSPEND  = 0x05,
147455 +       PCF50633_MBCS2_MBC_ADP_PRE      = 0x06,
147456 +       PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07,
147457 +       PCF50633_MBCS2_MBC_ADP_FAST     = 0x08,
147458 +       PCF50633_MBCS2_MBC_ADP_FAST_WAIT= 0x09,
147459 +       PCF50633_MBCS2_MBC_BAT_FULL     = 0x0a,
147460 +       PCF50633_MBCS2_MBC_HALT         = 0x0b,
147461 +};
147462 +#define PCF50633_MBCS2_MBC_MASK                0x0f
147463 +enum pcf50633_reg_mbcs2_chgstat {
147464 +       PCF50633_MBCS2_CHGS_NONE        = 0x00,
147465 +       PCF50633_MBCS2_CHGS_ADAPTER     = 0x10,
147466 +       PCF50633_MBCS2_CHGS_USB         = 0x20,
147467 +       PCF50633_MBCS2_CHGS_BOTH        = 0x30,
147468 +};
147469 +#define PCF50633_MBCS2_RESSTAT_AUTO    0x40
147470 +
147471 +enum pcf50633_reg_mbcs3 {
147472 +       PCF50633_MBCS3_USBLIM_PLAY      = 0x01,
147473 +       PCF50633_MBCS3_USBLIM_CGH       = 0x02,
147474 +       PCF50633_MBCS3_TLIM_PLAY        = 0x04,
147475 +       PCF50633_MBCS3_TLIM_CHG         = 0x08,
147476 +       PCF50633_MBCS3_ILIM             = 0x10, /* 1: Ibat > Icutoff */
147477 +       PCF50633_MBCS3_VLIM             = 0x20, /* 1: Vbat == Vmax */
147478 +       PCF50633_MBCS3_VBATSTAT         = 0x40, /* 1: Vbat > Vbatcond */
147479 +       PCF50633_MBCS3_VRES             = 0x80, /* 1: Vbat > Vth(RES) */
147480 +};
147481 +
147482 +struct adc_request {
147483 +       int mux;
147484 +       int avg;
147485 +       int result;
147486 +       void (*callback)(struct pcf50633_data *, void *, int);
147487 +       void *callback_param;
147488 +
147489 +       /* Used in case of sync requests */
147490 +       struct completion completion;
147491 +};
147492 +
147493 +struct pcf50633_data {
147494 +       struct i2c_client *client;
147495 +       struct pcf50633_platform_data *pdata;
147496 +       struct backlight_device *backlight;
147497 +       struct mutex lock;
147498 +       unsigned int flags;
147499 +       unsigned int working;
147500 +       struct mutex working_lock;
147501 +       struct work_struct work;
147502 +       struct rtc_device *rtc;
147503 +       struct input_dev *input_dev;
147504 +       int allow_close;
147505 +       int onkey_seconds;
147506 +       int irq;
147507 +       enum pcf50633_suspend_states suspend_state;
147508 +       int usb_removal_count;
147509 +       u8 pcfirq_resume[5];
147510 +       int probe_completed;
147511 +       int suppress_onkey_events;
147512 +
147513 +       /* if he pulls battery while charging, we notice that and correctly
147514 +        * report that the charger is idle.  But there is no interrupt that
147515 +        * fires if he puts a battery back in and charging resumes.  So when
147516 +        * the battery is pulled, we run this work function looking for
147517 +        * either charger resumption or USB cable pull
147518 +        */
147519 +       struct mutex working_lock_nobat;
147520 +       struct work_struct work_nobat;
147521 +       int working_nobat;
147522 +       int usb_removal_count_nobat;
147523 +       int jiffies_last_bat_ins;
147524 +
147525 +       /* current limit notification handler stuff */
147526 +       struct mutex working_lock_usb_curlimit;
147527 +       struct work_struct work_usb_curlimit;
147528 +       int pending_curlimit;
147529 +       int usb_removal_count_usb_curlimit;
147530 +
147531 +       int last_curlim_set;
147532 +
147533 +       int coldplug_done; /* cleared by probe, set by first work service */
147534 +       int flag_bat_voltage_read; /* ipc to /sys batt voltage read func */
147535 +
147536 +       /* we have a FIFO of ADC measurement requests that are used only by
147537 +        * the workqueue service code after the ADC completion interrupt
147538 +        */
147539 +       struct adc_request *adc_queue[MAX_ADC_FIFO_DEPTH]; /* amount of averaging */
147540 +       int adc_queue_head; /* head owned by foreground code */
147541 +       int adc_queue_tail; /* tail owned by service code */
147542 +
147543 +       struct platform_device *regulator_pdev[__NUM_PCF50633_REGULATORS];
147544 +};
147545 +
147546 +/* this is to be provided by the board implementation */
147547 +extern const u_int8_t pcf50633_initial_regs[__NUM_PCF50633_REGS];
147548 +
147549 +int pcf50633_read(struct pcf50633_data *pcf, u_int8_t reg,
147550 +                                               int nr_regs, u_int8_t *data);
147551 +
147552 +int pcf50633_write(struct pcf50633_data *pcf, u_int8_t reg,
147553 +                                               int nr_regs, u_int8_t *data);
147554 +
147555 +int pcf50633_reg_write(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val);
147556 +
147557 +u_int8_t pcf50633_reg_read(struct pcf50633_data *pcf, u_int8_t reg);
147558 +
147559 +int pcf50633_reg_set_bit_mask(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t mask, u_int8_t val);
147560 +int pcf50633_reg_clear_bits(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t bits);
147561 +
147562 +void pcf50633_charge_autofast(int on);
147563 +#endif /* _PCF50633_H */
147564 +
147565 --- /dev/null
147566 +++ b/include/linux/pcf506xx.h
147567 @@ -0,0 +1,34 @@
147568 +#ifndef _LINUX_PCF506XX_H
147569 +#define _LINUX_PCF506XX_H
147570 +
147571 +
147572 +#define PMU_VRAIL_F_SUSPEND_ON 0x00000001      /* Remains on during suspend */
147573 +#define PMU_VRAIL_F_UNUSED     0x00000002      /* This rail is not used */
147574 +struct pmu_voltage_rail {
147575 +       char *name;
147576 +       unsigned int flags;
147577 +       struct {
147578 +               unsigned int init;
147579 +               unsigned int max;
147580 +       } voltage;
147581 +};
147582 +
147583 +enum pmu_event {
147584 +       PMU_EVT_NONE,
147585 +       PMU_EVT_INSERT,
147586 +       PMU_EVT_REMOVE,
147587 +#ifdef CONFIG_SENSORS_PCF50633
147588 +       PMU_EVT_USB_INSERT,
147589 +       PMU_EVT_USB_REMOVE,
147590 +#endif
147591 +       PMU_EVT_CHARGER_ACTIVE,
147592 +       PMU_EVT_CHARGER_IDLE,
147593 +       PMU_EVT_CHARGER_CHANGE,
147594 +       __NUM_PMU_EVTS
147595 +};
147596 +
147597 +typedef int (*pmu_cb)(struct device *dev, unsigned int feature,
147598 +                  enum pmu_event event);
147599 +
147600 +
147601 +#endif /* !_LINUX_PCF506XX_H */
147602 --- /dev/null
147603 +++ b/include/linux/regulator/pcf50633.h
147604 @@ -0,0 +1,3 @@
147605 +#include <linux/pcf50633.h>
147606 +
147607 +int pcf50633_regulator_init(struct pcf50633_data *, int);
147608 --- /dev/null
147609 +++ b/include/linux/resume-dependency.h
147610 @@ -0,0 +1,114 @@
147611 +#ifndef __RESUME_DEPENDENCY_H__
147612 +#define __RESUME_DEPENDENCY_H__
147613 +
147614 +/* Resume dependency framework
147615 + *
147616 + * (C) 2008 Openmoko, Inc.
147617 + * Author: Andy Green <andy@openmoko.com>
147618 + *
147619 + * This program is free software; you can redistribute it and/or
147620 + * modify it under the terms of the GNU General Public License as
147621 + * published by the Free Software Foundation; version 2.1.
147622 + *
147623 + * This program is distributed in the hope that it will be useful,
147624 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
147625 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
147626 + * GNU General Public License for more details.
147627 + *
147628 + * You should have received a copy of the GNU General Public License
147629 + * along with this program; if not, write to the Free Software
147630 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
147631 + * MA 02111-1307 USA
147632 + *
147633 + */
147634 +
147635 +#include <linux/list.h>
147636 +
147637 +struct resume_dependency {
147638 +       struct list_head list;
147639 +
147640 +       void (*callback)(void *); /* called with context as arg */
147641 +       void * context;
147642 +       int called_flag; /* set to 1 after called, use for multi dep */
147643 +};
147644 +
147645 +/* if you are a driver accept to have other drivers as dependencies, you need to
147646 + * instantiate a struct resume_dependency above, then initialize it by invoking
147647 + * init_resume_dependency_list() on it
147648 + */
147649 +
147650 +#define init_resume_dependency_list(_head) \
147651 +       printk(KERN_INFO "##### init_resume_dependency_list(head=%p)\n", (_head)); \
147652 +       INIT_LIST_HEAD(&(_head)->list);
147653 +
147654 +
147655 +/* if your resume function depends on something else being resumed first, you
147656 + * can register the dependency by calling this in your suspend function with
147657 + * head being the list held by the thing you are dependent on, and dep being
147658 + * your struct resume_dependency
147659 + */
147660 +
147661 +#define register_resume_dependency(_head, _dep) { \
147662 +       struct list_head *_pos, *_q; \
147663 +       struct resume_dependency *_d; \
147664 +\
147665 +       printk(KERN_ERR "##### register_resume_dependency(head=%p, dep=%p)\n", (_head), (_dep)); \
147666 +       (_dep)->called_flag = 1; \
147667 +       list_for_each_safe(_pos, _q, &((_head)->list)) { \
147668 +               _d = list_entry(_pos, struct resume_dependency, list); \
147669 +               if (_d == (_dep)) { \
147670 +                       list_del(_pos); \
147671 +                       printk(KERN_ERR "#####   duplicate dependency removed first\n"); \
147672 +               } \
147673 +       } \
147674 +       list_add(&(_dep)->list, &(_head)->list); \
147675 +}
147676 +
147677 +/* In the resume function that things can be dependent on, at the end you
147678 + * invoke this macro.  This calls back the dependent resumes now it is safe to
147679 + * use the resumed thing they were dependent on.
147680 + */
147681 +
147682 +#define callback_all_resume_dependencies(_head) { \
147683 +       struct list_head *_pos, *_q; \
147684 +       struct resume_dependency *_dep; \
147685 +\
147686 +       printk(KERN_ERR "##### callback_all_resume_dependencies(head=%p)\n", (_head)); \
147687 +       list_for_each_safe(_pos, _q, &((_head)->list)) { \
147688 +               _dep = list_entry(_pos, struct resume_dependency, list); \
147689 +               printk(KERN_ERR "#####   callback list entry (head=%p, dep=%p)\n", (_head), (_dep)); \
147690 +               _dep->called_flag = 1; \
147691 +               printk(KERN_ERR "#####      callback=%p(context=%p))\n", (_dep->callback),(_dep->context)); \
147692 +               (_dep->callback)(_dep->context); \
147693 +               list_del(_pos); \
147694 +       } \
147695 +}
147696 +
147697 +/* When a dependency is added, it is not actually active; the dependent resume
147698 + * handler will function as normal.  The dependency is activated by the suspend
147699 + * handler for the driver that will be doing the callbacks.  This ensures that
147700 + * if the suspend is aborted for any reason (error, driver busy, etc), that all
147701 + * suspended drivers will resume, even if the driver upon which they are dependent
147702 + * did not suspend, and hence will not resume, and thus would be unable to perform
147703 + * the callbacks.
147704 + */
147705 +
147706 +#define activate_all_resume_dependencies(_head) { \
147707 +       struct list_head *_pos, *_q; \
147708 +       struct resume_dependency *_dep; \
147709 +\
147710 +       printk(KERN_ERR "##### activate_all_resume_dependencies(head=%p)\n", (_head)); \
147711 +       list_for_each_safe(_pos, _q, &((_head)->list)) { \
147712 +               _dep = list_entry(_pos, struct resume_dependency, list); \
147713 +               printk(KERN_ERR "#####   activating callback list entry (head=%p, dep=%p)\n", (_head), (_dep)); \
147714 +               _dep->called_flag = 0; \
147715 +       } \
147716 +}
147717 +
147718 +/* if your resume action is dependent on multiple drivers being resumed already,
147719 + * register the same callback with each driver you are dependent on, and check
147720 + * .called_flag for all of the struct resume_dependency.  When they are all 1
147721 + * you know it is the last callback and you can resume, otherwise just return
147722 + */
147723 +
147724 +#endif
147725 --- /dev/null
147726 +++ b/include/linux/rtc/pcf50633.h
147727 @@ -0,0 +1,9 @@
147728 +enum pcf50633_rtc_event {
147729 +        PCF50633_RTC_EVENT_ALARM,
147730 +        PCF50633_RTC_EVENT_SECOND,
147731 +};
147732 +
147733 +extern void pcf50633_rtc_handle_event(struct pcf50633_data *pcf,
147734 +                                        enum pcf50633_rtc_event evt);
147735 +
147736 +
147737 --- a/include/linux/serial_core.h
147738 +++ b/include/linux/serial_core.h
147739 @@ -158,6 +158,8 @@
147740  /* SH-SCI */
147741  #define PORT_SCIFA     83
147742
147743 +#define PORT_S3C6400   83
147744 +
147745  #ifdef __KERNEL__
147746
147747  #include <linux/compiler.h>
147748 --- /dev/null
147749 +++ b/include/linux/spi/glamo.h
147750 @@ -0,0 +1,28 @@
147751 +#ifndef __GLAMO_SPI_H
147752 +#define __GLAMO_SPI_H
147753 +
147754 +#include <linux/glamo-gpio.h>
147755 +
147756 +struct spi_board_info;
147757 +struct glamofb_handle;
147758 +struct glamo_core;
147759 +
147760 +struct glamo_spi_info {
147761 +       unsigned long           board_size;
147762 +       struct spi_board_info   *board_info;
147763 +       struct glamofb_handle   *glamofb_handle;
147764 +};
147765 +
147766 +struct glamo_spigpio_info {
147767 +       unsigned int            pin_clk;
147768 +       unsigned int            pin_mosi;
147769 +       unsigned int            pin_miso;
147770 +       unsigned int            pin_cs;
147771 +
147772 +       unsigned int            board_size;
147773 +       struct spi_board_info   *board_info;
147774 +       struct glamo_core       *glamo;
147775 +};
147776 +
147777 +
147778 +#endif
147779 --- a/include/linux/suspend.h
147780 +++ b/include/linux/suspend.h
147781 @@ -146,6 +146,12 @@ struct pbe {
147782         struct pbe *next;
147783  };
147784
147785 +/**
147786 + * global indication we are somewhere between start of suspend and end of
147787 + * resume, nonzero is true
147788 + */
147789 +extern int global_inside_suspend;
147790 +
147791  /* mm/page_alloc.c */
147792  extern void mark_free_pages(struct zone *zone);
147793
147794 --- /dev/null
147795 +++ b/include/linux/ts_filter_group.h
147796 @@ -0,0 +1,39 @@
147797 +#ifndef __TS_FILTER_GROUP_H__
147798 +#define __TS_FILTER_GROUP_H__
147799 +
147800 +#include <linux/ts_filter.h>
147801 +
147802 +/*
147803 + * Touchscreen group filter.
147804 + *
147805 + * Copyright (C) 2008 by Openmoko, Inc.
147806 + * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
147807 + *
147808 + */
147809 +
147810 +struct ts_filter_group_configuration {
147811 +       int extent;
147812 +       int close_enough;
147813 +       int threshold;
147814 +       int attempts;
147815 +};
147816 +
147817 +struct ts_filter_group {
147818 +       struct ts_filter tsf;
147819 +       struct ts_filter_group_configuration *config;
147820 +
147821 +       int N;          /* How many samples we have */
147822 +       int *samples[MAX_TS_FILTER_COORDS];     /* the samples, our input */
147823 +
147824 +       int *group_size;        /* used for temporal computations */
147825 +       int *sorted_samples;    /* used for temporal computations */
147826 +
147827 +       int range_max[MAX_TS_FILTER_COORDS];    /* max computed ranges */
147828 +       int range_min[MAX_TS_FILTER_COORDS];    /* min computed ranges */
147829 +
147830 +       int tries_left;         /* We finish if we don't get enough samples */
147831 +};
147832 +
147833 +extern struct ts_filter_api ts_filter_group_api;
147834 +
147835 +#endif
147836 --- /dev/null
147837 +++ b/include/linux/ts_filter.h
147838 @@ -0,0 +1,56 @@
147839 +#ifndef __TS_FILTER_H__
147840 +#define __TS_FILTER_H__
147841 +
147842 +/*
147843 + * touchscreen filter
147844 + *
147845 + * (c) 2008 Andy Green <andy@openmoko.com>
147846 + */
147847 +
147848 +#include <linux/platform_device.h>
147849 +
147850 +#define MAX_TS_FILTER_CHAIN            4  /* max filters you can chain up */
147851 +#define MAX_TS_FILTER_COORDS           3  /* X, Y and Z (pressure) */
147852 +
147853 +struct ts_filter;
147854 +
147855 +/* operations that a filter can perform
147856 + */
147857 +struct ts_filter_api {
147858 +       struct ts_filter * (*create)(struct platform_device *pdev, void *config,
147859 +                                    int count_coords);
147860 +       void (*destroy)(struct platform_device *pdev, struct ts_filter *filter);
147861 +       void (*clear)(struct ts_filter *filter);
147862 +       int (*process)(struct ts_filter *filter, int *coords);
147863 +       void (*scale)(struct ts_filter *filter, int *coords);
147864 +};
147865 +
147866 +/* this is the common part of all filters, the result
147867 + * we use this type as an otherwise opaque handle on to
147868 + * the actual filter.  Therefore you need one of these
147869 + * at the start of your actual filter struct
147870 + */
147871 +
147872 +struct ts_filter {
147873 +       struct ts_filter *next; /* next in chain */
147874 +       struct ts_filter_api *api; /* operations to use for this object */
147875 +       int count_coords;
147876 +       int coords[MAX_TS_FILTER_COORDS];
147877 +};
147878 +
147879 +/*
147880 + * helper to create a filter chain from array of API pointers and
147881 + * array of config ints... leaves pointers to created filters in list
147882 + * array and fills in ->next pointers to create the chain
147883 + */
147884 +
147885 +extern int ts_filter_create_chain(struct platform_device *pdev,
147886 +                                 struct ts_filter_api **api, void **config,
147887 +                                 struct ts_filter **list, int count_coords);
147888 +
147889 +/* helper to destroy a whole chain from the list of filter pointers */
147890 +
147891 +extern void ts_filter_destroy_chain(struct platform_device *pdev,
147892 +                                   struct ts_filter **list);
147893 +
147894 +#endif
147895 --- /dev/null
147896 +++ b/include/linux/ts_filter_linear.h
147897 @@ -0,0 +1,64 @@
147898 +#ifndef __TS_FILTER_LINEAR_H__
147899 +#define __TS_FILTER_LINEAR_H__
147900 +
147901 +#include <linux/ts_filter.h>
147902 +#include <linux/kobject.h>
147903 +
147904 +/*
147905 + * touchscreen linear filter.
147906 + *
147907 + * Copyright (C) 2008 by Openmoko, Inc.
147908 + * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
147909 + *
147910 + */
147911 +
147912 +#define TS_FILTER_LINEAR_NCONSTANTS 7
147913 +
147914 +/* sysfs */
147915 +
147916 +struct ts_filter_linear;
147917 +
147918 +struct const_obj {
147919 +       struct ts_filter_linear *tsfl;
147920 +       struct kobject kobj;
147921 +};
147922 +
147923 +#define to_const_obj(x) container_of(x, struct const_obj, kobj)
147924 +
147925 +struct const_attribute {
147926 +       struct attribute attr;
147927 +       ssize_t (*show)(struct const_obj *const, struct const_attribute *attr,
147928 +                       char *buf);
147929 +       ssize_t (*store)(struct const_obj *const, struct const_attribute *attr,
147930 +                        const char *buf, size_t count);
147931 +};
147932 +
147933 +#define to_const_attr(x) container_of(x, struct const_attribute, attr)
147934 +
147935 +/* filter configuration */
147936 +
147937 +struct ts_filter_linear_configuration {
147938 +       int constants[TS_FILTER_LINEAR_NCONSTANTS];
147939 +       int coord0;
147940 +       int coord1;
147941 +};
147942 +
147943 +/* the filter */
147944 +
147945 +struct ts_filter_linear {
147946 +       struct ts_filter tsf;
147947 +       struct ts_filter_linear_configuration *config;
147948 +
147949 +       int constants[TS_FILTER_LINEAR_NCONSTANTS];
147950 +
147951 +       /* sysfs */
147952 +       struct const_obj c_obj;
147953 +       struct kobj_type const_ktype;
147954 +       struct const_attribute kattrs[TS_FILTER_LINEAR_NCONSTANTS];
147955 +       struct attribute *attrs[TS_FILTER_LINEAR_NCONSTANTS + 1];
147956 +       char attr_names[TS_FILTER_LINEAR_NCONSTANTS][2];
147957 +};
147958 +
147959 +extern struct ts_filter_api ts_filter_linear_api;
147960 +
147961 +#endif
147962 --- /dev/null
147963 +++ b/include/linux/ts_filter_mean.h
147964 @@ -0,0 +1,34 @@
147965 +#ifndef __TS_FILTER_MEAN_H__
147966 +#define __TS_FILTER_MEAN_H__
147967 +
147968 +#include <linux/ts_filter.h>
147969 +
147970 +/*
147971 + * touchscreen filter
147972 + *
147973 + * mean
147974 + *
147975 + * (c) 2008 Andy Green <andy@openmoko.com>
147976 + */
147977 +
147978 +struct ts_filter_mean_configuration {
147979 +       int bits_filter_length;
147980 +       int averaging_threshold;
147981 +
147982 +       int extent;
147983 +};
147984 +
147985 +struct ts_filter_mean {
147986 +       struct ts_filter tsf;
147987 +       struct ts_filter_mean_configuration *config;
147988 +
147989 +       int reported[MAX_TS_FILTER_COORDS];
147990 +       int lowpass[MAX_TS_FILTER_COORDS];
147991 +       int *fifo[MAX_TS_FILTER_COORDS];
147992 +       int fhead[MAX_TS_FILTER_COORDS];
147993 +       int ftail[MAX_TS_FILTER_COORDS];
147994 +};
147995 +
147996 +extern struct ts_filter_api ts_filter_mean_api;
147997 +
147998 +#endif
147999 --- /dev/null
148000 +++ b/include/linux/ts_filter_median.h
148001 @@ -0,0 +1,36 @@
148002 +#ifndef __TS_FILTER_MEDIAN_H__
148003 +#define __TS_FILTER_MEDIAN_H__
148004 +
148005 +#include <linux/ts_filter.h>
148006 +
148007 +/*
148008 + * touchscreen filter
148009 + *
148010 + * median
148011 + *
148012 + * (c) 2008 Andy Green <andy@openmoko.com>
148013 + */
148014 +
148015 +struct ts_filter_median_configuration {
148016 +       int extent;
148017 +       int midpoint;
148018 +       int decimation_threshold;
148019 +       int decimation_above;
148020 +       int decimation_below;
148021 +};
148022 +
148023 +struct ts_filter_median {
148024 +       struct ts_filter tsf;
148025 +       struct ts_filter_median_configuration *config;
148026 +
148027 +       int decimation_count;
148028 +       int last_issued[MAX_TS_FILTER_COORDS];
148029 +       int valid; /* how many samples in the sort buffer are valid */
148030 +       int *sort[MAX_TS_FILTER_COORDS]; /* samples taken for median */
148031 +       int *fifo[MAX_TS_FILTER_COORDS]; /* samples taken for median */
148032 +       int pos; /* where we are in the fifo sample memory */
148033 +};
148034 +
148035 +extern struct ts_filter_api ts_filter_median_api;
148036 +
148037 +#endif
148038 --- a/include/linux/vt.h
148039 +++ b/include/linux/vt.h
148040 @@ -18,8 +18,19 @@ extern int unregister_vt_notifier(struct
148041   * resizing).
148042   */
148043  #define MIN_NR_CONSOLES 1       /* must be at least 1 */
148044 +#if (CONFIG_NR_TTY_DEVICES < 4)
148045 +/* Lower Limit */
148046 +#define MAX_NR_CONSOLES        4       /* serial lines start at 64 */
148047 +#define MAX_NR_USER_CONSOLES 4 /* must be root to allocate above this */
148048 +#elif (CONFIG_NR_TTY_DEVICES > 63)
148049 +/* Upper Limit */
148050  #define MAX_NR_CONSOLES        63      /* serial lines start at 64 */
148051  #define MAX_NR_USER_CONSOLES 63        /* must be root to allocate above this */
148052 +#else
148053 +/* They chose a sensible number */
148054 +#define MAX_NR_CONSOLES CONFIG_NR_TTY_DEVICES
148055 +#define MAX_NR_USER_CONSOLES CONFIG_NR_TTY_DEVICES
148056 +#endif
148057                 /* Note: the ioctl VT_GETSTATE does not work for
148058                    consoles 16 and higher (since it returns a short) */
148059
148060 --- a/include/sound/soc-dapm.h
148061 +++ b/include/sound/soc-dapm.h
148062 @@ -244,6 +244,13 @@ int snd_soc_dapm_nc_pin(struct snd_soc_c
148063  int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, char *pin);
148064  int snd_soc_dapm_sync(struct snd_soc_codec *codec);
148065
148066 +/* dapm audio endpoint control */
148067 +int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec,
148068 +       char *pin, int status);
148069 +int snd_soc_dapm_get_endpoint(struct snd_soc_codec *codec,
148070 +       char *pin);
148071 +int snd_soc_dapm_sync_endpoints(struct snd_soc_codec *codec);
148072 +
148073  /* dapm widget types */
148074  enum snd_soc_dapm_type {
148075         snd_soc_dapm_input = 0,         /* input pin */
148076 --- a/init/Kconfig
148077 +++ b/init/Kconfig
148078 @@ -732,6 +732,15 @@ config AIO
148079            by some high performance threaded applications. Disabling
148080            this option saves about 7k.
148081
148082 +config ASHMEM
148083 +       bool "Enable Android's Shared Memory Subsystem"
148084 +       default n
148085 +       depends on SHMEM || TINY_SHMEM
148086 +       help
148087 +         The ashmem subsystem is a new shared memory allocator, similar to
148088 +         POSIX SHM but with different behavior and sporting a simpler
148089 +         file-based API.
148090 +
148091  config VM_EVENT_COUNTERS
148092         default y
148093         bool "Enable VM event counters for /proc/vmstat" if EMBEDDED
148094 --- a/kernel/irq/chip.c
148095 +++ b/kernel/irq/chip.c
148096 @@ -380,6 +380,7 @@ handle_level_irq(unsigned int irq, struc
148097  out_unlock:
148098         spin_unlock(&desc->lock);
148099  }
148100 +EXPORT_SYMBOL(handle_level_irq);
148101
148102  /**
148103   *     handle_fasteoi_irq - irq handler for transparent controllers
148104 @@ -583,6 +584,7 @@ __set_irq_handler(unsigned int irq, irq_
148105         }
148106         spin_unlock_irqrestore(&desc->lock, flags);
148107  }
148108 +EXPORT_SYMBOL(__set_irq_handler);
148109
148110  void
148111  set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
148112 --- a/kernel/power/main.c
148113 +++ b/kernel/power/main.c
148114 @@ -132,6 +132,9 @@ static inline int suspend_test(int level
148115
148116  #endif /* CONFIG_PM_SLEEP */
148117
148118 +int global_inside_suspend;
148119 +EXPORT_SYMBOL(global_inside_suspend);
148120 +
148121  #ifdef CONFIG_SUSPEND
148122
148123  #ifdef CONFIG_PM_TEST_SUSPEND
148124 @@ -322,6 +325,8 @@ int suspend_devices_and_enter(suspend_st
148125         if (!suspend_ops)
148126                 return -ENOSYS;
148127
148128 +       global_inside_suspend = 1;
148129 +
148130         if (suspend_ops->begin) {
148131                 error = suspend_ops->begin(state);
148132                 if (error)
148133 @@ -365,6 +370,8 @@ int suspend_devices_and_enter(suspend_st
148134   Close:
148135         if (suspend_ops->end)
148136                 suspend_ops->end();
148137 +       global_inside_suspend = 0;
148138 +
148139         return error;
148140
148141   Recover_platform:
148142 @@ -427,6 +434,8 @@ static int enter_state(suspend_state_t s
148143                 return -EBUSY;
148144
148145         printk(KERN_INFO "PM: Syncing filesystems ... ");
148146 +       global_inside_suspend = 1;
148147 +
148148         sys_sync();
148149         printk("done.\n");
148150
148151 --- a/kernel/printk.c
148152 +++ b/kernel/printk.c
148153 @@ -32,8 +32,11 @@
148154  #include <linux/security.h>
148155  #include <linux/bootmem.h>
148156  #include <linux/syscalls.h>
148157 +#include <linux/jiffies.h>
148158 +#include <linux/suspend.h>
148159
148160  #include <asm/uaccess.h>
148161 +#include <asm/plat-s3c24xx/neo1973.h>
148162
148163  /*
148164   * Architectures can override it:
148165 @@ -67,6 +70,12 @@ int console_printk[4] = {
148166  int oops_in_progress;
148167  EXPORT_SYMBOL(oops_in_progress);
148168
148169 +void (*printk_emergency_debug_spew_init)(void) = NULL;
148170 +EXPORT_SYMBOL(printk_emergency_debug_spew_init);
148171 +
148172 +void (*printk_emergency_debug_spew_send_string)(const char *) = NULL;
148173 +EXPORT_SYMBOL(printk_emergency_debug_spew_send_string);
148174 +
148175  /*
148176   * console_sem protects the console_drivers list, and also
148177   * provides serialisation for access to the entire console
148178 @@ -667,8 +676,39 @@ asmlinkage int vprintk(const char *fmt,
148179         /* Emit the output into the temporary buffer */
148180         printed_len += vscnprintf(printk_buf + printed_len,
148181                                   sizeof(printk_buf) - printed_len, fmt, args);
148182 -
148183 -
148184 +#ifdef CONFIG_MACH_NEO1973_GTA02
148185 +       /* if you're debugging resume, the normal methods can change resume
148186 +        * ordering behaviours because their debugging output is synchronous
148187 +        * (ie, CONFIG_DEBUG_LL).  If your problem is an OOPS, this code
148188 +        * will not affect the speed and duration and ordering of resume
148189 +        * actions, but will give you a chance to read the full undumped
148190 +        * syslog AND the OOPS data when it happens
148191 +        *
148192 +        * if you support it, your debug device init can override the exported
148193 +        * emergency_debug_spew_init and emergency_debug_spew_send_string to
148194 +        * usually force polling or bitbanging on your debug console device
148195 +        */
148196 +       if (oops_in_progress && global_inside_suspend &&
148197 +           printk_emergency_debug_spew_init &&
148198 +           printk_emergency_debug_spew_send_string) {
148199 +               unsigned long cur_index;
148200 +               char ch[2];
148201 +
148202 +               if (global_inside_suspend == 1) {
148203 +                       (printk_emergency_debug_spew_init)();
148204 +
148205 +                       ch[1] = '\0';
148206 +                       cur_index = con_start;
148207 +                       while (cur_index != log_end) {
148208 +                               ch[0] = LOG_BUF(cur_index);
148209 +                               (printk_emergency_debug_spew_send_string)(ch);
148210 +                               cur_index++;
148211 +                       }
148212 +                       global_inside_suspend++; /* only once */
148213 +               }
148214 +               (printk_emergency_debug_spew_send_string)(printk_buf);
148215 +       }
148216 +#endif
148217         /*
148218          * Copy the output into log_buf.  If the caller didn't provide
148219          * appropriate log level tags, we insert them here
148220 --- a/kernel/timer.c
148221 +++ b/kernel/timer.c
148222 @@ -813,7 +813,11 @@ static int cascade(struct tvec_base *bas
148223          * don't have to detach them individually.
148224          */
148225         list_for_each_entry_safe(timer, tmp, &tv_list, entry) {
148226 -               BUG_ON(tbase_get_base(timer->base) != base);
148227 +               if (tbase_get_base(timer->base) != base) {
148228 +                       printk(KERN_ERR "cascade: timer %p: tbase_get_base(timer->base) 0x%x "
148229 +                               "!= base 0x%x\n", timer, tbase_get_base(timer->base), base);
148230 +                       BUG_ON(1);
148231 +               }
148232                 internal_add_timer(base, timer);
148233         }
148234
148235 --- a/MAINTAINERS
148236 +++ b/MAINTAINERS
148237 @@ -1705,6 +1705,20 @@ FILE LOCKING (flock() and fcntl()/lockf(
148238  P:     Matthew Wilcox
148239  M:     matthew@wil.cx
148240  L:     linux-fsdevel@vger.kernel.org
148241 +
148242 +FIC/OPENMOKO NEO1973 GSM PHONE
148243 +P:     Harald Welte
148244 +M:     laforge@openmoko.org
148245 +L:     openmoko-kernel@lists.openmoko.org
148246 +W:     http://wiki.openmoko.org/wiki/Kernel
148247 +W:     http://wiki.openmoko.org/wiki/Neo1973
148248 +S:     Maintained
148249 +
148250 +FRAMEBUFFER LAYER
148251 +P:     Antonino Daplas
148252 +M:     adaplas@gmail.com
148253 +L:     linux-fbdev-devel@lists.sourceforge.net (moderated for non-subscribers)
148254 +W:     http://linux-fbdev.sourceforge.net/
148255  S:     Maintained
148256
148257  FILESYSTEMS (VFS and infrastructure)
148258 --- /dev/null
148259 +++ b/makerecovery
148260 @@ -0,0 +1,17 @@
148261 +#!/bin/sh
148262 +#
148263 +# make 6MB recovery image from two moredrivers type kernels
148264 +# placed at start and at +4MBytes
148265 +
148266 +if [ -z "$1" ] ; then
148267 + echo "Usage: $0 uImage-moredrivers-..."
148268 + exit 1
148269 +fi
148270 +cat $1 > recovery-$1
148271 +SIZE=`ls -l $1 | tr -s ' ' ' ' | cut -d' ' -f5`
148272 +SPACE=$(( 4 * 1024 * 1024 - $SIZE ))
148273 +dd if=/dev/zero of=_spacer bs=1 count=$SPACE
148274 +cat _spacer >> recovery-$1
148275 +rm -f _spacer
148276 +cat $1 >> recovery-$1
148277 +
148278 --- /dev/null
148279 +++ b/mm/ashmem.c
148280 @@ -0,0 +1,657 @@
148281 +/* drivers/android/ashmem.c
148282 +**
148283 +** Android / Anonymous Shared Memory Subsystem, ashmem
148284 +**
148285 +** Copyright (C) 2008 Google, Inc.
148286 +**
148287 +** Robert Love <rlove@google.com>
148288 +**
148289 +** This software is licensed under the terms of the GNU General Public
148290 +** License version 2, as published by the Free Software Foundation, and
148291 +** may be copied, distributed, and modified under those terms.
148292 +**
148293 +** This program is distributed in the hope that it will be useful,
148294 +** but WITHOUT ANY WARRANTY; without even the implied warranty of
148295 +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
148296 +** GNU General Public License for more details.
148297 +*/
148298 +
148299 +#include <linux/module.h>
148300 +#include <linux/file.h>
148301 +#include <linux/fs.h>
148302 +#include <linux/miscdevice.h>
148303 +#include <linux/security.h>
148304 +#include <linux/mm.h>
148305 +#include <linux/mman.h>
148306 +#include <linux/uaccess.h>
148307 +#include <linux/personality.h>
148308 +#include <linux/bitops.h>
148309 +#include <linux/mutex.h>
148310 +#include <linux/shmem_fs.h>
148311 +#include <linux/ashmem.h>
148312 +
148313 +/*
148314 + * ashmem_area - android shared memory area
148315 + * Lifecycle: From our parent file's open() until its release()
148316 + * Locking: Protected by `ashmem_mutex'
148317 + * Big Note: Mappings do NOT pin this structure; it dies on close()
148318 + */
148319 +struct ashmem_area {
148320 +       char name[ASHMEM_NAME_LEN];     /* optional name for /proc/pid/maps */
148321 +       struct list_head unpinned_list; /* list of all ashmem areas */
148322 +       struct file *file;              /* the shmem-based backing file */
148323 +       size_t size;                    /* size of the mapping, in bytes */
148324 +       unsigned long prot_mask;        /* allowed prot bits, as vm_flags */
148325 +};
148326 +
148327 +/*
148328 + * ashmem_range - represents an interval of unpinned (evictable) pages
148329 + * Lifecycle: From unpin to pin
148330 + * Locking: Protected by `ashmem_mutex'
148331 + */
148332 +struct ashmem_range {
148333 +       struct list_head lru;           /* entry in LRU list */
148334 +       struct list_head unpinned;      /* entry in its area's unpinned list */
148335 +       struct ashmem_area *asma;       /* associated area */
148336 +       size_t pgstart;                 /* starting page, inclusive */
148337 +       size_t pgend;                   /* ending page, inclusive */
148338 +       unsigned int purged;            /* ASHMEM_NOT or ASHMEM_WAS_PURGED */
148339 +};
148340 +
148341 +/* LRU list of unpinned pages, protected by ashmem_mutex */
148342 +static LIST_HEAD(ashmem_lru_list);
148343 +
148344 +/* Count of pages on our LRU list, protected by ashmem_mutex */
148345 +static unsigned long lru_count;
148346 +
148347 +/*
148348 + * ashmem_mutex - protects the list of and each individual ashmem_area
148349 + *
148350 + * Lock Ordering: ashmex_mutex -> i_mutex -> i_alloc_sem
148351 + */
148352 +static DEFINE_MUTEX(ashmem_mutex);
148353 +
148354 +static struct kmem_cache *ashmem_area_cachep __read_mostly;
148355 +static struct kmem_cache *ashmem_range_cachep __read_mostly;
148356 +
148357 +#define range_size(range) \
148358 +  ((range)->pgend - (range)->pgstart + 1)
148359 +
148360 +#define range_on_lru(range) \
148361 +  ((range)->purged == ASHMEM_NOT_PURGED)
148362 +
148363 +#define page_range_subsumes_range(range, start, end) \
148364 +  (((range)->pgstart >= (start)) && ((range)->pgend <= (end)))
148365 +
148366 +#define page_range_subsumed_by_range(range, start, end) \
148367 +  (((range)->pgstart <= (start)) && ((range)->pgend >= (end)))
148368 +
148369 +#define page_in_range(range, page) \
148370 + (((range)->pgstart <= (page)) && ((range)->pgend >= (page)))
148371 +
148372 +#define page_range_in_range(range, start, end) \
148373 +  (page_in_range(range, start) || page_in_range(range, end) || \
148374 +   page_range_subsumes_range(range, start, end))
148375 +
148376 +#define range_before_page(range, page) \
148377 +  ((range)->pgend < (page))
148378 +
148379 +#define PROT_MASK              (PROT_EXEC | PROT_READ | PROT_WRITE)
148380 +
148381 +static inline void lru_add(struct ashmem_range *range)
148382 +{
148383 +       list_add_tail(&range->lru, &ashmem_lru_list);
148384 +       lru_count += range_size(range);
148385 +}
148386 +
148387 +static inline void lru_del(struct ashmem_range *range)
148388 +{
148389 +       list_del(&range->lru);
148390 +       lru_count -= range_size(range);
148391 +}
148392 +
148393 +/*
148394 + * range_alloc - allocate and initialize a new ashmem_range structure
148395 + *
148396 + * 'asma' - associated ashmem_area
148397 + * 'prev_range' - the previous ashmem_range in the sorted asma->unpinned list
148398 + * 'purged' - initial purge value (ASMEM_NOT_PURGED or ASHMEM_WAS_PURGED)
148399 + * 'start' - starting page, inclusive
148400 + * 'end' - ending page, inclusive
148401 + *
148402 + * Caller must hold ashmem_mutex.
148403 + */
148404 +static int range_alloc(struct ashmem_area *asma,
148405 +                      struct ashmem_range *prev_range, unsigned int purged,
148406 +                      size_t start, size_t end)
148407 +{
148408 +       struct ashmem_range *range;
148409 +
148410 +       range = kmem_cache_zalloc(ashmem_range_cachep, GFP_KERNEL);
148411 +       if (unlikely(!range))
148412 +               return -ENOMEM;
148413 +
148414 +       range->asma = asma;
148415 +       range->pgstart = start;
148416 +       range->pgend = end;
148417 +       range->purged = purged;
148418 +
148419 +       list_add_tail(&range->unpinned, &prev_range->unpinned);
148420 +
148421 +       if (range_on_lru(range))
148422 +               lru_add(range);
148423 +
148424 +       return 0;
148425 +}
148426 +
148427 +static void range_del(struct ashmem_range *range)
148428 +{
148429 +       list_del(&range->unpinned);
148430 +       if (range_on_lru(range))
148431 +               lru_del(range);
148432 +       kmem_cache_free(ashmem_range_cachep, range);
148433 +}
148434 +
148435 +/*
148436 + * range_shrink - shrinks a range
148437 + *
148438 + * Caller must hold ashmem_mutex.
148439 + */
148440 +static inline void range_shrink(struct ashmem_range *range,
148441 +                               size_t start, size_t end)
148442 +{
148443 +       size_t pre = range_size(range);
148444 +
148445 +       range->pgstart = start;
148446 +       range->pgend = end;
148447 +
148448 +       if (range_on_lru(range))
148449 +               lru_count -= pre - range_size(range);
148450 +}
148451 +
148452 +static int ashmem_open(struct inode *inode, struct file *file)
148453 +{
148454 +       struct ashmem_area *asma;
148455 +       int ret;
148456 +
148457 +       ret = nonseekable_open(inode, file);
148458 +       if (unlikely(ret))
148459 +               return ret;
148460 +
148461 +       asma = kmem_cache_zalloc(ashmem_area_cachep, GFP_KERNEL);
148462 +       if (unlikely(!asma))
148463 +               return -ENOMEM;
148464 +
148465 +       INIT_LIST_HEAD(&asma->unpinned_list);
148466 +       asma->prot_mask = PROT_MASK;
148467 +       file->private_data = asma;
148468 +
148469 +       return 0;
148470 +}
148471 +
148472 +static int ashmem_release(struct inode *ignored, struct file *file)
148473 +{
148474 +       struct ashmem_area *asma = file->private_data;
148475 +       struct ashmem_range *range, *next;
148476 +
148477 +       mutex_lock(&ashmem_mutex);
148478 +       list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned)
148479 +               range_del(range);
148480 +       mutex_unlock(&ashmem_mutex);
148481 +
148482 +       if (asma->file)
148483 +               fput(asma->file);
148484 +       kmem_cache_free(ashmem_area_cachep, asma);
148485 +
148486 +       return 0;
148487 +}
148488 +
148489 +static int ashmem_mmap(struct file *file, struct vm_area_struct *vma)
148490 +{
148491 +       struct ashmem_area *asma = file->private_data;
148492 +       int ret = 0;
148493 +
148494 +       mutex_lock(&ashmem_mutex);
148495 +
148496 +       /* user needs to SET_SIZE before mapping */
148497 +       if (unlikely(!asma->size)) {
148498 +               ret = -EINVAL;
148499 +               goto out;
148500 +       }
148501 +
148502 +       /* requested protection bits must match our allowed protection mask */
148503 +       if (unlikely((vma->vm_flags & ~asma->prot_mask) & PROT_MASK)) {
148504 +               ret = -EPERM;
148505 +               goto out;
148506 +       }
148507 +
148508 +       if (!asma->file) {
148509 +               char *name = ASHMEM_NAME_DEF;
148510 +               struct file *vmfile;
148511 +
148512 +               if (asma->name[0] != '\0')
148513 +                       name = asma->name;
148514 +
148515 +               /* ... and allocate the backing shmem file */
148516 +               vmfile = shmem_file_setup(name, asma->size, vma->vm_flags);
148517 +               if (unlikely(IS_ERR(vmfile))) {
148518 +                       ret = PTR_ERR(vmfile);
148519 +                       goto out;
148520 +               }
148521 +               asma->file = vmfile;
148522 +       }
148523 +       get_file(asma->file);
148524 +
148525 +       shmem_set_file(vma, asma->file);
148526 +       vma->vm_flags |= VM_CAN_NONLINEAR;
148527 +
148528 +out:
148529 +       mutex_unlock(&ashmem_mutex);
148530 +       return ret;
148531 +}
148532 +
148533 +/*
148534 + * ashmem_shrink - our cache shrinker, called from mm/vmscan.c :: shrink_slab
148535 + *
148536 + * 'nr_to_scan' is the number of objects (pages) to prune, or 0 to query how
148537 + * many objects (pages) we have in total.
148538 + *
148539 + * 'gfp_mask' is the mask of the allocation that got us into this mess.
148540 + *
148541 + * Return value is the number of objects (pages) remaining, or -1 if we cannot
148542 + * proceed without risk of deadlock (due to gfp_mask).
148543 + *
148544 + * We approximate LRU via least-recently-unpinned, jettisoning unpinned partial
148545 + * chunks of ashmem regions LRU-wise one-at-a-time until we hit 'nr_to_scan'
148546 + * pages freed.
148547 + */
148548 +static int ashmem_shrink(int nr_to_scan, gfp_t gfp_mask)
148549 +{
148550 +       struct ashmem_range *range, *next;
148551 +
148552 +       /* We might recurse into filesystem code, so bail out if necessary */
148553 +       if (nr_to_scan && !(gfp_mask & __GFP_FS))
148554 +               return -1;
148555 +       if (!nr_to_scan)
148556 +               return lru_count;
148557 +
148558 +       mutex_lock(&ashmem_mutex);
148559 +       list_for_each_entry_safe(range, next, &ashmem_lru_list, lru) {
148560 +               struct inode *inode = range->asma->file->f_dentry->d_inode;
148561 +               loff_t start = range->pgstart * PAGE_SIZE;
148562 +               loff_t end = (range->pgend + 1) * PAGE_SIZE - 1;
148563 +
148564 +               vmtruncate_range(inode, start, end);
148565 +               range->purged = ASHMEM_WAS_PURGED;
148566 +               lru_del(range);
148567 +
148568 +               nr_to_scan -= range_size(range);
148569 +               if (nr_to_scan <= 0)
148570 +                       break;
148571 +       }
148572 +       mutex_unlock(&ashmem_mutex);
148573 +
148574 +       return lru_count;
148575 +}
148576 +
148577 +static struct shrinker ashmem_shrinker = {
148578 +       .shrink = ashmem_shrink,
148579 +       .seeks = DEFAULT_SEEKS * 4,
148580 +};
148581 +
148582 +static int set_prot_mask(struct ashmem_area *asma, unsigned long prot)
148583 +{
148584 +       int ret = 0;
148585 +
148586 +       mutex_lock(&ashmem_mutex);
148587 +
148588 +       /* the user can only remove, not add, protection bits */
148589 +       if (unlikely((asma->prot_mask & prot) != prot)) {
148590 +               ret = -EINVAL;
148591 +               goto out;
148592 +       }
148593 +
148594 +       /* does the application expect PROT_READ to imply PROT_EXEC? */
148595 +       if ((prot & PROT_READ) && (current->personality & READ_IMPLIES_EXEC))
148596 +               prot |= PROT_EXEC;
148597 +
148598 +       asma->prot_mask = prot;
148599 +
148600 +out:
148601 +       mutex_unlock(&ashmem_mutex);
148602 +       return ret;
148603 +}
148604 +
148605 +static int set_name(struct ashmem_area *asma, void __user *name)
148606 +{
148607 +       int ret = 0;
148608 +
148609 +       mutex_lock(&ashmem_mutex);
148610 +
148611 +       /* cannot change an existing mapping's name */
148612 +       if (unlikely(asma->file)) {
148613 +               ret = -EINVAL;
148614 +               goto out;
148615 +       }
148616 +
148617 +       if (unlikely(copy_from_user(asma->name, name, ASHMEM_NAME_LEN)))
148618 +               ret = -EFAULT;
148619 +       asma->name[ASHMEM_NAME_LEN-1] = '\0';
148620 +
148621 +out:
148622 +       mutex_unlock(&ashmem_mutex);
148623 +
148624 +       return ret;
148625 +}
148626 +
148627 +static int get_name(struct ashmem_area *asma, void __user *name)
148628 +{
148629 +       int ret = 0;
148630 +
148631 +       mutex_lock(&ashmem_mutex);
148632 +       if (asma->name[0] != '\0') {
148633 +               size_t len;
148634 +
148635 +               /*
148636 +                * Copying only `len', instead of ASHMEM_NAME_LEN, bytes
148637 +                * prevents us from revealing one user's stack to another.
148638 +                */
148639 +               len = strlen(asma->name) + 1;
148640 +               if (unlikely(copy_to_user(name, asma->name, len)))
148641 +                       ret = -EFAULT;
148642 +       } else {
148643 +               if (unlikely(copy_to_user(name, ASHMEM_NAME_DEF,
148644 +                                         sizeof(ASHMEM_NAME_DEF))))
148645 +                       ret = -EFAULT;
148646 +       }
148647 +       mutex_unlock(&ashmem_mutex);
148648 +
148649 +       return ret;
148650 +}
148651 +
148652 +/*
148653 + * ashmem_pin - pin the given ashmem region, returning whether it was
148654 + * previously purged (ASHMEM_WAS_PURGED) or not (ASHMEM_NOT_PURGED).
148655 + *
148656 + * Caller must hold ashmem_mutex.
148657 + */
148658 +static int ashmem_pin(struct ashmem_area *asma, size_t pgstart, size_t pgend)
148659 +{
148660 +       struct ashmem_range *range, *next;
148661 +       int ret = ASHMEM_NOT_PURGED;
148662 +
148663 +       list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) {
148664 +               /* moved past last applicable page; we can short circuit */
148665 +               if (range_before_page(range, pgstart))
148666 +                       break;
148667 +
148668 +               /*
148669 +                * The user can ask us to pin pages that span multiple ranges,
148670 +                * or to pin pages that aren't even unpinned, so this is messy.
148671 +                *
148672 +                * Four cases:
148673 +                * 1. The requested range subsumes an existing range, so we
148674 +                *    just remove the entire matching range.
148675 +                * 2. The requested range overlaps the start of an existing
148676 +                *    range, so we just update that range.
148677 +                * 3. The requested range overlaps the end of an existing
148678 +                *    range, so we just update that range.
148679 +                * 4. The requested range punches a hole in an existing range,
148680 +                *    so we have to update one side of the range and then
148681 +                *    create a new range for the other side.
148682 +                */
148683 +               if (page_range_in_range(range, pgstart, pgend)) {
148684 +                       ret |= range->purged;
148685 +
148686 +                       /* Case #1: Easy. Just nuke the whole thing. */
148687 +                       if (page_range_subsumes_range(range, pgstart, pgend)) {
148688 +                               range_del(range);
148689 +                               continue;
148690 +                       }
148691 +
148692 +                       /* Case #2: We overlap from the start, so adjust it */
148693 +                       if (range->pgstart >= pgstart) {
148694 +                               range_shrink(range, pgend + 1, range->pgend);
148695 +                               continue;
148696 +                       }
148697 +
148698 +                       /* Case #3: We overlap from the rear, so adjust it */
148699 +                       if (range->pgend <= pgend) {
148700 +                               range_shrink(range, range->pgstart, pgstart-1);
148701 +                               continue;
148702 +                       }
148703 +
148704 +                       /*
148705 +                        * Case #4: We eat a chunk out of the middle. A bit
148706 +                        * more complicated, we allocate a new range for the
148707 +                        * second half and adjust the first chunk's endpoint.
148708 +                        */
148709 +                       range_alloc(asma, range, range->purged,
148710 +                                   pgend + 1, range->pgend);
148711 +                       range_shrink(range, range->pgstart, pgstart - 1);
148712 +                       break;
148713 +               }
148714 +       }
148715 +
148716 +       return ret;
148717 +}
148718 +
148719 +/*
148720 + * ashmem_unpin - unpin the given range of pages. Returns zero on success.
148721 + *
148722 + * Caller must hold ashmem_mutex.
148723 + */
148724 +static int ashmem_unpin(struct ashmem_area *asma, size_t pgstart, size_t pgend)
148725 +{
148726 +       struct ashmem_range *range, *next;
148727 +       unsigned int purged = ASHMEM_NOT_PURGED;
148728 +
148729 +restart:
148730 +       list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) {
148731 +               /* short circuit: this is our insertion point */
148732 +               if (range_before_page(range, pgstart))
148733 +                       break;
148734 +
148735 +               /*
148736 +                * The user can ask us to unpin pages that are already entirely
148737 +                * or partially pinned. We handle those two cases here.
148738 +                */
148739 +               if (page_range_subsumed_by_range(range, pgstart, pgend))
148740 +                       return 0;
148741 +               if (page_range_in_range(range, pgstart, pgend)) {
148742 +                       pgstart = min_t(size_t, range->pgstart, pgstart),
148743 +                       pgend = max_t(size_t, range->pgend, pgend);
148744 +                       purged |= range->purged;
148745 +                       range_del(range);
148746 +                       goto restart;
148747 +               }
148748 +       }
148749 +
148750 +       return range_alloc(asma, range, purged, pgstart, pgend);
148751 +}
148752 +
148753 +/*
148754 + * ashmem_get_pin_status - Returns ASHMEM_IS_UNPINNED if _any_ pages in the
148755 + * given interval are unpinned and ASHMEM_IS_PINNED otherwise.
148756 + *
148757 + * Caller must hold ashmem_mutex.
148758 + */
148759 +static int ashmem_get_pin_status(struct ashmem_area *asma, size_t pgstart,
148760 +                                size_t pgend)
148761 +{
148762 +       struct ashmem_range *range;
148763 +       int ret = ASHMEM_IS_PINNED;
148764 +
148765 +       list_for_each_entry(range, &asma->unpinned_list, unpinned) {
148766 +               if (range_before_page(range, pgstart))
148767 +                       break;
148768 +               if (page_range_in_range(range, pgstart, pgend)) {
148769 +                       ret = ASHMEM_IS_UNPINNED;
148770 +                       break;
148771 +               }
148772 +       }
148773 +
148774 +       return ret;
148775 +}
148776 +
148777 +static int ashmem_pin_unpin(struct ashmem_area *asma, unsigned long cmd,
148778 +                           void __user *p)
148779 +{
148780 +       struct ashmem_pin pin;
148781 +       size_t pgstart, pgend;
148782 +       int ret = -EINVAL;
148783 +
148784 +       if (unlikely(!asma->file))
148785 +               return -EINVAL;
148786 +
148787 +       if (unlikely(copy_from_user(&pin, p, sizeof(pin))))
148788 +               return -EFAULT;
148789 +
148790 +       /* per custom, you can pass zero for len to mean "everything onward" */
148791 +       if (!pin.len)
148792 +               pin.len = asma->size - pin.offset;
148793 +
148794 +       if (unlikely((pin.offset | pin.len) & ~PAGE_MASK))
148795 +               return -EINVAL;
148796 +
148797 +       if (unlikely(((__u32) -1) - pin.offset < pin.len))
148798 +               return -EINVAL;
148799 +
148800 +       if (unlikely(asma->size < pin.offset + pin.len))
148801 +               return -EINVAL;
148802 +
148803 +       pgstart = pin.offset / PAGE_SIZE;
148804 +       pgend = pgstart + (pin.len / PAGE_SIZE) - 1;
148805 +
148806 +       mutex_lock(&ashmem_mutex);
148807 +
148808 +       switch (cmd) {
148809 +       case ASHMEM_PIN:
148810 +               ret = ashmem_pin(asma, pgstart, pgend);
148811 +               break;
148812 +       case ASHMEM_UNPIN:
148813 +               ret = ashmem_unpin(asma, pgstart, pgend);
148814 +               break;
148815 +       case ASHMEM_GET_PIN_STATUS:
148816 +               ret = ashmem_get_pin_status(asma, pgstart, pgend);
148817 +               break;
148818 +       }
148819 +
148820 +       mutex_unlock(&ashmem_mutex);
148821 +
148822 +       return ret;
148823 +}
148824 +
148825 +static long ashmem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
148826 +{
148827 +       struct ashmem_area *asma = file->private_data;
148828 +       long ret = -ENOTTY;
148829 +
148830 +       switch (cmd) {
148831 +       case ASHMEM_SET_NAME:
148832 +               ret = set_name(asma, (void __user *) arg);
148833 +               break;
148834 +       case ASHMEM_GET_NAME:
148835 +               ret = get_name(asma, (void __user *) arg);
148836 +               break;
148837 +       case ASHMEM_SET_SIZE:
148838 +               ret = -EINVAL;
148839 +               if (!asma->file && !(arg & ~PAGE_MASK)) {
148840 +                       ret = 0;
148841 +                       asma->size = (size_t) arg;
148842 +               }
148843 +               break;
148844 +       case ASHMEM_GET_SIZE:
148845 +               ret = asma->size;
148846 +               break;
148847 +       case ASHMEM_SET_PROT_MASK:
148848 +               ret = set_prot_mask(asma, arg);
148849 +               break;
148850 +       case ASHMEM_GET_PROT_MASK:
148851 +               ret = asma->prot_mask;
148852 +               break;
148853 +       case ASHMEM_PIN:
148854 +       case ASHMEM_UNPIN:
148855 +       case ASHMEM_GET_PIN_STATUS:
148856 +               ret = ashmem_pin_unpin(asma, cmd, (void __user *) arg);
148857 +               break;
148858 +       case ASHMEM_PURGE_ALL_CACHES:
148859 +               ret = -EPERM;
148860 +               if (capable(CAP_SYS_ADMIN)) {
148861 +                       ret = ashmem_shrink(0, GFP_KERNEL);
148862 +                       ashmem_shrink(ret, GFP_KERNEL);
148863 +               }
148864 +               break;
148865 +       }
148866 +
148867 +       return ret;
148868 +}
148869 +
148870 +static struct file_operations ashmem_fops = {
148871 +       .owner = THIS_MODULE,
148872 +       .open = ashmem_open,
148873 +       .release = ashmem_release,
148874 +       .mmap = ashmem_mmap,
148875 +       .unlocked_ioctl = ashmem_ioctl,
148876 +       .compat_ioctl = ashmem_ioctl,
148877 +};
148878 +
148879 +static struct miscdevice ashmem_misc = {
148880 +       .minor = MISC_DYNAMIC_MINOR,
148881 +       .name = "ashmem",
148882 +       .fops = &ashmem_fops,
148883 +};
148884 +
148885 +static int __init ashmem_init(void)
148886 +{
148887 +       int ret;
148888 +
148889 +       ashmem_area_cachep = kmem_cache_create("ashmem_area_cache",
148890 +                                         sizeof(struct ashmem_area),
148891 +                                         0, 0, NULL);
148892 +       if (unlikely(!ashmem_area_cachep)) {
148893 +               printk(KERN_ERR "ashmem: failed to create slab cache\n");
148894 +               return -ENOMEM;
148895 +       }
148896 +
148897 +       ashmem_range_cachep = kmem_cache_create("ashmem_range_cache",
148898 +                                         sizeof(struct ashmem_range),
148899 +                                         0, 0, NULL);
148900 +       if (unlikely(!ashmem_range_cachep)) {
148901 +               printk(KERN_ERR "ashmem: failed to create slab cache\n");
148902 +               return -ENOMEM;
148903 +       }
148904 +
148905 +       ret = misc_register(&ashmem_misc);
148906 +       if (unlikely(ret)) {
148907 +               printk(KERN_ERR "ashmem: failed to register misc device!\n");
148908 +               return ret;
148909 +       }
148910 +
148911 +       register_shrinker(&ashmem_shrinker);
148912 +
148913 +       printk(KERN_INFO "ashmem: initialized\n");
148914 +
148915 +       return 0;
148916 +}
148917 +
148918 +static void __exit ashmem_exit(void)
148919 +{
148920 +       int ret;
148921 +
148922 +       unregister_shrinker(&ashmem_shrinker);
148923 +
148924 +       ret = misc_deregister(&ashmem_misc);
148925 +       if (unlikely(ret))
148926 +               printk(KERN_ERR "ashmem: failed to unregister misc device!\n");
148927 +
148928 +       kmem_cache_destroy(ashmem_range_cachep);
148929 +       kmem_cache_destroy(ashmem_area_cachep);
148930 +
148931 +       printk(KERN_INFO "ashmem: unloaded\n");
148932 +}
148933 +
148934 +module_init(ashmem_init);
148935 +module_exit(ashmem_exit);
148936 +
148937 +MODULE_LICENSE("GPL");
148938 --- a/mm/Makefile
148939 +++ b/mm/Makefile
148940 @@ -22,6 +22,7 @@ obj-$(CONFIG_NUMA)    += mempolicy.o
148941  obj-$(CONFIG_SPARSEMEM)        += sparse.o
148942  obj-$(CONFIG_SPARSEMEM_VMEMMAP) += sparse-vmemmap.o
148943  obj-$(CONFIG_SHMEM) += shmem.o
148944 +obj-$(CONFIG_ASHMEM) += ashmem.o
148945  obj-$(CONFIG_TMPFS_POSIX_ACL) += shmem_acl.o
148946  obj-$(CONFIG_TINY_SHMEM) += tiny-shmem.o
148947  obj-$(CONFIG_SLOB) += slob.o
148948 --- a/mm/tiny-shmem.c
148949 +++ b/mm/tiny-shmem.c
148950 @@ -97,6 +97,22 @@ put_memory:
148951  }
148952  EXPORT_SYMBOL_GPL(shmem_file_setup);
148953
148954 +void shmem_set_file(struct vm_area_struct *vma, struct file *file)
148955 +{
148956 +       if (vma->vm_file)
148957 +               fput(vma->vm_file);
148958 +       vma->vm_file = file;
148959 +       vma->vm_ops = &generic_file_vm_ops;
148960 +}
148961 +
148962 +void shmem_set_file(struct vm_area_struct *vma, struct file *file)
148963 +{
148964 +       if (vma->vm_file)
148965 +               fput(vma->vm_file);
148966 +       vma->vm_file = file;
148967 +       vma->vm_ops = &generic_file_vm_ops;
148968 +}
148969 +
148970  /**
148971   * shmem_zero_setup - setup a shared anonymous mapping
148972   * @vma: the vma to be mmapped is prepared by do_mmap_pgoff
148973 @@ -110,10 +126,8 @@ int shmem_zero_setup(struct vm_area_stru
148974         if (IS_ERR(file))
148975                 return PTR_ERR(file);
148976
148977 -       if (vma->vm_file)
148978 -               fput(vma->vm_file);
148979 -       vma->vm_file = file;
148980 -       vma->vm_ops = &generic_file_vm_ops;
148981 +       shmem_set_file(vma, file);
148982 +
148983         return 0;
148984  }
148985
148986 --- /dev/null
148987 +++ b/remote_install_sdcard
148988 @@ -0,0 +1,18 @@
148989 +#!/bin/sh
148990 +
148991 +# automatic kernel updater and reboot - Andy Green <andy@openmoko.com>
148992 +
148993 +GTA_DEVICE_IP=192.168.0.202
148994 +
148995 +# you should set up key-based auth on dropbear if you want
148996 +# to play this game.
148997 +#
148998 +# 1) mkdir /home/root/.ssh
148999 +# 2) chown root:root / /home /home/root
149000 +# 3) chmod 700 /home/root /home/root/.ssh
149001 +# 4) copy your id_*.pub into /home/root/.ssh/authorized_keys
149002 +# 5) chmod 600 /home/root/.ssh/*
149003 +
149004 +scp uImage.bin root@$GTA_DEVICE_IP:/boot
149005 +ssh root@$GTA_DEVICE_IP "mount /dev/mmcblk0p1 / -oremount,ro ; reboot -if &"
149006 +
149007 --- a/scripts/mkuboot.sh
149008 +++ b/scripts/mkuboot.sh
149009 @@ -11,7 +11,7 @@ if [ -z "${MKIMAGE}" ]; then
149010         if [ -z "${MKIMAGE}" ]; then
149011                 # Doesn't exist
149012                 echo '"mkimage" command not found - U-Boot images will not be built' >&2
149013 -               exit 0;
149014 +               exit 1;
149015         fi
149016  fi
149017
149018 --- a/sound/soc/codecs/wm8753.c
149019 +++ b/sound/soc/codecs/wm8753.c
149020 @@ -1584,6 +1584,9 @@ static int wm8753_init(struct snd_soc_de
149021         schedule_delayed_work(&codec->delayed_work,
149022                 msecs_to_jiffies(caps_charge));
149023
149024 +       /* Fix reg WM8753_ADCTL2 */
149025 +       wm8753_write(codec, WM8753_ADCTL2, 0x0000);
149026 +
149027         /* set the update bits */
149028         reg = wm8753_read_reg_cache(codec, WM8753_LDAC);
149029         wm8753_write(codec, WM8753_LDAC, reg | 0x0100);
149030 @@ -1644,17 +1647,20 @@ static int wm8753_i2c_probe(struct i2c_c
149031         struct snd_soc_codec *codec = socdev->codec;
149032         int ret;
149033
149034 +       /* codec->control_data must be set before call to wm8753_init */
149035         i2c_set_clientdata(i2c, codec);
149036         codec->control_data = i2c;
149037
149038         ret = wm8753_init(socdev);
149039 -       if (ret < 0)
149040 +       if (ret < 0) {
149041                 pr_err("failed to initialise WM8753\n");
149042 +               codec->control_data = NULL;
149043 +       }
149044
149045         return ret;
149046  }
149047
149048 -static int wm8753_i2c_remove(struct i2c_client *client)
149049 +static int __devexit wm8753_i2c_remove(struct i2c_client *client)
149050  {
149051         struct snd_soc_codec *codec = i2c_get_clientdata(client);
149052         kfree(codec->reg_cache);
149053 @@ -1675,6 +1681,7 @@ static struct i2c_driver wm8753_i2c_driv
149054         .probe =    wm8753_i2c_probe,
149055         .remove =   wm8753_i2c_remove,
149056         .id_table = wm8753_i2c_id,
149057 +       .class =    I2C_CLASS_SOUND
149058  };
149059
149060  static int wm8753_add_i2c_device(struct platform_device *pdev,
149061 @@ -1716,6 +1723,8 @@ err_driver:
149062         i2c_del_driver(&wm8753_i2c_driver);
149063         return -ENODEV;
149064  }
149065 +
149066 +
149067  #endif
149068
149069  #if defined(CONFIG_SPI_MASTER)
149070 @@ -1783,7 +1792,7 @@ static int wm8753_probe(struct platform_
149071         struct wm8753_priv *wm8753;
149072         int ret = 0;
149073
149074 -       pr_info("WM8753 Audio Codec %s", WM8753_VERSION);
149075 +       pr_info("WM8753 Audio Codec %s\n", WM8753_VERSION);
149076
149077         setup = socdev->codec_data;
149078         codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
149079 @@ -1820,6 +1829,7 @@ static int wm8753_probe(struct platform_
149080  #endif
149081
149082         if (ret != 0) {
149083 +               printk(KERN_ERR "can't add codec bus driver\n");
149084                 kfree(codec->private_data);
149085                 kfree(codec);
149086         }
149087 @@ -1857,7 +1867,6 @@ static int wm8753_remove(struct platform
149088         snd_soc_free_pcms(socdev);
149089         snd_soc_dapm_free(socdev);
149090  #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
149091 -       i2c_unregister_device(codec->control_data);
149092         i2c_del_driver(&wm8753_i2c_driver);
149093  #endif
149094  #if defined(CONFIG_SPI_MASTER)
149095 --- a/sound/soc/s3c24xx/Kconfig
149096 +++ b/sound/soc/s3c24xx/Kconfig
149097 @@ -26,6 +26,15 @@ config SND_S3C24XX_SOC_NEO1973_WM8753
149098           Say Y if you want to add support for SoC audio on smdk2440
149099           with the WM8753.
149100
149101 +config SND_S3C24XX_SOC_NEO1973_GTA02_WM8753
149102 +       tristate "SoC I2S Audio support for NEO1973 GTA02 - WM8753"
149103 +       depends on SND_S3C24XX_SOC && MACH_NEO1973_GTA02
149104 +       select SND_S3C24XX_SOC_I2S
149105 +       select SND_SOC_WM8753
149106 +       help
149107 +         Say Y if you want to add support for SoC audio on neo1973 gta02
149108 +         with the WM8753 codec
149109 +
149110  config SND_S3C24XX_SOC_SMDK2443_WM9710
149111         tristate "SoC AC97 Audio support for SMDK2443 - WM9710"
149112         depends on SND_S3C24XX_SOC && MACH_SMDK2443
149113 --- a/sound/soc/s3c24xx/Makefile
149114 +++ b/sound/soc/s3c24xx/Makefile
149115 @@ -13,7 +13,10 @@ obj-$(CONFIG_SND_S3C2412_SOC_I2S) += snd
149116  snd-soc-neo1973-wm8753-objs := neo1973_wm8753.o
149117  snd-soc-smdk2443-wm9710-objs := smdk2443_wm9710.o
149118  snd-soc-ln2440sbc-alc650-objs := ln2440sbc_alc650.o
149119 +snd-soc-neo1973-gta02-wm8753-objs := neo1973_gta02_wm8753.o
149120
149121  obj-$(CONFIG_SND_S3C24XX_SOC_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o
149122  obj-$(CONFIG_SND_S3C24XX_SOC_SMDK2443_WM9710) += snd-soc-smdk2443-wm9710.o
149123  obj-$(CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650) += snd-soc-ln2440sbc-alc650.o
149124 +obj-$(CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753) += snd-soc-neo1973-gta02-wm8753.o
149125 +
149126 --- /dev/null
149127 +++ b/sound/soc/s3c24xx/neo1973_gta02_wm8753.c
149128 @@ -0,0 +1,673 @@
149129 +/*
149130 + * neo1973_gta02_wm8753.c  --  SoC audio for Neo1973
149131 + *
149132 + * Copyright 2007 Openmoko Inc
149133 + * Author: Graeme Gregory <graeme@openmoko.org>
149134 + * Copyright 2007 Wolfson Microelectronics PLC.
149135 + * Author: Graeme Gregory <linux@wolfsonmicro.com>
149136 + *
149137 + *  This program is free software; you can redistribute  it and/or modify it
149138 + *  under  the terms of  the GNU General  Public License as published by the
149139 + *  Free Software Foundation;  either version 2 of the  License, or (at your
149140 + *  option) any later version.
149141 + *
149142 + *  Revision history
149143 + *    06th Nov 2007   Changed from GTA01 to GTA02
149144 + *    20th Jan 2007   Initial version.
149145 + *    05th Feb 2007   Rename all to Neo1973
149146 + *
149147 + */
149148 +
149149 +#include <linux/module.h>
149150 +#include <linux/moduleparam.h>
149151 +#include <linux/timer.h>
149152 +#include <linux/interrupt.h>
149153 +#include <linux/platform_device.h>
149154 +#include <linux/i2c.h>
149155 +#include <sound/core.h>
149156 +#include <sound/pcm.h>
149157 +#include <sound/soc.h>
149158 +#include <sound/soc-dapm.h>
149159 +
149160 +#include <asm/mach-types.h>
149161 +#include <asm/hardware/scoop.h>
149162 +#include <asm/plat-s3c24xx/regs-iis.h>
149163 +#include <mach/regs-clock.h>
149164 +#include <mach/regs-gpio.h>
149165 +#include <mach/hardware.h>
149166 +#include <mach/audio.h>
149167 +#include <asm/io.h>
149168 +#include <mach/spi-gpio.h>
149169 +#include <mach/regs-gpioj.h>
149170 +#include <mach/gta02.h>
149171 +#include "../codecs/wm8753.h"
149172 +#include "s3c24xx-pcm.h"
149173 +#include "s3c24xx-i2s.h"
149174 +
149175 +/* define the scenarios */
149176 +#define NEO_AUDIO_OFF                  0
149177 +#define NEO_GSM_CALL_AUDIO_HANDSET     1
149178 +#define NEO_GSM_CALL_AUDIO_HEADSET     2
149179 +#define NEO_GSM_CALL_AUDIO_BLUETOOTH   3
149180 +#define NEO_STEREO_TO_SPEAKERS         4
149181 +#define NEO_STEREO_TO_HEADPHONES       5
149182 +#define NEO_CAPTURE_HANDSET            6
149183 +#define NEO_CAPTURE_HEADSET            7
149184 +#define NEO_CAPTURE_BLUETOOTH          8
149185 +#define NEO_STEREO_TO_HANDSET_SPK      9
149186 +
149187 +static struct snd_soc_machine neo1973_gta02;
149188 +
149189 +static int neo1973_gta02_hifi_hw_params(struct snd_pcm_substream *substream,
149190 +       struct snd_pcm_hw_params *params)
149191 +{
149192 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
149193 +       struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
149194 +       struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
149195 +       unsigned int pll_out = 0, bclk = 0;
149196 +       int ret = 0;
149197 +       unsigned long iis_clkrate;
149198 +
149199 +       iis_clkrate = s3c24xx_i2s_get_clockrate();
149200 +
149201 +       switch (params_rate(params)) {
149202 +       case 8000:
149203 +       case 16000:
149204 +               pll_out = 12288000;
149205 +               break;
149206 +       case 48000:
149207 +               bclk = WM8753_BCLK_DIV_4;
149208 +               pll_out = 12288000;
149209 +               break;
149210 +       case 96000:
149211 +               bclk = WM8753_BCLK_DIV_2;
149212 +               pll_out = 12288000;
149213 +               break;
149214 +       case 11025:
149215 +               bclk = WM8753_BCLK_DIV_16;
149216 +               pll_out = 11289600;
149217 +               break;
149218 +       case 22050:
149219 +               bclk = WM8753_BCLK_DIV_8;
149220 +               pll_out = 11289600;
149221 +               break;
149222 +       case 44100:
149223 +               bclk = WM8753_BCLK_DIV_4;
149224 +               pll_out = 11289600;
149225 +               break;
149226 +       case 88200:
149227 +               bclk = WM8753_BCLK_DIV_2;
149228 +               pll_out = 11289600;
149229 +               break;
149230 +       }
149231 +
149232 +       /* set codec DAI configuration */
149233 +       ret = codec_dai->dai_ops.set_fmt(codec_dai,
149234 +               SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
149235 +               SND_SOC_DAIFMT_CBM_CFM);
149236 +       if (ret < 0)
149237 +               return ret;
149238 +
149239 +       /* set cpu DAI configuration */
149240 +       ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
149241 +               SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
149242 +               SND_SOC_DAIFMT_CBM_CFM);
149243 +       if (ret < 0)
149244 +               return ret;
149245 +
149246 +       /* set the codec system clock for DAC and ADC */
149247 +       ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8753_MCLK, pll_out,
149248 +               SND_SOC_CLOCK_IN);
149249 +       if (ret < 0)
149250 +               return ret;
149251 +
149252 +       /* set MCLK division for sample rate */
149253 +       ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK,
149254 +               S3C2410_IISMOD_32FS );
149255 +       if (ret < 0)
149256 +               return ret;
149257 +
149258 +       /* set codec BCLK division for sample rate */
149259 +       ret = codec_dai->dai_ops.set_clkdiv(codec_dai,
149260 +                                       WM8753_BCLKDIV, bclk);
149261 +       if (ret < 0)
149262 +               return ret;
149263 +
149264 +       /* set prescaler division for sample rate */
149265 +       ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
149266 +               S3C24XX_PRESCALE(4,4));
149267 +       if (ret < 0)
149268 +               return ret;
149269 +
149270 +       /* codec PLL input is PCLK/4 */
149271 +       ret = codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL1,
149272 +               iis_clkrate / 4, pll_out);
149273 +       if (ret < 0)
149274 +               return ret;
149275 +
149276 +       return 0;
149277 +}
149278 +
149279 +static int neo1973_gta02_hifi_hw_free(struct snd_pcm_substream *substream)
149280 +{
149281 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
149282 +       struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
149283 +
149284 +       /* disable the PLL */
149285 +       return codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL1, 0, 0);
149286 +}
149287 +
149288 +/*
149289 + * Neo1973 WM8753 HiFi DAI opserations.
149290 + */
149291 +static struct snd_soc_ops neo1973_gta02_hifi_ops = {
149292 +       .hw_params = neo1973_gta02_hifi_hw_params,
149293 +       .hw_free = neo1973_gta02_hifi_hw_free,
149294 +};
149295 +
149296 +static int neo1973_gta02_voice_hw_params(
149297 +       struct snd_pcm_substream *substream,
149298 +       struct snd_pcm_hw_params *params)
149299 +{
149300 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
149301 +       struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
149302 +       unsigned int pcmdiv = 0;
149303 +       int ret = 0;
149304 +       unsigned long iis_clkrate;
149305 +
149306 +       iis_clkrate = s3c24xx_i2s_get_clockrate();
149307 +
149308 +       if (params_rate(params) != 8000)
149309 +               return -EINVAL;
149310 +       if (params_channels(params) != 1)
149311 +               return -EINVAL;
149312 +
149313 +       pcmdiv = WM8753_PCM_DIV_6; /* 2.048 MHz */
149314 +
149315 +       /* todo: gg check mode (DSP_B) against CSR datasheet */
149316 +       /* set codec DAI configuration */
149317 +       ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B |
149318 +               SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
149319 +       if (ret < 0)
149320 +               return ret;
149321 +
149322 +       /* set the codec system clock for DAC and ADC */
149323 +       ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8753_PCMCLK,
149324 +               12288000, SND_SOC_CLOCK_IN);
149325 +       if (ret < 0)
149326 +               return ret;
149327 +
149328 +       /* set codec PCM division for sample rate */
149329 +       ret = codec_dai->dai_ops.set_clkdiv(codec_dai, WM8753_PCMDIV,
149330 +                                       pcmdiv);
149331 +       if (ret < 0)
149332 +               return ret;
149333 +
149334 +       /* configue and enable PLL for 12.288MHz output */
149335 +       ret = codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL2,
149336 +               iis_clkrate / 4, 12288000);
149337 +       if (ret < 0)
149338 +               return ret;
149339 +
149340 +       return 0;
149341 +}
149342 +
149343 +static int neo1973_gta02_voice_hw_free(struct snd_pcm_substream *substream)
149344 +{
149345 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
149346 +       struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
149347 +
149348 +       /* disable the PLL */
149349 +       return codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL2, 0, 0);
149350 +}
149351 +
149352 +static struct snd_soc_ops neo1973_gta02_voice_ops = {
149353 +       .hw_params = neo1973_gta02_voice_hw_params,
149354 +       .hw_free = neo1973_gta02_voice_hw_free,
149355 +};
149356 +
149357 +#define LM4853_AMP 1
149358 +#define LM4853_SPK 2
149359 +
149360 +static u8 lm4853_state=0;
149361 +
149362 +static int lm4853_set_state(struct snd_kcontrol *kcontrol,
149363 +       struct snd_ctl_elem_value *ucontrol)
149364 +{
149365 +       int val = ucontrol->value.integer.value[0];
149366 +
149367 +       if(val) {
149368 +               lm4853_state |= LM4853_AMP;
149369 +               s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT,0);
149370 +       } else {
149371 +               lm4853_state &= ~LM4853_AMP;
149372 +               s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT,1);
149373 +       }
149374 +
149375 +       return 0;
149376 +}
149377 +
149378 +static int lm4853_get_state(struct snd_kcontrol *kcontrol,
149379 +       struct snd_ctl_elem_value *ucontrol)
149380 +{
149381 +       ucontrol->value.integer.value[0] = lm4853_state & LM4853_AMP;
149382 +
149383 +       return 0;
149384 +}
149385 +
149386 +static int lm4853_set_spk(struct snd_kcontrol *kcontrol,
149387 +       struct snd_ctl_elem_value *ucontrol)
149388 +{
149389 +       int val = ucontrol->value.integer.value[0];
149390 +
149391 +       if(val) {
149392 +               lm4853_state |= LM4853_SPK;
149393 +               s3c2410_gpio_setpin(GTA02_GPIO_HP_IN,0);
149394 +       } else {
149395 +               lm4853_state &= ~LM4853_SPK;
149396 +               s3c2410_gpio_setpin(GTA02_GPIO_HP_IN,1);
149397 +       }
149398 +
149399 +       return 0;
149400 +}
149401 +
149402 +static int lm4853_get_spk(struct snd_kcontrol *kcontrol,
149403 +       struct snd_ctl_elem_value *ucontrol)
149404 +{
149405 +       ucontrol->value.integer.value[0] = (lm4853_state & LM4853_SPK) >> 1;
149406 +
149407 +       return 0;
149408 +}
149409 +
149410 +static int neo1973_gta02_set_stereo_out(struct snd_kcontrol *kcontrol,
149411 +       struct snd_ctl_elem_value *ucontrol)
149412 +{
149413 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149414 +       int val = ucontrol->value.integer.value[0];
149415 +
149416 +       snd_soc_dapm_set_endpoint(codec, "Stereo Out", val);
149417 +
149418 +       snd_soc_dapm_sync(codec);
149419 +
149420 +       return 0;
149421 +}
149422 +
149423 +static int neo1973_gta02_get_stereo_out(struct snd_kcontrol *kcontrol,
149424 +       struct snd_ctl_elem_value *ucontrol)
149425 +{
149426 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149427 +
149428 +       ucontrol->value.integer.value[0] =
149429 +               snd_soc_dapm_get_endpoint(codec, "Stereo Out");
149430 +
149431 +       return 0;
149432 +}
149433 +
149434 +
149435 +static int neo1973_gta02_set_gsm_out(struct snd_kcontrol *kcontrol,
149436 +       struct snd_ctl_elem_value *ucontrol)
149437 +{
149438 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149439 +       int val = ucontrol->value.integer.value[0];
149440 +
149441 +       snd_soc_dapm_set_endpoint(codec, "GSM Line Out", val);
149442 +
149443 +       snd_soc_dapm_sync(codec);
149444 +
149445 +       return 0;
149446 +}
149447 +
149448 +static int neo1973_gta02_get_gsm_out(struct snd_kcontrol *kcontrol,
149449 +       struct snd_ctl_elem_value *ucontrol)
149450 +{
149451 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149452 +
149453 +       ucontrol->value.integer.value[0] =
149454 +               snd_soc_dapm_get_endpoint(codec, "GSM Line Out");
149455 +
149456 +       return 0;
149457 +}
149458 +
149459 +static int neo1973_gta02_set_gsm_in(struct snd_kcontrol *kcontrol,
149460 +       struct snd_ctl_elem_value *ucontrol)
149461 +{
149462 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149463 +       int val = ucontrol->value.integer.value[0];
149464 +
149465 +       snd_soc_dapm_set_endpoint(codec, "GSM Line In", val);
149466 +
149467 +       snd_soc_dapm_sync(codec);
149468 +
149469 +       return 0;
149470 +}
149471 +
149472 +static int neo1973_gta02_get_gsm_in(struct snd_kcontrol *kcontrol,
149473 +       struct snd_ctl_elem_value *ucontrol)
149474 +{
149475 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149476 +
149477 +       ucontrol->value.integer.value[0] =
149478 +               snd_soc_dapm_get_endpoint(codec, "GSM Line In");
149479 +
149480 +       return 0;
149481 +}
149482 +
149483 +static int neo1973_gta02_set_headset_mic(struct snd_kcontrol *kcontrol,
149484 +       struct snd_ctl_elem_value *ucontrol)
149485 +{
149486 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149487 +       int val = ucontrol->value.integer.value[0];
149488 +
149489 +       snd_soc_dapm_set_endpoint(codec, "Headset Mic", val);
149490 +
149491 +       snd_soc_dapm_sync(codec);
149492 +
149493 +       return 0;
149494 +}
149495 +
149496 +static int neo1973_gta02_get_headset_mic(struct snd_kcontrol *kcontrol,
149497 +       struct snd_ctl_elem_value *ucontrol)
149498 +{
149499 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149500 +
149501 +       ucontrol->value.integer.value[0] =
149502 +               snd_soc_dapm_get_endpoint(codec, "Headset Mic");
149503 +
149504 +       return 0;
149505 +}
149506 +
149507 +static int neo1973_gta02_set_handset_mic(struct snd_kcontrol *kcontrol,
149508 +       struct snd_ctl_elem_value *ucontrol)
149509 +{
149510 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149511 +       int val = ucontrol->value.integer.value[0];
149512 +
149513 +       snd_soc_dapm_set_endpoint(codec, "Handset Mic", val);
149514 +
149515 +       snd_soc_dapm_sync(codec);
149516 +
149517 +       return 0;
149518 +}
149519 +
149520 +static int neo1973_gta02_get_handset_mic(struct snd_kcontrol *kcontrol,
149521 +       struct snd_ctl_elem_value *ucontrol)
149522 +{
149523 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149524 +
149525 +       ucontrol->value.integer.value[0] =
149526 +               snd_soc_dapm_get_endpoint(codec, "Handset Mic");
149527 +
149528 +       return 0;
149529 +}
149530 +
149531 +static int neo1973_gta02_set_handset_spk(struct snd_kcontrol *kcontrol,
149532 +       struct snd_ctl_elem_value *ucontrol)
149533 +{
149534 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149535 +       int val = ucontrol->value.integer.value[0];
149536 +
149537 +       snd_soc_dapm_set_endpoint(codec, "Handset Spk", val);
149538 +
149539 +       snd_soc_dapm_sync(codec);
149540 +
149541 +       return 0;
149542 +}
149543 +
149544 +static int neo1973_gta02_get_handset_spk(struct snd_kcontrol *kcontrol,
149545 +       struct snd_ctl_elem_value *ucontrol)
149546 +{
149547 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
149548 +
149549 +       ucontrol->value.integer.value[0] =
149550 +               snd_soc_dapm_get_endpoint(codec, "Handset Spk");
149551 +
149552 +       return 0;
149553 +}
149554 +
149555 +static const struct snd_soc_dapm_widget wm8753_dapm_widgets[] = {
149556 +       SND_SOC_DAPM_LINE("Stereo Out", NULL),
149557 +       SND_SOC_DAPM_LINE("GSM Line Out", NULL),
149558 +       SND_SOC_DAPM_LINE("GSM Line In", NULL),
149559 +       SND_SOC_DAPM_MIC("Headset Mic", NULL),
149560 +       SND_SOC_DAPM_MIC("Handset Mic", NULL),
149561 +       SND_SOC_DAPM_SPK("Handset Spk", NULL),
149562 +};
149563 +
149564 +
149565 +/* example machine audio_mapnections */
149566 +static const char* audio_map[][3] = {
149567 +
149568 +       /* Connections to the lm4853 amp */
149569 +       {"Stereo Out", NULL, "LOUT1"},
149570 +       {"Stereo Out", NULL, "ROUT1"},
149571 +
149572 +       /* Connections to the GSM Module */
149573 +       {"GSM Line Out", NULL, "MONO1"},
149574 +       {"GSM Line Out", NULL, "MONO2"},
149575 +       {"RXP", NULL, "GSM Line In"},
149576 +       {"RXN", NULL, "GSM Line In"},
149577 +
149578 +       /* Connections to Headset */
149579 +       {"MIC1", NULL, "Mic Bias"},
149580 +       {"Mic Bias", NULL, "Headset Mic"},
149581 +
149582 +       /* Call Mic */
149583 +       {"MIC2", NULL, "Mic Bias"},
149584 +       {"MIC2N", NULL, "Mic Bias"},
149585 +       {"Mic Bias", NULL, "Handset Mic"},
149586 +
149587 +       /* Call Speaker */
149588 +       {"Handset Spk", NULL, "LOUT2"},
149589 +       {"Handset Spk", NULL, "ROUT2"},
149590 +
149591 +       /* Connect the ALC pins */
149592 +       {"ACIN", NULL, "ACOP"},
149593 +
149594 +       {NULL, NULL, NULL},
149595 +};
149596 +
149597 +static const struct snd_kcontrol_new wm8753_neo1973_gta02_controls[] = {
149598 +       SOC_SINGLE_EXT("DAPM Stereo Out Switch", 0, 0, 1, 0,
149599 +               neo1973_gta02_get_stereo_out,
149600 +               neo1973_gta02_set_stereo_out),
149601 +       SOC_SINGLE_EXT("DAPM GSM Line Out Switch", 1, 0, 1, 0,
149602 +               neo1973_gta02_get_gsm_out,
149603 +               neo1973_gta02_set_gsm_out),
149604 +       SOC_SINGLE_EXT("DAPM GSM Line In Switch", 2, 0, 1, 0,
149605 +               neo1973_gta02_get_gsm_in,
149606 +               neo1973_gta02_set_gsm_in),
149607 +       SOC_SINGLE_EXT("DAPM Headset Mic Switch", 3, 0, 1, 0,
149608 +               neo1973_gta02_get_headset_mic,
149609 +               neo1973_gta02_set_headset_mic),
149610 +       SOC_SINGLE_EXT("DAPM Handset Mic Switch", 4, 0, 1, 0,
149611 +               neo1973_gta02_get_handset_mic,
149612 +               neo1973_gta02_set_handset_mic),
149613 +       SOC_SINGLE_EXT("DAPM Handset Spk Switch", 5, 0, 1, 0,
149614 +               neo1973_gta02_get_handset_spk,
149615 +               neo1973_gta02_set_handset_spk),
149616 +       SOC_SINGLE_EXT("Amp State Switch", 6, 0, 1, 0,
149617 +               lm4853_get_state,
149618 +               lm4853_set_state),
149619 +       SOC_SINGLE_EXT("Amp Spk Switch", 7, 0, 1, 0,
149620 +               lm4853_get_spk,
149621 +               lm4853_set_spk),
149622 +};
149623 +
149624 +/*
149625 + * This is an example machine initialisation for a wm8753 connected to a
149626 + * neo1973 GTA02.
149627 + */
149628 +static int neo1973_gta02_wm8753_init(struct snd_soc_codec *codec)
149629 +{
149630 +       int i, err;
149631 +
149632 +       /* set up NC codec pins */
149633 +       snd_soc_dapm_set_endpoint(codec, "OUT3",  0);
149634 +       snd_soc_dapm_set_endpoint(codec, "OUT4",  0);
149635 +       snd_soc_dapm_set_endpoint(codec, "LINE1", 0);
149636 +       snd_soc_dapm_set_endpoint(codec, "LINE2", 0);
149637 +
149638 +       /* Add neo1973 gta02 specific widgets */
149639 +       for (i = 0; i < ARRAY_SIZE(wm8753_dapm_widgets); i++)
149640 +               snd_soc_dapm_new_control(codec, &wm8753_dapm_widgets[i]);
149641 +
149642 +       /* add neo1973 gta02 specific controls */
149643 +       for (i = 0; i < ARRAY_SIZE(wm8753_neo1973_gta02_controls); i++) {
149644 +               err = snd_ctl_add(codec->card,
149645 +                       snd_soc_cnew(&wm8753_neo1973_gta02_controls[i],
149646 +                       codec, NULL));
149647 +               if (err < 0)
149648 +                       return err;
149649 +       }
149650 +
149651 +       /* set up neo1973 gta02 specific audio path audio_mapnects */
149652 +       for (i = 0; audio_map[i][0] != NULL; i++) {
149653 +               snd_soc_dapm_connect_input(codec, audio_map[i][0],
149654 +                       audio_map[i][1], audio_map[i][2]);
149655 +       }
149656 +
149657 +       /* set endpoints to default off mode */
149658 +       snd_soc_dapm_set_endpoint(codec, "Stereo Out",  0);
149659 +       snd_soc_dapm_set_endpoint(codec, "GSM Line Out",0);
149660 +       snd_soc_dapm_set_endpoint(codec, "GSM Line In", 0);
149661 +       snd_soc_dapm_set_endpoint(codec, "Headset Mic", 0);
149662 +       snd_soc_dapm_set_endpoint(codec, "Handset Mic", 0);
149663 +       snd_soc_dapm_set_endpoint(codec, "Handset Spk", 0);
149664 +
149665 +       snd_soc_dapm_sync(codec);
149666 +
149667 +       return 0;
149668 +}
149669 +
149670 +/*
149671 + * BT Codec DAI
149672 + */
149673 +static struct snd_soc_dai bt_dai =
149674 +{      .name = "Bluetooth",
149675 +       .id = 0,
149676 +       .type = SND_SOC_DAI_PCM,
149677 +       .playback = {
149678 +               .channels_min = 1,
149679 +               .channels_max = 1,
149680 +               .rates = SNDRV_PCM_RATE_8000,
149681 +               .formats = SNDRV_PCM_FMTBIT_S16_LE,},
149682 +       .capture = {
149683 +               .channels_min = 1,
149684 +               .channels_max = 1,
149685 +               .rates = SNDRV_PCM_RATE_8000,
149686 +               .formats = SNDRV_PCM_FMTBIT_S16_LE,},
149687 +};
149688 +
149689 +static struct snd_soc_dai_link neo1973_gta02_dai[] = {
149690 +{ /* Hifi Playback - for similatious use with voice below */
149691 +       .name = "WM8753",
149692 +       .stream_name = "WM8753 HiFi",
149693 +       .cpu_dai = &s3c24xx_i2s_dai,
149694 +       .codec_dai = &wm8753_dai[WM8753_DAI_HIFI],
149695 +       .init = neo1973_gta02_wm8753_init,
149696 +       .ops = &neo1973_gta02_hifi_ops,
149697 +},
149698 +{ /* Voice via BT */
149699 +       .name = "Bluetooth",
149700 +       .stream_name = "Voice",
149701 +       .cpu_dai = &bt_dai,
149702 +       .codec_dai = &wm8753_dai[WM8753_DAI_VOICE],
149703 +       .ops = &neo1973_gta02_voice_ops,
149704 +},
149705 +};
149706 +
149707 +#ifdef CONFIG_PM
149708 +int neo1973_gta02_suspend(struct platform_device *pdev, pm_message_t state)
149709 +{
149710 +       s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT, 1);
149711 +
149712 +       return 0;
149713 +}
149714 +
149715 +int neo1973_gta02_resume(struct platform_device *pdev)
149716 +{
149717 +       if(lm4853_state & LM4853_AMP)
149718 +               s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT, 0);
149719 +
149720 +       return 0;
149721 +}
149722 +#else
149723 +#define neo1973_gta02_suspend NULL
149724 +#define neo1973_gta02_resume NULL
149725 +#endif
149726 +
149727 +static struct snd_soc_machine neo1973_gta02 = {
149728 +       .name = "neo1973-gta02",
149729 +       .suspend_pre = neo1973_gta02_suspend,
149730 +       .resume_post = neo1973_gta02_resume,
149731 +       .dai_link = neo1973_gta02_dai,
149732 +       .num_links = ARRAY_SIZE(neo1973_gta02_dai),
149733 +};
149734 +
149735 +/* Audio private data */
149736 +static struct wm8753_setup_data soc_codec_data_wm8753_gta02 = {
149737 +       .i2c_bus = 0,
149738 +       .i2c_address = 0x1a,
149739 +//     .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED,
149740 +//     .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT,
149741 +};
149742 +
149743 +static struct snd_soc_device neo1973_gta02_snd_devdata = {
149744 +       .machine = &neo1973_gta02,
149745 +       .platform = &s3c24xx_soc_platform,
149746 +       .codec_dev = &soc_codec_dev_wm8753,
149747 +       .codec_data = &soc_codec_data_wm8753_gta02,
149748 +};
149749 +
149750 +
149751 +
149752 +static struct platform_device *neo1973_gta02_snd_device;
149753 +
149754 +static int __init neo1973_gta02_init(void)
149755 +{
149756 +       int ret;
149757 +
149758 +       if (!machine_is_neo1973_gta02()) {
149759 +               printk(KERN_INFO
149760 +                      "Only GTA02 hardware supported by ASoc driver\n");
149761 +               return -ENODEV;
149762 +       }
149763 +
149764 +       neo1973_gta02_snd_device = platform_device_alloc("soc-audio", -1);
149765 +       if (!neo1973_gta02_snd_device)
149766 +               return -ENOMEM;
149767 +
149768 +       platform_set_drvdata(neo1973_gta02_snd_device,
149769 +                       &neo1973_gta02_snd_devdata);
149770 +       neo1973_gta02_snd_devdata.dev = &neo1973_gta02_snd_device->dev;
149771 +       ret = platform_device_add(neo1973_gta02_snd_device);
149772 +
149773 +       if (ret)
149774 +               platform_device_put(neo1973_gta02_snd_device);
149775 +
149776 +       /* Initialise GPIOs used by amp */
149777 +       s3c2410_gpio_cfgpin(GTA02_GPIO_HP_IN, S3C2410_GPIO_OUTPUT);
149778 +       s3c2410_gpio_cfgpin(GTA02_GPIO_AMP_SHUT, S3C2410_GPIO_OUTPUT);
149779 +
149780 +       /* Amp off by default */
149781 +       s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT, 1);
149782 +
149783 +       /* Speaker off by default */
149784 +       s3c2410_gpio_setpin(GTA02_GPIO_HP_IN, 1);
149785 +
149786 +       return ret;
149787 +}
149788 +
149789 +static void __exit neo1973_gta02_exit(void)
149790 +{
149791 +       platform_device_unregister(neo1973_gta02_snd_device);
149792 +}
149793 +
149794 +module_init(neo1973_gta02_init);
149795 +module_exit(neo1973_gta02_exit);
149796 +
149797 +/* Module information */
149798 +MODULE_AUTHOR("Graeme Gregory, graeme@openmoko.org");
149799 +MODULE_DESCRIPTION("ALSA SoC WM8753 Neo1973 GTA02");
149800 +MODULE_LICENSE("GPL");
149801 +
149802 --- a/sound/soc/s3c24xx/neo1973_wm8753.c
149803 +++ b/sound/soc/s3c24xx/neo1973_wm8753.c
149804 @@ -32,7 +32,7 @@
149805  #include <mach/audio.h>
149806  #include <linux/io.h>
149807  #include <mach/spi-gpio.h>
149808 -
149809 +#include <asm/mach-types.h>
149810  #include <asm/plat-s3c24xx/regs-iis.h>
149811
149812  #include "../codecs/wm8753.h"
149813 @@ -585,7 +585,7 @@ static struct snd_soc_machine neo1973 =
149814         .num_links = ARRAY_SIZE(neo1973_dai),
149815  };
149816
149817 -static struct wm8753_setup_data neo1973_wm8753_setup = {
149818 +static struct wm8753_setup_data soc_codec_data_wm8753_gta01 = {
149819         .i2c_bus = 0,
149820         .i2c_address = 0x1a,
149821  };
149822 @@ -594,7 +594,7 @@ static struct snd_soc_device neo1973_snd
149823         .machine = &neo1973,
149824         .platform = &s3c24xx_soc_platform,
149825         .codec_dev = &soc_codec_dev_wm8753,
149826 -       .codec_data = &neo1973_wm8753_setup,
149827 +       .codec_data = &soc_codec_data_wm8753_gta01
149828  };
149829
149830  static int lm4857_i2c_probe(struct i2c_client *client,
149831 @@ -676,7 +676,7 @@ static int __init neo1973_init(void)
149832  {
149833         int ret;
149834
149835 -       DBG("Entered %s\n", __func__);
149836 +       printk(KERN_DEBUG "Entered %s\n", __func__);
149837
149838         if (!machine_is_neo1973_gta01()) {
149839                 printk(KERN_INFO
149840 --- a/sound/soc/s3c24xx/s3c2443-ac97.c
149841 +++ b/sound/soc/s3c24xx/s3c2443-ac97.c
149842 @@ -28,7 +28,7 @@
149843  #include <sound/soc.h>
149844
149845  #include <mach/hardware.h>
149846 -#include <asm/plat-s3c/regs-ac97.h>
149847 +#include <plat/regs-ac97.h>
149848  #include <mach/regs-gpio.h>
149849  #include <mach/regs-clock.h>
149850  #include <mach/audio.h>
149851 --- a/sound/soc/s3c24xx/s3c24xx-i2s.c
149852 +++ b/sound/soc/s3c24xx/s3c24xx-i2s.c
149853 @@ -175,7 +175,7 @@ static void s3c24xx_snd_rxctrl(int on)
149854  static int s3c24xx_snd_lrsync(void)
149855  {
149856         u32 iiscon;
149857 -       int timeout = 50; /* 5ms */
149858 +       int timeout = 5; /* 500us, 125 should be enough at 8kHz */
149859
149860         DBG("Entered %s\n", __func__);
149861
149862 @@ -282,11 +282,14 @@ static int s3c24xx_i2s_trigger(struct sn
149863         case SNDRV_PCM_TRIGGER_START:
149864         case SNDRV_PCM_TRIGGER_RESUME:
149865         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
149866 -               if (!s3c24xx_snd_is_clkmaster()) {
149867 -                       ret = s3c24xx_snd_lrsync();
149868 -                       if (ret)
149869 -                               goto exit_err;
149870 -               }
149871 +               if (!s3c24xx_snd_is_clkmaster())
149872 +                       /* we ignore the return code, if it sync'd then fine,
149873 +                        * if it didn't sync, which happens after resume the
149874 +                        * first time when there was a live stream at suspend,
149875 +                        * just let it timeout, the stream picks up OK after
149876 +                        * that and LRCK is evidently working again.
149877 +                        */
149878 +                       s3c24xx_snd_lrsync();
149879
149880                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
149881                         s3c24xx_snd_rxctrl(1);
149882 @@ -306,7 +309,6 @@ static int s3c24xx_i2s_trigger(struct sn
149883                 break;
149884         }
149885
149886 -exit_err:
149887         return ret;
149888  }
149889
149890 --- a/sound/soc/s3c24xx/s3c24xx-pcm.c
149891 +++ b/sound/soc/s3c24xx/s3c24xx-pcm.c
149892 @@ -168,7 +168,7 @@ static int s3c24xx_pcm_hw_params(struct
149893                                           prtd->params->client, NULL);
149894
149895                 if (ret < 0) {
149896 -                       DBG(KERN_ERR "failed to get dma channel\n");
149897 +                       DBG(KERN_ERR "failed to get dma channel: %d\n", ret);
149898                         return ret;
149899                 }
149900         }
149901 --- a/sound/soc/soc-core.c
149902 +++ b/sound/soc/soc-core.c
149903 @@ -1003,6 +1003,38 @@ static ssize_t codec_reg_show(struct dev
149904  }
149905  static DEVICE_ATTR(codec_reg, 0444, codec_reg_show, NULL);
149906
149907 +
149908 +static ssize_t codec_reg_write(struct device *dev,
149909 +                              struct device_attribute *attr,
149910 +                              const char *buf, size_t count)
149911 +{
149912 +       u32 address;
149913 +       u32 data;
149914 +       char * end;
149915 +       size_t left = count;
149916 +       struct snd_soc_device *devdata = dev_get_drvdata(dev);
149917 +       struct snd_soc_codec *codec = devdata->codec;
149918 +
149919 +       address = simple_strtoul(buf, &end, 16);
149920 +       left -= (int)(end - buf);
149921 +       while ((*end == ' ') && (left)) {
149922 +               end++;
149923 +               left--;
149924 +       }
149925 +       if (!left)
149926 +               return count;
149927 +       data = simple_strtoul(end, &end, 16);
149928 +
149929 +       printk(KERN_INFO"user writes Codec reg 0x%02X with Data 0x%04X\n",
149930 +                                                               address, data);
149931 +
149932 +       codec->write(codec, address, data);
149933 +
149934 +       return count;
149935 +}
149936 +
149937 +static DEVICE_ATTR(codec_reg_write, 0644, NULL, codec_reg_write);
149938 +
149939  /**
149940   * snd_soc_new_ac97_codec - initailise AC97 device
149941   * @codec: audio codec
149942 @@ -1218,6 +1250,9 @@ int snd_soc_register_card(struct snd_soc
149943
149944         mutex_unlock(&codec->mutex);
149945
149946 +       err = device_create_file(socdev->dev, &dev_attr_codec_reg_write);
149947 +       if (err < 0)
149948 +               printk(KERN_WARNING "asoc: failed to add codec sysfs entries\n");
149949  out:
149950         return ret;
149951  }
149952 --- a/sound/soc/soc-dapm.c
149953 +++ b/sound/soc/soc-dapm.c
149954 @@ -1525,6 +1525,56 @@ int snd_soc_dapm_get_pin_status(struct s
149955  EXPORT_SYMBOL_GPL(snd_soc_dapm_get_pin_status);
149956
149957  /**
149958 + * snd_soc_dapm_get_endpoint - get audio endpoint status
149959 + * @codec: audio codec
149960 + * @endpoint: audio signal endpoint (or start point)
149961 + *
149962 + * Get audio endpoint status - connected or disconnected.
149963 + *
149964 + * Returns status
149965 + */
149966 +int snd_soc_dapm_get_endpoint(struct snd_soc_codec *codec,
149967 +       char *endpoint)
149968 +{
149969 +       struct snd_soc_dapm_widget *w;
149970 +
149971 +       list_for_each_entry(w, &codec->dapm_widgets, list) {
149972 +               if (!strcmp(w->name, endpoint)) {
149973 +                       return w->connected;
149974 +               }
149975 +       }
149976 +
149977 +       return 0;
149978 +}
149979 +EXPORT_SYMBOL_GPL(snd_soc_dapm_get_endpoint);
149980 +
149981 +/**
149982 + * snd_soc_dapm_set_endpoint - set audio endpoint status
149983 + * @codec: audio codec
149984 + * @endpoint: audio signal endpoint (or start point)
149985 + * @status: point status
149986 + *
149987 + * Set audio endpoint status - connected or disconnected.
149988 + *
149989 + * Returns 0 for success else error.
149990 + */
149991 +int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec,
149992 +        char *endpoint, int status)
149993 +{
149994 +        struct snd_soc_dapm_widget *w;
149995 +
149996 +        list_for_each_entry(w, &codec->dapm_widgets, list) {
149997 +               if (!strcmp(w->name, endpoint)) {
149998 +                        w->connected = status;
149999 +                        return 0;
150000 +                }
150001 +        }
150002 +
150003 +        return -ENODEV;
150004 +}
150005 +EXPORT_SYMBOL_GPL(snd_soc_dapm_set_endpoint);
150006 +
150007 +/**
150008   * snd_soc_dapm_free - free dapm resources
150009   * @socdev: SoC device
150010   *