target/linux/s3c24xx/patches-2.6.30/070-s3c24xx-time.patch

   1 Index: linux-2.6.30-rc6/arch/arm/plat-s3c24xx/time.c
   2 ===================================================================
   3 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
   4 +++ linux-2.6.30-rc6/arch/arm/plat-s3c24xx/time.c       2009-05-18 19:08:34.000000000 +0200
   5 @@ -0,0 +1,480 @@
   6 +/* linux/arch/arm/plat-s3c24xx/time.c
   7 + *
   8 + * Copyright (C) 2003-2005 Simtec Electronics
   9 + *     Ben Dooks, <ben@simtec.co.uk>
  10 + *
  11 + * dyn_tick support by Andrzej Zaborowski based on omap_dyn_tick_timer.
  12 + *
  13 + * This program is free software; you can redistribute it and/or modify
  14 + * it under the terms of the GNU General Public License as published by
  15 + * the Free Software Foundation; either version 2 of the License, or
  16 + * (at your option) any later version.
  17 + *
  18 + * This program is distributed in the hope that it will be useful,
  19 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 + * GNU General Public License for more details.
  22 + *
  23 + * You should have received a copy of the GNU General Public License
  24 + * along with this program; if not, write to the Free Software
  25 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26 + */
  27 +
  28 +#include <linux/kernel.h>
  29 +#include <linux/sched.h>
  30 +#include <linux/init.h>
  31 +#include <linux/interrupt.h>
  32 +#include <linux/irq.h>
  33 +#include <linux/err.h>
  34 +#include <linux/clk.h>
  35 +
  36 +#include <asm/system.h>
  37 +#include <asm/leds.h>
  38 +#include <asm/mach-types.h>
  39 +
  40 +#include <asm/io.h>
  41 +#include <asm/irq.h>
  42 +#include <mach/map.h>
  43 +#include <asm/plat-s3c/regs-timer.h>
  44 +#include <mach/regs-irq.h>
  45 +#include <asm/mach/time.h>
  46 +
  47 +#include <asm/plat-s3c24xx/clock.h>
  48 +#include <asm/plat-s3c24xx/cpu.h>
  49 +
  50 +static unsigned long timer_startval;
  51 +static unsigned long timer_usec_ticks;
  52 +static struct work_struct resume_work;
  53 +
  54 +unsigned long pclk;
  55 +struct clk *clk;
  56 +
  57 +#define TIMER_USEC_SHIFT 16
  58 +
  59 +/* we use the shifted arithmetic to work out the ratio of timer ticks
  60 + * to usecs, as often the peripheral clock is not a nice even multiple
  61 + * of 1MHz.
  62 + *
  63 + * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
  64 + * for the current HZ value of 200 without producing overflows.
  65 + *
  66 + * Original patch by Dimitry Andric, updated by Ben Dooks
  67 +*/
  68 +
  69 +
  70 +/* timer_mask_usec_ticks
  71 + *
  72 + * given a clock and divisor, make the value to pass into timer_ticks_to_usec
  73 + * to scale the ticks into usecs
  74 +*/
  75 +
  76 +static inline unsigned long
  77 +timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
  78 +{
  79 +       unsigned long den = pclk / 1000;
  80 +
  81 +       return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
  82 +}
  83 +
  84 +/* timer_ticks_to_usec
  85 + *
  86 + * convert timer ticks to usec.
  87 +*/
  88 +
  89 +static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
  90 +{
  91 +       unsigned long res;
  92 +
  93 +       res = ticks * timer_usec_ticks;
  94 +       res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
  95 +
  96 +       return res >> TIMER_USEC_SHIFT;
  97 +}
  98 +
  99 +/***
 100 + * Returns microsecond  since last clock interrupt.  Note that interrupts
 101 + * will have been disabled by do_gettimeoffset()
 102 + * IRQs are disabled before entering here from do_gettimeofday()
 103 + */
 104 +
 105 +#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
 106 +
 107 +unsigned long s3c2410_gettimeoffset (void)
 108 +{
 109 +       unsigned long tdone;
 110 +       unsigned long irqpend;
 111 +       unsigned long tval;
 112 +
 113 +       /* work out how many ticks have gone since last timer interrupt */
 114 +
 115 +        tval =  __raw_readl(S3C2410_TCNTO(4));
 116 +       tdone = timer_startval - tval;
 117 +
 118 +       /* check to see if there is an interrupt pending */
 119 +
 120 +       irqpend = __raw_readl(S3C2410_SRCPND);
 121 +       if (irqpend & SRCPND_TIMER4) {
 122 +               /* re-read the timer, and try and fix up for the missed
 123 +                * interrupt. Note, the interrupt may go off before the
 124 +                * timer has re-loaded from wrapping.
 125 +                */
 126 +
 127 +               tval =  __raw_readl(S3C2410_TCNTO(4));
 128 +               tdone = timer_startval - tval;
 129 +
 130 +               if (tval != 0)
 131 +                       tdone += timer_startval;
 132 +       }
 133 +
 134 +       return timer_ticks_to_usec(tdone);
 135 +}
 136 +
 137 +
 138 +/*
 139 + * IRQ handler for the timer
 140 + */
 141 +static irqreturn_t
 142 +s3c2410_timer_interrupt(int irq, void *dev_id)
 143 +{
 144 +       timer_tick();
 145 +       return IRQ_HANDLED;
 146 +}
 147 +
 148 +static struct irqaction s3c2410_timer_irq = {
 149 +       .name           = "S3C2410 Timer Tick",
 150 +       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 151 +       .handler        = s3c2410_timer_interrupt,
 152 +};
 153 +
 154 +#define use_tclk1_12() ( \
 155 +       machine_is_bast()       || \
 156 +       machine_is_vr1000()     || \
 157 +       machine_is_anubis()     || \
 158 +       machine_is_osiris() )
 159 +
 160 +/*
 161 + * Set up timer interrupt, and return the current time in seconds.
 162 + *
 163 + * Currently we only use timer4, as it is the only timer which has no
 164 + * other function that can be exploited externally
 165 + */
 166 +static void s3c2410_timer_setup (void)
 167 +{
 168 +       unsigned long tcon;
 169 +       unsigned long tcnt;
 170 +       unsigned long tcfg1;
 171 +       unsigned long tcfg0;
 172 +
 173 +       tcnt = 0xffff;  /* default value for tcnt */
 174 +
 175 +       /* read the current timer configuration bits */
 176 +
 177 +       tcon = __raw_readl(S3C2410_TCON);
 178 +       tcfg1 = __raw_readl(S3C2410_TCFG1);
 179 +       tcfg0 = __raw_readl(S3C2410_TCFG0);
 180 +
 181 +       /* configure the system for whichever machine is in use */
 182 +
 183 +       if (use_tclk1_12()) {
 184 +               /* timer is at 12MHz, scaler is 1 */
 185 +               timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
 186 +               tcnt = 12000000 / HZ;
 187 +
 188 +               tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
 189 +               tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
 190 +       } else {
 191 +               /* since values around 50 to
 192 +                * 70MHz are not values we can directly generate the timer
 193 +                * value from, we need to pre-scale and divide before using it.
 194 +                *
 195 +                * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
 196 +                * (8.45 ticks per usec)
 197 +                */
 198 +
 199 +               /* configure clock tick */
 200 +               timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
 201 +               printk("timer_usec_ticks = %lu\n", timer_usec_ticks);
 202 +
 203 +               tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
 204 +               tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
 205 +
 206 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
 207 +               tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
 208 +
 209 +               tcnt = (pclk / 6) / HZ;
 210 +       }
 211 +
 212 +       /* timers reload after counting zero, so reduce the count by 1 */
 213 +
 214 +       tcnt--;
 215 +
 216 +       printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
 217 +              tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
 218 +
 219 +       /* check to see if timer is within 16bit range... */
 220 +       if (tcnt > 0xffff) {
 221 +               panic("setup_timer: HZ is too small, cannot configure timer!");
 222 +               return;
 223 +       }
 224 +
 225 +       __raw_writel(tcfg1, S3C2410_TCFG1);
 226 +       __raw_writel(tcfg0, S3C2410_TCFG0);
 227 +
 228 +       timer_startval = tcnt;
 229 +       __raw_writel(tcnt, S3C2410_TCNTB(4));
 230 +
 231 +       /* ensure timer is stopped... */
 232 +
 233 +       tcon &= ~(7<<20);
 234 +       tcon |= S3C2410_TCON_T4RELOAD;
 235 +       tcon |= S3C2410_TCON_T4MANUALUPD;
 236 +
 237 +       __raw_writel(tcon, S3C2410_TCON);
 238 +       __raw_writel(tcnt, S3C2410_TCNTB(4));
 239 +       __raw_writel(tcnt, S3C2410_TCMPB(4));
 240 +
 241 +       /* start the timer running */
 242 +       tcon |= S3C2410_TCON_T4START;
 243 +       tcon &= ~S3C2410_TCON_T4MANUALUPD;
 244 +       __raw_writel(tcon, S3C2410_TCON);
 245 +
 246 +       __raw_writel(__raw_readl(S3C2410_INTMSK) & (~(1UL << 14)),
 247 +                    S3C2410_INTMSK);
 248 +
 249 +}
 250 +
 251 +struct sys_timer s3c24xx_timer;
 252 +static void timer_resume_work(struct work_struct *work)
 253 +{
 254 +       clk_enable(clk);
 255 +
 256 +#ifdef CONFIG_NO_IDLE_HZ
 257 +       if (s3c24xx_timer.dyn_tick->state & DYN_TICK_ENABLED)
 258 +               s3c24xx_timer.dyn_tick->enable();
 259 +       else
 260 +#endif
 261 +               s3c2410_timer_setup();
 262 +}
 263 +
 264 +static void __init s3c2410_timer_init (void)
 265 +{
 266 +       if (!use_tclk1_12()) {
 267 +               /* for the h1940 (and others), we use the pclk from the core
 268 +                * to generate the timer values.
 269 +                */
 270 +
 271 +               /* this is used as default if no other timer can be found */
 272 +               clk = clk_get(NULL, "timers");
 273 +               if (IS_ERR(clk))
 274 +                       panic("failed to get clock for system timer");
 275 +
 276 +               clk_enable(clk);
 277 +
 278 +               pclk = clk_get_rate(clk);
 279 +               printk("pclk = %lu\n", pclk);
 280 +       }
 281 +
 282 +       INIT_WORK(&resume_work, timer_resume_work);
 283 +       s3c2410_timer_setup();
 284 +       setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
 285 +}
 286 +
 287 +static void s3c2410_timer_resume_work(struct work_struct *work)
 288 +{
 289 +       s3c2410_timer_setup();
 290 +}
 291 +
 292 +static void s3c2410_timer_resume(void)
 293 +{
 294 +       static DECLARE_WORK(work, s3c2410_timer_resume_work);
 295 +       int res;
 296 +
 297 +       res = schedule_work(&work);
 298 +       if (!res)
 299 +               printk(KERN_ERR
 300 +                   "s3c2410_timer_resume_work already queued ???\n");
 301 +}
 302 +
 303 +#ifdef CONFIG_NO_IDLE_HZ
 304 +/*
 305 + * We'll set a constant prescaler so we don't have to bother setting it
 306 + * when reprogramming and so that we avoid costly divisions.
 307 + *
 308 + * (2 * HZ) << INPUT_FREQ_SHIFT is the desired frequency after prescaler.
 309 + * At HZ == 200, HZ * 1024 should work for PCLKs of up to ~53.5 MHz.
 310 + */
 311 +#define INPUT_FREQ_SHIFT       9
 312 +
 313 +static int ticks_last;
 314 +static int ticks_left;
 315 +static uint32_t tcnto_last;
 316 +
 317 +static inline int s3c24xx_timer_read(void)
 318 +{
 319 +       uint32_t tcnto = __raw_readl(S3C2410_TCNTO(4));
 320 +
 321 +       /*
 322 +        * WARNING: sometimes we get called before TCNTB has been
 323 +        * loaded into the counter and TCNTO then returns its previous
 324 +        * value and kill us, so don't do anything before counter is
 325 +        * reloaded.
 326 +        */
 327 +       if (unlikely(tcnto == tcnto_last))
 328 +               return ticks_last;
 329 +
 330 +       tcnto_last = -1;
 331 +       return tcnto <<
 332 +               ((__raw_readl(S3C2410_TCFG1) >> S3C2410_TCFG1_MUX4_SHIFT) & 3);
 333 +}
 334 +
 335 +static inline void s3c24xx_timer_program(int ticks)
 336 +{
 337 +       uint32_t tcon = __raw_readl(S3C2410_TCON) & ~(7 << 20);
 338 +       uint32_t tcfg1 = __raw_readl(S3C2410_TCFG1) & ~S3C2410_TCFG1_MUX4_MASK;
 339 +
 340 +       /* Just make sure the timer is stopped.  */
 341 +       __raw_writel(tcon, S3C2410_TCON);
 342 +
 343 +       /* TODO: add likely()ies / unlikely()ies */
 344 +       if (ticks >> 18) {
 345 +               ticks_last = min(ticks, 0xffff << 3);
 346 +               ticks_left = ticks - ticks_last;
 347 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV16, S3C2410_TCFG1);
 348 +               __raw_writel(ticks_last >> 3, S3C2410_TCNTB(4));
 349 +       } else if (ticks >> 17) {
 350 +               ticks_last = ticks;
 351 +               ticks_left = 0;
 352 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV8, S3C2410_TCFG1);
 353 +               __raw_writel(ticks_last >> 2, S3C2410_TCNTB(4));
 354 +       } else if (ticks >> 16) {
 355 +               ticks_last = ticks;
 356 +               ticks_left = 0;
 357 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV4, S3C2410_TCFG1);
 358 +               __raw_writel(ticks_last >> 1, S3C2410_TCNTB(4));
 359 +       } else {
 360 +               ticks_last = ticks;
 361 +               ticks_left = 0;
 362 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV2, S3C2410_TCFG1);
 363 +               __raw_writel(ticks_last >> 0, S3C2410_TCNTB(4));
 364 +       }
 365 +
 366 +       tcnto_last = __raw_readl(S3C2410_TCNTO(4));
 367 +       __raw_writel(tcon | S3C2410_TCON_T4MANUALUPD,
 368 +                       S3C2410_TCON);
 369 +       __raw_writel(tcon | S3C2410_TCON_T4START,
 370 +                       S3C2410_TCON);
 371 +}
 372 +
 373 +/*
 374 + * If we have already waited all the time we were supposed to wait,
 375 + * kick the timer, setting the longest allowed timeout value just
 376 + * for time-keeping.
 377 + */
 378 +static inline void s3c24xx_timer_program_idle(void)
 379 +{
 380 +       s3c24xx_timer_program(0xffff << 3);
 381 +}
 382 +
 383 +static inline void s3c24xx_timer_update(int restart)
 384 +{
 385 +       int ticks_cur = s3c24xx_timer_read();
 386 +       int jiffies_elapsed = (ticks_last - ticks_cur) >> INPUT_FREQ_SHIFT;
 387 +       int subjiffy = ticks_last - (jiffies_elapsed << INPUT_FREQ_SHIFT);
 388 +
 389 +       if (restart) {
 390 +               if (ticks_left >= (1 << INPUT_FREQ_SHIFT))
 391 +                       s3c24xx_timer_program(ticks_left);
 392 +               else
 393 +                       s3c24xx_timer_program_idle();
 394 +               ticks_last += subjiffy;
 395 +       } else
 396 +               ticks_last = subjiffy;
 397 +
 398 +       while (jiffies_elapsed --)
 399 +               timer_tick();
 400 +}
 401 +
 402 +/* Called when the timer expires.  */
 403 +static irqreturn_t s3c24xx_timer_handler(int irq, void *dev_id)
 404 +{
 405 +       tcnto_last = -1;
 406 +       s3c24xx_timer_update(1);
 407 +
 408 +       return IRQ_HANDLED;
 409 +}
 410 +
 411 +/* Called to update jiffies with time elapsed.  */
 412 +static irqreturn_t s3c24xx_timer_handler_dyn_tick(int irq, void *dev_id)
 413 +{
 414 +       s3c24xx_timer_update(0);
 415 +
 416 +       return IRQ_HANDLED;
 417 +}
 418 +
 419 +/*
 420 + * Programs the next timer interrupt needed.  Called when dynamic tick is
 421 + * enabled, and to reprogram the ticks to skip from pm_idle.  The CPU goes
 422 + * to sleep directly after this.
 423 + */
 424 +static void s3c24xx_timer_reprogram_dyn_tick(unsigned long next_jiffies)
 425 +{
 426 +       int subjiffy_left = ticks_last - s3c24xx_timer_read();
 427 +
 428 +       s3c24xx_timer_program(max((int) next_jiffies, 1) << INPUT_FREQ_SHIFT);
 429 +       ticks_last += subjiffy_left;
 430 +}
 431 +
 432 +static unsigned long s3c24xx_timer_offset_dyn_tick(void)
 433 +{
 434 +       /* TODO */
 435 +       return 0;
 436 +}
 437 +
 438 +static int s3c24xx_timer_enable_dyn_tick(void)
 439 +{
 440 +       /* Set our constant prescaler.  */
 441 +       uint32_t tcfg0 = __raw_readl(S3C2410_TCFG0);
 442 +       int prescaler =
 443 +               max(min(256, (int) pclk / (HZ << (INPUT_FREQ_SHIFT + 1))), 1);
 444 +
 445 +       tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
 446 +       tcfg0 |= (prescaler - 1) << S3C2410_TCFG_PRESCALER1_SHIFT;
 447 +       __raw_writel(tcfg0, S3C2410_TCFG0);
 448 +
 449 +       /* Override handlers.  */
 450 +       s3c2410_timer_irq.handler = s3c24xx_timer_handler;
 451 +       s3c24xx_timer.offset = s3c24xx_timer_offset_dyn_tick;
 452 +
 453 +       printk(KERN_INFO "dyn_tick enabled on s3c24xx timer 4, "
 454 +                       "%li Hz pclk with prescaler %i\n", pclk, prescaler);
 455 +
 456 +       s3c24xx_timer_program_idle();
 457 +
 458 +       return 0;
 459 +}
 460 +
 461 +static int s3c24xx_timer_disable_dyn_tick(void)
 462 +{
 463 +       s3c2410_timer_irq.handler = s3c2410_timer_interrupt;
 464 +       s3c24xx_timer.offset = s3c2410_gettimeoffset;
 465 +       s3c2410_timer_setup();
 466 +
 467 +       return 0;
 468 +}
 469 +
 470 +static struct dyn_tick_timer s3c24xx_dyn_tick_timer = {
 471 +       .enable         = s3c24xx_timer_enable_dyn_tick,
 472 +       .disable        = s3c24xx_timer_disable_dyn_tick,
 473 +       .reprogram      = s3c24xx_timer_reprogram_dyn_tick,
 474 +       .handler        = s3c24xx_timer_handler_dyn_tick,
 475 +};
 476 +#endif /* CONFIG_NO_IDLE_HZ */
 477 +
 478 +struct sys_timer s3c24xx_timer = {
 479 +       .init           = s3c2410_timer_init,
 480 +       .offset         = s3c2410_gettimeoffset,
 481 +       .resume         = s3c2410_timer_resume,
 482 +#ifdef CONFIG_NO_IDLE_HZ
 483 +       .dyn_tick       = &s3c24xx_dyn_tick_timer,
 484 +#endif
 485 +};