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renumber sibyte patches
[openwrt/svn-archive/archive.git] / target / linux / sibyte / patches / 104-sibyte_rtc_cleanup.patch
1 --- a/arch/mips/sibyte/swarm/Makefile
2 +++ b/arch/mips/sibyte/swarm/Makefile
3 @@ -1,4 +1,3 @@
4 -obj-y := platform.o setup.o rtc_xicor1241.o \
5 - rtc_m41t81.o
6 +obj-y := platform.o setup.o
7
8 obj-$(CONFIG_I2C_BOARDINFO) += swarm-i2c.o
9 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c
10 +++ /dev/null
11 @@ -1,233 +0,0 @@
12 -/*
13 - * Copyright (C) 2000, 2001 Broadcom Corporation
14 - *
15 - * Copyright (C) 2002 MontaVista Software Inc.
16 - * Author: jsun@mvista.com or jsun@junsun.net
17 - *
18 - * This program is free software; you can redistribute it and/or modify it
19 - * under the terms of the GNU General Public License as published by the
20 - * Free Software Foundation; either version 2 of the License, or (at your
21 - * option) any later version.
22 - *
23 - */
24 -#include <linux/bcd.h>
25 -#include <linux/types.h>
26 -#include <linux/time.h>
27 -
28 -#include <asm/time.h>
29 -#include <asm/addrspace.h>
30 -#include <asm/io.h>
31 -
32 -#include <asm/sibyte/sb1250.h>
33 -#include <asm/sibyte/sb1250_regs.h>
34 -#include <asm/sibyte/sb1250_smbus.h>
35 -
36 -
37 -/* M41T81 definitions */
38 -
39 -/*
40 - * Register bits
41 - */
42 -
43 -#define M41T81REG_SC_ST 0x80 /* stop bit */
44 -#define M41T81REG_HR_CB 0x40 /* century bit */
45 -#define M41T81REG_HR_CEB 0x80 /* century enable bit */
46 -#define M41T81REG_CTL_S 0x20 /* sign bit */
47 -#define M41T81REG_CTL_FT 0x40 /* frequency test bit */
48 -#define M41T81REG_CTL_OUT 0x80 /* output level */
49 -#define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */
50 -#define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */
51 -#define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */
52 -#define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */
53 -#define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */
54 -#define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */
55 -#define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */
56 -#define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */
57 -#define M41T81REG_AMO_SQWE 0x40 /* square wave enable */
58 -#define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */
59 -#define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */
60 -#define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */
61 -#define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */
62 -#define M41T81REG_AHR_HT 0x40 /* halt update bit */
63 -#define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */
64 -#define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */
65 -#define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */
66 -#define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */
67 -#define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */
68 -#define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */
69 -#define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */
70 -#define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */
71 -
72 -
73 -/*
74 - * Register numbers
75 - */
76 -
77 -#define M41T81REG_TSC 0x00 /* tenths/hundredths of second */
78 -#define M41T81REG_SC 0x01 /* seconds */
79 -#define M41T81REG_MN 0x02 /* minute */
80 -#define M41T81REG_HR 0x03 /* hour/century */
81 -#define M41T81REG_DY 0x04 /* day of week */
82 -#define M41T81REG_DT 0x05 /* date of month */
83 -#define M41T81REG_MO 0x06 /* month */
84 -#define M41T81REG_YR 0x07 /* year */
85 -#define M41T81REG_CTL 0x08 /* control */
86 -#define M41T81REG_WD 0x09 /* watchdog */
87 -#define M41T81REG_AMO 0x0A /* alarm: month */
88 -#define M41T81REG_ADT 0x0B /* alarm: date */
89 -#define M41T81REG_AHR 0x0C /* alarm: hour */
90 -#define M41T81REG_AMN 0x0D /* alarm: minute */
91 -#define M41T81REG_ASC 0x0E /* alarm: second */
92 -#define M41T81REG_FLG 0x0F /* flags */
93 -#define M41T81REG_SQW 0x13 /* square wave register */
94 -
95 -#define M41T81_CCR_ADDRESS 0x68
96 -
97 -#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
98 -
99 -static int m41t81_read(uint8_t addr)
100 -{
101 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
102 - ;
103 -
104 - __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
105 - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE,
106 - SMB_CSR(R_SMB_START));
107 -
108 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
109 - ;
110 -
111 - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
112 - SMB_CSR(R_SMB_START));
113 -
114 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
115 - ;
116 -
117 - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
118 - /* Clear error bit by writing a 1 */
119 - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
120 - return -1;
121 - }
122 -
123 - return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
124 -}
125 -
126 -static int m41t81_write(uint8_t addr, int b)
127 -{
128 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
129 - ;
130 -
131 - __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
132 - __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA));
133 - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
134 - SMB_CSR(R_SMB_START));
135 -
136 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
137 - ;
138 -
139 - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
140 - /* Clear error bit by writing a 1 */
141 - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
142 - return -1;
143 - }
144 -
145 - /* read the same byte again to make sure it is written */
146 - __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
147 - SMB_CSR(R_SMB_START));
148 -
149 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
150 - ;
151 -
152 - return 0;
153 -}
154 -
155 -int m41t81_set_time(unsigned long t)
156 -{
157 - struct rtc_time tm;
158 - unsigned long flags;
159 -
160 - /* Note we don't care about the century */
161 - rtc_time_to_tm(t, &tm);
162 -
163 - /*
164 - * Note the write order matters as it ensures the correctness.
165 - * When we write sec, 10th sec is clear. It is reasonable to
166 - * believe we should finish writing min within a second.
167 - */
168 -
169 - spin_lock_irqsave(&rtc_lock, flags);
170 - tm.tm_sec = bin2bcd(tm.tm_sec);
171 - m41t81_write(M41T81REG_SC, tm.tm_sec);
172 -
173 - tm.tm_min = bin2bcd(tm.tm_min);
174 - m41t81_write(M41T81REG_MN, tm.tm_min);
175 -
176 - tm.tm_hour = bin2bcd(tm.tm_hour);
177 - tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0);
178 - m41t81_write(M41T81REG_HR, tm.tm_hour);
179 -
180 - /* tm_wday starts from 0 to 6 */
181 - if (tm.tm_wday == 0) tm.tm_wday = 7;
182 - tm.tm_wday = bin2bcd(tm.tm_wday);
183 - m41t81_write(M41T81REG_DY, tm.tm_wday);
184 -
185 - tm.tm_mday = bin2bcd(tm.tm_mday);
186 - m41t81_write(M41T81REG_DT, tm.tm_mday);
187 -
188 - /* tm_mon starts from 0, *ick* */
189 - tm.tm_mon ++;
190 - tm.tm_mon = bin2bcd(tm.tm_mon);
191 - m41t81_write(M41T81REG_MO, tm.tm_mon);
192 -
193 - /* we don't do century, everything is beyond 2000 */
194 - tm.tm_year %= 100;
195 - tm.tm_year = bin2bcd(tm.tm_year);
196 - m41t81_write(M41T81REG_YR, tm.tm_year);
197 - spin_unlock_irqrestore(&rtc_lock, flags);
198 -
199 - return 0;
200 -}
201 -
202 -unsigned long m41t81_get_time(void)
203 -{
204 - unsigned int year, mon, day, hour, min, sec;
205 - unsigned long flags;
206 -
207 - /*
208 - * min is valid if two reads of sec are the same.
209 - */
210 - for (;;) {
211 - spin_lock_irqsave(&rtc_lock, flags);
212 - sec = m41t81_read(M41T81REG_SC);
213 - min = m41t81_read(M41T81REG_MN);
214 - if (sec == m41t81_read(M41T81REG_SC)) break;
215 - spin_unlock_irqrestore(&rtc_lock, flags);
216 - }
217 - hour = m41t81_read(M41T81REG_HR) & 0x3f;
218 - day = m41t81_read(M41T81REG_DT);
219 - mon = m41t81_read(M41T81REG_MO);
220 - year = m41t81_read(M41T81REG_YR);
221 - spin_unlock_irqrestore(&rtc_lock, flags);
222 -
223 - sec = bcd2bin(sec);
224 - min = bcd2bin(min);
225 - hour = bcd2bin(hour);
226 - day = bcd2bin(day);
227 - mon = bcd2bin(mon);
228 - year = bcd2bin(year);
229 -
230 - year += 2000;
231 -
232 - return mktime(year, mon, day, hour, min, sec);
233 -}
234 -
235 -int m41t81_probe(void)
236 -{
237 - unsigned int tmp;
238 -
239 - /* enable chip if it is not enabled yet */
240 - tmp = m41t81_read(M41T81REG_SC);
241 - m41t81_write(M41T81REG_SC, tmp & 0x7f);
242 -
243 - return (m41t81_read(M41T81REG_SC) != -1);
244 -}
245 --- a/arch/mips/sibyte/swarm/rtc_xicor1241.c
246 +++ /dev/null
247 @@ -1,210 +0,0 @@
248 -/*
249 - * Copyright (C) 2000, 2001 Broadcom Corporation
250 - *
251 - * Copyright (C) 2002 MontaVista Software Inc.
252 - * Author: jsun@mvista.com or jsun@junsun.net
253 - *
254 - * This program is free software; you can redistribute it and/or modify it
255 - * under the terms of the GNU General Public License as published by the
256 - * Free Software Foundation; either version 2 of the License, or (at your
257 - * option) any later version.
258 - */
259 -#include <linux/bcd.h>
260 -#include <linux/types.h>
261 -#include <linux/time.h>
262 -
263 -#include <asm/time.h>
264 -#include <asm/addrspace.h>
265 -#include <asm/io.h>
266 -
267 -#include <asm/sibyte/sb1250.h>
268 -#include <asm/sibyte/sb1250_regs.h>
269 -#include <asm/sibyte/sb1250_smbus.h>
270 -
271 -
272 -/* Xicor 1241 definitions */
273 -
274 -/*
275 - * Register bits
276 - */
277 -
278 -#define X1241REG_SR_BAT 0x80 /* currently on battery power */
279 -#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */
280 -#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */
281 -#define X1241REG_SR_RTCF 0x01 /* clock failed */
282 -#define X1241REG_BL_BP2 0x80 /* block protect 2 */
283 -#define X1241REG_BL_BP1 0x40 /* block protect 1 */
284 -#define X1241REG_BL_BP0 0x20 /* block protect 0 */
285 -#define X1241REG_BL_WD1 0x10
286 -#define X1241REG_BL_WD0 0x08
287 -#define X1241REG_HR_MIL 0x80 /* military time format */
288 -
289 -/*
290 - * Register numbers
291 - */
292 -
293 -#define X1241REG_BL 0x10 /* block protect bits */
294 -#define X1241REG_INT 0x11 /* */
295 -#define X1241REG_SC 0x30 /* Seconds */
296 -#define X1241REG_MN 0x31 /* Minutes */
297 -#define X1241REG_HR 0x32 /* Hours */
298 -#define X1241REG_DT 0x33 /* Day of month */
299 -#define X1241REG_MO 0x34 /* Month */
300 -#define X1241REG_YR 0x35 /* Year */
301 -#define X1241REG_DW 0x36 /* Day of Week */
302 -#define X1241REG_Y2K 0x37 /* Year 2K */
303 -#define X1241REG_SR 0x3F /* Status register */
304 -
305 -#define X1241_CCR_ADDRESS 0x6F
306 -
307 -#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
308 -
309 -static int xicor_read(uint8_t addr)
310 -{
311 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
312 - ;
313 -
314 - __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
315 - __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
316 - __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
317 - SMB_CSR(R_SMB_START));
318 -
319 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
320 - ;
321 -
322 - __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
323 - SMB_CSR(R_SMB_START));
324 -
325 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
326 - ;
327 -
328 - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
329 - /* Clear error bit by writing a 1 */
330 - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
331 - return -1;
332 - }
333 -
334 - return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
335 -}
336 -
337 -static int xicor_write(uint8_t addr, int b)
338 -{
339 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
340 - ;
341 -
342 - __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
343 - __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
344 - __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
345 - SMB_CSR(R_SMB_START));
346 -
347 - while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
348 - ;
349 -
350 - if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
351 - /* Clear error bit by writing a 1 */
352 - __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
353 - return -1;
354 - } else {
355 - return 0;
356 - }
357 -}
358 -
359 -int xicor_set_time(unsigned long t)
360 -{
361 - struct rtc_time tm;
362 - int tmp;
363 - unsigned long flags;
364 -
365 - rtc_time_to_tm(t, &tm);
366 - tm.tm_year += 1900;
367 -
368 - spin_lock_irqsave(&rtc_lock, flags);
369 - /* unlock writes to the CCR */
370 - xicor_write(X1241REG_SR, X1241REG_SR_WEL);
371 - xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL);
372 -
373 - /* trivial ones */
374 - tm.tm_sec = bin2bcd(tm.tm_sec);
375 - xicor_write(X1241REG_SC, tm.tm_sec);
376 -
377 - tm.tm_min = bin2bcd(tm.tm_min);
378 - xicor_write(X1241REG_MN, tm.tm_min);
379 -
380 - tm.tm_mday = bin2bcd(tm.tm_mday);
381 - xicor_write(X1241REG_DT, tm.tm_mday);
382 -
383 - /* tm_mon starts from 0, *ick* */
384 - tm.tm_mon ++;
385 - tm.tm_mon = bin2bcd(tm.tm_mon);
386 - xicor_write(X1241REG_MO, tm.tm_mon);
387 -
388 - /* year is split */
389 - tmp = tm.tm_year / 100;
390 - tm.tm_year %= 100;
391 - xicor_write(X1241REG_YR, tm.tm_year);
392 - xicor_write(X1241REG_Y2K, tmp);
393 -
394 - /* hour is the most tricky one */
395 - tmp = xicor_read(X1241REG_HR);
396 - if (tmp & X1241REG_HR_MIL) {
397 - /* 24 hour format */
398 - tm.tm_hour = bin2bcd(tm.tm_hour);
399 - tmp = (tmp & ~0x3f) | (tm.tm_hour & 0x3f);
400 - } else {
401 - /* 12 hour format, with 0x2 for pm */
402 - tmp = tmp & ~0x3f;
403 - if (tm.tm_hour >= 12) {
404 - tmp |= 0x20;
405 - tm.tm_hour -= 12;
406 - }
407 - tm.tm_hour = bin2bcd(tm.tm_hour);
408 - tmp |= tm.tm_hour;
409 - }
410 - xicor_write(X1241REG_HR, tmp);
411 -
412 - xicor_write(X1241REG_SR, 0);
413 - spin_unlock_irqrestore(&rtc_lock, flags);
414 -
415 - return 0;
416 -}
417 -
418 -unsigned long xicor_get_time(void)
419 -{
420 - unsigned int year, mon, day, hour, min, sec, y2k;
421 - unsigned long flags;
422 -
423 - spin_lock_irqsave(&rtc_lock, flags);
424 - sec = xicor_read(X1241REG_SC);
425 - min = xicor_read(X1241REG_MN);
426 - hour = xicor_read(X1241REG_HR);
427 -
428 - if (hour & X1241REG_HR_MIL) {
429 - hour &= 0x3f;
430 - } else {
431 - if (hour & 0x20)
432 - hour = (hour & 0xf) + 0x12;
433 - }
434 -
435 - day = xicor_read(X1241REG_DT);
436 - mon = xicor_read(X1241REG_MO);
437 - year = xicor_read(X1241REG_YR);
438 - y2k = xicor_read(X1241REG_Y2K);
439 - spin_unlock_irqrestore(&rtc_lock, flags);
440 -
441 - sec = bcd2bin(sec);
442 - min = bcd2bin(min);
443 - hour = bcd2bin(hour);
444 - day = bcd2bin(day);
445 - mon = bcd2bin(mon);
446 - year = bcd2bin(year);
447 - y2k = bcd2bin(y2k);
448 -
449 - year += (y2k * 100);
450 -
451 - return mktime(year, mon, day, hour, min, sec);
452 -}
453 -
454 -int xicor_probe(void)
455 -{
456 - return (xicor_read(X1241REG_SC) != -1);
457 -}
458 --- a/arch/mips/sibyte/swarm/setup.c
459 +++ b/arch/mips/sibyte/swarm/setup.c
460 @@ -56,14 +56,6 @@ extern void sb1250_setup(void);
461 #error invalid SiByte board configuration
462 #endif
463
464 -extern int xicor_probe(void);
465 -extern int xicor_set_time(unsigned long);
466 -extern unsigned long xicor_get_time(void);
467 -
468 -extern int m41t81_probe(void);
469 -extern int m41t81_set_time(unsigned long);
470 -extern unsigned long m41t81_get_time(void);
471 -
472 const char *get_system_type(void)
473 {
474 return "SiByte " SIBYTE_BOARD_NAME;
475 @@ -79,42 +71,14 @@ int swarm_be_handler(struct pt_regs *reg
476 return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
477 }
478
479 -enum swarm_rtc_type {
480 - RTC_NONE,
481 - RTC_XICOR,
482 - RTC_M4LT81
483 -};
484 -
485 -enum swarm_rtc_type swarm_rtc_type;
486 -
487 unsigned long read_persistent_clock(void)
488 {
489 - switch (swarm_rtc_type) {
490 - case RTC_XICOR:
491 - return xicor_get_time();
492 -
493 - case RTC_M4LT81:
494 - return m41t81_get_time();
495 -
496 - case RTC_NONE:
497 - default:
498 - return mktime(2000, 1, 1, 0, 0, 0);
499 - }
500 + return mktime(2000, 1, 1, 0, 0, 0);
501 }
502
503 int rtc_mips_set_time(unsigned long sec)
504 {
505 - switch (swarm_rtc_type) {
506 - case RTC_XICOR:
507 - return xicor_set_time(sec);
508 -
509 - case RTC_M4LT81:
510 - return m41t81_set_time(sec);
511 -
512 - case RTC_NONE:
513 - default:
514 - return -1;
515 - }
516 + return -1;
517 }
518
519 void __init plat_mem_setup(void)
520 @@ -131,11 +95,6 @@ void __init plat_mem_setup(void)
521
522 board_be_handler = swarm_be_handler;
523
524 - if (xicor_probe())
525 - swarm_rtc_type = RTC_XICOR;
526 - if (m41t81_probe())
527 - swarm_rtc_type = RTC_M4LT81;
528 -
529 printk("This kernel optimized for "
530 #ifdef CONFIG_SIMULATION
531 "simulation"
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