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add preliminary support for Storm SL3512 based devices, not ready yet
[openwrt/svn-archive/archive.git] / target / linux / storm / patches / 1020-mtd.patch
1 Index: linux-2.6.23.16/drivers/mtd/chips/Kconfig
2 ===================================================================
3 --- linux-2.6.23.16.orig/drivers/mtd/chips/Kconfig 2008-03-15 17:03:14.374622039 +0200
4 +++ linux-2.6.23.16/drivers/mtd/chips/Kconfig 2008-03-15 17:03:17.874821522 +0200
5 @@ -220,6 +220,13 @@
6 This option enables basic support for ROM chips accessed through
7 a bus mapping driver.
8
9 +config MTD_SERIAL
10 + tristate "Support for Serial chips in bus mapping"
11 + depends on MTD
12 + help
13 + This option enables basic support for Serial chips accessed through
14 + a bus mapping driver.
15 +
16 config MTD_ABSENT
17 tristate "Support for absent chips in bus mapping"
18 help
19 Index: linux-2.6.23.16/drivers/mtd/chips/cfi_cmdset_0002.c
20 ===================================================================
21 --- linux-2.6.23.16.orig/drivers/mtd/chips/cfi_cmdset_0002.c 2008-03-15 17:03:14.374622039 +0200
22 +++ linux-2.6.23.16/drivers/mtd/chips/cfi_cmdset_0002.c 2008-03-15 17:03:17.874821522 +0200
23 @@ -39,10 +39,15 @@
24 #include <linux/mtd/cfi.h>
25 #include <linux/mtd/xip.h>
26
27 +//****** Storlink SoC ******
28 #define AMD_BOOTLOC_BUG
29 -#define FORCE_WORD_WRITE 0
30 -
31 -#define MAX_WORD_RETRIES 3
32 +//#define FORCE_WORD_WRITE 0
33 +#define FORCE_WORD_WRITE 1
34 +#define FORCE_FAST_PROG 0
35 +
36 +//#define MAX_WORD_RETRIES 3
37 +#define MAX_WORD_RETRIES 3 // CONFIG_MTD_CFI_AMDSTD_RETRY
38 +//**************************
39
40 #define MANUFACTURER_AMD 0x0001
41 #define MANUFACTURER_ATMEL 0x001F
42 @@ -322,6 +327,13 @@
43 #endif
44
45 bootloc = extp->TopBottom;
46 +//****** Storlink SoC ******
47 + if(bootloc == 5)
48 + {
49 + bootloc = 3;
50 + extp->TopBottom = 3;
51 + }
52 +//**************************
53 if ((bootloc != 2) && (bootloc != 3)) {
54 printk(KERN_WARNING "%s: CFI does not contain boot "
55 "bank location. Assuming top.\n", map->name);
56 @@ -340,6 +352,9 @@
57 cfi->cfiq->EraseRegionInfo[j] = swap;
58 }
59 }
60 +#ifdef CONFIG_MTD_MAP_BANK_WIDTH_1
61 + cfi->device_type = CFI_DEVICETYPE_X8;
62 +#endif
63 /* Set the default CFI lock/unlock addresses */
64 cfi->addr_unlock1 = 0x555;
65 cfi->addr_unlock2 = 0x2aa;
66 @@ -461,6 +476,7 @@
67 map_word d, t;
68
69 d = map_read(map, addr);
70 + udelay(20); //Storlink SoC
71 t = map_read(map, addr);
72
73 return map_word_equal(map, d, t);
74 @@ -626,7 +642,9 @@
75 default:
76 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
77 }
78 +//****** Storlink SoC ******
79 wake_up(&chip->wq);
80 +//**************************
81 }
82
83 #ifdef CONFIG_MTD_XIP
84 @@ -940,7 +958,9 @@
85 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
86 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
87
88 +//****** Storlink SoC ******
89 wake_up(&chip->wq);
90 +//**************************
91 spin_unlock(chip->mutex);
92
93 return 0;
94 @@ -1005,7 +1025,10 @@
95 */
96 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
97 int ret = 0;
98 - map_word oldd;
99 +//****** Storlink SoC ******
100 +// map_word oldd;
101 + map_word oldd, tmp;
102 +//**************************
103 int retry_cnt = 0;
104
105 adr += chip->start;
106 @@ -1037,9 +1060,15 @@
107 ENABLE_VPP(map);
108 xip_disable(map, chip, adr);
109 retry:
110 +//****** Storlink SoC ******
111 +#if FORCE_FAST_PROG /* Unlock bypass */
112 + cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
113 +#else
114 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
115 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
116 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
117 +#endif
118 +//**************************
119 map_write(map, datum, adr);
120 chip->state = FL_WRITING;
121
122 @@ -1072,7 +1101,13 @@
123 }
124
125 if (chip_ready(map, adr))
126 - break;
127 + {
128 + tmp = map_read(map, adr);
129 + if(map_word_equal(map, tmp, datum))
130 +// goto op_done;
131 + break;
132 +
133 + }
134
135 /* Latency issues. Drop the lock, wait a while and retry */
136 UDELAY(map, chip, adr, 1);
137 @@ -1084,8 +1119,17 @@
138 /* FIXME - should have reset delay before continuing */
139
140 if (++retry_cnt <= MAX_WORD_RETRIES)
141 + {
142 +//****** Storlink SoC ******
143 +#if FORCE_FAST_PROG
144 + cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
145 + cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
146 + cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
147 + //udelay(1);
148 +#endif
149 + udelay(1);
150 goto retry;
151 -
152 + }
153 ret = -EIO;
154 }
155 xip_enable(map, chip, adr);
156 @@ -1171,7 +1215,14 @@
157 return 0;
158 }
159 }
160 -
161 +//****** Storlink SoC ******
162 + map_write( map, CMD(0xF0), chipstart );
163 +#if FORCE_FAST_PROG
164 + cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
165 + cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
166 + cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
167 +#endif
168 +//**************************
169 /* We are now aligned, write as much as possible */
170 while(len >= map_bankwidth(map)) {
171 map_word datum;
172 @@ -1181,7 +1232,15 @@
173 ret = do_write_oneword(map, &cfi->chips[chipnum],
174 ofs, datum);
175 if (ret)
176 + {
177 +//****** Storlink SoC ******
178 +#if FORCE_FAST_PROG
179 + /* Get out of unlock bypass mode */
180 + cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
181 + cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
182 +#endif
183 return ret;
184 + }
185
186 ofs += map_bankwidth(map);
187 buf += map_bankwidth(map);
188 @@ -1189,19 +1248,38 @@
189 len -= map_bankwidth(map);
190
191 if (ofs >> cfi->chipshift) {
192 +//****** Storlink SoC ******
193 +#if FORCE_FAST_PROG
194 + /* Get out of unlock bypass mode */
195 + cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
196 + cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
197 +#endif
198 chipnum ++;
199 ofs = 0;
200 if (chipnum == cfi->numchips)
201 return 0;
202 chipstart = cfi->chips[chipnum].start;
203 +#if FORCE_FAST_PROG
204 + /* Go into unlock bypass mode for next set of chips */
205 + cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
206 + cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
207 + cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
208 +#endif
209 }
210 }
211
212 +#if FORCE_FAST_PROG
213 + /* Get out of unlock bypass mode */
214 + cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
215 + cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
216 +#endif
217 +
218 /* Write the trailing bytes if any */
219 if (len & (map_bankwidth(map)-1)) {
220 map_word tmp_buf;
221
222 retry1:
223 +
224 spin_lock(cfi->chips[chipnum].mutex);
225
226 if (cfi->chips[chipnum].state != FL_READY) {
227 @@ -1221,7 +1299,11 @@
228 #endif
229 goto retry1;
230 }
231 -
232 +#if FORCE_FAST_PROG
233 + cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
234 + cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
235 + cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
236 +#endif
237 tmp_buf = map_read(map, ofs + chipstart);
238
239 spin_unlock(cfi->chips[chipnum].mutex);
240 @@ -1231,11 +1313,23 @@
241 ret = do_write_oneword(map, &cfi->chips[chipnum],
242 ofs, tmp_buf);
243 if (ret)
244 + {
245 +#if FORCE_FAST_PROG
246 + /* Get out of unlock bypass mode */
247 + cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
248 + cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
249 +#endif
250 return ret;
251 -
252 + }
253 +#if FORCE_FAST_PROG
254 + /* Get out of unlock bypass mode */
255 + cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
256 + cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
257 +#endif
258 (*retlen) += len;
259 }
260
261 + map_write( map, CMD(0xF0), chipstart );
262 return 0;
263 }
264
265 @@ -1275,6 +1369,7 @@
266 ENABLE_VPP(map);
267 xip_disable(map, chip, cmd_adr);
268
269 + map_write( map, CMD(0xF0), chip->start ); //Storlink
270 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
271 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
272 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
273 @@ -1535,6 +1630,9 @@
274 DECLARE_WAITQUEUE(wait, current);
275 int ret = 0;
276
277 +#ifdef CONFIG_SL2312_SHARE_PIN
278 + mtd_lock(); // sl2312 share pin lock
279 +#endif
280 adr += chip->start;
281
282 spin_lock(chip->mutex);
283 @@ -1613,6 +1711,9 @@
284 chip->state = FL_READY;
285 put_chip(map, chip, adr);
286 spin_unlock(chip->mutex);
287 +#ifdef CONFIG_SL2312_SHARE_PIN
288 + mtd_unlock(); // sl2312 share pin lock
289 +#endif
290 return ret;
291 }
292
293 Index: linux-2.6.23.16/drivers/mtd/chips/map_serial.c
294 ===================================================================
295 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
296 +++ linux-2.6.23.16/drivers/mtd/chips/map_serial.c 2008-03-15 17:03:17.874821522 +0200
297 @@ -0,0 +1,188 @@
298 +/*
299 + * Common code to handle map devices which are simple ROM
300 + * (C) 2000 Red Hat. GPL'd.
301 + * $Id: map_serial.c,v 1.3 2006/06/05 02:34:54 middle Exp $
302 + */
303 +
304 +#include <linux/version.h>
305 +#include <linux/module.h>
306 +#include <linux/types.h>
307 +#include <linux/kernel.h>
308 +#include <asm/io.h>
309 +
310 +#include <asm/byteorder.h>
311 +#include <linux/errno.h>
312 +#include <linux/slab.h>
313 +
314 +#include <asm/hardware.h>
315 +#include <linux/mtd/map.h>
316 +#include <linux/mtd/mtd.h>
317 +#include <linux/init.h> //add
318 +#include <asm/arch/sl2312.h>
319 +#include <asm/arch/flash.h>
320 +
321 +static int mapserial_erase(struct mtd_info *mtd, struct erase_info *instr);
322 +static int mapserial_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
323 +static int mapserial_write (struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
324 +static void mapserial_nop (struct mtd_info *);
325 +struct mtd_info *map_serial_probe(struct map_info *map);
326 +
327 +extern int m25p80_sector_erase(__u32 address, __u32 schip_en);
328 +
329 +static struct mtd_chip_driver mapserial_chipdrv = {
330 + probe: map_serial_probe,
331 + name: "map_serial",
332 + module: THIS_MODULE
333 +};
334 +
335 +struct mtd_info *map_serial_probe(struct map_info *map)
336 +{
337 + struct mtd_info *mtd;
338 +
339 + mtd = kmalloc(sizeof(*mtd), GFP_KERNEL);
340 + if (!mtd)
341 + return NULL;
342 +
343 + memset(mtd, 0, sizeof(*mtd));
344 +
345 + map->fldrv = &mapserial_chipdrv;
346 + mtd->priv = map;
347 + mtd->name = map->name;
348 + mtd->type = MTD_OTHER;
349 + mtd->erase = mapserial_erase;
350 + mtd->size = map->size;
351 + mtd->read = mapserial_read;
352 + mtd->write = mapserial_write;
353 + mtd->sync = mapserial_nop;
354 + mtd->flags = (MTD_WRITEABLE|MTD_ERASEABLE);
355 +// mtd->erasesize = 512; // page size;
356 +#ifdef CONFIG_MTD_SL2312_SERIAL_ST
357 + mtd->erasesize = M25P80_SECTOR_SIZE; // block size;
358 +#else
359 + mtd->erasesize = 0x1000; // block size;
360 +#endif
361 +
362 + __module_get(THIS_MODULE);
363 + //MOD_INC_USE_COUNT;
364 + return mtd;
365 +}
366 +
367 +#define FLASH_ACCESS_OFFSET 0x00000010
368 +#define FLASH_ADDRESS_OFFSET 0x00000014
369 +#define FLASH_WRITE_DATA_OFFSET 0x00000018
370 +#define FLASH_READ_DATA_OFFSET 0x00000018
371 +
372 +static __u32 readflash_ctrl_reg(__u32 ofs)
373 +{
374 + __u32 *base;
375 +
376 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
377 + return __raw_readl(base);
378 +}
379 +
380 +static void writeflash_ctrl_reg(__u32 data, __u32 ofs)
381 +{
382 + __u32 *base;
383 +
384 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
385 + __raw_writel(data, base);
386 +}
387 +
388 +static int mapserial_erase_block(struct map_info *map,unsigned int block)
389 +{
390 +
391 + __u32 address;
392 +#ifdef CONFIG_MTD_SL2312_SERIAL_ST
393 +
394 + if(!m25p80_sector_erase(block, 0))
395 + return (MTD_ERASE_DONE);
396 +#else
397 + __u32 opcode;
398 + __u32 count=0;
399 +// __u8 status;
400 +
401 + // printk("mapserial_erase_block : erase block %d \n",block);
402 +// opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd;
403 + opcode = 0x80000000 | 0x0200 | 0x50;
404 + address = (block << 13);
405 + writeflash_ctrl_reg(address,FLASH_ADDRESS_OFFSET);
406 + writeflash_ctrl_reg(opcode,FLASH_ACCESS_OFFSET);
407 + opcode=readflash_ctrl_reg(FLASH_ACCESS_OFFSET);
408 + while(opcode&0x80000000)
409 + {
410 + opcode = readflash_ctrl_reg(FLASH_ACCESS_OFFSET);
411 + count++;
412 + if (count > 10000)
413 + {
414 + return (MTD_ERASE_FAILED);
415 + }
416 + }
417 + return (MTD_ERASE_DONE);
418 +#endif
419 +}
420 +
421 +static int mapserial_erase(struct mtd_info *mtd, struct erase_info *instr)
422 +{
423 + struct map_info *map = (struct map_info *)mtd->priv;
424 + unsigned int addr;
425 + int len;
426 + unsigned int block;
427 + unsigned int ret=0;
428 +
429 + addr = instr->addr;
430 + len = instr->len;
431 + while (len > 0)
432 + {
433 + block = addr / mtd->erasesize;
434 +#ifdef CONFIG_MTD_SL2312_SERIAL_ST
435 + ret = mapserial_erase_block(map,addr);
436 +#else
437 + ret = mapserial_erase_block(map,block);
438 +#endif
439 + addr = addr + mtd->erasesize;
440 + len = len - mtd->erasesize;
441 + }
442 + return (ret);
443 +}
444 +
445 +static int mapserial_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
446 +{
447 + struct map_info *map = (struct map_info *)mtd->priv;
448 +// printk("mapserial_read : \n");
449 + map->copy_from(map, buf, from, len);
450 + *retlen = len;
451 + return 0;
452 +}
453 +
454 +static void mapserial_nop(struct mtd_info *mtd)
455 +{
456 + /* Nothing to see here */
457 +}
458 +
459 +static int mapserial_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
460 +{
461 + struct map_info *map = (struct map_info *)mtd->priv;
462 +// printk("mapserial_write : buf %x to %x len %x \n",(int)buf, (int)to, (int)len);
463 + //map->copy_to(map, buf, to, len);
464 + map->copy_to(map, to, buf, len);
465 + *retlen = len;
466 + return 0;
467 +}
468 +
469 +int __init map_serial_init(void)
470 +{
471 + register_mtd_chip_driver(&mapserial_chipdrv);
472 + return 0;
473 +}
474 +
475 +static void __exit map_serial_exit(void)
476 +{
477 + unregister_mtd_chip_driver(&mapserial_chipdrv);
478 +}
479 +
480 +module_init(map_serial_init);
481 +module_exit(map_serial_exit);
482 +
483 +MODULE_LICENSE("GPL");
484 +MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
485 +MODULE_DESCRIPTION("MTD chip driver for ROM chips");
486 Index: linux-2.6.23.16/drivers/mtd/maps/Kconfig
487 ===================================================================
488 --- linux-2.6.23.16.orig/drivers/mtd/maps/Kconfig 2008-03-15 17:03:14.374622039 +0200
489 +++ linux-2.6.23.16/drivers/mtd/maps/Kconfig 2008-03-15 17:03:17.874821522 +0200
490 @@ -614,5 +614,30 @@
491
492 This selection automatically selects the map_ram driver.
493
494 +#***************************************************************************************
495 +# Storlink parallel/Serial Flash configuration
496 +#***************************************************************************************
497 +config MTD_SL2312_CFI
498 + tristate "CFI Flash device mapped on SL2312"
499 + depends on MTD_CFI
500 + help
501 + Map driver for SL2312 demo board.
502 +
503 +config MTD_SL2312_SERIAL_ATMEL
504 + tristate "ATMEL Serial Flash device mapped on SL2312"
505 + depends on MTD_PARTITIONS && ARCH_SL2312
506 + help
507 + Map driver for SL2312 demo board.
508 +
509 +config MTD_SL2312_SERIAL_ST
510 + tristate "ST Serial Flash device mapped on SL2312"
511 + depends on MTD_PARTITIONS && ARCH_SL2312
512 + help
513 + Map driver for SL2312 demo board.
514 +
515 +config SL2312_SHARE_PIN
516 + tristate "Parallel Flash share pin on SL2312 ASIC"
517 + depends on SL3516_ASIC
518 +
519 endmenu
520
521 Index: linux-2.6.23.16/drivers/mtd/maps/sl2312-flash-atmel.c
522 ===================================================================
523 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
524 +++ linux-2.6.23.16/drivers/mtd/maps/sl2312-flash-atmel.c 2008-03-15 17:04:02.877385981 +0200
525 @@ -0,0 +1,554 @@
526 +/*
527 + * $Id: sl2312-flash-atmel.c,v 1.2 2006/06/05 02:35:57 middle Exp $
528 + *
529 + * Flash and EPROM on Hitachi Solution Engine and similar boards.
530 + *
531 + * (C) 2001 Red Hat, Inc.
532 + *
533 + * GPL'd
534 + */
535 +
536 +#include <linux/module.h>
537 +#include <linux/types.h>
538 +#include <linux/kernel.h>
539 +
540 +#include <asm/io.h>
541 +#include <linux/mtd/mtd.h>
542 +#include <linux/mtd/map.h>
543 +#include <linux/mtd/partitions.h>
544 +#include <asm/hardware.h>
545 +
546 +#include <asm/arch/sl2312.h>
547 +#include <asm/arch/flash.h>
548 +#include <linux/init.h> //add
549 +
550 +
551 +#define g_page_addr AT45DB321_PAGE_SHIFT //321 : shift 10 ; 642 : shift 11
552 +#define g_chipen SERIAL_FLASH_CHIP0_EN //atmel
553 +
554 +extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
555 +
556 +void address_to_page(__u32 address, __u16 *page, __u16 *offset)
557 +{
558 + *page = address / SPAGE_SIZE;
559 + *offset = address % SPAGE_SIZE;
560 +}
561 +
562 +static __u32 read_flash_ctrl_reg(__u32 ofs)
563 +{
564 + __u32 *base;
565 +
566 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
567 + return __raw_readl(base);
568 +}
569 +
570 +static void write_flash_ctrl_reg(__u32 ofs,__u32 data)
571 +{
572 + __u32 *base;
573 +
574 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
575 + __raw_writel(data, base);
576 +}
577 +
578 +void atmel_read_status(__u8 cmd, __u8 *data)
579 +{
580 + __u32 opcode;
581 + __u32 value;
582 +
583 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | cmd | g_chipen;
584 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
585 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
586 + while(opcode&0x80000000)
587 + {
588 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
589 + flash_delay();
590 + schedule();
591 + }
592 +
593 + value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
594 + *data = value & 0xff;
595 +}
596 +
597 +void main_memory_page_read(__u8 cmd, __u16 page, __u16 offset, __u8 *data)
598 +{
599 + __u32 opcode;
600 + __u32 address;
601 + __u32 value;
602 +
603 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_4X_DATA | cmd | g_chipen;
604 + address = (page << g_page_addr) + offset;
605 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
606 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
607 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
608 + while(opcode&0x80000000)
609 + {
610 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
611 + flash_delay();
612 + schedule();
613 + }
614 +
615 + value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
616 + *data = value & 0xff;
617 +}
618 +
619 +void buffer_to_main_memory(__u8 cmd, __u16 page)
620 +{
621 + __u32 opcode;
622 + __u32 address;
623 + __u8 status;
624 +
625 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
626 + address = (page << g_page_addr);
627 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
628 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
629 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
630 + while(opcode&0x80000000)
631 + {
632 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
633 + flash_delay();
634 + schedule();
635 + }
636 + atmel_read_status(READ_STATUS_SPI, &status);
637 + while(!(status&0x80))
638 + {
639 + atmel_read_status(READ_STATUS_SPI, &status);
640 + flash_delay();
641 + schedule();
642 + }
643 +
644 +}
645 +
646 +
647 +void atmel_flash_read_page(__u32 address, __u8 *buffer, __u32 len)
648 +{
649 + __u8 byte;
650 + __u16 page, offset;
651 + __u16 i;
652 +
653 + address_to_page(address, &page, &offset);
654 +
655 + for(i=0; i<len; i++,offset++)
656 + {
657 + main_memory_page_read(MAIN_MEMORY_PAGE_READ_SPI , page, offset, &byte);
658 + buffer [i]= byte;
659 + }
660 +}
661 +
662 +void atmel_flash_program_page(__u32 address, __u8 *buffer, __u32 len)
663 +{
664 + __u8 pattern;
665 + __u16 page, offset;
666 + __u32 i;
667 +
668 + address_to_page(address, &page, &offset);
669 + // printk("atmel_flash_program_page: offset %x len %x page %x \n", offset, len, page);
670 +
671 + if(offset)
672 + main_memory_to_buffer(MAIN_MEMORY_TO_BUFFER1,page);
673 +
674 + for(i=0; i<len; i++,offset++)
675 + {
676 + pattern = buffer[i];
677 + atmel_buffer_write(BUFFER1_WRITE,offset,pattern);
678 + }
679 +
680 + // printk("atmel_flash_program_page: offset %x \n", offset);
681 + buffer_to_main_memory(BUFFER1_TO_MAIN_MEMORY, page);
682 + // printk("atmel_flash_program_page: buffer_to_main_memory %x page\n", page);
683 +
684 +}
685 +
686 +
687 +void main_memory_to_buffer(__u8 cmd, __u16 page)
688 +{
689 + __u32 opcode;
690 + __u32 address;
691 + __u8 status;
692 +
693 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
694 + address = (page << g_page_addr);
695 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
696 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
697 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
698 + while(opcode&0x80000000)
699 + {
700 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
701 + flash_delay();
702 + schedule();
703 + }
704 + atmel_read_status(READ_STATUS_SPI, &status);
705 + while(!(status&0x80))
706 + {
707 + atmel_read_status(READ_STATUS_SPI, &status);
708 + flash_delay();
709 + schedule();
710 + }
711 +
712 +}
713 +
714 +void main_memory_page_program(__u8 cmd, __u16 page, __u16 offset, __u8 data)
715 +{
716 + __u32 opcode;
717 + __u32 address;
718 + __u8 status;
719 +
720 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | cmd | g_chipen;
721 + address = (page << g_page_addr) + offset;
722 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
723 + write_flash_ctrl_reg(FLASH_WRITE_DATA_OFFSET, data);
724 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
725 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
726 + while(opcode&0x80000000)
727 + {
728 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
729 + flash_delay();
730 + schedule();
731 + }
732 + atmel_read_status(READ_STATUS_SPI, &status);
733 + while(!(status&0x80))
734 + {
735 + atmel_read_status(READ_STATUS_SPI, &status);
736 + flash_delay();
737 + schedule();
738 + }
739 +}
740 +
741 +void atmel_buffer_write(__u8 cmd, __u16 offset, __u8 data)
742 +{
743 + __u32 opcode;
744 + __u32 address;
745 +
746 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | cmd | g_chipen;
747 + address = offset;
748 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
749 + write_flash_ctrl_reg(FLASH_WRITE_DATA_OFFSET, data);
750 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
751 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
752 + while(opcode&0x80000000)
753 + {
754 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
755 + flash_delay();
756 + schedule();
757 + }
758 +
759 +}
760 +
761 +void atmel_erase_page(__u8 cmd, __u16 page)
762 +{
763 + __u32 opcode;
764 + __u32 address;
765 + __u8 status;
766 +
767 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
768 + address = (page << g_page_addr);
769 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
770 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
771 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
772 + while(opcode&0x80000000)
773 + {
774 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
775 + flash_delay();
776 + schedule();
777 + }
778 + atmel_read_status(READ_STATUS_SPI, &status);
779 + while(!(status&0x80))
780 + {
781 + atmel_read_status(READ_STATUS_SPI, &status);
782 + flash_delay();
783 + schedule();
784 + }
785 +
786 +}
787 +
788 +void atmel_erase_block(__u8 cmd, __u16 block)
789 +{
790 + __u32 opcode;
791 + __u32 address;
792 + __u8 status;
793 +
794 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
795 + address = (block << 13);
796 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
797 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
798 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
799 + while(opcode&0x80000000)
800 + {
801 + opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
802 + flash_delay();
803 + schedule();
804 + }
805 + atmel_read_status(READ_STATUS_SPI, &status);
806 + while(!(status&0x80))
807 + {
808 + atmel_read_status(READ_STATUS_SPI, &status);
809 + flash_delay();
810 + schedule();
811 + }
812 +
813 +}
814 +
815 +void flash_delay(void)
816 +{
817 + int i;
818 +
819 + for(i=0; i<50; i++)
820 + i=i;
821 +}
822 +
823 +
824 +
825 +
826 +__u32 sl2312_read32(struct map_info *map, unsigned long ofs)
827 +{
828 +
829 +#if 0
830 + __u16 page, offset;
831 + __u32 pattern;
832 + __u8 byte, i;
833 +
834 + pattern = 0;
835 + address_to_page(ofs, &page, &offset);
836 + for(i=0; i<4; i++, offset++)
837 + {
838 + pattern = pattern << 8;
839 + main_memory_page_read(MAIN_MEMORY_PAGE_READ_SPI , page, offset, &byte);
840 +//printk("sl2312_read32:: address = %08x data = %c \n",ofs,byte);
841 + pattern += byte;
842 + }
843 + return pattern;
844 +#else
845 + return read_flash_ctrl_reg(ofs);
846 +#endif
847 +
848 +}
849 +
850 +__u8 sl2312_read8(struct map_info *map, unsigned long ofs)
851 +{
852 + __u16 page, offset;
853 + __u8 byte;
854 +
855 + address_to_page(ofs, &page, &offset);
856 + main_memory_page_read(MAIN_MEMORY_PAGE_READ_SPI , page, offset, &byte);
857 + //printk("sl2312_read8:: address = %08x data = %c \n",ofs,byte);
858 + return byte;
859 +
860 +}
861 +
862 +void sl2312_write32(struct map_info *map, __u32 d, unsigned long ofs)
863 +{
864 +#if 0
865 + __u16 page, offset;
866 + __u8 byte, i;
867 +
868 + address_to_page(ofs, &page, &offset);
869 + for(i=0; i<4; i++, offset++)
870 + {
871 + byte = d & 0xff;
872 + main_memory_page_program(MAIN_MEMORY_PROGRAM_BUFFER1, page, offset, byte);
873 + d = d >> 8;
874 +//printk("sl2312_write32:: address = %08x data = %c \n",ofs,byte);
875 + }
876 +#else
877 + write_flash_ctrl_reg(ofs, d);
878 +#endif
879 +}
880 +
881 +void sl2312_write8(struct map_info *map, __u8 d, unsigned long ofs)
882 +{
883 + __u16 page, offset;
884 +
885 + address_to_page(ofs, &page, &offset);
886 + main_memory_page_program(MAIN_MEMORY_PROGRAM_BUFFER1, page, offset, d);
887 +//printk("sl2312_write8:: address = %08x data = %c \n",ofs,d);
888 +
889 +}
890 +
891 +void sl2312_copy_from(struct map_info *map, void *buf, unsigned long ofs, ssize_t len)
892 +{
893 + __u32 size;
894 + __u8 *buffer;
895 + __u32 length;//i, j,
896 +
897 + //printk("sl2312_copy_from:: address = %08x datalen = %d \n",ofs,len);
898 +
899 + length = len;
900 + buffer = (__u8 *)buf;
901 + while(len)
902 + {
903 + size = SPAGE_SIZE - (ofs%SPAGE_SIZE);
904 + if(size > len)
905 + size = len;
906 + atmel_flash_read_page(ofs, buffer, size);
907 + buffer+=size;
908 + ofs+=size;
909 + len -= size;
910 + }
911 +
912 +#if 0
913 + buffer = (__u8 *)buf;
914 + for(i=0; i<length; i+=16)
915 + {
916 + for(j=0; j<16; j++,buffer++)
917 + {
918 + if((i*16+j)<length)
919 + printk("%x ",(int)*buffer);
920 + }
921 + printk("\n");
922 + }
923 +
924 + printk("\n");
925 +#endif
926 +
927 +}
928 +
929 +
930 +void sl2312_copy_to(struct map_info *map, unsigned long ofs, void *buf, ssize_t len)
931 +{
932 + __u32 size;
933 + __u8 *buffer;
934 +
935 + buffer = (__u8 *)buf;
936 + //printk("sl2312_copy_to:offset %x len %x \n", ofs, len);
937 +// printk("sl2312_copy_to:buf is %x \n", (int)buf);
938 +
939 + while(len)
940 + {
941 + size = SPAGE_SIZE - (ofs%SPAGE_SIZE);
942 + if(size > len)
943 + size = len;
944 + atmel_flash_program_page(ofs, buffer, size);
945 + buffer+=size;
946 + ofs+=size;
947 + len-=size;
948 + }
949 +
950 +
951 +}
952 +
953 +
954 +static struct mtd_info *serial_mtd;
955 +
956 +static struct mtd_partition *parsed_parts;
957 +
958 +static struct map_info sl2312_serial_map = {
959 +// name: "SL2312 serial flash",
960 +// size: 4194304, //0x400000,
961 +// //buswidth: 4,
962 +// bankwidth: 4,
963 +// phys: SL2312_FLASH_BASE,
964 +//#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
965 +// //read32: sl2312_read32,
966 +// //read8: sl2312_read8,
967 +// copy_from: sl2312_copy_from,
968 +// //write8: sl2312_write8,
969 +// //write32: sl2312_write32,
970 +// read: sl2312_read32,
971 +// write: sl2312_write32,
972 +// copy_to: sl2312_copy_to
973 +//#endif
974 + .name = "SL2312 serial flash",
975 + .size = 4194304, //0x400000,
976 + //buswidth: 4,
977 + .bankwidth = 4,
978 + .phys = SL2312_FLASH_BASE,
979 +#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
980 + //read32: sl2312_read32,
981 + //read8: sl2312_read8,
982 + .copy_from = sl2312_copy_from,
983 + //write8: sl2312_write8,
984 + //write32: sl2312_write32,
985 + .read = sl2312_read32,
986 + .write = sl2312_write32,
987 + .copy_to = sl2312_copy_to
988 +#endif
989 +};
990 +
991 +
992 +
993 +static struct mtd_partition sl2312_partitions[] = {
994 +
995 +
996 + ///* boot code */
997 + //{ name: "bootloader", offset: 0x00000000, size: 0x20000, },
998 + ///* kernel image */
999 + //{ name: "kerel image", offset: 0x000020000, size: 0x2E0000 },
1000 + ///* All else is writable (e.g. JFFS) */
1001 + //{ name: "user data", offset: 0x00300000, size: 0x00100000, },
1002 + /* boot code */
1003 + { .name = "bootloader", .offset = 0x00000000, .size = 0x20000, },
1004 + /* kernel image */
1005 + { .name = "kerel image", .offset = 0x000020000, .size = 0xE0000 },
1006 + /* All else is writable (e.g. JFFS) */
1007 + { .name = "user data", .offset = 0x00100000, .size = 0x00300000, },
1008 +
1009 +
1010 +};
1011 +
1012 +
1013 +
1014 +static int __init init_sl2312_maps(void)
1015 +{
1016 + int nr_parts = 0;
1017 + struct mtd_partition *parts;
1018 +
1019 + serial_mtd = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
1020 + if (!serial_mtd)
1021 + return NULL;
1022 +
1023 + memset(serial_mtd, 0, sizeof(struct mtd_info));
1024 + //sl2312flash_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
1025 + //sl2312_serial_map.map_priv_1 = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)FLASH_VBASE;
1026 + sl2312_serial_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)ioremap(FLASH_START, SFLASH_SIZE);
1027 + if (!sl2312_serial_map.virt) {
1028 + printk(" failed to ioremap \n");
1029 + return -EIO;
1030 + }
1031 + serial_mtd = do_map_probe("map_serial", &sl2312_serial_map);
1032 + if (serial_mtd) {
1033 + //serial_mtd->module = THIS_MODULE;
1034 + serial_mtd->owner = THIS_MODULE;
1035 +
1036 + }
1037 +
1038 +#ifdef CONFIG_MTD_REDBOOT_PARTS
1039 + nr_parts = parse_redboot_partitions(serial_mtd, &parsed_parts);
1040 + if (nr_parts > 0)
1041 + printk(KERN_NOTICE "Found RedBoot partition table.\n");
1042 + else if (nr_parts < 0)
1043 + printk(KERN_NOTICE "Error looking for RedBoot partitions.\n");
1044 +#else
1045 + parsed_parts = sl2312_partitions;
1046 + parts = sl2312_partitions;
1047 + nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
1048 + nr_parts = sizeof(sl2312_partitions)/sizeof(*parsed_parts);
1049 +#endif /* CONFIG_MTD_REDBOOT_PARTS */
1050 +
1051 + if (nr_parts > 0)
1052 + add_mtd_partitions(serial_mtd, parsed_parts, nr_parts);
1053 + else
1054 + add_mtd_device(serial_mtd);
1055 +
1056 + return 0;
1057 +}
1058 +
1059 +static void __exit cleanup_sl2312_maps(void)
1060 +{
1061 + if (parsed_parts)
1062 + del_mtd_partitions(serial_mtd);
1063 + else
1064 + del_mtd_device(serial_mtd);
1065 +
1066 + map_destroy(serial_mtd);
1067 +
1068 +
1069 +}
1070 +
1071 +module_init(init_sl2312_maps);
1072 +module_exit(cleanup_sl2312_maps);
1073 +
1074 +
1075 +
1076 +MODULE_LICENSE("GPL");
1077 +MODULE_AUTHOR("Plus Chen <plus@storlink.com.tw>");
1078 +MODULE_DESCRIPTION("MTD map driver for Storlink Sword boards");
1079 +
1080 Index: linux-2.6.23.16/drivers/mtd/maps/sl2312-flash-cfi.c
1081 ===================================================================
1082 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1083 +++ linux-2.6.23.16/drivers/mtd/maps/sl2312-flash-cfi.c 2008-03-15 17:04:09.377756409 +0200
1084 @@ -0,0 +1,370 @@
1085 +/*======================================================================
1086 +
1087 + This program is free software; you can redistribute it and/or modify
1088 + it under the terms of the GNU General Public License as published by
1089 + the Free Software Foundation; either version 2 of the License, or
1090 + (at your option) any later version.
1091 +
1092 + This program is distributed in the hope that it will be useful,
1093 + but WITHOUT ANY WARRANTY; without even the implied warranty of
1094 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1095 + GNU General Public License for more details.
1096 +
1097 + You should have received a copy of the GNU General Public License
1098 + along with this program; if not, write to the Free Software
1099 + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1100 +======================================================================*/
1101 +
1102 +#include <linux/module.h>
1103 +#include <linux/types.h>
1104 +#include <linux/kernel.h>
1105 +#include <linux/slab.h>
1106 +#include <linux/ioport.h>
1107 +#include <linux/init.h>
1108 +#include <linux/string.h>
1109 +
1110 +#include <linux/mtd/mtd.h>
1111 +#include <linux/mtd/map.h>
1112 +#include <linux/mtd/partitions.h>
1113 +
1114 +#include <asm/hardware.h>
1115 +#include <asm/io.h>
1116 +#include <asm/system.h>
1117 +#include <asm/arch/sl2312.h>
1118 +#include <linux/mtd/kvctl.h>
1119 +#include "sl2312_flashmap.h"
1120 +
1121 +
1122 +//extern int parse_afs_partitions(struct mtd_info *, struct mtd_partition **);
1123 +
1124 +/* the base address of FLASH control register */
1125 +#define FLASH_CONTROL_BASE_ADDR (IO_ADDRESS(SL2312_FLASH_CTRL_BASE))
1126 +#define SL2312_GLOBAL_BASE_ADDR (IO_ADDRESS(SL2312_GLOBAL_BASE))
1127 +
1128 +/* define read/write register utility */
1129 +#define FLASH_READ_REG(offset) (__raw_readl(offset+FLASH_CONTROL_BASE_ADDR))
1130 +#define FLASH_WRITE_REG(offset,val) (__raw_writel(val,offset+FLASH_CONTROL_BASE_ADDR))
1131 +
1132 +/* the offset of FLASH control register */
1133 +enum EMAC_REGISTER {
1134 + FLASH_ID = 0x0000,
1135 + FLASH_STATUS = 0x0008,
1136 + FLASH_TYPE = 0x000c,
1137 + FLASH_ACCESS = 0x0020,
1138 + FLASH_ADDRESS = 0x0024,
1139 + FLASH_DATA = 0x0028,
1140 + FLASH_TIMING = 0x002c,
1141 +};
1142 +
1143 +//#define FLASH_BASE FLASH_CONTROL_BASE_ADDR
1144 +//#define FLASH_SIZE 0x00800000 //INTEGRATOR_FLASH_SIZE
1145 +
1146 +//#define FLASH_PART_SIZE 8388608
1147 +
1148 +static unsigned int flash_indirect_access = 0;
1149 +
1150 +#ifdef CONFIG_SL2312_SHARE_PIN
1151 +static unsigned int chip_en = 0x00000000;
1152 +
1153 +void sl2312flash_enable_parallel_flash(void)
1154 +{
1155 + unsigned int reg_val;
1156 +
1157 + reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
1158 + reg_val = reg_val & 0xfffffffd;
1159 + writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
1160 + return;
1161 +}
1162 +
1163 +void sl2312flash_disable_parallel_flash(void)
1164 +{
1165 + unsigned int reg_val;
1166 +
1167 + reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
1168 + reg_val = reg_val | 0x00000002;
1169 + writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
1170 + return;
1171 +}
1172 +#endif
1173 +
1174 +
1175 +static struct map_info sl2312flash_map =
1176 +{
1177 + name: "SL2312 CFI Flash",
1178 + size: FLASH_SIZE,
1179 + bankwidth: 2,
1180 + //bankwidth: 1, //for 8 bits width
1181 + phys: SL2312_FLASH_BASE,
1182 +};
1183 +
1184 +static struct mtd_info *mtd;
1185 +#if 0
1186 +static struct mtd_partition sl2312_partitions[] = {
1187 + /* boot code */
1188 + {
1189 + name: "bootloader",
1190 + offset: 0x00000000,
1191 + size: 0x20000,
1192 +// mask_flags: MTD_WRITEABLE,
1193 + },
1194 + /* kernel image */
1195 + {
1196 + name: "kerel image",
1197 + offset: 0x00020000,
1198 + size: 0x2E0000
1199 + },
1200 + /* All else is writable (e.g. JFFS) */
1201 + {
1202 + name: "user data",
1203 + offset: 0x00300000,
1204 + size: 0x00100000,
1205 + }
1206 +};
1207 +#endif
1208 +
1209 +
1210 +
1211 +static int __init sl2312flash_init(void)
1212 +{
1213 + struct mtd_partition *parts;
1214 + int nr_parts = 0;
1215 + int ret;
1216 +#ifndef CONFIG_SL2312_SHARE_PIN
1217 + unsigned int reg_val;
1218 +#endif
1219 +
1220 + printk("SL2312 MTD Driver Init.......\n");
1221 +
1222 +#ifndef CONFIG_SL2312_SHARE_PIN
1223 + /* enable flash */
1224 + reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
1225 + reg_val = reg_val & 0xfffffffd;
1226 + writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
1227 +#else
1228 + sl2312flash_enable_parallel_flash(); /* enable Parallel FLASH */
1229 +#endif
1230 + FLASH_WRITE_REG(FLASH_ACCESS,0x00004000); /* parallel flash direct access mode */
1231 + ret = FLASH_READ_REG(FLASH_ACCESS);
1232 + if (ret == 0x00004000)
1233 + {
1234 + flash_indirect_access = 0; /* parallel flash direct access */
1235 + }
1236 + else
1237 + {
1238 + flash_indirect_access = 1; /* parallel flash indirect access */
1239 + }
1240 +
1241 + /*
1242 + * Also, the CFI layer automatically works out what size
1243 + * of chips we have, and does the necessary identification
1244 + * for us automatically.
1245 + */
1246 +#ifdef CONFIG_GEMINI_IPI
1247 + sl2312flash_map.virt = FLASH_VBASE;//(unsigned int *)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
1248 +#else
1249 + sl2312flash_map.virt = (unsigned int *)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
1250 +#endif
1251 + //printk("sl2312flash_map.virt = %08x\n",(unsigned int)sl2312flash_map.virt);
1252 +
1253 +// simple_map_init(&sl2312flash_map);
1254 +
1255 + mtd = do_map_probe("cfi_probe", &sl2312flash_map);
1256 + if (!mtd)
1257 + {
1258 +#ifdef CONFIG_SL2312_SHARE_PIN
1259 + sl2312flash_disable_parallel_flash(); /* disable Parallel FLASH */
1260 +#endif
1261 + return -ENXIO;
1262 + }
1263 + mtd->owner = THIS_MODULE;
1264 +// mtd->erase = flash_erase;
1265 +// mtd->read = flash_read;
1266 +// mtd->write = flash_write;
1267 +
1268 + parts = sl2312_partitions;
1269 + nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
1270 + ret = add_mtd_partitions(mtd, parts, nr_parts);
1271 + /*If we got an error, free all resources.*/
1272 + if (ret < 0) {
1273 + del_mtd_partitions(mtd);
1274 + map_destroy(mtd);
1275 + }
1276 +#ifdef CONFIG_SL2312_SHARE_PIN
1277 + sl2312flash_disable_parallel_flash(); /* disable Parallel FLASH */
1278 +#endif
1279 + printk("SL2312 MTD Driver Init Success ......\n");
1280 + return ret;
1281 +}
1282 +
1283 +static void __exit sl2312flash_exit(void)
1284 +{
1285 + if (mtd) {
1286 + del_mtd_partitions(mtd);
1287 + map_destroy(mtd);
1288 + }
1289 +
1290 + if (sl2312flash_map.virt) {
1291 + iounmap((void *)sl2312flash_map.virt);
1292 + sl2312flash_map.virt = 0;
1293 + }
1294 +}
1295 +
1296 +char chrtohex(char c)
1297 +{
1298 + char val;
1299 + if ((c >= '0') && (c <= '9'))
1300 + {
1301 + val = c - '0';
1302 + return val;
1303 + }
1304 + else if ((c >= 'a') && (c <= 'f'))
1305 + {
1306 + val = 10 + (c - 'a');
1307 + return val;
1308 + }
1309 + else if ((c >= 'A') && (c <= 'F'))
1310 + {
1311 + val = 10 + (c - 'A');
1312 + return val;
1313 + }
1314 + printk("<1>Error number\n");
1315 + return 0;
1316 +}
1317 +
1318 +
1319 +int get_vlaninfo(vlaninfo* vlan)
1320 +{
1321 + vctl_mheader head;
1322 + vctl_entry entry;
1323 + struct mtd_info *mymtd=NULL;
1324 + int i, j, loc = 0;
1325 + char *payload=0, *tmp1, *tmp2, tmp3[9];
1326 + size_t retlen;
1327 +
1328 + #ifdef CONFIG_SL2312_SHARE_PIN
1329 + sl2312flash_enable_parallel_flash();
1330 + #endif
1331 + for(i=0;i<MAX_MTD_DEVICES;i++)
1332 + {
1333 + mymtd=get_mtd_device(NULL,i);
1334 + // printk("mymtd->name: %s\n", mymtd->name);
1335 + if(mymtd && !strcmp(mymtd->name,"VCTL"))
1336 + {
1337 + // printk("%s\n", mymtd->name);
1338 + break;
1339 + }
1340 + }
1341 + if( i >= MAX_MTD_DEVICES)
1342 + {
1343 + printk("Can't find version control\n");
1344 + #ifdef CONFIG_SL2312_SHARE_PIN
1345 + sl2312flash_disable_parallel_flash();
1346 + #endif
1347 + return 0;
1348 + }
1349 +
1350 + if (!mymtd | !mymtd->read)
1351 + {
1352 + printk("<1>Can't read Version Configuration\n");
1353 + #ifdef CONFIG_SL2312_SHARE_PIN
1354 + sl2312flash_disable_parallel_flash();
1355 + #endif
1356 + return 0;
1357 + }
1358 +
1359 + mymtd->read(mymtd, 0, VCTL_HEAD_SIZE, &retlen, (u_char*)&head);
1360 + // printk("entry header: %c%c%c%c\n", head.header[0], head.header[1], head.header[2], head.header[3]);
1361 + // printk("entry number: %x\n", head.entry_num);
1362 + if ( strncmp(head.header, "FLFM", 4) )
1363 + {
1364 + printk("VCTL is a erase block\n");
1365 + #ifdef CONFIG_SL2312_SHARE_PIN
1366 + sl2312flash_disable_parallel_flash();
1367 + #endif
1368 + return 0;
1369 + }
1370 + loc += retlen;
1371 + for (i = 0; i < head.entry_num; i++)
1372 + {
1373 + mymtd->read(mymtd, loc, VCTL_ENTRY_LEN, &retlen, (u_char*)&entry);
1374 + // printk("type: %x\n", entry.type);
1375 + // printk("size: %x\n", entry.size);
1376 + strncpy(tmp3, entry.header, 4);
1377 + if (entry.type == VCT_VLAN)
1378 + {
1379 + for (j = 0; j < 6 ; j++)
1380 + {
1381 + vlan[0].mac[j] = 0;
1382 + vlan[1].mac[j] = 0;
1383 + }
1384 + vlan[0].vlanid = 1;
1385 + vlan[1].vlanid = 2;
1386 + vlan[0].vlanmap = 0x7F;
1387 + vlan[1].vlanmap = 0x80;
1388 +
1389 + payload = (char *)kmalloc(entry.size - VCTL_ENTRY_LEN, GFP_KERNEL);
1390 + loc += VCTL_ENTRY_LEN;
1391 + mymtd->read(mymtd, loc, entry.size - VCTL_ENTRY_LEN, &retlen, payload);
1392 + // printk("%s\n", payload);
1393 + tmp1 = strstr(payload, "MAC1:");
1394 + tmp2 = strstr(payload, "MAC2:");
1395 + if(!tmp1||!tmp2){
1396 + kfree(payload);
1397 + #ifdef CONFIG_SL2312_SHARE_PIN
1398 + sl2312flash_disable_parallel_flash();
1399 + #endif
1400 + printk("Error VCTL format!!\n");
1401 + return 0;
1402 + }
1403 + tmp1 += 7;
1404 + tmp2 += 7;
1405 +
1406 +
1407 + for (j = 0; j < 6; j++)
1408 + {
1409 + vlan[0].mac[j] = chrtohex(tmp1[2*j])*16 + chrtohex(tmp1[(2*j)+1]);
1410 + vlan[1].mac[j] = chrtohex(tmp2[2*j])*16 + chrtohex(tmp2[(2*j)+1]);
1411 + }
1412 + tmp1 = strstr(payload, "ID1:");
1413 + tmp2 = strstr(payload, "ID2:");
1414 + tmp1 += 4;
1415 + tmp2 += 4;
1416 + vlan[0].vlanid = tmp1[0] - '0';
1417 + vlan[1].vlanid = tmp2[0] - '0';
1418 + tmp1 = strstr(payload, "MAP1:");
1419 + tmp2 = strstr(payload, "MAP2:");
1420 + tmp1 += 7;
1421 + tmp2 += 7;
1422 + vlan[0].vlanmap = chrtohex(tmp1[0]) * 16 + chrtohex(tmp1[1]);
1423 + vlan[1].vlanmap = chrtohex(tmp2[0]) * 16 + chrtohex(tmp2[1]);
1424 + // printk("Vlan1 id:%x map:%02x mac:%x%x%x%x%x%x\n", vlan[0].vlanid, vlan[0].vlanmap, vlan[0].mac[0], vlan[0].mac[1], vlan[0].mac[2], vlan[0].mac[3], vlan[0].mac[4], vlan[0].mac[5]);
1425 + // printk("Vlan2 id:%x map:%02x mac:%x%x%x%x%x%x\n", vlan[1].vlanid, vlan[1].vlanmap, vlan[1].mac[0], vlan[1].mac[1], vlan[1].mac[2], vlan[1].mac[3], vlan[1].mac[4], vlan[1].mac[5]);
1426 + break;
1427 + }
1428 + loc += entry.size;
1429 + }
1430 + if ( entry.type == VCT_VLAN )
1431 + {
1432 + #ifdef CONFIG_SL2312_SHARE_PIN
1433 + sl2312flash_disable_parallel_flash();
1434 + #endif
1435 + kfree(payload);
1436 + return 1;
1437 + }
1438 + if (i >= head.entry_num)
1439 + printk("Can't find vlan information\n");
1440 + #ifdef CONFIG_SL2312_SHARE_PIN
1441 + sl2312flash_disable_parallel_flash();
1442 + #endif
1443 + return 0;
1444 +}
1445 +
1446 +EXPORT_SYMBOL(get_vlaninfo);
1447 +
1448 +
1449 +module_init(sl2312flash_init);
1450 +module_exit(sl2312flash_exit);
1451 +
1452 +MODULE_AUTHOR("Storlink Ltd");
1453 +MODULE_DESCRIPTION("CFI map driver");
1454 +MODULE_LICENSE("GPL");
1455 Index: linux-2.6.23.16/drivers/mtd/maps/sl2312-flash-m25p80.c
1456 ===================================================================
1457 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1458 +++ linux-2.6.23.16/drivers/mtd/maps/sl2312-flash-m25p80.c 2008-03-15 17:04:15.378098557 +0200
1459 @@ -0,0 +1,498 @@
1460 +/*
1461 + * $Id: sl2312-flash-m25p80.c,v 1.2 2006/06/02 08:46:02 middle Exp $
1462 + *
1463 + * Flash and EPROM on Hitachi Solution Engine and similar boards.
1464 + *
1465 + * (C) 2001 Red Hat, Inc.
1466 + *
1467 + * GPL'd
1468 + */
1469 +
1470 +#include <linux/module.h>
1471 +#include <linux/types.h>
1472 +#include <linux/kernel.h>
1473 +
1474 +#include <asm/io.h>
1475 +#include <linux/mtd/mtd.h>
1476 +#include <linux/mtd/map.h>
1477 +#include <linux/mtd/partitions.h>
1478 +#include <asm/hardware.h>
1479 +
1480 +#include <asm/arch/sl2312.h>
1481 +#include <asm/arch/flash.h>
1482 +#include <linux/init.h> //add
1483 +#define g_chipen SERIAL_FLASH_CHIP0_EN //ST
1484 +
1485 +//static int m25p80_page_program(__u32 address, __u8 data, __u32 schip_en);
1486 +static void m25p80_write_cmd(__u8 cmd, __u32 schip_en);
1487 +extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
1488 +
1489 +
1490 +static __u32 read_flash_ctrl_reg(__u32 ofs)
1491 +{
1492 + __u32 *base;
1493 +
1494 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
1495 + return __raw_readl(base);
1496 +}
1497 +
1498 +static void write_flash_ctrl_reg(__u32 ofs,__u32 data)
1499 +{
1500 + __u32 *base;
1501 +
1502 + base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
1503 + __raw_writel(data, base);
1504 +}
1505 +
1506 +static void m25p80_read(__u32 address, __u8 *data, __u32 schip_en)
1507 +{
1508 + __u32 opcode,status;
1509 + __u32 value;
1510 +
1511 + //opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ;
1512 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | M25P80_READ;
1513 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
1514 +
1515 + opcode|=g_chipen;
1516 +
1517 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1518 + status=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1519 + while(status&0x80000000)
1520 + {
1521 + status=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1522 + flash_delay();
1523 + schedule();
1524 + }
1525 +
1526 + value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1527 + *data = value & 0xff;
1528 +}
1529 +
1530 +static int m25p80_page_program(__u32 address, __u8 *data, __u32 schip_en)
1531 +{
1532 + __u32 opcode;
1533 + __u32 status;
1534 + __u32 tmp;
1535 + int res = FLASH_ERR_OK;
1536 + //volatile FLASH_DATA_T* data_ptr = (volatile FLASH_DATA_T*) data;
1537 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1538 +
1539 + opcode|=g_chipen;
1540 +
1541 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1542 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1543 + while(tmp&0x80000000)
1544 + {
1545 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1546 + flash_delay();
1547 + schedule();
1548 + }
1549 + //middle delay_ms(130);
1550 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1551 + if((status&0x02)==0x02)
1552 + {
1553 + //middle delay_ms(100);
1554 + m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
1555 + }
1556 +
1557 +
1558 + m25p80_write_cmd(M25P80_WRITE_ENABLE, schip_en);
1559 + ////middle delay_ms(10);
1560 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | M25P80_PAGE_PROGRAM;
1561 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
1562 + write_flash_ctrl_reg(FLASH_WRITE_DATA_OFFSET, *data);
1563 +
1564 + //status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1565 + //while(status!=data)
1566 + //{
1567 + // status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1568 + // //middle delay_ms(10);
1569 + //}
1570 +
1571 + opcode|=g_chipen;
1572 +
1573 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1574 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1575 + while(tmp&0x80000000)
1576 + {
1577 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1578 + flash_delay();
1579 + schedule();
1580 + }
1581 + //opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1582 +
1583 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1584 +
1585 + opcode|=g_chipen;
1586 +
1587 +
1588 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1589 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1590 + while(tmp&0x80000000)
1591 + {
1592 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1593 + flash_delay();
1594 + schedule();
1595 + }
1596 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1597 + //while(status&0xfd)
1598 + while(status&0x01)
1599 + {
1600 + //if((status&0x9c)!=0)
1601 + // printf(" m25p80_page_program Protect Status = %x\n",status);
1602 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1603 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1604 + while(tmp&0x80000000)
1605 + {
1606 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1607 + flash_delay();
1608 + schedule();
1609 + }
1610 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1611 + flash_delay();
1612 + schedule();
1613 + //middle delay_ms(50);
1614 + }
1615 + //printf("status = %x, data = %x\n",status,data);
1616 + if((status&0x02)==0x02)
1617 + {
1618 + //middle delay_ms(100);
1619 + m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
1620 + }
1621 + //};//while (len > 0)
1622 + return res;
1623 +}
1624 +
1625 +void m25p80_copy_from(struct map_info *map, void *buf, unsigned long ofs, ssize_t len)
1626 +{
1627 +// __u32 size;
1628 + __u8 *buffer;
1629 + __u32 length;//i, j,
1630 +
1631 + length = len;
1632 + buffer = (__u8 *)buf;
1633 + while(len)
1634 + {
1635 + m25p80_read(ofs, buffer, g_chipen);
1636 + buffer++;
1637 + ofs++;
1638 + len --;
1639 + } ;
1640 +
1641 +}
1642 +
1643 +__u32 m25p80_read32(struct map_info *map, unsigned long ofs)
1644 +{
1645 +
1646 + return read_flash_ctrl_reg(ofs);
1647 +
1648 +
1649 +}
1650 +
1651 +void m25p80_write32(struct map_info *map, __u32 d, unsigned long ofs)
1652 +{
1653 +
1654 + write_flash_ctrl_reg(ofs, d);
1655 +
1656 +}
1657 +
1658 +void m25p80_copy_to(struct map_info *map, unsigned long ofs, void *buf, ssize_t len)
1659 +{
1660 + __u32 size, i, ret;
1661 +
1662 + while(len > 0)
1663 + {
1664 + if(len >= M25P80_PAGE_SIZE)
1665 + size = M25P80_PAGE_SIZE;
1666 + else
1667 + size = len;
1668 +
1669 + for(i=0;i<size;i++)
1670 + {
1671 + ret = m25p80_page_program( (ofs+i), (buf+i), g_chipen);
1672 + }
1673 + buf+=M25P80_PAGE_SIZE;
1674 + ofs+=M25P80_PAGE_SIZE;
1675 + len-=M25P80_PAGE_SIZE;
1676 +
1677 + };
1678 +
1679 +
1680 +}
1681 +
1682 +static struct mtd_info *serial_mtd;
1683 +
1684 +static struct mtd_partition *parsed_parts;
1685 +
1686 +static struct map_info m25p80_map = {
1687 +
1688 + .name = "SL2312 serial flash m25p80",
1689 + .size = 1048576, //0x100000,
1690 + //buswidth: 4,
1691 + .bankwidth = 4,
1692 + .phys = SL2312_FLASH_BASE,
1693 +#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
1694 + .copy_from = m25p80_copy_from,
1695 + .read = m25p80_read32,
1696 + .write = m25p80_write32,
1697 + .copy_to = m25p80_copy_to
1698 +#endif
1699 +};
1700 +
1701 +
1702 +
1703 +static struct mtd_partition m25p80_partitions[] = {
1704 +
1705 + /* boot code */
1706 + { .name = "bootloader", .offset = 0x00000000, .size = 0x20000, },
1707 + /* kernel image */
1708 + { .name = "kerel image", .offset = 0x000020000, .size = 0xC0000 },
1709 + /* All else is writable (e.g. JFFS) */
1710 + { .name = "user data", .offset = 0x000E0000, .size = 0x00010000, },
1711 +
1712 +
1713 +};
1714 +
1715 +void flash_delay()
1716 +{
1717 + int i,j;
1718 + for(i=0;i<0x100;i++)
1719 + j=i*3+5;
1720 +}
1721 +
1722 +int m25p80_sector_erase(__u32 address, __u32 schip_en)
1723 +{
1724 + __u32 opcode;
1725 + __u32 status;
1726 + __u32 tmp;
1727 + int res = FLASH_ERR_OK;
1728 + //printf("\n-->m25p80_sector_erase");
1729 + if(address >= FLASH_START)
1730 + address-=FLASH_START;
1731 +
1732 + m25p80_write_cmd(M25P80_WRITE_ENABLE, schip_en);
1733 + //printf("\n m25p80_sector_erase : after we-en");
1734 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | M25P80_SECTOR_ERASE;
1735 + write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
1736 + #ifdef MIDWAY_DIAG
1737 + opcode|=schip_en;
1738 + #endif
1739 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1740 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1741 + while(tmp&0x80000000)
1742 + {
1743 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1744 + flash_delay();
1745 + schedule();
1746 + }
1747 +
1748 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1749 + #ifdef MIDWAY_DIAG
1750 + opcode|=schip_en;
1751 + #endif
1752 +
1753 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1754 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1755 + while(tmp&0x80000000)
1756 + {
1757 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1758 + flash_delay();
1759 + schedule();
1760 + }
1761 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1762 + //while(status&0xfd)
1763 + while(status&0x01)
1764 + {
1765 + //if((status&0x9c)!=0)
1766 + // printf(" m25p80_sector_erase Protect Status = %x\n",status);
1767 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1768 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1769 + while(tmp&0x80000000)
1770 + {
1771 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1772 + flash_delay();
1773 + schedule();
1774 + }
1775 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1776 + flash_delay();
1777 + schedule();
1778 + //middle delay_ms(50);
1779 + }
1780 + if((status&0x02)==0x02)
1781 + {
1782 + //middle delay_ms(100);
1783 + m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
1784 + }
1785 + //printf("\n<--m25p80_sector_erase");
1786 + return res;
1787 +}
1788 +
1789 +static void m25p80_write_cmd(__u8 cmd, __u32 schip_en)
1790 +{
1791 + __u32 opcode,tmp;
1792 + __u32 status;
1793 +
1794 +
1795 +
1796 +
1797 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE | cmd;
1798 +
1799 + opcode|=g_chipen;
1800 +
1801 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1802 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1803 + while(tmp&0x80000000)
1804 + {
1805 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1806 + flash_delay();
1807 + schedule();
1808 + }
1809 + //////
1810 + opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1811 +
1812 + opcode|=g_chipen;
1813 +
1814 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1815 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1816 + while(tmp&0x80000000)
1817 + {
1818 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1819 + flash_delay();
1820 + schedule();
1821 + }
1822 + //middle delay_ms(130);
1823 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1824 + //printf("\ncmd =%x status = %x",cmd,status);
1825 + if(cmd==M25P80_WRITE_ENABLE)
1826 + {
1827 + //printf("\n**-->enable** status = %x",status);
1828 + //middle delay_ms(100);
1829 + while((status&0x03) != 2)
1830 + {
1831 + //if((status&0x9c)!=0)
1832 + // printf(" M25P80_WRITE_ENABLE Protect Status = %x\n",status);
1833 +
1834 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1835 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1836 + while(tmp&0x80000000)
1837 + {
1838 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1839 + //flash_delay();
1840 + }
1841 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1842 + //printf("\n**enable** status = %x",status);
1843 + flash_delay();
1844 + schedule();
1845 + //middle delay_ms(100);
1846 + }
1847 + }
1848 + else if(cmd==M25P80_WRITE_DISABLE)
1849 + {
1850 + //while((status&0x03) == 2)
1851 + // printf("\n**disable** status = %x",status);
1852 + //middle delay_ms(100);
1853 + while((status&0x03) != 0)
1854 + {
1855 + //m25p80_write_status((status&0xfd),schip_en);
1856 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1857 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1858 + while(tmp&0x80000000)
1859 + {
1860 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1861 + flash_delay();
1862 + schedule();
1863 + }
1864 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1865 + //printf("\n**disable** status = %x",status);
1866 + flash_delay();
1867 + schedule();
1868 + //middle delay_ms(50);
1869 + }
1870 + }
1871 + else
1872 + {
1873 + //while((status&0x01) !=0)
1874 + while((status&0x01) !=0)
1875 + {
1876 + write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1877 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1878 + while(tmp&0x80000000)
1879 + {
1880 + tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1881 + flash_delay();
1882 + schedule();
1883 + }
1884 + status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1885 + flash_delay();
1886 + schedule();
1887 + //middle delay_ms(50);
1888 + }
1889 + }
1890 + //////
1891 +
1892 + //printf("\n<-- status = %x",status);
1893 +}
1894 +
1895 +static int __init init_sl2312_m25p80(void)
1896 +{
1897 + int nr_parts = 0;
1898 + struct mtd_partition *parts;
1899 +
1900 + serial_mtd = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
1901 + if (!serial_mtd)
1902 + return NULL;
1903 +
1904 + memset(serial_mtd, 0, sizeof(struct mtd_info));
1905 + m25p80_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)ioremap(FLASH_START, SFLASH_SIZE);
1906 + if (!m25p80_map.virt) {
1907 + printk(" failed to ioremap \n");
1908 + return -EIO;
1909 + }
1910 + serial_mtd = do_map_probe("map_serial", &m25p80_map);
1911 + if (serial_mtd) {
1912 + serial_mtd->owner = THIS_MODULE;
1913 +
1914 + }
1915 +
1916 +#ifdef CONFIG_MTD_REDBOOT_PARTS
1917 + nr_parts = parse_redboot_partitions(serial_mtd, &parsed_parts);
1918 + if (nr_parts > 0)
1919 + printk(KERN_NOTICE "Found RedBoot partition table.\n");
1920 + else if (nr_parts < 0)
1921 + printk(KERN_NOTICE "Error looking for RedBoot partitions.\n");
1922 +#else
1923 + parsed_parts = m25p80_partitions;
1924 + parts = m25p80_partitions;
1925 + nr_parts = sizeof(m25p80_partitions)/sizeof(*parts);
1926 + nr_parts = sizeof(m25p80_partitions)/sizeof(*parsed_parts);
1927 +#endif /* CONFIG_MTD_REDBOOT_PARTS */
1928 +
1929 + if (nr_parts > 0)
1930 + add_mtd_partitions(serial_mtd, parsed_parts, nr_parts);
1931 + else
1932 + add_mtd_device(serial_mtd);
1933 +
1934 + return 0;
1935 +}
1936 +
1937 +static void __exit cleanup_sl2312_m25p80(void)
1938 +{
1939 + if (parsed_parts)
1940 + del_mtd_partitions(serial_mtd);
1941 + else
1942 + del_mtd_device(serial_mtd);
1943 +
1944 + map_destroy(serial_mtd);
1945 +
1946 +
1947 +}
1948 +
1949 +module_init(init_sl2312_m25p80);
1950 +module_exit(cleanup_sl2312_m25p80);
1951 +
1952 +
1953 +
1954 +MODULE_LICENSE("GPL");
1955 +MODULE_AUTHOR("Plus Chen <plus@storlink.com.tw>");
1956 +MODULE_DESCRIPTION("MTD map driver for Storlink Sword boards");
1957 +
1958 Index: linux-2.6.23.16/drivers/mtd/maps/sl2312_flashmap.h
1959 ===================================================================
1960 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1961 +++ linux-2.6.23.16/drivers/mtd/maps/sl2312_flashmap.h 2008-03-15 17:03:17.874821522 +0200
1962 @@ -0,0 +1,21 @@
1963 +/*
1964 + * Please note that the name are used in mkflash script. Therefore
1965 + * don't change them. If you want to add different partitions, you
1966 + * will need to modify mkflash script as well so that the end image
1967 + * is what you include here!
1968 + *
1969 + * Also, the 7th item is always the size, so please don't add extra
1970 + * spaces in the name or other items.
1971 + *
1972 + * - Alan
1973 + */
1974 +
1975 +static struct mtd_partition sl2312_partitions[] = {
1976 + { name: "RedBoot", offset: 0x00000000, size: 0x00020000, },
1977 + { name: "Kernel", offset: 0x00020000, size: 0x00100000, },
1978 + { name: "Ramdisk", offset: 0x00120000, size: 0x00500000, },
1979 + { name: "etc", offset: 0x00620000, size: 0x001A0000, },
1980 + { name: "VCTL", offset: 0x007C0000, size: 0x00010000, },
1981 + { name: "cfg", offset: 0x007D0000, size: 0x00020000, },
1982 + { name: "FIS directory", offset: 0x007F0000, size: 0x00010000, }
1983 +};
1984 Index: linux-2.6.23.16/drivers/mtd/maps/sl2312_flashmap.h.16MB
1985 ===================================================================
1986 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1987 +++ linux-2.6.23.16/drivers/mtd/maps/sl2312_flashmap.h.16MB 2008-03-15 17:03:17.874821522 +0200
1988 @@ -0,0 +1,21 @@
1989 +/*
1990 + * Please note that the name are used in mkflash script. Therefore
1991 + * don't change them. If you want to add different partitions, you
1992 + * will need to modify mkflash script as well so that the end image
1993 + * is what you include here!
1994 + *
1995 + * Also, the 7th item is always the size, so please don't add extra
1996 + * spaces in the name or other items.
1997 + *
1998 + * - Alan
1999 + */
2000 +
2001 +static struct mtd_partition sl2312_partitions[] = {
2002 + { name: "RedBoot", offset: 0x00000000, size: 0x00020000, },
2003 + { name: "Kernel", offset: 0x00020000, size: 0x00300000, },
2004 + { name: "Ramdisk", offset: 0x00320000, size: 0x00600000, },
2005 + { name: "Application", offset: 0x00920000, size: 0x00600000, },
2006 + { name: "VCTL", offset: 0x00F20000, size: 0x00020000, },
2007 + { name: "CurConf", offset: 0x00F40000, size: 0x000A0000, },
2008 + { name: "FIS directory", offset: 0x00FE0000, size: 0x00020000, }
2009 +};
2010 Index: linux-2.6.23.16/drivers/mtd/maps/sl2312_flashmap.h.8MB
2011 ===================================================================
2012 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2013 +++ linux-2.6.23.16/drivers/mtd/maps/sl2312_flashmap.h.8MB 2008-03-15 17:03:17.874821522 +0200
2014 @@ -0,0 +1,21 @@
2015 +/*
2016 + * Please note that the name are used in mkflash script. Therefore
2017 + * don't change them. If you want to add different partitions, you
2018 + * will need to modify mkflash script as well so that the end image
2019 + * is what you include here!
2020 + *
2021 + * Also, the 7th item is always the size, so please don't add extra
2022 + * spaces in the name or other items.
2023 + *
2024 + * - Alan
2025 + */
2026 +
2027 +static struct mtd_partition sl2312_partitions[] = {
2028 + { name: "RedBoot", offset: 0x00000000, size: 0x00020000, },
2029 + { name: "Kernel", offset: 0x00020000, size: 0x00200000, },
2030 + { name: "Ramdisk", offset: 0x00220000, size: 0x00280000, },
2031 + { name: "Application", offset: 0x004A0000, size: 0x00300000, },
2032 + { name: "VCTL", offset: 0x007A0000, size: 0x00020000, },
2033 + { name: "CurConf", offset: 0x007C0000, size: 0x00020000, },
2034 + { name: "FIS directory", offset: 0x007E0000, size: 0x00020000, }
2035 +};
2036 Index: linux-2.6.23.16/drivers/mtd/mtdchar.c
2037 ===================================================================
2038 --- linux-2.6.23.16.orig/drivers/mtd/mtdchar.c 2008-03-15 17:03:14.374622039 +0200
2039 +++ linux-2.6.23.16/drivers/mtd/mtdchar.c 2008-03-15 17:03:17.874821522 +0200
2040 @@ -59,6 +59,77 @@
2041 enum mtd_file_modes mode;
2042 };
2043
2044 +/***********************************************************************
2045 +/* Storlink SoC -- flash
2046 +/***********************************************************************/
2047 +#ifdef CONFIG_SL2312_SHARE_PIN
2048 +unsigned int share_pin_flag=0; // bit0:FLASH, bit1:UART, bit2:EMAC, bit3-4:IDE
2049 +unsigned int check_sleep_flag=0; // bit0:FLASH, bit1:IDE
2050 +static spinlock_t sl2312_flash_lock = SPIN_LOCK_UNLOCKED;
2051 +EXPORT_SYMBOL(share_pin_flag);
2052 +int dbg=0;
2053 +DECLARE_WAIT_QUEUE_HEAD(wq);
2054 +extern struct wait_queue_head_t *flash_wait;
2055 +unsigned int flash_req=0;
2056 +void mtd_lock()
2057 +{
2058 + struct task_struct *tsk = current;
2059 + unsigned int value ;
2060 + unsigned long flags;
2061 + flash_req = 1;
2062 + DECLARE_WAITQUEUE(wait, tsk);
2063 + add_wait_queue(&wq, &wait);
2064 + for(;;)
2065 + {
2066 + set_task_state(tsk, TASK_INTERRUPTIBLE);
2067 + spin_lock_irqsave(&sl2312_flash_lock,flags);
2068 + if((share_pin_flag&0x1E)){//||(check_sleep_flag&0x00000002)) {
2069 + spin_unlock_irqrestore(&sl2312_flash_lock, flags);
2070 + check_sleep_flag |= 0x00000001;
2071 + if(dbg)
2072 + printk("mtd yield %x %x\n",share_pin_flag,check_sleep_flag);
2073 + wake_up_interruptible(&flash_wait);
2074 + schedule();
2075 + }
2076 + else {
2077 + check_sleep_flag &= ~0x01;
2078 + share_pin_flag |= 0x00000001 ; // set share pin flag
2079 + spin_unlock_irqrestore(&sl2312_flash_lock, flags);
2080 + value = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2081 + value = value & (~PFLASH_SHARE_BIT) ;
2082 + writel(value,IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2083 + if(dbg)
2084 + printk("mtd Go %x %x\n",share_pin_flag,check_sleep_flag);
2085 + tsk->state = TASK_RUNNING;
2086 + remove_wait_queue(&wq, &wait);
2087 + return ;
2088 + }
2089 + }
2090 +}
2091 +
2092 +void mtd_unlock()
2093 +{
2094 + unsigned int value ;
2095 + unsigned long flags;
2096 +
2097 + spin_lock_irqsave(&sl2312_flash_lock,flags); // Disable IRQ
2098 + value = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2099 + value = value | PFLASH_SHARE_BIT ; // Disable Flash PADs
2100 + writel(value,IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2101 + share_pin_flag &= ~(0x00000001); // clear share pin flag
2102 + check_sleep_flag &= ~0x00000001;
2103 + spin_unlock_irqrestore(&sl2312_flash_lock, flags); // Restore IRQ
2104 + if (check_sleep_flag & 0x00000002)
2105 + {
2106 + check_sleep_flag &= ~(0x00000002);
2107 + wake_up_interruptible(&flash_wait);
2108 + }
2109 + DEBUG(MTD_DEBUG_LEVEL0, "Flash Unlock...\n");
2110 + flash_req = 0;
2111 +}
2112 +#endif
2113 +/***********************************************************************/
2114 +
2115 static loff_t mtd_lseek (struct file *file, loff_t offset, int orig)
2116 {
2117 struct mtd_file_info *mfi = file->private_data;
2118 @@ -162,13 +233,21 @@
2119 int len;
2120 char *kbuf;
2121
2122 +#ifdef CONFIG_SL2312_SHARE_PIN
2123 + mtd_lock(); // sl2312 share pin lock
2124 +#endif
2125 +
2126 DEBUG(MTD_DEBUG_LEVEL0,"MTD_read\n");
2127
2128 if (*ppos + count > mtd->size)
2129 count = mtd->size - *ppos;
2130
2131 - if (!count)
2132 + if (!count){
2133 +#ifdef CONFIG_SL2312_SHARE_PIN
2134 + mtd_unlock(); // sl2312 share pin lock
2135 +#endif
2136 return 0;
2137 + }
2138
2139 /* FIXME: Use kiovec in 2.5 to lock down the user's buffers
2140 and pass them directly to the MTD functions */
2141 @@ -178,8 +257,12 @@
2142 else
2143 kbuf=kmalloc(count, GFP_KERNEL);
2144
2145 - if (!kbuf)
2146 + if (!kbuf) {
2147 +#ifdef CONFIG_SL2312_SHARE_PIN
2148 + mtd_unlock(); // sl2312 share pin lock
2149 +#endif
2150 return -ENOMEM;
2151 + }
2152
2153 while (count) {
2154
2155 @@ -224,6 +307,9 @@
2156 *ppos += retlen;
2157 if (copy_to_user(buf, kbuf, retlen)) {
2158 kfree(kbuf);
2159 +#ifdef CONFIG_SL2312_SHARE_PIN
2160 + mtd_unlock(); // sl2312 share pin lock
2161 +#endif
2162 return -EFAULT;
2163 }
2164 else
2165 @@ -235,13 +321,19 @@
2166 count = 0;
2167 }
2168 else {
2169 - kfree(kbuf);
2170 + kfree(kbuf);
2171 +#ifdef CONFIG_SL2312_SHARE_PIN
2172 + mtd_unlock(); // sl2312 share pin lock
2173 +#endif
2174 return ret;
2175 }
2176
2177 }
2178
2179 kfree(kbuf);
2180 +#ifdef CONFIG_SL2312_SHARE_PIN
2181 + mtd_unlock(); // sl2312 share pin lock
2182 +#endif
2183 return total_retlen;
2184 } /* mtd_read */
2185
2186 @@ -255,24 +347,40 @@
2187 int ret=0;
2188 int len;
2189
2190 +#ifdef CONFIG_SL2312_SHARE_PIN
2191 + mtd_lock(); // sl2312 share pin lock
2192 +#endif
2193 +
2194 DEBUG(MTD_DEBUG_LEVEL0,"MTD_write\n");
2195
2196 - if (*ppos == mtd->size)
2197 + if (*ppos == mtd->size){
2198 +#ifdef CONFIG_SL2312_SHARE_PIN
2199 + mtd_unlock(); // sl2312 share pin lock
2200 +#endif
2201 return -ENOSPC;
2202 + }
2203
2204 if (*ppos + count > mtd->size)
2205 count = mtd->size - *ppos;
2206
2207 - if (!count)
2208 + if (!count){
2209 +#ifdef CONFIG_SL2312_SHARE_PIN
2210 + mtd_unlock(); // sl2312 share pin lock
2211 +#endif
2212 return 0;
2213 + }
2214
2215 if (count > MAX_KMALLOC_SIZE)
2216 kbuf=kmalloc(MAX_KMALLOC_SIZE, GFP_KERNEL);
2217 else
2218 kbuf=kmalloc(count, GFP_KERNEL);
2219
2220 - if (!kbuf)
2221 + if (!kbuf) {
2222 +#ifdef CONFIG_SL2312_SHARE_PIN
2223 + mtd_unlock(); // sl2312 share pin lock
2224 +#endif
2225 return -ENOMEM;
2226 + }
2227
2228 while (count) {
2229
2230 @@ -283,6 +391,9 @@
2231
2232 if (copy_from_user(kbuf, buf, len)) {
2233 kfree(kbuf);
2234 +#ifdef CONFIG_SL2312_SHARE_PIN
2235 + mtd_unlock(); // sl2312 share pin lock
2236 +#endif
2237 return -EFAULT;
2238 }
2239
2240 @@ -323,11 +434,17 @@
2241 }
2242 else {
2243 kfree(kbuf);
2244 +#ifdef CONFIG_SL2312_SHARE_PIN
2245 + mtd_unlock(); // sl2312 share pin lock
2246 +#endif
2247 return ret;
2248 }
2249 }
2250
2251 kfree(kbuf);
2252 +#ifdef CONFIG_SL2312_SHARE_PIN
2253 + mtd_unlock(); // sl2312 share pin lock
2254 +#endif
2255 return total_retlen;
2256 } /* mtd_write */
2257
2258 @@ -381,36 +498,67 @@
2259 u_long size;
2260 struct mtd_info_user info;
2261
2262 +#ifdef CONFIG_SL2312_SHARE_PIN
2263 + mtd_lock(); // sl2312 share pin lock
2264 +#endif
2265 +
2266 DEBUG(MTD_DEBUG_LEVEL0, "MTD_ioctl\n");
2267
2268 size = (cmd & IOCSIZE_MASK) >> IOCSIZE_SHIFT;
2269 if (cmd & IOC_IN) {
2270 if (!access_ok(VERIFY_READ, argp, size))
2271 + {
2272 +#ifdef CONFIG_SL2312_SHARE_PIN
2273 + mtd_unlock(); // sl2312 share pin lock
2274 +#endif
2275 return -EFAULT;
2276 + }
2277 }
2278 if (cmd & IOC_OUT) {
2279 if (!access_ok(VERIFY_WRITE, argp, size))
2280 + {
2281 +#ifdef CONFIG_SL2312_SHARE_PIN
2282 + mtd_unlock(); // sl2312 share pin lock
2283 +#endif
2284 return -EFAULT;
2285 + }
2286 }
2287
2288 switch (cmd) {
2289 case MEMGETREGIONCOUNT:
2290 if (copy_to_user(argp, &(mtd->numeraseregions), sizeof(int)))
2291 + {
2292 +#ifdef CONFIG_SL2312_SHARE_PIN
2293 + mtd_unlock(); // sl2312 share pin lock
2294 +#endif
2295 return -EFAULT;
2296 + }
2297 break;
2298
2299 case MEMGETREGIONINFO:
2300 {
2301 struct region_info_user ur;
2302
2303 - if (copy_from_user(&ur, argp, sizeof(struct region_info_user)))
2304 + if (copy_from_user(&ur, argp, sizeof(struct region_info_user))) {
2305 +#ifdef CONFIG_SL2312_SHARE_PIN
2306 + mtd_unlock(); // sl2312 share pin lock
2307 +#endif
2308 return -EFAULT;
2309 + }
2310
2311 - if (ur.regionindex >= mtd->numeraseregions)
2312 + if (ur.regionindex >= mtd->numeraseregions) {
2313 +#ifdef CONFIG_SL2312_SHARE_PIN
2314 + mtd_unlock(); // sl2312 share pin lock
2315 +#endif
2316 return -EINVAL;
2317 + }
2318 if (copy_to_user(argp, &(mtd->eraseregions[ur.regionindex]),
2319 - sizeof(struct mtd_erase_region_info)))
2320 + sizeof(struct mtd_erase_region_info))) {
2321 +#ifdef CONFIG_SL2312_SHARE_PIN
2322 + mtd_unlock(); // sl2312 share pin lock
2323 +#endif
2324 return -EFAULT;
2325 + }
2326 break;
2327 }
2328
2329 @@ -433,7 +581,12 @@
2330 struct erase_info *erase;
2331
2332 if(!(file->f_mode & 2))
2333 + {
2334 +#ifdef CONFIG_SL2312_SHARE_PIN
2335 + mtd_unlock(); // sl2312 share pin lock
2336 +#endif
2337 return -EPERM;
2338 + }
2339
2340 erase=kzalloc(sizeof(struct erase_info),GFP_KERNEL);
2341 if (!erase)
2342 @@ -447,6 +600,9 @@
2343 if (copy_from_user(&erase->addr, argp,
2344 sizeof(struct erase_info_user))) {
2345 kfree(erase);
2346 +#ifdef CONFIG_SL2312_SHARE_PIN
2347 + mtd_unlock(); // sl2312 share pin lock
2348 +#endif
2349 return -EFAULT;
2350 }
2351 erase->mtd = mtd;
2352 @@ -484,14 +640,26 @@
2353 struct mtd_oob_buf buf;
2354 struct mtd_oob_ops ops;
2355
2356 - if(!(file->f_mode & 2))
2357 + if(!(file->f_mode & 2)) {
2358 +#ifdef CONFIG_SL2312_SHARE_PIN
2359 + mtd_unlock(); // sl2312 share pin lock
2360 +#endif
2361 return -EPERM;
2362 + }
2363
2364 - if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf)))
2365 + if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf))) {
2366 +#ifdef CONFIG_SL2312_SHARE_PIN
2367 + mtd_unlock(); // sl2312 share pin lock
2368 +#endif
2369 return -EFAULT;
2370 + }
2371
2372 - if (buf.length > 4096)
2373 + if (buf.length > 4096) {
2374 +#ifdef CONFIG_SL2312_SHARE_PIN
2375 + mtd_unlock(); // sl2312 share pin lock
2376 +#endif
2377 return -EINVAL;
2378 + }
2379
2380 if (!mtd->write_oob)
2381 ret = -EOPNOTSUPP;
2382 @@ -499,8 +667,12 @@
2383 ret = access_ok(VERIFY_READ, buf.ptr,
2384 buf.length) ? 0 : EFAULT;
2385
2386 - if (ret)
2387 + if (ret) {
2388 +#ifdef CONFIG_SL2312_SHARE_PIN
2389 + mtd_unlock(); // sl2312 share pin lock
2390 +#endif
2391 return ret;
2392 + }
2393
2394 ops.ooblen = buf.length;
2395 ops.ooboffs = buf.start & (mtd->oobsize - 1);
2396 @@ -536,19 +708,35 @@
2397 struct mtd_oob_buf buf;
2398 struct mtd_oob_ops ops;
2399
2400 - if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf)))
2401 + if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf))) {
2402 +#ifdef CONFIG_SL2312_SHARE_PIN
2403 + mtd_unlock(); // sl2312 share pin lock
2404 +#endif
2405 return -EFAULT;
2406 + }
2407
2408 - if (buf.length > 4096)
2409 + if (buf.length > 4096) {
2410 +#ifdef CONFIG_SL2312_SHARE_PIN
2411 + mtd_unlock(); // sl2312 share pin lock
2412 +#endif
2413 return -EINVAL;
2414 + }
2415
2416 - if (!mtd->read_oob)
2417 + if (!mtd->read_oob) {
2418 +#ifdef CONFIG_SL2312_SHARE_PIN
2419 + mtd_unlock(); // sl2312 share pin lock
2420 +#endif
2421 ret = -EOPNOTSUPP;
2422 + }
2423 else
2424 ret = access_ok(VERIFY_WRITE, buf.ptr,
2425 buf.length) ? 0 : -EFAULT;
2426 - if (ret)
2427 + if (ret) {
2428 +#ifdef CONFIG_SL2312_SHARE_PIN
2429 + mtd_unlock(); // sl2312 share pin lock
2430 +#endif
2431 return ret;
2432 + }
2433
2434 ops.ooblen = buf.length;
2435 ops.ooboffs = buf.start & (mtd->oobsize - 1);
2436 @@ -580,7 +768,12 @@
2437 struct erase_info_user info;
2438
2439 if (copy_from_user(&info, argp, sizeof(info)))
2440 + {
2441 +#ifdef CONFIG_SL2312_SHARE_PIN
2442 + mtd_unlock(); // sl2312 share pin lock
2443 +#endif
2444 return -EFAULT;
2445 + }
2446
2447 if (!mtd->lock)
2448 ret = -EOPNOTSUPP;
2449 @@ -594,7 +787,12 @@
2450 struct erase_info_user info;
2451
2452 if (copy_from_user(&info, argp, sizeof(info)))
2453 + {
2454 +#ifdef CONFIG_SL2312_SHARE_PIN
2455 + mtd_unlock(); // sl2312 share pin lock
2456 +#endif
2457 return -EFAULT;
2458 + }
2459
2460 if (!mtd->unlock)
2461 ret = -EOPNOTSUPP;
2462 @@ -629,11 +827,21 @@
2463 loff_t offs;
2464
2465 if (copy_from_user(&offs, argp, sizeof(loff_t)))
2466 + {
2467 +#ifdef CONFIG_SL2312_SHARE_PIN
2468 + mtd_unlock(); // sl2312 share pin lock
2469 +#endif
2470 return -EFAULT;
2471 + }
2472 if (!mtd->block_isbad)
2473 ret = -EOPNOTSUPP;
2474 else
2475 + {
2476 +#ifdef CONFIG_SL2312_SHARE_PIN
2477 + mtd_unlock(); // sl2312 share pin lock
2478 +#endif
2479 return mtd->block_isbad(mtd, offs);
2480 + }
2481 break;
2482 }
2483
2484 @@ -642,11 +850,21 @@
2485 loff_t offs;
2486
2487 if (copy_from_user(&offs, argp, sizeof(loff_t)))
2488 + {
2489 +#ifdef CONFIG_SL2312_SHARE_PIN
2490 + mtd_unlock(); // sl2312 share pin lock
2491 +#endif
2492 return -EFAULT;
2493 + }
2494 if (!mtd->block_markbad)
2495 ret = -EOPNOTSUPP;
2496 else
2497 + {
2498 +#ifdef CONFIG_SL2312_SHARE_PIN
2499 + mtd_unlock(); // sl2312 share pin lock
2500 +#endif
2501 return mtd->block_markbad(mtd, offs);
2502 + }
2503 break;
2504 }
2505
2506 @@ -654,8 +872,12 @@
2507 case OTPSELECT:
2508 {
2509 int mode;
2510 - if (copy_from_user(&mode, argp, sizeof(int)))
2511 + if (copy_from_user(&mode, argp, sizeof(int))) {
2512 +#ifdef CONFIG_SL2312_SHARE_PIN
2513 + mtd_unlock(); // sl2312 share pin lock
2514 +#endif
2515 return -EFAULT;
2516 + }
2517
2518 mfi->mode = MTD_MODE_NORMAL;
2519
2520 @@ -670,7 +892,12 @@
2521 {
2522 struct otp_info *buf = kmalloc(4096, GFP_KERNEL);
2523 if (!buf)
2524 + {
2525 +#ifdef CONFIG_SL2312_SHARE_PIN
2526 + mtd_unlock(); // sl2312 share pin lock
2527 +#endif
2528 return -ENOMEM;
2529 + }
2530 ret = -EOPNOTSUPP;
2531 switch (mfi->mode) {
2532 case MTD_MODE_OTP_FACTORY:
2533 @@ -701,12 +928,24 @@
2534 {
2535 struct otp_info info;
2536
2537 - if (mfi->mode != MTD_MODE_OTP_USER)
2538 + if (mfi->mode != MTD_MODE_OTP_USER) {
2539 +#ifdef CONFIG_SL2312_SHARE_PIN
2540 + mtd_unlock(); // sl2312 share pin lock
2541 +#endif
2542 return -EINVAL;
2543 - if (copy_from_user(&info, argp, sizeof(info)))
2544 + }
2545 + if (copy_from_user(&info, argp, sizeof(info))) {
2546 +#ifdef CONFIG_SL2312_SHARE_PIN
2547 + mtd_unlock(); // sl2312 share pin lock
2548 +#endif
2549 return -EFAULT;
2550 - if (!mtd->lock_user_prot_reg)
2551 + }
2552 + if (!mtd->lock_user_prot_reg) {
2553 +#ifdef CONFIG_SL2312_SHARE_PIN
2554 + mtd_unlock(); // sl2312 share pin lock
2555 +#endif
2556 return -EOPNOTSUPP;
2557 + }
2558 ret = mtd->lock_user_prot_reg(mtd, info.start, info.length);
2559 break;
2560 }
2561 @@ -742,8 +981,12 @@
2562 break;
2563
2564 case MTD_MODE_RAW:
2565 - if (!mtd->read_oob || !mtd->write_oob)
2566 + if (!mtd->read_oob || !mtd->write_oob) {
2567 +#ifdef CONFIG_SL2312_SHARE_PIN
2568 + mtd_unlock(); // sl2312 share pin lock
2569 +#endif
2570 return -EOPNOTSUPP;
2571 + }
2572 mfi->mode = arg;
2573
2574 case MTD_MODE_NORMAL:
2575 @@ -766,6 +1009,10 @@
2576 ret = -ENOTTY;
2577 }
2578
2579 +#ifdef CONFIG_SL2312_SHARE_PIN
2580 + mtd_unlock(); // sl2312 share pin lock
2581 +#endif
2582 +
2583 return ret;
2584 } /* memory_ioctl */
2585
2586 Index: linux-2.6.23.16/drivers/mtd/nand/Kconfig
2587 ===================================================================
2588 --- linux-2.6.23.16.orig/drivers/mtd/nand/Kconfig 2008-03-15 17:03:14.374622039 +0200
2589 +++ linux-2.6.23.16/drivers/mtd/nand/Kconfig 2008-03-15 17:03:17.874821522 +0200
2590 @@ -44,6 +44,13 @@
2591 This enables the driver for the autronix autcpu12 board to
2592 access the SmartMediaCard.
2593
2594 +config MTD_NAND_SL2312
2595 + tristate "NAND Flash device on Storlink board"
2596 + depends on ARM && MTD_NAND && ARCH_SL2312
2597 + help
2598 + This enables the driver for the Storlink board to
2599 + access the nand device.
2600 +
2601 config MTD_NAND_EDB7312
2602 tristate "Support for Cirrus Logic EBD7312 evaluation board"
2603 depends on ARCH_EDB7312
2604 Index: linux-2.6.23.16/drivers/mtd/nand/sl2312-flash-nand.c
2605 ===================================================================
2606 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2607 +++ linux-2.6.23.16/drivers/mtd/nand/sl2312-flash-nand.c 2008-03-15 17:03:17.874821522 +0200
2608 @@ -0,0 +1,2287 @@
2609 +/*
2610 + * drivers/mtd/sl2312.c
2611 + *
2612 + * $Id: sl2312-flash-nand.c,v 1.5 2006/06/15 07:02:29 middle Exp $
2613 + *
2614 + * Copyright (C) 2001 Toshiba Corporation
2615 + *
2616 + * 2003 (c) MontaVista Software, Inc. This file is licensed under
2617 + * the terms of the GNU General Public License version 2. This program
2618 + * is licensed "as is" without any warranty of any kind, whether express
2619 + * or implied.
2620 + *
2621 + */
2622 +
2623 +#include <linux/slab.h>
2624 +#include <linux/init.h>
2625 +#include <linux/module.h>
2626 +#include <linux/mtd/mtd.h>
2627 +#include <linux/mtd/nand.h>
2628 +#include <linux/mtd/nand_ecc.h>
2629 +#include <linux/mtd/partitions.h>
2630 +#include <linux/delay.h>
2631 +#include <asm/io.h>
2632 +#include <asm/hardware.h>
2633 +#include <asm/arch/sl2312.h>
2634 +#include "sl2312-flash-nand.h"
2635 +
2636 +
2637 +#include <linux/errno.h>
2638 +#include <linux/sched.h>
2639 +#include <linux/types.h>
2640 +#include <linux/mtd/compatmac.h>
2641 +#include <linux/interrupt.h>
2642 +#include <linux/bitops.h>
2643 +
2644 +
2645 +/*
2646 + * NAND low-level MTD interface functions
2647 + */
2648 +static void sl2312_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
2649 +static void sl2312_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
2650 +static int sl2312_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
2651 +
2652 +static int sl2312_nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
2653 +static int sl2312_nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
2654 +static int sl2312_nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
2655 +static int sl2312_nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf);
2656 +static int sl2312_nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
2657 + size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
2658 +static int sl2312_nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char *buf);
2659 +static int sl2312_nand_writev (struct mtd_info *mtd, const struct kvec *vecs,
2660 + unsigned long count, loff_t to, size_t * retlen);
2661 +static int sl2312_nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs,
2662 + unsigned long count, loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
2663 +static int sl2312_nand_erase (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
2664 +static void sl2312_nand_sync (struct mtd_info *mtd);
2665 +static int sl2312_nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf, struct nand_oobinfo *oobsel);
2666 +static int sl2312_nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt);
2667 +static int sl2312_nand_erase_block(struct mtd_info *mtd, int page);
2668 +
2669 +/*
2670 + * MTD structure for sl2312 NDFMC
2671 + */
2672 +static struct mtd_info *sl2312_mtd = NULL;
2673 +static int nand_page=0,nand_col=0;
2674 +
2675 +/* Define default oob placement schemes for large and small page devices */
2676 +static struct nand_oobinfo nand_oob_8 = {
2677 + .useecc = MTD_NANDECC_AUTOPLACE,
2678 + .eccbytes = 3,
2679 + .eccpos = {0, 1, 2},
2680 + .oobfree = { {3, 2}, {6, 2} }
2681 +};
2682 +
2683 +static struct nand_oobinfo nand_oob_16 = {
2684 + .useecc = MTD_NANDECC_AUTOPLACE,
2685 + .eccbytes = 6,
2686 + .eccpos = {0, 1, 2, 3, 6, 7},
2687 + .oobfree = { {8, 8} }
2688 +};
2689 +
2690 +static struct nand_oobinfo nand_oob_64 = {
2691 + .useecc = MTD_NANDECC_AUTOPLACE,
2692 + .eccbytes = 24,
2693 + .eccpos = {
2694 + 40, 41, 42, 43, 44, 45, 46, 47,
2695 + 48, 49, 50, 51, 52, 53, 54, 55,
2696 + 56, 57, 58, 59, 60, 61, 62, 63},
2697 + .oobfree = { {2, 38} }
2698 +};
2699 +
2700 +
2701 +/*
2702 + * Define partitions for flash device
2703 + */
2704 +/* the base address of FLASH control register */
2705 +#define FLASH_CONTROL_BASE_ADDR (IO_ADDRESS(SL2312_FLASH_CTRL_BASE))
2706 +#define SL2312_GLOBAL_BASE_ADDR (IO_ADDRESS(SL2312_GLOBAL_BASE))
2707 +//#define SL2312_FLASH_BASE_ADDR (IO_ADDRESS(SL2312_FLASH_BASE))
2708 +#define SL2312_FLASH_BASE_ADDR FLASH_VADDR(SL2312_FLASH_BASE)
2709 +static unsigned int CHIP_EN;
2710 +/* define read/write register utility */
2711 +//#define FLASH_READ_REG(offset) (__raw_readl(offset+FLASH_CONTROL_BASE_ADDR))
2712 +//#define FLASH_WRITE_REG(offset,val) (__raw_writel(val,offset+FLASH_CONTROL_BASE_ADDR))
2713 +//#define FLASH_READ_DATA(offset) (__raw_readb(offset+SL2312_FLASH_BASE_ADDR))
2714 +//#define FLASH_WRITE_DATA(offset,val) (__raw_writeb(val,offset+SL2312_FLASH_BASE_ADDR))
2715 +
2716 +unsigned int FLASH_READ_REG(unsigned int addr)
2717 +{
2718 + unsigned int *base;
2719 + unsigned int data;
2720 +
2721 + base = (unsigned int *)(FLASH_CONTROL_BASE_ADDR + addr);
2722 + data = *base;
2723 + return (data);
2724 +}
2725 +
2726 +void FLASH_WRITE_REG(unsigned int addr,unsigned int data)
2727 +{
2728 + unsigned int *base;
2729 +
2730 + base = (unsigned int *)(FLASH_CONTROL_BASE_ADDR + addr);
2731 + *base = data;
2732 + return;
2733 +}
2734 +
2735 +unsigned int FLASH_READ_DATA(unsigned int addr)
2736 +{
2737 + unsigned char *base;
2738 + unsigned int data;
2739 +
2740 + base = (unsigned char *)(SL2312_FLASH_BASE_ADDR + addr);
2741 + data = *base;
2742 + return (data);
2743 +}
2744 +
2745 +void FLASH_WRITE_DATA(unsigned int addr,unsigned int data)
2746 +{
2747 + unsigned char *base;
2748 +
2749 + base = (unsigned char *)(SL2312_FLASH_BASE_ADDR + addr);
2750 + *base = data;
2751 + return;
2752 +}
2753 +
2754 +/* the offset of FLASH control register */
2755 +enum NFLASH_REGISTER {
2756 + NFLASH_ID = 0x0000,
2757 + NFLASH_STATUS = 0x0008,
2758 + NFLASH_TYPE = 0x000c,
2759 + NFLASH_ACCESS = 0x0030,
2760 + NFLASH_COUNT = 0x0034,
2761 + NFLASH_CMD_ADDR = 0x0038,
2762 + NFLASH_ADDRESS = 0x003C,
2763 + NFLASH_DATA = 0x0040,
2764 + NFLASH_TIMING = 0x004C,
2765 + NFLASH_ECC_STATUS = 0x0050,
2766 + NFLASH_ECC_CONTROL = 0x0054,
2767 + NFLASH_ECC_OOB = 0x005c,
2768 + NFLASH_ECC_CODE_GEN0 = 0x0060,
2769 + NFLASH_ECC_CODE_GEN1 = 0x0064,
2770 + NFLASH_ECC_CODE_GEN2 = 0x0068,
2771 + NFLASH_ECC_CODE_GEN3 = 0x006C,
2772 + NFLASH_FIFO_CONTROL = 0x0070,
2773 + NFLASH_FIFO_STATUS = 0x0074,
2774 + NFLASH_FIFO_ADDRESS = 0x0078,
2775 + NFLASH_FIFO_DATA = 0x007c,
2776 +};
2777 +
2778 +
2779 +
2780 +//#define FLASH_BASE FLASH_CONTROL_BASE_ADDR
2781 +//#define FLASH_SIZE 0x00800000 //INTEGRATOR_FLASH_SIZE
2782 +
2783 +//#define FLASH_PART_SIZE 8388608
2784 +
2785 +//static unsigned int flash_indirect_access = 0;
2786 +
2787 +
2788 +#ifdef CONFIG_SL2312_SHARE_PIN
2789 +void sl2312flash_enable_nand_flash(void)
2790 +{
2791 + unsigned int reg_val;
2792 +
2793 + reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
2794 + reg_val = reg_val & 0xfffffffb;
2795 + writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
2796 + return;
2797 +}
2798 +
2799 +void sl2312flash_disable_nand_flash(void)
2800 +{
2801 + unsigned int reg_val;
2802 +
2803 + reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
2804 + reg_val = reg_val | 0x00000004;
2805 + writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
2806 + return;
2807 +}
2808 +#endif
2809 +
2810 +extern struct nand_oobinfo jffs2_oobinfo;
2811 +/*
2812 + * Define partitions for flash devices
2813 + */
2814 +
2815 +static struct mtd_partition sl2312_partitions[] = {
2816 + { name: "RedBoot", offset: 0x00000000, size: 0x0020000, },
2817 + { name: "Kernel", offset: 0x00020000, size: 0x00200000, },
2818 + { name: "Ramdisk", offset: 0x00220000, size: 0x00280000, },
2819 + { name: "Application", offset: 0x004A0000, size: 0x00320000, },
2820 + { name: "VCTL", offset: 0x007C0000, size: 0x20000, },
2821 + { name: "CurConf", offset: 0x007E0000, size: 0x20000, },
2822 + { name: "FIS directory", offset: 0x007e0000, size: 0x00020000, }
2823 +
2824 +};
2825 +
2826 +
2827 +/*
2828 + * hardware specific access to control-lines
2829 +*/
2830 +static void sl2312_hwcontrol(struct mtd_info *mtd, int cmd)
2831 +{
2832 +
2833 + return ;
2834 +}
2835 +
2836 +static int sl2312_nand_scan_bbt(struct mtd_info *mtd)
2837 +{
2838 + return 0;
2839 +}
2840 +
2841 +/**
2842 + * nand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
2843 + * @mtd: MTD device structure
2844 + * @ofs: offset relative to mtd start
2845 + */
2846 +static int sl2312_nand_block_isbad (struct mtd_info *mtd, loff_t ofs)
2847 +{
2848 + /* Check for invalid offset */
2849 + if (ofs > mtd->size)
2850 + return -EINVAL;
2851 +
2852 + return sl2312_nand_block_checkbad (mtd, ofs, 1, 0);
2853 +}
2854 +
2855 +/**
2856 + * nand_block_checkbad - [GENERIC] Check if a block is marked bad
2857 + * @mtd: MTD device structure
2858 + * @ofs: offset from device start
2859 + * @getchip: 0, if the chip is already selected
2860 + * @allowbbt: 1, if its allowed to access the bbt area
2861 + *
2862 + * Check, if the block is bad. Either by reading the bad block table or
2863 + * calling of the scan function.
2864 + */
2865 +
2866 +static int sl2312_nand_erase_block(struct mtd_info *mtd, int page)
2867 +{
2868 + int opcode;
2869 + /* Send commands to erase a page */
2870 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
2871 +
2872 + if(mtd->oobblock > 528)
2873 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff21); // 3 address & 2 command
2874 + else
2875 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff11); // 2 address & 2 command
2876 +
2877 + FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x0000d060); // write read id command
2878 + FLASH_WRITE_REG(NFLASH_ADDRESS, page); //write address 0x00
2879 +
2880 +
2881 +
2882 + /* read maker code */
2883 + opcode = 0x80003000|DWIDTH|CHIP_EN; //set start bit & 8bits write command
2884 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
2885 +
2886 + while(opcode&0x80000000) //polling flash access 31b
2887 + {
2888 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
2889 + //sl2312_flash_delay();
2890 + schedule();
2891 + //cond_resched();
2892 + }
2893 +}
2894 +
2895 +void sl2312_flash_delay(void)
2896 +{
2897 + int i;
2898 +
2899 + for(i=0; i<50; i++)
2900 + i=i;
2901 +}
2902 +
2903 +static int sl2312_nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt)
2904 +{
2905 + struct nand_chip *this = mtd->priv;
2906 +
2907 + if (!this->bbt)
2908 + return this->block_bad(mtd, ofs, getchip);
2909 +
2910 + /* Return info from the table */
2911 + return nand_isbad_bbt (mtd, ofs, allowbbt);
2912 +}
2913 +
2914 +/**
2915 + * nand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
2916 + * @mtd: MTD device structure
2917 + * @ofs: offset relative to mtd start
2918 + */
2919 +static int sl2312_nand_block_markbad (struct mtd_info *mtd, loff_t ofs)
2920 +{
2921 + struct nand_chip *this = mtd->priv;
2922 + int ret;
2923 +
2924 + if ((ret = sl2312_nand_block_isbad(mtd, ofs))) {
2925 + /* If it was bad already, return success and do nothing. */
2926 + if (ret > 0)
2927 + return 0;
2928 + return ret;
2929 + }
2930 +
2931 + return this->block_markbad(mtd, ofs);
2932 +}
2933 +
2934 +/*
2935 + * Get chip for selected access
2936 + */
2937 +static inline void sl2312_nand_get_chip (struct nand_chip *this, struct mtd_info *mtd, int new_state, int *erase_state)
2938 +{
2939 +
2940 + DECLARE_WAITQUEUE (wait, current);
2941 +
2942 + /*
2943 + * Grab the lock and see if the device is available
2944 + * For erasing, we keep the spinlock until the
2945 + * erase command is written.
2946 + */
2947 +retry:
2948 + spin_lock_bh (&this->chip_lock);
2949 +
2950 + if (this->state == FL_READY) {
2951 + this->state = new_state;
2952 + if (new_state != FL_ERASING)
2953 + spin_unlock_bh (&this->chip_lock);
2954 + return;
2955 + }
2956 +
2957 + if (this->state == FL_ERASING) {
2958 + if (new_state != FL_ERASING) {
2959 + this->state = new_state;
2960 + spin_unlock_bh (&this->chip_lock);
2961 + this->select_chip(mtd, 0); /* select in any case */
2962 + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2963 + return;
2964 + }
2965 + }
2966 +
2967 + set_current_state (TASK_UNINTERRUPTIBLE);
2968 + add_wait_queue (&this->wq, &wait);
2969 + spin_unlock_bh (&this->chip_lock);
2970 + schedule ();
2971 + remove_wait_queue (&this->wq, &wait);
2972 + goto retry;
2973 +}
2974 +
2975 +/*
2976 +* read device ready pin
2977 +*/
2978 +static int sl2312_device_ready(struct mtd_info *mtd)
2979 +{
2980 + int ready;
2981 +
2982 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
2983 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000070); //set only command no address and two data
2984 +
2985 + FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000070); //write read status command
2986 +
2987 +
2988 + ready = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
2989 + FLASH_WRITE_REG(NFLASH_ACCESS, ready);
2990 +
2991 + while(ready&0x80000000) //polling flash access 31b
2992 + {
2993 + ready=FLASH_READ_REG(NFLASH_ACCESS);
2994 + //sl2312_flash_delay();
2995 + schedule();
2996 + }
2997 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
2998 + ready=FLASH_READ_REG(NFLASH_DATA)&0xff;
2999 + return ready;
3000 +}
3001 +void sl2312_enable_hwecc(struct mtd_info *mtd, int mode)
3002 +{
3003 + /* reset first */
3004 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
3005 +
3006 +}
3007 +
3008 +
3009 +void sl2312_device_setup(void)
3010 +{
3011 +
3012 +}
3013 +static u_char sl2312_nand_read_byte(struct mtd_info *mtd)
3014 +{
3015 +
3016 + unsigned int data=0, page=0, col=0, tmp, i;
3017 +
3018 + printk ("**************************sl2312_nand_read_byte !! \n");
3019 + //page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
3020 + //col = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
3021 + page = nand_page;
3022 + col = nand_col;
3023 + for(i=0;i<(mtd->oobblock+mtd->oobsize);i++)
3024 + {
3025 + if(i==col)
3026 + data = FLASH_READ_DATA(page*mtd->oobblock +i);
3027 + else
3028 + tmp = FLASH_READ_DATA(page*mtd->oobblock +i);
3029 + }
3030 + return data&0xff;
3031 +}
3032 +
3033 +static void sl2312_nand_write_byte(struct mtd_info *mtd, u_char byte)
3034 +{
3035 + //struct nand_chip *this = mtd->priv;
3036 + unsigned int page=0, col=0, i;
3037 + u_char *databuf,oobbuf[mtd->oobsize];
3038 + size_t retlen;
3039 + retlen=0;
3040 + printk ("********************sl2312_nand_write_byte !! \n");
3041 + page = nand_page;
3042 + col = nand_col;
3043 + databuf = kmalloc (mtd->oobsize+mtd->oobblock,GFP_KERNEL);
3044 +
3045 + if (!databuf) {
3046 + printk ("sl2312_nand_write_byte : Unable to allocate SL2312 NAND MTD device structure.\n");
3047 +
3048 + }
3049 +
3050 + for(i=0;i<(mtd->oobblock+mtd->oobsize);i++)
3051 + databuf[i] = FLASH_READ_DATA(page*mtd->oobblock +i);
3052 +
3053 + databuf[col] = byte;
3054 + sl2312_nand_write_ecc (mtd, page, mtd->oobblock, &retlen, databuf, oobbuf, NULL);
3055 +
3056 +}
3057 +
3058 +static void sl2312_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
3059 +{
3060 + int i, page=0,col=0;
3061 + struct nand_chip *this = mtd->priv;
3062 + u_char *databuf, *oobbuf;
3063 + size_t retlen;
3064 + retlen=0;
3065 +
3066 +
3067 + printk ("***********************sl2312_nand_write_buf !! \n");
3068 + databuf = &(this->data_buf[0]);
3069 + oobbuf = &(this->data_buf[mtd->oobblock]);
3070 + for (i = 0; i < mtd->oobsize; i++)
3071 + oobbuf[i] = 0xff;
3072 +
3073 + if(len < mtd->oobblock)
3074 + {
3075 + //addr = FLASH_READ_REG(NFLASH_ADDRESS);
3076 + //page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
3077 + //col = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
3078 + page = nand_page;
3079 + col = nand_col;
3080 +
3081 + sl2312_nand_read_ecc (mtd, page, mtd->oobblock , &retlen, databuf, oobbuf, NULL);
3082 +
3083 + for(i=col;i<len;i++)
3084 + databuf[col+i] = buf[i];
3085 +
3086 + sl2312_nand_write_ecc (mtd, page, mtd->oobblock, &retlen, databuf, oobbuf, NULL);
3087 +
3088 + }
3089 +
3090 +}
3091 +
3092 +static void sl2312_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
3093 +{
3094 + int i, page=0,col=0,addr=0,tmp=0;
3095 + //struct nand_chip *this = mtd->priv;
3096 + printk ("********************sl2312_nand_read_buf !! \n");
3097 + if(len < mtd->oobblock)
3098 + {
3099 + //addr = FLASH_READ_REG(NFLASH_ADDRESS);
3100 + //page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
3101 + //col = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
3102 + page = nand_page;
3103 + col = nand_col;
3104 + for (i=col; i<((mtd->oobblock+mtd->oobsize)-col); i++)
3105 + {
3106 + if(i<len)
3107 + buf[i] = FLASH_READ_DATA(addr+i);
3108 + else
3109 + tmp = FLASH_READ_DATA(addr+i);
3110 + }
3111 + }
3112 +}
3113 +
3114 +static int sl2312_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
3115 +{
3116 + int i;
3117 + //struct nand_chip *this = mtd->priv;
3118 + u_char *datatmp, *oobtmp;
3119 + size_t retlen;
3120 + retlen=0;
3121 +
3122 + datatmp = kmalloc (mtd->oobblock,GFP_KERNEL);
3123 + oobtmp = kmalloc (mtd->oobsize,GFP_KERNEL);
3124 +
3125 + if ((!datatmp)||(!oobtmp)) {
3126 + printk ("sl2312_nand_verify_buf : Unable to allocate SL2312 NAND MTD device structure.\n");
3127 +
3128 + }
3129 + //page = nand_page;
3130 + for(i=0;i<mtd->oobblock;i++)
3131 + datatmp[i] = FLASH_READ_DATA(nand_page*mtd->oobblock +i);
3132 + /* read oobdata */
3133 + for (i = 0; i < mtd->oobsize; i++)
3134 + oobtmp[i] = FLASH_READ_DATA(nand_page*mtd->oobblock + mtd->oobblock + i);
3135 +
3136 + if(len==mtd->oobblock)
3137 + {
3138 + for (i=0; i<len; i++)
3139 + {
3140 + if (buf[i] != datatmp[i])
3141 + {
3142 + kfree(datatmp);
3143 + kfree(oobtmp);
3144 + printk("Data verify error -> page: %x, byte: %x \n",nand_page,i);
3145 + return i;
3146 + }
3147 + }
3148 + }
3149 + else if(len == mtd->oobsize)
3150 + {
3151 + for (i=0; i<len; i++)
3152 + {
3153 + if (buf[i] != oobtmp[i])
3154 + {
3155 + kfree(datatmp);
3156 + kfree(oobtmp);
3157 + printk("OOB verify error -> page: %x, byte: %x \n",nand_page,i);
3158 + return i;
3159 + }
3160 + }
3161 + }
3162 + else
3163 + {
3164 + printk (KERN_WARNING "sl2312_nand_verify_buf : verify length not match 0x%08x\n", len);
3165 + kfree(datatmp);
3166 + kfree(oobtmp);
3167 + return -1;
3168 + }
3169 +
3170 + kfree(datatmp);
3171 + kfree(oobtmp);
3172 + return 0;
3173 +}
3174 +
3175 +/*
3176 + * Send command to NAND device
3177 + */
3178 +static void sl2312_nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
3179 +{
3180 + register struct nand_chip *this = mtd->priv;
3181 + int opcode;
3182 +
3183 +
3184 + /*
3185 + * program and erase have their own busy handlers
3186 + * status and sequential in needs no delay
3187 + */
3188 + switch (command) {
3189 +
3190 + case NAND_CMD_PAGEPROG:
3191 + case NAND_CMD_ERASE1:
3192 + case NAND_CMD_ERASE2:
3193 + case NAND_CMD_SEQIN:
3194 + case NAND_CMD_STATUS:
3195 + case NAND_CMD_READ0:
3196 +
3197 + /*
3198 + * Write out the command to the device.
3199 + */
3200 + if (column != -1 || page_addr != -1) {
3201 +
3202 + /* Serially input address */
3203 + if (column != -1)
3204 + //FLASH_WRITE_REG(NFLASH_ADDRESS,column);
3205 + nand_col=column;
3206 +
3207 + opcode = FLASH_READ_REG(NFLASH_ADDRESS);
3208 +
3209 + if (page_addr != -1)
3210 + //FLASH_WRITE_REG(NFLASH_ADDRESS,opcode|(page_addr<<8));
3211 + nand_page = page_addr;
3212 +
3213 + }
3214 + return;
3215 +
3216 + case NAND_CMD_RESET:
3217 + if (this->dev_ready)
3218 + break;
3219 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3220 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff70); //set only command and no other data
3221 + FLASH_WRITE_REG(NFLASH_CMD_ADDR, NAND_CMD_RESET); //write reset command
3222 +
3223 + opcode = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
3224 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3225 +
3226 + while(opcode&0x80000000) //polling flash access 31b
3227 + {
3228 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3229 + //sl2312_flash_delay();
3230 + schedule();
3231 + }
3232 + while ( !(sl2312_device_ready(mtd) & 0x40));
3233 + {
3234 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3235 + //sl2312_flash_delay();
3236 + schedule();
3237 + return;
3238 + }
3239 + /* This applies to read commands */
3240 + default:
3241 + /*
3242 + * If we don't have access to the busy pin, we apply the given
3243 + * command delay
3244 + */
3245 + if (!this->dev_ready) {
3246 + udelay (this->chip_delay);
3247 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3248 + return;
3249 + }
3250 + }
3251 +
3252 + /* wait until command is processed */
3253 + while (!this->dev_ready(mtd));
3254 +
3255 +}
3256 +/*Add function*/
3257 +static void nand_read_id(int chip_no, unsigned char *id)
3258 +{
3259 + unsigned int opcode, i;
3260 +
3261 + if(chip_no==0)
3262 + CHIP_EN = NFLASH_CHIP0_EN;
3263 + else
3264 + CHIP_EN = NFLASH_CHIP1_EN;
3265 +
3266 + opcode = FLASH_READ_REG(NFLASH_TYPE);
3267 +
3268 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3269 + if((opcode&0x00000300)<=0x00000100)
3270 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000100); //set only command & address and two data
3271 + else
3272 + FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000300); //set only command & address and 4 data
3273 +
3274 + FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000090); //write read id command
3275 + FLASH_WRITE_REG(NFLASH_ADDRESS, 0x00000000); //write address 0x00
3276 +
3277 + /* read maker code */
3278 + opcode = 0x80002000|DWIDTH|CHIP_EN;//|chip0_en; //set start bit & 8bits read command
3279 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3280 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3281 + while(opcode&0x80000000) //polling flash access 31b
3282 + {
3283 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3284 + //sl2312_flash_delay();
3285 + schedule();
3286 + }
3287 +
3288 + opcode = FLASH_READ_REG(NFLASH_DATA);
3289 + if(DWIDTH==NFLASH_WiDTH16)
3290 + {
3291 + id[0] = opcode&0xff;
3292 + id[1] = (opcode&0xff00)>>8;
3293 + }
3294 + else
3295 + {
3296 + id[0] = opcode&0xff;
3297 + opcode = 0x80002000|DWIDTH|CHIP_EN;//|chip0_en; //set start bit & 8bits read command
3298 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3299 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3300 + while(opcode&0x80000000) //polling flash access 31b
3301 + {
3302 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3303 + //sl2312_flash_delay();
3304 + schedule();
3305 + }
3306 + opcode = FLASH_READ_REG(NFLASH_DATA);
3307 + id[1] = (opcode&0xff00)>>8;
3308 +
3309 + opcode=FLASH_READ_REG(NFLASH_TYPE);
3310 + if((opcode&0x300)>0x100)
3311 + {
3312 + for(i=0;i<2;i++)
3313 + {
3314 + //data cycle 3 & 4 ->not use
3315 + opcode = 0x80002000|DWIDTH|CHIP_EN;//set start bit & 8bits read command
3316 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3317 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3318 + while(opcode&0x80000000) //polling flash access 31b
3319 + {
3320 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3321 + //sl2312_flash_delay();
3322 + schedule();
3323 + }
3324 +
3325 + opcode=FLASH_READ_REG(NFLASH_DATA);
3326 + id[2+i] = (opcode&(0xff0000<<i*8))>>(8*(2+i));
3327 + }
3328 + }
3329 + }
3330 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3331 +}
3332 +
3333 +/*
3334 + * NAND erase a block
3335 + */
3336 +static int sl2312_nand_erase (struct mtd_info *mtd, struct erase_info *instr, int allowbbt)
3337 +{
3338 + int page, len, status, pages_per_block, ret, chipnr;
3339 + struct nand_chip *this = mtd->priv;
3340 +
3341 + DEBUG (MTD_DEBUG_LEVEL3,
3342 + "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
3343 +
3344 + /* Start address must align on block boundary */
3345 + if (instr->addr & ((1 << this->phys_erase_shift) - 1)) {
3346 + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
3347 + return -EINVAL;
3348 + }
3349 +
3350 + /* Length must align on block boundary */
3351 + if (instr->len & ((1 << this->phys_erase_shift) - 1)) {
3352 + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n");
3353 + return -EINVAL;
3354 + }
3355 +
3356 + /* Do not allow erase past end of device */
3357 + if ((instr->len + instr->addr) > mtd->size) {
3358 + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n");
3359 + return -EINVAL;
3360 + }
3361 +
3362 + instr->fail_addr = 0xffffffff;
3363 +
3364 + /* Grab the lock and see if the device is available */
3365 + sl2312_nand_get_chip (this, mtd, FL_ERASING, NULL);
3366 +
3367 + /* Shift to get first page */
3368 + page = (int) (instr->addr >> this->page_shift);
3369 + chipnr = (int) (instr->addr >> this->chip_shift);
3370 +
3371 + /* Calculate pages in each block */
3372 + pages_per_block = 1 << (this->phys_erase_shift - this->page_shift);
3373 +
3374 + /* Select the NAND device */
3375 + //this->select_chip(mtd, chipnr);
3376 + this->select_chip(mtd, 0);
3377 +
3378 + /* Check the WP bit */
3379 + /* Check, if it is write protected */
3380 + status = sl2312_device_ready(mtd);
3381 + if (!(status & 0x80)) {
3382 + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n");
3383 + instr->state = MTD_ERASE_FAILED;
3384 + goto erase_exit;
3385 + }
3386 +
3387 + /* Loop through the pages */
3388 + len = instr->len;
3389 +
3390 + instr->state = MTD_ERASING;
3391 +
3392 + while (len) {
3393 + /* Check if we have a bad block, we do not erase bad blocks ! */
3394 + if (this->block_bad(mtd, ((loff_t) page) << this->page_shift, 0)) {
3395 + printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page);
3396 + //instr->state = MTD_ERASE_FAILED;
3397 + //goto erase_exit;
3398 + }
3399 +
3400 + /* Invalidate the page cache, if we erase the block which contains
3401 + the current cached page */
3402 + if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block))
3403 + this->pagebuf = -1;
3404 + /////////
3405 +
3406 + ///* Send commands to erase a page */
3407 + //FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3408 + //
3409 + //if(mtd->oobblock > 528)
3410 + // FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff21); // 3 address & 2 command
3411 + //else
3412 + // FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff11); // 2 address & 2 command
3413 + //
3414 + //FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x0000d060); // write read id command
3415 + //FLASH_WRITE_REG(NFLASH_ADDRESS, page); //write address 0x00
3416 + //
3417 + //
3418 + //
3419 + ///* read maker code */
3420 + //opcode = 0x80003000|DWIDTH|CHIP_EN; //set start bit & 8bits write command
3421 + //FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3422 + //
3423 + //while(opcode&0x80000000) //polling flash access 31b
3424 + //{
3425 + // opcode=FLASH_READ_REG(NFLASH_ACCESS);
3426 + // //sl2312_flash_delay();
3427 + // schedule();
3428 + // //cond_resched();
3429 + //}
3430 + sl2312_nand_erase_block(mtd, page);
3431 + //////////////
3432 + status = this->waitfunc (mtd, this, FL_ERASING);
3433 + /* See if block erase succeeded */
3434 + if (status & 0x01) {
3435 + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page);
3436 + instr->state = MTD_ERASE_FAILED;
3437 + instr->fail_addr = (page << this->page_shift);
3438 + goto erase_exit;
3439 + }
3440 +
3441 + /* Increment page address and decrement length */
3442 + len -= (1 << this->phys_erase_shift);
3443 + page += pages_per_block;
3444 +
3445 + /* Check, if we cross a chip boundary */
3446 + if (len && !(page & this->pagemask)) {
3447 + chipnr++;
3448 + this->select_chip(mtd, 0);
3449 + this->select_chip(mtd, 0);
3450 + }
3451 + //sl2312_flash_delay();
3452 + schedule();
3453 + //cond_resched();
3454 + }
3455 + instr->state = MTD_ERASE_DONE;
3456 +
3457 +erase_exit:
3458 + /* De-select the NAND device */
3459 + this->select_chip(mtd, 0);
3460 + spin_unlock_bh (&this->chip_lock);
3461 +
3462 + ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;;
3463 + /* Do call back function */
3464 + if (!ret && instr->callback)
3465 + instr->callback (instr);
3466 +
3467 + /* The device is ready */
3468 + spin_lock_bh (&this->chip_lock);
3469 + this->state = FL_READY;
3470 + spin_unlock_bh (&this->chip_lock);
3471 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3472 + /* Return more or less happy */
3473 + return ret;
3474 +}
3475 +
3476 +static void sl2312_nand_select_chip(struct mtd_info *mtd, int chip)
3477 +{
3478 + //struct nand_chip *this = mtd->priv;
3479 +
3480 + switch(chip) {
3481 + case -1:
3482 + CHIP_EN = NFLASH_CHIP0_EN;
3483 + break;
3484 + case 0:
3485 + CHIP_EN = NFLASH_CHIP0_EN;
3486 + break;
3487 + case 1:
3488 + CHIP_EN = NFLASH_CHIP1_EN;
3489 + break;
3490 + default:
3491 + CHIP_EN = NFLASH_CHIP0_EN;
3492 + break;
3493 + }
3494 +}
3495 +
3496 +/**
3497 + * nand_default_block_markbad - [DEFAULT] mark a block bad
3498 + * @mtd: MTD device structure
3499 + * @ofs: offset from device start
3500 + *
3501 + * This is the default implementation, which can be overridden by
3502 + * a hardware specific driver.
3503 +*/
3504 +static int sl2312_nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
3505 +{
3506 + struct nand_chip *this = mtd->priv;
3507 + u_char buf[2] = {0, 0};
3508 + size_t retlen;
3509 + int block;
3510 +
3511 + /* Get block number */
3512 + block = ((int) ofs) >> this->bbt_erase_shift;
3513 + this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
3514 +
3515 + /* Do we have a flash based bad block table ? */
3516 + if (this->options & NAND_USE_FLASH_BBT)
3517 + return nand_update_bbt (mtd, ofs);
3518 +
3519 + /* We write two bytes, so we dont have to mess with 16 bit access */
3520 + ofs += mtd->oobsize + (this->badblockpos & ~0x01);
3521 + return sl2312_nand_write_oob (mtd, ofs , 2, &retlen, buf);
3522 +}
3523 +
3524 +/* Appropriate chip should already be selected */
3525 +static int sl2312_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)//(struct mtd_info *mtd, unsigned long page, )
3526 +{
3527 + u_char *buf, *oobbuf;
3528 + size_t retlen;
3529 + unsigned long page, chipnr;
3530 + struct nand_chip *this = mtd->priv;
3531 +
3532 + if (getchip) {
3533 + page = (int)(ofs >> this->page_shift);
3534 + chipnr = (int)(ofs >> this->chip_shift);
3535 +
3536 + /* Grab the lock and see if the device is available */
3537 + sl2312_nand_get_chip (this, mtd, FL_READING, NULL);
3538 + /* Select the NAND device */
3539 + this->select_chip(mtd, chipnr);
3540 + } else
3541 + page = (int) ofs;
3542 +
3543 + buf = kmalloc (mtd->oobblock,GFP_KERNEL);
3544 + oobbuf = kmalloc (mtd->oobsize,GFP_KERNEL);
3545 +
3546 + if ((!buf)||(!oobbuf)) {
3547 + printk ("sl2312_nand_block_bad : Unable to allocate SL2312 NAND MTD device structure.\n");
3548 +
3549 + }
3550 +
3551 + sl2312_nand_read_ecc (mtd, page, mtd->oobblock , &retlen, buf, oobbuf, NULL);
3552 +
3553 +
3554 + if(((mtd->oobblock < 528)&&(oobbuf[5] != 0xff))||((mtd->oobblock > 528)&&(oobbuf[0] != 0xff)))
3555 + {
3556 + kfree(buf);
3557 + kfree(oobbuf);
3558 + return 1;
3559 + }
3560 +
3561 + kfree(buf);
3562 + kfree(oobbuf);
3563 + return 0;
3564 +}
3565 +
3566 +/*
3567 +* Use NAND read ECC
3568 +*/
3569 +static int sl2312_nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
3570 +{
3571 + return sl2312_nand_read_ecc (mtd, from, len, retlen, buf, NULL, NULL);
3572 +}
3573 +
3574 +/*
3575 + * NAND read with ECC
3576 + */
3577 +static int sl2312_nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
3578 + size_t * retlen, u_char * buf, u_char * oob_buf, struct nand_oobinfo *oobsel)
3579 +{
3580 + int j, col, page, opcode, i;
3581 + int end=0;//, ecc=0;//, end_page=0;
3582 + int erase_state = 0;
3583 + int read = 0, oob = 0, ecc_failed = 0;//, ecc_status = 0
3584 + struct nand_chip *this = mtd->priv;
3585 + u_char *data_poi, *oob_data = oob_buf;
3586 + //u_char ecc_calc[6];
3587 + //u_char ecc_code[6];
3588 + int eccmode;
3589 + int *oob_config;
3590 +
3591 +
3592 +
3593 + // use chip default if zero
3594 + if (oobsel == NULL)
3595 + oobsel = &mtd->oobinfo;
3596 +
3597 + eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
3598 + oob_config = oobsel->eccpos;
3599 +
3600 + DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
3601 +
3602 + /* Do not allow reads past end of device */
3603 + if ((from + len) > mtd->size) {
3604 + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n");
3605 + *retlen = 0;
3606 + return -EINVAL;
3607 + }
3608 +
3609 + /* Grab the lock and see if the device is available */
3610 + sl2312_nand_get_chip (this, mtd ,FL_READING, &erase_state);
3611 +
3612 + /* Select the NAND device */
3613 + this->select_chip(mtd, 0);
3614 +
3615 + /* First we calculate the starting page */
3616 + page = from >> this->page_shift;
3617 +
3618 + //end_page = mtd->oobblock + mtd->oobsize;
3619 + end = mtd->oobblock;
3620 + //ecc = mtd->eccsize;
3621 + /* Get raw starting column */
3622 + col = (from & (mtd->oobblock - 1));
3623 +
3624 +
3625 + /* Send the read command */
3626 + //this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page);
3627 +
3628 + /* Loop until all data read */
3629 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3630 + while (read < len) {
3631 +
3632 + //udelay(1200);
3633 + /* If we have consequent page reads, apply delay or wait for ready/busy pin */
3634 + if (read) {
3635 + if (!this->dev_ready)
3636 + udelay (this->chip_delay);
3637 + else
3638 + while (!this->dev_ready(mtd));
3639 + }
3640 +
3641 + /*
3642 + * If the read is not page aligned, we have to read into data buffer
3643 + * due to ecc, else we read into return buffer direct
3644 + */
3645 + if (!col && (len - read) >= end)
3646 + data_poi = &buf[read];
3647 + else
3648 + data_poi = this->data_buf;
3649 +
3650 + /* get oob area, if we have no oob buffer from fs-driver */
3651 + if (!oob_buf) {
3652 + oob_data = &this->data_buf[end];
3653 + oob = 0;
3654 + }
3655 +
3656 + j = 0;
3657 + switch (eccmode) {
3658 + case NAND_ECC_NONE: { /* No ECC, Read in a page */
3659 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3660 + break;
3661 + }
3662 +
3663 + case NAND_ECC_SOFT: /* Software ECC 3/256: Read in a page + oob data */
3664 + break;
3665 +
3666 + case NAND_ECC_HW3_256: /* Hardware ECC 3 byte /256 byte data: Read in first 256 byte, get ecc, */
3667 + break;
3668 +
3669 + case NAND_ECC_HW3_512:
3670 + case NAND_ECC_HW6_512: /* Hardware ECC 3/6 byte / 512 byte data : Read in a page */
3671 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
3672 + break;
3673 +
3674 + default:
3675 + printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
3676 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0);
3677 + //BUG();
3678 + }//end switch
3679 +
3680 + for(i=0;i<end;i++)
3681 + {
3682 + //udelay(7);
3683 + data_poi[i] = FLASH_READ_DATA(page*mtd->oobblock +i);
3684 + }
3685 + /* read oobdata */
3686 + for (i = 0; i < mtd->oobsize; i++)
3687 + {
3688 + //udelay(7);
3689 + oob_data[oob + i] = FLASH_READ_DATA(page*mtd->oobblock +end+i);
3690 + }
3691 +
3692 + /* Skip ECC, if not active */
3693 + if (eccmode == NAND_ECC_NONE)
3694 + goto readdata;
3695 +
3696 + // compare ecc and correct data
3697 +
3698 + opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3699 + while(!(opcode&0x80000000)) //polling flash access 31b
3700 + {
3701 + opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3702 + //sl2312_flash_delay();
3703 + schedule();
3704 + }
3705 + for(j=0;j<(end/512);j++)
3706 + {//for 2k page
3707 +
3708 + opcode = 0x00000000|oob_data[mtd->oobsize-3-4*j]<<16|oob_data[mtd->oobsize-2-4*j]<<8|oob_data[mtd->oobsize-1-4*j];
3709 +
3710 + //opcode=FLASH_READ_REG(NFLASH_ECC_CODE_GEN0+(j*4));
3711 +
3712 + FLASH_WRITE_REG(NFLASH_ECC_OOB, opcode);
3713 + opcode = 0x00000000|(j<<8); //select ECC code generation 0
3714 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, opcode); //???
3715 +
3716 + opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3717 + if((opcode&0x00000003)==0x03)
3718 + {
3719 + printk (KERN_WARNING "\nPageRead Uncorrectable error !!\n");
3720 + ecc_failed++;
3721 + }
3722 + else if((opcode&0x00000003)==0x01)
3723 + {
3724 + printk (KERN_WARNING "\nPageRead One bit data error !!");
3725 + // correct data
3726 + if((data_poi[(opcode&0xff80)>>7]>>((opcode&0x38)>>3))%1)
3727 + data_poi[(opcode&0xff80)>>7] &= ~(1<<((opcode&0x38)>>3));
3728 + else
3729 + data_poi[(opcode&0xff80)>>7] |= (1<<((opcode&0x38)>>3));
3730 +
3731 + }
3732 + else if((opcode&0x00000003)==0x02)
3733 + {
3734 + printk (KERN_WARNING "\nPageRead One bit ECC error !!\n");
3735 + }
3736 + else if((opcode&0x00000003)==0x00)
3737 + {
3738 +
3739 + }
3740 +
3741 + }//for 2k page
3742 +readdata:
3743 + if (col || (len - read) < end) {
3744 + for (j = col; j < end && read < len; j++)
3745 + buf[read++] = data_poi[j];
3746 + } else
3747 + read += mtd->oobblock;
3748 + /* For subsequent reads align to page boundary. */
3749 + col = 0;
3750 + /* Increment page address */
3751 + page++;
3752 + schedule();
3753 + }
3754 + /* De-select the NAND device */
3755 + //this->select_chip(mtd, -1);
3756 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3757 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_INDIRECT);
3758 + /* Wake up anyone waiting on the device */
3759 + spin_lock_bh (&this->chip_lock);
3760 + this->state = FL_READY;
3761 + wake_up (&this->wq);
3762 + spin_unlock_bh (&this->chip_lock);
3763 +
3764 + /*
3765 + * Return success, if no ECC failures, else -EIO
3766 + * fs driver will take care of that, because
3767 + * retlen == desired len and result == -EIO
3768 + */
3769 + *retlen = read;
3770 + return ecc_failed ? -EIO : 0;
3771 +}
3772 +
3773 +/*
3774 + * Wait for command done. This applies to erase and program only
3775 + * Erase can take up to 400ms and program up to 20ms according to
3776 + * general NAND and SmartMedia specs
3777 + *
3778 +*/
3779 +static int sl2312_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
3780 +{
3781 + unsigned long timeo = jiffies;
3782 + int status, opcode;
3783 +
3784 + if (state == FL_ERASING)
3785 + timeo += (HZ * 400) / 1000;
3786 + else
3787 + timeo += (HZ * 20) / 1000;
3788 +
3789 + spin_lock_bh (&this->chip_lock);
3790 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3791 + FLASH_WRITE_REG(NFLASH_COUNT, 0x007f000070); //set only command no address and two data
3792 +
3793 + FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000070); //write read status command
3794 +
3795 +
3796 + opcode = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
3797 + FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3798 +
3799 + while(opcode&0x80000000) //polling flash access 31b
3800 + {
3801 + opcode=FLASH_READ_REG(NFLASH_ACCESS);
3802 + //sl2312_flash_delay();
3803 + schedule();
3804 + }
3805 +
3806 + while (time_before(jiffies, timeo)) {
3807 + /* Check, if we were interrupted */
3808 + if (this->state != state) {
3809 + spin_unlock_bh (&this->chip_lock);
3810 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3811 + return 0;
3812 + }
3813 + if (this->dev_ready) {
3814 + if (this->dev_ready(mtd))
3815 + break;
3816 + }
3817 + if (FLASH_READ_REG(NFLASH_DATA) & 0x40)
3818 + break;
3819 +
3820 + spin_unlock_bh (&this->chip_lock);
3821 + yield ();
3822 + spin_lock_bh (&this->chip_lock);
3823 + }
3824 + status = FLASH_READ_REG(NFLASH_DATA)&0xff;
3825 + spin_unlock_bh (&this->chip_lock);
3826 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3827 + return status;
3828 +}
3829 +
3830 +static int sl2312_nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
3831 +{
3832 + int i, col, page, j=0;
3833 + //int erase_state = 0;
3834 + struct nand_chip *this = mtd->priv;
3835 + u_char *databuf, *oobbuf;
3836 +
3837 + databuf = &this->data_buf[0];
3838 + oobbuf = &this->data_buf[mtd->oobblock];
3839 + for (i = 0; i < mtd->oobsize; i++)
3840 + oobbuf[i] = 0xff;
3841 +
3842 + DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
3843 +
3844 + /* Shift to get page */
3845 + page = ((int) from) >> this->page_shift;
3846 +
3847 + /* Mask to get column */
3848 + col = from & (mtd->oobsize-1); //0x0f;
3849 +
3850 + /* Initialize return length value */
3851 + *retlen = 0;
3852 + sl2312_nand_read_ecc (mtd, page, mtd->oobblock , retlen, databuf, oobbuf, NULL);
3853 + for(i=col,j=0;i<mtd->oobsize||i<(col+len);i++,j++)
3854 + buf[j] = oobbuf[i];
3855 +
3856 + *retlen = j ;
3857 + return 0;
3858 +}
3859 +
3860 +#define NOTALIGNED(x) (x & (mtd->oobblock-1)) != 0
3861 +/*
3862 +* Use NAND write ECC
3863 +*/
3864 +static int sl2312_nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
3865 +{
3866 + return (sl2312_nand_write_ecc (mtd, to, len, retlen, buf, NULL, NULL));
3867 +}
3868 +
3869 +/*
3870 + * NAND write with ECC
3871 + */
3872 +static int sl2312_nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
3873 + size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel)
3874 +{
3875 + int page, ret = 0, oob = 0, written = 0;
3876 + struct nand_chip *this = mtd->priv;
3877 +
3878 + DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
3879 +
3880 +
3881 + /* Do not allow write past end of device */
3882 + if ((to + len) > mtd->size) {
3883 + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n");
3884 + return -EINVAL;
3885 + }
3886 +
3887 + /* reject writes, which are not page aligned */
3888 + if (NOTALIGNED (to) || NOTALIGNED(len)) {
3889 + printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
3890 + return -EINVAL;
3891 + }
3892 +
3893 + // if oobsel is NULL, use chip defaults
3894 + if (oobsel == NULL)
3895 + oobsel = &mtd->oobinfo;
3896 +
3897 + /* Shift to get page */
3898 + page = ((int) to) >> this->page_shift;
3899 +
3900 + /* Grab the lock and see if the device is available */
3901 + sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
3902 +
3903 + /* Select the NAND device */
3904 + this->select_chip(mtd, 0);
3905 +
3906 + /* Check the WP bit */
3907 + if (!(sl2312_device_ready(mtd) & 0x80)) {
3908 + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Device is write protected!!!\n");
3909 + ret = -EIO;
3910 + goto out;
3911 + }
3912 +
3913 + /* Loop until all data is written */
3914 + while (written < len) {
3915 + //udelay(100);
3916 + int cnt = mtd->oobblock;
3917 + this->data_poi = (u_char*) &buf[written];
3918 + /* We use the same function for write and writev */
3919 + if (eccbuf) {
3920 + ret = sl2312_nand_write_page (mtd, this, page, &eccbuf[oob], oobsel);
3921 + oob += mtd->oobsize;
3922 + } else
3923 + ret = sl2312_nand_write_page (mtd, this, page, NULL, oobsel);
3924 +
3925 + if (ret)
3926 + goto out;
3927 +
3928 + /* Update written bytes count */
3929 + written += cnt;
3930 + /* Increment page address */
3931 + page++;
3932 + }
3933 +
3934 +out:
3935 + /* De-select the NAND device */
3936 + //this->select_chip(mtd, -1);
3937 +
3938 + /* Wake up anyone waiting on the device */
3939 + spin_lock_bh (&this->chip_lock);
3940 + this->state = FL_READY;
3941 + wake_up (&this->wq);
3942 + spin_unlock_bh (&this->chip_lock);
3943 +
3944 + *retlen = written;
3945 + return ret;
3946 +}
3947 +
3948 +/*
3949 + * Nand_page_program function is used for write and writev !
3950 + * This function will always program a full page of data
3951 + * If you call it with a non page aligned buffer, you're lost :)
3952 + */
3953 +static int sl2312_nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf, struct nand_oobinfo *oobsel)
3954 +{
3955 + int i, j, status, opcode;
3956 + u_char ecc_code[16], *oob_data;
3957 + int eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
3958 + //int *oob_config = oobsel->eccpos;
3959 +
3960 + /* pad oob area, if we have no oob buffer from fs-driver */
3961 + if (!oob_buf) {
3962 + oob_data = &this->data_buf[mtd->oobblock];
3963 + for (i = 0; i < mtd->oobsize; i++)
3964 + oob_data[i] = 0xff;
3965 + } else
3966 + oob_data = oob_buf;
3967 +
3968 + /* Send command to begin auto page programming */
3969 +
3970 + memset(oob_data,0xff,mtd->oobsize);
3971 + /* Write out complete page of data, take care of eccmode */
3972 + switch (eccmode) {
3973 + /* No ecc and software ecc 3/256, write all */
3974 + case NAND_ECC_NONE:
3975 + printk (KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n");
3976 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3977 + break;
3978 + case NAND_ECC_SOFT:
3979 + break;
3980 +
3981 + /* Hardware ecc 3 byte / 256 data, write first half, get ecc, then second, if 512 byte pagesize */
3982 + case NAND_ECC_HW3_256:
3983 + break;
3984 +
3985 + /* Hardware ecc 3 byte / 512 byte data, write full page */
3986 + case NAND_ECC_HW3_512:
3987 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
3988 +
3989 + /* Hardware ecc 6 byte / 512 byte data, write full page */
3990 + case NAND_ECC_HW6_512:
3991 + break;
3992 +
3993 + default:
3994 + printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
3995 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3996 + //BUG();
3997 + }
3998 +
3999 + FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
4000 +
4001 + for(i=0;i<mtd->oobblock;i++)
4002 + {
4003 + //udelay(5);
4004 + FLASH_WRITE_DATA((page*mtd->oobblock)+i,this->data_poi[i]);
4005 + }
4006 + ///////////////
4007 + if(eccmode!=NAND_ECC_NONE)
4008 + {
4009 + opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
4010 + while(!(opcode&0x80000000)) //polling flash access 31b
4011 + {
4012 + opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
4013 + //sl2312_flash_delay();
4014 + schedule();
4015 + }
4016 +
4017 +
4018 + for(i=0;i<(mtd->oobblock/512);i++)
4019 + {
4020 + opcode=FLASH_READ_REG(NFLASH_ECC_CODE_GEN0+(i*4));
4021 +
4022 + for(j=3;j>0;j--)
4023 + oob_data[(mtd->oobsize-j-(i*4))] = (opcode<<((4-j)*8)) >>24;
4024 +
4025 + for(j=0;j<4;j++)
4026 + {
4027 + ecc_code[15-i*4] = opcode;
4028 + ecc_code[15-i*4-1] = opcode>>8;
4029 + ecc_code[15-i*4-2] = opcode>>16;
4030 + }
4031 + }
4032 +
4033 + //disable ecc
4034 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000);
4035 +
4036 + /* Write out OOB data */
4037 + for(i=0;i<mtd->oobsize;i++)
4038 + {
4039 + //udelay(5);
4040 + FLASH_WRITE_DATA((page*mtd->oobblock)+mtd->oobblock+i,oob_data[i]);
4041 + }
4042 + }
4043 + else
4044 + {
4045 + for(i=0;i<mtd->oobsize;i++)
4046 + {
4047 + //udelay(5);
4048 + FLASH_WRITE_DATA((page*mtd->oobblock)+mtd->oobblock+i,0xff);
4049 + }
4050 + }
4051 +
4052 +
4053 + /* call wait ready function */
4054 + status = this->waitfunc (mtd, this, FL_WRITING);
4055 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
4056 + /* See if device thinks it succeeded */
4057 + if (status & 0x01) {
4058 + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page);
4059 + FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
4060 + return -EIO;
4061 + }
4062 +
4063 +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
4064 + /*
4065 + * The NAND device assumes that it is always writing to
4066 + * a cleanly erased page. Hence, it performs its internal
4067 + * write verification only on bits that transitioned from
4068 + * 1 to 0. The device does NOT verify the whole page on a
4069 + * byte by byte basis. It is possible that the page was
4070 + * not completely erased or the page is becoming unusable
4071 + * due to wear. The read with ECC would catch the error
4072 + * later when the ECC page check fails, but we would rather
4073 + * catch it early in the page write stage. Better to write
4074 + * no data than invalid data.
4075 + */
4076 +
4077 + /* Send command to read back the page */
4078 + this->cmdfunc (mtd, NAND_CMD_READ0, 0, page);
4079 + /* Loop through and verify the data */
4080 + if (this->verify_buf(mtd, this->data_poi, mtd->oobblock)) {
4081 + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
4082 + return -EIO;
4083 + }
4084 +
4085 + /* check, if we have a fs-supplied oob-buffer */
4086 + if (oob_buf) {
4087 + if (this->verify_buf(mtd, oob_data, mtd->oobsize)) {
4088 + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
4089 + return -EIO;
4090 + }
4091 + } else {
4092 + if (eccmode != NAND_ECC_NONE) {
4093 + int ecc_bytes = 0;
4094 +
4095 + switch (this->eccmode) {
4096 + case NAND_ECC_SOFT:
4097 + case NAND_ECC_HW3_256: ecc_bytes = (mtd->oobblock == 512) ? 6 : 3; break;
4098 + case NAND_ECC_HW3_512: ecc_bytes = 3; break;
4099 + case NAND_ECC_HW6_512: ecc_bytes = 6; break;
4100 + }
4101 +
4102 +
4103 +
4104 + for(i=0;i < (mtd->oobblock+mtd->oobsize);i++)
4105 + {
4106 + if(i>=mtd->oobblock)
4107 + oob_data[i-mtd->oobblock] = FLASH_READ_DATA((page*mtd->oobblock) +i);
4108 + else
4109 + oob_data[0] = FLASH_READ_DATA((page*mtd->oobblock) +i);
4110 + }
4111 +
4112 + if(this->eccmode == NAND_ECC_HW3_512)
4113 + {
4114 + for(i=0;i<(mtd->oobblock/512);i++)
4115 + {
4116 + for(j=0;j<3;j++)
4117 + {
4118 + if (oob_data[mtd->oobsize-1-j-4*i] != ecc_code[15-j-4*i]) {
4119 + DEBUG (MTD_DEBUG_LEVEL0,
4120 + "%s: Failed ECC write "
4121 + "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
4122 + return -EIO;
4123 + }
4124 + }
4125 + }
4126 + }
4127 + }//eccmode != NAND_ECC_NONE
4128 + }
4129 + /*
4130 + * Terminate the read command. This is faster than sending a reset command or
4131 + * applying a 20us delay before issuing the next programm sequence.
4132 + * This is not a problem for all chips, but I have found a bunch of them.
4133 + */
4134 + //this->select_chip(mtd, -1);
4135 + //this->select_chip(mtd, 0);
4136 +#endif
4137 +
4138 + return 0;
4139 +}
4140 +
4141 +/*
4142 + * NAND write with iovec
4143 + */
4144 +static int sl2312_nand_writev (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
4145 + loff_t to, size_t * retlen)
4146 +{
4147 + return (sl2312_nand_writev_ecc (mtd, vecs, count, to, retlen, NULL, 0));
4148 +}
4149 +
4150 +static int sl2312_nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
4151 + loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel)
4152 +{
4153 + int i, page, len, total_len, ret = 0, written = 0;
4154 + struct nand_chip *this = mtd->priv;
4155 +
4156 + /* Calculate total length of data */
4157 + total_len = 0;
4158 + for (i = 0; i < count; i++)
4159 + total_len += (int) vecs[i].iov_len;
4160 +
4161 + DEBUG (MTD_DEBUG_LEVEL3,
4162 + "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
4163 +
4164 + /* Do not allow write past end of page */
4165 + if ((to + total_len) > mtd->size) {
4166 + DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n");
4167 + return -EINVAL;
4168 + }
4169 +
4170 + /* reject writes, which are not page aligned */
4171 + if (NOTALIGNED (to) || NOTALIGNED(total_len)) {
4172 + printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
4173 + return -EINVAL;
4174 + }
4175 +
4176 + // if oobsel is NULL, use chip defaults
4177 + if (oobsel == NULL)
4178 + oobsel = &mtd->oobinfo;
4179 +
4180 + /* Shift to get page */
4181 + page = ((int) to) >> this->page_shift;
4182 +
4183 + /* Grab the lock and see if the device is available */
4184 + sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
4185 +
4186 + /* Select the NAND device */
4187 + this->select_chip(mtd, 0);
4188 +
4189 + /* Check the WP bit */
4190 + if (!(sl2312_device_ready(mtd) & 0x80)) {
4191 + DEBUG (MTD_DEBUG_LEVEL0, "sl2312_nand_writev_ecc: Device is write protected!!!\n");
4192 + ret = -EIO;
4193 + goto out;
4194 + }
4195 +
4196 + /* Loop until all iovecs' data has been written */
4197 + len = 0;
4198 + while (count) {
4199 + /*
4200 + * Check, if the tuple gives us not enough data for a
4201 + * full page write. Then we can use the iov direct,
4202 + * else we have to copy into data_buf.
4203 + */
4204 + if ((vecs->iov_len - len) >= mtd->oobblock) {
4205 + this->data_poi = (u_char *) vecs->iov_base;
4206 + this->data_poi += len;
4207 + len += mtd->oobblock;
4208 + /* Check, if we have to switch to the next tuple */
4209 + if (len >= (int) vecs->iov_len) {
4210 + vecs++;
4211 + len = 0;
4212 + count--;
4213 + }
4214 + } else {
4215 + /*
4216 + * Read data out of each tuple until we have a full page
4217 + * to write or we've read all the tuples.
4218 + */
4219 + int cnt = 0;
4220 + while ((cnt < mtd->oobblock) && count) {
4221 + if (vecs->iov_base != NULL && vecs->iov_len) {
4222 + this->data_buf[cnt++] = ((u_char *) vecs->iov_base)[len++];
4223 + }
4224 + /* Check, if we have to switch to the next tuple */
4225 + if (len >= (int) vecs->iov_len) {
4226 + vecs++;
4227 + len = 0;
4228 + count--;
4229 + }
4230 + }
4231 + this->data_poi = this->data_buf;
4232 + }
4233 +
4234 + /* We use the same function for write and writev !) */
4235 + ret = sl2312_nand_write_page (mtd, this, page, NULL, oobsel);
4236 + if (ret)
4237 + goto out;
4238 +
4239 + /* Update written bytes count */
4240 + written += mtd->oobblock;;
4241 +
4242 + /* Increment page address */
4243 + page++;
4244 + }
4245 +
4246 +out:
4247 + /* De-select the NAND device */
4248 + //this->select_chip(mtd, -1);
4249 +
4250 + /* Wake up anyone waiting on the device */
4251 + spin_lock_bh (&this->chip_lock);
4252 + this->state = FL_READY;
4253 + wake_up (&this->wq);
4254 + spin_unlock_bh (&this->chip_lock);
4255 +
4256 + *retlen = written;
4257 + return ret;
4258 +}
4259 +
4260 +/*
4261 +static u_char ffchars[] = {
4262 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4263 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
4264 +};
4265 +*/
4266 +/*
4267 + * NAND write out-of-band
4268 + */
4269 +static int sl2312_nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
4270 +{
4271 + int column, page, status, ret = 0, j=0;
4272 + struct nand_chip *this = mtd->priv;
4273 + u_char *databuf, *oobbuf;
4274 +
4275 +
4276 + databuf = &this->data_buf[0];
4277 + oobbuf = &this->data_buf[mtd->oobblock];
4278 + for (j = 0; j < mtd->oobsize; j++)
4279 + oobbuf[j] = 0xff;
4280 +//#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
4281 +// int i;
4282 +//#endif
4283 +
4284 + DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
4285 +
4286 + /* Shift to get page */
4287 + page = ((int) to) >> this->page_shift;
4288 +
4289 + /* Mask to get column */
4290 + column = to & 0x1f;
4291 +
4292 + /* Initialize return length value */
4293 + *retlen = 0;
4294 +
4295 + /* Do not allow write past end of page */
4296 + if ((column + len) > mtd->oobsize) {
4297 + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n");
4298 + return -EINVAL;
4299 + }
4300 +
4301 + /* Grab the lock and see if the device is available */
4302 + sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
4303 +
4304 + /* Select the NAND device */
4305 + this->select_chip(mtd, 0);
4306 +
4307 + /* Reset the chip. Some chips (like the Toshiba TC5832DC found
4308 + in one of my DiskOnChip 2000 test units) will clear the whole
4309 + data page too if we don't do this. I have no clue why, but
4310 + I seem to have 'fixed' it in the doc2000 driver in
4311 + August 1999. dwmw2. */
4312 + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4313 +
4314 + /* Check the WP bit */
4315 + if (!(sl2312_device_ready(mtd) & 0x80)) {
4316 + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Device is write protected!!!\n");
4317 + ret = -EIO;
4318 + goto out;
4319 + }
4320 + /* Write out desired data */
4321 + this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page);
4322 +
4323 + sl2312_nand_read_ecc (mtd, page, mtd->oobblock , retlen, databuf, oobbuf, NULL);
4324 +
4325 + for(j=column;j<(column+len);j++)
4326 + oobbuf[j] = buf[j-column];
4327 + sl2312_nand_write_ecc (mtd, page, mtd->oobblock, retlen, databuf, oobbuf, NULL);
4328 +
4329 + status = this->waitfunc (mtd, this, FL_WRITING);
4330 +
4331 + /* See if device thinks it succeeded */
4332 + if (status & 0x01) {
4333 + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page);
4334 + ret = -EIO;
4335 + goto out;
4336 + }
4337 + /* Return happy */
4338 + *retlen = len;
4339 +
4340 +
4341 +out:
4342 + /* De-select the NAND device */
4343 + //this->select_chip(mtd, -1);
4344 +
4345 + /* Wake up anyone waiting on the device */
4346 + spin_lock_bh (&this->chip_lock);
4347 + this->state = FL_READY;
4348 + wake_up (&this->wq);
4349 + spin_unlock_bh (&this->chip_lock);
4350 +
4351 + return ret;
4352 +}
4353 +
4354 +/*
4355 + * NAND sync
4356 + */
4357 +static void sl2312_nand_sync (struct mtd_info *mtd)
4358 +{
4359 + struct nand_chip *this = mtd->priv;
4360 + DECLARE_WAITQUEUE (wait, current);
4361 +
4362 + DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
4363 +
4364 +retry:
4365 + /* Grab the spinlock */
4366 + spin_lock_bh (&this->chip_lock);
4367 +
4368 + /* See what's going on */
4369 + switch (this->state) {
4370 + case FL_READY:
4371 + case FL_SYNCING:
4372 + this->state = FL_SYNCING;
4373 + spin_unlock_bh (&this->chip_lock);
4374 + break;
4375 +
4376 + default:
4377 + /* Not an idle state */
4378 + add_wait_queue (&this->wq, &wait);
4379 + spin_unlock_bh (&this->chip_lock);
4380 + schedule ();
4381 +
4382 + remove_wait_queue (&this->wq, &wait);
4383 + goto retry;
4384 + }
4385 +
4386 + /* Lock the device */
4387 + spin_lock_bh (&this->chip_lock);
4388 +
4389 + /* Set the device to be ready again */
4390 + if (this->state == FL_SYNCING) {
4391 + this->state = FL_READY;
4392 + wake_up (&this->wq);
4393 + }
4394 +
4395 + /* Unlock the device */
4396 + spin_unlock_bh (&this->chip_lock);
4397 +}
4398 +
4399 +
4400 +/*
4401 + * Scan for the NAND device
4402 + */
4403 +int sl2312_nand_scan (struct mtd_info *mtd, int maxchips)
4404 +{
4405 + int i, j, nand_maf_id, nand_dev_id, busw;
4406 + struct nand_chip *this = mtd->priv;
4407 + unsigned char id[4];
4408 +
4409 + /* Get buswidth to select the correct functions*/
4410 + busw = this->options & NAND_BUSWIDTH_16;
4411 +
4412 + /* check for proper chip_delay setup, set 20us if not */
4413 + if (!this->chip_delay)
4414 + this->chip_delay = 20;
4415 +
4416 + /* check, if a user supplied command function given */
4417 + if (this->cmdfunc == NULL)
4418 + this->cmdfunc = sl2312_nand_command;
4419 +
4420 + /* check, if a user supplied wait function given */
4421 + if (this->waitfunc == NULL)
4422 + this->waitfunc = sl2312_nand_waitfunc;
4423 +
4424 + if (!this->select_chip)
4425 + this->select_chip = sl2312_nand_select_chip;
4426 + if (!this->write_byte)
4427 + this->write_byte = sl2312_nand_write_byte; //busw ? nand_write_byte16 : nand_write_byte;
4428 + if (!this->read_byte)
4429 + this->read_byte = sl2312_nand_read_byte; //busw ? nand_read_byte16 : nand_read_byte;
4430 +// if (!this->write_word)
4431 +// this->write_word = nand_write_word;
4432 +// if (!this->read_word)
4433 +// this->read_word = nand_read_word;
4434 +// if (!this->block_bad)
4435 + this->block_bad = sl2312_nand_block_bad; //nand_block_bad;
4436 + if (!this->block_markbad)
4437 + this->block_markbad = sl2312_nand_default_block_markbad;
4438 + if (!this->write_buf)
4439 + this->write_buf = sl2312_nand_write_buf; //busw ? nand_write_buf16 : nand_write_buf;
4440 + if (!this->read_buf)
4441 + this->read_buf = sl2312_nand_read_buf; //busw ? nand_read_buf16 : nand_read_buf;
4442 + if (!this->verify_buf)
4443 + this->verify_buf = sl2312_nand_verify_buf; //busw ? nand_verify_buf16 : nand_verify_buf;
4444 + if (!this->scan_bbt)
4445 + this->scan_bbt = sl2312_nand_scan_bbt;
4446 +
4447 + /* Select the device */
4448 + this->select_chip(mtd, 0);
4449 +
4450 + /* Read manufacturer and device IDs */
4451 + nand_read_id(0,id);
4452 +
4453 + nand_maf_id = id[0];
4454 + nand_dev_id = id[1];
4455 +
4456 + /* Print and store flash device information */
4457 + for (i = 0; nand_flash_ids[i].name != NULL; i++) {
4458 +
4459 + if (nand_dev_id != nand_flash_ids[i].id)
4460 + continue;
4461 +
4462 + if (!mtd->name) mtd->name = nand_flash_ids[i].name;
4463 + this->chipsize = nand_flash_ids[i].chipsize << 20;
4464 +
4465 + /* New devices have all the information in additional id bytes */
4466 + if (!nand_flash_ids[i].pagesize) {
4467 + int extid;
4468 +
4469 + /* The 4th id byte is the important one */
4470 + extid = id[3];
4471 + /* Calc pagesize */
4472 + mtd->oobblock = 1024 << (extid & 0x3);
4473 + extid >>= 2;
4474 + /* Calc oobsize */
4475 + mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512);
4476 + extid >>= 2;
4477 + /* Calc blocksize. Blocksize is multiples of 64KiB */
4478 + mtd->erasesize = (64 * 1024) << (extid & 0x03);
4479 + extid >>= 2;
4480 + /* Get buswidth information */
4481 + busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
4482 +
4483 + } else {
4484 + /* Old devices have this data hardcoded in the
4485 + * device id table */
4486 + mtd->erasesize = nand_flash_ids[i].erasesize;
4487 + mtd->oobblock = nand_flash_ids[i].pagesize;
4488 + mtd->oobsize = mtd->oobblock / 32;
4489 + busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
4490 + }
4491 +
4492 + /* Check, if buswidth is correct. Hardware drivers should set
4493 + * this correct ! */
4494 + if (busw != (this->options & NAND_BUSWIDTH_16)) {
4495 + printk (KERN_INFO "NAND device: Manufacturer ID:"
4496 + " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
4497 + nand_manuf_ids[i].name , mtd->name);
4498 + printk (KERN_WARNING
4499 + "NAND bus width %d instead %d bit\n",
4500 + (this->options & NAND_BUSWIDTH_16) ? 16 : 8,
4501 + busw ? 16 : 8);
4502 + this->select_chip(mtd, -1);
4503 + return 1;
4504 + }
4505 +
4506 + /* Calculate the address shift from the page size */
4507 + this->page_shift = ffs(mtd->oobblock) - 1;
4508 + this->bbt_erase_shift = this->phys_erase_shift = ffs(mtd->erasesize) - 1;
4509 + this->chip_shift = ffs(this->chipsize) - 1;
4510 +
4511 + /* Set the bad block position */
4512 + this->badblockpos = mtd->oobblock > 512 ?
4513 + NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
4514 +
4515 + /* Get chip options, preserve non chip based options */
4516 + this->options &= ~NAND_CHIPOPTIONS_MSK;
4517 + this->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
4518 + /* Set this as a default. Board drivers can override it, if neccecary */
4519 + this->options |= NAND_NO_AUTOINCR;
4520 + /* Check if this is a not a samsung device. Do not clear the options
4521 + * for chips which are not having an extended id.
4522 + */
4523 + if (nand_maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
4524 + this->options &= ~NAND_SAMSUNG_LP_OPTIONS;
4525 +
4526 + /* Check for AND chips with 4 page planes */
4527 + // if (this->options & NAND_4PAGE_ARRAY)
4528 + // this->erase_cmd = multi_erase_cmd;
4529 + // else
4530 + // this->erase_cmd = single_erase_cmd;
4531 +
4532 + /* Do not replace user supplied command function ! */
4533 + // if (mtd->oobblock > 512 && this->cmdfunc == nand_command)
4534 + // this->cmdfunc = nand_command_lp;
4535 +
4536 + /* Try to identify manufacturer */
4537 + for (j = 0; nand_manuf_ids[j].id != 0x0; j++) {
4538 + if (nand_manuf_ids[j].id == nand_maf_id)
4539 + break;
4540 + }
4541 + printk (KERN_INFO "NAND device: Manufacturer ID:"
4542 + " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
4543 + nand_manuf_ids[j].name , nand_flash_ids[i].name);
4544 + break;
4545 + }
4546 + /////////////////////////////
4547 +
4548 + for (i=1; i < maxchips; i++) {
4549 + this->select_chip(mtd, i);
4550 +
4551 + /* Send the command for reading device ID */
4552 + nand_read_id(1,id);
4553 +
4554 + /* Read manufacturer and device IDs */
4555 + if (nand_maf_id != id[0] ||
4556 + nand_dev_id != id[1])
4557 + break;
4558 + }
4559 + if (i > 1)
4560 + printk(KERN_INFO "%d NAND chips detected\n", i);
4561 +
4562 + /* Allocate buffers, if neccecary */
4563 + if (!this->oob_buf) {
4564 + size_t len;
4565 + len = mtd->oobsize << (this->phys_erase_shift - this->page_shift);
4566 + this->oob_buf = kmalloc (len, GFP_KERNEL);
4567 + if (!this->oob_buf) {
4568 + printk (KERN_ERR "nand_scan(): Cannot allocate oob_buf\n");
4569 + return -ENOMEM;
4570 + }
4571 + this->options |= NAND_OOBBUF_ALLOC;
4572 + }
4573 +
4574 + if (!this->data_buf) {
4575 + size_t len;
4576 + len = mtd->oobblock + mtd->oobsize;
4577 + this->data_buf = kmalloc (len, GFP_KERNEL);
4578 + if (!this->data_buf) {
4579 + if (this->options & NAND_OOBBUF_ALLOC)
4580 + kfree (this->oob_buf);
4581 + printk (KERN_ERR "nand_scan(): Cannot allocate data_buf\n");
4582 + return -ENOMEM;
4583 + }
4584 + this->options |= NAND_DATABUF_ALLOC;
4585 + }
4586 +
4587 + /* Store the number of chips and calc total size for mtd */
4588 + this->numchips = i;
4589 + mtd->size = i * this->chipsize;
4590 + /* Convert chipsize to number of pages per chip -1. */
4591 + this->pagemask = (this->chipsize >> this->page_shift) - 1;
4592 + /* Preset the internal oob buffer */
4593 + memset(this->oob_buf, 0xff, mtd->oobsize << (this->phys_erase_shift - this->page_shift));
4594 +
4595 + /* If no default placement scheme is given, select an
4596 + * appropriate one */
4597 + if (!this->autooob) {
4598 + /* Select the appropriate default oob placement scheme for
4599 + * placement agnostic filesystems */
4600 + switch (mtd->oobsize) {
4601 + case 8:
4602 + this->autooob = &nand_oob_8;
4603 + break;
4604 + case 16:
4605 + this->autooob = &nand_oob_16;
4606 + break;
4607 + case 64:
4608 + this->autooob = &nand_oob_64;
4609 + break;
4610 + default:
4611 + printk (KERN_WARNING "No oob scheme defined for oobsize %d\n",
4612 + mtd->oobsize);
4613 + BUG();
4614 + }
4615 + }
4616 +
4617 + /* The number of bytes available for the filesystem to place fs dependend
4618 + * oob data */
4619 + if (this->options & NAND_BUSWIDTH_16) {
4620 + mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2);
4621 + if (this->autooob->eccbytes & 0x01)
4622 + mtd->oobavail--;
4623 + } else
4624 + mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1);
4625 +
4626 +
4627 + /*
4628 + * check ECC mode, default to software
4629 + * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize
4630 + * fallback to software ECC
4631 + */
4632 + this->eccsize = 256; /* set default eccsize */
4633 + this->eccbytes = 3;
4634 +
4635 + switch (this->eccmode) {
4636 + case NAND_ECC_HW12_2048:
4637 + if (mtd->oobblock < 2048) {
4638 + printk(KERN_WARNING "2048 byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4639 + mtd->oobblock);
4640 + this->eccmode = NAND_ECC_SOFT;
4641 + this->calculate_ecc = nand_calculate_ecc;
4642 + this->correct_data = nand_correct_data;
4643 + } else
4644 + this->eccsize = 2048;
4645 + break;
4646 +
4647 + case NAND_ECC_HW3_512:
4648 + case NAND_ECC_HW6_512:
4649 + case NAND_ECC_HW8_512:
4650 + if (mtd->oobblock == 256) {
4651 + printk (KERN_WARNING "512 byte HW ECC not possible on 256 Byte pagesize, fallback to SW ECC \n");
4652 + this->eccmode = NAND_ECC_SOFT;
4653 + this->calculate_ecc = nand_calculate_ecc;
4654 + this->correct_data = nand_correct_data;
4655 + } else
4656 + this->eccsize = 512; /* set eccsize to 512 */
4657 + break;
4658 +
4659 + case NAND_ECC_HW3_256:
4660 + break;
4661 +
4662 + case NAND_ECC_NONE:
4663 + printk (KERN_WARNING "NAND_ECC_NONE selected by board driver. This is not recommended !!\n");
4664 + this->eccmode = NAND_ECC_NONE;
4665 + break;
4666 +
4667 + case NAND_ECC_SOFT:
4668 + this->calculate_ecc = nand_calculate_ecc;
4669 + this->correct_data = nand_correct_data;
4670 + break;
4671 +
4672 + default:
4673 + printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
4674 + BUG();
4675 + }
4676 +
4677 + /* Check hardware ecc function availability and adjust number of ecc bytes per
4678 + * calculation step
4679 + */
4680 + switch (this->eccmode) {
4681 + case NAND_ECC_HW12_2048:
4682 + this->eccbytes += 4;
4683 + case NAND_ECC_HW8_512:
4684 + this->eccbytes += 2;
4685 + case NAND_ECC_HW6_512:
4686 + this->eccbytes += 3;
4687 +// case NAND_ECC_HW3_512:
4688 + case NAND_ECC_HW3_256:
4689 + if (this->calculate_ecc && this->correct_data && this->enable_hwecc)
4690 + break;
4691 + printk (KERN_WARNING "No ECC functions supplied, Hardware ECC not possible\n");
4692 + BUG();
4693 + }
4694 +
4695 + mtd->eccsize = this->eccsize;
4696 +
4697 + /* Set the number of read / write steps for one page to ensure ECC generation */
4698 + switch (this->eccmode) {
4699 + case NAND_ECC_HW12_2048:
4700 + this->eccsteps = mtd->oobblock / 2048;
4701 + break;
4702 + case NAND_ECC_HW3_512:
4703 + case NAND_ECC_HW6_512:
4704 + case NAND_ECC_HW8_512:
4705 + this->eccsteps = mtd->oobblock / 512;
4706 + break;
4707 + case NAND_ECC_HW3_256:
4708 + case NAND_ECC_SOFT:
4709 + this->eccsteps = mtd->oobblock / 256;
4710 + break;
4711 +
4712 + case NAND_ECC_NONE:
4713 + this->eccsteps = 1;
4714 + break;
4715 + }
4716 +
4717 + /* Initialize state, waitqueue and spinlock */
4718 + this->state = FL_READY;
4719 + init_waitqueue_head (&this->wq);
4720 + spin_lock_init (&this->chip_lock);
4721 +
4722 + /* De-select the device */
4723 + this->select_chip(mtd, 0);
4724 +
4725 + /* Print warning message for no device */
4726 + if (!mtd->size) {
4727 + printk (KERN_WARNING "No NAND device found!!!\n");
4728 + return 1;
4729 + }
4730 +
4731 + /* Fill in remaining MTD driver data */
4732 + mtd->type = MTD_NANDFLASH;
4733 + mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC;
4734 + mtd->ecctype = MTD_ECC_SW;
4735 + mtd->erase = sl2312_nand_erase;
4736 + mtd->point = NULL;
4737 + mtd->unpoint = NULL;
4738 + mtd->read = sl2312_nand_read;
4739 + mtd->write = sl2312_nand_write;
4740 + mtd->read_ecc = sl2312_nand_read_ecc;
4741 + mtd->write_ecc = sl2312_nand_write_ecc;
4742 + mtd->read_oob = sl2312_nand_read_oob;
4743 + mtd->write_oob = sl2312_nand_write_oob;
4744 + mtd->readv = NULL;
4745 + mtd->writev = sl2312_nand_writev;
4746 + mtd->writev_ecc = sl2312_nand_writev_ecc;
4747 + mtd->sync = sl2312_nand_sync;
4748 + mtd->lock = NULL;
4749 + mtd->unlock = NULL;
4750 + mtd->suspend = NULL;
4751 + mtd->resume = NULL;
4752 + mtd->block_isbad = sl2312_nand_block_isbad;
4753 + mtd->block_markbad = sl2312_nand_block_markbad;
4754 +
4755 + /* and make the autooob the default one */
4756 + memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo));
4757 +
4758 + mtd->owner = THIS_MODULE;
4759 +
4760 + /* Build bad block table */
4761 + return this->scan_bbt (mtd);
4762 +}
4763 +
4764 +/*End Add function*/
4765 +
4766 +/*
4767 + * Main initialization routine
4768 + */
4769 +extern int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
4770 +
4771 +int __init sl2312_mtd_init (void)
4772 +{
4773 + struct nand_chip *this;
4774 + int err = 0;
4775 + struct mtd_partition *parts;
4776 + int nr_parts = 0;
4777 + int ret, data, *base;
4778 +
4779 + printk("NAND MTD Driver Start Init ......\n");
4780 +
4781 + base = (unsigned int *)(IO_ADDRESS(SL2312_GLOBAL_BASE) + 0x30);
4782 + data = *base;
4783 + data&=0xffffffeb;
4784 + data|=0x3; //disable p & s flash
4785 + *base = data;
4786 +
4787 + /* Allocate memory for MTD device structure and private data */
4788 + sl2312_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
4789 + if (!sl2312_mtd) {
4790 + printk ("Unable to allocate SL2312 NAND MTD device structure.\n");
4791 + err = -ENOMEM;
4792 + goto out;
4793 + }
4794 +
4795 + // sl2312_device_setup();
4796 +
4797 + /* io is indirect via a register so don't need to ioremap address */
4798 +
4799 + /* Get pointer to private data */
4800 + this = (struct nand_chip *) (&sl2312_mtd[1]);
4801 +
4802 + /* Initialize structures */
4803 + memset((char *) sl2312_mtd, 0, sizeof(struct mtd_info));
4804 + memset((char *) this, 0, sizeof(struct nand_chip));
4805 +
4806 + /* Link the private data with the MTD structure */
4807 + sl2312_mtd->priv = this;
4808 + sl2312_mtd->name = "sl2312-nand";
4809 +
4810 + /* Set address of NAND IO lines */
4811 + this->IO_ADDR_R = (void __iomem *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE+NFLASH_DATA)); //(unsigned long)&(sl2312_ndfmcptr->dtr);
4812 + this->IO_ADDR_W = (void __iomem *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE+NFLASH_DATA)); //(unsigned long)&(sl2312_ndfmcptr->dtr);
4813 + this->read_byte = sl2312_nand_read_byte;
4814 + this->write_byte = sl2312_nand_write_byte;
4815 + this->write_buf = sl2312_nand_write_buf;
4816 + this->read_buf = sl2312_nand_read_buf;
4817 + this->verify_buf = sl2312_nand_verify_buf;
4818 + this->select_chip = sl2312_nand_select_chip;
4819 + this->block_bad = sl2312_nand_block_bad;
4820 + this->hwcontrol = sl2312_hwcontrol;
4821 + this->dev_ready = sl2312_device_ready;
4822 + this->cmdfunc = sl2312_nand_command;
4823 + this->waitfunc = sl2312_nand_waitfunc;
4824 + //this->calculate_ecc = sl2312_readecc;
4825 + this->enable_hwecc = sl2312_enable_hwecc;
4826 + this->eccmode = NAND_ECC_HW3_512;
4827 + /*this->eccsize = 512; */
4828 + /* 20 us command delay time */
4829 + this->chip_delay = 20;
4830 +
4831 + this->correct_data = nand_correct_data;
4832 +// this->scan_bbt = sl2312_nand_scan_bbt;
4833 +
4834 + /* Allocate memory for internal data buffer */
4835 + this->data_buf = kmalloc (sizeof(u_char) * (sl2312_mtd->oobblock + sl2312_mtd->oobsize), GFP_KERNEL);
4836 + if (!this->data_buf) {
4837 + printk ("Unable to allocate NAND data buffer.\n");
4838 + err = -ENOMEM;
4839 + goto out_ior;
4840 + }
4841 +
4842 + /* Scan to find existance of the device */
4843 + if (sl2312_nand_scan(sl2312_mtd, 1)) {
4844 + err = -ENXIO;
4845 + goto out_ior;
4846 + }
4847 +
4848 + /* Register the partitions */
4849 + parts = sl2312_partitions;
4850 + nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
4851 +
4852 + ret = add_mtd_partitions(sl2312_mtd, sl2312_partitions, nr_parts);
4853 + /*If we got an error, free all resources.*/
4854 + if (ret < 0) {
4855 + del_mtd_partitions(sl2312_mtd);
4856 + map_destroy(sl2312_mtd);
4857 + }
4858 + goto out;
4859 +
4860 +//out_buf:
4861 +// kfree (this->data_buf);
4862 +out_ior:
4863 +out:
4864 + printk("NAND MTD Driver Init Success ......\n");
4865 + return err;
4866 +}
4867 +
4868 +module_init(sl2312_mtd_init);
4869 +
4870 +/*
4871 + * Clean up routine
4872 + */
4873 +#ifdef MODULE
4874 +static void __exit sl2312_cleanup (void)
4875 +{
4876 + struct nand_chip *this = (struct nand_chip *) &sl2312_mtd[1];
4877 +
4878 + /* Unregister partitions */
4879 + del_mtd_partitions(sl2312_mtd);
4880 +
4881 + /* Unregister the device */
4882 + del_mtd_device (sl2312_mtd);
4883 +
4884 + /* Free internal data buffers */
4885 + kfree (this->data_buf);
4886 +
4887 + /* Free the MTD device structure */
4888 + kfree (sl2312_mtd);
4889 +}
4890 +module_exit(sl2312_cleanup);
4891 +#endif
4892 +
4893 +MODULE_LICENSE("GPL");
4894 +MODULE_AUTHOR("Alice Hennessy <ahennessy@mvista.com>");
4895 +MODULE_DESCRIPTION("Glue layer for SmartMediaCard on Toshiba RBsl2312");
4896 Index: linux-2.6.23.16/drivers/mtd/nand/sl2312-flash-nand.h
4897 ===================================================================
4898 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4899 +++ linux-2.6.23.16/drivers/mtd/nand/sl2312-flash-nand.h 2008-03-15 17:04:25.878696749 +0200
4900 @@ -0,0 +1,24 @@
4901 +#ifndef SL2312_FLASH_NAND_H
4902 +#define SL2312_FLASH_NAND_H
4903 +
4904 +#include <linux/wait.h>
4905 +#include <linux/spinlock.h>
4906 +
4907 +/*Add function*/
4908 +static void nand_read_id(int chip_no,unsigned char *id);
4909 +
4910 +
4911 +
4912 +#define NFLASH_WiDTH8 0x00000000
4913 +#define NFLASH_WiDTH16 0x00000400
4914 +#define NFLASH_WiDTH32 0x00000800
4915 +#define NFLASH_CHIP0_EN 0x00000000 // 16th bit = 0
4916 +#define NFLASH_CHIP1_EN 0x00010000 // 16th bit = 1
4917 +#define NFLASH_DIRECT 0x00004000
4918 +#define NFLASH_INDIRECT 0x00000000
4919 +
4920 +
4921 +#define DWIDTH NFLASH_WiDTH8
4922 +
4923 +
4924 +#endif /* SL2312_FLASH_NAND_H */
4925 Index: linux-2.6.23.16/include/linux/mtd/kvctl.h
4926 ===================================================================
4927 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4928 +++ linux-2.6.23.16/include/linux/mtd/kvctl.h 2008-03-15 17:03:17.874821522 +0200
4929 @@ -0,0 +1,40 @@
4930 +#ifndef KVCTL_H
4931 +#define KVCTL_H
4932 +
4933 +#define VCTL_HEAD_SIZE 8
4934 +#define VCTL_ENTRY_LEN 20
4935 +
4936 +typedef struct
4937 +{
4938 + char header[4];
4939 + unsigned int entry_num;
4940 +} vctl_mheader;
4941 +
4942 +typedef struct
4943 +{
4944 + char header[4];
4945 + unsigned int size;
4946 + unsigned int type;
4947 + char majorver[4];
4948 + char minorver[4];
4949 + unsigned char *payload;
4950 +} vctl_entry;
4951 +
4952 +typedef struct
4953 +{
4954 + unsigned char mac[6];
4955 + unsigned char vlanid;
4956 + unsigned char vlanmap;
4957 +} vlaninfo;
4958 +
4959 +#define VCT_VENDORSPEC 0
4960 +#define VCT_BOOTLOADER 1
4961 +#define VCT_KERNEL 2
4962 +#define VCT_VERCTL 3
4963 +#define VCT_CURRCONF 4
4964 +#define VCT_DEFAULTCONF 5
4965 +#define VCT_ROOTFS 6
4966 +#define VCT_APP 7
4967 +#define VCT_VLAN 8
4968 +
4969 +#endif
4970 Index: linux-2.6.23.16/drivers/mtd/maps/Makefile
4971 ===================================================================
4972 --- linux-2.6.23.16.orig/drivers/mtd/maps/Makefile 2008-03-15 17:03:14.374622039 +0200
4973 +++ linux-2.6.23.16/drivers/mtd/maps/Makefile 2008-03-15 17:03:17.874821522 +0200
4974 @@ -71,3 +71,7 @@
4975 obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o
4976 obj-$(CONFIG_MTD_MTX1) += mtx-1_flash.o
4977 obj-$(CONFIG_MTD_TQM834x) += tqm834x.o
4978 +###### for Storlink Soc #######
4979 +obj-$(CONFIG_MTD_SL2312_CFI) += sl2312-flash-cfi.o
4980 +obj-$(CONFIG_MTD_SL2312_SERIAL_ATMEL) += sl2312-flash-atmel.o
4981 +obj-$(CONFIG_MTD_SL2312_SERIAL_ST) += sl2312-flash-m25p80.o
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