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[xburst] jz_mmc: Fix timeout timer. Annotate timeout checks as unlikely()
[openwrt/svn-archive/archive.git] / target / linux / xburst / files-2.6.32 / drivers / mmc / host / jz_mmc.c
1 /*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ7420/JZ4740 GPIO SD/MMC controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16 #include <linux/mmc/host.h>
17 #include <linux/io.h>
18 #include <linux/irq.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/delay.h>
23 #include <linux/scatterlist.h>
24 #include <linux/clk.h>
25 #include <linux/mmc/jz4740_mmc.h>
26
27 #include <linux/gpio.h>
28 #include <asm/mach-jz4740/gpio.h>
29 #include <asm/cacheflush.h>
30 #include <linux/dma-mapping.h>
31
32 #define JZ_REG_MMC_STRPCL 0x00
33 #define JZ_REG_MMC_STATUS 0x04
34 #define JZ_REG_MMC_CLKRT 0x08
35 #define JZ_REG_MMC_CMDAT 0x0C
36 #define JZ_REG_MMC_RESTO 0x10
37 #define JZ_REG_MMC_RDTO 0x14
38 #define JZ_REG_MMC_BLKLEN 0x18
39 #define JZ_REG_MMC_NOB 0x1C
40 #define JZ_REG_MMC_SNOB 0x20
41 #define JZ_REG_MMC_IMASK 0x24
42 #define JZ_REG_MMC_IREG 0x28
43 #define JZ_REG_MMC_CMD 0x2C
44 #define JZ_REG_MMC_ARG 0x30
45 #define JZ_REG_MMC_RESP_FIFO 0x34
46 #define JZ_REG_MMC_RXFIFO 0x38
47 #define JZ_REG_MMC_TXFIFO 0x3C
48
49 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
50 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
51 #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
52 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
53 #define JZ_MMC_STRPCL_RESET BIT(3)
54 #define JZ_MMC_STRPCL_START_OP BIT(2)
55 #define JZ_MMC_STRPCL_CLOCK_CONTROL BIT(1) | BIT(0)
56 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
57 #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
58
59
60 #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
61 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
62 #define JZ_MMC_STATUS_PRG_DONE BIT(13)
63 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
64 #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
65 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
66 #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
67 #define JZ_MMC_STATUS_CLK_EN BIT(8)
68 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
69 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
70 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
71 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
72 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
73 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
74 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
75 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
76
77 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
78 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
79
80
81 #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
82 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
83 #define JZ_MMC_CMDAT_DMA_EN BIT(8)
84 #define JZ_MMC_CMDAT_INIT BIT(7)
85 #define JZ_MMC_CMDAT_BUSY BIT(6)
86 #define JZ_MMC_CMDAT_STREAM BIT(5)
87 #define JZ_MMC_CMDAT_WRITE BIT(4)
88 #define JZ_MMC_CMDAT_DATA_EN BIT(3)
89 #define JZ_MMC_CMDAT_RESPONSE_FORMAT BIT(2) | BIT(1) | BIT(0)
90 #define JZ_MMC_CMDAT_RSP_R1 1
91 #define JZ_MMC_CMDAT_RSP_R2 2
92 #define JZ_MMC_CMDAT_RSP_R3 3
93
94 #define JZ_MMC_IRQ_SDIO BIT(7)
95 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
96 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
97 #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
98 #define JZ_MMC_IRQ_PRG_DONE BIT(1)
99 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
100
101
102 #define JZ_MMC_CLK_RATE 24000000
103
104 #define JZ4740_MMC_MAX_TIMEOUT 10000000
105
106 struct jz4740_mmc_host {
107 struct mmc_host *mmc;
108 struct platform_device *pdev;
109 struct jz4740_mmc_platform_data *pdata;
110 struct clk *clk;
111
112 int irq;
113 int card_detect_irq;
114
115 struct resource *mem;
116 void __iomem *base;
117 struct mmc_request *req;
118 struct mmc_command *cmd;
119
120 int max_clock;
121 uint32_t cmdat;
122
123 uint16_t irq_mask;
124
125 spinlock_t lock;
126 struct timer_list clock_timer;
127 struct timer_list timeout_timer;
128 unsigned waiting:1;
129 };
130
131 static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host);
132
133 static void jz4740_mmc_enable_irq(struct jz4740_mmc_host *host, unsigned int irq)
134 {
135 unsigned long flags;
136 spin_lock_irqsave(&host->lock, flags);
137
138 host->irq_mask &= ~irq;
139 writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
140
141 spin_unlock_irqrestore(&host->lock, flags);
142 }
143
144 static void jz4740_mmc_disable_irq(struct jz4740_mmc_host *host, unsigned int irq)
145 {
146 unsigned long flags;
147 spin_lock_irqsave(&host->lock, flags);
148
149 host->irq_mask |= irq;
150 writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
151
152 spin_unlock_irqrestore(&host->lock, flags);
153 }
154
155 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, bool start_transfer)
156 {
157 uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
158
159 if (start_transfer)
160 val |= JZ_MMC_STRPCL_START_OP;
161
162 writew(val, host->base + JZ_REG_MMC_STRPCL);
163 }
164
165 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
166 {
167 uint16_t status;
168 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
169 do {
170 status = readl(host->base + JZ_REG_MMC_STATUS);
171 } while (status & JZ_MMC_STATUS_CLK_EN);
172
173 }
174
175 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
176 {
177 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
178 udelay(10);
179 while(readw(host->base + JZ_REG_MMC_STATUS) & JZ_MMC_STATUS_IS_RESETTING);
180 }
181
182 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
183 {
184 struct mmc_request *req;
185 unsigned long flags;
186
187 spin_lock_irqsave(&host->lock, flags);
188 req = host->req;
189 host->req = NULL;
190 host->waiting = 0;
191 spin_unlock_irqrestore(&host->lock, flags);
192
193 if (!unlikely(req))
194 return;
195
196 /* if (req->cmd->error != 0) {
197 printk("error\n");
198 jz4740_mmc_reset(host);
199 }*/
200
201 mmc_request_done(host->mmc, req);
202 }
203
204 static void jz4740_mmc_write_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
205 struct scatterlist *sg;
206 uint32_t *sg_pointer;
207 int status;
208 unsigned int timeout;
209 size_t i, j;
210
211 for (sg = data->sg; sg; sg = sg_next(sg)) {
212 sg_pointer = sg_virt(sg);
213 i = sg->length / 4;
214 j = i >> 3;
215 i = i & 0x7;
216 while (j) {
217 timeout = JZ4740_MMC_MAX_TIMEOUT;
218 do {
219 status = readw(host->base + JZ_REG_MMC_IREG);
220 } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ) && --timeout);
221 if (unlikely(timeout == 0))
222 goto err_timeout;
223
224 writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
225
226 writel(sg_pointer[0], host->base + JZ_REG_MMC_TXFIFO);
227 writel(sg_pointer[1], host->base + JZ_REG_MMC_TXFIFO);
228 writel(sg_pointer[2], host->base + JZ_REG_MMC_TXFIFO);
229 writel(sg_pointer[3], host->base + JZ_REG_MMC_TXFIFO);
230 writel(sg_pointer[4], host->base + JZ_REG_MMC_TXFIFO);
231 writel(sg_pointer[5], host->base + JZ_REG_MMC_TXFIFO);
232 writel(sg_pointer[6], host->base + JZ_REG_MMC_TXFIFO);
233 writel(sg_pointer[7], host->base + JZ_REG_MMC_TXFIFO);
234 sg_pointer += 8;
235 --j;
236 }
237 if (i) {
238 timeout = JZ4740_MMC_MAX_TIMEOUT;
239 do {
240 status = readw(host->base + JZ_REG_MMC_IREG);
241 } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ) && --timeout);
242 if (unlikely(timeout == 0))
243 goto err_timeout;
244
245 writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
246
247 while (i) {
248 writel(*sg_pointer, host->base + JZ_REG_MMC_TXFIFO);
249 ++sg_pointer;
250 --i;
251 }
252 }
253 data->bytes_xfered += sg->length;
254 }
255
256 status = readl(host->base + JZ_REG_MMC_STATUS);
257 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK)
258 goto err;
259
260 writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
261 timeout = JZ4740_MMC_MAX_TIMEOUT;
262 do {
263 status = readl(host->base + JZ_REG_MMC_STATUS);
264 } while ((status & JZ_MMC_STATUS_DATA_TRAN_DONE) == 0 && --timeout);
265
266 if (unlikely(timeout == 0))
267 goto err_timeout;
268 writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
269
270 return;
271 err_timeout:
272 host->req->cmd->error = -ETIMEDOUT;
273 data->error = -ETIMEDOUT;
274 return;
275 err:
276 if(status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
277 host->req->cmd->error = -ETIMEDOUT;
278 data->error = -ETIMEDOUT;
279 } else {
280 host->req->cmd->error = -EILSEQ;
281 data->error = -EILSEQ;
282 }
283 }
284
285 static void jz4740_mmc_timeout(unsigned long data)
286 {
287 struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)data;
288 unsigned long flags;
289
290 spin_lock_irqsave(&host->lock, flags);
291 if (!host->waiting) {
292 spin_unlock_irqrestore(&host->lock, flags);
293 return;
294 }
295
296 host->waiting = 0;
297
298 spin_unlock_irqrestore(&host->lock, flags);
299
300 host->req->cmd->error = -ETIMEDOUT;
301 jz4740_mmc_request_done(host);
302 }
303
304 static void jz4740_mmc_read_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
305 struct scatterlist *sg;
306 uint32_t *sg_pointer;
307 uint32_t d;
308 uint16_t status = 0;
309 size_t i, j;
310 unsigned int timeout;
311
312 for (sg = data->sg; sg; sg = sg_next(sg)) {
313 sg_pointer = sg_virt(sg);
314 i = sg->length;
315 j = i >> 5;
316 i = i & 0x1f;
317 while (j) {
318 timeout = JZ4740_MMC_MAX_TIMEOUT;
319 do {
320 status = readw(host->base + JZ_REG_MMC_IREG);
321 } while (!(status & JZ_MMC_IRQ_RXFIFO_RD_REQ) && --timeout);
322
323 if (unlikely(timeout == 0))
324 goto err_timeout;
325
326 writew(JZ_MMC_IRQ_RXFIFO_RD_REQ, host->base + JZ_REG_MMC_IREG);
327
328 sg_pointer[0] = readl(host->base + JZ_REG_MMC_RXFIFO);
329 sg_pointer[1] = readl(host->base + JZ_REG_MMC_RXFIFO);
330 sg_pointer[2] = readl(host->base + JZ_REG_MMC_RXFIFO);
331 sg_pointer[3] = readl(host->base + JZ_REG_MMC_RXFIFO);
332 sg_pointer[4] = readl(host->base + JZ_REG_MMC_RXFIFO);
333 sg_pointer[5] = readl(host->base + JZ_REG_MMC_RXFIFO);
334 sg_pointer[6] = readl(host->base + JZ_REG_MMC_RXFIFO);
335 sg_pointer[7] = readl(host->base + JZ_REG_MMC_RXFIFO);
336
337 sg_pointer += 8;
338 --j;
339 }
340
341 while (i >= 4) {
342 timeout = JZ4740_MMC_MAX_TIMEOUT;
343 do {
344 status = readl(host->base + JZ_REG_MMC_STATUS);
345 } while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout);
346
347 if (unlikely(timeout == 0))
348 goto err_timeout;
349
350 *sg_pointer = readl(host->base + JZ_REG_MMC_RXFIFO);
351 ++sg_pointer;
352 i -= 4;
353 }
354 if (i > 0) {
355 d = readl(host->base + JZ_REG_MMC_RXFIFO);
356 memcpy(sg_pointer, &d, i);
357 }
358 data->bytes_xfered += sg->length;
359
360 flush_dcache_page(sg_page(sg));
361 }
362
363 status = readl(host->base + JZ_REG_MMC_STATUS);
364 if (status & JZ_MMC_STATUS_READ_ERROR_MASK)
365 goto err;
366
367 /* For whatever reason there is sometime one word more in the fifo then
368 * requested */
369 while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) == 0 && --timeout) {
370 d = readl(host->base + JZ_REG_MMC_RXFIFO);
371 status = readl(host->base + JZ_REG_MMC_STATUS);
372 }
373 return;
374 err_timeout:
375 host->req->cmd->error = -ETIMEDOUT;
376 data->error = -ETIMEDOUT;
377 return;
378 err:
379 if(status & JZ_MMC_STATUS_TIMEOUT_READ) {
380 host->req->cmd->error = -ETIMEDOUT;
381 data->error = -ETIMEDOUT;
382 } else {
383 host->req->cmd->error = -EILSEQ;
384 data->error = -EILSEQ;
385 }
386 }
387
388 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
389 {
390 struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)devid;
391
392 if (host->cmd->error)
393 jz4740_mmc_request_done(host);
394 else
395 jz4740_mmc_cmd_done(host);
396
397 return IRQ_HANDLED;
398 }
399
400 static irqreturn_t jz_mmc_irq(int irq, void *devid)
401 {
402 struct jz4740_mmc_host *host = devid;
403 uint16_t irq_reg, status, tmp;
404 unsigned long flags;
405 irqreturn_t ret = IRQ_HANDLED;
406
407 irq_reg = readw(host->base + JZ_REG_MMC_IREG);
408
409 tmp = irq_reg;
410 spin_lock_irqsave(&host->lock, flags);
411 irq_reg &= ~host->irq_mask;
412 spin_unlock_irqrestore(&host->lock, flags);
413
414 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
415 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
416
417 if (tmp != irq_reg) {
418 dev_warn(&host->pdev->dev, "Sparse irq: %x\n", tmp & ~irq_reg);
419 writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
420 }
421
422
423 if (irq_reg & JZ_MMC_IRQ_SDIO) {
424 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
425 mmc_signal_sdio_irq(host->mmc);
426 }
427
428 if (!host->req || !host->cmd) {
429 goto handled;
430 }
431
432
433 spin_lock_irqsave(&host->lock, flags);
434 if (!host->waiting) {
435 spin_unlock_irqrestore(&host->lock, flags);
436 goto handled;
437 }
438
439 host->waiting = 0;
440 spin_unlock_irqrestore(&host->lock, flags);
441
442 del_timer(&host->timeout_timer);
443
444 status = readl(host->base + JZ_REG_MMC_STATUS);
445
446 if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
447 host->cmd->error = -ETIMEDOUT;
448 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
449 host->cmd->error = -EIO;
450 } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
451 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
452 host->cmd->data->error = -EIO;
453 } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
454 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
455 host->cmd->data->error = -EIO;
456 }
457
458 if (irq_reg & JZ_MMC_IRQ_END_CMD_RES) {
459 jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
460 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
461 ret = IRQ_WAKE_THREAD;
462 }
463
464 return ret;
465 handled:
466
467 writew(0xff, host->base + JZ_REG_MMC_IREG);
468 return IRQ_HANDLED;
469 }
470
471 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) {
472 int div = 0;
473 int real_rate;
474
475 jz4740_mmc_clock_disable(host);
476 clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
477
478 real_rate = clk_get_rate(host->clk);
479
480 while (real_rate > rate && div < 7) {
481 ++div;
482 real_rate >>= 1;
483 }
484
485 writew(div, host->base + JZ_REG_MMC_CLKRT);
486 return real_rate;
487 }
488
489
490 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, struct mmc_command *cmd)
491 {
492 int i;
493 uint16_t tmp;
494 if (cmd->flags & MMC_RSP_136) {
495 tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
496 for (i = 0; i < 4; ++i) {
497 cmd->resp[i] = tmp << 24;
498 cmd->resp[i] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
499 tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
500 cmd->resp[i] |= tmp >> 8;
501 }
502 } else {
503 cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24;
504 cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
505 cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff;
506 }
507 }
508
509 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, struct mmc_command *cmd)
510 {
511 uint32_t cmdat = host->cmdat;
512
513 host->cmdat &= ~JZ_MMC_CMDAT_INIT;
514 jz4740_mmc_clock_disable(host);
515
516 host->cmd = cmd;
517
518 if (cmd->flags & MMC_RSP_BUSY)
519 cmdat |= JZ_MMC_CMDAT_BUSY;
520
521 switch (mmc_resp_type(cmd)) {
522 case MMC_RSP_R1B:
523 case MMC_RSP_R1:
524 cmdat |= JZ_MMC_CMDAT_RSP_R1;
525 break;
526 case MMC_RSP_R2:
527 cmdat |= JZ_MMC_CMDAT_RSP_R2;
528 break;
529 case MMC_RSP_R3:
530 cmdat |= JZ_MMC_CMDAT_RSP_R3;
531 break;
532 default:
533 break;
534 }
535
536 if (cmd->data) {
537 cmdat |= JZ_MMC_CMDAT_DATA_EN;
538 if (cmd->data->flags & MMC_DATA_WRITE)
539 cmdat |= JZ_MMC_CMDAT_WRITE;
540 if (cmd->data->flags & MMC_DATA_STREAM)
541 cmdat |= JZ_MMC_CMDAT_STREAM;
542
543 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
544 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
545 }
546
547 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
548 writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
549 writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
550
551 host->waiting = 1;
552 jz4740_mmc_clock_enable(host, 1);
553 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
554 }
555
556 static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host)
557 {
558 uint32_t status;
559 struct mmc_command *cmd = host->req->cmd;
560 struct mmc_request *req = host->req;
561 unsigned int timeout = JZ4740_MMC_MAX_TIMEOUT;
562
563 if (cmd->flags & MMC_RSP_PRESENT)
564 jz4740_mmc_read_response(host, cmd);
565
566 if (cmd->data) {
567 if (cmd->data->flags & MMC_DATA_READ)
568 jz4740_mmc_read_data(host, cmd->data);
569 else
570 jz4740_mmc_write_data(host, cmd->data);
571 }
572
573 if (req->stop) {
574 jz4740_mmc_send_command(host, req->stop);
575 do {
576 status = readw(host->base + JZ_REG_MMC_IREG);
577 } while ((status & JZ_MMC_IRQ_PRG_DONE) == 0 && --timeout);
578 writew(JZ_MMC_IRQ_PRG_DONE, host->base + JZ_REG_MMC_IREG);
579 }
580
581 if (unlikely(timeout == 0))
582 req->stop->error = -ETIMEDOUT;
583
584 jz4740_mmc_request_done(host);
585 }
586
587 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
588 {
589 struct jz4740_mmc_host *host = mmc_priv(mmc);
590
591 host->req = req;
592
593 writew(0xffff, host->base + JZ_REG_MMC_IREG);
594
595 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
596 jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
597 jz4740_mmc_send_command(host, req->cmd);
598 }
599
600
601 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
602 {
603 struct jz4740_mmc_host *host = mmc_priv(mmc);
604 if (ios->clock)
605 jz4740_mmc_set_clock_rate(host, ios->clock);
606
607 switch(ios->power_mode) {
608 case MMC_POWER_UP:
609 jz4740_mmc_reset(host);
610 if (gpio_is_valid(host->pdata->gpio_power))
611 gpio_set_value(host->pdata->gpio_power,
612 !host->pdata->power_active_low);
613 host->cmdat |= JZ_MMC_CMDAT_INIT;
614 clk_enable(host->clk);
615 break;
616 case MMC_POWER_ON:
617 break;
618 default:
619 if (gpio_is_valid(host->pdata->gpio_power))
620 gpio_set_value(host->pdata->gpio_power,
621 host->pdata->power_active_low);
622 clk_disable(host->clk);
623 break;
624 }
625
626 switch(ios->bus_width) {
627 case MMC_BUS_WIDTH_1:
628 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
629 break;
630 case MMC_BUS_WIDTH_4:
631 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
632 break;
633 default:
634 dev_err(&host->pdev->dev, "Invalid bus width: %d\n", ios->bus_width);
635 }
636 }
637
638 static int jz4740_mmc_get_ro(struct mmc_host *mmc)
639 {
640 struct jz4740_mmc_host *host = mmc_priv(mmc);
641 if (!gpio_is_valid(host->pdata->gpio_read_only))
642 return -ENOSYS;
643
644 return gpio_get_value(host->pdata->gpio_read_only) ^
645 host->pdata->read_only_active_low;
646 }
647
648 static int jz4740_mmc_get_cd(struct mmc_host *mmc)
649 {
650 struct jz4740_mmc_host *host = mmc_priv(mmc);
651 if (!gpio_is_valid(host->pdata->gpio_card_detect))
652 return -ENOSYS;
653
654 return gpio_get_value(host->pdata->gpio_card_detect) ^
655 host->pdata->card_detect_active_low;
656 }
657
658 static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
659 {
660 struct jz4740_mmc_host *host = devid;
661
662 mmc_detect_change(host->mmc, HZ / 3);
663
664 return IRQ_HANDLED;
665 }
666
667 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
668 {
669 struct jz4740_mmc_host *host = mmc_priv(mmc);
670 if (enable)
671 jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_SDIO);
672 else
673 jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_SDIO);
674 }
675
676 static const struct mmc_host_ops jz4740_mmc_ops = {
677 .request = jz4740_mmc_request,
678 .set_ios = jz4740_mmc_set_ios,
679 .get_ro = jz4740_mmc_get_ro,
680 .get_cd = jz4740_mmc_get_cd,
681 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
682 };
683
684 static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
685 JZ_GPIO_BULK_PIN(MSC_CMD),
686 JZ_GPIO_BULK_PIN(MSC_CLK),
687 JZ_GPIO_BULK_PIN(MSC_DATA0),
688 JZ_GPIO_BULK_PIN(MSC_DATA1),
689 JZ_GPIO_BULK_PIN(MSC_DATA2),
690 JZ_GPIO_BULK_PIN(MSC_DATA3),
691 };
692
693 static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
694 {
695 int ret;
696 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
697
698 if (!pdata)
699 return 0;
700
701 if (gpio_is_valid(pdata->gpio_card_detect)) {
702 ret = gpio_request(pdata->gpio_card_detect, "MMC detect change");
703 if (ret) {
704 dev_err(&pdev->dev, "Failed to request detect change gpio\n");
705 goto err;
706 }
707 gpio_direction_input(pdata->gpio_card_detect);
708 }
709
710 if (gpio_is_valid(pdata->gpio_read_only)) {
711 ret = gpio_request(pdata->gpio_read_only, "MMC read only");
712 if (ret) {
713 dev_err(&pdev->dev, "Failed to request read only gpio: %d\n", ret);
714 goto err_free_gpio_card_detect;
715 }
716 gpio_direction_input(pdata->gpio_read_only);
717 }
718
719 if (gpio_is_valid(pdata->gpio_power)) {
720 ret = gpio_request(pdata->gpio_power, "MMC power");
721 if (ret) {
722 dev_err(&pdev->dev, "Failed to request power gpio: %d\n", ret);
723 goto err_free_gpio_read_only;
724 }
725 gpio_direction_output(pdata->gpio_power, pdata->power_active_low);
726 }
727
728 return 0;
729
730 err_free_gpio_read_only:
731 if (gpio_is_valid(pdata->gpio_read_only))
732 gpio_free(pdata->gpio_read_only);
733 err_free_gpio_card_detect:
734 if (gpio_is_valid(pdata->gpio_card_detect))
735 gpio_free(pdata->gpio_card_detect);
736 err:
737 return ret;
738 }
739
740 static void jz4740_mmc_free_gpios(struct platform_device *pdev)
741 {
742 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
743
744 if (!pdata)
745 return;
746
747 if (gpio_is_valid(pdata->gpio_power))
748 gpio_free(pdata->gpio_power);
749 if (gpio_is_valid(pdata->gpio_read_only))
750 gpio_free(pdata->gpio_read_only);
751 if (gpio_is_valid(pdata->gpio_card_detect))
752 gpio_free(pdata->gpio_card_detect);
753 }
754
755 static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
756 {
757 int ret;
758 struct mmc_host *mmc;
759 struct jz4740_mmc_host *host;
760 struct jz4740_mmc_platform_data *pdata;
761
762 pdata = pdev->dev.platform_data;
763
764 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
765
766 if (!mmc) {
767 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
768 return -ENOMEM;
769 }
770
771 host = mmc_priv(mmc);
772
773 host->irq = platform_get_irq(pdev, 0);
774
775 if (host->irq < 0) {
776 ret = host->irq;
777 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
778 goto err_free_host;
779 }
780
781 host->clk = clk_get(&pdev->dev, "mmc");
782 if (!host->clk) {
783 ret = -ENOENT;
784 dev_err(&pdev->dev, "Failed to get mmc clock\n");
785 goto err_free_host;
786 }
787
788 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
789
790 if (!host->mem) {
791 ret = -ENOENT;
792 dev_err(&pdev->dev, "Failed to get base platform memory\n");
793 goto err_clk_put;
794 }
795
796 host->mem = request_mem_region(host->mem->start, resource_size(host->mem),
797 pdev->name);
798
799 if (!host->mem) {
800 ret = -EBUSY;
801 dev_err(&pdev->dev, "Failed to request base memory region\n");
802 goto err_clk_put;
803 }
804
805 host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
806
807 if (!host->base) {
808 ret = -EBUSY;
809 dev_err(&pdev->dev, "Failed to ioremap base memory\n");
810 goto err_release_mem_region;
811 }
812
813 if (pdata && pdata->data_1bit)
814 ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
815 else
816 ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
817
818 if (ret) {
819 dev_err(&pdev->dev, "Failed to request function pins: %d\n", ret);
820 goto err_iounmap;
821 }
822
823 ret = jz4740_mmc_request_gpios(pdev);
824 if (ret)
825 goto err_gpio_bulk_free;
826
827 mmc->ops = &jz4740_mmc_ops;
828 mmc->f_min = JZ_MMC_CLK_RATE / 128;
829 mmc->f_max = JZ_MMC_CLK_RATE;
830 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
831 mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
832 mmc->caps |= MMC_CAP_SDIO_IRQ;
833 mmc->max_seg_size = 4096;
834 mmc->max_phys_segs = 128;
835
836 mmc->max_blk_size = (1 << 10) - 1;
837 mmc->max_blk_count = (1 << 15) - 1;
838 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
839
840 host->mmc = mmc;
841 host->pdev = pdev;
842 host->pdata = pdata;
843 host->max_clock = JZ_MMC_CLK_RATE;
844 spin_lock_init(&host->lock);
845 host->irq_mask = 0xffff;
846
847 host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
848
849 if (host->card_detect_irq < 0) {
850 dev_warn(&pdev->dev, "Failed to get irq for card detect gpio\n");
851 } else {
852 ret = request_irq(host->card_detect_irq,
853 jz4740_mmc_card_detect_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC/SD detect changed", host);
854
855 if (ret) {
856 dev_err(&pdev->dev, "Failed to request card detect irq");
857 goto err_free_gpios;
858 }
859 }
860
861 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, IRQF_DISABLED, "MMC/SD", host);
862 if (ret) {
863 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
864 goto err_free_card_detect_irq;
865 }
866
867 jz4740_mmc_reset(host);
868 jz4740_mmc_clock_disable(host);
869 setup_timer(&host->timeout_timer, jz4740_mmc_timeout, (unsigned long)host);
870
871 platform_set_drvdata(pdev, host);
872 ret = mmc_add_host(mmc);
873
874 if (ret) {
875 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
876 goto err_free_irq;
877 }
878 printk("JZ SD/MMC card driver registered\n");
879
880 return 0;
881
882 err_free_irq:
883 free_irq(host->irq, host);
884 err_free_card_detect_irq:
885 if (host->card_detect_irq >= 0)
886 free_irq(host->card_detect_irq, host);
887 err_free_gpios:
888 jz4740_mmc_free_gpios(pdev);
889 err_gpio_bulk_free:
890 if (pdata && pdata->data_1bit)
891 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
892 else
893 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
894 err_iounmap:
895 iounmap(host->base);
896 err_release_mem_region:
897 release_mem_region(host->mem->start, resource_size(host->mem));
898 err_clk_put:
899 clk_put(host->clk);
900 err_free_host:
901 platform_set_drvdata(pdev, NULL);
902 mmc_free_host(mmc);
903
904 return ret;
905 }
906
907 static int jz4740_mmc_remove(struct platform_device *pdev)
908 {
909 struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
910 struct jz4740_mmc_platform_data *pdata = host->pdata;
911
912 del_timer_sync(&host->timeout_timer);
913 jz4740_mmc_disable_irq(host, 0xff);
914 jz4740_mmc_reset(host);
915
916 mmc_remove_host(host->mmc);
917
918 free_irq(host->irq, host);
919 if (host->card_detect_irq >= 0)
920 free_irq(host->card_detect_irq, host);
921
922 jz4740_mmc_free_gpios(pdev);
923 if (pdata && pdata->data_1bit)
924 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
925 else
926 jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
927
928 iounmap(host->base);
929 release_mem_region(host->mem->start, resource_size(host->mem));
930
931 clk_put(host->clk);
932
933 platform_set_drvdata(pdev, NULL);
934 mmc_free_host(host->mmc);
935
936 return 0;
937 }
938
939 #ifdef CONFIG_PM
940 static int jz4740_mmc_suspend(struct device *dev)
941 {
942 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
943 struct jz4740_mmc_platform_data *pdata = host->pdata;
944
945 mmc_suspend_host(host->mmc, PMSG_SUSPEND);
946
947 if (pdata && pdata->data_1bit)
948 jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
949 else
950 jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
951
952 return 0;
953 }
954
955 static int jz4740_mmc_resume(struct device *dev)
956 {
957 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
958 struct jz4740_mmc_platform_data *pdata = host->pdata;
959
960 if (pdata && pdata->data_1bit)
961 jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
962 else
963 jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
964
965 mmc_resume_host(host->mmc);
966
967 return 0;
968 }
969
970 struct dev_pm_ops jz4740_mmc_pm_ops = {
971 .suspend = jz4740_mmc_suspend,
972 .resume = jz4740_mmc_resume,
973 .poweroff = jz4740_mmc_suspend,
974 .restore = jz4740_mmc_resume,
975 };
976
977 #define jz4740_mmc_PM_OPS (&jz4740_mmc_pm_ops)
978 #else
979 #define jz4740_mmc_PM_OPS NULL
980 #endif
981
982 static struct platform_driver jz4740_mmc_driver = {
983 .probe = jz4740_mmc_probe,
984 .remove = jz4740_mmc_remove,
985 .driver = {
986 .name = "jz4740-mmc",
987 .owner = THIS_MODULE,
988 .pm = jz4740_mmc_PM_OPS,
989 },
990 };
991
992 static int __init jz4740_mmc_init(void) {
993 return platform_driver_register(&jz4740_mmc_driver);
994 }
995 module_init(jz4740_mmc_init);
996
997 static void __exit jz4740_mmc_exit(void) {
998 platform_driver_unregister(&jz4740_mmc_driver);
999 }
1000 module_exit(jz4740_mmc_exit);
1001
1002 MODULE_DESCRIPTION("JZ4720/JZ4740 SD/MMC controller driver");
1003 MODULE_LICENSE("GPL");
1004 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
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