danube to ifxmips transition

[openwrt/svn-archive/archive.git] / target / linux / ifxmips / files / include / asm-mips / danube / danube_irq.h

diff --git a/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h b/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h
index 45796831fe11dccd747e9d4b2c3225c20c9f5622..b96d091823f83e59555dece038003146b4bebd3e 100644 (file)
--- a/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h
+++ b/target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h
@@ -17,8 +17,8 @@
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
  *
  */
-#ifndef _DANUBE_IRQ__
-#define _DANUBE_IRQ__
+#ifndef _IFXMIPS_IRQ__
+#define _IFXMIPS_IRQ__
 
 #define INT_NUM_IRQ0                   8
 #define INT_NUM_IM0_IRL0               (INT_NUM_IRQ0 + 0)
@@ -28,39 +28,39 @@
 #define INT_NUM_IM4_IRL0               (INT_NUM_IRQ0 + 128)
 #define INT_NUM_IM_OFFSET              (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
 
-#define DANUBEASC1_TIR                 (INT_NUM_IM3_IRL0 + 7)
-#define DANUBEASC1_RIR                 (INT_NUM_IM3_IRL0 + 9)
-#define DANUBEASC1_EIR                 (INT_NUM_IM3_IRL0 + 10)
+#define IFXMIPSASC1_TIR                        (INT_NUM_IM3_IRL0 + 7)
+#define IFXMIPSASC1_RIR                        (INT_NUM_IM3_IRL0 + 9)
+#define IFXMIPSASC1_EIR                        (INT_NUM_IM3_IRL0 + 10)
 
-#define DANUBE_SSC_TIR                 (INT_NUM_IM0_IRL0 + 15)
-#define DANUBE_SSC_RIR                 (INT_NUM_IM0_IRL0 + 14)
-#define DANUBE_SSC_EIR                 (INT_NUM_IM0_IRL0 + 16)
+#define IFXMIPS_SSC_TIR                        (INT_NUM_IM0_IRL0 + 15)
+#define IFXMIPS_SSC_RIR                        (INT_NUM_IM0_IRL0 + 14)
+#define IFXMIPS_SSC_EIR                        (INT_NUM_IM0_IRL0 + 16)
 
-#define DANUBE_TIMER6_INT              (INT_NUM_IM1_IRL0 + 23)
+#define IFXMIPS_TIMER6_INT             (INT_NUM_IM1_IRL0 + 23)
 
 #define MIPS_CPU_TIMER_IRQ             7
 
-#define DANUBE_DMA_CH0_INT             (INT_NUM_IM2_IRL0)
-#define DANUBE_DMA_CH1_INT             (INT_NUM_IM2_IRL0 + 1)
-#define DANUBE_DMA_CH2_INT             (INT_NUM_IM2_IRL0 + 2)
-#define DANUBE_DMA_CH3_INT             (INT_NUM_IM2_IRL0 + 3)
-#define DANUBE_DMA_CH4_INT             (INT_NUM_IM2_IRL0 + 4)
-#define DANUBE_DMA_CH5_INT             (INT_NUM_IM2_IRL0 + 5)
-#define DANUBE_DMA_CH6_INT             (INT_NUM_IM2_IRL0 + 6)
-#define DANUBE_DMA_CH7_INT             (INT_NUM_IM2_IRL0 + 7)
-#define DANUBE_DMA_CH8_INT             (INT_NUM_IM2_IRL0 + 8)
-#define DANUBE_DMA_CH9_INT             (INT_NUM_IM2_IRL0 + 9)
-#define DANUBE_DMA_CH10_INT            (INT_NUM_IM2_IRL0 + 10)
-#define DANUBE_DMA_CH11_INT            (INT_NUM_IM2_IRL0 + 11)
-#define DANUBE_DMA_CH12_INT            (INT_NUM_IM2_IRL0 + 25)
-#define DANUBE_DMA_CH13_INT            (INT_NUM_IM2_IRL0 + 26)
-#define DANUBE_DMA_CH14_INT            (INT_NUM_IM2_IRL0 + 27)
-#define DANUBE_DMA_CH15_INT            (INT_NUM_IM2_IRL0 + 28)
-#define DANUBE_DMA_CH16_INT            (INT_NUM_IM2_IRL0 + 29)
-#define DANUBE_DMA_CH17_INT            (INT_NUM_IM2_IRL0 + 30)
-#define DANUBE_DMA_CH18_INT            (INT_NUM_IM2_IRL0 + 16)
-#define DANUBE_DMA_CH19_INT            (INT_NUM_IM2_IRL0 + 21)
+#define IFXMIPS_DMA_CH0_INT            (INT_NUM_IM2_IRL0)
+#define IFXMIPS_DMA_CH1_INT            (INT_NUM_IM2_IRL0 + 1)
+#define IFXMIPS_DMA_CH2_INT            (INT_NUM_IM2_IRL0 + 2)
+#define IFXMIPS_DMA_CH3_INT            (INT_NUM_IM2_IRL0 + 3)
+#define IFXMIPS_DMA_CH4_INT            (INT_NUM_IM2_IRL0 + 4)
+#define IFXMIPS_DMA_CH5_INT            (INT_NUM_IM2_IRL0 + 5)
+#define IFXMIPS_DMA_CH6_INT            (INT_NUM_IM2_IRL0 + 6)
+#define IFXMIPS_DMA_CH7_INT            (INT_NUM_IM2_IRL0 + 7)
+#define IFXMIPS_DMA_CH8_INT            (INT_NUM_IM2_IRL0 + 8)
+#define IFXMIPS_DMA_CH9_INT            (INT_NUM_IM2_IRL0 + 9)
+#define IFXMIPS_DMA_CH10_INT           (INT_NUM_IM2_IRL0 + 10)
+#define IFXMIPS_DMA_CH11_INT           (INT_NUM_IM2_IRL0 + 11)
+#define IFXMIPS_DMA_CH12_INT           (INT_NUM_IM2_IRL0 + 25)
+#define IFXMIPS_DMA_CH13_INT           (INT_NUM_IM2_IRL0 + 26)
+#define IFXMIPS_DMA_CH14_INT           (INT_NUM_IM2_IRL0 + 27)
+#define IFXMIPS_DMA_CH15_INT           (INT_NUM_IM2_IRL0 + 28)
+#define IFXMIPS_DMA_CH16_INT           (INT_NUM_IM2_IRL0 + 29)
+#define IFXMIPS_DMA_CH17_INT           (INT_NUM_IM2_IRL0 + 30)
+#define IFXMIPS_DMA_CH18_INT           (INT_NUM_IM2_IRL0 + 16)
+#define IFXMIPS_DMA_CH19_INT           (INT_NUM_IM2_IRL0 + 21)
 
-extern void mask_and_ack_danube_irq (unsigned int irq_nr);
+extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
 
 #endif