ramips/rt305x: add initial support for Rt5350 SoC

[openwrt/svn-archive/archive.git] / target / linux / ramips / files / arch / mips / ralink / rt305x / clock.c

diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
index 958547611b24f3f41d90128398781b6379b2bae8..c46a1747b5cd20e49a7fbd61eed458874aae0b16 100644 (file)
--- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
@@ -62,6 +62,27 @@ void __init rt305x_clocks_init(void)
                rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
                rt305x_uart_clk.rate = 40000000;
                rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
+       } else if (soc_is_rt5350()) {
+               t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
+                    RT5350_SYSCFG0_CPUCLK_MASK;
+               switch (t) {
+               case RT5350_SYSCFG0_CPUCLK_360:
+                       rt305x_cpu_clk.rate = 360000000;
+                       rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
+                       break;
+               case RT5350_SYSCFG0_CPUCLK_320:
+                       rt305x_cpu_clk.rate = 320000000;
+                       rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 4;
+                       break;
+               case RT5350_SYSCFG0_CPUCLK_300:
+                       rt305x_cpu_clk.rate = 300000000;
+                       rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
+                       break;
+               default:
+                       BUG();
+               }
+               rt305x_uart_clk.rate = 40000000;
+               rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
        } else {
                BUG();
        }