fixes ifxmips pci support and adds GENERIC_GPIO
authorJohn Crispin <john@openwrt.org>
Sat, 7 Jun 2008 16:04:31 +0000 (16:04 +0000)
committerJohn Crispin <john@openwrt.org>
Sat, 7 Jun 2008 16:04:31 +0000 (16:04 +0000)
SVN-Revision: 11396

21 files changed:
target/linux/ifxmips/config-2.6.25
target/linux/ifxmips/files/arch/mips/ifxmips/board.c
target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c
target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c
target/linux/ifxmips/files/arch/mips/ifxmips/pci.c
target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c
target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
target/linux/ifxmips/files/arch/mips/ifxmips/reset.c
target/linux/ifxmips/files/arch/mips/ifxmips/setup.c
target/linux/ifxmips/files/drivers/char/ifxmips_gpio.c
target/linux/ifxmips/files/drivers/char/ifxmips_led.c
target/linux/ifxmips/files/drivers/char/ifxmips_mei_core.c
target/linux/ifxmips/files/drivers/char/ifxmips_ssc.c
target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c
target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c
target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c
target/linux/ifxmips/files/drivers/watchdog/ifxmips_wdt.c
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h [new file with mode: 0644]
target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/irq.h
target/linux/ifxmips/patches/100-board.patch

index 6b36b1e..4299aef 100644 (file)
@@ -168,8 +168,8 @@ CONFIG_MTD_PHYSMAP_START=0x0
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_64KB is not set
 # CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PCIPCWATCHDOG is not set
 CONFIG_PCI=y
+# CONFIG_PCIPCWATCHDOG is not set
 CONFIG_PCI_DOMAINS=y
 # CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
@@ -213,8 +213,8 @@ CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
 # CONFIG_TOSHIBA_RBTX4927 is not set
 # CONFIG_TOSHIBA_RBTX4938 is not set
 CONFIG_TRAD_SIGNALS=y
-# CONFIG_USBPCWATCHDOG is not set
 CONFIG_USB=m
+# CONFIG_USBPCWATCHDOG is not set
 # CONFIG_USB_EHCI_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
 # CONFIG_USB_UHCI_HCD is not set
index 580dc6a..bcbf117 100644 (file)
@@ -99,7 +99,7 @@ static struct platform_device ifxmips_mtd[] =
 const char*
 get_system_type (void)
 {
-       chiprev = readl(IFXMIPS_MPS_CHIPID);
+       chiprev = ifxmips_r32(IFXMIPS_MPS_CHIPID);
        switch(chiprev)
        {
        case BOARD_DANUBE_CHIPID:
index 1c97b16..e47082d 100644 (file)
@@ -97,9 +97,9 @@ enable_ch_irq (_dma_channel_info *pCh)
        int flag;
 
        local_irq_save(flag);
-       writel(chan_no, IFXMIPS_DMA_CS);
-       writel(0x4a, IFXMIPS_DMA_CIE);
-       writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+       ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+       ifxmips_w32(0x4a, IFXMIPS_DMA_CIE);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
        local_irq_restore(flag);
        enable_ifxmips_irq(pCh->irq);
 }
@@ -112,9 +112,9 @@ disable_ch_irq (_dma_channel_info *pCh)
 
        local_irq_save(flag);
        g_ifxmips_dma_int_status &= ~(1 << chan_no);
-       writel(chan_no, IFXMIPS_DMA_CS);
-       writel(0, IFXMIPS_DMA_CIE);
-       writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
+       ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+       ifxmips_w32(0, IFXMIPS_DMA_CIE);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);
        local_irq_restore(flag);
        mask_and_ack_ifxmips_irq(pCh->irq);
 }
@@ -126,8 +126,8 @@ open_chan (_dma_channel_info *pCh)
        int chan_no = (int)(pCh - dma_chan);
 
        local_irq_save(flag);
-       writel(chan_no, IFXMIPS_DMA_CS);
-       writel(readl(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
+       ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL);
        if(pCh->dir == IFXMIPS_DMA_RX)
                enable_ch_irq(pCh);
        local_irq_restore(flag);
@@ -140,8 +140,8 @@ close_chan(_dma_channel_info *pCh)
        int chan_no = (int) (pCh - dma_chan);
 
        local_irq_save(flag);
-       writel(chan_no, IFXMIPS_DMA_CS);
-       writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+       ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
        disable_ch_irq(pCh);
        local_irq_restore(flag);
 }
@@ -151,8 +151,8 @@ reset_chan (_dma_channel_info *pCh)
 {
        int chan_no = (int) (pCh - dma_chan);
 
-       writel(chan_no, IFXMIPS_DMA_CS);
-       writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+       ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
 }
 
 void
@@ -176,10 +176,10 @@ rx_chan_intr_handler (int chan_no)
                pCh->weight--;
        } else {
                local_irq_save(flag);
-               tmp = readl(IFXMIPS_DMA_CS);
-               writel(chan_no, IFXMIPS_DMA_CS);
-               writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
-               writel(tmp, IFXMIPS_DMA_CS);
+               tmp = ifxmips_r32(IFXMIPS_DMA_CS);
+               ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+               ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
+               ifxmips_w32(tmp, IFXMIPS_DMA_CS);
                g_ifxmips_dma_int_status &= ~(1 << chan_no);
                local_irq_restore(flag);
                enable_ifxmips_irq(dma_chan[chan_no].irq);
@@ -195,10 +195,10 @@ tx_chan_intr_handler (int chan_no)
     int flag;
 
     local_irq_save(flag);
-    tmp = readl(IFXMIPS_DMA_CS);
-    writel(chan_no, IFXMIPS_DMA_CS);
-    writel(readl(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
-    writel(tmp, IFXMIPS_DMA_CS);
+    tmp = ifxmips_r32(IFXMIPS_DMA_CS);
+    ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+    ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS);
+    ifxmips_w32(tmp, IFXMIPS_DMA_CS);
     g_ifxmips_dma_int_status &= ~(1 << chan_no);
     local_irq_restore(flag);
        pDev->current_tx_chan = pCh->rel_chan_no;
@@ -272,10 +272,10 @@ dma_interrupt (int irq, void *dev_id)
        if (chan_no < 0 || chan_no > 19)
                BUG();
 
-       tmp = readl(IFXMIPS_DMA_IRNEN);
-       writel(0, IFXMIPS_DMA_IRNEN);
+       tmp = ifxmips_r32(IFXMIPS_DMA_IRNEN);
+       ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
        g_ifxmips_dma_int_status |= 1 << chan_no;
-       writel(tmp, IFXMIPS_DMA_IRNEN);
+       ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN);
        mask_and_ack_ifxmips_irq(irq);
 
     if (!g_ifxmips_dma_in_process)
@@ -337,16 +337,16 @@ dma_device_register(_dma_device_info *dev)
                                memset(tx_desc_p, 0, sizeof(struct tx_desc));
                        }
                        local_irq_save(flag);
-                       writel(chan_no, IFXMIPS_DMA_CS);
+                       ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
                        /*check if the descriptor length is changed */
-                       if (readl(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
-                               writel(pCh->desc_len, IFXMIPS_DMA_CDLEN);
-
-                       writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
-                       writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
-                       while (readl(IFXMIPS_DMA_CCTRL) & 2){};
-                       writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
-                       writel(0x30100, IFXMIPS_DMA_CCTRL);     /*reset and enable channel,enable channel later */
+                       if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
+                               ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
+
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+                       while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2){};
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+                       ifxmips_w32(0x30100, IFXMIPS_DMA_CCTRL);        /*reset and enable channel,enable channel later */
                        local_irq_restore(flag);
                }
        }
@@ -376,16 +376,16 @@ dma_device_register(_dma_device_info *dev)
                        }
 
                        local_irq_save(flag);
-                       writel(chan_no, IFXMIPS_DMA_CS);
+                       ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
                        /*check if the descriptor length is changed */
-                       if (readl(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
-                               writel(pCh->desc_len, IFXMIPS_DMA_CDLEN);
-                       writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
-                       writel(readl(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
-                       while (readl(IFXMIPS_DMA_CCTRL) & 2){};
-                       writel(0x0a, IFXMIPS_DMA_CIE);  /*fix me, should enable all the interrupts here? */
-                       writel(readl(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
-                       writel(0x30000, IFXMIPS_DMA_CCTRL);
+                       if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len)
+                               ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN);
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL);
+                       while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2){};
+                       ifxmips_w32(0x0a, IFXMIPS_DMA_CIE);     /*fix me, should enable all the interrupts here? */
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN);
+                       ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL);
                        local_irq_restore(flag);
                        enable_ifxmips_irq(dma_chan[chan_no].irq);
                }
@@ -409,14 +409,14 @@ dma_device_unregister (_dma_device_info *dev)
                {
                        chan_no = (int)(dev->tx_chan[i] - dma_chan);
                        local_irq_save (flag);
-                       writel(chan_no, IFXMIPS_DMA_CS);
+                       ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
                        pCh->curr_desc = 0;
                        pCh->prev_desc = 0;
                        pCh->control = IFXMIPS_DMA_CH_OFF;
-                       writel(0, IFXMIPS_DMA_CIE);     /*fix me, should disable all the interrupts here? */
-                       writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);  /*disable interrupts */
-                       writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
-                       while (readl(IFXMIPS_DMA_CCTRL) & 1) {};
+                       ifxmips_w32(0, IFXMIPS_DMA_CIE);        /*fix me, should disable all the interrupts here? */
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);       /*disable interrupts */
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+                       while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) {};
                        local_irq_restore (flag);
 
                        for (j = 0; j < pCh->desc_len; j++)
@@ -446,11 +446,11 @@ dma_device_unregister (_dma_device_info *dev)
                pCh->prev_desc = 0;
                pCh->control = IFXMIPS_DMA_CH_OFF;
 
-               writel(chan_no, IFXMIPS_DMA_CS);
-               writel(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
-               writel(readl(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);  /*disable interrupts */
-               writel(readl(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
-               while (readl(IFXMIPS_DMA_CCTRL) & 1) {};
+               ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+               ifxmips_w32(0, IFXMIPS_DMA_CIE); /*fix me, should disable all the interrupts here? */
+               ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN);       /*disable interrupts */
+               ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL);
+               while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) {};
 
                local_irq_restore (flag);
                for (j = 0; j < pCh->desc_len; j++)
@@ -577,8 +577,8 @@ dma_device_write (struct dma_device_info *dma_dev, u8 * dataptr, int len, void *
                dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
        }
 
-       writel(chan_no, IFXMIPS_DMA_CS);
-       tmp = readl(IFXMIPS_DMA_CCTRL);
+       ifxmips_w32(chan_no, IFXMIPS_DMA_CS);
+       tmp = ifxmips_r32(IFXMIPS_DMA_CCTRL);
 
        if (!(tmp & 1))
                pCh->open (pCh);
@@ -625,14 +625,14 @@ map_dma_chan(_dma_chan_map *map)
                dma_devs[i].rx_burst_len = 4;
                if (i == 0)
                {
-                       writel(0, IFXMIPS_DMA_PS);
-                       writel(readl(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL);  /*enable dma drop */
+                       ifxmips_w32(0, IFXMIPS_DMA_PS);
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL);       /*enable dma drop */
                }
 
                if (i == 1)
                {
-                       writel(1, IFXMIPS_DMA_PS);
-                       writel(0x14, IFXMIPS_DMA_PCTRL);        /*deu port setting */
+                       ifxmips_w32(1, IFXMIPS_DMA_PS);
+                       ifxmips_w32(0x14, IFXMIPS_DMA_PCTRL);   /*deu port setting */
                }
 
                for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++)
@@ -688,17 +688,17 @@ dma_chip_init(void)
        ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
 
        // reset DMA
-       writel(readl(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL);
 
        // diable all interrupts
-       writel(0, IFXMIPS_DMA_IRNEN);
+       ifxmips_w32(0, IFXMIPS_DMA_IRNEN);
 
        for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
        {
-               writel(i, IFXMIPS_DMA_CS);
-               writel(0x2, IFXMIPS_DMA_CCTRL);
-               writel(0x80000040, IFXMIPS_DMA_CPOLL);
-               writel(readl(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
+               ifxmips_w32(i, IFXMIPS_DMA_CS);
+               ifxmips_w32(0x2, IFXMIPS_DMA_CCTRL);
+               ifxmips_w32(0x80000040, IFXMIPS_DMA_CPOLL);
+               ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL);
 
        }
 }
@@ -728,9 +728,9 @@ ifxmips_dma_init (void)
                dma_chan[i].curr_desc = 0;
                dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET;
 
-               writel(i, IFXMIPS_DMA_CS);
-               writel((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
-               writel(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
+               ifxmips_w32(i, IFXMIPS_DMA_CS);
+               ifxmips_w32((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA);
+               ifxmips_w32(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN);
        }
 
        return 0;
index 32ecaa0..c30a783 100644 (file)
@@ -48,7 +48,7 @@ disable_ifxmips_irq (unsigned int irq_nr)
        for (i = 0; i <= 4; i++)
        {
                if (irq_nr < INT_NUM_IM_OFFSET){
-                       writel(readl(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
+                       ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
                        return;
                }
                ifxmips_ier += IFXMIPS_ICU_OFFSET;
@@ -69,8 +69,8 @@ mask_and_ack_ifxmips_irq (unsigned int irq_nr)
        {
                if (irq_nr < INT_NUM_IM_OFFSET)
                {
-                       writel(readl(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
-                       writel((1 << irq_nr ), ifxmips_isr);
+                       ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr ), ifxmips_ier);
+                       ifxmips_w32((1 << irq_nr ), ifxmips_isr);
                        return;
                }
                ifxmips_ier += IFXMIPS_ICU_OFFSET;
@@ -91,7 +91,7 @@ enable_ifxmips_irq (unsigned int irq_nr)
        {
                if (irq_nr < INT_NUM_IM_OFFSET)
                {
-                       writel(readl(ifxmips_ier) | (1 << irq_nr ), ifxmips_ier);
+                       ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr ), ifxmips_ier);
                        return;
                }
                ifxmips_ier += IFXMIPS_ICU_OFFSET;
@@ -145,7 +145,7 @@ ifxmips_hw_irqdispatch (int module)
 {
        u32 irq;
 
-       irq = readl(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
+       irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
        if (irq == 0)
                return;
 
@@ -153,7 +153,7 @@ ifxmips_hw_irqdispatch (int module)
        do_IRQ ((int) irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
 
        if ((irq == 22) && (module == 0)){
-               writel(readl(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT);
+               ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10, IFXMIPS_EBU_PCC_ISTAT);
        }
 }
 
@@ -195,7 +195,7 @@ arch_init_irq(void)
 
        for (i = 0; i < 5; i++)
        {
-               writel(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
+               ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
        }
 
        mips_cpu_irq_init();
index d8dac46..ae58076 100644 (file)
@@ -21,7 +21,7 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
-//#define CONFIG_IFXMIPS_PCI_HW_SWAP 1
+#define CONFIG_IFXMIPS_PCI_HW_SWAP 1
 
 static int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
 static int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
@@ -80,12 +80,12 @@ ifxmips_pci_config_access(unsigned char access_type,
        if (access_type == PCI_ACCESS_WRITE)
        {
 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
-               writel(swab32(*data), ((u32*)cfg_base));
+               ifxmips_w32(swab32(*data), ((u32*)cfg_base));
 #else
-               writel(*data, ((u32*)cfg_base));
+               ifxmips_w32(*data, ((u32*)cfg_base));
 #endif
        } else {
-               *data = readl(((u32*)(cfg_base)));
+               *data = ifxmips_r32(((u32*)(cfg_base)));
 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
                *data = swab32(*data);
 #endif
@@ -94,12 +94,12 @@ ifxmips_pci_config_access(unsigned char access_type,
 
        /* clean possible Master abort */
        cfg_base = (ifxmips_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
-       temp = readl(((u32*)(cfg_base)));
+       temp = ifxmips_r32(((u32*)(cfg_base)));
 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
        temp = swab32 (temp);
 #endif
        cfg_base = (ifxmips_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
-       writel(temp, ((u32*)cfg_base));
+       ifxmips_w32(temp, ((u32*)cfg_base));
 
        local_irq_restore(flags);
 
@@ -164,8 +164,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev){
                        break;
                case 1:
                        //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
-                       writel(readl(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
-                       writel(readl(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
+                       ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
                        break;
                case 2:
                case 3:
@@ -183,44 +183,44 @@ static void __init ifxmips_pci_startup (void){
        /*initialize the first PCI device--ifxmips itself */
        u32 temp_buffer;
        /*TODO: trigger reset */
-       writel(readl(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
-       writel(readl(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
        /* PCIS of IF_CLK of CGU   : 1 =>PCI Clock output
           0 =>clock input
           PADsel of PCI_CR of CGU : 1 =>From CGU
           : 0 =>From pad
         */
-       writel(readl(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
-       writel((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
+       ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
 
        /* prepare GPIO */
        /* PCI_RST: P1.5 ALT 01 */
        //pliu20060613: start
-       writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
-       writel(readl(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
-       writel(readl(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
-       writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
-       writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
        //pliu20060613: end
        /* PCI_REQ1: P1.13 ALT 01 */
        /* PCI_GNT1: P1.14 ALT 01 */
-       writel(readl(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
-       writel(readl(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
-       writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
-       writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
        /* PCI_REQ2: P1.15 ALT 10 */
        /* PCI_GNT2: P1.7 ALT 10 */
 
 
        /* enable auto-switching between PCI and EBU */
-       writel(0xa, PCI_CR_CLK_CTRL);
+       ifxmips_w32(0xa, PCI_CR_CLK_CTRL);
        /* busy, i.e. configuration is not done, PCI access has to be retried */
-       writel(readl(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
+       ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
        wmb ();
        /* BUS Master/IO/MEM access */
-       writel(readl(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
+       ifxmips_w32(ifxmips_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
 
-       temp_buffer = readl(PCI_CR_PC_ARB);
+       temp_buffer = ifxmips_r32(PCI_CR_PC_ARB);
        /* enable external 2 PCI masters */
        temp_buffer &= (~(0xf << 16));
        /* enable internal arbiter */
@@ -233,51 +233,51 @@ static void __init ifxmips_pci_startup (void){
 
        /* enable all external masters request */
        temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
-       writel(temp_buffer, PCI_CR_PC_ARB);
+       ifxmips_w32(temp_buffer, PCI_CR_PC_ARB);
 
        wmb ();
 
        /* FPI ==> PCI MEM address mapping */
        /* base: 0xb8000000 == > 0x18000000 */
        /* size: 8x4M = 32M */
-       writel(0x18000000, PCI_CR_FCI_ADDR_MAP0);
-       writel(0x18400000, PCI_CR_FCI_ADDR_MAP1);
-       writel(0x18800000, PCI_CR_FCI_ADDR_MAP2);
-       writel(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
-       writel(0x19000000, PCI_CR_FCI_ADDR_MAP4);
-       writel(0x19400000, PCI_CR_FCI_ADDR_MAP5);
-       writel(0x19800000, PCI_CR_FCI_ADDR_MAP6);
-       writel(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
+       ifxmips_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
+       ifxmips_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
+       ifxmips_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
+       ifxmips_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
+       ifxmips_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
+       ifxmips_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
+       ifxmips_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
+       ifxmips_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
 
        /* FPI ==> PCI IO address mapping */
        /* base: 0xbAE00000 == > 0xbAE00000 */
        /* size: 2M */
-       writel(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
+       ifxmips_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
 
        /* PCI ==> FPI address mapping */
        /* base: 0x0 ==> 0x0 */
        /* size: 32M */
        /* BAR1 32M map to SDR address */
-       writel(0x0e000008, PCI_CR_BAR11MASK);
-       writel(0, PCI_CR_PCI_ADDR_MAP11);
-       writel(0, PCI_CS_BASE_ADDR1);
+       ifxmips_w32(0x0e000008, PCI_CR_BAR11MASK);
+       ifxmips_w32(0, PCI_CR_PCI_ADDR_MAP11);
+       ifxmips_w32(0, PCI_CS_BASE_ADDR1);
 #ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
        /* both TX and RX endian swap are enabled */
-       writel(readl(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
+       ifxmips_w32(ifxmips_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
        wmb ();
 #endif
        /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
-       writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
-       writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
+       ifxmips_w32(ifxmips_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
+       ifxmips_w32(ifxmips_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
        /*use 8 dw burse length */
-       writel(0x303, PCI_CR_FCI_BURST_LENGTH);
+       ifxmips_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
 
-       writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
+       ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
        wmb();
-       writel(readl(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
        wmb();
        mdelay (1);
-       writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
 }
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
index 296dd5c..080656f 100644 (file)
@@ -29,8 +29,8 @@ ifxmips_pmu_enable (unsigned int module)
 {
        int err = 1000000;
 
-       writel(readl(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR);
-       while (--err && (readl(IFXMIPS_PMU_PWDSR) & module)) {}
+       ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) & ~module, IFXMIPS_PMU_PWDCR);
+       while (--err && (ifxmips_r32(IFXMIPS_PMU_PWDSR) & module)) {}
 
        if (!err)
                panic("activating PMU module failed!");
@@ -40,6 +40,6 @@ EXPORT_SYMBOL(ifxmips_pmu_enable);
 void
 ifxmips_pmu_disable (unsigned int module)
 {
-       writel(readl(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR);
 }
 EXPORT_SYMBOL(ifxmips_pmu_disable);
index d3009e4..2fb33b7 100644 (file)
@@ -39,11 +39,11 @@ prom_free_prom_memory (void)
 void
 prom_putchar (char c)
 {
-       while ((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
+       while ((ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
 
        if (c == '\n')
-               writel('\r', IFXMIPS_ASC1_TBUF);
-       writel(c, IFXMIPS_ASC1_TBUF);
+               ifxmips_w32('\r', IFXMIPS_ASC1_TBUF);
+       ifxmips_w32(c, IFXMIPS_ASC1_TBUF);
 }
 
 void
index a1f7a46..4953c60 100644 (file)
@@ -37,7 +37,7 @@ ifxmips_machine_restart (char *command)
        printk (KERN_NOTICE "System restart\n");
        local_irq_disable ();
 
-       writel(readl(IFXMIPS_RCU_REQ) | IFXMIPS_RST_ALL, IFXMIPS_RCU_REQ);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_REQ) | IFXMIPS_RST_ALL, IFXMIPS_RCU_REQ);
        for (;;);
 }
 
index 1e62029..19b6c30 100644 (file)
@@ -49,7 +49,7 @@ __init bus_error_init (void)
 unsigned int
 ifxmips_get_ddr_hz (void)
 {
-       switch (readl(IFXMIPS_CGU_SYS) & 0x3)
+       switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3)
        {
        case 0:
                return CLOCK_167M;
@@ -66,7 +66,7 @@ unsigned int
 ifxmips_get_cpu_hz (void)
 {
        unsigned int ddr_clock = ifxmips_get_ddr_hz();
-       switch (readl(IFXMIPS_CGU_SYS) & 0xc)
+       switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
        {
        case 0:
                return CLOCK_333M;
@@ -81,7 +81,7 @@ unsigned int
 ifxmips_get_fpi_hz (void)
 {
        unsigned int ddr_clock = ifxmips_get_ddr_hz();
-       if (readl(IFXMIPS_CGU_SYS) & 0x40)
+       if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
        {
                return ddr_clock >> 1;
        }
@@ -92,7 +92,7 @@ EXPORT_SYMBOL(ifxmips_get_fpi_hz);
 unsigned int
 ifxmips_get_cpu_ver (void)
 {
-       return readl(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
+       return ifxmips_r32(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
 }
 EXPORT_SYMBOL(ifxmips_get_cpu_ver);
 
@@ -130,10 +130,10 @@ plat_time_init (void)
        write_c0_compare(r4k_cur);
        ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
 
-       writel(0x100, IFXMIPS_GPTU_GPT_CLC);
+       ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC);
 
-       writel(0xffff, IFXMIPS_GPTU_GPT_CAPREL);
-       writel(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
+       ifxmips_w32(0xffff, IFXMIPS_GPTU_GPT_CAPREL);
+       ifxmips_w32(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
 }
 
 extern const char* get_system_type (void);
index 8802523..c1eefa5 100644 (file)
@@ -95,7 +95,7 @@ int
 ifxmips_port_set_open_drain (unsigned int port, unsigned int pin)
 {
        IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
 
        return 0;
 }
@@ -105,7 +105,7 @@ int
 ifxmips_port_clear_open_drain (unsigned int port, unsigned int pin)
 {
        IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OD + (port * 0xC));
 
        return 0;
 }
@@ -115,7 +115,7 @@ int
 ifxmips_port_set_pudsel (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
 
        return 0;
 }
@@ -125,7 +125,7 @@ int
 ifxmips_port_clear_pudsel (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC));
 
        return 0;
 }
@@ -135,7 +135,7 @@ int
 ifxmips_port_set_puden (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
 
        return 0;
 }
@@ -145,7 +145,7 @@ int
 ifxmips_port_clear_puden (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_PUDEN + (port * 0xC));
 
        return 0;
 }
@@ -155,7 +155,7 @@ int
 ifxmips_port_set_stoff (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
 
        return 0;
 }
@@ -165,7 +165,7 @@ int
 ifxmips_port_clear_stoff (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_STOFF + (port * 0xC));
 
        return 0;
 }
@@ -175,7 +175,7 @@ int
 ifxmips_port_set_dir_out (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
 
        return 0;
 }
@@ -185,7 +185,7 @@ int
 ifxmips_port_set_dir_in (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_DIR + (port * 0xC));
 
        return 0;
 }
@@ -195,7 +195,7 @@ int
 ifxmips_port_set_output (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
 
        return 0;
 }
@@ -205,7 +205,7 @@ int
 ifxmips_port_clear_output (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_OUT + (port * 0xC));
 
        return 0;
 }
@@ -216,7 +216,7 @@ ifxmips_port_get_input (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
 
-       if (readl(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin))
+       if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin))
                return 0;
        else
                return 1;
@@ -227,7 +227,7 @@ int
 ifxmips_port_set_altsel0 (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
 
        return 0;
 }
@@ -237,7 +237,7 @@ int
 ifxmips_port_clear_altsel0 (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC));
 
        return 0;
 }
@@ -247,7 +247,7 @@ int
 ifxmips_port_set_altsel1 (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
 
        return 0;
 }
@@ -257,7 +257,7 @@ int
 ifxmips_port_clear_altsel1 (unsigned int port, unsigned int pin)
 {
     IFXMIPS_GPIO_SANITY;
-       writel(readl(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
+       ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin), IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC));
 
        return 0;
 }
@@ -347,7 +347,7 @@ long ifxmips_port_read_procmem_helper(char* tag, u32* in_reg, char *buf)
        unsigned int len, t;
 
        len = sprintf(buf, "\n%s: ", tag);
-       reg = readl(in_reg);
+       reg = ifxmips_r32(in_reg);
        bit = 0x80000000;
        for (t = 0; t < 32; t++) {
                if ((reg & bit) > 0)
index 0e87fd2..40d2c96 100644 (file)
@@ -54,7 +54,7 @@ void
 ifxmips_led_set (unsigned int led)
 {
        led &= 0xffffff;
-       writel(readl(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0);
 }
 EXPORT_SYMBOL(ifxmips_led_set);
 
@@ -62,7 +62,7 @@ void
 ifxmips_led_clear (unsigned int led)
 {
        led = ~(led & 0xffffff);
-       writel(readl(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0);
 }
 EXPORT_SYMBOL(ifxmips_led_clear);
 
@@ -70,7 +70,7 @@ void
 ifxmips_led_blink_set (unsigned int led)
 {
        led &= 0xffffff;
-       writel(readl(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0);
 }
 EXPORT_SYMBOL(ifxmips_led_blink_set);
 
@@ -78,7 +78,7 @@ void
 ifxmips_led_blink_clear (unsigned int led)
 {
        led = ~(led & 0xffffff);
-       writel(readl(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0);
 }
 EXPORT_SYMBOL(ifxmips_led_blink_clear);
 
@@ -115,29 +115,29 @@ ifxmips_led_probe(struct platform_device *dev)
 
        ifxmips_led_setup_gpio();
 
-       writel(0, IFXMIPS_LED_AR);
-       writel(0, IFXMIPS_LED_CPU0);
-       writel(0, IFXMIPS_LED_CPU1);
-       writel(LED_CON0_SWU, IFXMIPS_LED_CON0);
-       writel(0, IFXMIPS_LED_CON1);
+       ifxmips_w32(0, IFXMIPS_LED_AR);
+       ifxmips_w32(0, IFXMIPS_LED_CPU0);
+       ifxmips_w32(0, IFXMIPS_LED_CPU1);
+       ifxmips_w32(LED_CON0_SWU, IFXMIPS_LED_CON0);
+       ifxmips_w32(0, IFXMIPS_LED_CON1);
 
        /* setup the clock edge that the shift register is triggered on */
-       writel(readl(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK, IFXMIPS_LED_CON0);
-       writel(readl(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE, IFXMIPS_LED_CON0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK, IFXMIPS_LED_CON0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE, IFXMIPS_LED_CON0);
 
        /* per default leds 15-0 are set */
-       writel(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1);
+       ifxmips_w32(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1);
 
        /* leds are update periodically by the FPID */
-       writel(readl(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK, IFXMIPS_LED_CON1);
-       writel(readl(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI, IFXMIPS_LED_CON1);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK, IFXMIPS_LED_CON1);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI, IFXMIPS_LED_CON1);
 
        /* set led update speed */
-       writel(readl(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK, IFXMIPS_LED_CON1);
-       writel(readl(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED, IFXMIPS_LED_CON1);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK, IFXMIPS_LED_CON1);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED, IFXMIPS_LED_CON1);
 
        /* adsl 0 and 1 leds are updated by the arc */
-       writel(readl(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC, IFXMIPS_LED_CON0);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC, IFXMIPS_LED_CON0);
 
        /* per default, the leds are turned on */
        ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_LED);
index 4d14b89..91e17a9 100644 (file)
@@ -260,7 +260,7 @@ unsigned char got_int = 0;
 static void
 meiLongwordWrite (u32* ul_address, u32 ul_data)
 {
-       writel(ul_data, ul_address);
+       ifxmips_w32(ul_data, ul_address);
        wmb();
        return;
 }                              //    end of "meiLongwordWrite(..."
@@ -277,7 +277,7 @@ static void
 meiLongwordRead (u32* ul_address, u32 * pul_data)
 {
        //*pul_data = *((volatile u32 *)ul_address);
-       *pul_data = readl(ul_address);
+       *pul_data = ifxmips_r32(ul_address);
        wmb();
        return;
 }                              //    end of "meiLongwordRead(..."
@@ -3561,9 +3561,9 @@ ifxmips_mei_init_module (void)
        ifxmips_mei_ceoc_init ();
 #endif
        // power up mei 
-       temp = readl(IFXMIPS_PMU_PWDCR);
+       temp = ifxmips_r32(IFXMIPS_PMU_PWDCR);
        temp &= 0xffff7dbe;
-       writel(temp, IFXMIPS_PMU_PWDCR);
+       ifxmips_w32(temp, IFXMIPS_PMU_PWDCR);
 
 #if defined (CONFIG_ATM_IFXMIPS)
        IFX_ATM_LED_Callback_Register (adsl_led_flash);
index 3742e20..7b55a4d 100644 (file)
@@ -80,7 +80,7 @@ ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
 {
        unsigned int rmc;
 
-       rmc = (readl(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
+       rmc = (ifxmips_r32(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
        if (rmc == 0)
        {
                printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
@@ -97,12 +97,12 @@ rx_int (struct ifx_ssc_port *info)
        unsigned long *tmp_ptr;
        unsigned int rx_valid_cnt;
        /* number of words waiting in the RX FIFO */
-       fifo_fill_lev = (readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
+       fifo_fill_lev = (ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
        bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
        // transfer with 32 bits per entry
        while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
                tmp_ptr = (unsigned long *) info->rxbuf_ptr;
-               *tmp_ptr = readl(IFXMIPS_SSC_RB);
+               *tmp_ptr = ifxmips_r32(IFXMIPS_SSC_RB);
                info->rxbuf_ptr += 4;
                info->stats.rxBytes += 4;
                fifo_fill_lev--;
@@ -111,14 +111,14 @@ rx_int (struct ifx_ssc_port *info)
 
        // now do the rest as mentioned in STATE.RXBV
        while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
-               rx_valid_cnt = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
+               rx_valid_cnt = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
                if (rx_valid_cnt == 0)
                        break;
 
                if (rx_valid_cnt > bytes_in_buf)
                        rx_valid_cnt = bytes_in_buf;
 
-               tmp_val = readl(IFXMIPS_SSC_RB);
+               tmp_val = ifxmips_r32(IFXMIPS_SSC_RB);
 
                for (i = 0; i < rx_valid_cnt; i++)
                {
@@ -134,12 +134,12 @@ rx_int (struct ifx_ssc_port *info)
        {
                disable_irq(IFXMIPS_SSC_RIR);
                wake_up_interruptible (&info->rwait);
-       } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (readl(IFXMIPS_SSC_RXCNT) == 0))
+       } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (ifxmips_r32(IFXMIPS_SSC_RXCNT) == 0))
        {
                if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
-                       writel((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
+                       ifxmips_w32((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
                else
-                       writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET,  IFXMIPS_SSC_RXREQ);
+                       ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET,  IFXMIPS_SSC_RXREQ);
        }
 }
 
@@ -148,8 +148,8 @@ tx_int (struct ifx_ssc_port *info)
 {
 
        int fifo_space, fill, i;
-       fifo_space = ((readl(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
-               - ((readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
+       fifo_space = ((ifxmips_r32(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
+               - ((ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
 
        if (fifo_space == 0)
                return;
@@ -162,7 +162,7 @@ tx_int (struct ifx_ssc_port *info)
        for (i = 0; i < fill / 4; i++)
        {
                // at first 32 bit access
-               writel(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB);
+               ifxmips_w32(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB);
                info->txbuf_ptr += 4;
        }
 
@@ -224,7 +224,7 @@ ifx_ssc_err_int (int irq, void *dev_id)
        unsigned long flags;
 
        local_irq_save (flags);
-       state = readl(IFXMIPS_SSC_STATE);
+       state = ifxmips_r32(IFXMIPS_SSC_STATE);
 
        if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
                info->stats.rxUnErr++;
@@ -252,7 +252,7 @@ ifx_ssc_err_int (int irq, void *dev_id)
        }
 
        if (write_back)
-               writel(write_back, IFXMIPS_SSC_WHBSTATE);
+               ifxmips_w32(write_back, IFXMIPS_SSC_WHBSTATE);
 
        local_irq_restore (flags);
 
@@ -278,12 +278,12 @@ ifx_ssc_abort (struct ifx_ssc_port *info)
        // complete word. The disable cuts the transmission immediatly and 
        // releases the chip selects. This could result in unpredictable 
        // behavior of connected external devices!
-       enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
-       writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
+       enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
+       ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
 
        // flush fifos
-       writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
-       writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
+       ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
+       ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
 
        // free txbuf
        if (info->txbuf != NULL)
@@ -302,10 +302,10 @@ ifx_ssc_abort (struct ifx_ssc_port *info)
        mask_and_ack_ifxmips_irq(IFXMIPS_SSC_EIR);
 
        // clear error flags
-       writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
+       ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
 
        if (enabled)
-               writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
+               ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
 
 }
 
@@ -343,22 +343,22 @@ ifx_ssc_open (struct inode *inode, struct file *filp)
        disable_irq(IFXMIPS_SSC_EIR);
 
        /* Flush and enable TX/RX FIFO */
-       writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
-       writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
+       ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
+       ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
 
        /* logically flush the software FIFOs */
        info->rxbuf_ptr = 0;
        info->txbuf_ptr = 0;
 
        /* clear all error bits */
-       writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
+       ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
 
        // clear pending interrupts
        mask_and_ack_ifxmips_irq(IFXMIPS_SSC_RIR);
        mask_and_ack_ifxmips_irq(IFXMIPS_SSC_TIR);
        mask_and_ack_ifxmips_irq(IFXMIPS_SSC_EIR);
 
-       writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
+       ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
 
        return 0;
 }
@@ -382,7 +382,7 @@ ifx_ssc_close (struct inode *inode, struct file *filp)
        if (!info)
                return -ENXIO;
 
-       writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
+       ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
 
        ifx_ssc_abort(info);
 
@@ -451,13 +451,13 @@ ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_
                enable_irq(IFXMIPS_SSC_RIR);
        } else {
                local_irq_restore(flags);
-               if (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
+               if (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
                        return -EBUSY;
                enable_irq(IFXMIPS_SSC_RIR);
                if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
-                       writel(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
+                       ifxmips_w32(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
                else
-                       writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
+                       ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
        }
 
        __add_wait_queue (&info->rwait, &wait);
@@ -643,12 +643,12 @@ ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
 {
        unsigned long tmp;
 
-       tmp = readl(IFXMIPS_SSC_SFSTAT);
+       tmp = ifxmips_r32(IFXMIPS_SSC_SFSTAT);
        info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
        info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
        info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
        info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
-       tmp = readl(IFXMIPS_SSC_SFCON);
+       tmp = ifxmips_r32(IFXMIPS_SSC_SFCON);
        info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
        info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
 
@@ -661,7 +661,7 @@ ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
 {
        unsigned long tmp;
 
-       tmp = readl(IFXMIPS_SSC_SFCON);
+       tmp = ifxmips_r32(IFXMIPS_SSC_SFCON);
        info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
        info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
        info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
@@ -686,7 +686,7 @@ ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
                return -EINVAL;
 
        // read interrupt bits (they're not changed here)
-       tmp = readl(IFXMIPS_SSC_SFCON) &
+       tmp = ifxmips_r32(IFXMIPS_SSC_SFCON) &
                (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
 
        // set all values with respect to it's bit position (for data and pause 
@@ -698,7 +698,7 @@ ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
        tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
        tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
 
-       writel(tmp, IFXMIPS_SSC_SFCON);
+       ifxmips_w32(tmp, IFXMIPS_SSC_SFCON);
 
        return 0;
 }
@@ -711,12 +711,12 @@ ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
        if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
                return -EINVAL;
 
-       if ((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
-           || (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
+       if ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
+           || (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
                return -EBUSY;
 
-       tmp = (readl(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
-       writel(tmp, IFXMIPS_SSC_SFCON);
+       tmp = (ifxmips_r32(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
+       ifxmips_w32(tmp, IFXMIPS_SSC_SFCON);
        info->opts.modeRxTx = val;
 
        return 0;
@@ -766,20 +766,20 @@ ifx_ssc_sethwopts (struct ifx_ssc_port *info)
 
        local_irq_save (flags);
 
-       writel(bits, IFXMIPS_SSC_CON);
-       writel((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
+       ifxmips_w32(bits, IFXMIPS_SSC_CON);
+       ifxmips_w32((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
                                   (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON);
 
-       writel(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
+       ifxmips_w32(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
 
        //master mode
        if (opts->masterSelect)
-               writel(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
+               ifxmips_w32(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
        else
-               writel(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
+               ifxmips_w32(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
 
        // init serial framing
-       writel(0, IFXMIPS_SSC_SFCON);
+       ifxmips_w32(0, IFXMIPS_SSC_SFCON);
        /* set up the port pins */
        //check for general requirements to switch (external) pad/pin characteristics
        /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
@@ -823,23 +823,23 @@ ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
 
        local_irq_save (flags);
 
-       enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
-       writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
+       enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
+       ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
 
        br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
        wmb();
 
        if (br > 0xffff || ((br == 0) &&
-                       ((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
+                       ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
                local_irq_restore (flags);
                printk ("%s: invalid baudrate %u\n", __func__, baud);
                return -EINVAL;
        }
 
-       writel(br, IFXMIPS_SSC_BR);
+       ifxmips_w32(br, IFXMIPS_SSC_BR);
 
        if (enabled)
-               writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
+               ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
 
        local_irq_restore(flags);
 
@@ -853,8 +853,8 @@ ifx_ssc_hwinit (struct ifx_ssc_port *info)
        unsigned long flags;
        bool enabled;
 
-       enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
-       writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
+       enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
+       ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
 
        if (ifx_ssc_sethwopts (info) < 0)
        {
@@ -871,14 +871,14 @@ ifx_ssc_hwinit (struct ifx_ssc_port *info)
        local_irq_save (flags);
 
        /* TX FIFO */
-       writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
+       ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
        /* RX FIFO */
-       writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
+       ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
 
        local_irq_restore (flags);
 
        if (enabled)
-               writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
+               ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
 
        return 0;
 }
@@ -926,7 +926,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
                /* if the buffers are not empty then the port is */
                /* busy and we shouldn't change things on-the-fly! */
                if (!info->txbuf || !info->rxbuf ||
-                   (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
+                   (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
                        ret_val = -EBUSY;
                        break;
                }
@@ -967,7 +967,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
                ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
                break;
        case IFX_SSC_RXTX_MODE_GET:
-               tmp = readl(IFXMIPS_SSC_CON) &
+               tmp = ifxmips_r32(IFXMIPS_SSC_CON) &
                        (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
                if (from_kernel)
                        *((unsigned int *) data) = tmp;
@@ -991,7 +991,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
                if (tmp > IFX_SSC_MAX_GPO_OUT)
                        ret_val = -EINVAL;
                else
-                       writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
+                       ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
                                 IFXMIPS_SSC_WHBGPOSTAT);
                break;
        case IFX_SSC_GPO_OUT_CLR:
@@ -1004,12 +1004,12 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
                if (tmp > IFX_SSC_MAX_GPO_OUT)
                        ret_val = -EINVAL;
                else {
-                       writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
+                       ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
                                 IFXMIPS_SSC_WHBGPOSTAT);
                }
                break;
        case IFX_SSC_GPO_OUT_GET:
-               tmp = readl(IFXMIPS_SSC_GPOSTAT);
+               tmp = ifxmips_r32(IFXMIPS_SSC_GPOSTAT);
                if (from_kernel)
                        *((unsigned int *) data) = tmp;
                else if (copy_to_user ((void *) data,
@@ -1053,7 +1053,7 @@ ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigne
                /* if the buffers are not empty then the port is */
                /* busy and we shouldn't change things on-the-fly! */
                if (!info->txbuf || !info->rxbuf ||
-                   (readl(IFXMIPS_SSC_STATE)
+                   (ifxmips_r32(IFXMIPS_SSC_STATE)
                     & IFX_SSC_STATE_BUSY)) {
                        ret_val = -EBUSY;
                        break;
@@ -1165,14 +1165,14 @@ ifx_ssc_init (void)
                        info->mapbase = IFXMIPS_SSC_BASE_ADDR;
                }
 
-               writel(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
+               ifxmips_w32(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
 
                init_waitqueue_head (&info->rwait);
 
                local_irq_save (flags);
 
                // init serial framing register
-               writel(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
+               ifxmips_w32(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
 
                ret_val = request_irq(IFXMIPS_SSC_TIR, ifx_ssc_tx_int, IRQF_DISABLED, "ifx_ssc_tx", info);
                if (ret_val)
@@ -1197,7 +1197,7 @@ ifx_ssc_init (void)
                        local_irq_restore (flags);
                        goto irqerr;
                }
-               writel(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
+               ifxmips_w32(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
 
                //enable_irq(IFXMIPS_SSC_TIR);
                //enable_irq(IFXMIPS_SSC_RIR);
@@ -1233,7 +1233,7 @@ ifx_ssc_cleanup_module (void)
        int i;
 
        for (i = 0; i < PORT_CNT; i++) {
-               writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
+               ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
                free_irq(IFXMIPS_SSC_TIR, &isp[i]);
                free_irq(IFXMIPS_SSC_RIR, &isp[i]);
                free_irq(IFXMIPS_SSC_EIR, &isp[i]);
index 3dd41d1..4b9c6ef 100644 (file)
@@ -135,7 +135,7 @@ ifxmips_mtd_probe (void)
        struct mtd_partition *parts = NULL;
        unsigned long uimage_size;
 
-       writel(0x1d7ff, IFXMIPS_EBU_BUSCON0);
+       ifxmips_w32(0x1d7ff, IFXMIPS_EBU_BUSCON0);
 
        ifxmips_map.read = ifxmips_read16;
        ifxmips_map.write = ifxmips_write16;
index 33cdc83..c629360 100644 (file)
@@ -60,8 +60,8 @@ ifxmips_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
                ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
                phy_data;
 
-       while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
-       writel(val, IFXMIPS_PPE32_MDIO_ACC);
+       while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
+       ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
 }
 
 unsigned short
@@ -71,9 +71,9 @@ ifxmips_read_mdio (u32 phy_addr, u32 phy_reg)
                ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
                ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
 
-       writel(val, IFXMIPS_PPE32_MDIO_ACC);
-       while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
-       val = readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
+       ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC);
+       while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
+       val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
 
        return val;
 }
@@ -374,13 +374,13 @@ ifxmips_sw_chip_init (int mode)
        ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
 
        if(mode == REV_MII_MODE)
-               writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
+               ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
        else if(mode == MII_MODE)
-               writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
+               ifxmips_w32((ifxmips_r32(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
 
-       writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
+       ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
 
-       writel(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
+       ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
 
        wmb();
 }
index b191241..dec64e4 100644 (file)
@@ -88,7 +88,7 @@ static void
 ifxmipsasc_stop_rx (struct uart_port *port)
 {
        /* clear the RX enable bit */
-       writel(ASCWHBSTATE_CLRREN, IFXMIPS_ASC1_WHBSTATE);
+       ifxmips_w32(ASCWHBSTATE_CLRREN, IFXMIPS_ASC1_WHBSTATE);
 }
 
 static void
@@ -104,12 +104,12 @@ ifxmipsasc_rx_chars (struct uart_port *port)
        struct tty_struct *tty = port->info->tty;
        unsigned int ch = 0, rsr = 0, fifocnt;
 
-       fifocnt = readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
+       fifocnt = ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
        while (fifocnt--)
        {
                u8 flag = TTY_NORMAL;
-               ch = readl(IFXMIPS_ASC1_RBUF);
-               rsr = (readl(IFXMIPS_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
+               ch = ifxmips_r32(IFXMIPS_ASC1_RBUF);
+               rsr = (ifxmips_r32(IFXMIPS_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
                tty_flip_buffer_push(tty);
                port->icount.rx++;
 
@@ -120,14 +120,14 @@ ifxmipsasc_rx_chars (struct uart_port *port)
                if (rsr & ASCSTATE_ANY) {
                        if (rsr & ASCSTATE_PE) {
                                port->icount.parity++;
-                               writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, IFXMIPS_ASC1_WHBSTATE);
+                               ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, IFXMIPS_ASC1_WHBSTATE);
                        } else if (rsr & ASCSTATE_FE) {
                                port->icount.frame++;
-                               writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, IFXMIPS_ASC1_WHBSTATE);
+                               ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, IFXMIPS_ASC1_WHBSTATE);
                        }
                        if (rsr & ASCSTATE_ROE) {
                                port->icount.overrun++;
-                               writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
+                               ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
                        }
 
                        rsr &= port->read_status_mask;
@@ -166,11 +166,11 @@ ifxmipsasc_tx_chars (struct uart_port *port)
                return;
        }
 
-       while(((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+       while(((ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
                                >> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL)
        {
                if (port->x_char) {
-                       writel(port->x_char, IFXMIPS_ASC1_TBUF);
+                       ifxmips_w32(port->x_char, IFXMIPS_ASC1_TBUF);
                        port->icount.tx++;
                        port->x_char = 0;
                        continue;
@@ -179,7 +179,7 @@ ifxmipsasc_tx_chars (struct uart_port *port)
                if (uart_circ_empty(xmit))
                        break;
 
-               writel(port->info->xmit.buf[port->info->xmit.tail], IFXMIPS_ASC1_TBUF);
+               ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], IFXMIPS_ASC1_TBUF);
                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
                port->icount.tx++;
        }
@@ -191,7 +191,7 @@ ifxmipsasc_tx_chars (struct uart_port *port)
 static irqreturn_t
 ifxmipsasc_tx_int (int irq, void *port)
 {
-       writel(ASC_IRNCR_TIR, IFXMIPS_ASC1_IRNCR);
+       ifxmips_w32(ASC_IRNCR_TIR, IFXMIPS_ASC1_IRNCR);
        ifxmipsasc_start_tx(port);
        mask_and_ack_ifxmips_irq(irq);
 
@@ -202,7 +202,7 @@ static irqreturn_t
 ifxmipsasc_er_int (int irq, void *port)
 {
        /* clear any pending interrupts */
-       writel(readl(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
                        ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, IFXMIPS_ASC1_WHBSTATE);
 
        return IRQ_HANDLED;
@@ -211,7 +211,7 @@ ifxmipsasc_er_int (int irq, void *port)
 static irqreturn_t
 ifxmipsasc_rx_int (int irq, void *port)
 {
-       writel(ASC_IRNCR_RIR, IFXMIPS_ASC1_IRNCR);
+       ifxmips_w32(ASC_IRNCR_RIR, IFXMIPS_ASC1_IRNCR);
        ifxmipsasc_rx_chars((struct uart_port *) port);
        mask_and_ack_ifxmips_irq(irq);
 
@@ -223,7 +223,7 @@ ifxmipsasc_tx_empty (struct uart_port *port)
 {
        int status;
 
-       status = readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
+       status = ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
 
        return status ? 0 : TIOCSER_TEMT;
 }
@@ -251,17 +251,17 @@ ifxmipsasc1_hw_init (void)
 {
        /* this setup was probably already done in ROM/u-boot  but we do it again*/
        /* TODO: GPIO pins are multifunction */
-       writel(readl(IFXMIPS_ASC1_CLC) & ~IFXMIPS_ASC1_CLC_DISS, IFXMIPS_ASC1_CLC);
-       writel((readl(IFXMIPS_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), IFXMIPS_ASC1_CLC);
-       writel(0, IFXMIPS_ASC1_PISEL);
-       writel(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CLC) & ~IFXMIPS_ASC1_CLC_DISS, IFXMIPS_ASC1_CLC);
+       ifxmips_w32((ifxmips_r32(IFXMIPS_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), IFXMIPS_ASC1_CLC);
+       ifxmips_w32(0, IFXMIPS_ASC1_PISEL);
+       ifxmips_w32(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
                ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
-       writel(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
+       ifxmips_w32(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
                ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
        wmb ();
 
        /*framing, overrun, enable */
-       writel(readl(IFXMIPS_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
                IFXMIPS_ASC1_CON);
 }
 
@@ -299,7 +299,7 @@ ifxmipsasc_startup (struct uart_port *port)
                goto err2;
        }
 
-       writel(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
+       ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
                IFXMIPS_ASC1_IRNREN);
 
        local_irq_restore(flags);
@@ -325,13 +325,13 @@ ifxmipsasc_shutdown (struct uart_port *port)
        /*
         * disable the baudrate generator to disable the ASC
         */
-       writel(0, IFXMIPS_ASC1_CON);
+       ifxmips_w32(0, IFXMIPS_ASC1_CON);
 
        /* flush and then disable the fifos */
-       writel(readl(IFXMIPS_ASC1_RXFCON) | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
-       writel(readl(IFXMIPS_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, IFXMIPS_ASC1_RXFCON);
-       writel(readl(IFXMIPS_ASC1_TXFCON) | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
-       writel(readl(IFXMIPS_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, IFXMIPS_ASC1_TXFCON);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_RXFCON) | ASCRXFCON_RXFFLU, IFXMIPS_ASC1_RXFCON);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, IFXMIPS_ASC1_RXFCON);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_TXFCON) | ASCTXFCON_TXFFLU, IFXMIPS_ASC1_TXFCON);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, IFXMIPS_ASC1_TXFCON);
 }
 
 static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
@@ -395,7 +395,7 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new,
        local_irq_save(flags);
 
        /* set up CON */
-       writel(readl(IFXMIPS_ASC1_CON) | con, IFXMIPS_ASC1_CON);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) | con, IFXMIPS_ASC1_CON);
 
        /* Set baud rate - take a divider of 2 into account */
     baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
@@ -403,22 +403,22 @@ static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new,
        quot = quot / 2 - 1;
 
        /* disable the baudrate generator */
-       writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_R, IFXMIPS_ASC1_CON);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) & ~ASCCON_R, IFXMIPS_ASC1_CON);
 
        /* make sure the fractional divider is off */
-       writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_FDE, IFXMIPS_ASC1_CON);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) & ~ASCCON_FDE, IFXMIPS_ASC1_CON);
 
        /* set up to use divisor of 2 */
-       writel(readl(IFXMIPS_ASC1_CON) & ~ASCCON_BRS, IFXMIPS_ASC1_CON);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) & ~ASCCON_BRS, IFXMIPS_ASC1_CON);
 
        /* now we can write the new baudrate into the register */
-       writel(quot, IFXMIPS_ASC1_BG);
+       ifxmips_w32(quot, IFXMIPS_ASC1_BG);
 
        /* turn the baudrate generator back on */
-       writel(readl(IFXMIPS_ASC1_CON) | ASCCON_R, IFXMIPS_ASC1_CON);
+       ifxmips_w32(ifxmips_r32(IFXMIPS_ASC1_CON) | ASCCON_R, IFXMIPS_ASC1_CON);
 
        /* enable rx */
-       writel(ASCWHBSTATE_SETREN, IFXMIPS_ASC1_WHBSTATE);
+       ifxmips_w32(ASCWHBSTATE_SETREN, IFXMIPS_ASC1_WHBSTATE);
 
        local_irq_restore(flags);
 }
@@ -507,7 +507,7 @@ ifxmipsasc_console_write (struct console *co, const char *s, u_int count)
                /* wait until the FIFO is not full */
                do
                {
-                       fifocnt = (readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+                       fifocnt = (ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
                                        >> ASCFSTAT_TXFFLOFF;
                } while (fifocnt == IFXMIPSASC_TXFIFO_FULL);
 
@@ -518,14 +518,14 @@ ifxmipsasc_console_write (struct console *co, const char *s, u_int count)
 
                if (s[i] == '\n')
                {
-                       writel('\r', IFXMIPS_ASC1_TBUF);
+                       ifxmips_w32('\r', IFXMIPS_ASC1_TBUF);
                        do
                        {
-                               fifocnt = (readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
+                               fifocnt = (ifxmips_r32(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
                                        >> ASCFSTAT_TXFFLOFF;
                        } while (fifocnt == IFXMIPSASC_TXFIFO_FULL);
                }
-               writel(s[i], IFXMIPS_ASC1_TBUF);
+               ifxmips_w32(s[i], IFXMIPS_ASC1_TBUF);
        }
 
        local_irq_restore(flags);
index d631f4a..b0c554d 100644 (file)
@@ -46,8 +46,8 @@ ifxmips_wdt_enable (unsigned int timeout)
        int retval = 0;
 
        /* clock divider & prewarning limit */
-       wdt_clkdiv = 1 << (7 * IFXMIPS_BIU_WDT_CR_CLKDIV_GET(readl(IFXMIPS_BIU_WDT_CR)));
-       wdt_pwl = 0x8000 >> IFXMIPS_BIU_WDT_CR_PWL_GET(readl(IFXMIPS_BIU_WDT_CR));
+       wdt_clkdiv = 1 << (7 * IFXMIPS_BIU_WDT_CR_CLKDIV_GET(ifxmips_r32(IFXMIPS_BIU_WDT_CR)));
+       wdt_pwl = 0x8000 >> IFXMIPS_BIU_WDT_CR_PWL_GET(ifxmips_r32(IFXMIPS_BIU_WDT_CR));
 
        //TODO
        printk("WARNING FUNCTION CALL MISSING!!!");
@@ -68,21 +68,21 @@ ifxmips_wdt_enable (unsigned int timeout)
        }
 
        /* Write first part of password access */
-       writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
+       ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
 
-       wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
+       wdt_cr = ifxmips_r32(IFXMIPS_BIU_WDT_CR);
        wdt_cr &= (!IFXMIPS_BIU_WDT_CR_PW_SET(0xff) &
                   !IFXMIPS_BIU_WDT_CR_PWL_SET(0x3) &
                   !IFXMIPS_BIU_WDT_CR_CLKDIV_SET(0x3) &
                   !IFXMIPS_BIU_WDT_CR_RELOAD_SET(0xffff));
 
        wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) |
-                  IFXMIPS_BIU_WDT_CR_PWL_SET(IFXMIPS_BIU_WDT_CR_PWL_GET(readl(IFXMIPS_BIU_WDT_CR))) |
-                  IFXMIPS_BIU_WDT_CR_CLKDIV_SET(IFXMIPS_BIU_WDT_CR_CLKDIV_GET(readl(IFXMIPS_BIU_WDT_CR))) |
+                  IFXMIPS_BIU_WDT_CR_PWL_SET(IFXMIPS_BIU_WDT_CR_PWL_GET(ifxmips_r32(IFXMIPS_BIU_WDT_CR))) |
+                  IFXMIPS_BIU_WDT_CR_CLKDIV_SET(IFXMIPS_BIU_WDT_CR_CLKDIV_GET(ifxmips_r32(IFXMIPS_BIU_WDT_CR))) |
                   IFXMIPS_BIU_WDT_CR_RELOAD_SET(wdt_reload) |
                   IFXMIPS_BIU_WDT_CR_GEN);
 
-       writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
+       ifxmips_w32(wdt_cr, IFXMIPS_BIU_WDT_CR);
 
        printk("watchdog enabled\n");
 
@@ -93,8 +93,8 @@ out:
 void
 ifxmips_wdt_disable (void)
 {
-       writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
-       writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2), IFXMIPS_BIU_WDT_CR);
+       ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
+       ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2), IFXMIPS_BIU_WDT_CR);
 
        printk("watchdog disabled\n");
 }
@@ -105,9 +105,9 @@ ifxmips_wdt_enable_feature (int en, int type)
 {
        unsigned int wdt_cr = 0;
 
-       writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
+       ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
 
-       wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
+       wdt_cr = ifxmips_r32(IFXMIPS_BIU_WDT_CR);
 
        if (en)
        {
@@ -118,7 +118,7 @@ ifxmips_wdt_enable_feature (int en, int type)
                wdt_cr |= IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2);
        }
 
-       writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
+       ifxmips_w32(wdt_cr, IFXMIPS_BIU_WDT_CR);
 }
 
 void
@@ -126,14 +126,14 @@ ifxmips_wdt_prewarning_limit (int pwl)
 {
        unsigned int wdt_cr = 0;
 
-       wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
-       writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
+       wdt_cr = ifxmips_r32(IFXMIPS_BIU_WDT_CR);
+       ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
 
        wdt_cr &= 0xf300ffff;
        wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | IFXMIPS_BIU_WDT_CR_PWL_SET(pwl));
 
        /* Set reload value in second password access */
-       writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
+       ifxmips_w32(wdt_cr, IFXMIPS_BIU_WDT_CR);
 }
 
 void
@@ -141,14 +141,14 @@ ifxmips_wdt_set_clkdiv (int clkdiv)
 {
        unsigned int wdt_cr = 0;
 
-       wdt_cr = readl(IFXMIPS_BIU_WDT_CR);
-       writel(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
+       wdt_cr = ifxmips_r32(IFXMIPS_BIU_WDT_CR);
+       ifxmips_w32(IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW1), IFXMIPS_BIU_WDT_CR);
 
        wdt_cr &= 0xfc00ffff;
        wdt_cr |= (IFXMIPS_BIU_WDT_CR_PW_SET(IFXMIPS_WDT_PW2) | IFXMIPS_BIU_WDT_CR_CLKDIV_SET(clkdiv));
 
        /* Set reload value in second password access */
-       writel(wdt_cr, IFXMIPS_BIU_WDT_CR);
+       ifxmips_w32(wdt_cr, IFXMIPS_BIU_WDT_CR);
 }
 
 static int
@@ -189,7 +189,7 @@ ifxmips_wdt_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
                break;
 
        case IFXMIPS_WDT_IOC_GET_STATUS:
-               user_arg = readl(IFXMIPS_BIU_WDT_SR);
+               user_arg = ifxmips_r32(IFXMIPS_BIU_WDT_SR);
                copy_to_user((int*)arg, (int*)&user_arg, sizeof(int));
                break;
 
@@ -244,9 +244,9 @@ ifxmips_wdt_register_proc_read (char *buf, char **start, off_t offset, int count
 
        len += sprintf (buf + len, "IFXMIPS_BIU_WDT_PROC_READ\n");
        len += sprintf (buf + len, "IFXMIPS_BIU_WDT_CR(0x%08x)  : 0x%08x\n",
-                       (unsigned int)IFXMIPS_BIU_WDT_CR, readl(IFXMIPS_BIU_WDT_CR));
+                       (unsigned int)IFXMIPS_BIU_WDT_CR, ifxmips_r32(IFXMIPS_BIU_WDT_CR));
        len += sprintf (buf + len, "IFXMIPS_BIU_WDT_SR(0x%08x)  : 0x%08x\n",
-                       (unsigned int)IFXMIPS_BIU_WDT_SR, readl(IFXMIPS_BIU_WDT_SR));
+                       (unsigned int)IFXMIPS_BIU_WDT_SR, ifxmips_r32(IFXMIPS_BIU_WDT_SR));
 
        *eof = 1;
 
index 3575596..70e5ec9 100644 (file)
@@ -20,6 +20,8 @@
 #ifndef _IFXMIPS_H__
 #define _IFXMIPS_H__
 
+#define ifxmips_r32(reg) __raw_readl(reg)
+#define ifxmips_w32(val,reg) __raw_writel(val,reg)
 
 /*------------ GENERAL */
 
diff --git a/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h b/target/linux/ifxmips/files/include/asm-mips/mach-ifxmips/gpio.h
new file mode 100644 (file)
index 0000000..3083b88
--- /dev/null
@@ -0,0 +1,74 @@
+/*
+ *   include/asm-mips/mach-ifxmips/gpio.h 
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
+
+#ifndef _IFXMIPS_GPIO_H_
+#define _IFXMIPS_GPIO_H_
+
+#include <asm/ifxmips/ifxmips.h>
+
+static inline int gpio_direction_input(unsigned gpio) {
+       ifxmips_port_set_dir_in(0, gpio);
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value) {
+       ifxmips_port_set_dir_out(0, gpio);
+}
+
+static inline int gpio_get_value(unsigned gpio) {
+       ifxmips_port_get_input(0, gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value) {
+       ifxmips_port_set_output(0, gpio);
+}
+
+static inline int gpio_request(unsigned gpio, const char *label) {
+       return 0;
+}
+
+static inline void gpio_free(unsigned gpio) {
+}
+
+static inline int gpio_to_irq(unsigned gpio) {
+       return 0;
+}
+
+static inline int irq_to_gpio(unsigned irq) {
+       return 0;
+}
+
+static inline int gpio_cansleep(unsigned gpio) {
+        return 0;
+}
+
+static inline int gpio_get_value_cansleep(unsigned gpio) {
+        might_sleep();
+        return gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value_cansleep(unsigned gpio, int value) {
+        might_sleep();
+        gpio_set_value(gpio, value);
+}
+
+#endif
+
index e836cf0..f178abf 100644 (file)
@@ -1,7 +1,28 @@
+/*
+ *   include/asm-mips/mach-ifxmips/irq.h 
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ *
+ */
+
 #ifndef __IFXMIPS_IRQ_H
 #define __IFXMIPS_IRQ_H
 
-#define NR_IRQS    256 
+#define NR_IRQS    256
 #include_next <irq.h>
 
 #endif
index 0608f8a..60d2fe7 100644 (file)
@@ -2,7 +2,7 @@ Index: linux-2.6.25.4/arch/mips/Kconfig
 ===================================================================
 --- linux-2.6.25.4.orig/arch/mips/Kconfig
 +++ linux-2.6.25.4/arch/mips/Kconfig
-@@ -78,6 +78,19 @@ config MIPS_COBALT
+@@ -78,6 +78,21 @@ config MIPS_COBALT
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select GENERIC_HARDIRQS_NO__DO_IRQ
  
@@ -18,6 +18,8 @@ Index: linux-2.6.25.4/arch/mips/Kconfig
 +      select SYS_SUPPORTS_32BIT_KERNEL
 +      select SYS_HAS_EARLY_PRINTK
 +      select HW_HAS_PCI
++      select GENERIC_GPIO 
++      select SWAP_IO_SPACE
 +
  config MACH_DECSTATION
        bool "DECstations"