get rid of CRLF encoding in various files

SVN-Revision: 21462

diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h
index cecd279b393d53f4b4bc363ff2b71ea7421af603..3a4b1350e40d7397e837af63aec7f24e735ed3fb 100644 (file)
--- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h
+++ b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h
@@ -1,50 +1,50 @@
-/* Settings for Denali DDR SDRAM controller */\r
-/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */\r
-#define MC_DC0_VALUE   0x1B1B\r
-#define MC_DC1_VALUE   0x0\r
-#define MC_DC2_VALUE   0x0\r
-#define MC_DC3_VALUE   0x0\r
-#define MC_DC4_VALUE   0x0\r
-#define MC_DC5_VALUE   0x200\r
-#define MC_DC6_VALUE   0x605\r
-#define MC_DC7_VALUE   0x303\r
-#define MC_DC8_VALUE   0x102\r
-#define MC_DC9_VALUE   0x70a\r
-#define MC_DC10_VALUE  0x203\r
-#define MC_DC11_VALUE  0xc02\r
-#define MC_DC12_VALUE  0x1C8\r
-#define MC_DC13_VALUE  0x1\r
-#define MC_DC14_VALUE  0x0\r
-#define MC_DC15_VALUE  0xf3c\r
-#define MC_DC16_VALUE  0xC800\r
-#define MC_DC17_VALUE  0xd\r
-#define MC_DC18_VALUE  0x300\r
-#define MC_DC19_VALUE  0x200\r
-#define MC_DC20_VALUE  0xA03\r
-#define MC_DC21_VALUE  0x1d00\r
-#define MC_DC22_VALUE  0x1d1d\r
-#define MC_DC23_VALUE  0x0\r
-#define MC_DC24_VALUE  0x5e   /* was 0x7f */\r
-#define MC_DC25_VALUE  0x0\r
-#define MC_DC26_VALUE  0x0\r
-#define MC_DC27_VALUE  0x0\r
-#define MC_DC28_VALUE  0x510\r
-#define MC_DC29_VALUE  0x2d89\r
-#define MC_DC30_VALUE  0x8300\r
-#define MC_DC31_VALUE  0x0\r
-#define MC_DC32_VALUE  0x0\r
-#define MC_DC33_VALUE  0x0\r
-#define MC_DC34_VALUE  0x0\r
-#define MC_DC35_VALUE  0x0\r
-#define MC_DC36_VALUE  0x0\r
-#define MC_DC37_VALUE  0x0\r
-#define MC_DC38_VALUE  0x0\r
-#define MC_DC39_VALUE  0x0\r
-#define MC_DC40_VALUE  0x0\r
-#define MC_DC41_VALUE  0x0\r
-#define MC_DC42_VALUE  0x0\r
-#define MC_DC43_VALUE  0x0\r
-#define MC_DC44_VALUE  0x0\r
-#define MC_DC45_VALUE  0x500\r
-//#define MC_DC45_VALUE        0x400\r
-#define MC_DC46_VALUE  0x0\r
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE   0x1B1B
+#define MC_DC1_VALUE   0x0
+#define MC_DC2_VALUE   0x0
+#define MC_DC3_VALUE   0x0
+#define MC_DC4_VALUE   0x0
+#define MC_DC5_VALUE   0x200
+#define MC_DC6_VALUE   0x605
+#define MC_DC7_VALUE   0x303
+#define MC_DC8_VALUE   0x102
+#define MC_DC9_VALUE   0x70a
+#define MC_DC10_VALUE  0x203
+#define MC_DC11_VALUE  0xc02
+#define MC_DC12_VALUE  0x1C8
+#define MC_DC13_VALUE  0x1
+#define MC_DC14_VALUE  0x0
+#define MC_DC15_VALUE  0xf3c
+#define MC_DC16_VALUE  0xC800
+#define MC_DC17_VALUE  0xd
+#define MC_DC18_VALUE  0x300
+#define MC_DC19_VALUE  0x200
+#define MC_DC20_VALUE  0xA03
+#define MC_DC21_VALUE  0x1d00
+#define MC_DC22_VALUE  0x1d1d
+#define MC_DC23_VALUE  0x0
+#define MC_DC24_VALUE  0x5e   /* was 0x7f */
+#define MC_DC25_VALUE  0x0
+#define MC_DC26_VALUE  0x0
+#define MC_DC27_VALUE  0x0
+#define MC_DC28_VALUE  0x510
+#define MC_DC29_VALUE  0x2d89
+#define MC_DC30_VALUE  0x8300
+#define MC_DC31_VALUE  0x0
+#define MC_DC32_VALUE  0x0
+#define MC_DC33_VALUE  0x0
+#define MC_DC34_VALUE  0x0
+#define MC_DC35_VALUE  0x0
+#define MC_DC36_VALUE  0x0
+#define MC_DC37_VALUE  0x0
+#define MC_DC38_VALUE  0x0
+#define MC_DC39_VALUE  0x0
+#define MC_DC40_VALUE  0x0
+#define MC_DC41_VALUE  0x0
+#define MC_DC42_VALUE  0x0
+#define MC_DC43_VALUE  0x0
+#define MC_DC44_VALUE  0x0
+#define MC_DC45_VALUE  0x500
+//#define MC_DC45_VALUE        0x400
+#define MC_DC46_VALUE  0x0

diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h
index 385f7e4e5815a0471e782e54bb3e10d87318be8e..fd155973ee3cd5d5d56d13ead04cc070b7141673 100644 (file)
--- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h
+++ b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h
@@ -1,50 +1,50 @@
-/* Settings for Denali DDR SDRAM controller */\r
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */\r
-#define MC_DC0_VALUE   0x1B1B\r
-#define MC_DC1_VALUE   0x0\r
-#define MC_DC2_VALUE   0x0\r
-#define MC_DC3_VALUE   0x0\r
-#define MC_DC4_VALUE   0x0\r
-#define MC_DC5_VALUE   0x200\r
-#define MC_DC6_VALUE   0x605\r
-#define MC_DC7_VALUE   0x303\r
-#define MC_DC8_VALUE   0x102\r
-#define MC_DC9_VALUE   0x70a\r
-#define MC_DC10_VALUE  0x203\r
-#define MC_DC11_VALUE  0xc02\r
-#define MC_DC12_VALUE  0x1C8\r
-#define MC_DC13_VALUE  0x1\r
-#define MC_DC14_VALUE  0x0\r
-#define MC_DC15_VALUE  0xf3c  /* WDQS tuning for clk_wr*/\r
-#define MC_DC16_VALUE  0xC800\r
-#define MC_DC17_VALUE  0xd\r
-#define MC_DC18_VALUE  0x300\r
-#define MC_DC19_VALUE  0x200\r
-#define MC_DC20_VALUE  0xA04  /* A04 for reference board, A03 for Eval board */\r
-#define MC_DC21_VALUE  0x1200\r
-#define MC_DC22_VALUE  0x1212\r
-#define MC_DC23_VALUE  0x0\r
-#define MC_DC24_VALUE  0x5e   /* WDQS Tuning for DQS */\r
-#define MC_DC25_VALUE  0x0\r
-#define MC_DC26_VALUE  0x0\r
-#define MC_DC27_VALUE  0x0\r
-#define MC_DC28_VALUE  0x510\r
-#define MC_DC29_VALUE  0x2d89\r
-#define MC_DC30_VALUE  0x8300\r
-#define MC_DC31_VALUE  0x0\r
-#define MC_DC32_VALUE  0x0\r
-#define MC_DC33_VALUE  0x0\r
-#define MC_DC34_VALUE  0x0\r
-#define MC_DC35_VALUE  0x0\r
-#define MC_DC36_VALUE  0x0\r
-#define MC_DC37_VALUE  0x0\r
-#define MC_DC38_VALUE  0x0\r
-#define MC_DC39_VALUE  0x0\r
-#define MC_DC40_VALUE  0x0\r
-#define MC_DC41_VALUE  0x0\r
-#define MC_DC42_VALUE  0x0\r
-#define MC_DC43_VALUE  0x0\r
-#define MC_DC44_VALUE  0x0\r
-#define MC_DC45_VALUE  0x500\r
-//#define MC_DC45_VALUE        0x400\r
-#define MC_DC46_VALUE  0x0\r
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE   0x1B1B
+#define MC_DC1_VALUE   0x0
+#define MC_DC2_VALUE   0x0
+#define MC_DC3_VALUE   0x0
+#define MC_DC4_VALUE   0x0
+#define MC_DC5_VALUE   0x200
+#define MC_DC6_VALUE   0x605
+#define MC_DC7_VALUE   0x303
+#define MC_DC8_VALUE   0x102
+#define MC_DC9_VALUE   0x70a
+#define MC_DC10_VALUE  0x203
+#define MC_DC11_VALUE  0xc02
+#define MC_DC12_VALUE  0x1C8
+#define MC_DC13_VALUE  0x1
+#define MC_DC14_VALUE  0x0
+#define MC_DC15_VALUE  0xf3c  /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE  0xC800
+#define MC_DC17_VALUE  0xd
+#define MC_DC18_VALUE  0x300
+#define MC_DC19_VALUE  0x200
+#define MC_DC20_VALUE  0xA04  /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE  0x1200
+#define MC_DC22_VALUE  0x1212
+#define MC_DC23_VALUE  0x0
+#define MC_DC24_VALUE  0x5e   /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE  0x0
+#define MC_DC26_VALUE  0x0
+#define MC_DC27_VALUE  0x0
+#define MC_DC28_VALUE  0x510
+#define MC_DC29_VALUE  0x2d89
+#define MC_DC30_VALUE  0x8300
+#define MC_DC31_VALUE  0x0
+#define MC_DC32_VALUE  0x0
+#define MC_DC33_VALUE  0x0
+#define MC_DC34_VALUE  0x0
+#define MC_DC35_VALUE  0x0
+#define MC_DC36_VALUE  0x0
+#define MC_DC37_VALUE  0x0
+#define MC_DC38_VALUE  0x0
+#define MC_DC39_VALUE  0x0
+#define MC_DC40_VALUE  0x0
+#define MC_DC41_VALUE  0x0
+#define MC_DC42_VALUE  0x0
+#define MC_DC43_VALUE  0x0
+#define MC_DC44_VALUE  0x0
+#define MC_DC45_VALUE  0x500
+//#define MC_DC45_VALUE        0x400
+#define MC_DC46_VALUE  0x0

diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h
index cecd279b393d53f4b4bc363ff2b71ea7421af603..3a4b1350e40d7397e837af63aec7f24e735ed3fb 100644 (file)
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h
+++ b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings.h
@@ -1,50 +1,50 @@
-/* Settings for Denali DDR SDRAM controller */\r
-/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */\r
-#define MC_DC0_VALUE   0x1B1B\r
-#define MC_DC1_VALUE   0x0\r
-#define MC_DC2_VALUE   0x0\r
-#define MC_DC3_VALUE   0x0\r
-#define MC_DC4_VALUE   0x0\r
-#define MC_DC5_VALUE   0x200\r
-#define MC_DC6_VALUE   0x605\r
-#define MC_DC7_VALUE   0x303\r
-#define MC_DC8_VALUE   0x102\r
-#define MC_DC9_VALUE   0x70a\r
-#define MC_DC10_VALUE  0x203\r
-#define MC_DC11_VALUE  0xc02\r
-#define MC_DC12_VALUE  0x1C8\r
-#define MC_DC13_VALUE  0x1\r
-#define MC_DC14_VALUE  0x0\r
-#define MC_DC15_VALUE  0xf3c\r
-#define MC_DC16_VALUE  0xC800\r
-#define MC_DC17_VALUE  0xd\r
-#define MC_DC18_VALUE  0x300\r
-#define MC_DC19_VALUE  0x200\r
-#define MC_DC20_VALUE  0xA03\r
-#define MC_DC21_VALUE  0x1d00\r
-#define MC_DC22_VALUE  0x1d1d\r
-#define MC_DC23_VALUE  0x0\r
-#define MC_DC24_VALUE  0x5e   /* was 0x7f */\r
-#define MC_DC25_VALUE  0x0\r
-#define MC_DC26_VALUE  0x0\r
-#define MC_DC27_VALUE  0x0\r
-#define MC_DC28_VALUE  0x510\r
-#define MC_DC29_VALUE  0x2d89\r
-#define MC_DC30_VALUE  0x8300\r
-#define MC_DC31_VALUE  0x0\r
-#define MC_DC32_VALUE  0x0\r
-#define MC_DC33_VALUE  0x0\r
-#define MC_DC34_VALUE  0x0\r
-#define MC_DC35_VALUE  0x0\r
-#define MC_DC36_VALUE  0x0\r
-#define MC_DC37_VALUE  0x0\r
-#define MC_DC38_VALUE  0x0\r
-#define MC_DC39_VALUE  0x0\r
-#define MC_DC40_VALUE  0x0\r
-#define MC_DC41_VALUE  0x0\r
-#define MC_DC42_VALUE  0x0\r
-#define MC_DC43_VALUE  0x0\r
-#define MC_DC44_VALUE  0x0\r
-#define MC_DC45_VALUE  0x500\r
-//#define MC_DC45_VALUE        0x400\r
-#define MC_DC46_VALUE  0x0\r
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE   0x1B1B
+#define MC_DC1_VALUE   0x0
+#define MC_DC2_VALUE   0x0
+#define MC_DC3_VALUE   0x0
+#define MC_DC4_VALUE   0x0
+#define MC_DC5_VALUE   0x200
+#define MC_DC6_VALUE   0x605
+#define MC_DC7_VALUE   0x303
+#define MC_DC8_VALUE   0x102
+#define MC_DC9_VALUE   0x70a
+#define MC_DC10_VALUE  0x203
+#define MC_DC11_VALUE  0xc02
+#define MC_DC12_VALUE  0x1C8
+#define MC_DC13_VALUE  0x1
+#define MC_DC14_VALUE  0x0
+#define MC_DC15_VALUE  0xf3c
+#define MC_DC16_VALUE  0xC800
+#define MC_DC17_VALUE  0xd
+#define MC_DC18_VALUE  0x300
+#define MC_DC19_VALUE  0x200
+#define MC_DC20_VALUE  0xA03
+#define MC_DC21_VALUE  0x1d00
+#define MC_DC22_VALUE  0x1d1d
+#define MC_DC23_VALUE  0x0
+#define MC_DC24_VALUE  0x5e   /* was 0x7f */
+#define MC_DC25_VALUE  0x0
+#define MC_DC26_VALUE  0x0
+#define MC_DC27_VALUE  0x0
+#define MC_DC28_VALUE  0x510
+#define MC_DC29_VALUE  0x2d89
+#define MC_DC30_VALUE  0x8300
+#define MC_DC31_VALUE  0x0
+#define MC_DC32_VALUE  0x0
+#define MC_DC33_VALUE  0x0
+#define MC_DC34_VALUE  0x0
+#define MC_DC35_VALUE  0x0
+#define MC_DC36_VALUE  0x0
+#define MC_DC37_VALUE  0x0
+#define MC_DC38_VALUE  0x0
+#define MC_DC39_VALUE  0x0
+#define MC_DC40_VALUE  0x0
+#define MC_DC41_VALUE  0x0
+#define MC_DC42_VALUE  0x0
+#define MC_DC43_VALUE  0x0
+#define MC_DC44_VALUE  0x0
+#define MC_DC45_VALUE  0x500
+//#define MC_DC45_VALUE        0x400
+#define MC_DC46_VALUE  0x0

diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h
index 385f7e4e5815a0471e782e54bb3e10d87318be8e..fd155973ee3cd5d5d56d13ead04cc070b7141673 100644 (file)
--- a/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h
+++ b/package/uboot-lantiq/files/board/infineon/easy50712/ddr_settings_r111.h
@@ -1,50 +1,50 @@
-/* Settings for Denali DDR SDRAM controller */\r
-/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */\r
-#define MC_DC0_VALUE   0x1B1B\r
-#define MC_DC1_VALUE   0x0\r
-#define MC_DC2_VALUE   0x0\r
-#define MC_DC3_VALUE   0x0\r
-#define MC_DC4_VALUE   0x0\r
-#define MC_DC5_VALUE   0x200\r
-#define MC_DC6_VALUE   0x605\r
-#define MC_DC7_VALUE   0x303\r
-#define MC_DC8_VALUE   0x102\r
-#define MC_DC9_VALUE   0x70a\r
-#define MC_DC10_VALUE  0x203\r
-#define MC_DC11_VALUE  0xc02\r
-#define MC_DC12_VALUE  0x1C8\r
-#define MC_DC13_VALUE  0x1\r
-#define MC_DC14_VALUE  0x0\r
-#define MC_DC15_VALUE  0xf3c  /* WDQS tuning for clk_wr*/\r
-#define MC_DC16_VALUE  0xC800\r
-#define MC_DC17_VALUE  0xd\r
-#define MC_DC18_VALUE  0x300\r
-#define MC_DC19_VALUE  0x200\r
-#define MC_DC20_VALUE  0xA04  /* A04 for reference board, A03 for Eval board */\r
-#define MC_DC21_VALUE  0x1200\r
-#define MC_DC22_VALUE  0x1212\r
-#define MC_DC23_VALUE  0x0\r
-#define MC_DC24_VALUE  0x5e   /* WDQS Tuning for DQS */\r
-#define MC_DC25_VALUE  0x0\r
-#define MC_DC26_VALUE  0x0\r
-#define MC_DC27_VALUE  0x0\r
-#define MC_DC28_VALUE  0x510\r
-#define MC_DC29_VALUE  0x2d89\r
-#define MC_DC30_VALUE  0x8300\r
-#define MC_DC31_VALUE  0x0\r
-#define MC_DC32_VALUE  0x0\r
-#define MC_DC33_VALUE  0x0\r
-#define MC_DC34_VALUE  0x0\r
-#define MC_DC35_VALUE  0x0\r
-#define MC_DC36_VALUE  0x0\r
-#define MC_DC37_VALUE  0x0\r
-#define MC_DC38_VALUE  0x0\r
-#define MC_DC39_VALUE  0x0\r
-#define MC_DC40_VALUE  0x0\r
-#define MC_DC41_VALUE  0x0\r
-#define MC_DC42_VALUE  0x0\r
-#define MC_DC43_VALUE  0x0\r
-#define MC_DC44_VALUE  0x0\r
-#define MC_DC45_VALUE  0x500\r
-//#define MC_DC45_VALUE        0x400\r
-#define MC_DC46_VALUE  0x0\r
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE   0x1B1B
+#define MC_DC1_VALUE   0x0
+#define MC_DC2_VALUE   0x0
+#define MC_DC3_VALUE   0x0
+#define MC_DC4_VALUE   0x0
+#define MC_DC5_VALUE   0x200
+#define MC_DC6_VALUE   0x605
+#define MC_DC7_VALUE   0x303
+#define MC_DC8_VALUE   0x102
+#define MC_DC9_VALUE   0x70a
+#define MC_DC10_VALUE  0x203
+#define MC_DC11_VALUE  0xc02
+#define MC_DC12_VALUE  0x1C8
+#define MC_DC13_VALUE  0x1
+#define MC_DC14_VALUE  0x0
+#define MC_DC15_VALUE  0xf3c  /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE  0xC800
+#define MC_DC17_VALUE  0xd
+#define MC_DC18_VALUE  0x300
+#define MC_DC19_VALUE  0x200
+#define MC_DC20_VALUE  0xA04  /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE  0x1200
+#define MC_DC22_VALUE  0x1212
+#define MC_DC23_VALUE  0x0
+#define MC_DC24_VALUE  0x5e   /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE  0x0
+#define MC_DC26_VALUE  0x0
+#define MC_DC27_VALUE  0x0
+#define MC_DC28_VALUE  0x510
+#define MC_DC29_VALUE  0x2d89
+#define MC_DC30_VALUE  0x8300
+#define MC_DC31_VALUE  0x0
+#define MC_DC32_VALUE  0x0
+#define MC_DC33_VALUE  0x0
+#define MC_DC34_VALUE  0x0
+#define MC_DC35_VALUE  0x0
+#define MC_DC36_VALUE  0x0
+#define MC_DC37_VALUE  0x0
+#define MC_DC38_VALUE  0x0
+#define MC_DC39_VALUE  0x0
+#define MC_DC40_VALUE  0x0
+#define MC_DC41_VALUE  0x0
+#define MC_DC42_VALUE  0x0
+#define MC_DC43_VALUE  0x0
+#define MC_DC44_VALUE  0x0
+#define MC_DC45_VALUE  0x500
+//#define MC_DC45_VALUE        0x400
+#define MC_DC46_VALUE  0x0

diff --git a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h
index b00177e0a5dd70fdd30a7459c1461295caf5e79a..45daa188d3a6a8f84dc995bb89a3d7d8baacc781 100644 (file)
--- a/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h
+++ b/package/uboot-lantiq/files/board/infineon/easy50812/ar9_ddr196_settings.h
@@ -1,51 +1,51 @@
-/* Settings for Denali DDR SDRAM controller */\r
-/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */\r
-\r
-#define MC_DC0_VALUE   0x1B1B\r
-#define MC_DC1_VALUE   0x0\r
-#define MC_DC2_VALUE   0x0\r
-#define MC_DC3_VALUE   0x0\r
-#define MC_DC4_VALUE   0x0\r
-#define MC_DC5_VALUE   0x200\r
-#define MC_DC6_VALUE   0x306\r
-#define MC_DC7_VALUE   0x303\r
-#define MC_DC8_VALUE   0x102\r
-#define MC_DC9_VALUE   0x80B\r
-#define MC_DC10_VALUE  0x203\r
-#define MC_DC11_VALUE  0xD02\r
-#define MC_DC12_VALUE  0x1C8\r
-#define MC_DC13_VALUE  0x1\r
-#define MC_DC14_VALUE  0x0\r
-#define MC_DC15_VALUE  0x144  /* WDQS tuning for clk_wr*/\r
-#define MC_DC16_VALUE  0xC800\r
-#define MC_DC17_VALUE  0xF\r
-#define MC_DC18_VALUE  0x301\r
-#define MC_DC19_VALUE  0x200\r
-#define MC_DC20_VALUE  0xA04  /* A04 for reference board, A03 for Eval board */\r
-#define MC_DC21_VALUE  0x1200\r
-#define MC_DC22_VALUE  0x1212\r
-#define MC_DC23_VALUE  0x0\r
-#define MC_DC24_VALUE  0x66   /* WDQS Tuning for DQS */\r
-#define MC_DC25_VALUE  0x0\r
-#define MC_DC26_VALUE  0x0\r
-#define MC_DC27_VALUE  0x0\r
-#define MC_DC28_VALUE  0x5FB\r
-#define MC_DC29_VALUE  0x35DF\r
-#define MC_DC30_VALUE  0x99E9\r
-#define MC_DC31_VALUE  0x0\r
-#define MC_DC32_VALUE  0x0\r
-#define MC_DC33_VALUE  0x0\r
-#define MC_DC34_VALUE  0x0\r
-#define MC_DC35_VALUE  0x0\r
-#define MC_DC36_VALUE  0x0\r
-#define MC_DC37_VALUE  0x0\r
-#define MC_DC38_VALUE  0x0\r
-#define MC_DC39_VALUE  0x0\r
-#define MC_DC40_VALUE  0x0\r
-#define MC_DC41_VALUE  0x0\r
-#define MC_DC42_VALUE  0x0\r
-#define MC_DC43_VALUE  0x0\r
-#define MC_DC44_VALUE  0x0\r
-#define MC_DC45_VALUE  0x600\r
-//#define MC_DC45_VALUE        0x400\r
-#define MC_DC46_VALUE  0x0\r
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
+
+#define MC_DC0_VALUE   0x1B1B
+#define MC_DC1_VALUE   0x0
+#define MC_DC2_VALUE   0x0
+#define MC_DC3_VALUE   0x0
+#define MC_DC4_VALUE   0x0
+#define MC_DC5_VALUE   0x200
+#define MC_DC6_VALUE   0x306
+#define MC_DC7_VALUE   0x303
+#define MC_DC8_VALUE   0x102
+#define MC_DC9_VALUE   0x80B
+#define MC_DC10_VALUE  0x203
+#define MC_DC11_VALUE  0xD02
+#define MC_DC12_VALUE  0x1C8
+#define MC_DC13_VALUE  0x1
+#define MC_DC14_VALUE  0x0
+#define MC_DC15_VALUE  0x144  /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE  0xC800
+#define MC_DC17_VALUE  0xF
+#define MC_DC18_VALUE  0x301
+#define MC_DC19_VALUE  0x200
+#define MC_DC20_VALUE  0xA04  /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE  0x1200
+#define MC_DC22_VALUE  0x1212
+#define MC_DC23_VALUE  0x0
+#define MC_DC24_VALUE  0x66   /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE  0x0
+#define MC_DC26_VALUE  0x0
+#define MC_DC27_VALUE  0x0
+#define MC_DC28_VALUE  0x5FB
+#define MC_DC29_VALUE  0x35DF
+#define MC_DC30_VALUE  0x99E9
+#define MC_DC31_VALUE  0x0
+#define MC_DC32_VALUE  0x0
+#define MC_DC33_VALUE  0x0
+#define MC_DC34_VALUE  0x0
+#define MC_DC35_VALUE  0x0
+#define MC_DC36_VALUE  0x0
+#define MC_DC37_VALUE  0x0
+#define MC_DC38_VALUE  0x0
+#define MC_DC39_VALUE  0x0
+#define MC_DC40_VALUE  0x0
+#define MC_DC41_VALUE  0x0
+#define MC_DC42_VALUE  0x0
+#define MC_DC43_VALUE  0x0
+#define MC_DC44_VALUE  0x0
+#define MC_DC45_VALUE  0x600
+//#define MC_DC45_VALUE        0x400
+#define MC_DC46_VALUE  0x0

diff --git a/target/linux/etrax/files/arch/cris/arch-v10/drivers/etraxi2c.h b/target/linux/etrax/files/arch/cris/arch-v10/drivers/etraxi2c.h
index 4235086d5e386217b94a946ee797467ecf86f420..9d5c9bf95177b3e6f759a0c6d5c89369f4f027bb 100644 (file)
--- a/target/linux/etrax/files/arch/cris/arch-v10/drivers/etraxi2c.h
+++ b/target/linux/etrax/files/arch/cris/arch-v10/drivers/etraxi2c.h
@@ -1,49 +1,49 @@
-#ifndef _LINUX_ETRAXI2C_H\r
-#define _LINUX_ETRAXI2C_H\r
-\r
-/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */\r
-\r
-#define ETRAXI2C_IOCTYPE 44\r
-\r
-/* supported ioctl _IOC_NR's */\r
-\r
-/* in write operations, the argument contains both i2c\r
- * slave, register and value.\r
- */\r
-\r
-#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value))\r
-#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8))\r
-\r
-#define I2C_ARGSLAVE(arg) ((arg) >> 16)\r
-#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff)\r
-#define I2C_ARGVALUE(arg) ((arg) & 0xff)\r
-\r
-#define I2C_WRITEREG    0x1   /* write to an I2C register */\r
-#define I2C_READREG     0x2   /* read from an I2C register */\r
-\r
-/*\r
-EXAMPLE usage:\r
-\r
-    i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);\r
-    ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg);\r
-\r
-    i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);\r
-    val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);\r
-\r
-*/\r
-\r
-/* Extended part */\r
-#define I2C_READ        0x4     /* reads from I2C device */\r
-#define I2C_WRITE       0x3     /* writes to I2C device */\r
-#define I2C_WRITEREAD   0x5        /* writes to I2C device where to start reading */\r
-\r
-typedef struct _I2C_DATA \r
-{\r
-    unsigned char slave;        /* I2C address (8-bit representation) of slave device */\r
-    unsigned char wbuf[256];    /* Write buffer (length = 256 bytes) */\r
-       unsigned int  wlen;         /* Number of bytes to write from wbuf[] */   \r
-       unsigned char rbuf[256];    /* Read buffer (length = 256 bytes) */\r
-    unsigned int  rlen;         /* Number of bytes to read into rbuf[] */\r
-} I2C_DATA;\r
-\r
-#endif\r
+#ifndef _LINUX_ETRAXI2C_H
+#define _LINUX_ETRAXI2C_H
+
+/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */
+
+#define ETRAXI2C_IOCTYPE 44
+
+/* supported ioctl _IOC_NR's */
+
+/* in write operations, the argument contains both i2c
+ * slave, register and value.
+ */
+
+#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value))
+#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8))
+
+#define I2C_ARGSLAVE(arg) ((arg) >> 16)
+#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff)
+#define I2C_ARGVALUE(arg) ((arg) & 0xff)
+
+#define I2C_WRITEREG    0x1   /* write to an I2C register */
+#define I2C_READREG     0x2   /* read from an I2C register */
+
+/*
+EXAMPLE usage:
+
+    i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);
+    ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg);
+
+    i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);
+    val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);
+
+*/
+
+/* Extended part */
+#define I2C_READ        0x4     /* reads from I2C device */
+#define I2C_WRITE       0x3     /* writes to I2C device */
+#define I2C_WRITEREAD   0x5        /* writes to I2C device where to start reading */
+
+typedef struct _I2C_DATA 
+{
+    unsigned char slave;        /* I2C address (8-bit representation) of slave device */
+    unsigned char wbuf[256];    /* Write buffer (length = 256 bytes) */
+       unsigned int  wlen;         /* Number of bytes to write from wbuf[] */   
+       unsigned char rbuf[256];    /* Read buffer (length = 256 bytes) */
+    unsigned int  rlen;         /* Number of bytes to read into rbuf[] */
+} I2C_DATA;
+
+#endif

diff --git a/target/linux/etrax/files/arch/cris/arch-v10/drivers/i2c_errno.h b/target/linux/etrax/files/arch/cris/arch-v10/drivers/i2c_errno.h
index 7de4ad62c09a527b6a996a959f55225c99d1b0b8..ddd99b0e5b857dfc64e2db298a8889426a1c8460 100644 (file)
--- a/target/linux/etrax/files/arch/cris/arch-v10/drivers/i2c_errno.h
+++ b/target/linux/etrax/files/arch/cris/arch-v10/drivers/i2c_errno.h
@@ -1,20 +1,20 @@
-#ifndef _I2C_ERRNO_H\r
-#define _I2C_ERRNO_H\r
-\r
-#define EI2CNOERRORS  0     /* All fine */\r
-#define EI2CBUSNFREE  1     /* I2C bus not free */\r
-#define EI2CWADDRESS  2     /* Address write failed */\r
-#define EI2CRADDRESS  3     /* Address read failed */\r
-#define EI2CSENDDATA  4     /* Sending data failed */\r
-#define EI2CRECVDATA  5     /* Receiving data failed */\r
-#define EI2CSTRTCOND  6     /* Start condition failed */\r
-#define EI2CRSTACOND  7     /* Repeated start condition failed */\r
-#define EI2CSTOPCOND  8     /* Stop condition failed */\r
-#define EI2CNOSNDBYT  9     /* Number of send bytes is 0, while there's a send buffer defined */ \r
-#define EI2CNOSNDBUF  10    /* No send buffer defined, while number of send bytes is not 0 */\r
-#define EI2CNORCVBYT  11    /* Number of receive bytes is 0, while there's a receive buffer defined */\r
-#define EI2CNORCVBUF  12    /* No receive buffer defined, while number of receive bytes is not 0 */\r
-#define EI2CNOACKNLD  13    /* No acknowledge received from slave */\r
-#define EI2CNOMNUMBR  14    /* No MAJOR number received from kernel while registering the device */\r
-\r
-#endif /* _I2C_ERRNO_H */\r
+#ifndef _I2C_ERRNO_H
+#define _I2C_ERRNO_H
+
+#define EI2CNOERRORS  0     /* All fine */
+#define EI2CBUSNFREE  1     /* I2C bus not free */
+#define EI2CWADDRESS  2     /* Address write failed */
+#define EI2CRADDRESS  3     /* Address read failed */
+#define EI2CSENDDATA  4     /* Sending data failed */
+#define EI2CRECVDATA  5     /* Receiving data failed */
+#define EI2CSTRTCOND  6     /* Start condition failed */
+#define EI2CRSTACOND  7     /* Repeated start condition failed */
+#define EI2CSTOPCOND  8     /* Stop condition failed */
+#define EI2CNOSNDBYT  9     /* Number of send bytes is 0, while there's a send buffer defined */ 
+#define EI2CNOSNDBUF  10    /* No send buffer defined, while number of send bytes is not 0 */
+#define EI2CNORCVBYT  11    /* Number of receive bytes is 0, while there's a receive buffer defined */
+#define EI2CNORCVBUF  12    /* No receive buffer defined, while number of receive bytes is not 0 */
+#define EI2CNOACKNLD  13    /* No acknowledge received from slave */
+#define EI2CNOMNUMBR  14    /* No MAJOR number received from kernel while registering the device */
+
+#endif /* _I2C_ERRNO_H */

diff --git a/target/linux/etrax/files/arch/cris/arch-v10/drivers/i2c_gvc.h b/target/linux/etrax/files/arch/cris/arch-v10/drivers/i2c_gvc.h
index e4d4d2c7fe844142dc4e9539b5ff74cd172e320e..cac2d4689bcd9539c269b5c21583a8757f898a4e 100644 (file)
--- a/target/linux/etrax/files/arch/cris/arch-v10/drivers/i2c_gvc.h
+++ b/target/linux/etrax/files/arch/cris/arch-v10/drivers/i2c_gvc.h
@@ -1,30 +1,30 @@
-#ifndef _I2C_H\r
-#define _I2C_H\r
-\r
-int i2c_init(void);\r
-\r
-/* High level I2C actions */\r
-int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);\r
-unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg);\r
-\r
-/* Low level I2C */\r
-int i2c_start(void);\r
-int i2c_stop(void);\r
-int i2c_outbyte(unsigned char x);\r
-unsigned char i2c_inbyte(void);\r
-int i2c_getack(void);\r
-void i2c_sendack(void);\r
-void i2c_sendnack(void);\r
-\r
-/**GVC**/\r
-/* New low level I2C functions */\r
-int i2c_read( unsigned char slave, unsigned char* rbuf, unsigned char rlen );\r
-int i2c_write( unsigned char slave, unsigned char* wbuf, unsigned char wlen );\r
-int i2c_writeread( unsigned char  slave\r
-                 , unsigned char* wbuf\r
-                 , unsigned char  wlen\r
-                 , unsigned char* rbuf\r
-                 , unsigned char  rlen\r
-                 );\r
-/**END GVC**/\r
-#endif /* _I2C_H */\r
+#ifndef _I2C_H
+#define _I2C_H
+
+int i2c_init(void);
+
+/* High level I2C actions */
+int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);
+unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg);
+
+/* Low level I2C */
+int i2c_start(void);
+int i2c_stop(void);
+int i2c_outbyte(unsigned char x);
+unsigned char i2c_inbyte(void);
+int i2c_getack(void);
+void i2c_sendack(void);
+void i2c_sendnack(void);
+
+/**GVC**/
+/* New low level I2C functions */
+int i2c_read( unsigned char slave, unsigned char* rbuf, unsigned char rlen );
+int i2c_write( unsigned char slave, unsigned char* wbuf, unsigned char wlen );
+int i2c_writeread( unsigned char  slave
+                 , unsigned char* wbuf
+                 , unsigned char  wlen
+                 , unsigned char* rbuf
+                 , unsigned char  rlen
+                 );
+/**END GVC**/
+#endif /* _I2C_H */

diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile
index 9b41329852ff5d2fd4dce6aefd0f87f2b0f6d735..90f36e63c4c2a7985720d8a74d347345d250d349 100644 (file)
--- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile
+++ b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile
@@ -1,42 +1,42 @@
-#\r
-# linux/arch/mips/boot/compressed/Makefile\r
-#\r
-# create a compressed zImage from the original vmlinux\r
-#\r
-\r
-targets                := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o\r
-\r
-OBJS           := $(obj)/head.o $(obj)/misc.o\r
-\r
-LD_ARGS        := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic\r
-OBJCOPY_ARGS   := -O elf32-tradlittlemips\r
-\r
-ENTRY          := $(obj)/../tools/entry\r
-FILESIZE       := $(obj)/../tools/filesize\r
-\r
-drop-sections  = .reginfo .mdebug .comment .note .pdr .options .MIPS.options\r
-strip-flags    = $(addprefix --remove-section=,$(drop-sections))\r
-\r
-\r
-$(obj)/vmlinux.bin.gz: vmlinux\r
-       rm -f $(obj)/vmlinux.bin.gz\r
-       $(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin\r
-       gzip -v9f $(obj)/vmlinux.bin\r
-\r
-$(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux\r
-       $(CC) $(KBUILD_AFLAGS) \\r
-       -DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \\r
-       -DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \\r
-       -DLOADADDR=$(loadaddr) \\r
-       -c -o $(obj)/head.o $<\r
-\r
-$(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o\r
-       $(OBJCOPY) \\r
-               --add-section=.image=$(obj)/vmlinux.bin.gz \\r
-               --set-section-flags=.image=contents,alloc,load,readonly,data \\r
-               $(obj)/dummy.o $(obj)/piggy.o\r
-       $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o\r
-       $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap\r
-\r
-zImage: $(obj)/vmlinuz\r
-       $(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage       \r
+#
+# linux/arch/mips/boot/compressed/Makefile
+#
+# create a compressed zImage from the original vmlinux
+#
+
+targets                := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o
+
+OBJS           := $(obj)/head.o $(obj)/misc.o
+
+LD_ARGS        := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic
+OBJCOPY_ARGS   := -O elf32-tradlittlemips
+
+ENTRY          := $(obj)/../tools/entry
+FILESIZE       := $(obj)/../tools/filesize
+
+drop-sections  = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
+strip-flags    = $(addprefix --remove-section=,$(drop-sections))
+
+
+$(obj)/vmlinux.bin.gz: vmlinux
+       rm -f $(obj)/vmlinux.bin.gz
+       $(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin
+       gzip -v9f $(obj)/vmlinux.bin
+
+$(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux
+       $(CC) $(KBUILD_AFLAGS) \
+       -DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \
+       -DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \
+       -DLOADADDR=$(loadaddr) \
+       -c -o $(obj)/head.o $<
+
+$(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o
+       $(OBJCOPY) \
+               --add-section=.image=$(obj)/vmlinux.bin.gz \
+               --set-section-flags=.image=contents,alloc,load,readonly,data \
+               $(obj)/dummy.o $(obj)/piggy.o
+       $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o
+       $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap
+
+zImage: $(obj)/vmlinuz
+       $(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage       

diff --git a/tools/firmware-utils/src/nand_ecc.c b/tools/firmware-utils/src/nand_ecc.c
index e270480d7396a8d919602e8fd1894822897045fb..b1e9305158c21b962d471a6a3e36a8ae3601e524 100644 (file)
--- a/tools/firmware-utils/src/nand_ecc.c
+++ b/tools/firmware-utils/src/nand_ecc.c
@@ -1,204 +1,204 @@
-/*\r
- * calculate ecc code for nand flash\r
- *\r
- * Copyright (C) 2008 yajin <yajin@vm-kernel.org>\r
- * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>\r
- *\r
- * This program is free software; you can redistribute it and/or\r
- * modify it under the terms of the GNU General Public License as\r
- * published by the Free Software Foundation; either version 2 or\r
- * (at your option) version 3 of the License.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
- * MA 02111-1307 USA\r
- */\r
-\r
-\r
-#include <sys/types.h>\r
-#include <sys/stat.h>\r
-#include <unistd.h>\r
-#include <stdlib.h>\r
-#include <stdint.h>\r
-#include <fcntl.h>\r
-#include <stdio.h>\r
-\r
-#define DEF_NAND_PAGE_SIZE   2048\r
-#define DEF_NAND_OOB_SIZE     64\r
-#define DEF_NAND_ECC_OFFSET   0x28\r
-\r
-static int page_size = DEF_NAND_PAGE_SIZE;\r
-static int oob_size = DEF_NAND_OOB_SIZE;\r
-static int ecc_offset = DEF_NAND_ECC_OFFSET;\r
-\r
-/*\r
- * Pre-calculated 256-way 1 byte column parity\r
- */\r
-static const uint8_t nand_ecc_precalc_table[] = {\r
-       0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,\r
-       0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,\r
-       0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,\r
-       0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,\r
-       0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,\r
-       0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,\r
-       0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,\r
-       0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,\r
-       0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,\r
-       0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,\r
-       0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,\r
-       0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,\r
-       0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,\r
-       0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,\r
-       0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,\r
-       0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00\r
-};\r
-\r
-/**\r
- * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256-byte block\r
- * @dat:       raw data\r
- * @ecc_code:  buffer for ECC\r
- */\r
-int nand_calculate_ecc(const uint8_t *dat,\r
-                      uint8_t *ecc_code)\r
-{\r
-       uint8_t idx, reg1, reg2, reg3, tmp1, tmp2;\r
-       int i;\r
-\r
-       /* Initialize variables */\r
-       reg1 = reg2 = reg3 = 0;\r
-\r
-       /* Build up column parity */\r
-       for(i = 0; i < 256; i++) {\r
-               /* Get CP0 - CP5 from table */\r
-               idx = nand_ecc_precalc_table[*dat++];\r
-               reg1 ^= (idx & 0x3f);\r
-\r
-               /* All bit XOR = 1 ? */\r
-               if (idx & 0x40) {\r
-                       reg3 ^= (uint8_t) i;\r
-                       reg2 ^= ~((uint8_t) i);\r
-               }\r
-       }\r
-\r
-       /* Create non-inverted ECC code from line parity */\r
-       tmp1  = (reg3 & 0x80) >> 0; /* B7 -> B7 */\r
-       tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */\r
-       tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */\r
-       tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */\r
-       tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */\r
-       tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */\r
-       tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */\r
-       tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */\r
-\r
-       tmp2  = (reg3 & 0x08) << 4; /* B3 -> B7 */\r
-       tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */\r
-       tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */\r
-       tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */\r
-       tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */\r
-       tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */\r
-       tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */\r
-       tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */\r
-\r
-       /* Calculate final ECC code */\r
-#ifdef CONFIG_MTD_NAND_ECC_SMC\r
-       ecc_code[0] = ~tmp2;\r
-       ecc_code[1] = ~tmp1;\r
-#else\r
-       ecc_code[0] = ~tmp1;\r
-       ecc_code[1] = ~tmp2;\r
-#endif\r
-       ecc_code[2] = ((~reg1) << 2) | 0x03;\r
-\r
-       return 0;\r
-}\r
-\r
-/*\r
- *  usage: bb-nandflash-ecc    start_address  size\r
- */\r
-void usage(const char *prog)\r
-{\r
-       fprintf(stderr, "Usage: %s [options] <input> <output>\n"\r
-               "Options:\n"\r
-               "    -p <pagesize>      NAND page size (default: %d)\n"\r
-               "    -o <oobsize>       NAND OOB size (default: %d)\n"\r
-               "    -e <offset>        NAND ECC offset (default: %d)\n"\r
-               "\n", prog, DEF_NAND_PAGE_SIZE, DEF_NAND_OOB_SIZE,\r
-               DEF_NAND_ECC_OFFSET);\r
-       exit(1);\r
-}\r
-\r
-/*start_address/size does not include oob\r
-  */\r
-int main(int argc, char **argv)\r
-{\r
-       uint8_t *page_data = NULL;\r
-       uint8_t *ecc_data;\r
-       int infd = -1, outfd = -1;\r
-       int ret = 1;\r
-       ssize_t bytes;\r
-       int ch;\r
-\r
-       while ((ch = getopt(argc, argv, "e:o:p:")) != -1) {\r
-               switch(ch) {\r
-               case 'p':\r
-                       page_size = strtoul(optarg, NULL, 0);\r
-                       break;\r
-               case 'o':\r
-                       oob_size = strtoul(optarg, NULL, 0);\r
-                       break;\r
-               case 'e':\r
-                       ecc_offset = strtoul(optarg, NULL, 0);\r
-                       break;\r
-               default:\r
-                       usage(argv[0]);\r
-               }\r
-       }\r
-       argc -= optind;\r
-       if (argc < 2)\r
-               usage(argv[0]);\r
-\r
-       argv += optind;\r
-\r
-       infd = open(argv[0], O_RDONLY, 0);\r
-       if (infd < 0) {\r
-               perror("open input file");\r
-               goto out;\r
-       }\r
-\r
-       outfd = open(argv[1], O_WRONLY|O_CREAT|O_TRUNC, 0644);\r
-       if (outfd < 0) {\r
-               perror("open output file");\r
-               goto out;\r
-       }\r
-\r
-       page_data = malloc(page_size + oob_size);\r
-\r
-       while ((bytes = read(infd, page_data, page_size)) == page_size) {\r
-               int j;\r
-\r
-               ecc_data = page_data + page_size + ecc_offset;\r
-               for (j = 0; j < page_size / 256; j++)\r
-               {\r
-                       nand_calculate_ecc(page_data + j * 256, ecc_data);\r
-                       ecc_data += 3;\r
-               }\r
-               write(outfd, page_data, page_size + oob_size);\r
-       }\r
-\r
-       ret = 0;\r
-out:\r
-       if (infd >= 0)\r
-               close(infd);\r
-       if (outfd >= 0)\r
-               close(outfd);\r
-       if (page_data)\r
-               free(page_data);\r
-       return ret;\r
-}\r
-\r
+/*
+ * calculate ecc code for nand flash
+ *
+ * Copyright (C) 2008 yajin <yajin@vm-kernel.org>
+ * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <fcntl.h>
+#include <stdio.h>
+
+#define DEF_NAND_PAGE_SIZE   2048
+#define DEF_NAND_OOB_SIZE     64
+#define DEF_NAND_ECC_OFFSET   0x28
+
+static int page_size = DEF_NAND_PAGE_SIZE;
+static int oob_size = DEF_NAND_OOB_SIZE;
+static int ecc_offset = DEF_NAND_ECC_OFFSET;
+
+/*
+ * Pre-calculated 256-way 1 byte column parity
+ */
+static const uint8_t nand_ecc_precalc_table[] = {
+       0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
+       0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
+       0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
+       0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
+       0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
+       0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
+       0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
+       0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
+       0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
+       0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
+       0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
+       0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
+       0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
+       0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
+       0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
+       0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
+};
+
+/**
+ * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256-byte block
+ * @dat:       raw data
+ * @ecc_code:  buffer for ECC
+ */
+int nand_calculate_ecc(const uint8_t *dat,
+                      uint8_t *ecc_code)
+{
+       uint8_t idx, reg1, reg2, reg3, tmp1, tmp2;
+       int i;
+
+       /* Initialize variables */
+       reg1 = reg2 = reg3 = 0;
+
+       /* Build up column parity */
+       for(i = 0; i < 256; i++) {
+               /* Get CP0 - CP5 from table */
+               idx = nand_ecc_precalc_table[*dat++];
+               reg1 ^= (idx & 0x3f);
+
+               /* All bit XOR = 1 ? */
+               if (idx & 0x40) {
+                       reg3 ^= (uint8_t) i;
+                       reg2 ^= ~((uint8_t) i);
+               }
+       }
+
+       /* Create non-inverted ECC code from line parity */
+       tmp1  = (reg3 & 0x80) >> 0; /* B7 -> B7 */
+       tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */
+       tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */
+       tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */
+       tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */
+       tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */
+       tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */
+       tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */
+
+       tmp2  = (reg3 & 0x08) << 4; /* B3 -> B7 */
+       tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */
+       tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */
+       tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */
+       tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */
+       tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */
+       tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */
+       tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */
+
+       /* Calculate final ECC code */
+#ifdef CONFIG_MTD_NAND_ECC_SMC
+       ecc_code[0] = ~tmp2;
+       ecc_code[1] = ~tmp1;
+#else
+       ecc_code[0] = ~tmp1;
+       ecc_code[1] = ~tmp2;
+#endif
+       ecc_code[2] = ((~reg1) << 2) | 0x03;
+
+       return 0;
+}
+
+/*
+ *  usage: bb-nandflash-ecc    start_address  size
+ */
+void usage(const char *prog)
+{
+       fprintf(stderr, "Usage: %s [options] <input> <output>\n"
+               "Options:\n"
+               "    -p <pagesize>      NAND page size (default: %d)\n"
+               "    -o <oobsize>       NAND OOB size (default: %d)\n"
+               "    -e <offset>        NAND ECC offset (default: %d)\n"
+               "\n", prog, DEF_NAND_PAGE_SIZE, DEF_NAND_OOB_SIZE,
+               DEF_NAND_ECC_OFFSET);
+       exit(1);
+}
+
+/*start_address/size does not include oob
+  */
+int main(int argc, char **argv)
+{
+       uint8_t *page_data = NULL;
+       uint8_t *ecc_data;
+       int infd = -1, outfd = -1;
+       int ret = 1;
+       ssize_t bytes;
+       int ch;
+
+       while ((ch = getopt(argc, argv, "e:o:p:")) != -1) {
+               switch(ch) {
+               case 'p':
+                       page_size = strtoul(optarg, NULL, 0);
+                       break;
+               case 'o':
+                       oob_size = strtoul(optarg, NULL, 0);
+                       break;
+               case 'e':
+                       ecc_offset = strtoul(optarg, NULL, 0);
+                       break;
+               default:
+                       usage(argv[0]);
+               }
+       }
+       argc -= optind;
+       if (argc < 2)
+               usage(argv[0]);
+
+       argv += optind;
+
+       infd = open(argv[0], O_RDONLY, 0);
+       if (infd < 0) {
+               perror("open input file");
+               goto out;
+       }
+
+       outfd = open(argv[1], O_WRONLY|O_CREAT|O_TRUNC, 0644);
+       if (outfd < 0) {
+               perror("open output file");
+               goto out;
+       }
+
+       page_data = malloc(page_size + oob_size);
+
+       while ((bytes = read(infd, page_data, page_size)) == page_size) {
+               int j;
+
+               ecc_data = page_data + page_size + ecc_offset;
+               for (j = 0; j < page_size / 256; j++)
+               {
+                       nand_calculate_ecc(page_data + j * 256, ecc_data);
+                       ecc_data += 3;
+               }
+               write(outfd, page_data, page_size + oob_size);
+       }
+
+       ret = 0;
+out:
+       if (infd >= 0)
+               close(infd);
+       if (outfd >= 0)
+               close(outfd);
+       if (page_data)
+               free(page_data);
+       return ret;
+}
+