ramips: backport batch fixing illegal instruction when booting secodnary CPUs in...

Signed-off-by: Nikolay Martynov <mar.kolya@gmail.com>
SVN-Revision: 47837

diff --git a/target/linux/ramips/patches-4.3/0055-MIPS-CPS-drop-.set-mips64r2-directives.patch b/target/linux/ramips/patches-4.3/0055-MIPS-CPS-drop-.set-mips64r2-directives.patch
new file mode 100644 (file)
index 0000000..049efb9
--- /dev/null
+++ b/target/linux/ramips/patches-4.3/0055-MIPS-CPS-drop-.set-mips64r2-directives.patch
@@ -0,0 +1,53 @@
+From patchwork Wed Aug  5 22:42:40 2015
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: [6/6] MIPS: CPS: drop .set mips64r2 directives
+From: Paul Burton <paul.burton@imgtec.com>
+X-Patchwork-Id: 10869
+Message-Id: <1438814560-19821-7-git-send-email-paul.burton@imgtec.com>
+To: <linux-mips@linux-mips.org>
+Cc: Paul Burton <paul.burton@imgtec.com>,
+ Markos Chandras <markos.chandras@imgtec.com>,
+ <stable@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
+ James Hogan <james.hogan@imgtec.com>, "Ralf Baechle" <ralf@linux-mips.org>
+Date: Wed, 5 Aug 2015 15:42:40 -0700
+
+Commit 977e043d5ea1 ("MIPS: kernel: cps-vec: Replace mips32r2 ISA level
+with mips64r2") leads to .set mips64r2 directives being present in 32
+bit (ie. CONFIG_32BIT=y) kernels. This is incorrect & leads to MIPS64
+instructions being emitted by the assembler when expanding
+pseudo-instructions. For example the "move" instruction can legitimately
+be expanded to a "daddu". This causes problems when the kernel is run on
+a MIPS32 CPU, as CONFIG_32BIT kernels of course often are...
+
+Fix this by dropping the .set <ISA> directives entirely now that Kconfig
+should be ensuring that kernels including this code are built with a
+suitable -march= compiler flag.
+
+Signed-off-by: Paul Burton <paul.burton@imgtec.com>
+Cc: Markos Chandras <markos.chandras@imgtec.com>
+Cc: <stable@vger.kernel.org> # 3.16+
+---
+
+ arch/mips/kernel/cps-vec.S | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/arch/mips/kernel/cps-vec.S
++++ b/arch/mips/kernel/cps-vec.S
+@@ -229,7 +229,6 @@ LEAF(mips_cps_core_init)
+       has_mt  t0, 3f
+ 
+       .set    push
+-      .set    mips64r2
+       .set    mt
+ 
+       /* Only allow 1 TC per VPE to execute... */
+@@ -348,7 +347,6 @@ LEAF(mips_cps_boot_vpes)
+        nop
+ 
+       .set    push
+-      .set    mips64r2
+       .set    mt
+ 
+ 1:    /* Enter VPE configuration state */