[ar71xx] fix ar71xx_device_{start,stop} functions on the AR7240 SoC
authorGabor Juhos <juhosg@openwrt.org>
Wed, 1 Jul 2009 19:41:00 +0000 (19:41 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Wed, 1 Jul 2009 19:41:00 +0000 (19:41 +0000)
SVN-Revision: 16648

target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

index a13c928125951e59db4204a2b04c50adea821018..30d08c051a251e5565077ac5c807fda604f4765f 100644 (file)
@@ -48,6 +48,13 @@ void ar71xx_device_stop(u32 mask)
                local_irq_restore(flags);
                break;
 
                local_irq_restore(flags);
                break;
 
+       case AR71XX_SOC_AR7240:
+               local_irq_save(flags);
+               t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
+               ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t | mask);
+               local_irq_restore(flags);
+               break;
+
        case AR71XX_SOC_AR9130:
        case AR71XX_SOC_AR9132:
                local_irq_save(flags);
        case AR71XX_SOC_AR9130:
        case AR71XX_SOC_AR9132:
                local_irq_save(flags);
@@ -77,6 +84,13 @@ void ar71xx_device_start(u32 mask)
                local_irq_restore(flags);
                break;
 
                local_irq_restore(flags);
                break;
 
+       case AR71XX_SOC_AR7240:
+               local_irq_save(flags);
+               t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
+               ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t & ~mask);
+               local_irq_restore(flags);
+               break;
+
        case AR71XX_SOC_AR9130:
        case AR71XX_SOC_AR9132:
                local_irq_save(flags);
        case AR71XX_SOC_AR9130:
        case AR71XX_SOC_AR9132:
                local_irq_save(flags);
index 14e5fe3ddad34491c2997827a77b13c0035b1b1b..0fc0d2066457b884afa0c3beba02c85c87edbe48 100644 (file)
@@ -362,6 +362,8 @@ void ar71xx_ddr_flush(u32 reg);
 #define AR91XX_RESET_REG_PERFC0                        0x24
 #define AR91XX_RESET_REG_PERFC1                        0x28
 
 #define AR91XX_RESET_REG_PERFC0                        0x24
 #define AR91XX_RESET_REG_PERFC1                        0x28
 
+#define AR724X_RESET_REG_RESET_MODULE          0x1c
+
 #define WDOG_CTRL_LAST_RESET           BIT(31)
 #define WDOG_CTRL_ACTION_MASK          3
 #define WDOG_CTRL_ACTION_NONE          0       /* no action */
 #define WDOG_CTRL_LAST_RESET           BIT(31)
 #define WDOG_CTRL_ACTION_MASK          3
 #define WDOG_CTRL_ACTION_NONE          0       /* no action */