sync ath9k with latest git code
authorImre Kaloz <kaloz@openwrt.org>
Thu, 31 Jul 2008 09:51:31 +0000 (09:51 +0000)
committerImre Kaloz <kaloz@openwrt.org>
Thu, 31 Jul 2008 09:51:31 +0000 (09:51 +0000)
SVN-Revision: 12038

15 files changed:
package/ath9k/Makefile
package/ath9k/src/drivers/net/wireless/ath9k/ath9k.h
package/ath9k/src/drivers/net/wireless/ath9k/beacon.c
package/ath9k/src/drivers/net/wireless/ath9k/core.c
package/ath9k/src/drivers/net/wireless/ath9k/core.h
package/ath9k/src/drivers/net/wireless/ath9k/hw.c
package/ath9k/src/drivers/net/wireless/ath9k/hw.h
package/ath9k/src/drivers/net/wireless/ath9k/main.c
package/ath9k/src/drivers/net/wireless/ath9k/phy.c
package/ath9k/src/drivers/net/wireless/ath9k/phy.h
package/ath9k/src/drivers/net/wireless/ath9k/rc.c
package/ath9k/src/drivers/net/wireless/ath9k/recv.c
package/ath9k/src/drivers/net/wireless/ath9k/regd.c
package/ath9k/src/drivers/net/wireless/ath9k/regd.h
package/ath9k/src/drivers/net/wireless/ath9k/xmit.c

index b4ddc6d..88ffa42 100644 (file)
@@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=ath9k
-PKG_VERSION:=20080722
+PKG_VERSION:=20080731
 PKG_RELEASE:=1
 
 include $(INCLUDE_DIR)/package.mk
index ed440a0..c3294c0 100644 (file)
 #define        AR_SUBVENDOR_ID_NOG     0x0e11
 #define AR_SUBVENDOR_ID_NEW_A  0x7065
 
-#define        HAL_TXERR_XRETRY        0x01
-#define        HAL_TXERR_FILT          0x02
-#define        HAL_TXERR_FIFO          0x04
-#define HAL_TXERR_XTXOP                0x08
-#define HAL_TXERR_TIMER_EXPIRED 0x10
-
-#define HAL_TX_BA               0x01
-#define HAL_TX_PWRMGMT          0x02
-#define HAL_TX_DESC_CFG_ERR     0x04
-#define HAL_TX_DATA_UNDERRUN    0x08
-#define HAL_TX_DELIM_UNDERRUN   0x10
-#define HAL_TX_SW_ABORTED       0x40
-#define HAL_TX_SW_FILTERED      0x80
+#define ATH9K_TXERR_XRETRY         0x01
+#define ATH9K_TXERR_FILT           0x02
+#define ATH9K_TXERR_FIFO           0x04
+#define ATH9K_TXERR_XTXOP          0x08
+#define ATH9K_TXERR_TIMER_EXPIRED  0x10
+
+#define ATH9K_TX_BA                0x01
+#define ATH9K_TX_PWRMGMT           0x02
+#define ATH9K_TX_DESC_CFG_ERR      0x04
+#define ATH9K_TX_DATA_UNDERRUN     0x08
+#define ATH9K_TX_DELIM_UNDERRUN    0x10
+#define ATH9K_TX_SW_ABORTED        0x40
+#define ATH9K_TX_SW_FILTERED       0x80
 
 #define NBBY    8
 #ifndef howmany
@@ -102,24 +102,19 @@ struct ath_rx_status {
        u_int32_t evm2;
 };
 
-#define        HAL_RXERR_CRC           0x01
-#define        HAL_RXERR_PHY           0x02
-#define        HAL_RXERR_FIFO          0x04
-#define        HAL_RXERR_DECRYPT       0x08
-#define        HAL_RXERR_MIC           0x10
-
-#define HAL_RX_MORE             0x01
-#define HAL_RX_MORE_AGGR        0x02
-#define HAL_RX_GI               0x04
-#define HAL_RX_2040             0x08
-#define HAL_RX_DELIM_CRC_PRE    0x10
-#define HAL_RX_DELIM_CRC_POST   0x20
-#define HAL_RX_DECRYPT_BUSY     0x40
-
-enum hal_bool {
-       AH_FALSE = 0,
-       AH_TRUE = 1,
-};
+#define ATH9K_RXERR_CRC           0x01
+#define ATH9K_RXERR_PHY           0x02
+#define ATH9K_RXERR_FIFO          0x04
+#define ATH9K_RXERR_DECRYPT       0x08
+#define ATH9K_RXERR_MIC           0x10
+
+#define ATH9K_RX_MORE             0x01
+#define ATH9K_RX_MORE_AGGR        0x02
+#define ATH9K_RX_GI               0x04
+#define ATH9K_RX_2040             0x08
+#define ATH9K_RX_DELIM_CRC_PRE    0x10
+#define ATH9K_RX_DELIM_CRC_POST   0x20
+#define ATH9K_RX_DECRYPT_BUSY     0x40
 
 #define        HAL_RXKEYIX_INVALID     ((u_int8_t)-1)
 #define        HAL_TXKEYIX_INVALID     ((u_int)-1)
@@ -243,7 +238,6 @@ struct hal_ops_config {
        u_int16_t ath_hal_antennaSwitchSwap;
        int ath_hal_serializeRegMode;
        int ath_hal_intrMitigation;
-       int ath_hal_debug;
 #define SPUR_DISABLE           0
 #define SPUR_ENABLE_IOCTL      1
 #define SPUR_ENABLE_EEPROM     2
@@ -482,11 +476,11 @@ struct hal_channel_internal {
        int8_t maxRegTxPower;
        int8_t maxTxPower;
        int8_t minTxPower;
-       enum hal_bool bssSendHere;
+       bool bssSendHere;
        u_int8_t gainI;
-       enum hal_bool iqCalValid;
+       bool iqCalValid;
        int32_t CalValid;
-       enum hal_bool oneTimeCalsDone;
+       bool oneTimeCalsDone;
        int8_t iCoff;
        int8_t qCoff;
        int16_t rawNoiseFloor;
@@ -623,49 +617,20 @@ struct hal_country_entry {
        u_int8_t iso[3];
 };
 
-#define HAL_DBG_RESET           0x00000001
-#define HAL_DBG_PHY_IO          0x00000002
-#define HAL_DBG_REG_IO          0x00000004
-#define HAL_DBG_RF_PARAM        0x00000008
-#define HAL_DBG_QUEUE           0x00000010
-#define HAL_DBG_EEPROM_DUMP     0x00000020
-#define HAL_DBG_EEPROM          0x00000040
-#define HAL_DBG_NF_CAL          0x00000080
-#define HAL_DBG_CALIBRATE       0x00000100
-#define HAL_DBG_CHANNEL         0x00000200
-#define HAL_DBG_INTERRUPT       0x00000400
-#define HAL_DBG_DFS             0x00000800
-#define HAL_DBG_DMA             0x00001000
-#define HAL_DBG_REGULATORY      0x00002000
-#define HAL_DBG_TX              0x00004000
-#define HAL_DBG_TXDESC          0x00008000
-#define HAL_DBG_RX              0x00010000
-#define HAL_DBG_RXDESC          0x00020000
-#define HAL_DBG_ANI             0x00040000
-#define HAL_DBG_BEACON          0x00080000
-#define HAL_DBG_KEYCACHE        0x00100000
-#define HAL_DBG_POWER_MGMT      0x00200000
-#define HAL_DBG_MALLOC         0x00400000
-#define HAL_DBG_POWER_OVERRIDE 0x01000000
-#define HAL_DBG_SPUR_MITIGATE  0x02000000
-#define HAL_DBG_UNMASKABLE      0xFFFFFFFF
-
 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
 
 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
-#define OS_REG_RMW(_a, _r, _set, _clr)    \
+#define REG_RMW(_a, _r, _set, _clr)    \
        REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
-#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
+#define REG_RMW_FIELD(_a, _r, _f, _v) \
        REG_WRITE(_a, _r, \
        (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
-#define OS_REG_SET_BIT(_a, _r, _f) \
+#define REG_SET_BIT(_a, _r, _f) \
        REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
-#define OS_REG_CLR_BIT(_a, _r, _f) \
+#define REG_CLR_BIT(_a, _r, _f) \
        REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
-#define OS_REG_ath9k_regd_is_bit_set(_a, _r, _f) \
-       ((REG_READ(_a, _r) & _f) != 0)
 
 #define HAL_COMP_BUF_MAX_SIZE   9216
 #define HAL_COMP_BUF_ALIGN_SIZE 512
@@ -913,7 +878,7 @@ struct ath_hal {
        u_int32_t ah_magic;
        u_int16_t ah_devid;
        u_int16_t ah_subvendorid;
-       void *ah_sc;
+       struct ath_softc *ah_sc;
        void __iomem *ah_sh;
        u_int16_t ah_countryCode;
        u_int32_t ah_macVersion;
@@ -936,25 +901,19 @@ struct ath_hal {
        u_int16_t ah_currentRD2G;
        char ah_iso[4];
        enum start_adhoc_option ah_adHocMode;
-       enum hal_bool ah_commonMode;
+       bool ah_commonMode;
        struct hal_channel_internal ah_channels[150];
        u_int ah_nchan;
        struct hal_channel_internal *ah_curchan;
        u_int16_t ah_rfsilent;
-       enum hal_bool ah_rfkillEnabled;
-       enum hal_bool ah_isPciExpress;
+       bool ah_rfkillEnabled;
+       bool ah_isPciExpress;
        u_int16_t ah_txTrigLevel;
 #ifndef ATH_NF_PER_CHAN
        struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
 #endif
 };
 
-#define HDPRINTF(_ah, _m, _fmt, ...) do {                              \
-               if (((_ah) == NULL && _m == HAL_DBG_UNMASKABLE) ||      \
-                   (((struct ath_hal *)(_ah))->ah_config.ath_hal_debug & _m)) \
-                       printk(KERN_DEBUG _fmt , ##__VA_ARGS__);        \
-       } while (0)
-
 enum wireless_mode {
        WIRELESS_MODE_11a = 0,
        WIRELESS_MODE_11b = 2,
@@ -999,38 +958,39 @@ enum hal_status ath_hal_getcapability(struct ath_hal *ah,
 const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
                                                   u_int mode);
 void ath9k_hw_detach(struct ath_hal *ah);
-struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
+struct ath_hal *ath9k_hw_attach(u_int16_t devid,
+                               struct ath_softc *sc,
+                               void __iomem *mem,
                                enum hal_status *error);
-enum hal_bool ath9k_regd_init_channels(struct ath_hal *ah,
-                                      struct hal_channel *chans,
-                                      u_int maxchans, u_int *nchans,
-                                      u_int8_t *regclassids,
-                                      u_int maxregids, u_int *nregids,
-                                      u_int16_t cc, u_int32_t modeSelect,
-                                      enum hal_bool enableOutdoor,
-                                      enum hal_bool
-                                      enableExtendedChannels);
+bool ath9k_regd_init_channels(struct ath_hal *ah,
+                             struct hal_channel *chans,
+                             u_int maxchans, u_int *nchans,
+                             u_int8_t *regclassids,
+                             u_int maxregids, u_int *nregids,
+                             u_int16_t cc, u_int32_t modeSelect,
+                             bool enableOutdoor,
+                             bool enableExtendedChannels);
 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
 enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah,
                                     enum hal_int ints);
-enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
-                            struct hal_channel *chan,
-                            enum hal_ht_macmode macmode,
-                            u_int8_t txchainmask, u_int8_t rxchainmask,
-                            enum hal_ht_extprotspacing extprotspacing,
-                            enum hal_bool bChannelChange,
-                            enum hal_status *status);
-enum hal_bool ath9k_hw_phy_disable(struct ath_hal *ah);
+bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
+                   struct hal_channel *chan,
+                   enum hal_ht_macmode macmode,
+                   u_int8_t txchainmask, u_int8_t rxchainmask,
+                   enum hal_ht_extprotspacing extprotspacing,
+                   bool bChannelChange,
+                   enum hal_status *status);
+bool ath9k_hw_phy_disable(struct ath_hal *ah);
 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
-                            enum hal_bool *isCalDone);
+                            bool *isCalDone);
 void ath9k_hw_ani_monitor(struct ath_hal *ah,
                          const struct hal_node_stats *stats,
                          struct hal_channel *chan);
-enum hal_bool ath9k_hw_calibrate(struct ath_hal *ah,
-                                struct hal_channel *chan,
-                                u_int8_t rxchainmask,
-                                enum hal_bool longcal,
-                                enum hal_bool *isCalDone);
+bool ath9k_hw_calibrate(struct ath_hal *ah,
+                       struct hal_channel *chan,
+                       u_int8_t rxchainmask,
+                       bool longcal,
+                       bool *isCalDone);
 int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
                               struct hal_channel *chan);
 void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
@@ -1038,70 +998,65 @@ void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
 void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits);
 void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
                            u_int16_t assocId);
-enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
+bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
 void ath9k_hw_reset_tsf(struct ath_hal *ah);
-enum hal_bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
-enum hal_bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
-                                const u_int8_t *mac);
-enum hal_bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
-                                         u_int16_t entry,
-                                         const struct hal_keyval *k,
-                                         const u_int8_t *mac,
-                                         int xorKey);
-enum hal_bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
-                                    u_int32_t setting);
+bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
+bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
+                       const u_int8_t *mac);
+bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
+                                u_int16_t entry,
+                                const struct hal_keyval *k,
+                                const u_int8_t *mac,
+                                int xorKey);
+bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
+                           u_int32_t setting);
 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
-enum hal_bool ath9k_hw_intrpend(struct ath_hal *ah);
-enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
-enum hal_bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
-                                        enum hal_bool bIncTrigLevel);
+bool ath9k_hw_intrpend(struct ath_hal *ah);
+bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
+bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
+                               bool bIncTrigLevel);
 void ath9k_hw_procmibevent(struct ath_hal *ah,
                           const struct hal_node_stats *stats);
-enum hal_bool ath9k_hw_setrxabort(struct ath_hal *ah, enum hal_bool set);
+bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode);
-enum hal_bool ath9k_hw_setupxtxdesc(struct ath_hal *ah,
-                                   struct ath_desc *ds,
-                                   u_int txRate1, u_int txTries1,
-                                   u_int txRate2, u_int txTries2,
-                                   u_int txRate3, u_int txTries3);
-enum hal_bool ath9k_hw_phycounters(struct ath_hal *ah);
-enum hal_bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
-enum hal_bool ath9k_hw_getcapability(struct ath_hal *ah,
-                                    enum hal_capability_type type,
-                                    u_int32_t capability,
-                                    u_int32_t *result);
-enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
-                                    enum hal_capability_type type,
-                                    u_int32_t capability,
-                                    u_int32_t setting,
-                                    enum hal_status *status);
+bool ath9k_hw_phycounters(struct ath_hal *ah);
+bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
+bool ath9k_hw_getcapability(struct ath_hal *ah,
+                           enum hal_capability_type type,
+                           u_int32_t capability,
+                           u_int32_t *result);
+bool ath9k_hw_setcapability(struct ath_hal *ah,
+                           enum hal_capability_type type,
+                           u_int32_t capability,
+                           u_int32_t setting,
+                           enum hal_status *status);
 u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
 void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac);
 void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask);
-enum hal_bool ath9k_hw_setbssidmask(struct ath_hal *ah,
-                                   const u_int8_t *mask);
-enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
-                               enum hal_power_mode mode);
+bool ath9k_hw_setbssidmask(struct ath_hal *ah,
+                          const u_int8_t *mask);
+bool ath9k_hw_setpower(struct ath_hal *ah,
+                      enum hal_power_mode mode);
 enum hal_int ath9k_hw_intrget(struct ath_hal *ah);
 u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah);
 u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
-enum hal_bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
-enum hal_bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
-                                       enum hal_ant_setting settings,
-                                       struct hal_channel *chan,
-                                       u_int8_t *tx_chainmask,
-                                       u_int8_t *rx_chainmask,
-                                       u_int8_t *antenna_cfgd);
+bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
+bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
+                              enum hal_ant_setting settings,
+                              struct hal_channel *chan,
+                              u_int8_t *tx_chainmask,
+                              u_int8_t *rx_chainmask,
+                              u_int8_t *antenna_cfgd);
 void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna);
 enum hal_status ath9k_hw_select_antconfig(struct ath_hal *ah,
                                          u_int32_t cfg);
-enum hal_bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
-                               u_int32_t txdp);
-enum hal_bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
+bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
+                      u_int32_t txdp);
+bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
 u_int16_t ath9k_hw_computetxtime(struct ath_hal *ah,
                                 const struct hal_rate_table *rates,
                                 u_int32_t frameLen, u_int16_t rateix,
-                                enum hal_bool shortPreamble);
+                                bool shortPreamble);
 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
                                  struct ath_desc *lastds,
                                  u_int durUpdateEn, u_int rtsctsRate,
@@ -1113,25 +1068,25 @@ void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
                                   u_int burstDuration);
 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
 u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n);
-enum hal_bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
+bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
 u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan);
 u_int ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
-       struct hal_channel *chan);
+                                    struct hal_channel *chan);
 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
-enum hal_bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
-       struct hal_txq_info *qInfo);
-enum hal_bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
-                                      const struct hal_txq_info *qInfo);
+bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
+                             struct hal_txq_info *qInfo);
+bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
+                             const struct hal_txq_info *qInfo);
 struct hal_channel_internal *ath9k_regd_check_channel(struct ath_hal *ah,
-       const struct hal_channel *c);
+                                             const struct hal_channel *c);
 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
-       u_int pktLen, enum hal_pkt_type type,
-       u_int txPower, u_int keyIx,
-       enum hal_key_type keyType, u_int flags);
-enum hal_bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
-       u_int segLen, enum hal_bool firstSeg,
-       enum hal_bool lastSeg,
-       const struct ath_desc *ds0);
+                           u_int pktLen, enum hal_pkt_type type,
+                           u_int txPower, u_int keyIx,
+                           enum hal_key_type keyType, u_int flags);
+bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
+                        u_int segLen, bool firstSeg,
+                        bool lastSeg,
+                        const struct ath_desc *ds0);
 u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
                                        u_int32_t *rxc_pcnt,
                                        u_int32_t *rxf_pcnt,
@@ -1141,18 +1096,18 @@ void ath9k_hw_beaconinit(struct ath_hal *ah,
                         u_int32_t next_beacon, u_int32_t beacon_period);
 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
                                    const struct hal_beacon_state *bs);
-enum hal_bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
-                                  u_int32_t size, u_int flags);
+bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
+                         u_int32_t size, u_int flags);
 void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp);
 void ath9k_hw_rxena(struct ath_hal *ah);
 void ath9k_hw_setopmode(struct ath_hal *ah);
-enum hal_bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
+bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
                             u_int32_t filter1);
 u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah);
 void ath9k_hw_startpcureceive(struct ath_hal *ah);
 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
-enum hal_bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
+bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
 enum hal_status ath9k_hw_rxprocdesc(struct ath_hal *ah,
                                    struct ath_desc *ds, u_int32_t pa,
                                    struct ath_desc *nds, u_int64_t tsf);
@@ -1164,26 +1119,26 @@ void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
                                u_int aggrLen);
 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
-enum hal_bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
+bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs);
 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
                                     struct ath_desc *ds, u_int vmf);
-enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
-enum hal_bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
+bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
+bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
                          const struct hal_txq_info *qInfo);
 u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q);
 const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid);
-enum hal_bool ath9k_hw_disable(struct ath_hal *ah);
+bool ath9k_hw_disable(struct ath_hal *ah);
 void ath9k_hw_rfdetach(struct ath_hal *ah);
 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
                                  struct hal_channel_internal *chan,
                                  struct chan_centers *centers);
-enum hal_bool ath9k_get_channel_edges(struct ath_hal *ah,
-                                     u_int16_t flags, u_int16_t *low,
-                                     u_int16_t *high);
-enum hal_bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
-                                            struct hal_channel *chans,
-                                            u_int32_t nchans);
+bool ath9k_get_channel_edges(struct ath_hal *ah,
+                            u_int16_t flags, u_int16_t *low,
+                            u_int16_t *high);
+bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
+                                   struct hal_channel *chans,
+                                   u_int32_t nchans);
 #endif
index 1a23fd1..596591e 100644 (file)
@@ -45,7 +45,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
        }
 
        if (!ath9k_hw_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to update h/w beacon queue parameters\n",
                        __func__);
                return 0;
@@ -76,7 +76,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
        int ctsduration = 0;
        struct hal_11n_rate_series  series[4];
 
-       DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n",
+       DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n",
                __func__, skb, skb->len);
 
        /* setup descriptors */
@@ -84,7 +84,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
 
        flags = HAL_TXDESC_NOACK;
 
-       if (sc->sc_opmode == HAL_M_IBSS && sc->sc_hasveol) {
+       if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport) {
                ds->ds_link = bf->bf_daddr; /* self-linked */
                flags |= HAL_TXDESC_VEOL;
                /* Let hardware handle antenna switching. */
@@ -97,11 +97,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
                 * SWBA's
                 * XXX assumes two antenna
                 */
-               if (sc->sc_stagbeacons)
-                       antenna = ((sc->ast_be_xmit /
-                                       sc->sc_nbcnvaps) & 1 ? 2 : 1);
-               else
-                       antenna = (sc->ast_be_xmit & 1 ? 2 : 1);
+               antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1);
        }
 
        ds->ds_data = bf->bf_buf_addr;
@@ -128,8 +124,8 @@ static void ath_beacon_setup(struct ath_softc *sc,
        /* NB: beacon's BufLen must be a multiple of 4 bytes */
        ath9k_hw_filltxdesc(ah, ds
                           , roundup(skb->len, 4) /* buffer length */
-                          , AH_TRUE /* first segment */
-                          , AH_TRUE /* last segment */
+                          , true /* first segment */
+                          , true /* last segment */
                           , ds /* first descriptor */
                );
 
@@ -219,7 +215,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
        ASSERT(avp);
 
        if (avp->av_bcbuf == NULL) {
-               DPRINTF(sc, ATH_DEBUG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
+               DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
                        __func__, avp, avp->av_bcbuf);
                return NULL;
        }
@@ -272,9 +268,9 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
                 * the lock again which is a common function and that
                 * acquires txq lock inside.
                 */
-               if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
-                       ath_tx_draintxq(sc, cabq, AH_FALSE);
-                       DPRINTF(sc, ATH_DEBUG_BEACON,
+               if (sc->sc_nvaps > 1) {
+                       ath_tx_draintxq(sc, cabq, false);
+                       DPRINTF(sc, ATH_DBG_BEACON,
                                "%s: flush previous cabq traffic\n", __func__);
                }
        }
@@ -309,7 +305,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
        ASSERT(avp);
 
        if (avp->av_bcbuf == NULL) {
-               DPRINTF(sc, ATH_DEBUG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
+               DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n",
                        __func__, avp, avp != NULL ? avp->av_bcbuf : NULL);
                return;
        }
@@ -322,7 +318,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
        /* NB: caller is known to have already stopped tx dma */
        ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
        ath9k_hw_txstart(ah, sc->sc_bhalq);
-       DPRINTF(sc, ATH_DEBUG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__,
+       DPRINTF(sc, ATH_DBG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__,
                sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc);
 }
 
@@ -377,7 +373,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
                                struct ath_buf, list);
                list_del(&avp->av_bcbuf->list);
 
-               if (sc->sc_opmode == HAL_M_HOSTAP || !sc->sc_hasveol) {
+               if (sc->sc_opmode == HAL_M_HOSTAP ||
+                       !sc->sc_ah->ah_caps.halVEOLSupport) {
                        int slot;
                        /*
                         * Assign the vap to a beacon xmit slot. As
@@ -399,8 +396,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
                                        avp->av_bslot = slot;
                                        /* NB: keep looking for a double slot */
                                }
-                       KASSERT(sc->sc_bslot[avp->av_bslot] == ATH_IF_ID_ANY,
-                               ("beacon slot %u not empty?", avp->av_bslot));
+                       BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY);
                        sc->sc_bslot[avp->av_bslot] = if_id;
                        sc->sc_nbcnvaps++;
                }
@@ -409,14 +405,10 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
        /* release the previous beacon frame , if it already exists. */
        bf = avp->av_bcbuf;
        if (bf->bf_mpdu != NULL) {
-               struct ath_xmit_status tx_status;
-
-               skb = (struct sk_buff *) bf->bf_mpdu;
+               skb = (struct sk_buff *)bf->bf_mpdu;
                ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
                                     get_dma_mem_context(bf, bf_dmacontext));
-               tx_status.flags = 0;
-               tx_status.retries = 0;
-               ath_tx_complete(sc, skb, &tx_status, NULL);
+               dev_kfree_skb_any(skb);
                bf->bf_mpdu = NULL;
        }
 
@@ -424,10 +416,12 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
         * NB: the beacon data buffer must be 32-bit aligned;
         * we assume the wbuf routines will return us something
         * with this alignment (perhaps should assert).
+        * FIXME: Fill avp->av_boff.bo_tim,avp->av_btxctl.txpower and
+        * avp->av_btxctl.shortPreamble
         */
-       skb = ath_get_beacon(sc, if_id, &avp->av_boff, &avp->av_btxctl);
+       skb = ieee80211_beacon_get(sc->hw, avp->av_if_data);
        if (skb == NULL) {
-               DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get skb\n",
+               DPRINTF(sc, ATH_DBG_BEACON, "%s: cannot get skb\n",
                        __func__);
                return -ENOMEM;
        }
@@ -438,8 +432,9 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
         * of the beacon frame leaves the tstamp field immediately
         * following the header.
         */
-       if (sc->sc_stagbeacons && avp->av_bslot > 0) {
+       if (avp->av_bslot > 0) {
                u_int64_t tsfadjust;
+               __le64 val;
                int intval;
 
                /* FIXME: Use default value for now: Sujith */
@@ -458,15 +453,15 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
                 * others get a timestamp aligned to the next interval.
                 */
                tsfadjust = (intval * (ATH_BCBUF - avp->av_bslot)) / ATH_BCBUF;
-               tsfadjust = cpu_to_le64(tsfadjust<<10);     /* TU->TSF */
+               val = cpu_to_le64(tsfadjust << 10);     /* TU->TSF */
 
-               DPRINTF(sc, ATH_DEBUG_BEACON,
+               DPRINTF(sc, ATH_DBG_BEACON,
                        "%s: %s beacons, bslot %d intval %u tsfadjust %llu\n",
-                       __func__, sc->sc_stagbeacons ? "stagger" : "burst",
+                       __func__, "stagger",
                        avp->av_bslot, intval, (unsigned long long)tsfadjust);
 
                wh = (struct ieee80211_hdr *)skb->data;
-               memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
+               memcpy(&wh[1], &val, sizeof(val));
        }
 
        bf->bf_buf_addr = ath_skb_map_single(sc, skb, PCI_DMA_TODEVICE,
@@ -495,14 +490,10 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp)
 
                bf = avp->av_bcbuf;
                if (bf->bf_mpdu != NULL) {
-                       struct sk_buff *skb = (struct sk_buff *) bf->bf_mpdu;
-                       struct ath_xmit_status tx_status;
-
+                       struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
                        ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
                                get_dma_mem_context(bf, bf_dmacontext));
-                       tx_status.flags = 0;
-                       tx_status.retries = 0;
-                       ath_tx_complete(sc, skb, &tx_status, NULL);
+                       dev_kfree_skb_any(skb);
                        bf->bf_mpdu = NULL;
                }
                list_add_tail(&bf->list, &sc->sc_bbuf);
@@ -527,13 +518,9 @@ void ath_beacon_free(struct ath_softc *sc)
        list_for_each_entry(bf, &sc->sc_bbuf, list) {
                if (bf->bf_mpdu != NULL) {
                        struct sk_buff *skb = (struct sk_buff *) bf->bf_mpdu;
-                       struct ath_xmit_status tx_status;
-
                        ath_skb_unmap_single(sc, skb, PCI_DMA_TODEVICE,
                                get_dma_mem_context(bf, bf_dmacontext));
-                       tx_status.flags = 0;
-                       tx_status.retries = 0;
-                       ath_tx_complete(sc, skb, &tx_status, NULL);
+                       dev_kfree_skb_any(skb);
                        bf->bf_mpdu = NULL;
                }
        }
@@ -562,6 +549,9 @@ void ath9k_beacon_tasklet(unsigned long data)
        u_int32_t rx_clear = 0, rx_frame = 0, tx_frame = 0;
        u_int32_t show_cycles = 0;
        u_int32_t bc = 0; /* beacon count */
+       u_int64_t tsf;
+       u_int32_t tsftu;
+       u_int16_t intval;
 
        if (sc->sc_noreset) {
                show_cycles = ath9k_hw_GetMibCycleCountsPct(ah,
@@ -586,7 +576,7 @@ void ath9k_beacon_tasklet(unsigned long data)
                 */
                if (sc->sc_bmisscount < BSTUCK_THRESH) {
                        if (sc->sc_noreset) {
-                               DPRINTF(sc, ATH_DEBUG_BEACON,
+                               DPRINTF(sc, ATH_DBG_BEACON,
                                        "%s: missed %u consecutive beacons\n",
                                        __func__, sc->sc_bmisscount);
                                if (show_cycles) {
@@ -596,19 +586,19 @@ void ath9k_beacon_tasklet(unsigned long data)
                                         * stickiness.
                                         */
                                        DPRINTF(sc,
-                                               ATH_DEBUG_BEACON,
+                                               ATH_DBG_BEACON,
                                                "%s: busy times: rx_clear=%d, "
                                                "rx_frame=%d, tx_frame=%d\n",
                                                __func__, rx_clear, rx_frame,
                                                tx_frame);
                                } else {
                                        DPRINTF(sc,
-                                               ATH_DEBUG_BEACON,
+                                               ATH_DBG_BEACON,
                                                "%s: unable to obtain "
                                                "busy times\n", __func__);
                                }
                        } else {
-                               DPRINTF(sc, ATH_DEBUG_BEACON,
+                               DPRINTF(sc, ATH_DBG_BEACON,
                                        "%s: missed %u consecutive beacons\n",
                                        __func__, sc->sc_bmisscount);
                        }
@@ -616,13 +606,13 @@ void ath9k_beacon_tasklet(unsigned long data)
                        if (sc->sc_noreset) {
                                if (sc->sc_bmisscount == BSTUCK_THRESH) {
                                        DPRINTF(sc,
-                                               ATH_DEBUG_BEACON,
+                                               ATH_DBG_BEACON,
                                                "%s: beacon is officially "
                                                "stuck\n", __func__);
                                        ath9k_hw_dmaRegDump(ah);
                                }
                        } else {
-                               DPRINTF(sc, ATH_DEBUG_BEACON,
+                               DPRINTF(sc, ATH_DBG_BEACON,
                                        "%s: beacon is officially stuck\n",
                                        __func__);
                                ath_bstuck_process(sc);
@@ -634,11 +624,11 @@ void ath9k_beacon_tasklet(unsigned long data)
        if (sc->sc_bmisscount != 0) {
                if (sc->sc_noreset) {
                        DPRINTF(sc,
-                               ATH_DEBUG_BEACON,
+                               ATH_DBG_BEACON,
                                "%s: resume beacon xmit after %u misses\n",
                                __func__, sc->sc_bmisscount);
                } else {
-                       DPRINTF(sc, ATH_DEBUG_BEACON,
+                       DPRINTF(sc, ATH_DBG_BEACON,
                                "%s: resume beacon xmit after %u misses\n",
                                __func__, sc->sc_bmisscount);
                }
@@ -646,55 +636,29 @@ void ath9k_beacon_tasklet(unsigned long data)
        }
 
        /*
-        * Generate beacon frames.  If we are sending frames
-        * staggered then calculate the slot for this frame based
+        * Generate beacon frames. we are sending frames
+        * staggered so calculate the slot for this frame based
         * on the tsf to safeguard against missing an swba.
-        * Otherwise we are bursting all frames together and need
-        * to generate a frame for each vap that is up and running.
         */
-       if (sc->sc_stagbeacons) {
-               /* staggered beacons */
-               u_int64_t tsf;
-               u_int32_t tsftu;
-               u_int16_t intval;
 
-               /* FIXME: Use default value for now - Sujith */
-               intval = ATH_DEFAULT_BINTVAL;
+       /* FIXME: Use default value for now - Sujith */
+       intval = ATH_DEFAULT_BINTVAL;
 
-               tsf = ath9k_hw_gettsf64(ah);
-               tsftu = TSF_TO_TU(tsf>>32, tsf);
-               slot = ((tsftu % intval) * ATH_BCBUF) / intval;
-               if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF];
-               DPRINTF(sc, ATH_DEBUG_BEACON,
+       tsf = ath9k_hw_gettsf64(ah);
+       tsftu = TSF_TO_TU(tsf>>32, tsf);
+       slot = ((tsftu % intval) * ATH_BCBUF) / intval;
+       if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF];
+       DPRINTF(sc, ATH_DBG_BEACON,
                        "%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n",
                        __func__, slot, (unsigned long long) tsf, tsftu,
                        intval, if_id);
-               bfaddr = 0;
-               if (if_id != ATH_IF_ID_ANY) {
-                       bf = ath_beacon_generate(sc, if_id);
-                       if (bf != NULL) {
-                               bfaddr = bf->bf_daddr;
-                               bc = 1;
-                       }
+       bfaddr = 0;
+       if (if_id != ATH_IF_ID_ANY) {
+               bf = ath_beacon_generate(sc, if_id);
+               if (bf != NULL) {
+                       bfaddr = bf->bf_daddr;
+                       bc = 1;
                }
-       } else {
-               /* XXX: Clean this up, move work to a helper */
-               /* burst'd beacons */
-               u_int32_t *bflink;
-               bflink = &bfaddr;
-               /* XXX rotate/randomize order? */
-               for (slot = 0; slot < ATH_BCBUF; slot++) {
-                       if_id = sc->sc_bslot[slot];
-                       if (if_id != ATH_IF_ID_ANY) {
-                               bf = ath_beacon_generate(sc, if_id);
-                               if (bf != NULL) {
-                                       *bflink = bf->bf_daddr;
-                                       bflink = &bf->bf_desc->ds_link;
-                                       bc++;
-                               }
-                       }
-               }
-               *bflink = 0;    /* link of last frame */
        }
        /*
         * Handle slot time change when a non-ERP station joins/leaves
@@ -719,27 +683,6 @@ void ath9k_beacon_tasklet(unsigned long data)
        } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
                ath_setslottime(sc);        /* commit change to hardware */
 
-       if ((!sc->sc_stagbeacons || slot == 0) && (!sc->sc_diversity)) {
-               int otherant;
-               /*
-                * Check recent per-antenna transmit statistics and flip
-                * the default rx antenna if noticeably more frames went out
-                * on the non-default antenna.  Only do this if rx diversity
-                * is off.
-                * XXX assumes 2 anntenae
-                */
-               otherant = sc->sc_defant & 1 ? 2 : 1;
-               if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] +
-                       ATH_ANTENNA_DIFF) {
-                       DPRINTF(sc, ATH_DEBUG_BEACON,
-                               "%s: flip defant to %u, %u > %u\n",
-                               __func__, otherant, sc->sc_ant_tx[otherant],
-                               sc->sc_ant_tx[sc->sc_defant]);
-                       ath_setdefantenna(sc, otherant);
-               }
-               sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
-       }
-
        if (bfaddr != 0) {
                /*
                 * Stop any current dma and put the new frame(s) on the queue.
@@ -747,7 +690,7 @@ void ath9k_beacon_tasklet(unsigned long data)
                 * are still pending on the queue.
                 */
                if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) {
-                       DPRINTF(sc, ATH_DEBUG_FATAL,
+                       DPRINTF(sc, ATH_DBG_FATAL,
                                "%s: beacon queue %u did not stop?\n",
                                __func__, sc->sc_bhalq);
                        /* NB: the HAL still stops DMA, so proceed */
@@ -771,7 +714,7 @@ void ath9k_beacon_tasklet(unsigned long data)
 
 void ath_bstuck_process(struct ath_softc *sc)
 {
-       DPRINTF(sc, ATH_DEBUG_BEACON,
+       DPRINTF(sc, ATH_DBG_BEACON,
                "%s: stuck beacon; resetting (bmiss count %u)\n",
                __func__, sc->sc_bmisscount);
        ath_internal_reset(sc);
@@ -834,11 +777,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
                 */
                /* NB: the beacon interval is kept internally in TU's */
                intval = conf.beacon_interval & HAL_BEACON_PERIOD;
-               if (sc->sc_stagbeacons)
-                       intval /= ATH_BCBUF;    /* for staggered beacons */
-               if ((sc->sc_nostabeacons) &&
-                   (av_opmode == HAL_M_HOSTAP))
-                       nexttbtt = 0;
+               intval /= ATH_BCBUF;    /* for staggered beacons */
        } else {
                intval = conf.beacon_interval & HAL_BEACON_PERIOD;
        }
@@ -847,13 +786,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
                nexttbtt = intval;
        else if (intval)        /* NB: can be 0 for monitor mode */
                nexttbtt = roundup(nexttbtt, intval);
-       DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
+       DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
                __func__, nexttbtt, intval, conf.beacon_interval);
        /* Check for HAL_M_HOSTAP and sc_nostabeacons for WDS client */
-       if ((sc->sc_opmode == HAL_M_STA) ||
-            ((sc->sc_opmode == HAL_M_HOSTAP) &&
-             (av_opmode == HAL_M_STA) &&
-             (sc->sc_nostabeacons))) {
+       if (sc->sc_opmode == HAL_M_STA) {
                struct hal_beacon_state bs;
                u_int64_t tsf;
                u_int32_t tsftu;
@@ -936,7 +872,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
                if (bs.bs_sleepduration > bs.bs_dtimperiod)
                        bs.bs_sleepduration = bs.bs_dtimperiod;
 
-               DPRINTF(sc, ATH_DEBUG_BEACON,
+               DPRINTF(sc, ATH_DBG_BEACON,
                        "%s: tsf %llu "
                        "tsf:tu %u "
                        "intval %u "
@@ -963,12 +899,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
                        , bs.bs_timoffset
                        );
 
-               if (!(sc->sc_nostabeacons)) {
-                       ath9k_hw_set_interrupts(ah, 0);
-                       ath9k_hw_set_sta_beacon_timers(ah, &bs);
-                       sc->sc_imask |= HAL_INT_BMISS;
-                       ath9k_hw_set_interrupts(ah, sc->sc_imask);
-               }
+               ath9k_hw_set_interrupts(ah, 0);
+               ath9k_hw_set_sta_beacon_timers(ah, &bs);
+               sc->sc_imask |= HAL_INT_BMISS;
+               ath9k_hw_set_interrupts(ah, sc->sc_imask);
        } else {
                u_int64_t tsf;
                u_int32_t tsftu;
@@ -990,7 +924,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
                                } while (nexttbtt < tsftu);
                        }
 #undef FUDGE
-                       DPRINTF(sc, ATH_DEBUG_BEACON,
+                       DPRINTF(sc, ATH_DBG_BEACON,
                                "%s: IBSS nexttbtt %u intval %u (%u)\n",
                                __func__, nexttbtt,
                                intval & ~HAL_BEACON_RESET_TSF,
@@ -1004,7 +938,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
                         * deal with things.
                         */
                        intval |= HAL_BEACON_ENA;
-                       if (!sc->sc_hasveol)
+                       if (!ah->ah_caps.halVEOLSupport)
                                sc->sc_imask |= HAL_INT_SWBA;
                        ath_beaconq_config(sc);
                } else if (sc->sc_opmode == HAL_M_HOSTAP) {
@@ -1023,7 +957,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
                 * When using a self-linked beacon descriptor in
                 * ibss mode load it once here.
                 */
-               if (sc->sc_opmode == HAL_M_IBSS && sc->sc_hasveol)
+               if (sc->sc_opmode == HAL_M_IBSS && ah->ah_caps.halVEOLSupport)
                        ath_beacon_start_adhoc(sc, 0);
        }
 #undef TSF_TO_TU
index a0810ac..587f307 100644 (file)
@@ -19,7 +19,7 @@
 #include "core.h"
 #include "regd.h"
 
-static int ath_outdoor = AH_FALSE;             /* enable outdoor use */
+static int ath_outdoor;                /* enable outdoor use */
 
 static const u_int8_t ath_bcast_mac[ETH_ALEN] =
     { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
@@ -65,7 +65,7 @@ static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
 
        memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
        rt = sc->sc_rates[mode];
-       KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
+       BUG_ON(!rt);
 
        for (i = 0; i < rt->rateCount; i++)
                sc->sc_rixmap[rt->info[i].rateCode] = (u_int8_t) i;
@@ -152,7 +152,7 @@ static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
                                ATH9K_MODE_SEL_11NG_HT40MINUS);
                break;
        default:
-               DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid mode %u\n",
+               DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid mode %u\n",
                        __func__, mode);
                return 0;
        }
@@ -176,8 +176,8 @@ static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
 
 static int ath_getchannels(struct ath_softc *sc,
                           u_int cc,
-                          enum hal_bool outDoor,
-                          enum hal_bool xchanMode)
+                          bool outDoor,
+                          bool xchanMode)
 {
        struct ath_hal *ah = sc->sc_ah;
        struct hal_channel *chans;
@@ -187,7 +187,7 @@ static int ath_getchannels(struct ath_softc *sc,
 
        chans = kmalloc(ATH_CHAN_MAX * sizeof(struct hal_channel), GFP_KERNEL);
        if (chans == NULL) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to allocate channel table\n", __func__);
                return -ENOMEM;
        }
@@ -205,7 +205,7 @@ static int ath_getchannels(struct ath_softc *sc,
                                      xchanMode)) {
                u_int32_t rd = ah->ah_currentRD;
 
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to collect channel list from hal; "
                        "regdomain likely %u country code %u\n",
                        __func__, rd, cc);
@@ -290,7 +290,7 @@ static int ath_stop(struct ath_softc *sc)
 {
        struct ath_hal *ah = sc->sc_ah;
 
-       DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: invalid %u\n",
+       DPRINTF(sc, ATH_DBG_CONFIG, "%s: invalid %u\n",
                __func__, sc->sc_invalid);
 
        /*
@@ -311,7 +311,7 @@ static int ath_stop(struct ath_softc *sc)
 
        if (!sc->sc_invalid)
                ath9k_hw_set_interrupts(ah, 0);
-       ath_draintxq(sc, AH_FALSE);
+       ath_draintxq(sc, false);
        if (!sc->sc_invalid) {
                ath_stoprecv(sc);
                ath9k_hw_phy_disable(ah);
@@ -342,7 +342,7 @@ void ath_scan_start(struct ath_softc *sc)
 
        /* Restore previous power management state. */
 
-       DPRINTF(sc, ATH_DEBUG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0\n",
+       DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0\n",
                now / 1000, now % 1000, __func__, rfilt);
 }
 
@@ -361,11 +361,13 @@ void ath_scan_end(struct ath_softc *sc)
        u_int32_t now = (u_int32_t) jiffies_to_msecs(get_timestamp());
 
        sc->sc_scanning = 0;
+       /* Request for a full reset due to rx packet filter changes */
+       sc->sc_full_reset = 1;
        rfilt = ath_calcrxfilter(sc);
        ath9k_hw_setrxfilter(ah, rfilt);
        ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
 
-       DPRINTF(sc, ATH_DEBUG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0x%x\n",
+       DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0x%x\n",
                now / 1000, now % 1000, __func__, rfilt, sc->sc_curaid);
 }
 
@@ -379,13 +381,13 @@ void ath_scan_end(struct ath_softc *sc)
 int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 {
        struct ath_hal *ah = sc->sc_ah;
-       enum hal_bool fastcc = AH_TRUE, stopped;
+       bool fastcc = true, stopped;
        enum hal_ht_macmode ht_macmode;
 
        if (sc->sc_invalid)     /* if the device is invalid or removed */
                return -EIO;
 
-       DPRINTF(sc, ATH_DEBUG_CONFIG,
+       DPRINTF(sc, ATH_DBG_CONFIG,
                "%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n",
                __func__,
                ath9k_hw_mhz2ieee(ah, sc->sc_curchan.channel,
@@ -410,7 +412,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
                 * the relevant bits of the h/w.
                 */
                ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
-               ath_draintxq(sc, AH_FALSE);     /* clear pending tx frames */
+               ath_draintxq(sc, false);        /* clear pending tx frames */
                stopped = ath_stoprecv(sc);     /* turn off frame recv */
 
                /* XXX: do not flush receive queue here. We don't want
@@ -418,7 +420,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
                 * changing channel. */
 
                if (!stopped || sc->sc_full_reset)
-                       fastcc = AH_FALSE;
+                       fastcc = false;
 
                spin_lock_bh(&sc->sc_resetlock);
                if (!ath9k_hw_reset(ah, sc->sc_opmode, hchan,
@@ -426,7 +428,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
                                        sc->sc_rx_chainmask,
                                        sc->sc_ht_extprotspacing,
                                        fastcc, &status)) {
-                       DPRINTF(sc, ATH_DEBUG_FATAL,
+                       DPRINTF(sc, ATH_DBG_FATAL,
                                "%s: unable to reset channel %u (%uMhz) "
                                "flags 0x%x hal status %u\n", __func__,
                                ath9k_hw_mhz2ieee(ah, hchan->channel,
@@ -443,7 +445,7 @@ int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan)
 
                /* Re-enable rx framework */
                if (ath_startrecv(sc) != 0) {
-                       DPRINTF(sc, ATH_DEBUG_FATAL,
+                       DPRINTF(sc, ATH_DBG_FATAL,
                                "%s: unable to restart recv logic\n", __func__);
                        return -EIO;
                }
@@ -507,10 +509,10 @@ int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
         * sc_chainmask_auto_sel is used for internal global auto-switching
         * enabled/disabled setting
         */
-       if ((sc->sc_no_tx_3_chains == AH_FALSE) ||
-           (sc->sc_config.chainmask_sel == AH_FALSE))
+       if (sc->sc_ah->ah_caps.halTxChainMask != ATH_CHAINMASK_SEL_3X3) {
                cm->cur_tx_mask = sc->sc_tx_chainmask;
                return cm->cur_tx_mask;
+       }
 
        if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER)
                return cm->cur_tx_mask;
@@ -541,56 +543,31 @@ int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
        return cm->cur_tx_mask;
 }
 
-/******************/
-/* VAP management */
-/******************/
-
 /*
- *  Down VAP instance
- *
- *  This routine will stop the indicated VAP and put it in a "down" state.
- *  The down state is basically an initialization state that can be brought
- *  back up by calling the opposite up routine.
- *  This routine will bring the interface out of power save mode, set the
- *  LED states, update the rate control processing, stop DMA transfers, and
- *  set the VAP into the down state.
-*/
+ * Update tx/rx chainmask. For legacy association,
+ * hard code chainmask to 1x1, for 11n association, use
+ * the chainmask configuration.
+ */
 
-int ath_vap_down(struct ath_softc *sc, int if_id, u_int flags)
+void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 {
-       struct ath_hal *ah = sc->sc_ah;
-       struct ath_vap *avp;
-
-       avp = sc->sc_vaps[if_id];
-       if (avp == NULL) {
-               DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
-                       __func__, if_id);
-               return -EINVAL;
-       }
-
-#ifdef CONFIG_SLOW_ANT_DIV
-       if (sc->sc_slowAntDiv)
-               ath_slow_ant_div_stop(&sc->sc_antdiv);
-#endif
-
-       /* update ratectrl about the new state */
-       ath_rate_newstate(sc, avp, 0);
-
-       /* Reclaim beacon resources */
-       if (sc->sc_opmode == HAL_M_HOSTAP || sc->sc_opmode == HAL_M_IBSS) {
-               ath9k_hw_stoptxdma(ah, sc->sc_bhalq);
-               ath_beacon_return(sc, avp);
-       }
-
-       if (flags & ATH_IF_HW_OFF) {
-               sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
-               ath9k_hw_set_interrupts(ah, sc->sc_imask & ~HAL_INT_GLOBAL);
-               sc->sc_beacons = 0;
+       sc->sc_update_chainmask = 1;
+       if (is_ht) {
+               sc->sc_tx_chainmask = sc->sc_ah->ah_caps.halTxChainMask;
+               sc->sc_rx_chainmask = sc->sc_ah->ah_caps.halRxChainMask;
+       } else {
+               sc->sc_tx_chainmask = 1;
+               sc->sc_rx_chainmask = 1;
        }
 
-       return 0;
+       DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
+               __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 }
 
+/******************/
+/* VAP management */
+/******************/
+
 /*
  *  VAP in Listen mode
  *
@@ -608,14 +585,13 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
 
        avp = sc->sc_vaps[if_id];
        if (avp == NULL) {
-               DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
+               DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
                        __func__, if_id);
                return -EINVAL;
        }
 
 #ifdef CONFIG_SLOW_ANT_DIV
-       if (sc->sc_slowAntDiv)
-               ath_slow_ant_div_stop(&sc->sc_antdiv);
+       ath_slow_ant_div_stop(&sc->sc_antdiv);
 #endif
 
        /* update ratectrl about the new state */
@@ -630,7 +606,7 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
        } else
                sc->sc_curaid = 0;
 
-       DPRINTF(sc, ATH_DEBUG_CONFIG,
+       DPRINTF(sc, ATH_DBG_CONFIG,
                "%s: RX filter 0x%x bssid %s aid 0x%x\n",
                __func__, rfilt, print_mac(mac,
                        sc->sc_curbssid), sc->sc_curaid);
@@ -648,210 +624,25 @@ int ath_vap_listen(struct ath_softc *sc, int if_id)
        return 0;
 }
 
-int ath_vap_join(struct ath_softc *sc, int if_id,
-                const u_int8_t bssid[ETH_ALEN], u_int flags)
-{
-       struct ath_hal *ah = sc->sc_ah;
-       struct ath_vap *avp;
-       u_int32_t rfilt = 0;
-       DECLARE_MAC_BUF(mac);
-
-       avp = sc->sc_vaps[if_id];
-       if (avp == NULL) {
-               DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
-                       __func__, if_id);
-               return -EINVAL;
-       }
-
-       /* update ratectrl about the new state */
-       ath_rate_newstate(sc, avp, 0);
-
-       rfilt = ath_calcrxfilter(sc);
-       ath9k_hw_setrxfilter(ah, rfilt);
-
-       memcpy(sc->sc_curbssid, bssid, ETH_ALEN);
-       sc->sc_curaid = 0;
-       ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
-
-       DPRINTF(sc, ATH_DEBUG_CONFIG,
-               "%s: RX filter 0x%x bssid %s aid 0x%x\n",
-               __func__, rfilt,
-               print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
-
-       /*
-        * Update tx/rx chainmask. For legacy association,
-        * hard code chainmask to 1x1, for 11n association, use
-        * the chainmask configuration.
-        */
-       sc->sc_update_chainmask = 1;
-       if (flags & ATH_IF_HT) {
-               sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;
-               sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask;
-       } else {
-               sc->sc_tx_chainmask = 1;
-               sc->sc_rx_chainmask = 1;
-       }
-
-       /* Enable rx chain mask detection if configured to do so */
-
-       sc->sc_rx_chainmask_detect = 0;
-
-       /* Set aggregation protection mode parameters */
-
-       sc->sc_config.ath_aggr_prot = 0;
-
-       /*
-        * Reset our TSF so that its value is lower than the beacon that we are
-        * trying to catch. Only then hw will update its TSF register with the
-        * new beacon. Reset the TSF before setting the BSSID to avoid allowing
-        * in any frames that would update our TSF only to have us clear it
-        * immediately thereafter.
-        */
-       ath9k_hw_reset_tsf(ah);
-
-       /*
-        * XXXX
-        * Disable BMISS interrupt when we're not associated
-        */
-       ath9k_hw_set_interrupts(ah,
-               sc->sc_imask & ~(HAL_INT_SWBA | HAL_INT_BMISS));
-       sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
-       /* need to reconfigure the beacons when it moves to RUN */
-       sc->sc_beacons = 0;
-
-       return 0;
-}
-
-int ath_vap_up(struct ath_softc *sc,
-              int if_id,
-              const u_int8_t bssid[ETH_ALEN],
-              u_int8_t aid, u_int flags)
-{
-       struct ath_hal *ah = sc->sc_ah;
-       struct ath_vap *avp;
-       u_int32_t rfilt = 0;
-       int i, error = 0;
-       DECLARE_MAC_BUF(mac);
-
-       ASSERT(if_id != ATH_IF_ID_ANY);
-       avp = sc->sc_vaps[if_id];
-       if (avp == NULL) {
-               DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
-                       __func__, if_id);
-               return -EINVAL;
-       }
-
-       /* update ratectrl about the new state */
-       ath_rate_newstate(sc, avp, 1);
-
-       rfilt = ath_calcrxfilter(sc);
-       ath9k_hw_setrxfilter(ah, rfilt);
-
-       if (avp->av_opmode == HAL_M_STA || avp->av_opmode == HAL_M_IBSS) {
-               memcpy(sc->sc_curbssid, bssid, ETH_ALEN);
-               sc->sc_curaid = aid;
-               ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
-       }
-
-       DPRINTF(sc, ATH_DEBUG_CONFIG,
-               "%s: RX filter 0x%x bssid %s aid 0x%x\n",
-               __func__, rfilt,
-               print_mac(mac, sc->sc_curbssid), sc->sc_curaid);
-
-       if ((avp->av_opmode != IEEE80211_IF_TYPE_STA) &&
-               (flags & ATH_IF_PRIVACY)) {
-               for (i = 0; i < IEEE80211_WEP_NKID; i++)
-                       if (ath9k_hw_keyisvalid(ah, (u_int16_t) i))
-                               ath9k_hw_keysetmac(ah, (u_int16_t) i, bssid);
-       }
-
-       switch (avp->av_opmode) {
-       case HAL_M_HOSTAP:
-       case HAL_M_IBSS:
-               /*
-                * Allocate and setup the beacon frame.
-                *
-                * Stop any previous beacon DMA.  This may be
-                * necessary, for example, when an ibss merge
-                * causes reconfiguration; there will be a state
-                * transition from RUN->RUN that means we may
-                * be called with beacon transmission active.
-                */
-               ath9k_hw_stoptxdma(ah, sc->sc_bhalq);
-
-               error = ath_beacon_alloc(sc, if_id);
-               if (error != 0)
-                       goto bad;
-
-               if (flags & ATH_IF_BEACON_ENABLE)
-                       sc->sc_beacons = 0;
-
-               break;
-       case HAL_M_STA:
-               /*
-                * start rx chain mask detection if it is enabled.
-                * Use the default chainmask as starting point.
-                */
-               if (sc->sc_rx_chainmask_detect) {
-                       if (flags & ATH_IF_HT)
-                               sc->sc_rx_chainmask =
-                                       ah->ah_caps.halRxChainMask;
-                       else
-                               sc->sc_rx_chainmask = 1;
-
-                       sc->sc_rx_chainmask_start = 1;
-               }
-               break;
-       default:
-               break;
-       }
-       /* Moved beacon_config after dfs_wait check
-        * so that ath_beacon_config won't be called duing dfswait
-        * period - this will fix the beacon stuck afer DFS
-        * CAC period issue
-        * Configure the beacon and sleep timers. */
-
-       if (!sc->sc_beacons && !(flags & ATH_IF_BEACON_SYNC)) {
-               ath_beacon_config(sc, if_id);
-               sc->sc_beacons = 1;
-       }
-
-       /* Reset rssi stats; maybe not the best place... */
-       if (flags & ATH_IF_HW_ON) {
-               sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
-               sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
-               sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
-               sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
-       }
-bad:
-       return error;
-}
-
 int ath_vap_attach(struct ath_softc *sc,
                   int if_id,
                   struct ieee80211_vif *if_data,
-                  enum hal_opmode opmode,
-                  enum hal_opmode iv_opmode,
-                  int nostabeacons)
+                  enum hal_opmode opmode)
 {
        struct ath_vap *avp;
 
        if (if_id >= ATH_BCBUF || sc->sc_vaps[if_id] != NULL) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: Invalid interface id = %u\n", __func__, if_id);
                return -EINVAL;
        }
 
        switch (opmode) {
        case HAL_M_STA:
-               sc->sc_nostabeacons = nostabeacons;
-               break;
        case HAL_M_IBSS:
        case HAL_M_MONITOR:
                break;
        case HAL_M_HOSTAP:
-               /* copy nostabeacons - for WDS client */
-               sc->sc_nostabeacons = nostabeacons;
                /* XXX not right, beacon buffer is allocated on RUN trans */
                if (list_empty(&sc->sc_bbuf))
                        return -ENOMEM;
@@ -868,24 +659,13 @@ int ath_vap_attach(struct ath_softc *sc,
        memzero(avp, sizeof(struct ath_vap));
        avp->av_if_data = if_data;
        /* Set the VAP opmode */
-       avp->av_opmode = iv_opmode;
+       avp->av_opmode = opmode;
        avp->av_bslot = -1;
        INIT_LIST_HEAD(&avp->av_mcastq.axq_q);
        INIT_LIST_HEAD(&avp->av_mcastq.axq_acq);
        spin_lock_init(&avp->av_mcastq.axq_lock);
-       if (opmode == HAL_M_HOSTAP || opmode == HAL_M_IBSS) {
-               if (sc->sc_hastsfadd) {
-                       /*
-                        * Multiple vaps are to transmit beacons and we
-                        * have h/w support for TSF adjusting; enable use
-                        * of staggered beacons.
-                        */
-                       /* XXX check for beacon interval too small */
-                       sc->sc_stagbeacons = 1;
-               }
-       }
-       if (sc->sc_hastsfadd)
-               ath9k_hw_set_tsfadjust(sc->sc_ah, sc->sc_stagbeacons);
+
+       ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
 
        sc->sc_vaps[if_id] = avp;
        sc->sc_nvaps++;
@@ -906,7 +686,7 @@ int ath_vap_detach(struct ath_softc *sc, int if_id)
 
        avp = sc->sc_vaps[if_id];
        if (avp == NULL) {
-               DPRINTF(sc, ATH_DEBUG_FATAL, "%s: invalid interface id %u\n",
+               DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
                        __func__, if_id);
                return -EINVAL;
        }
@@ -919,32 +699,17 @@ int ath_vap_detach(struct ath_softc *sc, int if_id)
         * XXX can we do this w/o affecting other vap's?
         */
        ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
-       ath_draintxq(sc, AH_FALSE);     /* stop xmit side */
+       ath_draintxq(sc, false);        /* stop xmit side */
        ath_stoprecv(sc);       /* stop recv side */
        ath_flushrecv(sc);      /* flush recv queue */
 
        /* Reclaim any pending mcast bufs on the vap. */
-       ath_tx_draintxq(sc, &avp->av_mcastq, AH_FALSE);
-
-       if (sc->sc_opmode == HAL_M_HOSTAP && sc->sc_nostabeacons)
-               sc->sc_nostabeacons = 0;
+       ath_tx_draintxq(sc, &avp->av_mcastq, false);
 
        kfree(avp);
        sc->sc_vaps[if_id] = NULL;
        sc->sc_nvaps--;
 
-       /* restart H/W in case there are other VAPs */
-       if (sc->sc_nvaps) {
-               /* Restart rx+tx machines if device is still running. */
-               if (ath_startrecv(sc) != 0)     /* restart recv */
-                       DPRINTF(sc, ATH_DEBUG_FATAL,
-                               "%s: unable to start recv logic\n", __func__);
-               if (sc->sc_beacons)
-                       /* restart beacons */
-                       ath_beacon_config(sc, ATH_IF_ID_ANY);
-
-               ath9k_hw_set_interrupts(ah, sc->sc_imask);
-       }
        return 0;
 }
 
@@ -954,7 +719,7 @@ int ath_vap_config(struct ath_softc *sc,
        struct ath_vap *avp;
 
        if (if_id >= ATH_BCBUF) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: Invalid interface id = %u\n", __func__, if_id);
                return -EINVAL;
        }
@@ -979,7 +744,7 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
        int error = 0;
        enum hal_ht_macmode ht_macmode = ath_cwm_macmode(sc);
 
-       DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
+       DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
 
        /*
         * Stop anything previously setup.  This is safe
@@ -1006,8 +771,8 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
        spin_lock_bh(&sc->sc_resetlock);
        if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, ht_macmode,
                           sc->sc_tx_chainmask, sc->sc_rx_chainmask,
-                          sc->sc_ht_extprotspacing, AH_FALSE, &status)) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+                          sc->sc_ht_extprotspacing, false, &status)) {
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to reset hardware; hal status %u "
                        "(freq %u flags 0x%x)\n", __func__, status,
                        sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
@@ -1030,7 +795,7 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
         * here except setup the interrupt mask.
         */
        if (ath_startrecv(sc) != 0) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to start recv logic\n", __func__);
                error = -EIO;
                goto done;
@@ -1043,14 +808,14 @@ int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan)
        if (ah->ah_caps.halGTTSupport)
                sc->sc_imask |= HAL_INT_GTT;
 
-       if (sc->sc_hashtsupport)
+       if (ah->ah_caps.halHTSupport)
                sc->sc_imask |= HAL_INT_CST;
 
        /*
         * Enable MIB interrupts when there are hardware phy counters.
         * Note we only do this (at the moment) for station mode.
         */
-       if (sc->sc_needmib &&
+       if (ath9k_hw_phycounters(ah) &&
            ((sc->sc_opmode == HAL_M_STA) || (sc->sc_opmode == HAL_M_IBSS)))
                sc->sc_imask |= HAL_INT_MIB;
        /*
@@ -1101,7 +866,7 @@ static int ath_reset_end(struct ath_softc *sc, u_int32_t flag)
        struct ath_hal *ah = sc->sc_ah;
 
        if (ath_startrecv(sc) != 0)     /* restart recv */
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to start recv logic\n", __func__);
 
        /*
@@ -1143,8 +908,8 @@ int ath_reset(struct ath_softc *sc)
        if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan,
                           ht_macmode,
                           sc->sc_tx_chainmask, sc->sc_rx_chainmask,
-                          sc->sc_ht_extprotspacing, AH_FALSE, &status)) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+                          sc->sc_ht_extprotspacing, false, &status)) {
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to reset hardware; hal status %u\n",
                        __func__, status);
                error = -EIO;
@@ -1180,11 +945,12 @@ int ath_suspend(struct ath_softc *sc)
 /* Interrupt handler.  Most of the actual processing is deferred.
  * It's the caller's responsibility to ensure the chip is awake. */
 
-int ath_intr(struct ath_softc *sc)
+irqreturn_t ath_isr(int irq, void *dev)
 {
+       struct ath_softc *sc = dev;
        struct ath_hal *ah = sc->sc_ah;
        enum hal_int status;
-       int sched = ATH_ISR_NOSCHED;
+       bool sched = false;
 
        do {
                if (sc->sc_invalid) {
@@ -1193,10 +959,10 @@ int ath_intr(struct ath_softc *sc)
                         * touch anything. Note this can happen early
                         * on if the IRQ is shared.
                         */
-                       return ATH_ISR_NOTMINE;
+                       return IRQ_NONE;
                }
                if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
-                       return ATH_ISR_NOTMINE;
+                       return IRQ_NONE;
                }
 
                /*
@@ -1215,16 +981,16 @@ int ath_intr(struct ath_softc *sc)
                 */
 
                if (!status)
-                       return ATH_ISR_NOTMINE;
+                       return IRQ_NONE;
 
                sc->sc_intrstatus = status;
 
                if (status & HAL_INT_FATAL) {
                        /* need a chip reset */
-                       sched = ATH_ISR_SCHED;
+                       sched = true;
                } else if (status & HAL_INT_RXORN) {
                        /* need a chip reset */
-                       sched = ATH_ISR_SCHED;
+                       sched = true;
                } else {
                        if (status & HAL_INT_SWBA) {
                                /* schedule a tasklet for beacon handling */
@@ -1236,22 +1002,22 @@ int ath_intr(struct ath_softc *sc)
                                 *     RXE bit is written, but it doesn't work
                                 *     at least on older hardware revs.
                                 */
-                               sched = ATH_ISR_SCHED;
+                               sched = true;
                        }
 
                        if (status & HAL_INT_TXURN)
                                /* bump tx trigger level */
-                               ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
+                               ath9k_hw_updatetxtriglevel(ah, true);
                        /* XXX: optimize this */
                        if (status & HAL_INT_RX)
-                               sched = ATH_ISR_SCHED;
+                               sched = true;
                        if (status & HAL_INT_TX)
-                               sched = ATH_ISR_SCHED;
+                               sched = true;
                        if (status & HAL_INT_BMISS)
-                               sched = ATH_ISR_SCHED;
+                               sched = true;
                        /* carrier sense timeout */
                        if (status & HAL_INT_CST)
-                               sched = ATH_ISR_SCHED;
+                               sched = true;
                        if (status & HAL_INT_MIB) {
                                /*
                                 * Disable interrupts until we service the MIB
@@ -1268,26 +1034,23 @@ int ath_intr(struct ath_softc *sc)
                                ath9k_hw_set_interrupts(ah, sc->sc_imask);
                        }
                        if (status & HAL_INT_TIM_TIMER) {
-                               if (!sc->sc_hasautosleep) {
+                               if (!ah->ah_caps.halAutoSleepSupport) {
                                        /* Clear RxAbort bit so that we can
                                         * receive frames */
                                        ath9k_hw_setrxabort(ah, 0);
-                                       /* Set flag indicating we're waiting
-                                        * for a beacon */
-                                       sc->sc_waitbeacon = 1;
-
-                                       sched = ATH_ISR_SCHED;
+                                       sched = true;
                                }
                        }
                }
        } while (0);
 
-       if (sched == ATH_ISR_SCHED)
+       if (sched) {
                /* turn off every interrupt except SWBA */
                ath9k_hw_set_interrupts(ah, (sc->sc_imask & HAL_INT_SWBA));
+               tasklet_schedule(&sc->intr_tq);
+       }
 
-       return sched;
-
+       return IRQ_HANDLED;
 }
 
 /* Deferred interrupt processing  */
@@ -1335,11 +1098,6 @@ static void ath9k_tasklet(unsigned long data)
        ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 }
 
-void ath_set_macmode(struct ath_softc *sc, enum hal_ht_macmode macmode)
-{
-       ath9k_hw_set11nmac2040(sc->sc_ah, macmode);
-}
-
 int ath_init(u_int16_t devid, struct ath_softc *sc)
 {
        struct ath_hal *ah = NULL;
@@ -1352,7 +1110,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
        sc->sc_invalid = 1;
 
        sc->sc_debug = DBG_DEFAULT;
-       DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
+       DPRINTF(sc, ATH_DBG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
 
        /* Initialize tasklet */
        tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
@@ -1371,7 +1129,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
 
        ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
        if (ah == NULL) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to attach hardware; HAL status %u\n",
                        __func__, status);
                error = -ENXIO;
@@ -1382,29 +1140,10 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
        /* Get the chipset-specific aggr limit. */
        sc->sc_rtsaggrlimit = ah->ah_caps.halRtsAggrLimit;
 
-       /*
-        * Check if the MAC has multi-rate retry support.
-        * We do this by trying to setup a fake extended
-        * descriptor.  MAC's that don't have support will
-        * return false w/o doing anything.  MAC's that do
-        * support it will return true w/o doing anything.
-        *
-        *  XXX This is lame.  Just query a hal property, Luke!
-        */
-       sc->sc_mrretry = ath9k_hw_setupxtxdesc(ah, NULL, 0, 0, 0, 0, 0, 0);
-
-       /*
-        * Check if the device has hardware counters for PHY
-        * errors.  If so we need to enable the MIB interrupt
-        * so we can act on stat triggers.
-        */
-       if (ath9k_hw_phycounters(ah))
-               sc->sc_needmib = 1;
-
        /* Get the hardware key cache size. */
        sc->sc_keymax = ah->ah_caps.halKeyCacheSize;
        if (sc->sc_keymax > ATH_KEYMAX) {
-               DPRINTF(sc, ATH_DEBUG_KEYCACHE,
+               DPRINTF(sc, ATH_DBG_KEYCACHE,
                        "%s: Warning, using only %u entries in %u key cache\n",
                        __func__, ATH_KEYMAX, sc->sc_keymax);
                sc->sc_keymax = ATH_KEYMAX;
@@ -1463,14 +1202,14 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
         */
        sc->sc_bhalq = ath_beaconq_setup(ah);
        if (sc->sc_bhalq == -1) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to setup a beacon xmit queue\n", __func__);
                error = -EIO;
                goto bad2;
        }
        sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
        if (sc->sc_cabq == NULL) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to setup CAB xmit queue\n", __func__);
                error = -EIO;
                goto bad2;
@@ -1485,7 +1224,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
        /* Setup data queues */
        /* NB: ensure BK queue is the lowest priority h/w queue */
        if (!ath_tx_setup(sc, HAL_WME_AC_BK)) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to setup xmit queue for BK traffic\n",
                        __func__);
                error = -EIO;
@@ -1493,30 +1232,27 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
        }
 
        if (!ath_tx_setup(sc, HAL_WME_AC_BE)) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to setup xmit queue for BE traffic\n",
                        __func__);
                error = -EIO;
                goto bad2;
        }
        if (!ath_tx_setup(sc, HAL_WME_AC_VI)) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to setup xmit queue for VI traffic\n",
                        __func__);
                error = -EIO;
                goto bad2;
        }
        if (!ath_tx_setup(sc, HAL_WME_AC_VO)) {
-               DPRINTF(sc, ATH_DEBUG_FATAL,
+               DPRINTF(sc, ATH_DBG_FATAL,
                        "%s: unable to setup xmit queue for VO traffic\n",
                        __func__);
                error = -EIO;
                goto bad2;
        }
 
-       if (ah->ah_caps.halHTSupport)
-               sc->sc_hashtsupport = 1;
-
        sc->sc_rc = ath_rate_attach(ah);
        if (sc->sc_rc == NULL) {
                error = EIO;
@@ -1532,8 +1268,6 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
                 */
                ath9k_hw_setcapability(sc->sc_ah, HAL_CAP_TKIP_MIC, 0, 1, NULL);
        }
-       sc->sc_hasclrkey = ath9k_hw_getcapability(ah, HAL_CAP_CIPHER,
-                                                 HAL_CIPHER_CLR, NULL);
 
        /*
         * Check whether the separate key cache entries
@@ -1556,26 +1290,11 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
        sc->sc_config.txpowlimit_override = 0;
 
        /* 11n Capabilities */
-       if (sc->sc_hashtsupport) {
+       if (ah->ah_caps.halHTSupport) {
                sc->sc_txaggr = 1;
                sc->sc_rxaggr = 1;
        }
 
-       /* Check for misc other capabilities. */
-       sc->sc_hasbmask = ah->ah_caps.halBssIdMaskSupport ? 1 : 0;
-       sc->sc_hastsfadd =
-               ath9k_hw_getcapability(ah, HAL_CAP_TSF_ADJUST, 0, NULL);
-
-       /*
-        * If we cannot transmit on three chains, prevent chain mask
-        * selection logic from switching between 2x2 and 3x3 chain
-        * masks based on RSSI.
-        */
-       sc->sc_no_tx_3_chains =
-           (ah->ah_caps.halTxChainMask == ATH_CHAINMASK_SEL_3X3) ?
-               AH_TRUE : AH_FALSE;
-       sc->sc_config.chainmask_sel = sc->sc_no_tx_3_chains;
-
        sc->sc_tx_chainmask = ah->ah_caps.halTxChainMask;
        sc->sc_rx_chainmask = ah->ah_caps.halRxChainMask;
 
@@ -1586,37 +1305,15 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
        sc->sc_rxchaindetect_delta5GHz = 30;
        sc->sc_rxchaindetect_delta2GHz = 30;
 
-       /*
-        * Query the hal about antenna support
-        * Enable rx fast diversity if hal has support
-        */
-       if (ath9k_hw_getcapability(ah, HAL_CAP_DIVERSITY, 0, NULL)) {
-               sc->sc_hasdiversity = 1;
-               ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY,
-                       1, AH_TRUE, NULL);
-               sc->sc_diversity = 1;
-       } else {
-               sc->sc_hasdiversity = 0;
-               sc->sc_diversity = 0;
-               ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY,
-                       1, AH_FALSE, NULL);
-       }
+       ath9k_hw_setcapability(ah, HAL_CAP_DIVERSITY, 1, true, NULL);
        sc->sc_defant = ath9k_hw_getdefantenna(ah);
 
-       /*
-        * Not all chips have the VEOL support we want to
-        * use with IBSS beacons; check here for it.
-        */
-       sc->sc_hasveol = ah->ah_caps.halVEOLSupport;
-
        ath9k_hw_getmac(ah, sc->sc_myaddr);
-       if (sc->sc_hasbmask) {
+       if (ah->ah_caps.halBssIdMaskSupport) {
                ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
                ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
                ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
        }
-       sc->sc_hasautosleep = ah->ah_caps.halAutoSleepSupport;
-       sc->sc_waitbeacon = 0;
        sc->sc_slottime = HAL_SLOT_TIME_9;      /* default to short slot time */
 
        /* initialize beacon slots */
@@ -1627,11 +1324,8 @@ int ath_init(u_int16_t devid, struct ath_softc *sc)
        sc->sc_config.swBeaconProcess = 1;
 
 #ifdef CONFIG_SLOW_ANT_DIV
-       sc->sc_slowAntDiv = 1;
        /* range is 40 - 255, we use something in the middle */
        ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
-#else
-       sc->sc_slowAntDiv = 0;
 #endif
 
        return 0;
@@ -1651,7 +1345,7 @@ void ath_deinit(struct ath_softc *sc)
        struct ath_hal *ah = sc->sc_ah;
        int i;
 
-       DPRINTF(sc, ATH_DEBUG_CONFIG, "%s\n", __func__);
+       DPRINTF(sc, ATH_DBG_CONFIG, "%s\n", __func__);
 
        ath_stop(sc);
        if (!sc->sc_invalid)
@@ -1695,9 +1389,6 @@ struct ath_node *ath_node_attach(struct ath_softc *sc, u8 *addr, int if_id)
        ath_chainmask_sel_timerstart(&an->an_chainmask_sel);
        list_add(&an->list, &sc->node_list);
 
-       DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p for: %s\n",
-               __func__, an, print_mac(mac, addr));
-
        return an;
 }
 
@@ -1721,9 +1412,6 @@ void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
 
        spin_unlock_irqrestore(&sc->node_lock, flags);
 
-       DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p for: %s\n",
-               __func__, an, print_mac(mac, an->an_addr));
-
        kfree(an);
 }
 
@@ -1799,6 +1487,7 @@ void ath_newassoc(struct ath_softc *sc,
 /**************/
 /* Encryption */
 /**************/
+
 void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot)
 {
        ath9k_hw_keyreset(sc->sc_ah, keyix);
@@ -1811,12 +1500,12 @@ int ath_keyset(struct ath_softc *sc,
               struct hal_keyval *hk,
               const u_int8_t mac[ETH_ALEN])
 {
-       enum hal_bool status;
+       bool status;
 
        status = ath9k_hw_set_keycache_entry(sc->sc_ah,
-               keyix, hk, mac, AH_FALSE);
+               keyix, hk, mac, false);
 
-       return status != AH_FALSE;
+       return status != false;
 }
 
 /***********************/
@@ -2020,12 +1709,12 @@ int ath_descdma_setup(struct ath_softc *sc,
        struct ath_buf *bf;
        int i, bsize, error;
 
-       DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
+       DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
                __func__, name, nbuf, ndesc);
 
        /* ath_desc must be a multiple of DWORDs */
        if ((sizeof(struct ath_desc) % 4) != 0) {
-               DPRINTF(sc, ATH_DEBUG_FATAL, "%s: ath_desc not DWORD aligned\n",
+               DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
                        __func__);
                ASSERT((sizeof(struct ath_desc) % 4) == 0);
                error = -ENOMEM;
@@ -2062,7 +1751,7 @@ int ath_descdma_setup(struct ath_softc *sc,
                goto fail;
        }
        ds = dd->dd_desc;
-       DPRINTF(sc, ATH_DEBUG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
+       DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
                __func__, dd->dd_name, ds, (u_int32_t) dd->dd_desc_len,
                ito64(dd->dd_desc_paddr), /*XXX*/(u_int32_t) dd->dd_desc_len);
 
@@ -2143,14 +1832,6 @@ void ath_internal_reset(struct ath_softc *sc)
        ath_reset_end(sc, 0);
 }
 
-void ath_setrxfilter(struct ath_softc *sc)
-{
-       u_int32_t rxfilt;
-
-       rxfilt = ath_calcrxfilter(sc);
-       ath9k_hw_setrxfilter(sc->sc_ah, rxfilt);
-}
-
 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
 {
        int qnum;
index 9348107..b271343 100644 (file)
@@ -156,13 +156,6 @@ static inline void list_cut_position(struct list_head *list,
                }                               \
        } while (0)
 
-#define KASSERT(exp, msg) do {                 \
-               if (unlikely(!(exp))) {         \
-                       printk msg;             \
-                       BUG();                  \
-               }                               \
-       } while (0)
-
 /* XXX: remove */
 #define memzero(_buf, _len) memset(_buf, 0, _len)
 
@@ -184,23 +177,29 @@ static inline unsigned long get_timestamp(void)
 /*************/
 
 enum ATH_DEBUG {
-       ATH_DEBUG_XMIT          = 0x00000001,   /* basic xmit operation */
-       ATH_DEBUG_RECV          = 0x00000002,   /* basic recv operation */
-       ATH_DEBUG_BEACON        = 0x00000004,   /* beacon handling */
-       ATH_DEBUG_TX_PROC       = 0x00000008,   /* tx ISR proc */
-       ATH_DEBUG_RX_PROC       = 0x00000010,   /* rx ISR proc */
-       ATH_DEBUG_BEACON_PROC   = 0x00000020,   /* beacon ISR proc */
-       ATH_DEBUG_RATE          = 0x00000040,   /* rate control */
-       ATH_DEBUG_CONFIG        = 0x00000080,   /* configuration */
-       ATH_DEBUG_KEYCACHE      = 0x00000100,   /* key cache management */
-       ATH_DEBUG_NODE          = 0x00000200,   /* node management */
-       ATH_DEBUG_AGGR          = 0x00000400,   /* Aggregation */
-       ATH_DEBUG_CWM           = 0x00000800,   /* Channel Width Management */
-       ATH_DEBUG_FATAL         = 0x00001000,   /* fatal errors */
-       ATH_DEBUG_ANY           = 0xffffffff
+       ATH_DBG_RESET           = 0x00000001,
+       ATH_DBG_PHY_IO          = 0x00000002,
+       ATH_DBG_REG_IO          = 0x00000004,
+       ATH_DBG_QUEUE           = 0x00000008,
+       ATH_DBG_EEPROM          = 0x00000010,
+       ATH_DBG_NF_CAL          = 0x00000020,
+       ATH_DBG_CALIBRATE       = 0x00000040,
+       ATH_DBG_CHANNEL         = 0x00000080,
+       ATH_DBG_INTERRUPT       = 0x00000100,
+       ATH_DBG_REGULATORY      = 0x00000200,
+       ATH_DBG_ANI             = 0x00000400,
+       ATH_DBG_POWER_MGMT      = 0x00000800,
+       ATH_DBG_XMIT            = 0x00001000,
+       ATH_DBG_BEACON          = 0x00002000,
+       ATH_DBG_RATE            = 0x00004000,
+       ATH_DBG_CONFIG          = 0x00008000,
+       ATH_DBG_KEYCACHE        = 0x00010000,
+       ATH_DBG_AGGR            = 0x00020000,
+       ATH_DBG_FATAL           = 0x00040000,
+       ATH_DBG_ANY             = 0xffffffff
 };
 
-#define DBG_DEFAULT (ATH_DEBUG_FATAL)
+#define DBG_DEFAULT (ATH_DBG_FATAL)
 
 #define        DPRINTF(sc, _m, _fmt, ...) do {                 \
                if (sc->sc_debug & (_m))                \
@@ -214,7 +213,6 @@ enum ATH_DEBUG {
 /* Per-instance load-time (note: NOT run-time) configurations
  * for Atheros Device */
 struct ath_config {
-       u_int8_t    chainmask_sel; /* enable automatic tx chainmask selection */
        u_int32_t   ath_aggr_prot;
        u_int16_t   txpowlimit;
        u_int16_t   txpowlimit_override;
@@ -249,6 +247,7 @@ struct ath_chainmask_sel {
 };
 
 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
+void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 
 /*************************/
 /* Descriptor Management */
@@ -452,9 +451,8 @@ struct ath_arx {
        struct ath_arx_tid  tid[WME_NUM_TID];
 };
 
-void ath_setrxfilter(struct ath_softc *sc);
 int ath_startrecv(struct ath_softc *sc);
-enum hal_bool ath_stoprecv(struct ath_softc *sc);
+bool ath_stoprecv(struct ath_softc *sc);
 void ath_flushrecv(struct ath_softc *sc);
 u_int32_t ath_calcrxfilter(struct ath_softc *sc);
 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
@@ -635,9 +633,9 @@ struct ath_tx_stat {
 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 int ath_tx_setup(struct ath_softc *sc, int haltype);
-void ath_draintxq(struct ath_softc *sc, enum hal_bool retry_tx);
+void ath_draintxq(struct ath_softc *sc, bool retry_tx);
 void ath_tx_draintxq(struct ath_softc *sc,
-       struct ath_txq *txq, enum hal_bool retry_tx);
+       struct ath_txq *txq, bool retry_tx);
 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 void ath_tx_node_cleanup(struct ath_softc *sc,
        struct ath_node *an, bool bh_flag);
@@ -695,7 +693,7 @@ void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 
 #define ATH_DS_BA_SEQ(_ds)               ((_ds)->ds_us.tx.ts_seqnum)
 #define ATH_DS_BA_BITMAP(_ds)            (&(_ds)->ds_us.tx.ba_low)
-#define ATH_DS_TX_BA(_ds)                ((_ds)->ds_us.tx.ts_flags & HAL_TX_BA)
+#define ATH_DS_TX_BA(_ds)      ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
 #define ATH_AN_2_TID(_an, _tidno)        (&(_an)->an_aggr.tx.tid[(_tidno)])
 
 enum ATH_AGGR_STATUS {
@@ -822,10 +820,6 @@ void ath_update_beacon_info(struct ath_softc *sc, int avgbrssi);
 void ath_get_beaconconfig(struct ath_softc *sc,
                          int if_id,
                          struct ath_beacon_config *conf);
-struct sk_buff *ath_get_beacon(struct ath_softc *sc,
-                              int if_id,
-                              struct ath_beacon_offset *bo,
-                              struct ath_tx_control *txctl);
 int ath_update_beacon(struct ath_softc *sc,
                      int if_id,
                      struct ath_beacon_offset *bo,
@@ -880,23 +874,11 @@ struct ath_vap {
 int ath_vap_attach(struct ath_softc *sc,
                   int if_id,
                   struct ieee80211_vif *if_data,
-                  enum hal_opmode opmode,
-                  enum hal_opmode iv_opmode,
-                  int nostabeacons);
+                  enum hal_opmode opmode);
 int ath_vap_detach(struct ath_softc *sc, int if_id);
 int ath_vap_config(struct ath_softc *sc,
        int if_id, struct ath_vap_config *if_config);
-int ath_vap_down(struct ath_softc *sc, int if_id, u_int flags);
 int ath_vap_listen(struct ath_softc *sc, int if_id);
-int ath_vap_join(struct ath_softc *sc,
-                int if_id,
-                const u_int8_t bssid[ETH_ALEN],
-                u_int flags);
-int ath_vap_up(struct ath_softc *sc,
-              int if_id,
-              const u_int8_t bssid[ETH_ALEN],
-              u_int8_t aid,
-              u_int flags);
 
 /*********************/
 /* Antenna diversity */
@@ -972,12 +954,6 @@ void ath_setdefantenna(void *sc, u_int antenna);
 
 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 
-#define ATH_ISR_NOSCHED         0x0000 /* Do not schedule bottom half */
-/* Schedule the bottom half for execution */
-#define ATH_ISR_SCHED           0x0001
-/* This was not my interrupt, for shared IRQ's */
-#define ATH_ISR_NOTMINE         0x0002
-
 #define RSSI_LPF_THRESHOLD         -20
 #define ATH_RSSI_EP_MULTIPLIER     (1<<7)  /* pow2 to optimize out * and / */
 #define ATH_RATE_DUMMY_MARKER      0
@@ -1042,34 +1018,13 @@ struct ath_softc {
        enum hal_opmode         sc_opmode;  /* current operating mode */
 
        /* Properties, Config */
-       unsigned int
-               sc_invalid             : 1, /* being detached */
-               sc_mrretry             : 1, /* multi-rate retry support */
-               sc_needmib             : 1, /* enable MIB stats intr */
-               sc_hasdiversity        : 1, /* rx diversity available */
-               sc_diversity           : 1, /* enable rx diversity */
-               sc_hasveol             : 1, /* tx VEOL support */
-               sc_beacons             : 1, /* beacons running */
-               sc_hasbmask            : 1, /* bssid mask support */
-               sc_hastsfadd           : 1, /* tsf adjust support */
-               sc_scanning            : 1, /* scanning active */
-               sc_nostabeacons        : 1, /* no beacons for station */
-               sc_hasclrkey           : 1, /* CLR key supported */
-               sc_stagbeacons         : 1, /* use staggered beacons */
-               sc_txaggr              : 1, /* enable 11n tx aggregation */
-               sc_rxaggr              : 1, /* enable 11n rx aggregation */
-               sc_hasautosleep        : 1, /* automatic sleep after TIM */
-               sc_waitbeacon          : 1, /* waiting for first beacon
-                                               after waking up */
-               sc_no_tx_3_chains      : 1, /* user, hardware, regulatory
-                                       or country may disallow transmit on
-                                       three chains. */
-               sc_update_chainmask    : 1, /* change chain mask */
-               sc_rx_chainmask_detect : 1, /* enable rx chain mask detection */
-               sc_rx_chainmask_start  : 1, /* start rx chain mask detection */
-               sc_hashtsupport        : 1, /* supports 11n */
-               sc_full_reset          : 1, /* force full reset */
-               sc_slowAntDiv          : 1; /* enable slow antenna diversity */
+       u_int8_t                sc_invalid;     /* being detached */
+       u_int8_t                sc_beacons;     /* beacons running */
+       u_int8_t                sc_scanning;    /* scanning active */
+       u_int8_t                sc_txaggr;      /* enable 11n tx aggregation */
+       u_int8_t                sc_rxaggr;      /* enable 11n rx aggregation */
+       u_int8_t                sc_update_chainmask;    /* change chain mask */
+       u_int8_t                sc_full_reset;          /* force full reset */
        enum wireless_mode      sc_curmode;     /* current phy mode */
        u_int16_t               sc_curtxpow;    /* current tx power limit */
        u_int16_t               sc_curaid;      /* current association id */
@@ -1119,7 +1074,7 @@ struct ath_softc {
 
        /* Crypto */
        u_int                   sc_keymax;      /* size of key cache */
-       u_int8_t                sc_keymap[ATH_KEYBYTES];/* key use bit map */
+       DECLARE_BITMAP          (sc_keymap, ATH_KEYBYTES);/* key use bit map */
        u_int8_t                sc_splitmic;    /* split TKIP MIC keys */
        int                     sc_keytype;     /* type of the key being used */
 
@@ -1181,7 +1136,7 @@ int ath_init(u_int16_t devid, struct ath_softc *sc);
 void ath_deinit(struct ath_softc *sc);
 int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan);
 int ath_suspend(struct ath_softc *sc);
-int ath_intr(struct ath_softc *sc);
+irqreturn_t ath_isr(int irq, void *dev);
 int ath_reset(struct ath_softc *sc);
 void ath_scan_start(struct ath_softc *sc);
 void ath_scan_end(struct ath_softc *sc);
@@ -1202,7 +1157,6 @@ void ath_setup_rate(struct ath_softc *sc,
 /* Utility Functions */
 /*********************/
 
-void ath_set_macmode(struct ath_softc *sc, enum hal_ht_macmode macmode);
 void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot);
 int ath_keyset(struct ath_softc *sc,
               u_int16_t keyix,
index de91934..a16dbfb 100644 (file)
@@ -16,7 +16,7 @@
 
 #include <linux/io.h>
 
-#include "ath9k.h"
+#include "core.h"
 #include "hw.h"
 #include "reg.h"
 #include "phy.h"
@@ -111,14 +111,14 @@ static struct hal_rate_table ar5416_11a_table = {
        8,
        {0},
        {
-               {AH_TRUE, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
-               {AH_TRUE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
-               {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
-               {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
-               {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
-               {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
-               {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
-               {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
+               {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
+               {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
+               {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
+               {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
+               {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
+               {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
+               {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
+               {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
        },
 };
 
@@ -126,10 +126,10 @@ static struct hal_rate_table ar5416_11b_table = {
        4,
        {0},
        {
-               {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
-               {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
-               {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
-               {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
+               {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
+               {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
+               {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
+               {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
        },
 };
 
@@ -137,19 +137,19 @@ static struct hal_rate_table ar5416_11g_table = {
        12,
        {0},
        {
-               {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
-               {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
-               {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
-               {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
-
-               {AH_FALSE, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
-               {AH_FALSE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
-               {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
-               {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
-               {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
-               {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
-               {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
-               {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
+               {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
+               {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
+               {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
+               {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
+
+               {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
+               {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
+               {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
+               {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
+               {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
+               {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
+               {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
+               {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
        },
 };
 
@@ -157,35 +157,35 @@ static struct hal_rate_table ar5416_11ng_table = {
        28,
        {0},
        {
-               {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
-               {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
-               {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
-               {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
-
-               {AH_FALSE, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
-               {AH_FALSE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
-               {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
-               {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
-               {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
-               {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
-               {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
-               {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
-               {AH_TRUE, PHY_HT, 6500, 0x80, 0x00, 0, 4},
-               {AH_TRUE, PHY_HT, 13000, 0x81, 0x00, 1, 6},
-               {AH_TRUE, PHY_HT, 19500, 0x82, 0x00, 2, 6},
-               {AH_TRUE, PHY_HT, 26000, 0x83, 0x00, 3, 8},
-               {AH_TRUE, PHY_HT, 39000, 0x84, 0x00, 4, 8},
-               {AH_TRUE, PHY_HT, 52000, 0x85, 0x00, 5, 8},
-               {AH_TRUE, PHY_HT, 58500, 0x86, 0x00, 6, 8},
-               {AH_TRUE, PHY_HT, 65000, 0x87, 0x00, 7, 8},
-               {AH_TRUE, PHY_HT, 13000, 0x88, 0x00, 8, 4},
-               {AH_TRUE, PHY_HT, 26000, 0x89, 0x00, 9, 6},
-               {AH_TRUE, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
-               {AH_TRUE, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
-               {AH_TRUE, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
-               {AH_TRUE, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
-               {AH_TRUE, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
-               {AH_TRUE, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
+               {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
+               {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
+               {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
+               {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
+
+               {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
+               {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
+               {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
+               {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
+               {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
+               {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
+               {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
+               {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
+               {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
+               {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
+               {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
+               {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
+               {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
+               {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
+               {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
+               {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
+               {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
+               {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
+               {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
+               {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
+               {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
+               {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
+               {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
+               {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
        },
 };
 
@@ -193,30 +193,30 @@ static struct hal_rate_table ar5416_11na_table = {
        24,
        {0},
        {
-               {AH_TRUE, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
-               {AH_TRUE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
-               {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
-               {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
-               {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
-               {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
-               {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
-               {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
-               {AH_TRUE, PHY_HT, 6500, 0x80, 0x00, 0, 0},
-               {AH_TRUE, PHY_HT, 13000, 0x81, 0x00, 1, 2},
-               {AH_TRUE, PHY_HT, 19500, 0x82, 0x00, 2, 2},
-               {AH_TRUE, PHY_HT, 26000, 0x83, 0x00, 3, 4},
-               {AH_TRUE, PHY_HT, 39000, 0x84, 0x00, 4, 4},
-               {AH_TRUE, PHY_HT, 52000, 0x85, 0x00, 5, 4},
-               {AH_TRUE, PHY_HT, 58500, 0x86, 0x00, 6, 4},
-               {AH_TRUE, PHY_HT, 65000, 0x87, 0x00, 7, 4},
-               {AH_TRUE, PHY_HT, 13000, 0x88, 0x00, 8, 0},
-               {AH_TRUE, PHY_HT, 26000, 0x89, 0x00, 9, 2},
-               {AH_TRUE, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
-               {AH_TRUE, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
-               {AH_TRUE, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
-               {AH_TRUE, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
-               {AH_TRUE, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
-               {AH_TRUE, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
+               {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
+               {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
+               {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
+               {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
+               {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
+               {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
+               {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
+               {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
+               {true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
+               {true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
+               {true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
+               {true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
+               {true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
+               {true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
+               {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
+               {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
+               {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
+               {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
+               {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
+               {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
+               {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
+               {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
+               {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
+               {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
        },
 };
 
@@ -230,27 +230,27 @@ static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
        return WIRELESS_MODE_11a;
 }
 
-static enum hal_bool ath9k_hw_wait(struct ath_hal *ah,
-                           u_int reg,
-                           u_int32_t mask,
-                           u_int32_t val)
+static bool ath9k_hw_wait(struct ath_hal *ah,
+                         u_int reg,
+                         u_int32_t mask,
+                         u_int32_t val)
 {
        int i;
 
        for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
                if ((REG_READ(ah, reg) & mask) == val)
-                       return AH_TRUE;
+                       return true;
 
                udelay(AH_TIME_QUANTUM);
        }
-       HDPRINTF(ah, HAL_DBG_PHY_IO,
+       DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
                 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
                 __func__, reg, REG_READ(ah, reg), mask, val);
-       return AH_FALSE;
+       return false;
 }
 
-static enum hal_bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
-                                  u_int16_t *data)
+static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
+                                u_int16_t *data)
 {
        (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
 
@@ -258,13 +258,13 @@ static enum hal_bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
                           AR_EEPROM_STATUS_DATA,
                           AR_EEPROM_STATUS_DATA_BUSY |
                           AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
-               return AH_FALSE;
+               return false;
        }
 
        *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
                   AR_EEPROM_STATUS_DATA_VAL);
 
-       return AH_TRUE;
+       return true;
 }
 
 static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
@@ -274,7 +274,7 @@ static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
        ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
 
        if (!ahp->ah_cal_mem) {
-               HDPRINTF(ah, HAL_DBG_EEPROM,
+               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                         "%s: cannot remap eeprom region \n", __func__);
                return HAL_EIO;
        }
@@ -282,13 +282,13 @@ static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
        return HAL_OK;
 }
 
-static enum hal_bool ath9k_hw_flash_read(struct ath_hal *ah, u_int off,
-                                 u_int16_t *data)
+static bool ath9k_hw_flash_read(struct ath_hal *ah, u_int off,
+                               u_int16_t *data)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
        *data = ioread16(ahp->ah_cal_mem + off);
-       return AH_TRUE;
+       return true;
 }
 
 static void ath9k_hw_read_revisions(struct ath_hal *ah)
@@ -314,7 +314,7 @@ static void ath9k_hw_read_revisions(struct ath_hal *ah)
                ah->ah_macRev = val & AR_SREV_REVISION;
 
                if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
-                       ah->ah_isPciExpress = AH_TRUE;
+                       ah->ah_isPciExpress = true;
        }
 }
 
@@ -368,7 +368,6 @@ static void ath9k_hw_set_defaults(struct ath_hal *ah)
        }
 
        ah->ah_config.ath_hal_intrMitigation = 0;
-       ah->ah_config.ath_hal_debug = 0;
 }
 
 static inline void ath9k_hw_override_ini(struct ath_hal *ah,
@@ -513,9 +512,9 @@ ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
        return HAL_EINVAL;
 }
 
-static inline enum hal_bool ath9k_hw_nvram_read(struct ath_hal *ah,
-                                               u_int off,
-                                               u_int16_t *data)
+static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
+                                      u_int off,
+                                      u_int16_t *data)
 {
        if (ath9k_hw_use_flash(ah))
                return ath9k_hw_flash_read(ah, off, data);
@@ -523,7 +522,7 @@ static inline enum hal_bool ath9k_hw_nvram_read(struct ath_hal *ah,
                return ath9k_hw_eeprom_read(ah, off, data);
 }
 
-static inline enum hal_bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
+static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
        struct ar5416_eeprom *eep = &ahp->ah_eeprom;
@@ -531,7 +530,7 @@ static inline enum hal_bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
        int addr, ar5416_eep_start_loc = 0;
 
        if (!ath9k_hw_use_flash(ah)) {
-               HDPRINTF(ah, HAL_DBG_EEPROM,
+               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                         "%s: Reading from EEPROM, not flash\n", __func__);
                ar5416_eep_start_loc = 256;
        }
@@ -544,18 +543,18 @@ static inline enum hal_bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
             addr++) {
                if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
                                         eep_data)) {
-                       HDPRINTF(ah, HAL_DBG_EEPROM,
+                       DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                                 "%s: Unable to read eeprom region \n",
                                 __func__);
-                       return AH_FALSE;
+                       return false;
                }
                eep_data++;
        }
-       return AH_TRUE;
+       return true;
 }
 
 /* XXX: Clean me up, make me more legible */
-static enum hal_bool
+static bool
 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
                                 struct hal_channel_internal *chan)
 {
@@ -602,33 +601,34 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
 
                if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
                        if ((eep->baseEepHeader.version &
-                       AR5416_EEP_VER_MINOR_MASK) >= AR5416_EEP_MINOR_VER_3) {
+                            AR5416_EEP_VER_MINOR_MASK) >=
+                           AR5416_EEP_MINOR_VER_3) {
                                txRxAttenLocal = pModal->txRxAttenCh[i];
                                if (AR_SREV_9280_10_OR_LATER(ah)) {
-                                       OS_REG_RMW_FIELD(ah,
-                                                AR_PHY_GAIN_2GHZ +
-                                                regChainOffset,
-                                        AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
-                                                pModal->
-                                                bswMargin[i]);
-                                       OS_REG_RMW_FIELD(ah,
-                                                AR_PHY_GAIN_2GHZ +
-                                                regChainOffset,
-                                                AR_PHY_GAIN_2GHZ_XATTEN1_DB,
-                                                pModal->
-                                                bswAtten[i]);
-                                       OS_REG_RMW_FIELD(ah,
-                                                AR_PHY_GAIN_2GHZ +
-                                                regChainOffset,
-                                        AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
-                                                pModal->
-                                                xatten2Margin[i]);
-                                       OS_REG_RMW_FIELD(ah,
-                                                AR_PHY_GAIN_2GHZ +
-                                                regChainOffset,
-                                                AR_PHY_GAIN_2GHZ_XATTEN2_DB,
-                                                pModal->
-                                                xatten2Db[i]);
+                                       REG_RMW_FIELD(ah,
+                                               AR_PHY_GAIN_2GHZ +
+                                               regChainOffset,
+                                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
+                                               pModal->
+                                               bswMargin[i]);
+                                       REG_RMW_FIELD(ah,
+                                               AR_PHY_GAIN_2GHZ +
+                                               regChainOffset,
+                                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
+                                               pModal->
+                                               bswAtten[i]);
+                                       REG_RMW_FIELD(ah,
+                                               AR_PHY_GAIN_2GHZ +
+                                               regChainOffset,
+                                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
+                                               pModal->
+                                               xatten2Margin[i]);
+                                       REG_RMW_FIELD(ah,
+                                               AR_PHY_GAIN_2GHZ +
+                                               regChainOffset,
+                                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
+                                               pModal->
+                                               xatten2Db[i]);
                                } else {
                                        REG_WRITE(ah,
                                                  AR_PHY_GAIN_2GHZ +
@@ -638,8 +638,8 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
                                                            regChainOffset) &
                                                   ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
                                                  | SM(pModal->
-                                              bswMargin[i],
-                                              AR_PHY_GAIN_2GHZ_BSW_MARGIN));
+                                                 bswMargin[i],
+                                                 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
                                        REG_WRITE(ah,
                                                  AR_PHY_GAIN_2GHZ +
                                                  regChainOffset,
@@ -648,20 +648,20 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
                                                            regChainOffset) &
                                                   ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
                                                  | SM(pModal->bswAtten[i],
-                                              AR_PHY_GAIN_2GHZ_BSW_ATTEN));
+                                                 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
                                }
                        }
                        if (AR_SREV_9280_10_OR_LATER(ah)) {
-                               OS_REG_RMW_FIELD(ah,
-                                                AR_PHY_RXGAIN +
-                                                regChainOffset,
-                                                AR9280_PHY_RXGAIN_TXRX_ATTEN,
-                                                txRxAttenLocal);
-                               OS_REG_RMW_FIELD(ah,
-                                                AR_PHY_RXGAIN +
-                                                regChainOffset,
-                                                AR9280_PHY_RXGAIN_TXRX_MARGIN,
-                                                pModal->rxTxMarginCh[i]);
+                               REG_RMW_FIELD(ah,
+                                             AR_PHY_RXGAIN +
+                                             regChainOffset,
+                                             AR9280_PHY_RXGAIN_TXRX_ATTEN,
+                                             txRxAttenLocal);
+                               REG_RMW_FIELD(ah,
+                                             AR_PHY_RXGAIN +
+                                             regChainOffset,
+                                             AR9280_PHY_RXGAIN_TXRX_MARGIN,
+                                             pModal->rxTxMarginCh[i]);
                        } else {
                                REG_WRITE(ah,
                                          AR_PHY_RXGAIN + regChainOffset,
@@ -728,21 +728,21 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
                                          AR_AN_TOP2_LOCALBIAS,
                                          AR_AN_TOP2_LOCALBIAS_S,
                                          pModal->local_bias);
-               HDPRINTF(NULL, HAL_DBG_UNMASKABLE, "ForceXPAon: %d\n",
-                        pModal->force_xpaon);
-               OS_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
-                                pModal->force_xpaon);
+               DPRINTF(ah->ah_sc, ATH_DBG_ANY, "ForceXPAon: %d\n",
+                       pModal->force_xpaon);
+               REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
+                             pModal->force_xpaon);
        }
 
-       OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
-                        pModal->switchSettling);
-       OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
-                        pModal->adcDesiredSize);
+       REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
+                     pModal->switchSettling);
+       REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
+                     pModal->adcDesiredSize);
 
        if (!AR_SREV_9280_10_OR_LATER(ah))
-               OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
-                                AR_PHY_DESIRED_SZ_PGA,
-                                pModal->pgaDesiredSize);
+               REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
+                             AR_PHY_DESIRED_SZ_PGA,
+                             pModal->pgaDesiredSize);
 
        REG_WRITE(ah, AR_PHY_RF_CTL4,
                  SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
@@ -753,40 +753,40 @@ ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
                  | SM(pModal->txFrameToXpaOn,
                       AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 
-       OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
-                        pModal->txEndToRxOn);
+       REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
+                     pModal->txEndToRxOn);
        if (AR_SREV_9280_10_OR_LATER(ah)) {
-               OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
-                                pModal->thresh62);
-               OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
-                                AR_PHY_EXT_CCA0_THRESH62,
-                                pModal->thresh62);
+               REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
+                             pModal->thresh62);
+               REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
+                             AR_PHY_EXT_CCA0_THRESH62,
+                             pModal->thresh62);
        } else {
-               OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
-                                pModal->thresh62);
-               OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
-                                AR_PHY_EXT_CCA_THRESH62,
-                                pModal->thresh62);
+               REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
+                             pModal->thresh62);
+               REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
+                             AR_PHY_EXT_CCA_THRESH62,
+                             pModal->thresh62);
        }
 
        if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
            AR5416_EEP_MINOR_VER_2) {
-               OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
-                                AR_PHY_TX_END_DATA_START,
-                                pModal->txFrameToDataStart);
-               OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
-                                pModal->txFrameToPaOn);
+               REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
+                             AR_PHY_TX_END_DATA_START,
+                             pModal->txFrameToDataStart);
+               REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
+                             pModal->txFrameToPaOn);
        }
 
        if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
            AR5416_EEP_MINOR_VER_3) {
                if (IS_CHAN_HT40(chan))
-                       OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
-                                        AR_PHY_SETTLING_SWITCH,
-                                        pModal->swSettleHt40);
+                       REG_RMW_FIELD(ah, AR_PHY_SETTLING,
+                                     AR_PHY_SETTLING_SWITCH,
+                                     pModal->swSettleHt40);
        }
 
-       return AH_TRUE;
+       return true;
 }
 
 static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
@@ -795,7 +795,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
        u_int16_t *eepdata;
        int i;
        struct ath_hal_5416 *ahp = AH5416(ah);
-       enum hal_bool need_swap = AH_FALSE;
+       bool need_swap = false;
        struct ar5416_eeprom *eep =
                (struct ar5416_eeprom *) &ahp->ah_eeprom;
 
@@ -805,18 +805,18 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 
                if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
                                        &magic)) {
-                       HDPRINTF(ah, HAL_DBG_EEPROM,
+                       DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                                 "%s: Reading Magic # failed\n", __func__);
-                       return AH_FALSE;
+                       return false;
                }
-               HDPRINTF(ah, HAL_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
+               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
                         __func__, magic);
 
                if (magic != AR5416_EEPROM_MAGIC) {
                        magic2 = swab16(magic);
 
                        if (magic2 == AR5416_EEPROM_MAGIC) {
-                               need_swap = AH_TRUE;
+                               need_swap = true;
                                eepdata = (u_int16_t *) (&ahp->ah_eeprom);
 
                                for (addr = 0;
@@ -829,22 +829,22 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
                                        *eepdata = temp;
                                        eepdata++;
 
-                                       HDPRINTF(ah, HAL_DBG_EEPROM_DUMP,
+                                       DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                                                 "0x%04X  ", *eepdata);
                                        if (((addr + 1) % 6) == 0)
-                                               HDPRINTF(ah,
-                                                        HAL_DBG_EEPROM_DUMP,
+                                               DPRINTF(ah->ah_sc,
+                                                        ATH_DBG_EEPROM,
                                                         "\n");
                                }
                        } else {
-                               HDPRINTF(ah, HAL_DBG_EEPROM,
+                               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                                         "Invalid EEPROM Magic. "
                                        "endianness missmatch.\n");
                                return HAL_EEBADSUM;
                        }
                }
        }
-       HDPRINTF(ah, HAL_DBG_EEPROM, "need_swap = %s.\n",
+       DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
                 need_swap ? "True" : "False");
 
        if (need_swap)
@@ -852,7 +852,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
        else
                el = ahp->ah_eeprom.baseEepHeader.length;
 
-       if (el < sizeof(struct ar5416_eeprom))
+       if (el > sizeof(struct ar5416_eeprom))
                el = sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
        else
                el = el / sizeof(u_int16_t);
@@ -866,7 +866,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
                u_int32_t integer, j;
                u_int16_t word;
 
-               HDPRINTF(ah, HAL_DBG_EEPROM,
+               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                         "EEPROM Endianness is not native.. Changing \n");
 
                word = swab16(eep->baseEepHeader.length);
@@ -913,7 +913,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
 
        if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
            ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
-               HDPRINTF(ah, HAL_DBG_EEPROM,
+               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                         "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
                         sum, ar5416_get_eep_ver(ahp));
                return HAL_EEBADSUM;
@@ -922,7 +922,7 @@ static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
        return HAL_OK;
 }
 
-static enum hal_bool ath9k_hw_chip_test(struct ath_hal *ah)
+static bool ath9k_hw_chip_test(struct ath_hal *ah)
 {
        u_int32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
        u_int32_t regHold[2];
@@ -942,11 +942,11 @@ static enum hal_bool ath9k_hw_chip_test(struct ath_hal *ah)
                        REG_WRITE(ah, addr, wrData);
                        rdData = REG_READ(ah, addr);
                        if (rdData != wrData) {
-                               HDPRINTF(ah, HAL_DBG_REG_IO,
+                               DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                                 "%s: address test failed "
                                "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
                                 __func__, addr, wrData, rdData);
-                               return AH_FALSE;
+                               return false;
                        }
                }
                for (j = 0; j < 4; j++) {
@@ -954,17 +954,17 @@ static enum hal_bool ath9k_hw_chip_test(struct ath_hal *ah)
                        REG_WRITE(ah, addr, wrData);
                        rdData = REG_READ(ah, addr);
                        if (wrData != rdData) {
-                               HDPRINTF(ah, HAL_DBG_REG_IO,
+                               DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                                 "%s: address test failed "
                                "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
                                 __func__, addr, wrData, rdData);
-                               return AH_FALSE;
+                               return false;
                        }
                }
                REG_WRITE(ah, regAddr[i], regHold[i]);
        }
        udelay(100);
-       return AH_TRUE;
+       return true;
 }
 
 u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah)
@@ -999,11 +999,11 @@ void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits)
                          REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
 }
 
-enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
-                                    enum hal_capability_type type,
-                                    u_int32_t capability,
-                                    u_int32_t setting,
-                                    enum hal_status *status)
+bool ath9k_hw_setcapability(struct ath_hal *ah,
+                           enum hal_capability_type type,
+                           u_int32_t capability,
+                           u_int32_t setting,
+                           enum hal_status *status)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
        u_int32_t v;
@@ -1016,7 +1016,7 @@ enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
                else
                        ahp->ah_staId1Defaults &=
                                ~AR_STA_ID1_CRPT_MIC_ENABLE;
-               return AH_TRUE;
+               return true;
        case HAL_CAP_DIVERSITY:
                v = REG_READ(ah, AR_PHY_CCK_DETECT);
                if (setting)
@@ -1024,21 +1024,21 @@ enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
                else
                        v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
                REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
-               return AH_TRUE;
+               return true;
        case HAL_CAP_MCAST_KEYSRCH:
                if (setting)
                        ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
                else
                        ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
-               return AH_TRUE;
+               return true;
        case HAL_CAP_TSF_ADJUST:
                if (setting)
                        ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
                else
                        ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
-               return AH_TRUE;
+               return true;
        default:
-               return AH_FALSE;
+               return false;
        }
 }
 
@@ -1054,17 +1054,17 @@ void ath9k_hw_dmaRegDump(struct ath_hal *ah)
                   (AR_MACMISC_MISC_OBS_BUS_1 <<
                    AR_MACMISC_MISC_OBS_BUS_MSB_S)));
 
-       HDPRINTF(ah, HAL_DBG_REG_IO, "Raw DMA Debug values:\n");
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n");
        for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
                if (i % 4 == 0)
-                       HDPRINTF(ah, HAL_DBG_REG_IO, "\n");
+                       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
 
                val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
-               HDPRINTF(ah, HAL_DBG_REG_IO, "%d: %08x ", i, val[i]);
+               DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
        }
 
-       HDPRINTF(ah, HAL_DBG_REG_IO, "\n\n");
-       HDPRINTF(ah, HAL_DBG_REG_IO,
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n");
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                 "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
 
        for (i = 0; i < ATH9K_NUM_QUEUES;
@@ -1079,7 +1079,7 @@ void ath9k_hw_dmaRegDump(struct ath_hal *ah)
                        dcuBase++;
                }
 
-               HDPRINTF(ah, HAL_DBG_REG_IO,
+               DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                         "%2d          %2x      %1x     %2x           %2x\n",
                         i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
                         (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
@@ -1088,29 +1088,30 @@ void ath9k_hw_dmaRegDump(struct ath_hal *ah)
                         (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
        }
 
-       HDPRINTF(ah, HAL_DBG_REG_IO, "\n");
-       HDPRINTF(ah, HAL_DBG_REG_IO,
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                 "qcu_stitch state:   %2x    qcu_fetch state:        %2x\n",
                 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
-       HDPRINTF(ah, HAL_DBG_REG_IO,
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                 "qcu_complete state: %2x    dcu_complete state:     %2x\n",
                 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
-       HDPRINTF(ah, HAL_DBG_REG_IO,
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                 "dcu_arb state:      %2x    dcu_fp state:           %2x\n",
                 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
-       HDPRINTF(ah, HAL_DBG_REG_IO,
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                 "chan_idle_dur:     %3d    chan_idle_dur_valid:     %1d\n",
                 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
-       HDPRINTF(ah, HAL_DBG_REG_IO,
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                 "txfifo_valid_0:      %1d    txfifo_valid_1:          %1d\n",
                 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
-       HDPRINTF(ah, HAL_DBG_REG_IO,
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                 "txfifo_dcu_num_0:   %2d    txfifo_dcu_num_1:       %2d\n",
                 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
 
-       HDPRINTF(ah, HAL_DBG_REG_IO, "pcu observe 0x%x \n",
-                REG_READ(ah, AR_OBS_BUS_1));
-       HDPRINTF(ah, HAL_DBG_REG_IO, "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n",
+               REG_READ(ah, AR_OBS_BUS_1));
+       DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
+               "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
 }
 
 u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
@@ -1127,7 +1128,7 @@ u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
        u_int32_t cc = REG_READ(ah, AR_CCCNT);
 
        if (cycles == 0 || cycles > cc) {
-               HDPRINTF(ah, HAL_DBG_CHANNEL,
+               DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
                         "%s: cycle counter wrap. ExtBusy = 0\n",
                         __func__);
                good = 0;
@@ -1173,7 +1174,8 @@ static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
 }
 
 
-static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid, void *sc,
+static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid,
+                                             struct ath_softc *sc,
                                              void __iomem *mem,
                                              enum hal_status *status)
 {
@@ -1184,7 +1186,7 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid, void *sc,
 
        ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
        if (ahp == NULL) {
-               HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
+               DPRINTF(sc, ATH_DBG_FATAL,
                         "%s: cannot allocate memory for state block\n",
                         __func__);
                *status = HAL_ENOMEM;
@@ -1320,7 +1322,7 @@ static inline enum hal_status ath9k_hw_init_macaddr(struct ath_hal *ah)
                ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
        }
        if (sum == 0 || sum == 0xffff * 3) {
-               HDPRINTF(ah, HAL_DBG_EEPROM,
+               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                         "%s: mac address read failed: %s\n", __func__,
                         print_mac(mac, ahp->ah_macaddr));
                return HAL_EEBADMAC;
@@ -1348,7 +1350,7 @@ static inline int16_t ath9k_hw_interpolate(u_int16_t target,
 }
 
 static inline u_int16_t ath9k_hw_fbin2freq(u_int8_t fbin,
-                                          enum hal_bool is2GHz)
+                                          bool is2GHz)
 {
 
        if (fbin == AR5416_BCHAN_UNUSED)
@@ -1359,14 +1361,14 @@ static inline u_int16_t ath9k_hw_fbin2freq(u_int8_t fbin,
 
 static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
                                               u_int16_t i,
-                                              enum hal_bool is2GHz)
+                                              bool is2GHz)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
        struct ar5416_eeprom *eep =
                (struct ar5416_eeprom *) &ahp->ah_eeprom;
        u_int16_t spur_val = AR_NO_SPUR;
 
-       HDPRINTF(ah, HAL_DBG_ANI,
+       DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                 "Getting spur idx %d is2Ghz. %d val %x\n",
                 i, is2GHz, ah->ah_config.ath_hal_spurChans[i][is2GHz]);
 
@@ -1375,7 +1377,7 @@ static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
                break;
        case SPUR_ENABLE_IOCTL:
                spur_val = ah->ah_config.ath_hal_spurChans[i][is2GHz];
-               HDPRINTF(ah, HAL_DBG_ANI,
+               DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                         "Getting spur val from new loc. %d\n", spur_val);
                break;
        case SPUR_ENABLE_EEPROM:
@@ -1388,12 +1390,12 @@ static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
 
 static inline enum hal_status ath9k_hw_rfattach(struct ath_hal *ah)
 {
-       enum hal_bool rfStatus = AH_FALSE;
+       bool rfStatus = false;
        enum hal_status ecode = HAL_OK;
 
        rfStatus = ath9k_hw_init_rf(ah, &ecode);
        if (!rfStatus) {
-               HDPRINTF(ah, HAL_DBG_RESET,
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET,
                         "%s: RF setup failed, status %u\n", __func__,
                         ecode);
                return ecode;
@@ -1419,7 +1421,7 @@ static enum hal_status ath9k_hw_rf_claim(struct ath_hal *ah)
        case AR_RAD2122_SREV_MAJOR:
                break;
        default:
-               HDPRINTF(ah, HAL_DBG_CHANNEL,
+               DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
                         "%s: 5G Radio Chip Rev 0x%02X is not "
                        "supported by this driver\n",
                         __func__, ah->ah_analog5GhzRev);
@@ -1535,12 +1537,12 @@ static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
        case HAL_M_HOSTAP:
                REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
                          | AR_STA_ID1_KSRCH_MODE);
-               OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
+               REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
                break;
        case HAL_M_IBSS:
                REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
                          | AR_STA_ID1_KSRCH_MODE);
-               OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
+               REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
                break;
        case HAL_M_STA:
        case HAL_M_MONITOR:
@@ -1570,7 +1572,7 @@ ath9k_hw_set_rfmode(struct ath_hal *ah, struct hal_channel *chan)
        REG_WRITE(ah, AR_PHY_MODE, rfMode);
 }
 
-static enum hal_bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
+static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
 {
        u_int32_t rst_flags;
        u_int32_t tmpReg;
@@ -1602,9 +1604,10 @@ static enum hal_bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
 
        REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), 0);
        if (!ath9k_hw_wait(ah, (u_int16_t) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
-               HDPRINTF(ah, HAL_DBG_RESET, "%s: RTC stuck in MAC reset\n",
-                        __func__);
-               return AH_FALSE;
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET,
+                       "%s: RTC stuck in MAC reset\n",
+                       __func__);
+               return false;
        }
 
        if (!AR_SREV_9100(ah))
@@ -1615,10 +1618,10 @@ static enum hal_bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
        if (AR_SREV_9100(ah))
                udelay(50);
 
-       return AH_TRUE;
+       return true;
 }
 
-static inline enum hal_bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
+static inline bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
 {
        REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
                  AR_RTC_FORCE_WAKE_ON_INT);
@@ -1630,9 +1633,9 @@ static inline enum hal_bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
                           AR_RTC_STATUS,
                           AR_RTC_STATUS_M,
                           AR_RTC_STATUS_ON)) {
-               HDPRINTF(ah, HAL_DBG_RESET, "%s: RTC not waking up\n",
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
                         __func__);
-               return AH_FALSE;
+               return false;
        }
 
        ath9k_hw_read_revisions(ah);
@@ -1640,8 +1643,8 @@ static inline enum hal_bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
        return ath9k_hw_set_reset(ah, HAL_RESET_WARM);
 }
 
-static enum hal_bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
-                                           u_int32_t type)
+static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
+                                  u_int32_t type)
 {
        REG_WRITE(ah, AR_RTC_FORCE_WAKE,
                  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
@@ -1655,7 +1658,7 @@ static enum hal_bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
                return ath9k_hw_set_reset(ah, type);
                break;
        default:
-               return AH_FALSE;
+               return false;
        }
 }
 
@@ -1663,7 +1666,7 @@ static inline struct hal_channel_internal *ath9k_hw_check_chan(
                        struct ath_hal *ah, struct hal_channel *chan)
 {
        if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
-               HDPRINTF(ah, HAL_DBG_CHANNEL,
+               DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
                         "%s: invalid channel %u/0x%x; not marked as "
                         "2GHz or 5GHz\n", __func__, chan->channel,
                         chan->channelFlags);
@@ -1675,7 +1678,7 @@ static inline struct hal_channel_internal *ath9k_hw_check_chan(
             ^ IS(chan, CHANNEL_HT20)
             ^ IS(chan, CHANNEL_HT40PLUS)
             ^ IS(chan, CHANNEL_HT40MINUS)) == 0) {
-               HDPRINTF(ah, HAL_DBG_CHANNEL,
+               DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
                         "%s: invalid channel %u/0x%x; not marked as "
                         "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
                         __func__, chan->channel, chan->channelFlags);
@@ -1685,7 +1688,7 @@ static inline struct hal_channel_internal *ath9k_hw_check_chan(
        return ath9k_regd_check_channel(ah, chan);
 }
 
-static inline enum hal_bool
+static inline bool
 ath9k_hw_get_lower_upper_index(u_int8_t target,
                               u_int8_t *pList,
                               u_int16_t listSize,
@@ -1696,25 +1699,25 @@ ath9k_hw_get_lower_upper_index(u_int8_t target,
 
        if (target <= pList[0]) {
                *indexL = *indexR = 0;
-               return AH_TRUE;
+               return true;
        }
        if (target >= pList[listSize - 1]) {
                *indexL = *indexR = (u_int16_t) (listSize - 1);
-               return AH_TRUE;
+               return true;
        }
 
        for (i = 0; i < listSize - 1; i++) {
                if (pList[i] == target) {
                        *indexL = *indexR = i;
-                       return AH_TRUE;
+                       return true;
                }
                if (target < pList[i + 1]) {
                        *indexL = i;
                        *indexR = (u_int16_t) (i + 1);
-                       return AH_FALSE;
+                       return false;
                }
        }
-       return AH_FALSE;
+       return false;
 }
 
 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
@@ -1779,7 +1782,7 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 
        if (nf & 0x100)
                nf = 0 - ((nf ^ 0x1ff) + 1);
-       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                 "NF calibrated [ctl] [chain 0] is %d\n", nf);
        nfarray[0] = nf;
 
@@ -1792,7 +1795,7 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 
        if (nf & 0x100)
                nf = 0 - ((nf ^ 0x1ff) + 1);
-       HDPRINTF(ah, HAL_DBG_NF_CAL,
+       DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
                 "NF calibrated [ctl] [chain 1] is %d\n", nf);
        nfarray[1] = nf;
 
@@ -1801,7 +1804,7 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
                        AR_PHY_CH2_MINCCA_PWR);
                if (nf & 0x100)
                        nf = 0 - ((nf ^ 0x1ff) + 1);
-               HDPRINTF(ah, HAL_DBG_NF_CAL,
+               DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
                         "NF calibrated [ctl] [chain 2] is %d\n", nf);
                nfarray[2] = nf;
        }
@@ -1815,7 +1818,7 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 
        if (nf & 0x100)
                nf = 0 - ((nf ^ 0x1ff) + 1);
-       HDPRINTF(ah, HAL_DBG_NF_CAL,
+       DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
                 "NF calibrated [ext] [chain 0] is %d\n", nf);
        nfarray[3] = nf;
 
@@ -1828,7 +1831,7 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
 
        if (nf & 0x100)
                nf = 0 - ((nf ^ 0x1ff) + 1);
-       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                 "NF calibrated [ext] [chain 1] is %d\n", nf);
        nfarray[4] = nf;
 
@@ -1837,13 +1840,13 @@ static void ar5416GetNoiseFloor(struct ath_hal *ah,
                        AR_PHY_CH2_EXT_MINCCA_PWR);
                if (nf & 0x100)
                        nf = 0 - ((nf ^ 0x1ff) + 1);
-               HDPRINTF(ah, HAL_DBG_NF_CAL,
+               DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
                         "NF calibrated [ext] [chain 2] is %d\n", nf);
                nfarray[5] = nf;
        }
 }
 
-static enum hal_bool
+static bool
 getNoiseFloorThresh(struct ath_hal *ah,
                    const struct hal_channel_internal *chan,
                    int16_t *nft)
@@ -1865,21 +1868,21 @@ getNoiseFloorThresh(struct ath_hal *ah,
                *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
                break;
        default:
-               HDPRINTF(ah, HAL_DBG_CHANNEL,
+               DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
                         "%s: invalid channel flags 0x%x\n", __func__,
                         chan->channelFlags);
-               return AH_FALSE;
+               return false;
        }
-       return AH_TRUE;
+       return true;
 }
 
 static void ath9k_hw_start_nfcal(struct ath_hal *ah)
 {
-       OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
-                      AR_PHY_AGC_CONTROL_ENABLE_NF);
-       OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
-                      AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
-       OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+       REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
+                   AR_PHY_AGC_CONTROL_ENABLE_NF);
+       REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
+                   AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+       REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 }
 
 static void
@@ -1918,11 +1921,11 @@ ath9k_hw_loadnf(struct ath_hal *ah, struct hal_channel_internal *chan)
                }
        }
 
-       OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
-                      AR_PHY_AGC_CONTROL_ENABLE_NF);
-       OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
-                      AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
-       OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+       REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
+                   AR_PHY_AGC_CONTROL_ENABLE_NF);
+       REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
+                   AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+       REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 
        for (j = 0; j < 1000; j++) {
                if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
@@ -1956,7 +1959,7 @@ static int16_t ath9k_hw_getnf(struct ath_hal *ah,
 
        chan->channelFlags &= (~CHANNEL_CW_INT);
        if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "%s: NF did not complete in calibration window\n",
                         __func__);
                nf = 0;
@@ -1967,7 +1970,7 @@ static int16_t ath9k_hw_getnf(struct ath_hal *ah,
                nf = nfarray[0];
                if (getNoiseFloorThresh(ah, chan, &nfThresh)
                    && nf > nfThresh) {
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                                 "%s: noise floor failed detected; "
                                 "detected %d, threshold %d\n", __func__,
                                 nf, nfThresh);
@@ -2001,7 +2004,7 @@ static void ath9k_enable_mib_counters(struct ath_hal *ah)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
-       HDPRINTF(ah, HAL_DBG_ANI, "Enable mib counters\n");
+       DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable mib counters\n");
 
        ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
 
@@ -2018,7 +2021,7 @@ static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
-       HDPRINTF(ah, HAL_DBG_ANI, "Disabling MIB counters\n");
+       DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling MIB counters\n");
 
        REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
 
@@ -2044,7 +2047,7 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
                }
        }
 
-       HDPRINTF(ah, HAL_DBG_ANI,
+       DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                 "No more channel states left. Using channel 0\n");
        return 0;
 }
@@ -2078,10 +2081,11 @@ static void ath9k_hw_ani_attach(struct ath_hal *ah)
                }
        }
        if (ahp->ah_hasHwPhyCounters) {
-               HDPRINTF(ah, HAL_DBG_ANI, "Setting OfdmErrBase = 0x%08x\n",
-                        ahp->ah_ani[0].ofdmPhyErrBase);
-               HDPRINTF(ah, HAL_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
-                        ahp->ah_ani[0].cckPhyErrBase);
+               DPRINTF(ah->ah_sc, ATH_DBG_ANI,
+                       "Setting OfdmErrBase = 0x%08x\n",
+                       ahp->ah_ani[0].ofdmPhyErrBase);
+               DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
+                       ahp->ah_ani[0].cckPhyErrBase);
 
                REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
                REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
@@ -2114,7 +2118,7 @@ static void ath9k_hw_ani_detach(struct ath_hal *ah)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
-       HDPRINTF(ah, HAL_DBG_ANI, "Detaching Ani\n");
+       DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detaching Ani\n");
        if (ahp->ah_hasHwPhyCounters) {
                ath9k_hw_disable_mib_counters(ah);
                REG_WRITE(ah, AR_PHY_ERR_1, 0);
@@ -2123,8 +2127,8 @@ static void ath9k_hw_ani_detach(struct ath_hal *ah)
 }
 
 
-static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
-                                         enum hal_ani_cmd cmd, int param)
+static bool ath9k_hw_ani_control(struct ath_hal *ah,
+                                enum hal_ani_cmd cmd, int param)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
        struct ar5416AniState *aniState = ahp->ah_curani;
@@ -2134,26 +2138,26 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
                u_int level = param;
 
                if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
-                       HDPRINTF(ah, HAL_DBG_ANI,
+                       DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                                 "%s: level out of range (%u > %u)\n",
                                 __func__, level,
                                 (unsigned) ARRAY_SIZE(ahp->
                                                       ah_totalSizeDesired));
-                       return AH_FALSE;
-               }
-
-               OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
-                                AR_PHY_DESIRED_SZ_TOT_DES,
-                                ahp->ah_totalSizeDesired[level]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
-                                AR_PHY_AGC_CTL1_COARSE_LOW,
-                                ahp->ah_coarseLow[level]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
-                                AR_PHY_AGC_CTL1_COARSE_HIGH,
-                                ahp->ah_coarseHigh[level]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
-                                AR_PHY_FIND_SIG_FIRPWR,
-                                ahp->ah_firpwr[level]);
+                       return false;
+               }
+
+               REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
+                             AR_PHY_DESIRED_SZ_TOT_DES,
+                             ahp->ah_totalSizeDesired[level]);
+               REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
+                             AR_PHY_AGC_CTL1_COARSE_LOW,
+                             ahp->ah_coarseLow[level]);
+               REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
+                             AR_PHY_AGC_CTL1_COARSE_HIGH,
+                             ahp->ah_coarseHigh[level]);
+               REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
+                             AR_PHY_FIND_SIG_FIRPWR,
+                             ahp->ah_firpwr[level]);
 
                if (level > aniState->noiseImmunityLevel)
                        ahp->ah_stats.ast_ani_niup++;
@@ -2171,44 +2175,44 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
                const int m2CountThrLow[] = { 63, 48 };
                u_int on = param ? 1 : 0;
 
-               OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
-                                AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
-                                m1ThreshLow[on]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
-                                AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
-                                m2ThreshLow[on]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
-                                AR_PHY_SFCORR_M1_THRESH,
-                                m1Thresh[on]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
-                                AR_PHY_SFCORR_M2_THRESH,
-                                m2Thresh[on]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
-                                AR_PHY_SFCORR_M2COUNT_THR,
-                                m2CountThr[on]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
-                                AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
-                                m2CountThrLow[on]);
-
-               OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-                                AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
-                                m1ThreshLow[on]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-                                AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
-                                m2ThreshLow[on]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-                                AR_PHY_SFCORR_EXT_M1_THRESH,
-                                m1Thresh[on]);
-               OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-                                AR_PHY_SFCORR_EXT_M2_THRESH,
-                                m2Thresh[on]);
+               REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+                             AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
+                             m1ThreshLow[on]);
+               REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+                             AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
+                             m2ThreshLow[on]);
+               REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+                             AR_PHY_SFCORR_M1_THRESH,
+                             m1Thresh[on]);
+               REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+                             AR_PHY_SFCORR_M2_THRESH,
+                             m2Thresh[on]);
+               REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+                             AR_PHY_SFCORR_M2COUNT_THR,
+                             m2CountThr[on]);
+               REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+                             AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
+                             m2CountThrLow[on]);
+
+               REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+                             AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
+                             m1ThreshLow[on]);
+               REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+                             AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
+                             m2ThreshLow[on]);
+               REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+                             AR_PHY_SFCORR_EXT_M1_THRESH,
+                             m1Thresh[on]);
+               REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+                             AR_PHY_SFCORR_EXT_M2_THRESH,
+                             m2Thresh[on]);
 
                if (on)
-                       OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
-                                      AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+                       REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
+                                   AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
                else
-                       OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
-                                      AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+                       REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
+                                   AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 
                if (!on != aniState->ofdmWeakSigDetectOff) {
                        if (on)
@@ -2223,9 +2227,9 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
                const int weakSigThrCck[] = { 8, 6 };
                u_int high = param ? 1 : 0;
 
-               OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
-                                AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
-                                weakSigThrCck[high]);
+               REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
+                             AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
+                             weakSigThrCck[high]);
                if (high != aniState->cckWeakSigThreshold) {
                        if (high)
                                ahp->ah_stats.ast_ani_cckhigh++;
@@ -2240,15 +2244,15 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
                u_int level = param;
 
                if (level >= ARRAY_SIZE(firstep)) {
-                       HDPRINTF(ah, HAL_DBG_ANI,
+                       DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                                 "%s: level out of range (%u > %u)\n",
                                 __func__, level,
-                                (unsigned) ARRAY_SIZE(firstep));
-                       return AH_FALSE;
+                               (unsigned) ARRAY_SIZE(firstep));
+                       return false;
                }
-               OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
-                                AR_PHY_FIND_SIG_FIRSTEP,
-                                firstep[level]);
+               REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
+                             AR_PHY_FIND_SIG_FIRSTEP,
+                             firstep[level]);
                if (level > aniState->firstepLevel)
                        ahp->ah_stats.ast_ani_stepup++;
                else if (level < aniState->firstepLevel)
@@ -2262,16 +2266,16 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
                u_int level = param;
 
                if (level >= ARRAY_SIZE(cycpwrThr1)) {
-                       HDPRINTF(ah, HAL_DBG_ANI,
+                       DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                                 "%s: level out of range (%u > %u)\n",
                                 __func__, level,
                                 (unsigned)
-                                ARRAY_SIZE(cycpwrThr1));
-                       return AH_FALSE;
+                               ARRAY_SIZE(cycpwrThr1));
+                       return false;
                }
-               OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
-                                AR_PHY_TIMING5_CYCPWR_THR1,
-                                cycpwrThr1[level]);
+               REG_RMW_FIELD(ah, AR_PHY_TIMING5,
+                             AR_PHY_TIMING5_CYCPWR_THR1,
+                             cycpwrThr1[level]);
                if (level > aniState->spurImmunityLevel)
                        ahp->ah_stats.ast_ani_spurup++;
                else if (level < aniState->spurImmunityLevel)
@@ -2282,27 +2286,27 @@ static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
        case HAL_ANI_PRESENT:
                break;
        default:
-               HDPRINTF(ah, HAL_DBG_ANI, "%s: invalid cmd %u\n", __func__,
-                        cmd);
-               return AH_FALSE;
+               DPRINTF(ah->ah_sc, ATH_DBG_ANI,
+                       "%s: invalid cmd %u\n", __func__, cmd);
+               return false;
        }
 
-       HDPRINTF(ah, HAL_DBG_ANI, "%s: ANI parameters:\n", __func__);
-       HDPRINTF(ah, HAL_DBG_ANI,
+       DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__);
+       DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
                "ofdmWeakSigDetectOff=%d\n",
                 aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
                 !aniState->ofdmWeakSigDetectOff);
-       HDPRINTF(ah, HAL_DBG_ANI,
+       DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                "cckWeakSigThreshold=%d, "
                "firstepLevel=%d, listenTime=%d\n",
                 aniState->cckWeakSigThreshold, aniState->firstepLevel,
                 aniState->listenTime);
-       HDPRINTF(ah, HAL_DBG_ANI,
+       DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
                 aniState->cycleCount, aniState->ofdmPhyErrCount,
                 aniState->cckPhyErrCount);
-       return AH_TRUE;
+       return true;
 }
 
 static void ath9k_ani_restart(struct ath_hal *ah)
@@ -2319,7 +2323,7 @@ static void ath9k_ani_restart(struct ath_hal *ah)
        if (ahp->ah_hasHwPhyCounters) {
                if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
                        aniState->ofdmPhyErrBase = 0;
-                       HDPRINTF(ah, HAL_DBG_ANI,
+                       DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                                 "OFDM Trigger is too high for hw counters\n");
                } else {
                        aniState->ofdmPhyErrBase =
@@ -2327,13 +2331,13 @@ static void ath9k_ani_restart(struct ath_hal *ah)
                }
                if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
                        aniState->cckPhyErrBase = 0;
-                       HDPRINTF(ah, HAL_DBG_ANI,
+                       DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                                 "CCK Trigger is too high for hw counters\n");
                } else {
                        aniState->cckPhyErrBase =
                                AR_PHY_COUNTMAX - aniState->cckTrigHigh;
                }
-               HDPRINTF(ah, HAL_DBG_ANI,
+               DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                         "%s: Writing ofdmbase=%u   cckbase=%u\n",
                         __func__, aniState->ofdmPhyErrBase,
                         aniState->cckPhyErrBase);
@@ -2363,16 +2367,14 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
 
        if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
                if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
-                                        aniState->noiseImmunityLevel +
-                                        1) == AH_TRUE) {
+                                        aniState->noiseImmunityLevel + 1)) {
                        return;
                }
        }
 
        if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
                if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
-                                        aniState->spurImmunityLevel +
-                                        1) == AH_TRUE) {
+                                        aniState->spurImmunityLevel + 1)) {
                        return;
                }
        }
@@ -2389,7 +2391,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
                if (!aniState->ofdmWeakSigDetectOff) {
                        if (ath9k_hw_ani_control(ah,
                                         HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-                                        AH_FALSE) == AH_TRUE) {
+                                        false)) {
                                ath9k_hw_ani_control(ah,
                                        HAL_ANI_SPUR_IMMUNITY_LEVEL,
                                        0);
@@ -2405,7 +2407,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
                if (aniState->ofdmWeakSigDetectOff)
                        ath9k_hw_ani_control(ah,
                                             HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-                                            AH_TRUE);
+                                            true);
                if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
                        ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
                                             aniState->firstepLevel + 1);
@@ -2416,7 +2418,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
                        if (!aniState->ofdmWeakSigDetectOff)
                                ath9k_hw_ani_control(ah,
                                             HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-                                            AH_FALSE);
+                                            false);
                        if (aniState->firstepLevel > 0)
                                ath9k_hw_ani_control(ah,
                                                     HAL_ANI_FIRSTEP_LEVEL,
@@ -2440,8 +2442,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
        aniState = ahp->ah_curani;
        if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
                if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
-                                        aniState->noiseImmunityLevel +
-                                        1) == AH_TRUE) {
+                                        aniState->noiseImmunityLevel + 1)) {
                        return;
                }
        }
@@ -2484,7 +2485,7 @@ static void ath9k_ani_reset(struct ath_hal *ah)
 
        if (DO_ANI(ah) && ah->ah_opmode != HAL_M_STA
            && ah->ah_opmode != HAL_M_IBSS) {
-               HDPRINTF(ah, HAL_DBG_ANI,
+               DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                         "%s: Reset ANI state opmode %u\n", __func__,
                         ah->ah_opmode);
                ahp->ah_stats.ast_ani_reset++;
@@ -2551,7 +2552,7 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
        struct ath_hal_5416 *ahp = AH5416(ah);
        u_int32_t phyCnt1, phyCnt2;
 
-       HDPRINTF(ah, HAL_DBG_ANI, "Processing Mib Intr\n");
+       DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
 
        REG_WRITE(ah, AR_FILT_OFDM, 0);
        REG_WRITE(ah, AR_FILT_CCK, 0);
@@ -2601,8 +2602,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
        if (ah->ah_opmode == HAL_M_HOSTAP) {
                if (aniState->firstepLevel > 0) {
                        if (ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
-                                                aniState->firstepLevel -
-                                                1) == AH_TRUE) {
+                                                aniState->firstepLevel - 1)) {
                                return;
                        }
                }
@@ -2614,8 +2614,8 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
                        if (aniState->ofdmWeakSigDetectOff) {
                                if (ath9k_hw_ani_control(ah,
                                         HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
-                                        AH_TRUE) ==
-                                   AH_TRUE) {
+                                        true) ==
+                                   true) {
                                        return;
                                }
                        }
@@ -2623,7 +2623,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
                                if (ath9k_hw_ani_control
                                    (ah, HAL_ANI_FIRSTEP_LEVEL,
                                     aniState->firstepLevel - 1) ==
-                                   AH_TRUE) {
+                                   true) {
                                        return;
                                }
                        }
@@ -2632,7 +2632,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
                                if (ath9k_hw_ani_control
                                    (ah, HAL_ANI_FIRSTEP_LEVEL,
                                     aniState->firstepLevel - 1) ==
-                                   AH_TRUE) {
+                                   true) {
                                        return;
                                }
                        }
@@ -2641,8 +2641,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
 
        if (aniState->spurImmunityLevel > 0) {
                if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
-                                        aniState->spurImmunityLevel -
-                                        1) == AH_TRUE) {
+                                        aniState->spurImmunityLevel - 1)) {
                        return;
                }
        }
@@ -2715,7 +2714,7 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
                if (phyCnt1 < aniState->ofdmPhyErrBase ||
                    phyCnt2 < aniState->cckPhyErrBase) {
                        if (phyCnt1 < aniState->ofdmPhyErrBase) {
-                               HDPRINTF(ah, HAL_DBG_ANI,
+                               DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                                         "%s: phyCnt1 0x%x, resetting "
                                         "counter value to 0x%x\n",
                                         __func__, phyCnt1,
@@ -2726,7 +2725,7 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
                                          AR_PHY_ERR_OFDM_TIMING);
                        }
                        if (phyCnt2 < aniState->cckPhyErrBase) {
-                               HDPRINTF(ah, HAL_DBG_ANI,
+                               DPRINTF(ah->ah_sc, ATH_DBG_ANI,
                                         "%s: phyCnt2 0x%x, resetting "
                                         "counter value to 0x%x\n",
                                         __func__, phyCnt2,
@@ -2810,8 +2809,8 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
 
        if (AR_SREV_9280_20_OR_LATER(ah)
            || (addr != AR_GPIO_OUTPUT_MUX1)) {
-               OS_REG_RMW(ah, addr, (type << gpio_shift),
-                          (0x1f << gpio_shift));
+               REG_RMW(ah, addr, (type << gpio_shift),
+                       (0x1f << gpio_shift));
        } else {
                tmp = REG_READ(ah, addr);
                tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
@@ -2821,9 +2820,9 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
        }
 }
 
-static enum hal_bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
-                                 enum hal_gpio_output_mux_type
-                                 halSignalType)
+static bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
+                               enum hal_gpio_output_mux_type
+                               halSignalType)
 {
        u_int32_t ah_signal_type;
        u_int32_t gpio_shift;
@@ -2845,26 +2844,26 @@ static enum hal_bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
            && (halSignalType < ARRAY_SIZE(MuxSignalConversionTable)))
                ah_signal_type = MuxSignalConversionTable[halSignalType];
        else
-               return AH_FALSE;
+               return false;
 
        ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
 
        gpio_shift = 2 * gpio;
 
-       OS_REG_RMW(ah,
-                  AR_GPIO_OE_OUT,
-                  (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
-                  (AR_GPIO_OE_OUT_DRV << gpio_shift));
+       REG_RMW(ah,
+               AR_GPIO_OE_OUT,
+               (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
+               (AR_GPIO_OE_OUT_DRV << gpio_shift));
 
-       return AH_TRUE;
+       return true;
 }
 
-static enum hal_bool ath9k_hw_set_gpio(struct ath_hal *ah, u_int32_t gpio,
-                               u_int32_t val)
+static bool ath9k_hw_set_gpio(struct ath_hal *ah, u_int32_t gpio,
+                             u_int32_t val)
 {
-       OS_REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
-                  AR_GPIO_BIT(gpio));
-       return AH_TRUE;
+       REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
+               AR_GPIO_BIT(gpio));
+       return true;
 }
 
 static u_int32_t ath9k_hw_gpio_get(struct ath_hal *ah, u_int32_t gpio)
@@ -2887,7 +2886,7 @@ static inline enum hal_status ath9k_hw_post_attach(struct ath_hal *ah)
        enum hal_status ecode;
 
        if (!ath9k_hw_chip_test(ah)) {
-               HDPRINTF(ah, HAL_DBG_REG_IO,
+               DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                         "%s: hardware self-test failed\n", __func__);
                return HAL_ESELFTEST;
        }
@@ -2919,23 +2918,23 @@ static u_int32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
        switch (ah->ah_devid) {
        case AR9280_DEVID_PCI:
                if (reg == 0x7894) {
-                       HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_ANY,
                                 "ini VAL: %x  EEPROM: %x\n", value,
                                 (pBase->version & 0xff));
 
                        if ((pBase->version & 0xff) > 0x0a) {
-                               HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
+                               DPRINTF(ah->ah_sc, ATH_DBG_ANY,
                                         "PWDCLKIND: %d\n",
                                         pBase->pwdclkind);
                                value &= ~AR_AN_TOP2_PWDCLKIND;
                                value |= AR_AN_TOP2_PWDCLKIND & (pBase->
                                         pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
                        } else {
-                               HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
+                               DPRINTF(ah->ah_sc, ATH_DBG_ANY,
                                         "PWDCLKIND Earlier Rev\n");
                        }
 
-                       HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_ANY,
                                 "final ini VAL: %x\n", value);
                }
                break;
@@ -2943,7 +2942,7 @@ static u_int32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
        return value;
 }
 
-static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
+static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
        struct hal_capabilities *pCap = &ah->ah_caps;
@@ -2964,7 +2963,7 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
                        ah->ah_currentRD += 5;
                else if (ah->ah_currentRD == 0x41)
                        ah->ah_currentRD = 0x43;
-               HDPRINTF(ah, HAL_DBG_REGULATORY,
+               DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
                         "%s: regdomain mapped to 0x%x\n", __func__,
                         ah->ah_currentRD);
        }
@@ -3011,22 +3010,22 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
        pCap->halLow5GhzChan = 4920;
        pCap->halHigh5GhzChan = 6100;
 
-       pCap->halCipherCkipSupport = AH_FALSE;
-       pCap->halCipherTkipSupport = AH_TRUE;
-       pCap->halCipherAesCcmSupport = AH_TRUE;
+       pCap->halCipherCkipSupport = false;
+       pCap->halCipherTkipSupport = true;
+       pCap->halCipherAesCcmSupport = true;
 
-       pCap->halMicCkipSupport = AH_FALSE;
-       pCap->halMicTkipSupport = AH_TRUE;
-       pCap->halMicAesCcmSupport = AH_TRUE;
+       pCap->halMicCkipSupport = false;
+       pCap->halMicTkipSupport = true;
+       pCap->halMicAesCcmSupport = true;
 
-       pCap->halChanSpreadSupport = AH_TRUE;
+       pCap->halChanSpreadSupport = true;
 
        pCap->halHTSupport =
-               ah->ah_config.ath_hal_htEnable ? AH_TRUE : AH_FALSE;
-       pCap->halGTTSupport = AH_TRUE;
-       pCap->halVEOLSupport = AH_TRUE;
-       pCap->halBssIdMaskSupport = AH_TRUE;
-       pCap->halMcastKeySrchSupport = AH_FALSE;
+               ah->ah_config.ath_hal_htEnable ? true : false;
+       pCap->halGTTSupport = true;
+       pCap->halVEOLSupport = true;
+       pCap->halBssIdMaskSupport = true;
+       pCap->halMcastKeySrchSupport = false;
 
        if (capField & AR_EEPROM_EEPCAP_MAXQCU)
                pCap->halTotalQueues =
@@ -3040,7 +3039,7 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
        else
                pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
 
-       pCap->halFastCCSupport = AH_TRUE;
+       pCap->halFastCCSupport = true;
        pCap->halNumMRRetries = 4;
        pCap->halTxTrigLevelMax = MAX_TX_FIFO_THRESHOLD;
 
@@ -3050,21 +3049,21 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
                pCap->halNumGpioPins = AR_NUM_GPIO;
 
        if (AR_SREV_9280_10_OR_LATER(ah)) {
-               pCap->halWowSupport = AH_TRUE;
-               pCap->halWowMatchPatternExact = AH_TRUE;
+               pCap->halWowSupport = true;
+               pCap->halWowMatchPatternExact = true;
        } else {
-               pCap->halWowSupport = AH_FALSE;
-               pCap->halWowMatchPatternExact = AH_FALSE;
+               pCap->halWowSupport = false;
+               pCap->halWowMatchPatternExact = false;
        }
 
        if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
-               pCap->halCSTSupport = AH_TRUE;
+               pCap->halCSTSupport = true;
                pCap->halRtsAggrLimit = ATH_AMPDU_LIMIT_MAX;
        } else {
                pCap->halRtsAggrLimit = (8 * 1024);
        }
 
-       pCap->halEnhancedPmSupport = AH_TRUE;
+       pCap->halEnhancedPmSupport = true;
 
        ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
        if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
@@ -3073,9 +3072,9 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
                ahp->ah_polarity =
                        MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
 
-               ath9k_hw_setcapability(ah, HAL_CAP_RFSILENT, 1, AH_TRUE,
+               ath9k_hw_setcapability(ah, HAL_CAP_RFSILENT, 1, true,
                                       NULL);
-               pCap->halRfSilentSupport = AH_TRUE;
+               pCap->halRfSilentSupport = true;
        }
 
        if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
@@ -3083,14 +3082,14 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
            (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
            (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
            (ah->ah_macVersion == AR_SREV_VERSION_9280))
-               pCap->halAutoSleepSupport = AH_FALSE;
+               pCap->halAutoSleepSupport = false;
        else
-               pCap->halAutoSleepSupport = AH_TRUE;
+               pCap->halAutoSleepSupport = true;
 
        if (AR_SREV_9280(ah))
-               pCap->hal4kbSplitTransSupport = AH_FALSE;
+               pCap->hal4kbSplitTransSupport = false;
        else
-               pCap->hal4kbSplitTransSupport = AH_TRUE;
+               pCap->hal4kbSplitTransSupport = true;
 
        if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
                pCap->halRegCap =
@@ -3111,7 +3110,7 @@ static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
        pCap->halNumAntCfg2GHz =
                ath9k_hw_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ);
 
-       return AH_TRUE;
+       return true;
 }
 
 static void ar5416DisablePciePhy(struct ath_hal *ah)
@@ -3134,21 +3133,21 @@ static void ar5416DisablePciePhy(struct ath_hal *ah)
 
 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
 {
-       OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+       REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
        if (setChip) {
-               OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
-                              AR_RTC_FORCE_WAKE_EN);
+               REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
+                           AR_RTC_FORCE_WAKE_EN);
                if (!AR_SREV_9100(ah))
                        REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
 
-               OS_REG_CLR_BIT(ah, (u_int16_t) (AR_RTC_RESET),
-                              AR_RTC_RESET_EN);
+               REG_CLR_BIT(ah, (u_int16_t) (AR_RTC_RESET),
+                           AR_RTC_RESET_EN);
        }
 }
 
 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
 {
-       OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+       REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
        if (setChip) {
                struct hal_capabilities *pCap = &ah->ah_caps;
 
@@ -3156,14 +3155,14 @@ static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
                        REG_WRITE(ah, AR_RTC_FORCE_WAKE,
                                  AR_RTC_FORCE_WAKE_ON_INT);
                } else {
-                       OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
-                                      AR_RTC_FORCE_WAKE_EN);
+                       REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
+                                   AR_RTC_FORCE_WAKE_EN);
                }
        }
 }
 
-static enum hal_bool ath9k_hw_set_power_awake(struct ath_hal *ah,
-                                             int setChip)
+static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
+                                    int setChip)
 {
        u_int32_t val;
        int i;
@@ -3172,16 +3171,16 @@ static enum hal_bool ath9k_hw_set_power_awake(struct ath_hal *ah,
                if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
                    AR_RTC_STATUS_SHUTDOWN) {
                        if (ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)
-                           != AH_TRUE) {
-                               return AH_FALSE;
+                           != true) {
+                               return false;
                        }
                }
                if (AR_SREV_9100(ah))
-                       OS_REG_SET_BIT(ah, AR_RTC_RESET,
+                       REG_SET_BIT(ah, AR_RTC_RESET,
                                       AR_RTC_RESET_EN);
 
-               OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
-                              AR_RTC_FORCE_WAKE_EN);
+               REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
+                           AR_RTC_FORCE_WAKE_EN);
                udelay(50);
 
                for (i = POWER_UP_TIME / 50; i > 0; i--) {
@@ -3189,23 +3188,23 @@ static enum hal_bool ath9k_hw_set_power_awake(struct ath_hal *ah,
                        if (val == AR_RTC_STATUS_ON)
                                break;
                        udelay(50);
-                       OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
+                       REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
                                       AR_RTC_FORCE_WAKE_EN);
                }
                if (i == 0) {
-                       HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+                       DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
                                 "%s: Failed to wakeup in %uus\n",
                                 __func__, POWER_UP_TIME / 20);
-                       return AH_FALSE;
+                       return false;
                }
        }
 
-       OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
-       return AH_TRUE;
+       REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+       return true;
 }
 
-enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
-                               enum hal_power_mode mode)
+bool ath9k_hw_setpower(struct ath_hal *ah,
+                      enum hal_power_mode mode)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
        static const char *modes[] = {
@@ -3214,9 +3213,9 @@ enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
                "NETWORK SLEEP",
                "UNDEFINED"
        };
-       int status = AH_TRUE, setChip = AH_TRUE;
+       int status = true, setChip = true;
 
-       HDPRINTF(ah, HAL_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
+       DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
                 modes[ahp->ah_powerMode], modes[mode],
                 setChip ? "set chip " : "");
 
@@ -3226,21 +3225,22 @@ enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
                break;
        case HAL_PM_FULL_SLEEP:
                ath9k_set_power_sleep(ah, setChip);
-               ahp->ah_chipFullSleep = AH_TRUE;
+               ahp->ah_chipFullSleep = true;
                break;
        case HAL_PM_NETWORK_SLEEP:
                ath9k_set_power_network_sleep(ah, setChip);
                break;
        default:
-               HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+               DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
                         "%s: unknown power mode %u\n", __func__, mode);
-               return AH_FALSE;
+               return false;
        }
        ahp->ah_powerMode = mode;
        return status;
 }
 
-static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
+static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid,
+                                         struct ath_softc *sc,
                                          void __iomem *mem,
                                          enum hal_status *status)
 {
@@ -3261,17 +3261,17 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
        ath9k_hw_set_defaults(ah);
 
        if (ah->ah_config.ath_hal_intrMitigation != 0)
-               ahp->ah_intrMitigation = AH_TRUE;
+               ahp->ah_intrMitigation = true;
 
        if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)) {
-               HDPRINTF(ah, HAL_DBG_RESET, "%s: couldn't reset chip\n",
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
                         __func__);
                ecode = HAL_EIO;
                goto bad;
        }
 
        if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE)) {
-               HDPRINTF(ah, HAL_DBG_RESET, "%s: couldn't wakeup chip\n",
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
                         __func__);
                ecode = HAL_EIO;
                goto bad;
@@ -3286,14 +3286,15 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
                                SER_REG_MODE_OFF;
                }
        }
-       HDPRINTF(ah, HAL_DBG_RESET, "%s: ath_hal_serializeRegMode is %d\n",
-                __func__, ah->ah_config.ath_hal_serializeRegMode);
+       DPRINTF(ah->ah_sc, ATH_DBG_RESET,
+               "%s: ath_hal_serializeRegMode is %d\n",
+               __func__, ah->ah_config.ath_hal_serializeRegMode);
 
        if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
            (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
            (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
            (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
-               HDPRINTF(ah, HAL_DBG_RESET,
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET,
                         "%s: Mac Chip Rev 0x%02x.%x is not supported by "
                         "this driver\n", __func__,
                         ah->ah_macVersion, ah->ah_macRev);
@@ -3304,7 +3305,7 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
        if (AR_SREV_9100(ah)) {
                ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
                ahp->ah_suppCals = IQ_MISMATCH_CAL;
-               ah->ah_isPciExpress = AH_FALSE;
+               ah->ah_isPciExpress = false;
        }
        ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 
@@ -3342,7 +3343,7 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
                }
        }
 
-       HDPRINTF(ah, HAL_DBG_RESET,
+       DPRINTF(ah->ah_sc, ATH_DBG_RESET,
                 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
                 ah->ah_macVersion, ah->ah_macRev);
 
@@ -3477,7 +3478,7 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
 #endif
 
        if (!ath9k_hw_fill_cap_info(ah)) {
-               HDPRINTF(ah, HAL_DBG_RESET,
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET,
                         "%s:failed ath9k_hw_fill_cap_info\n", __func__);
                ecode = HAL_EEREAD;
                goto bad;
@@ -3485,7 +3486,7 @@ static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
 
        ecode = ath9k_hw_init_macaddr(ah);
        if (ecode != HAL_OK) {
-               HDPRINTF(ah, HAL_DBG_RESET,
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET,
                         "%s: failed initializing mac address\n",
                         __func__);
                goto bad;
@@ -3521,33 +3522,33 @@ void ath9k_hw_detach(struct ath_hal *ah)
        kfree(ah);
 }
 
-enum hal_bool ath9k_get_channel_edges(struct ath_hal *ah,
-                                     u_int16_t flags, u_int16_t *low,
-                                     u_int16_t *high)
+bool ath9k_get_channel_edges(struct ath_hal *ah,
+                            u_int16_t flags, u_int16_t *low,
+                            u_int16_t *high)
 {
        struct hal_capabilities *pCap = &ah->ah_caps;
 
        if (flags & CHANNEL_5GHZ) {
                *low = pCap->halLow5GhzChan;
                *high = pCap->halHigh5GhzChan;
-               return AH_TRUE;
+               return true;
        }
        if ((flags & CHANNEL_2GHZ)) {
                *low = pCap->halLow2GhzChan;
                *high = pCap->halHigh2GhzChan;
 
-               return AH_TRUE;
+               return true;
        }
-       return AH_FALSE;
+       return false;
 }
 
-static inline enum hal_bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
-                                                   u_int8_t pwrMax,
-                                                   u_int8_t *pPwrList,
-                                                   u_int8_t *pVpdList,
-                                                   u_int16_t
-                                                   numIntercepts,
-                                                   u_int8_t *pRetVpdList)
+static inline bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
+                                          u_int8_t pwrMax,
+                                          u_int8_t *pPwrList,
+                                          u_int8_t *pVpdList,
+                                          u_int16_t
+                                          numIntercepts,
+                                          u_int8_t *pRetVpdList)
 {
        u_int16_t i, k;
        u_int8_t currPwr = pwrMin;
@@ -3575,7 +3576,7 @@ static inline enum hal_bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
                currPwr += 2;
        }
 
-       return AH_TRUE;
+       return true;
 }
 
 static inline void
@@ -3606,7 +3607,7 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
        int16_t vpdStep;
        int16_t tmpVal;
        u_int16_t sizeCurrVpdTable, maxIndex, tgtIndex;
-       enum hal_bool match;
+       bool match;
        int16_t minDelta = 0;
        struct chan_centers centers;
 
@@ -3760,7 +3761,7 @@ ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
        return;
 }
 
-static inline enum hal_bool
+static inline bool
 ath9k_hw_set_power_cal_table(struct ath_hal *ah,
                             struct ar5416_eeprom *pEepData,
                             struct hal_channel_internal *chan,
@@ -3814,14 +3815,14 @@ ath9k_hw_set_power_cal_table(struct ath_hal *ah,
                }
        }
 
-       OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
-                        (numXpdGain - 1) & 0x3);
-       OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
-                        xpdGainValues[0]);
-       OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
-                        xpdGainValues[1]);
-       OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
-                        xpdGainValues[2]);
+       REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
+                     (numXpdGain - 1) & 0x3);
+       REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
+                     xpdGainValues[0]);
+       REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
+                     xpdGainValues[1]);
+       REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
+                     xpdGainValues[2]);
 
        for (i = 0; i < AR5416_MAX_CHAINS; i++) {
                if (AR_SREV_5416_V20_OR_LATER(ah) &&
@@ -3874,11 +3875,11 @@ ath9k_hw_set_power_cal_table(struct ath_hal *ah,
                                         24);
                                REG_WRITE(ah, regOffset, reg32);
 
-                               HDPRINTF(ah, HAL_DBG_PHY_IO,
+                               DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
                                         i, regChainOffset, regOffset,
                                         reg32);
-                               HDPRINTF(ah, HAL_DBG_PHY_IO,
+                               DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
                                "PDADC: Chain %d | PDADC %3d Value %3d | "
                                "PDADC %3d Value %3d | PDADC %3d Value %3d | "
                                "PDADC %3d Value %3d |\n",
@@ -3894,7 +3895,7 @@ ath9k_hw_set_power_cal_table(struct ath_hal *ah,
        }
        *pTxPowerIndexOffset = 0;
 
-       return AH_TRUE;
+       return true;
 }
 
 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
@@ -3902,7 +3903,7 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
        struct ath_hal_5416 *ahp = AH5416(ah);
        u_int8_t i;
 
-       if (ah->ah_isPciExpress != AH_TRUE)
+       if (ah->ah_isPciExpress != true)
                return;
 
        if (ah->ah_config.ath_hal_pciePowerSaveEnable == 2)
@@ -3951,7 +3952,7 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
                REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
        }
 
-       OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 
        if (ah->ah_config.ath_hal_pcieWaen) {
                REG_WRITE(ah, AR_WA, ah->ah_config.ath_hal_pcieWaen);
@@ -3970,7 +3971,7 @@ ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
                                  u_int16_t numChannels,
                                  struct cal_target_power_leg *pNewPower,
                                  u_int16_t numRates,
-                                 enum hal_bool isExtTarget)
+                                 bool isExtTarget)
 {
        u_int16_t clo, chi;
        int i;
@@ -4036,7 +4037,7 @@ ath9k_hw_get_target_powers(struct ath_hal *ah,
                           u_int16_t numChannels,
                           struct cal_target_power_ht *pNewPower,
                           u_int16_t numRates,
-                          enum hal_bool isHt40Target)
+                          bool isHt40Target)
 {
        u_int16_t clo, chi;
        int i;
@@ -4099,7 +4100,7 @@ ath9k_hw_get_target_powers(struct ath_hal *ah,
 static inline u_int16_t
 ath9k_hw_get_max_edge_power(u_int16_t freq,
                            struct cal_ctl_edges *pRdEdgesPower,
-                           enum hal_bool is2GHz)
+                           bool is2GHz)
 {
        u_int16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
        int i;
@@ -4126,7 +4127,7 @@ ath9k_hw_get_max_edge_power(u_int16_t freq,
        return twiceMaxEdgePower;
 }
 
-static inline enum hal_bool
+static inline bool
 ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
                                  struct ar5416_eeprom *pEepData,
                                  struct hal_channel_internal *chan,
@@ -4220,17 +4221,17 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
                        calTargetPowerCck,
                        AR5416_NUM_2G_CCK_TARGET_POWERS,
                        &targetPowerCck, 4,
-                       AH_FALSE);
+                       false);
                ath9k_hw_get_legacy_target_powers(ah, chan,
                        pEepData->
                        calTargetPower2G,
                        AR5416_NUM_2G_20_TARGET_POWERS,
                        &targetPowerOfdm, 4,
-                       AH_FALSE);
+                       false);
                ath9k_hw_get_target_powers(ah, chan,
                        pEepData->calTargetPower2GHT20,
                        AR5416_NUM_2G_20_TARGET_POWERS,
-                       &targetPowerHt20, 8, AH_FALSE);
+                       &targetPowerHt20, 8, false);
 
                if (IS_CHAN_HT40(chan)) {
                        numCtlModes = ARRAY_SIZE(ctlModesFor11g);
@@ -4239,19 +4240,19 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
                                calTargetPower2GHT40,
                                AR5416_NUM_2G_40_TARGET_POWERS,
                                &targetPowerHt40, 8,
-                               AH_TRUE);
+                               true);
                        ath9k_hw_get_legacy_target_powers(ah, chan,
                                pEepData->
                                calTargetPowerCck,
                                AR5416_NUM_2G_CCK_TARGET_POWERS,
                                &targetPowerCckExt,
-                               4, AH_TRUE);
+                               4, true);
                        ath9k_hw_get_legacy_target_powers(ah, chan,
                                pEepData->
                                calTargetPower2G,
                                AR5416_NUM_2G_20_TARGET_POWERS,
                                &targetPowerOfdmExt,
-                               4, AH_TRUE);
+                               4, true);
                }
        } else {
 
@@ -4265,11 +4266,11 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
                        calTargetPower5G,
                        AR5416_NUM_5G_20_TARGET_POWERS,
                        &targetPowerOfdm, 4,
-                       AH_FALSE);
+                       false);
                ath9k_hw_get_target_powers(ah, chan,
                        pEepData->calTargetPower5GHT20,
                        AR5416_NUM_5G_20_TARGET_POWERS,
-                       &targetPowerHt20, 8, AH_FALSE);
+                       &targetPowerHt20, 8, false);
 
                if (IS_CHAN_HT40(chan)) {
                        numCtlModes = ARRAY_SIZE(ctlModesFor11a);
@@ -4278,18 +4279,18 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
                                calTargetPower5GHT40,
                                AR5416_NUM_5G_40_TARGET_POWERS,
                                &targetPowerHt40, 8,
-                               AH_TRUE);
+                               true);
                        ath9k_hw_get_legacy_target_powers(ah, chan,
                                pEepData->
                                calTargetPower5G,
                                AR5416_NUM_5G_20_TARGET_POWERS,
                                &targetPowerOfdmExt,
-                               4, AH_TRUE);
+                               4, true);
                }
        }
 
        for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
-               enum hal_bool isHt40CtlMode =
+               bool isHt40CtlMode =
                        (pCtlMode[ctlMode] == CTL_5GHT40)
                        || (pCtlMode[ctlMode] == CTL_2GHT40);
                if (isHt40CtlMode)
@@ -4303,7 +4304,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
                    && ar5416_get_eep_rev(ahp) <= 2)
                        twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 
-               HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+               DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
                        "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
                        "EXT_ADDITIVE %d\n",
                         ctlMode, numCtlModes, isHt40CtlMode,
@@ -4311,7 +4312,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 
                for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
                     i++) {
-                       HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+                       DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
                                 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
                                "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
                                "chan %d chanctl 0x%x\n",
@@ -4339,7 +4340,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
                                                IS_CHAN_2GHZ
                                                (chan));
 
-                               HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+                               DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
                                        "    MATCH-EE_IDX %d: ch %d is2 %d "
                                        "2xMinEdge %d chainmask %d chains %d\n",
                                         i, freq, IS_CHAN_2GHZ(chan),
@@ -4360,7 +4361,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
 
                minCtlPower = min(twiceMaxEdgePower, scaledPower);
 
-               HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+               DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
                                "    SEL-Min ctlMode %d pCtlMode %d "
                                "2xMaxEdge %d sP %d minCtlPwr %d\n",
                         ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
@@ -4451,7 +4452,7 @@ ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
                                targetPowerCckExt.tPow2x[0];
                }
        }
-       return AH_TRUE;
+       return true;
 }
 
 static enum hal_status
@@ -4483,7 +4484,7 @@ ath9k_hw_set_txpower(struct ath_hal *ah,
                                               twiceAntennaReduction,
                                               twiceMaxRegulatoryPower,
                                               powerLimit)) {
-               HDPRINTF(ah, HAL_DBG_EEPROM,
+               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                        "ath9k_hw_set_txpower: unable to set "
                        "tx power per rate table\n");
                return HAL_EIO;
@@ -4491,7 +4492,7 @@ ath9k_hw_set_txpower(struct ath_hal *ah,
 
        if (!ath9k_hw_set_power_cal_table
            (ah, pEepData, chan, &txPowerIndexOffset)) {
-               HDPRINTF(ah, HAL_DBG_EEPROM,
+               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                         "ath9k_hw_set_txpower: unable to set power table\n");
                return HAL_EIO;
        }
@@ -4637,20 +4638,20 @@ ath9k_hw_set_delta_slope(struct ath_hal *ah,
        ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
                                      &ds_coef_exp);
 
-       OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
-                        AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
-       OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
-                        AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING3,
+                     AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING3,
+                     AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 
        coef_scaled = (9 * coef_scaled) / 10;
 
        ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
                                      &ds_coef_exp);
 
-       OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
-                        AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
-       OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
-                        AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
+       REG_RMW_FIELD(ah, AR_PHY_HALFGI,
+                     AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
+       REG_RMW_FIELD(ah, AR_PHY_HALFGI,
+                     AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
 }
 
 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
@@ -4681,7 +4682,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
        int8_t mask_amt;
        int tmp_mask;
        int cur_bb_spur;
-       enum hal_bool is2GHz = IS_CHAN_2GHZ(chan);
+       bool is2GHz = IS_CHAN_2GHZ(chan);
 
        memset(&mask_m, 0, sizeof(int8_t) * 123);
        memset(&mask_p, 0, sizeof(int8_t) * 123);
@@ -4716,12 +4717,12 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
        }
 
        if (AR_NO_SPUR == bb_spur) {
-               OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
-                              AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+               REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
+                           AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
                return;
        } else {
-               OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
-                              AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
+               REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
+                           AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
        }
 
        bin = bb_spur * 320;
@@ -4925,7 +4926,7 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
        int8_t mask_amt;
        int tmp_mask;
        int cur_bb_spur;
-       enum hal_bool is2GHz = IS_CHAN_2GHZ(chan);
+       bool is2GHz = IS_CHAN_2GHZ(chan);
 
        memset(&mask_m, 0, sizeof(int8_t) * 123);
        memset(&mask_p, 0, sizeof(int8_t) * 123);
@@ -5109,8 +5110,8 @@ static inline void ath9k_hw_init_chain_masks(struct ath_hal *ah)
 
        switch (rx_chainmask) {
        case 0x5:
-               OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
-                              AR_PHY_SWAP_ALT_CHAIN);
+               REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
+                           AR_PHY_SWAP_ALT_CHAIN);
        case 0x3:
                if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
                        REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
@@ -5131,8 +5132,8 @@ static inline void ath9k_hw_init_chain_masks(struct ath_hal *ah)
 
        REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
        if (tx_chainmask == 0x5) {
-               OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
-                              AR_PHY_SWAP_ALT_CHAIN);
+               REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
+                           AR_PHY_SWAP_ALT_CHAIN);
        }
        if (AR_SREV_9100(ah))
                REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
@@ -5241,69 +5242,69 @@ static u_int ath9k_hw_mac_to_clks(struct ath_hal *ah, u_int usecs)
                return ath9k_hw_mac_clks(ah, usecs);
 }
 
-static enum hal_bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u_int us)
+static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u_int us)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
        if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
-               HDPRINTF(ah, HAL_DBG_RESET, "%s: bad ack timeout %u\n",
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
                         __func__, us);
                ahp->ah_acktimeout = (u_int) -1;
-               return AH_FALSE;
+               return false;
        } else {
-               OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
-                                AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
+               REG_RMW_FIELD(ah, AR_TIME_OUT,
+                             AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
                ahp->ah_acktimeout = us;
-               return AH_TRUE;
+               return true;
        }
 }
 
-static enum hal_bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u_int us)
+static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u_int us)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
        if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
-               HDPRINTF(ah, HAL_DBG_RESET, "%s: bad cts timeout %u\n",
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
                         __func__, us);
                ahp->ah_ctstimeout = (u_int) -1;
-               return AH_FALSE;
+               return false;
        } else {
-               OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
-                                AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
+               REG_RMW_FIELD(ah, AR_TIME_OUT,
+                             AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
                ahp->ah_ctstimeout = us;
-               return AH_TRUE;
+               return true;
        }
 }
-static enum hal_bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
-                                                  u_int tu)
+static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
+                                         u_int tu)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
        if (tu > 0xFFFF) {
-               HDPRINTF(ah, HAL_DBG_TX, "%s: bad global tx timeout %u\n",
-                        __func__, tu);
+               DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
+                       "%s: bad global tx timeout %u\n", __func__, tu);
                ahp->ah_globaltxtimeout = (u_int) -1;
-               return AH_FALSE;
+               return false;
        } else {
-               OS_REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
+               REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
                ahp->ah_globaltxtimeout = tu;
-               return AH_TRUE;
+               return true;
        }
 }
 
-enum hal_bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us)
+bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
        if (us < HAL_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
-               HDPRINTF(ah, HAL_DBG_RESET, "%s: bad slot time %u\n",
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
                         __func__, us);
                ahp->ah_slottime = (u_int) -1;
-               return AH_FALSE;
+               return false;
        } else {
                REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
                ahp->ah_slottime = us;
-               return AH_TRUE;
+               return true;
        }
 }
 
@@ -5311,7 +5312,7 @@ static inline void ath9k_hw_init_user_settings(struct ath_hal *ah)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
-       HDPRINTF(ah, HAL_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
+       DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
                 __func__, ahp->ah_miscMode);
        if (ahp->ah_miscMode != 0)
                REG_WRITE(ah, AR_PCU_MISC,
@@ -5444,13 +5445,13 @@ ath9k_hw_process_ini(struct ath_hal *ah,
                                      min((u_int32_t) MAX_RATE_POWER,
                                          (u_int32_t) ah->ah_powerLimit));
        if (status != HAL_OK) {
-               HDPRINTF(ah, HAL_DBG_POWER_MGMT,
+               DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
                         "%s: error init'ing transmit power\n", __func__);
                return HAL_EIO;
        }
 
        if (!ath9k_hw_set_rf_regs(ah, ichan, freqIndex)) {
-               HDPRINTF(ah, HAL_DBG_REG_IO,
+               DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
                         "%s: ar5416SetRfRegs failed\n", __func__);
                return HAL_EIO;
        }
@@ -5461,37 +5462,37 @@ ath9k_hw_process_ini(struct ath_hal *ah,
 static inline void ath9k_hw_setup_calibration(struct ath_hal *ah,
                                              struct hal_cal_list *currCal)
 {
-       OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
-                        AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
-                        currCal->calData->calCountMax);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
+                     AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
+                     currCal->calData->calCountMax);
 
        switch (currCal->calData->calType) {
        case IQ_MISMATCH_CAL:
                REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "%s: starting IQ Mismatch Calibration\n",
                         __func__);
                break;
        case ADC_GAIN_CAL:
                REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "%s: starting ADC Gain Calibration\n", __func__);
                break;
        case ADC_DC_CAL:
                REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "%s: starting ADC DC Calibration\n", __func__);
                break;
        case ADC_DC_INIT_CAL:
                REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "%s: starting Init ADC DC Calibration\n",
                         __func__);
                break;
        }
 
-       OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
-                      AR_PHY_TIMING_CTRL4_DO_CAL);
+       REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
+                   AR_PHY_TIMING_CTRL4_DO_CAL);
 }
 
 static inline void ath9k_hw_reset_calibration(struct ath_hal *ah,
@@ -5519,11 +5520,11 @@ ath9k_hw_per_calibration(struct ath_hal *ah,
                         struct hal_channel_internal *ichan,
                         u_int8_t rxchainmask,
                         struct hal_cal_list *currCal,
-                        enum hal_bool *isCalDone)
+                        bool *isCalDone)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
-       *isCalDone = AH_FALSE;
+       *isCalDone = false;
 
        if (currCal->calState == CAL_RUNNING) {
                if (!(REG_READ(ah,
@@ -5548,7 +5549,7 @@ ath9k_hw_per_calibration(struct ath_hal *ah,
                                ichan->CalValid |=
                                        currCal->calData->calType;
                                currCal->calState = CAL_DONE;
-                               *isCalDone = AH_TRUE;
+                               *isCalDone = true;
                        } else {
                                ath9k_hw_setup_calibration(ah, currCal);
                        }
@@ -5558,18 +5559,18 @@ ath9k_hw_per_calibration(struct ath_hal *ah,
        }
 }
 
-static inline enum hal_bool ath9k_hw_run_init_cals(struct ath_hal *ah,
-                                                  int init_cal_count)
+static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah,
+                                         int init_cal_count)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
        struct hal_channel_internal ichan;
-       enum hal_bool isCalDone;
+       bool isCalDone;
        struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
        const struct hal_percal_data *calData = currCal->calData;
        int i;
 
        if (currCal == NULL)
-               return AH_FALSE;
+               return false;
 
        ichan.CalValid = 0;
 
@@ -5578,19 +5579,19 @@ static inline enum hal_bool ath9k_hw_run_init_cals(struct ath_hal *ah,
 
                if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0),
                                   AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                                 "%s: Cal %d failed to complete in 100ms.\n",
                                 __func__, calData->calType);
 
                        ahp->ah_cal_list = ahp->ah_cal_list_last =
                                ahp->ah_cal_list_curr = NULL;
-                       return AH_FALSE;
+                       return false;
                }
 
                ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask,
                                         currCal, &isCalDone);
-               if (isCalDone == AH_FALSE) {
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               if (!isCalDone) {
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                                 "%s: Not able to run Init Cal %d.\n",
                                 __func__, calData->calType);
                }
@@ -5601,10 +5602,10 @@ static inline enum hal_bool ath9k_hw_run_init_cals(struct ath_hal *ah,
        }
 
        ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
-       return AH_TRUE;
+       return true;
 }
 
-static inline enum hal_bool
+static inline bool
 ath9k_hw_channel_change(struct ath_hal *ah,
                        struct hal_channel *chan,
                        struct hal_channel_internal *ichan,
@@ -5615,34 +5616,34 @@ ath9k_hw_channel_change(struct ath_hal *ah,
 
        for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
                if (ath9k_hw_numtxpending(ah, qnum)) {
-                       HDPRINTF(ah, HAL_DBG_QUEUE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
                                 "%s: Transmit frames pending on queue %d\n",
                                 __func__, qnum);
-                       return AH_FALSE;
+                       return false;
                }
        }
 
        REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
        if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
                           AR_PHY_RFBUS_GRANT_EN)) {
-               HDPRINTF(ah, HAL_DBG_PHY_IO,
+               DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
                         "%s: Could not kill baseband RX\n", __func__);
-               return AH_FALSE;
+               return false;
        }
 
        ath9k_hw_set_regs(ah, chan, macmode);
 
        if (AR_SREV_9280_10_OR_LATER(ah)) {
                if (!(ath9k_hw_ar9280_set_channel(ah, ichan))) {
-                       HDPRINTF(ah, HAL_DBG_CHANNEL,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
                                 "%s: failed to set channel\n", __func__);
-                       return AH_FALSE;
+                       return false;
                }
        } else {
                if (!(ath9k_hw_set_channel(ah, ichan))) {
-                       HDPRINTF(ah, HAL_DBG_CHANNEL,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
                                 "%s: failed to set channel\n", __func__);
-                       return AH_FALSE;
+                       return false;
                }
        }
 
@@ -5653,9 +5654,9 @@ ath9k_hw_channel_change(struct ath_hal *ah,
                                 min((u_int32_t) MAX_RATE_POWER,
                                     (u_int32_t) ah->ah_powerLimit))
            != HAL_OK) {
-               HDPRINTF(ah, HAL_DBG_EEPROM,
+               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                         "%s: error init'ing transmit power\n", __func__);
-               return AH_FALSE;
+               return false;
        }
 
        synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
@@ -5677,29 +5678,29 @@ ath9k_hw_channel_change(struct ath_hal *ah,
                ath9k_hw_spur_mitigate(ah, chan);
 
        if (!ichan->oneTimeCalsDone)
-               ichan->oneTimeCalsDone = AH_TRUE;
+               ichan->oneTimeCalsDone = true;
 
-       return AH_TRUE;
+       return true;
 }
 
-static enum hal_bool ath9k_hw_chip_reset(struct ath_hal *ah,
-                                        struct hal_channel *chan)
+static bool ath9k_hw_chip_reset(struct ath_hal *ah,
+                               struct hal_channel *chan)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
 
        if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM))
-               return AH_FALSE;
+               return false;
 
        if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
-               return AH_FALSE;
+               return false;
 
-       ahp->ah_chipFullSleep = AH_FALSE;
+       ahp->ah_chipFullSleep = false;
 
        ath9k_hw_init_pll(ah, chan);
 
        ath9k_hw_set_rfmode(ah, chan);
 
-       return AH_TRUE;
+       return true;
 }
 
 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
@@ -5712,7 +5713,7 @@ static inline void ath9k_hw_set_dma(struct ath_hal *ah)
        regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
        REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 
-       OS_REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
+       REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
 
        regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
        REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
@@ -5728,24 +5729,25 @@ static inline void ath9k_hw_set_dma(struct ath_hal *ah)
        }
 }
 
-enum hal_bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
+bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
 {
        REG_WRITE(ah, AR_CR, AR_CR_RXD);
        if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
-               HDPRINTF(ah, HAL_DBG_RX, "%s: dma failed to stop in 10ms\n"
-                        "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
-                        __func__,
-                        REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
-               return AH_FALSE;
+               DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
+                       "%s: dma failed to stop in 10ms\n"
+                       "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
+                       __func__,
+                       REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
+               return false;
        } else {
-               return AH_TRUE;
+               return true;
        }
 }
 
 void ath9k_hw_startpcureceive(struct ath_hal *ah)
 {
-       OS_REG_CLR_BIT(ah, AR_DIAG_SW,
-                      (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
+       REG_CLR_BIT(ah, AR_DIAG_SW,
+                   (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 
        ath9k_enable_mib_counters(ah);
 
@@ -5754,36 +5756,36 @@ void ath9k_hw_startpcureceive(struct ath_hal *ah)
 
 void ath9k_hw_stoppcurecv(struct ath_hal *ah)
 {
-       OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
+       REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
 
        ath9k_hw_disable_mib_counters(ah);
 }
 
-static enum hal_bool ath9k_hw_iscal_supported(struct ath_hal *ah,
-                                             struct hal_channel *chan,
-                                             enum hal_cal_types calType)
+static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
+                                    struct hal_channel *chan,
+                                    enum hal_cal_types calType)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
-       enum hal_bool retval = AH_FALSE;
+       bool retval = false;
 
        switch (calType & ahp->ah_suppCals) {
        case IQ_MISMATCH_CAL:
                if (!IS_CHAN_B(chan))
-                       retval = AH_TRUE;
+                       retval = true;
                break;
        case ADC_GAIN_CAL:
        case ADC_DC_CAL:
                if (!IS_CHAN_B(chan)
                    && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
-                       retval = AH_TRUE;
+                       retval = true;
                break;
        }
 
        return retval;
 }
 
-static inline enum hal_bool ath9k_hw_init_cal(struct ath_hal *ah,
-                                             struct hal_channel *chan)
+static inline bool ath9k_hw_init_cal(struct ath_hal *ah,
+                                    struct hal_channel *chan)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
        struct hal_channel_internal *ichan =
@@ -5795,10 +5797,10 @@ static inline enum hal_bool ath9k_hw_init_cal(struct ath_hal *ah,
 
        if (!ath9k_hw_wait
            (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "%s: offset calibration failed to complete in 1ms; "
                         "noisy environment?\n", __func__);
-               return AH_FALSE;
+               return false;
        }
 
        REG_WRITE(ah, AR_PHY_AGC_CONTROL,
@@ -5809,27 +5811,24 @@ static inline enum hal_bool ath9k_hw_init_cal(struct ath_hal *ah,
                NULL;
 
        if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
-               if (AH_TRUE ==
-                   ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
+               if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
                        INIT_CAL(&ahp->ah_adcGainCalData);
                        INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                                 "%s: enabling ADC Gain Calibration.\n",
                                 __func__);
                }
-               if (AH_TRUE ==
-                   ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
+               if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
                        INIT_CAL(&ahp->ah_adcDcCalData);
                        INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                                 "%s: enabling ADC DC Calibration.\n",
                                 __func__);
                }
-               if (AH_TRUE ==
-                   ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
+               if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
                        INIT_CAL(&ahp->ah_iqCalData);
                        INSERT_CAL(ahp, &ahp->ah_iqCalData);
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                                 "%s: enabling IQ Calibration.\n",
                                 __func__);
                }
@@ -5843,17 +5842,17 @@ static inline enum hal_bool ath9k_hw_init_cal(struct ath_hal *ah,
 
        ichan->CalValid = 0;
 
-       return AH_TRUE;
+       return true;
 }
 
 
-enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
-                            struct hal_channel *chan,
-                            enum hal_ht_macmode macmode,
-                            u_int8_t txchainmask, u_int8_t rxchainmask,
-                            enum hal_ht_extprotspacing extprotspacing,
-                            enum hal_bool bChannelChange,
-                            enum hal_status *status)
+bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
+                   struct hal_channel *chan,
+                   enum hal_ht_macmode macmode,
+                   u_int8_t txchainmask, u_int8_t rxchainmask,
+                   enum hal_ht_extprotspacing extprotspacing,
+                   bool bChannelChange,
+                   enum hal_status *status)
 {
 #define FAIL(_code)     do { ecode = _code; goto bad; } while (0)
        u_int32_t saveLedState;
@@ -5876,20 +5875,20 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 
        ichan = ath9k_hw_check_chan(ah, chan);
        if (ichan == NULL) {
-               HDPRINTF(ah, HAL_DBG_CHANNEL,
+               DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
                         "%s: invalid channel %u/0x%x; no mapping\n",
                         __func__, chan->channel, chan->channelFlags);
                FAIL(HAL_EINVAL);
        }
 
        if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
-               return AH_FALSE;
+               return false;
 
        if (curchan)
                ath9k_hw_getnf(ah, curchan);
 
        if (bChannelChange &&
-           (ahp->ah_chipFullSleep != AH_TRUE) &&
+           (ahp->ah_chipFullSleep != true) &&
            (ah->ah_curchan != NULL) &&
            (chan->channel != ah->ah_curchan->channel) &&
            ((chan->channelFlags & CHANNEL_ALL) ==
@@ -5906,7 +5905,7 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 
                        ath9k_hw_start_nfcal(ah);
 
-                       return AH_TRUE;
+                       return true;
                }
        }
 
@@ -5923,14 +5922,14 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
        ath9k_hw_mark_phy_inactive(ah);
 
        if (!ath9k_hw_chip_reset(ah, chan)) {
-               HDPRINTF(ah, HAL_DBG_RESET, "%s: chip reset failed\n",
+               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
                         __func__);
                FAIL(HAL_EIO);
        }
 
        if (AR_SREV_9280(ah)) {
-               OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-                              AR_GPIO_JTAG_DISABLE);
+               REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
+                           AR_GPIO_JTAG_DISABLE);
 
                if (ah->ah_caps.halWirelessModes & ATH9K_MODE_SEL_11A) {
                        if (IS_CHAN_5GHZ(chan))
@@ -5954,7 +5953,7 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
                ath9k_hw_spur_mitigate(ah, chan);
 
        if (!ath9k_hw_eeprom_set_board_values(ah, ichan)) {
-               HDPRINTF(ah, HAL_DBG_EEPROM,
+               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
                         "%s: error setting board options\n", __func__);
                FAIL(HAL_EIO);
        }
@@ -6014,8 +6013,8 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
 
        if (ahp->ah_intrMitigation) {
 
-               OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
-               OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
+               REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
+               REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
        }
 
        ath9k_hw_init_bb(ah, chan);
@@ -6035,14 +6034,14 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
                u_int32_t mask;
                mask = REG_READ(ah, AR_CFG);
                if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
-                       HDPRINTF(ah, HAL_DBG_RESET,
+                       DPRINTF(ah->ah_sc, ATH_DBG_RESET,
                                 "%s CFG Byte Swap Set 0x%x\n", __func__,
                                 mask);
                } else {
                        mask =
                                INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
                        REG_WRITE(ah, AR_CFG, mask);
-                       HDPRINTF(ah, HAL_DBG_RESET,
+                       DPRINTF(ah->ah_sc, ATH_DBG_RESET,
                                 "%s Setting CFG 0x%x\n", __func__,
                                 REG_READ(ah, AR_CFG));
                }
@@ -6053,44 +6052,44 @@ enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
        }
        chan->channelFlags = ichan->channelFlags;
        chan->privFlags = ichan->privFlags;
-       return AH_TRUE;
+       return true;
 bad:
        if (status)
                *status = ecode;
-       return AH_FALSE;
+       return false;
 #undef FAIL
 }
 
-enum hal_bool ath9k_hw_phy_disable(struct ath_hal *ah)
+bool ath9k_hw_phy_disable(struct ath_hal *ah)
 {
        return ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM);
 }
 
-enum hal_bool ath9k_hw_disable(struct ath_hal *ah)
+bool ath9k_hw_disable(struct ath_hal *ah)
 {
        if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
-               return AH_FALSE;
+               return false;
 
        return ath9k_hw_set_reset_reg(ah, HAL_RESET_COLD);
 }
 
-enum hal_bool
+bool
 ath9k_hw_calibrate(struct ath_hal *ah, struct hal_channel *chan,
-                  u_int8_t rxchainmask, enum hal_bool longcal,
-                  enum hal_bool *isCalDone)
+                  u_int8_t rxchainmask, bool longcal,
+                  bool *isCalDone)
 {
        struct ath_hal_5416 *ahp = AH5416(ah);
        struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
        struct hal_channel_internal *ichan =
                ath9k_regd_check_channel(ah, chan);
 
-       *isCalDone = AH_TRUE;
+       *isCalDone = true;
 
        if (ichan == NULL) {
-               HDPRINTF(ah, HAL_DBG_CHANNEL,
+               DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
                         "%s: invalid channel %u/0x%x; no mapping\n",
                         __func__, chan->channel, chan->channelFlags);
-               return AH_FALSE;
+               return false;
        }
 
        if (currCal &&
@@ -6098,11 +6097,11 @@ ath9k_hw_calibrate(struct ath_hal *ah, struct hal_channel *chan,
             currCal->calState == CAL_WAITING)) {
                ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
                                         isCalDone);
-               if (*isCalDone == AH_TRUE) {
+               if (*isCalDone) {
                        ahp->ah_cal_list_curr = currCal = currCal->calNext;
 
                        if (currCal->calState == CAL_WAITING) {
-                               *isCalDone = AH_FALSE;
+                               *isCalDone = false;
                                ath9k_hw_reset_calibration(ah, currCal);
                        }
                }
@@ -6120,7 +6119,7 @@ ath9k_hw_calibrate(struct ath_hal *ah, struct hal_channel *chan,
                }
        }
 
-       return AH_TRUE;
+       return true;
 }
 
 static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
@@ -6135,7 +6134,7 @@ static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
                        REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
                ahp->ah_totalIqCorrMeas[i] +=
                        (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
                         ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
                         ahp->ah_totalPowerMeasQ[i],
@@ -6158,7 +6157,7 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
                ahp->ah_totalAdcQEvenPhase[i] +=
                        REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                        "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
                        "oddq=0x%08x; evenq=0x%08x;\n",
                         ahp->ah_CalSamples, i,
@@ -6184,7 +6183,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
                ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
                        (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                        "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
                        "oddq=0x%08x; evenq=0x%08x;\n",
                         ahp->ah_CalSamples, i,
@@ -6208,11 +6207,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
                powerMeasQ = ahp->ah_totalPowerMeasQ[i];
                iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
 
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "Starting IQ Cal and Correction for Chain %d\n",
                         i);
 
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "Orignal: Chn %diq_corr_meas = 0x%08x\n",
                         i, ahp->ah_totalIqCorrMeas[i]);
 
@@ -6224,11 +6223,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
                        iqCorrNeg = 1;
                }
 
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
-               HDPRINTF(ah, HAL_DBG_CALIBRATE,
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                         "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
-               HDPRINTF(ah, HAL_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
+               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
                         iqCorrNeg);
 
                iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
@@ -6238,14 +6237,14 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
 
                        iCoff = iqCorrMeas / iCoffDenom;
                        qCoff = powerMeasI / qCoffDenom - 64;
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                                 "Chn %d iCoff = 0x%08x\n", i, iCoff);
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                                 "Chn %d qCoff = 0x%08x\n", i, qCoff);
 
 
                        iCoff = iCoff & 0x3f;
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                                 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
                        if (iqCorrNeg == 0x0)
                                iCoff = 0x40 - iCoff;
@@ -6255,24 +6254,24 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
                        else if (qCoff <= -16)
                                qCoff = 16;
 
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
                                 "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
-                                i, iCoff, qCoff);
+                               i, iCoff, qCoff);
 
-                       OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
-                                        AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
-                                        iCoff);
-                       OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
-                                        AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
-                                        qCoff);
-                       HDPRINTF(ah, HAL_DBG_CALIBRATE,
-                                "IQ Cal and Correction done for Chain %d\n",
-                                i);
+                       REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
+                                     AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
+                                     iCoff);
+                       REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
+                                     AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
+                                     qCoff);
+                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                               "IQ Cal and Correction done for Chain %d\n",
+                               i);
                }
        }
 
-       OS_REG_SET_BIT(ah, AR_PHY_TIM