ar71xx: add support for 3.8
authorGabor Juhos <juhosg@openwrt.org>
Thu, 21 Feb 2013 17:47:15 +0000 (17:47 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Thu, 21 Feb 2013 17:47:15 +0000 (17:47 +0000)
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 35728

101 files changed:
target/linux/ar71xx/config-3.8 [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/143-MIPS-pci-ar724x-convert-to-a-platform-driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/144-MIPS-pci-ar71xx-convert-to-a-platform-driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/146-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/147-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/148-MIPS-avoid-possible-resource-conflict-in-register_pc.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/149-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/150-MIPS-pci-ar724x-remove-static-PCI-resources.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/151-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/152-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/153-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/154-MIPS-pci-ar71xx-remove-static-PCI-controller-resourc.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/169-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/171-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/172-MIPS-ath79-add-support-for-the-QCA9556-SoC.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/200-spi-ath79-add-delay-between-SCK-changes.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/201-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/202-spi-ath79-remove-superfluous-chip-select-code.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/203-spi-ath79-use-gpio_request_one.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/204-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/205-spi-ath79-add-shutdown-handler.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/206-spi-ath79-make-chipselect-logic-more-flexible.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/210-MIPS-ath79-simplify-misc-irq-handling.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/213-MIPS-ath79-fix-ar933x-wmac-reset.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/220-add_cpu_feature_overrides.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/310-lib-add-rle-decompression.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/401-mtd-physmap-add-lock-unlock.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/402-mtd-SST39VF6401B-support.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/403-mtd_fix_cfi_cmdset_0002_status_check.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/404-mtd-wrt160nl-trx-parser.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/405-mtd-tp-link-partition-parser.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/406-mtd-m25p80-allow-to-specify-max-read-size.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/408-mtd-redboot_partition_scan.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/409-mtd-rb4xx_nand_driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/410-mtd-rb750-nand-driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/411-mtd-cfi_cmdset_0002-force-word-write.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/412-mtd-m25p80-zero-partition-parser-data.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/413-mtd-ar934x-nand-driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/420-net-ar71xx_mac_driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/422-dsa-trailer-tag-validation-fix.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/423-dsa-add-88e6063-driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/430-drivers-link-spi-before-mtd.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/431-spi-add-various-flags.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/432-spi-rb4xx-spi-driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/433-spi-rb4xx-cpld-driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/434-spi-ap83_spi_controller.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/435-spi-vsc7385_driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/440-leds-wndr3700-usb-led-driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/441-leds-rb750-led-driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/450-gpio-nxp-74hc153-gpio-chip-driver.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/460-spi-bitbang-export-spi_bitbang_bufs.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/461-spi-add-type-field-to-spi_transfer.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/462-mtd-m25p80-set-spi-transfer-type.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/463-spi-ath79-add-fast-flash-read.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/500-MIPS-fw-myloader.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/502-MIPS-ath79-export-ath79_gpio_base.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/503-MIPS-ath79-add-flash-acquire-release.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/504-MIPS-ath79-add-ath79_device_reset_get.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/505-MIPS-ath79-add-ath79_gpio_function_select.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/506-MIPS-ath79-prom-parse-redboot-args.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/507-MIPS-ath79-prom-add-myloader-support.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/508-MIPS-ath79-prom-image-command-line-hack.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/509-MIPS-ath79-process-board-kernel-option.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/520-MIPS-ath79-enable-UART-function.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/521-MIPS-ath79-enable-UART-for-early_serial.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/523-MIPS-ath79-OTP-support.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/602-MIPS-ath79-add-openwrt-stuff.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/603-MIPS-ath79-ap121-fixes.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/604-MIPS-ath79-ap81-fixes.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/605-MIPS-ath79-db120-fixes.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/606-MIPS-ath79-pb44-fixes.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/607-MIPS-ath79-ubnt-xm-fixes.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/608-MIPS-ath79-ubnt-xm-add-more-boards.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/610-MIPS-ath79-openwrt-machines.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/611-MIPS-ath79-add-QCA9556-SoC-on-AP132.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/612-MIPS-ath79-add-DIR-825-C1-support.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/613-MIPS-ath79-add-TL-WDR3500-support.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/614-MIPS-ath79-MR600v2-support.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/615-MIPS-ath79-RB951G-support.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/901-mdio_bitbang_ignore_ta_value.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.8/902-unaligned_access_hacks.patch [new file with mode: 0644]

diff --git a/target/linux/ar71xx/config-3.8 b/target/linux/ar71xx/config-3.8
new file mode 100644 (file)
index 0000000..847b9a5
--- /dev/null
@@ -0,0 +1,260 @@
+CONFIG_AG71XX=y
+CONFIG_AG71XX_AR8216_SUPPORT=y
+# CONFIG_AG71XX_DEBUG is not set
+# CONFIG_AG71XX_DEBUG_FS is not set
+CONFIG_AR8216_PHY=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ATH79=y
+CONFIG_ATH79_DEV_AP9X_PCI=y
+CONFIG_ATH79_DEV_DSA=y
+CONFIG_ATH79_DEV_ETH=y
+CONFIG_ATH79_DEV_GPIO_BUTTONS=y
+CONFIG_ATH79_DEV_LEDS_GPIO=y
+CONFIG_ATH79_DEV_M25P80=y
+CONFIG_ATH79_DEV_NFC=y
+CONFIG_ATH79_DEV_SPI=y
+CONFIG_ATH79_DEV_USB=y
+CONFIG_ATH79_DEV_WMAC=y
+CONFIG_ATH79_MACH_ALFA_AP96=y
+CONFIG_ATH79_MACH_ALFA_NX=y
+CONFIG_ATH79_MACH_ALL0258N=y
+CONFIG_ATH79_MACH_ALL0315N=y
+CONFIG_ATH79_MACH_AP113=y
+CONFIG_ATH79_MACH_AP121=y
+CONFIG_ATH79_MACH_AP132=y
+CONFIG_ATH79_MACH_AP136=y
+CONFIG_ATH79_MACH_AP81=y
+CONFIG_ATH79_MACH_AP83=y
+CONFIG_ATH79_MACH_AP96=y
+CONFIG_ATH79_MACH_AW_NR580=y
+CONFIG_ATH79_MACH_CAP4200AG=y
+CONFIG_ATH79_MACH_DB120=y
+CONFIG_ATH79_MACH_DIR_600_A1=y
+CONFIG_ATH79_MACH_DIR_615_C1=y
+CONFIG_ATH79_MACH_DIR_825_B1=y
+CONFIG_ATH79_MACH_DIR_825_C1=y
+CONFIG_ATH79_MACH_EAP7660D=y
+CONFIG_ATH79_MACH_EW_DORIN=y
+CONFIG_ATH79_MACH_HORNET_UB=y
+CONFIG_ATH79_MACH_JA76PF=y
+CONFIG_ATH79_MACH_JWAP003=y
+CONFIG_ATH79_MACH_MR600=y
+CONFIG_ATH79_MACH_MZK_W04NU=y
+CONFIG_ATH79_MACH_MZK_W300NH=y
+CONFIG_ATH79_MACH_NBG460N=y
+CONFIG_ATH79_MACH_OM2P=y
+CONFIG_ATH79_MACH_PB42=y
+CONFIG_ATH79_MACH_PB44=y
+CONFIG_ATH79_MACH_PB92=y
+CONFIG_ATH79_MACH_RB2011=y
+CONFIG_ATH79_MACH_RB4XX=y
+CONFIG_ATH79_MACH_RB750=y
+CONFIG_ATH79_MACH_RB95X=y
+CONFIG_ATH79_MACH_RW2458N=y
+CONFIG_ATH79_MACH_TEW_632BRP=y
+CONFIG_ATH79_MACH_TEW_673GRU=y
+CONFIG_ATH79_MACH_TEW_712BR=y
+CONFIG_ATH79_MACH_TL_MR11U=y
+CONFIG_ATH79_MACH_TL_MR3020=y
+CONFIG_ATH79_MACH_TL_MR3X20=y
+CONFIG_ATH79_MACH_TL_WA901ND=y
+CONFIG_ATH79_MACH_TL_WA901ND_V2=y
+CONFIG_ATH79_MACH_TL_WDR3500=y
+CONFIG_ATH79_MACH_TL_WDR4300=y
+CONFIG_ATH79_MACH_TL_WR1041N_V2=y
+CONFIG_ATH79_MACH_TL_WR1043ND=y
+CONFIG_ATH79_MACH_TL_WR2543N=y
+CONFIG_ATH79_MACH_TL_WR703N=y
+CONFIG_ATH79_MACH_TL_WR741ND=y
+CONFIG_ATH79_MACH_TL_WR741ND_V4=y
+CONFIG_ATH79_MACH_TL_WR841N_V1=y
+CONFIG_ATH79_MACH_TL_WR841N_V8=y
+CONFIG_ATH79_MACH_TL_WR941ND=y
+CONFIG_ATH79_MACH_UBNT=y
+CONFIG_ATH79_MACH_UBNT_XM=y
+CONFIG_ATH79_MACH_WHR_HP_G300N=y
+CONFIG_ATH79_MACH_WLAE_AG300N=y
+CONFIG_ATH79_MACH_WNDR3700=y
+CONFIG_ATH79_MACH_WNDR4300=y
+CONFIG_ATH79_MACH_WNR2000=y
+CONFIG_ATH79_MACH_WP543=y
+CONFIG_ATH79_MACH_WPE72=y
+CONFIG_ATH79_MACH_WRT160NL=y
+CONFIG_ATH79_MACH_WRT400N=y
+CONFIG_ATH79_MACH_WZR_HP_AG300H=y
+CONFIG_ATH79_MACH_WZR_HP_G300NH=y
+CONFIG_ATH79_MACH_WZR_HP_G300NH2=y
+CONFIG_ATH79_MACH_WZR_HP_G450H=y
+CONFIG_ATH79_MACH_ZCN_1523H=y
+CONFIG_ATH79_NVRAM=y
+CONFIG_ATH79_PCI_ATH9K_FIXUP=y
+CONFIG_ATH79_ROUTERBOOT=y
+# CONFIG_ATH79_WDT is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CMDLINE="rootfstype=squashfs,yaffs,jffs2 noinitrd"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_NXP_74HC153=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_GPIO=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_SOURCE="../../root"
+CONFIG_IP17XX_PHY=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+# CONFIG_LEDS_RB750 is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+# CONFIG_LEDS_TRIGGER_NETDEV is not set
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_WNDR3700_USB is not set
+# CONFIG_M25PXX_USE_FAST_READ is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MICREL_PHY=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_MACHINE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_SEAD3 is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+CONFIG_MTD_MYLOADER_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_TPLINK_PARTS=y
+CONFIG_MTD_WRT160NL_PARTS=y
+CONFIG_MYLOADER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MV88E6060=y
+CONFIG_NET_DSA_MV88E6063=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_AR724X=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERCPU_RWSEM=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RLE_DECOMPRESS=y
+CONFIG_RTL8306_PHY=y
+CONFIG_RTL8366RB_PHY=y
+CONFIG_RTL8366S_PHY=y
+CONFIG_RTL8366_SMI=y
+CONFIG_RTL8367_PHY=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_AR933X=y
+CONFIG_SERIAL_AR933X_CONSOLE=y
+CONFIG_SERIAL_AR933X_NR_UARTS=2
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SOC_AR71XX=y
+CONFIG_SOC_AR724X=y
+CONFIG_SOC_AR913X=y
+CONFIG_SOC_AR933X=y
+CONFIG_SOC_AR934X=y
+CONFIG_SOC_QCA955X=y
+CONFIG_SPI=y
+CONFIG_SPI_AP83=y
+CONFIG_SPI_ATH79=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_RB4XX is not set
+# CONFIG_SPI_RB4XX_CPLD is not set
+# CONFIG_SPI_VSC7385 is not set
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_UIDGID_CONVERTED=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/ar71xx/patches-3.8/143-MIPS-pci-ar724x-convert-to-a-platform-driver.patch b/target/linux/ar71xx/patches-3.8/143-MIPS-pci-ar724x-convert-to-a-platform-driver.patch
new file mode 100644 (file)
index 0000000..43d4b47
--- /dev/null
@@ -0,0 +1,94 @@
+From f2d2d928c3900b67a5f95e53b86de5b61a3ab12c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 11 Jun 2012 13:19:44 +0200
+Subject: [PATCH 04/34] MIPS: pci-ar724x: convert to a platform driver
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c |   57 ++++++++++++++++++++++++++++++++++++++++++-
+ 1 files changed, 55 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -11,6 +11,8 @@
+ #include <linux/irq.h>
+ #include <linux/pci.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/pci.h>
+@@ -262,7 +264,7 @@ static struct irq_chip ar724x_pci_irq_ch
+       .irq_mask_ack   = ar724x_pci_irq_mask,
+ };
+-static void __init ar724x_pci_irq_init(int irq)
++static void ar724x_pci_irq_init(int irq)
+ {
+       void __iomem *base;
+       int i;
+@@ -282,7 +284,7 @@ static void __init ar724x_pci_irq_init(i
+       irq_set_chained_handler(irq, ar724x_pci_irq_handler);
+ }
+-int __init ar724x_pcibios_init(int irq)
++int ar724x_pcibios_init(int irq)
+ {
+       int ret;
+@@ -312,3 +314,54 @@ err_unmap_devcfg:
+ err:
+       return ret;
+ }
++
++static int ar724x_pci_probe(struct platform_device *pdev)
++{
++      struct resource *res;
++      int irq;
++
++      res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
++      if (!res)
++              return -EINVAL;
++
++      ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
++      if (ar724x_pci_ctrl_base == NULL)
++              return -EBUSY;
++
++      res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
++      if (!res)
++              return -EINVAL;
++
++      ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
++      if (!ar724x_pci_devcfg_base)
++              return -EBUSY;
++
++      irq = platform_get_irq(pdev, 0);
++      if (irq < 0)
++              return -EINVAL;
++
++      ar724x_pci_link_up = ar724x_pci_check_link();
++      if (!ar724x_pci_link_up)
++              dev_warn(&pdev->dev, "PCIe link is down\n");
++
++      ar724x_pci_irq_init(irq);
++
++      register_pci_controller(&ar724x_pci_controller);
++
++      return 0;
++}
++
++static struct platform_driver ar724x_pci_driver = {
++      .probe = ar724x_pci_probe,
++      .driver = {
++              .name = "ar724x-pci",
++              .owner = THIS_MODULE,
++      },
++};
++
++static int __init ar724x_pci_init(void)
++{
++      return platform_driver_register(&ar724x_pci_driver);
++}
++
++postcore_initcall(ar724x_pci_init);
diff --git a/target/linux/ar71xx/patches-3.8/144-MIPS-pci-ar71xx-convert-to-a-platform-driver.patch b/target/linux/ar71xx/patches-3.8/144-MIPS-pci-ar71xx-convert-to-a-platform-driver.patch
new file mode 100644 (file)
index 0000000..98000a0
--- /dev/null
@@ -0,0 +1,104 @@
+From d1a22e73f991145a4abd7d0c37bcf318703c89ed Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 11 Jun 2012 13:24:55 +0200
+Subject: [PATCH 05/34] MIPS: pci-ar71xx: convert to a platform driver
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c |   60 +++++++++++++++++++++++++++++++++++++++++---
+ 1 files changed, 56 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -18,6 +18,8 @@
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
+ #include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+@@ -309,7 +311,7 @@ static struct irq_chip ar71xx_pci_irq_ch
+       .irq_mask_ack   = ar71xx_pci_irq_mask,
+ };
+-static __init void ar71xx_pci_irq_init(void)
++static void ar71xx_pci_irq_init(int irq)
+ {
+       void __iomem *base = ath79_reset_base;
+       int i;
+@@ -324,10 +326,10 @@ static __init void ar71xx_pci_irq_init(v
+               irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+                                        handle_level_irq);
+-      irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
++      irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
+ }
+-static __init void ar71xx_pci_reset(void)
++static void ar71xx_pci_reset(void)
+ {
+       void __iomem *ddr_base = ath79_ddr_base;
+@@ -367,9 +369,59 @@ __init int ar71xx_pcibios_init(void)
+       /* clear bus errors */
+       ar71xx_pci_check_error(1);
+-      ar71xx_pci_irq_init();
++      ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2);
+       register_pci_controller(&ar71xx_pci_controller);
+       return 0;
+ }
++
++static int ar71xx_pci_probe(struct platform_device *pdev)
++{
++      struct resource *res;
++      int irq;
++      u32 t;
++
++      res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
++      if (!res)
++              return -EINVAL;
++
++      ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
++      if (!ar71xx_pcicfg_base)
++              return -ENOMEM;
++
++      irq = platform_get_irq(pdev, 0);
++      if (irq < 0)
++              return -EINVAL;
++
++      ar71xx_pci_reset();
++
++      /* setup COMMAND register */
++      t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
++        | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
++      ar71xx_pci_local_write(PCI_COMMAND, 4, t);
++
++      /* clear bus errors */
++      ar71xx_pci_check_error(1);
++
++      ar71xx_pci_irq_init(irq);
++
++      register_pci_controller(&ar71xx_pci_controller);
++
++      return 0;
++}
++
++static struct platform_driver ar71xx_pci_driver = {
++      .probe = ar71xx_pci_probe,
++      .driver = {
++              .name = "ar71xx-pci",
++              .owner = THIS_MODULE,
++      },
++};
++
++static int __init ar71xx_pci_init(void)
++{
++      return platform_driver_register(&ar71xx_pci_driver);
++}
++
++postcore_initcall(ar71xx_pci_init);
diff --git a/target/linux/ar71xx/patches-3.8/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch b/target/linux/ar71xx/patches-3.8/145-MIPS-ath79-move-global-PCI-defines-into-a-common-hea.patch
new file mode 100644 (file)
index 0000000..4861db0
--- /dev/null
@@ -0,0 +1,94 @@
+From c3a8b5fa196cedc4b940c1e5ec482dd875aa3180 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 11 Jun 2012 13:38:06 +0200
+Subject: [PATCH 06/34] MIPS: ath79: move global PCI defines into a common header
+
+The constants will be used by a subsequent patch.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   24 ++++++++++++++++++++++++
+ arch/mips/pci/pci-ar71xx.c                     |   16 ----------------
+ arch/mips/pci/pci-ar724x.c                     |    8 --------
+ 3 files changed, 24 insertions(+), 24 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -41,11 +41,35 @@
+ #define AR71XX_RESET_BASE     (AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE     0x100
++#define AR71XX_PCI_MEM_BASE   0x10000000
++#define AR71XX_PCI_MEM_SIZE   0x07000000
++
++#define AR71XX_PCI_WIN0_OFFS  0x10000000
++#define AR71XX_PCI_WIN1_OFFS  0x11000000
++#define AR71XX_PCI_WIN2_OFFS  0x12000000
++#define AR71XX_PCI_WIN3_OFFS  0x13000000
++#define AR71XX_PCI_WIN4_OFFS  0x14000000
++#define AR71XX_PCI_WIN5_OFFS  0x15000000
++#define AR71XX_PCI_WIN6_OFFS  0x16000000
++#define AR71XX_PCI_WIN7_OFFS  0x07000000
++
++#define AR71XX_PCI_CFG_BASE   \
++      (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
++#define AR71XX_PCI_CFG_SIZE   0x100
++
+ #define AR7240_USB_CTRL_BASE  (AR71XX_APB_BASE + 0x00030000)
+ #define AR7240_USB_CTRL_SIZE  0x100
+ #define AR7240_OHCI_BASE      0x1b000000
+ #define AR7240_OHCI_SIZE      0x1000
++#define AR724X_PCI_MEM_BASE   0x10000000
++#define AR724X_PCI_MEM_SIZE   0x04000000
++
++#define AR724X_PCI_CFG_BASE   0x14000000
++#define AR724X_PCI_CFG_SIZE   0x1000
++#define AR724X_PCI_CTRL_BASE  (AR71XX_APB_BASE + 0x000f0000)
++#define AR724X_PCI_CTRL_SIZE  0x100
++
+ #define AR724X_EHCI_BASE      0x1b000000
+ #define AR724X_EHCI_SIZE      0x1000
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -25,22 +25,6 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/pci.h>
+-#define AR71XX_PCI_MEM_BASE   0x10000000
+-#define AR71XX_PCI_MEM_SIZE   0x07000000
+-
+-#define AR71XX_PCI_WIN0_OFFS          0x10000000
+-#define AR71XX_PCI_WIN1_OFFS          0x11000000
+-#define AR71XX_PCI_WIN2_OFFS          0x12000000
+-#define AR71XX_PCI_WIN3_OFFS          0x13000000
+-#define AR71XX_PCI_WIN4_OFFS          0x14000000
+-#define AR71XX_PCI_WIN5_OFFS          0x15000000
+-#define AR71XX_PCI_WIN6_OFFS          0x16000000
+-#define AR71XX_PCI_WIN7_OFFS          0x07000000
+-
+-#define AR71XX_PCI_CFG_BASE           \
+-      (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+-#define AR71XX_PCI_CFG_SIZE           0x100
+-
+ #define AR71XX_PCI_REG_CRP_AD_CBE     0x00
+ #define AR71XX_PCI_REG_CRP_WRDATA     0x04
+ #define AR71XX_PCI_REG_CRP_RDDATA     0x08
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -17,14 +17,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/pci.h>
+-#define AR724X_PCI_CFG_BASE   0x14000000
+-#define AR724X_PCI_CFG_SIZE   0x1000
+-#define AR724X_PCI_CTRL_BASE  (AR71XX_APB_BASE + 0x000f0000)
+-#define AR724X_PCI_CTRL_SIZE  0x100
+-
+-#define AR724X_PCI_MEM_BASE   0x10000000
+-#define AR724X_PCI_MEM_SIZE   0x04000000
+-
+ #define AR724X_PCI_REG_RESET          0x18
+ #define AR724X_PCI_REG_INT_STATUS     0x4c
+ #define AR724X_PCI_REG_INT_MASK               0x50
diff --git a/target/linux/ar71xx/patches-3.8/146-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch b/target/linux/ar71xx/patches-3.8/146-MIPS-ath79-register-platform-devices-for-the-PCI-con.patch
new file mode 100644 (file)
index 0000000..cc2572f
--- /dev/null
@@ -0,0 +1,119 @@
+From 2fdf8dcff3ffaa806e9f9d7f1c1bd876222cff4d Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 11 Jun 2012 13:39:32 +0200
+Subject: [PATCH 07/34] MIPS: ath79: register platform devices for the PCI controllers
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/pci.c |   87 +++++++++++++++++++++++++++++++++++++++++++-----
+ 1 files changed, 78 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -14,6 +14,8 @@
+ #include <linux/init.h>
+ #include <linux/pci.h>
++#include <linux/resource.h>
++#include <linux/platform_device.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+@@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init(
+       ath79_pci_plat_dev_init = func;
+ }
+-int __init ath79_register_pci(void)
++static struct platform_device *
++ath79_register_pci_ar71xx(void)
+ {
+-      if (soc_is_ar71xx())
+-              return ar71xx_pcibios_init();
++      struct platform_device *pdev;
++      struct resource res[2];
++
++      memset(res, 0, sizeof(res));
+-      if (soc_is_ar724x())
+-              return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
++      res[0].name = "cfg_base";
++      res[0].flags = IORESOURCE_MEM;
++      res[0].start = AR71XX_PCI_CFG_BASE;
++      res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
++
++      res[1].flags = IORESOURCE_IRQ;
++      res[1].start = ATH79_CPU_IRQ_IP2;
++      res[1].end = ATH79_CPU_IRQ_IP2;
++
++      pdev = platform_device_register_simple("ar71xx-pci", -1,
++                                             res, ARRAY_SIZE(res));
++      return pdev;
++}
+-      if (soc_is_ar9342() || soc_is_ar9344()) {
++static struct platform_device *
++ath79_register_pci_ar724x(int id,
++                        unsigned long cfg_base,
++                        unsigned long ctrl_base,
++                        int irq)
++{
++      struct platform_device *pdev;
++      struct resource res[3];
++
++      memset(res, 0, sizeof(res));
++
++      res[0].name = "cfg_base";
++      res[0].flags = IORESOURCE_MEM;
++      res[0].start = cfg_base;
++      res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
++
++      res[1].name = "ctrl_base";
++      res[1].flags = IORESOURCE_MEM;
++      res[1].start = ctrl_base;
++      res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
++
++      res[2].flags = IORESOURCE_IRQ;
++      res[2].start = irq;
++      res[2].end = irq;
++
++      pdev = platform_device_register_simple("ar724x-pci", id,
++                                             res, ARRAY_SIZE(res));
++      return pdev;
++}
++
++int __init ath79_register_pci(void)
++{
++      struct platform_device *pdev = NULL;
++
++      if (soc_is_ar71xx()) {
++              pdev = ath79_register_pci_ar71xx();
++      } else if (soc_is_ar724x()) {
++              pdev = ath79_register_pci_ar724x(-1,
++                                               AR724X_PCI_CFG_BASE,
++                                               AR724X_PCI_CTRL_BASE,
++                                               ATH79_CPU_IRQ_IP2);
++      } else if (soc_is_ar9342() ||
++                 soc_is_ar9344()) {
+               u32 bootstrap;
+               bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+-              if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
+-                      return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
++              if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
++                      return -ENODEV;
++
++              pdev = ath79_register_pci_ar724x(-1,
++                                               AR724X_PCI_CFG_BASE,
++                                               AR724X_PCI_CTRL_BASE,
++                                               ATH79_IP2_IRQ(0));
++      } else {
++              /* No PCI support */
++              return -ENODEV;
+       }
+-      return -ENODEV;
++      if (!pdev)
++              pr_err("unable to register PCI controller device\n");
++
++      return pdev ? 0 : -ENODEV;
+ }
diff --git a/target/linux/ar71xx/patches-3.8/147-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch b/target/linux/ar71xx/patches-3.8/147-MIPS-ath79-remove-unused-ar7-1x-24-x_pcibios_init-fu.patch
new file mode 100644 (file)
index 0000000..c3a7fca
--- /dev/null
@@ -0,0 +1,147 @@
+From 07224e2fa5f889162ee0560c6ab1eb8cd16a8dd2 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 11 Jun 2012 14:59:39 +0200
+Subject: [PATCH 08/34] MIPS: ath79: remove unused ar7{1x,24}x_pcibios_init functions
+
+The functions are unused now, so remove them.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/pci.c                  |    1 -
+ arch/mips/include/asm/mach-ath79/pci.h |   28 ----------------------------
+ arch/mips/pci/pci-ar71xx.c             |   26 --------------------------
+ arch/mips/pci/pci-ar724x.c             |   32 --------------------------------
+ 4 files changed, 0 insertions(+), 87 deletions(-)
+ delete mode 100644 arch/mips/include/asm/mach-ath79/pci.h
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -19,7 +19,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+-#include <asm/mach-ath79/pci.h>
+ #include "pci.h"
+ static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
+--- a/arch/mips/include/asm/mach-ath79/pci.h
++++ /dev/null
+@@ -1,28 +0,0 @@
+-/*
+- *  Atheros AR71XX/AR724X PCI support
+- *
+- *  Copyright (C) 2011 RenĂ© Bolldorf <xsecute@googlemail.com>
+- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- *  This program is free software; you can redistribute it and/or modify it
+- *  under the terms of the GNU General Public License version 2 as published
+- *  by the Free Software Foundation.
+- */
+-
+-#ifndef __ASM_MACH_ATH79_PCI_H
+-#define __ASM_MACH_ATH79_PCI_H
+-
+-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
+-int ar71xx_pcibios_init(void);
+-#else
+-static inline int ar71xx_pcibios_init(void) { return 0; }
+-#endif
+-
+-#if defined(CONFIG_PCI_AR724X)
+-int ar724x_pcibios_init(int irq);
+-#else
+-static inline int ar724x_pcibios_init(int irq) { return 0; }
+-#endif
+-
+-#endif /* __ASM_MACH_ATH79_PCI_H */
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -23,7 +23,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/pci.h>
+ #define AR71XX_PCI_REG_CRP_AD_CBE     0x00
+ #define AR71XX_PCI_REG_CRP_WRDATA     0x04
+@@ -335,31 +334,6 @@ static void ar71xx_pci_reset(void)
+       mdelay(100);
+ }
+-__init int ar71xx_pcibios_init(void)
+-{
+-      u32 t;
+-
+-      ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
+-      if (ar71xx_pcicfg_base == NULL)
+-              return -ENOMEM;
+-
+-      ar71xx_pci_reset();
+-
+-      /* setup COMMAND register */
+-      t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
+-        | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
+-      ar71xx_pci_local_write(PCI_COMMAND, 4, t);
+-
+-      /* clear bus errors */
+-      ar71xx_pci_check_error(1);
+-
+-      ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2);
+-
+-      register_pci_controller(&ar71xx_pci_controller);
+-
+-      return 0;
+-}
+-
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
+       struct resource *res;
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -15,7 +15,6 @@
+ #include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+-#include <asm/mach-ath79/pci.h>
+ #define AR724X_PCI_REG_RESET          0x18
+ #define AR724X_PCI_REG_INT_STATUS     0x4c
+@@ -276,37 +275,6 @@ static void ar724x_pci_irq_init(int irq)
+       irq_set_chained_handler(irq, ar724x_pci_irq_handler);
+ }
+-int ar724x_pcibios_init(int irq)
+-{
+-      int ret;
+-
+-      ret = -ENOMEM;
+-
+-      ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
+-                                       AR724X_PCI_CFG_SIZE);
+-      if (ar724x_pci_devcfg_base == NULL)
+-              goto err;
+-
+-      ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
+-                                     AR724X_PCI_CTRL_SIZE);
+-      if (ar724x_pci_ctrl_base == NULL)
+-              goto err_unmap_devcfg;
+-
+-      ar724x_pci_link_up = ar724x_pci_check_link();
+-      if (!ar724x_pci_link_up)
+-              pr_warn("ar724x: PCIe link is down\n");
+-
+-      ar724x_pci_irq_init(irq);
+-      register_pci_controller(&ar724x_pci_controller);
+-
+-      return PCIBIOS_SUCCESSFUL;
+-
+-err_unmap_devcfg:
+-      iounmap(ar724x_pci_devcfg_base);
+-err:
+-      return ret;
+-}
+-
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
+       struct resource *res;
diff --git a/target/linux/ar71xx/patches-3.8/148-MIPS-avoid-possible-resource-conflict-in-register_pc.patch b/target/linux/ar71xx/patches-3.8/148-MIPS-avoid-possible-resource-conflict-in-register_pc.patch
new file mode 100644 (file)
index 0000000..e732ce0
--- /dev/null
@@ -0,0 +1,35 @@
+From a018b28d3953a32008de839d997a992a724ae314 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 17:40:45 +0200
+Subject: [PATCH 09/34] MIPS: avoid possible resource conflict in register_pci_controller
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/pci/pci.c |   15 +++++++++++++--
+ 1 files changed, 13 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci.c
++++ b/arch/mips/pci/pci.c
+@@ -175,9 +175,20 @@ static DEFINE_MUTEX(pci_scan_mutex);
+ void register_pci_controller(struct pci_controller *hose)
+ {
+-      if (request_resource(&iomem_resource, hose->mem_resource) < 0)
++      struct resource *parent;
++
++      parent = hose->mem_resource->parent;
++      if (!parent)
++              parent = &iomem_resource;
++
++      if (request_resource(parent, hose->mem_resource) < 0)
+               goto out;
+-      if (request_resource(&ioport_resource, hose->io_resource) < 0) {
++
++      parent = hose->io_resource->parent;
++      if (!parent)
++              parent = &ioport_resource;
++
++      if (request_resource(parent, hose->io_resource) < 0) {
+               release_resource(hose->mem_resource);
+               goto out;
+       }
diff --git a/target/linux/ar71xx/patches-3.8/149-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch b/target/linux/ar71xx/patches-3.8/149-MIPS-pci-ar724x-use-dynamically-allocated-PCI-contro.patch
new file mode 100644 (file)
index 0000000..1a7ec7a
--- /dev/null
@@ -0,0 +1,307 @@
+From 242aedf3246dc5085271aca56134ac455bfb64b5 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 11:51:34 +0200
+Subject: [PATCH 10/34] MIPS: pci-ar724x: use dynamically allocated PCI controller structure
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c |  129 ++++++++++++++++++++++++++++----------------
+ 1 files changed, 82 insertions(+), 47 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -9,6 +9,7 @@
+  *  by the Free Software Foundation.
+  */
++#include <linux/spinlock.h>
+ #include <linux/irq.h>
+ #include <linux/pci.h>
+ #include <linux/module.h>
+@@ -28,38 +29,56 @@
+ #define AR7240_BAR0_WAR_VALUE 0xffff
+-static DEFINE_SPINLOCK(ar724x_pci_lock);
+-static void __iomem *ar724x_pci_devcfg_base;
+-static void __iomem *ar724x_pci_ctrl_base;
+-
+-static u32 ar724x_pci_bar0_value;
+-static bool ar724x_pci_bar0_is_cached;
+-static bool ar724x_pci_link_up;
++struct ar724x_pci_controller {
++      void __iomem *devcfg_base;
++      void __iomem *ctrl_base;
+-static inline bool ar724x_pci_check_link(void)
++      int irq;
++
++      bool link_up;
++      bool bar0_is_cached;
++      u32  bar0_value;
++
++      spinlock_t lock;
++
++      struct pci_controller pci_controller;
++};
++
++static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+ {
+       u32 reset;
+-      reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET);
++      reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
+       return reset & AR724X_PCI_RESET_LINK_UP;
+ }
++static inline struct ar724x_pci_controller *
++pci_bus_to_ar724x_controller(struct pci_bus *bus)
++{
++      struct pci_controller *hose;
++
++      hose = (struct pci_controller *) bus->sysdata;
++      return container_of(hose, struct ar724x_pci_controller, pci_controller);
++}
++
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+                           int size, uint32_t *value)
+ {
++      struct ar724x_pci_controller *apc;
+       unsigned long flags;
+       void __iomem *base;
+       u32 data;
+-      if (!ar724x_pci_link_up)
++      apc = pci_bus_to_ar724x_controller(bus);
++      if (!apc->link_up)
+               return PCIBIOS_DEVICE_NOT_FOUND;
+       if (devfn)
+               return PCIBIOS_DEVICE_NOT_FOUND;
+-      base = ar724x_pci_devcfg_base;
++      base = apc->devcfg_base;
+-      spin_lock_irqsave(&ar724x_pci_lock, flags);
++      spin_lock_irqsave(&apc->lock, flags);
+       data = __raw_readl(base + (where & ~3));
+       switch (size) {
+@@ -78,17 +97,17 @@ static int ar724x_pci_read(struct pci_bu
+       case 4:
+               break;
+       default:
+-              spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++              spin_unlock_irqrestore(&apc->lock, flags);
+               return PCIBIOS_BAD_REGISTER_NUMBER;
+       }
+-      spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++      spin_unlock_irqrestore(&apc->lock, flags);
+       if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
+-          ar724x_pci_bar0_is_cached) {
++          apc->bar0_is_cached) {
+               /* use the cached value */
+-              *value = ar724x_pci_bar0_value;
++              *value = apc->bar0_value;
+       } else {
+               *value = data;
+       }
+@@ -99,12 +118,14 @@ static int ar724x_pci_read(struct pci_bu
+ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+                            int size, uint32_t value)
+ {
++      struct ar724x_pci_controller *apc;
+       unsigned long flags;
+       void __iomem *base;
+       u32 data;
+       int s;
+-      if (!ar724x_pci_link_up)
++      apc = pci_bus_to_ar724x_controller(bus);
++      if (!apc->link_up)
+               return PCIBIOS_DEVICE_NOT_FOUND;
+       if (devfn)
+@@ -122,18 +143,18 @@ static int ar724x_pci_write(struct pci_b
+                        * BAR0 register in order to make the device memory
+                        * accessible.
+                        */
+-                      ar724x_pci_bar0_is_cached = true;
+-                      ar724x_pci_bar0_value = value;
++                      apc->bar0_is_cached = true;
++                      apc->bar0_value = value;
+                       value = AR7240_BAR0_WAR_VALUE;
+               } else {
+-                      ar724x_pci_bar0_is_cached = false;
++                      apc->bar0_is_cached = false;
+               }
+       }
+-      base = ar724x_pci_devcfg_base;
++      base = apc->devcfg_base;
+-      spin_lock_irqsave(&ar724x_pci_lock, flags);
++      spin_lock_irqsave(&apc->lock, flags);
+       data = __raw_readl(base + (where & ~3));
+       switch (size) {
+@@ -151,7 +172,7 @@ static int ar724x_pci_write(struct pci_b
+               data = value;
+               break;
+       default:
+-              spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++              spin_unlock_irqrestore(&apc->lock, flags);
+               return PCIBIOS_BAD_REGISTER_NUMBER;
+       }
+@@ -159,7 +180,7 @@ static int ar724x_pci_write(struct pci_b
+       __raw_writel(data, base + (where & ~3));
+       /* flush write */
+       __raw_readl(base + (where & ~3));
+-      spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++      spin_unlock_irqrestore(&apc->lock, flags);
+       return PCIBIOS_SUCCESSFUL;
+ }
+@@ -183,18 +204,14 @@ static struct resource ar724x_mem_resour
+       .flags  = IORESOURCE_MEM,
+ };
+-static struct pci_controller ar724x_pci_controller = {
+-      .pci_ops        = &ar724x_pci_ops,
+-      .io_resource    = &ar724x_io_resource,
+-      .mem_resource   = &ar724x_mem_resource,
+-};
+-
+ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
++      struct ar724x_pci_controller *apc;
+       void __iomem *base;
+       u32 pending;
+-      base = ar724x_pci_ctrl_base;
++      apc = irq_get_handler_data(irq);
++      base = apc->ctrl_base;
+       pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
+                 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+@@ -208,10 +225,12 @@ static void ar724x_pci_irq_handler(unsig
+ static void ar724x_pci_irq_unmask(struct irq_data *d)
+ {
++      struct ar724x_pci_controller *apc;
+       void __iomem *base;
+       u32 t;
+-      base = ar724x_pci_ctrl_base;
++      apc = irq_data_get_irq_chip_data(d);
++      base = apc->ctrl_base;
+       switch (d->irq) {
+       case ATH79_PCI_IRQ(0):
+@@ -225,10 +244,12 @@ static void ar724x_pci_irq_unmask(struct
+ static void ar724x_pci_irq_mask(struct irq_data *d)
+ {
++      struct ar724x_pci_controller *apc;
+       void __iomem *base;
+       u32 t;
+-      base = ar724x_pci_ctrl_base;
++      apc = irq_data_get_irq_chip_data(d);
++      base = apc->ctrl_base;
+       switch (d->irq) {
+       case ATH79_PCI_IRQ(0):
+@@ -255,12 +276,12 @@ static struct irq_chip ar724x_pci_irq_ch
+       .irq_mask_ack   = ar724x_pci_irq_mask,
+ };
+-static void ar724x_pci_irq_init(int irq)
++static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
+ {
+       void __iomem *base;
+       int i;
+-      base = ar724x_pci_ctrl_base;
++      base = apc->ctrl_base;
+       __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+       __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+@@ -268,45 +289,59 @@ static void ar724x_pci_irq_init(int irq)
+       BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
+       for (i = ATH79_PCI_IRQ_BASE;
+-           i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
++           i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
+               irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+                                        handle_level_irq);
++              irq_set_chip_data(i, apc);
++      }
+-      irq_set_chained_handler(irq, ar724x_pci_irq_handler);
++      irq_set_handler_data(apc->irq, apc);
++      irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
+ }
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
++      struct ar724x_pci_controller *apc;
+       struct resource *res;
+-      int irq;
++
++      apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
++                          GFP_KERNEL);
++      if (!apc)
++              return -ENOMEM;
+       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
+       if (!res)
+               return -EINVAL;
+-      ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
+-      if (ar724x_pci_ctrl_base == NULL)
++      apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
++      if (apc->ctrl_base == NULL)
+               return -EBUSY;
+       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
+       if (!res)
+               return -EINVAL;
+-      ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
+-      if (!ar724x_pci_devcfg_base)
++      apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
++      if (!apc->devcfg_base)
+               return -EBUSY;
+-      irq = platform_get_irq(pdev, 0);
+-      if (irq < 0)
++      apc->irq = platform_get_irq(pdev, 0);
++      if (apc->irq < 0)
+               return -EINVAL;
+-      ar724x_pci_link_up = ar724x_pci_check_link();
+-      if (!ar724x_pci_link_up)
++      spin_lock_init(&apc->lock);
++
++      apc->pci_controller.pci_ops = &ar724x_pci_ops;
++      apc->pci_controller.io_resource = &ar724x_io_resource;
++      apc->pci_controller.mem_resource = &ar724x_mem_resource;
++
++      apc->link_up = ar724x_pci_check_link(apc);
++      if (!apc->link_up)
+               dev_warn(&pdev->dev, "PCIe link is down\n");
+-      ar724x_pci_irq_init(irq);
++      ar724x_pci_irq_init(apc);
+-      register_pci_controller(&ar724x_pci_controller);
++      register_pci_controller(&apc->pci_controller);
+       return 0;
+ }
diff --git a/target/linux/ar71xx/patches-3.8/150-MIPS-pci-ar724x-remove-static-PCI-resources.patch b/target/linux/ar71xx/patches-3.8/150-MIPS-pci-ar724x-remove-static-PCI-resources.patch
new file mode 100644 (file)
index 0000000..34e2c07
--- /dev/null
@@ -0,0 +1,131 @@
+From f1c3a7dadf7b77809cda7f77df4b1ba3b24fbfa3 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 27 Jun 2012 10:12:50 +0200
+Subject: [PATCH 11/34] MIPS: pci-ar724x: remove static PCI resources
+
+Get those from the platform device instead.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/pci.c      |   21 ++++++++++++++++++++-
+ arch/mips/pci/pci-ar724x.c |   40 ++++++++++++++++++++++++----------------
+ 2 files changed, 44 insertions(+), 17 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -137,10 +137,13 @@ static struct platform_device *
+ ath79_register_pci_ar724x(int id,
+                         unsigned long cfg_base,
+                         unsigned long ctrl_base,
++                        unsigned long mem_base,
++                        unsigned long mem_size,
++                        unsigned long io_base,
+                         int irq)
+ {
+       struct platform_device *pdev;
+-      struct resource res[3];
++      struct resource res[5];
+       memset(res, 0, sizeof(res));
+@@ -158,6 +161,16 @@ ath79_register_pci_ar724x(int id,
+       res[2].start = irq;
+       res[2].end = irq;
++      res[3].name = "mem_base";
++      res[3].flags = IORESOURCE_MEM;
++      res[3].start = mem_base;
++      res[3].end = mem_base + mem_size - 1;
++
++      res[4].name = "io_base";
++      res[4].flags = IORESOURCE_IO;
++      res[4].start = io_base;
++      res[4].end = io_base;
++
+       pdev = platform_device_register_simple("ar724x-pci", id,
+                                              res, ARRAY_SIZE(res));
+       return pdev;
+@@ -173,6 +186,9 @@ int __init ath79_register_pci(void)
+               pdev = ath79_register_pci_ar724x(-1,
+                                                AR724X_PCI_CFG_BASE,
+                                                AR724X_PCI_CTRL_BASE,
++                                               AR724X_PCI_MEM_BASE,
++                                               AR724X_PCI_MEM_SIZE,
++                                               0,
+                                                ATH79_CPU_IRQ_IP2);
+       } else if (soc_is_ar9342() ||
+                  soc_is_ar9344()) {
+@@ -185,6 +201,9 @@ int __init ath79_register_pci(void)
+               pdev = ath79_register_pci_ar724x(-1,
+                                                AR724X_PCI_CFG_BASE,
+                                                AR724X_PCI_CTRL_BASE,
++                                               AR724X_PCI_MEM_BASE,
++                                               AR724X_PCI_MEM_SIZE,
++                                               0,
+                                                ATH79_IP2_IRQ(0));
+       } else {
+               /* No PCI support */
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -42,6 +42,8 @@ struct ar724x_pci_controller {
+       spinlock_t lock;
+       struct pci_controller pci_controller;
++      struct resource io_res;
++      struct resource mem_res;
+ };
+ static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+@@ -190,20 +192,6 @@ static struct pci_ops ar724x_pci_ops = {
+       .write  = ar724x_pci_write,
+ };
+-static struct resource ar724x_io_resource = {
+-      .name   = "PCI IO space",
+-      .start  = 0,
+-      .end    = 0,
+-      .flags  = IORESOURCE_IO,
+-};
+-
+-static struct resource ar724x_mem_resource = {
+-      .name   = "PCI memory space",
+-      .start  = AR724X_PCI_MEM_BASE,
+-      .end    = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
+-      .flags  = IORESOURCE_MEM,
+-};
+-
+ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+       struct ar724x_pci_controller *apc;
+@@ -331,9 +319,29 @@ static int ar724x_pci_probe(struct platf
+       spin_lock_init(&apc->lock);
++      res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
++      if (!res)
++              return -EINVAL;
++
++      apc->io_res.parent = res;
++      apc->io_res.name = "PCI IO space";
++      apc->io_res.start = res->start;
++      apc->io_res.end = res->end;
++      apc->io_res.flags = IORESOURCE_IO;
++
++      res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
++      if (!res)
++              return -EINVAL;
++
++      apc->mem_res.parent = res;
++      apc->mem_res.name = "PCI memory space";
++      apc->mem_res.start = res->start;
++      apc->mem_res.end = res->end;
++      apc->mem_res.flags = IORESOURCE_MEM;
++
+       apc->pci_controller.pci_ops = &ar724x_pci_ops;
+-      apc->pci_controller.io_resource = &ar724x_io_resource;
+-      apc->pci_controller.mem_resource = &ar724x_mem_resource;
++      apc->pci_controller.io_resource = &apc->io_res;
++      apc->pci_controller.mem_resource = &apc->mem_res;
+       apc->link_up = ar724x_pci_check_link(apc);
+       if (!apc->link_up)
diff --git a/target/linux/ar71xx/patches-3.8/151-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch b/target/linux/ar71xx/patches-3.8/151-MIPS-pci-ar724x-use-per-controller-IRQ-base.patch
new file mode 100644 (file)
index 0000000..1debcfc
--- /dev/null
@@ -0,0 +1,110 @@
+From d258929cd4c8c495f619f0e66d9d1c23f3f9246f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 26 Jun 2012 11:59:45 +0200
+Subject: [PATCH 12/34] MIPS: pci-ar724x: use per-controller IRQ base
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c |   31 +++++++++++++++++++++----------
+ 1 files changed, 21 insertions(+), 10 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -34,6 +34,7 @@ struct ar724x_pci_controller {
+       void __iomem *ctrl_base;
+       int irq;
++      int irq_base;
+       bool link_up;
+       bool bar0_is_cached;
+@@ -205,7 +206,7 @@ static void ar724x_pci_irq_handler(unsig
+                 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+       if (pending & AR724X_PCI_INT_DEV0)
+-              generic_handle_irq(ATH79_PCI_IRQ(0));
++              generic_handle_irq(apc->irq_base + 0);
+       else
+               spurious_interrupt();
+@@ -215,13 +216,15 @@ static void ar724x_pci_irq_unmask(struct
+ {
+       struct ar724x_pci_controller *apc;
+       void __iomem *base;
++      int offset;
+       u32 t;
+       apc = irq_data_get_irq_chip_data(d);
+       base = apc->ctrl_base;
++      offset = apc->irq_base - d->irq;
+-      switch (d->irq) {
+-      case ATH79_PCI_IRQ(0):
++      switch (offset) {
++      case 0:
+               t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+               __raw_writel(t | AR724X_PCI_INT_DEV0,
+                            base + AR724X_PCI_REG_INT_MASK);
+@@ -234,13 +237,15 @@ static void ar724x_pci_irq_mask(struct i
+ {
+       struct ar724x_pci_controller *apc;
+       void __iomem *base;
++      int offset;
+       u32 t;
+       apc = irq_data_get_irq_chip_data(d);
+       base = apc->ctrl_base;
++      offset = apc->irq_base - d->irq;
+-      switch (d->irq) {
+-      case ATH79_PCI_IRQ(0):
++      switch (offset) {
++      case 0:
+               t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+               __raw_writel(t & ~AR724X_PCI_INT_DEV0,
+                            base + AR724X_PCI_REG_INT_MASK);
+@@ -264,7 +269,8 @@ static struct irq_chip ar724x_pci_irq_ch
+       .irq_mask_ack   = ar724x_pci_irq_mask,
+ };
+-static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
++static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
++                                        int id)
+ {
+       void __iomem *base;
+       int i;
+@@ -274,10 +280,10 @@ static void ar724x_pci_irq_init(struct a
+       __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+       __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+-      BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
++      apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
+-      for (i = ATH79_PCI_IRQ_BASE;
+-           i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
++      for (i = apc->irq_base;
++           i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
+               irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+                                        handle_level_irq);
+               irq_set_chip_data(i, apc);
+@@ -291,6 +297,11 @@ static int ar724x_pci_probe(struct platf
+ {
+       struct ar724x_pci_controller *apc;
+       struct resource *res;
++      int id;
++
++      id = pdev->id;
++      if (id == -1)
++              id = 0;
+       apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
+                           GFP_KERNEL);
+@@ -347,7 +358,7 @@ static int ar724x_pci_probe(struct platf
+       if (!apc->link_up)
+               dev_warn(&pdev->dev, "PCIe link is down\n");
+-      ar724x_pci_irq_init(apc);
++      ar724x_pci_irq_init(apc, id);
+       register_pci_controller(&apc->pci_controller);
diff --git a/target/linux/ar71xx/patches-3.8/152-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch b/target/linux/ar71xx/patches-3.8/152-MIPS-pci-ar724x-setup-command-register-of-the-PCI-co.patch
new file mode 100644 (file)
index 0000000..9f895bb
--- /dev/null
@@ -0,0 +1,165 @@
+From 93824983ceb36d4ce1f4a644031ec6fb5f332f1d Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 26 Jun 2012 15:14:47 +0200
+Subject: [PATCH 13/34] MIPS: pci-ar724x: setup command register of the PCI controller
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/pci.c                          |   10 +++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 +
+ arch/mips/pci/pci-ar724x.c                     |   63 ++++++++++++++++++++++++
+ 3 files changed, 74 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -137,13 +137,14 @@ static struct platform_device *
+ ath79_register_pci_ar724x(int id,
+                         unsigned long cfg_base,
+                         unsigned long ctrl_base,
++                        unsigned long crp_base,
+                         unsigned long mem_base,
+                         unsigned long mem_size,
+                         unsigned long io_base,
+                         int irq)
+ {
+       struct platform_device *pdev;
+-      struct resource res[5];
++      struct resource res[6];
+       memset(res, 0, sizeof(res));
+@@ -171,6 +172,11 @@ ath79_register_pci_ar724x(int id,
+       res[4].start = io_base;
+       res[4].end = io_base;
++      res[5].name = "crp_base";
++      res[5].flags = IORESOURCE_MEM;
++      res[5].start = crp_base;
++      res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
++
+       pdev = platform_device_register_simple("ar724x-pci", id,
+                                              res, ARRAY_SIZE(res));
+       return pdev;
+@@ -186,6 +192,7 @@ int __init ath79_register_pci(void)
+               pdev = ath79_register_pci_ar724x(-1,
+                                                AR724X_PCI_CFG_BASE,
+                                                AR724X_PCI_CTRL_BASE,
++                                               AR724X_PCI_CRP_BASE,
+                                                AR724X_PCI_MEM_BASE,
+                                                AR724X_PCI_MEM_SIZE,
+                                                0,
+@@ -201,6 +208,7 @@ int __init ath79_register_pci(void)
+               pdev = ath79_register_pci_ar724x(-1,
+                                                AR724X_PCI_CFG_BASE,
+                                                AR724X_PCI_CTRL_BASE,
++                                               AR724X_PCI_CRP_BASE,
+                                                AR724X_PCI_MEM_BASE,
+                                                AR724X_PCI_MEM_SIZE,
+                                                0,
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -67,6 +67,8 @@
+ #define AR724X_PCI_CFG_BASE   0x14000000
+ #define AR724X_PCI_CFG_SIZE   0x1000
++#define AR724X_PCI_CRP_BASE   (AR71XX_APB_BASE + 0x000c0000)
++#define AR724X_PCI_CRP_SIZE   0x1000
+ #define AR724X_PCI_CTRL_BASE  (AR71XX_APB_BASE + 0x000f0000)
+ #define AR724X_PCI_CTRL_SIZE  0x100
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -29,9 +29,17 @@
+ #define AR7240_BAR0_WAR_VALUE 0xffff
++#define AR724X_PCI_CMD_INIT   (PCI_COMMAND_MEMORY |           \
++                               PCI_COMMAND_MASTER |           \
++                               PCI_COMMAND_INVALIDATE |       \
++                               PCI_COMMAND_PARITY |           \
++                               PCI_COMMAND_SERR |             \
++                               PCI_COMMAND_FAST_BACK)
++
+ struct ar724x_pci_controller {
+       void __iomem *devcfg_base;
+       void __iomem *ctrl_base;
++      void __iomem *crp_base;
+       int irq;
+       int irq_base;
+@@ -64,6 +72,51 @@ pci_bus_to_ar724x_controller(struct pci_
+       return container_of(hose, struct ar724x_pci_controller, pci_controller);
+ }
++static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
++                                int where, int size, u32 value)
++{
++      unsigned long flags;
++      void __iomem *base;
++      u32 data;
++      int s;
++
++      WARN_ON(where & (size - 1));
++
++      if (!apc->link_up)
++              return PCIBIOS_DEVICE_NOT_FOUND;
++
++      base = apc->crp_base;
++
++      spin_lock_irqsave(&apc->lock, flags);
++      data = __raw_readl(base + (where & ~3));
++
++      switch (size) {
++      case 1:
++              s = ((where & 3) * 8);
++              data &= ~(0xff << s);
++              data |= ((value & 0xff) << s);
++              break;
++      case 2:
++              s = ((where & 2) * 8);
++              data &= ~(0xffff << s);
++              data |= ((value & 0xffff) << s);
++              break;
++      case 4:
++              data = value;
++              break;
++      default:
++              spin_unlock_irqrestore(&apc->lock, flags);
++              return PCIBIOS_BAD_REGISTER_NUMBER;
++      }
++
++      __raw_writel(data, base + (where & ~3));
++      /* flush write */
++      __raw_readl(base + (where & ~3));
++      spin_unlock_irqrestore(&apc->lock, flags);
++
++      return PCIBIOS_SUCCESSFUL;
++}
++
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+                           int size, uint32_t *value)
+ {
+@@ -324,6 +377,14 @@ static int ar724x_pci_probe(struct platf
+       if (!apc->devcfg_base)
+               return -EBUSY;
++      res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
++      if (!res)
++              return -EINVAL;
++
++      apc->crp_base = devm_request_and_ioremap(&pdev->dev, res);
++      if (apc->crp_base == NULL)
++              return -EBUSY;
++
+       apc->irq = platform_get_irq(pdev, 0);
+       if (apc->irq < 0)
+               return -EINVAL;
+@@ -360,6 +421,8 @@ static int ar724x_pci_probe(struct platf
+       ar724x_pci_irq_init(apc, id);
++      ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
++
+       register_pci_controller(&apc->pci_controller);
+       return 0;
diff --git a/target/linux/ar71xx/patches-3.8/153-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch b/target/linux/ar71xx/patches-3.8/153-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch
new file mode 100644 (file)
index 0000000..9d73823
--- /dev/null
@@ -0,0 +1,228 @@
+From 6c3ef689e4364dca74eaaecd72384be09e5a6bc8 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 25 Jun 2012 09:19:08 +0200
+Subject: [PATCH 14/34] MIPS: pci-ar71xx: use dynamically allocated PCI controller structure
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c |   84 +++++++++++++++++++++++++++----------------
+ 1 files changed, 53 insertions(+), 31 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -20,6 +20,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
++#include <linux/slab.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+@@ -48,8 +49,12 @@
+ #define AR71XX_PCI_IRQ_COUNT          5
+-static DEFINE_SPINLOCK(ar71xx_pci_lock);
+-static void __iomem *ar71xx_pcicfg_base;
++struct ar71xx_pci_controller {
++      void __iomem *cfg_base;
++      spinlock_t lock;
++      int irq;
++      struct pci_controller pci_ctrl;
++};
+ /* Byte lane enable bits */
+ static const u8 ar71xx_pci_ble_table[4][4] = {
+@@ -92,9 +97,18 @@ static inline u32 ar71xx_pci_bus_addr(st
+       return ret;
+ }
+-static int ar71xx_pci_check_error(int quiet)
++static inline struct ar71xx_pci_controller *
++pci_bus_to_ar71xx_controller(struct pci_bus *bus)
+ {
+-      void __iomem *base = ar71xx_pcicfg_base;
++      struct pci_controller *hose;
++
++      hose = (struct pci_controller *) bus->sysdata;
++      return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
++}
++
++static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
++{
++      void __iomem *base = apc->cfg_base;
+       u32 pci_err;
+       u32 ahb_err;
+@@ -129,9 +143,10 @@ static int ar71xx_pci_check_error(int qu
+       return !!(ahb_err | pci_err);
+ }
+-static inline void ar71xx_pci_local_write(int where, int size, u32 value)
++static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
++                                        int where, int size, u32 value)
+ {
+-      void __iomem *base = ar71xx_pcicfg_base;
++      void __iomem *base = apc->cfg_base;
+       u32 ad_cbe;
+       value = value << (8 * (where & 3));
+@@ -147,7 +162,8 @@ static inline int ar71xx_pci_set_cfgaddr
+                                        unsigned int devfn,
+                                        int where, int size, u32 cmd)
+ {
+-      void __iomem *base = ar71xx_pcicfg_base;
++      struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++      void __iomem *base = apc->cfg_base;
+       u32 addr;
+       addr = ar71xx_pci_bus_addr(bus, devfn, where);
+@@ -156,13 +172,14 @@ static inline int ar71xx_pci_set_cfgaddr
+       __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
+                    base + AR71XX_PCI_REG_CFG_CBE);
+-      return ar71xx_pci_check_error(1);
++      return ar71xx_pci_check_error(apc, 1);
+ }
+ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+                                 int where, int size, u32 *value)
+ {
+-      void __iomem *base = ar71xx_pcicfg_base;
++      struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++      void __iomem *base = apc->cfg_base;
+       unsigned long flags;
+       u32 data;
+       int err;
+@@ -171,7 +188,7 @@ static int ar71xx_pci_read_config(struct
+       ret = PCIBIOS_SUCCESSFUL;
+       data = ~0;
+-      spin_lock_irqsave(&ar71xx_pci_lock, flags);
++      spin_lock_irqsave(&apc->lock, flags);
+       err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
+                                    AR71XX_PCI_CFG_CMD_READ);
+@@ -180,7 +197,7 @@ static int ar71xx_pci_read_config(struct
+       else
+               data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
+-      spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
++      spin_unlock_irqrestore(&apc->lock, flags);
+       *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
+@@ -190,7 +207,8 @@ static int ar71xx_pci_read_config(struct
+ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+                                  int where, int size, u32 value)
+ {
+-      void __iomem *base = ar71xx_pcicfg_base;
++      struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++      void __iomem *base = apc->cfg_base;
+       unsigned long flags;
+       int err;
+       int ret;
+@@ -198,7 +216,7 @@ static int ar71xx_pci_write_config(struc
+       value = value << (8 * (where & 3));
+       ret = PCIBIOS_SUCCESSFUL;
+-      spin_lock_irqsave(&ar71xx_pci_lock, flags);
++      spin_lock_irqsave(&apc->lock, flags);
+       err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
+                                    AR71XX_PCI_CFG_CMD_WRITE);
+@@ -207,7 +225,7 @@ static int ar71xx_pci_write_config(struc
+       else
+               __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
+-      spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
++      spin_unlock_irqrestore(&apc->lock, flags);
+       return ret;
+ }
+@@ -231,12 +249,6 @@ static struct resource ar71xx_pci_mem_re
+       .flags          = IORESOURCE_MEM
+ };
+-static struct pci_controller ar71xx_pci_controller = {
+-      .pci_ops        = &ar71xx_pci_ops,
+-      .mem_resource   = &ar71xx_pci_mem_resource,
+-      .io_resource    = &ar71xx_pci_io_resource,
+-};
+-
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+       void __iomem *base = ath79_reset_base;
+@@ -294,7 +306,7 @@ static struct irq_chip ar71xx_pci_irq_ch
+       .irq_mask_ack   = ar71xx_pci_irq_mask,
+ };
+-static void ar71xx_pci_irq_init(int irq)
++static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
+ {
+       void __iomem *base = ath79_reset_base;
+       int i;
+@@ -309,7 +321,7 @@ static void ar71xx_pci_irq_init(int irq)
+               irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+                                        handle_level_irq);
+-      irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
++      irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
+ }
+ static void ar71xx_pci_reset(void)
+@@ -336,20 +348,26 @@ static void ar71xx_pci_reset(void)
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
++      struct ar71xx_pci_controller *apc;
+       struct resource *res;
+-      int irq;
+       u32 t;
++      apc = kzalloc(sizeof(struct ar71xx_pci_controller), GFP_KERNEL);
++      if (!apc)
++              return -ENOMEM;
++
++      spin_lock_init(&apc->lock);
++
+       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
+       if (!res)
+               return -EINVAL;
+-      ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
+-      if (!ar71xx_pcicfg_base)
++      apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res);
++      if (!apc->cfg_base)
+               return -ENOMEM;
+-      irq = platform_get_irq(pdev, 0);
+-      if (irq < 0)
++      apc->irq = platform_get_irq(pdev, 0);
++      if (apc->irq < 0)
+               return -EINVAL;
+       ar71xx_pci_reset();
+@@ -357,14 +375,18 @@ static int ar71xx_pci_probe(struct platf
+       /* setup COMMAND register */
+       t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
+         | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
+-      ar71xx_pci_local_write(PCI_COMMAND, 4, t);
++      ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
+       /* clear bus errors */
+-      ar71xx_pci_check_error(1);
++      ar71xx_pci_check_error(apc, 1);
++
++      ar71xx_pci_irq_init(apc);
+-      ar71xx_pci_irq_init(irq);
++      apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
++      apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
++      apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
+-      register_pci_controller(&ar71xx_pci_controller);
++      register_pci_controller(&apc->pci_ctrl);
+       return 0;
+ }
diff --git a/target/linux/ar71xx/patches-3.8/154-MIPS-pci-ar71xx-remove-static-PCI-controller-resourc.patch b/target/linux/ar71xx/patches-3.8/154-MIPS-pci-ar71xx-remove-static-PCI-controller-resourc.patch
new file mode 100644 (file)
index 0000000..d17ad52
--- /dev/null
@@ -0,0 +1,70 @@
+From 7dc3ccb5dc972b06c41b309653d132beaaedeb37 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 25 Jun 2012 09:52:23 +0200
+Subject: [PATCH 15/34] MIPS: pci-ar71xx: remove static PCI controller resources
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c |   30 ++++++++++++++----------------
+ 1 files changed, 14 insertions(+), 16 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -54,6 +54,8 @@ struct ar71xx_pci_controller {
+       spinlock_t lock;
+       int irq;
+       struct pci_controller pci_ctrl;
++      struct resource io_res;
++      struct resource mem_res;
+ };
+ /* Byte lane enable bits */
+@@ -235,20 +237,6 @@ static struct pci_ops ar71xx_pci_ops = {
+       .write  = ar71xx_pci_write_config,
+ };
+-static struct resource ar71xx_pci_io_resource = {
+-      .name           = "PCI IO space",
+-      .start          = 0,
+-      .end            = 0,
+-      .flags          = IORESOURCE_IO,
+-};
+-
+-static struct resource ar71xx_pci_mem_resource = {
+-      .name           = "PCI memory space",
+-      .start          = AR71XX_PCI_MEM_BASE,
+-      .end            = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
+-      .flags          = IORESOURCE_MEM
+-};
+-
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+       void __iomem *base = ath79_reset_base;
+@@ -370,6 +358,16 @@ static int ar71xx_pci_probe(struct platf
+       if (apc->irq < 0)
+               return -EINVAL;
++      apc->io_res.name = "PCI IO space";
++      apc->io_res.start = 0;
++      apc->io_res.end = 0;
++      apc->io_res.flags = IORESOURCE_IO;
++
++      apc->mem_res.name = "PCI memory space";
++      apc->mem_res.start = AR71XX_PCI_MEM_BASE;
++      apc->mem_res.end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
++      apc->mem_res.flags = IORESOURCE_MEM;
++
+       ar71xx_pci_reset();
+       /* setup COMMAND register */
+@@ -383,8 +381,8 @@ static int ar71xx_pci_probe(struct platf
+       ar71xx_pci_irq_init(apc);
+       apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
+-      apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
+-      apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
++      apc->pci_ctrl.mem_resource = &apc->mem_res;
++      apc->pci_ctrl.io_resource = &apc->io_res;
+       register_pci_controller(&apc->pci_ctrl);
diff --git a/target/linux/ar71xx/patches-3.8/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch b/target/linux/ar71xx/patches-3.8/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch
new file mode 100644 (file)
index 0000000..7f1f230
--- /dev/null
@@ -0,0 +1,31 @@
+From 114df1e368b8503de1fe63e97d6eea521eecfbe4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:40:38 +0200
+Subject: [PATCH 16/34] MIPS: ath79: add early printk support for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/early_printk.c                 |    1 +
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
+ 2 files changed, 2 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -74,6 +74,7 @@ static void prom_putchar_init(void)
+       case REV_ID_MAJOR_AR9341:
+       case REV_ID_MAJOR_AR9342:
+       case REV_ID_MAJOR_AR9344:
++      case REV_ID_MAJOR_QCA9558:
+               _prom_putchar = prom_putchar_ar71xx;
+               break;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -370,6 +370,7 @@
+ #define REV_ID_MAJOR_AR9341           0x0120
+ #define REV_ID_MAJOR_AR9342           0x1120
+ #define REV_ID_MAJOR_AR9344           0x2120
++#define REV_ID_MAJOR_QCA9558          0x1130
+ #define AR71XX_REV_ID_MINOR_MASK      0x3
+ #define AR71XX_REV_ID_MINOR_AR7130    0x0
diff --git a/target/linux/ar71xx/patches-3.8/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch b/target/linux/ar71xx/patches-3.8/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch
new file mode 100644 (file)
index 0000000..1d9dd4b
--- /dev/null
@@ -0,0 +1,91 @@
+From 3c3c0eccf63b12fea98fd0eb65d0ccf69a7c5a57 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:42:16 +0200
+Subject: [PATCH 17/34] MIPS: ath79: add SoC detection code for the QCA9558 SoC
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/Kconfig                        |    4 ++++
+ arch/mips/ath79/setup.c                        |   12 +++++++++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ arch/mips/include/asm/mach-ath79/ath79.h       |   11 +++++++++++
+ 4 files changed, 28 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -88,6 +88,10 @@ config SOC_AR934X
+       select PCI_AR724X if PCI
+       def_bool n
++config SOC_QCA955X
++      select USB_ARCH_HAS_EHCI
++      def_bool n
++
+ config PCI_AR724X
+       def_bool n
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -164,13 +164,23 @@ static void __init ath79_detect_sys_type
+               rev = id & AR934X_REV_ID_REVISION_MASK;
+               break;
++      case REV_ID_MAJOR_QCA9558:
++              ath79_soc = ATH79_SOC_QCA9558;
++              chip = "9558";
++              rev = id & AR944X_REV_ID_REVISION_MASK;
++              break;
++
+       default:
+               panic("ath79: unknown SoC, id:0x%08x", id);
+       }
+       ath79_soc_rev = rev;
+-      sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
++      if (soc_is_qca955x())
++              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
++                      chip, rev);
++      else
++              sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
+       pr_info("SoC: %s\n", ath79_sys_type);
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -391,6 +391,8 @@
+ #define AR934X_REV_ID_REVISION_MASK     0xf
++#define AR944X_REV_ID_REVISION_MASK   0xf
++
+ /*
+  * SPI block
+  */
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -32,6 +32,7 @@ enum ath79_soc_type {
+       ATH79_SOC_AR9341,
+       ATH79_SOC_AR9342,
+       ATH79_SOC_AR9344,
++      ATH79_SOC_QCA9558,
+ };
+ extern enum ath79_soc_type ath79_soc;
+@@ -98,6 +99,16 @@ static inline int soc_is_ar934x(void)
+       return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+ }
++static inline int soc_is_qca9558(void)
++{
++      return ath79_soc == ATH79_SOC_QCA9558;
++}
++
++static inline int soc_is_qca955x(void)
++{
++      return soc_is_qca9558();
++}
++
+ extern void __iomem *ath79_ddr_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
diff --git a/target/linux/ar71xx/patches-3.8/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch
new file mode 100644 (file)
index 0000000..bb0924c
--- /dev/null
@@ -0,0 +1,167 @@
+From f465a16766a015a31d4e83af1ad62cc718d64f5a Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:43:08 +0200
+Subject: [PATCH 18/34] MIPS: ath79: add clock setup for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/clock.c                        |   78 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   39 ++++++++++++
+ 2 files changed, 117 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
+       iounmap(dpll_base);
+ }
++static void __init qca955x_clocks_init(void)
++{
++      u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
++      u32 cpu_pll, ddr_pll;
++      u32 bootstrap;
++
++      bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
++      if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
++              ath79_ref_clk.rate = 40 * 1000 * 1000;
++      else
++              ath79_ref_clk.rate = 25 * 1000 * 1000;
++
++      pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
++      out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
++                QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
++      ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
++                QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
++      nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
++             QCA955X_PLL_CPU_CONFIG_NINT_MASK;
++      frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
++             QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
++
++      cpu_pll = nint * ath79_ref_clk.rate / ref_div;
++      cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
++      cpu_pll /= (1 << out_div);
++
++      pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
++      out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
++                QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
++      ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
++                QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
++      nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
++             QCA955X_PLL_DDR_CONFIG_NINT_MASK;
++      frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
++             QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
++
++      ddr_pll = nint * ath79_ref_clk.rate / ref_div;
++      ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
++      ddr_pll /= (1 << out_div);
++
++      clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
++
++      postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
++                QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
++              ath79_cpu_clk.rate = ath79_ref_clk.rate;
++      else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
++              ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
++      else
++              ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
++
++      postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
++                QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
++              ath79_ddr_clk.rate = ath79_ref_clk.rate;
++      else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
++              ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
++      else
++              ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
++
++      postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
++                QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
++              ath79_ahb_clk.rate = ath79_ref_clk.rate;
++      else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
++              ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
++      else
++              ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
++
++      ath79_wdt_clk.rate = ath79_ref_clk.rate;
++      ath79_uart_clk.rate = ath79_ref_clk.rate;
++}
++
+ void __init ath79_clocks_init(void)
+ {
+       if (soc_is_ar71xx())
+@@ -307,6 +383,8 @@ void __init ath79_clocks_init(void)
+               ar933x_clocks_init();
+       else if (soc_is_ar934x())
+               ar934x_clocks_init();
++      else if (soc_is_qca955x())
++              qca955x_clocks_init();
+       else
+               BUG();
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -225,6 +225,41 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL        BIT(21)
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL        BIT(24)
++#define QCA955X_PLL_CPU_CONFIG_REG            0x00
++#define QCA955X_PLL_DDR_CONFIG_REG            0x04
++#define QCA955X_PLL_CLK_CTRL_REG              0x08
++
++#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT    0
++#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK     0x3f
++#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT     6
++#define QCA955X_PLL_CPU_CONFIG_NINT_MASK      0x3f
++#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT   12
++#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK    0x1f
++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT   19
++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK    0x3
++
++#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT    0
++#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK     0x3ff
++#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT     10
++#define QCA955X_PLL_DDR_CONFIG_NINT_MASK      0x3f
++#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT   16
++#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK    0x1f
++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT   23
++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK    0x7
++
++#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS           BIT(2)
++#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS           BIT(3)
++#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS           BIT(4)
++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT               5
++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK                0x1f
++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT               10
++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK                0x1f
++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT               15
++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK                0x1f
++#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL               BIT(20)
++#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
++#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
++
+ /*
+  * USB_CONFIG block
+  */
+@@ -264,6 +299,8 @@
+ #define AR934X_RESET_REG_BOOTSTRAP            0xb0
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
++#define QCA955X_RESET_REG_BOOTSTRAP           0xb0
++
+ #define MISC_INT_ETHSW                        BIT(12)
+ #define MISC_INT_TIMER4                       BIT(10)
+ #define MISC_INT_TIMER3                       BIT(9)
+@@ -341,6 +378,8 @@
+ #define AR934X_BOOTSTRAP_SDRAM_DISABLED       BIT(1)
+ #define AR934X_BOOTSTRAP_DDR1         BIT(0)
++#define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
++
+ #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
+ #define AR934X_PCIE_WMAC_INT_WMAC_TX          BIT(1)
+ #define AR934X_PCIE_WMAC_INT_WMAC_RXLP                BIT(2)
diff --git a/target/linux/ar71xx/patches-3.8/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch b/target/linux/ar71xx/patches-3.8/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
new file mode 100644 (file)
index 0000000..8d24c74
--- /dev/null
@@ -0,0 +1,239 @@
+From 5d0de52f8e36916485a61b820916b71b5d918e6f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:44:23 +0200
+Subject: [PATCH 19/34] MIPS: ath79: add IRQ handling code for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/irq.c                          |  110 ++++++++++++++++++++++--
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   32 +++++++
+ arch/mips/include/asm/mach-ath79/irq.h         |    9 ++-
+ 3 files changed, 142 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -130,7 +130,10 @@ static void __init ath79_misc_irq_init(v
+       if (soc_is_ar71xx() || soc_is_ar913x())
+               ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
+-      else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
++      else if (soc_is_ar724x() ||
++               soc_is_ar933x() ||
++               soc_is_ar934x() ||
++               soc_is_qca955x())
+               ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+       else
+               BUG();
+@@ -177,6 +180,88 @@ static void ar934x_ip2_irq_init(void)
+       irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
+ }
++static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++      u32 status;
++
++      disable_irq_nosync(irq);
++
++      status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
++      status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
++
++      if (status == 0) {
++              spurious_interrupt();
++              goto enable;
++      }
++
++      if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
++              /* TODO: flush DDR? */
++              generic_handle_irq(ATH79_IP2_IRQ(0));
++      }
++
++      if (status & QCA955X_EXT_INT_WMAC_ALL) {
++              /* TODO: flsuh DDR? */
++              generic_handle_irq(ATH79_IP2_IRQ(1));
++      }
++
++enable:
++      enable_irq(irq);
++}
++
++static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++      u32 status;
++
++      disable_irq_nosync(irq);
++
++      status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
++      status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
++                QCA955X_EXT_INT_USB1 |
++                QCA955X_EXT_INT_USB2;
++
++      if (status == 0) {
++              spurious_interrupt();
++              goto enable;
++      }
++
++      if (status & QCA955X_EXT_INT_USB1) {
++              /* TODO: flush DDR? */
++              generic_handle_irq(ATH79_IP3_IRQ(0));
++      }
++
++      if (status & QCA955X_EXT_INT_USB2) {
++              /* TODO: flsuh DDR? */
++              generic_handle_irq(ATH79_IP3_IRQ(1));
++      }
++
++      if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
++              /* TODO: flush DDR? */
++              generic_handle_irq(ATH79_IP3_IRQ(2));
++      }
++
++enable:
++      enable_irq(irq);
++}
++
++static void qca955x_irq_init(void)
++{
++      int i;
++
++      for (i = ATH79_IP2_IRQ_BASE;
++           i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
++              irq_set_chip_and_handler(i, &dummy_irq_chip,
++                                       handle_level_irq);
++
++      irq_set_chained_handler(ATH79_CPU_IRQ_IP2, qca955x_ip2_irq_dispatch);
++
++      for (i = ATH79_IP3_IRQ_BASE;
++           i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
++              irq_set_chip_and_handler(i, &dummy_irq_chip,
++                                       handle_level_irq);
++
++      irq_set_chained_handler(ATH79_CPU_IRQ_IP3, qca955x_ip3_irq_dispatch);
++}
++
+ asmlinkage void plat_irq_dispatch(void)
+ {
+       unsigned long pending;
+@@ -212,6 +297,17 @@ asmlinkage void plat_irq_dispatch(void)
+  * Issue a flush in the handlers to ensure that the driver sees
+  * the update.
+  */
++
++static void ath79_default_ip2_handler(void)
++{
++      do_IRQ(ATH79_CPU_IRQ_IP2);
++}
++
++static void ath79_default_ip3_handler(void)
++{
++      do_IRQ(ATH79_CPU_IRQ_USB);
++}
++
+ static void ar71xx_ip2_handler(void)
+ {
+       ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
+@@ -236,11 +332,6 @@ static void ar933x_ip2_handler(void)
+       do_IRQ(ATH79_CPU_IRQ_IP2);
+ }
+-static void ar934x_ip2_handler(void)
+-{
+-      do_IRQ(ATH79_CPU_IRQ_IP2);
+-}
+-
+ static void ar71xx_ip3_handler(void)
+ {
+       ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
+@@ -286,8 +377,11 @@ void __init arch_init_irq(void)
+               ath79_ip2_handler = ar933x_ip2_handler;
+               ath79_ip3_handler = ar933x_ip3_handler;
+       } else if (soc_is_ar934x()) {
+-              ath79_ip2_handler = ar934x_ip2_handler;
++              ath79_ip2_handler = ath79_default_ip2_handler;
+               ath79_ip3_handler = ar934x_ip3_handler;
++      } else if (soc_is_qca955x()) {
++              ath79_ip2_handler = ath79_default_ip2_handler;
++              ath79_ip3_handler = ath79_default_ip3_handler;
+       } else {
+               BUG();
+       }
+@@ -298,4 +392,6 @@ void __init arch_init_irq(void)
+       if (soc_is_ar934x())
+               ar934x_ip2_irq_init();
++      else if (soc_is_qca955x())
++              qca955x_irq_init();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -300,6 +300,7 @@
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+ #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
++#define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
+ #define MISC_INT_ETHSW                        BIT(12)
+ #define MISC_INT_TIMER4                       BIT(10)
+@@ -398,6 +399,37 @@
+        AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+        AR934X_PCIE_WMAC_INT_PCIE_RC3)
++#define QCA955X_EXT_INT_WMAC_MISC             BIT(0)
++#define QCA955X_EXT_INT_WMAC_TX                       BIT(1)
++#define QCA955X_EXT_INT_WMAC_RXLP             BIT(2)
++#define QCA955X_EXT_INT_WMAC_RXHP             BIT(3)
++#define QCA955X_EXT_INT_PCIE_RC1              BIT(4)
++#define QCA955X_EXT_INT_PCIE_RC1_INT0         BIT(5)
++#define QCA955X_EXT_INT_PCIE_RC1_INT1         BIT(6)
++#define QCA955X_EXT_INT_PCIE_RC1_INT2         BIT(7)
++#define QCA955X_EXT_INT_PCIE_RC1_INT3         BIT(8)
++#define QCA955X_EXT_INT_PCIE_RC2              BIT(12)
++#define QCA955X_EXT_INT_PCIE_RC2_INT0         BIT(13)
++#define QCA955X_EXT_INT_PCIE_RC2_INT1         BIT(14)
++#define QCA955X_EXT_INT_PCIE_RC2_INT2         BIT(15)
++#define QCA955X_EXT_INT_PCIE_RC2_INT3         BIT(16)
++#define QCA955X_EXT_INT_USB1                  BIT(24)
++#define QCA955X_EXT_INT_USB2                  BIT(28)
++
++#define QCA955X_EXT_INT_WMAC_ALL \
++      (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
++       QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
++
++#define QCA955X_EXT_INT_PCIE_RC1_ALL \
++      (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
++       QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
++       QCA955X_EXT_INT_PCIE_RC1_INT3)
++
++#define QCA955X_EXT_INT_PCIE_RC2_ALL \
++      (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
++       QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
++       QCA955X_EXT_INT_PCIE_RC2_INT3)
++
+ #define REV_ID_MAJOR_MASK             0xfff0
+ #define REV_ID_MAJOR_AR71XX           0x00a0
+ #define REV_ID_MAJOR_AR913X           0x00b0
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -10,7 +10,7 @@
+ #define __ASM_MACH_ATH79_IRQ_H
+ #define MIPS_CPU_IRQ_BASE     0
+-#define NR_IRQS                       48
++#define NR_IRQS                       51
+ #define ATH79_MISC_IRQ_BASE   8
+ #define ATH79_MISC_IRQ_COUNT  32
+@@ -23,8 +23,13 @@
+ #define ATH79_IP2_IRQ_COUNT   2
+ #define ATH79_IP2_IRQ(_x)     (ATH79_IP2_IRQ_BASE + (_x))
++#define ATH79_IP3_IRQ_BASE    (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
++#define ATH79_IP3_IRQ_COUNT     3
++#define ATH79_IP3_IRQ(_x)       (ATH79_IP3_IRQ_BASE + (_x))
++
+ #define ATH79_CPU_IRQ_IP2     (MIPS_CPU_IRQ_BASE + 2)
+-#define ATH79_CPU_IRQ_USB     (MIPS_CPU_IRQ_BASE + 3)
++#define ATH79_CPU_IRQ_IP3     (MIPS_CPU_IRQ_BASE + 3)
++#define ATH79_CPU_IRQ_USB     ATH79_CPU_IRQ_IP3
+ #define ATH79_CPU_IRQ_GE0     (MIPS_CPU_IRQ_BASE + 4)
+ #define ATH79_CPU_IRQ_GE1     (MIPS_CPU_IRQ_BASE + 5)
+ #define ATH79_CPU_IRQ_MISC    (MIPS_CPU_IRQ_BASE + 6)
diff --git a/target/linux/ar71xx/patches-3.8/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch
new file mode 100644 (file)
index 0000000..af91e2b
--- /dev/null
@@ -0,0 +1,39 @@
+From c9a552f3007f0621b2440ae17bad816578299e52 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:45:27 +0200
+Subject: [PATCH 20/34] MIPS: ath79: add GPIO setup code for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/gpio.c                         |    4 +++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
+ 2 files changed, 4 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -198,12 +198,14 @@ void __init ath79_gpio_init(void)
+               ath79_gpio_count = AR933X_GPIO_COUNT;
+       else if (soc_is_ar934x())
+               ath79_gpio_count = AR934X_GPIO_COUNT;
++      else if (soc_is_qca955x())
++              ath79_gpio_count = QCA955X_GPIO_COUNT;
+       else
+               BUG();
+       ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+       ath79_gpio_chip.ngpio = ath79_gpio_count;
+-      if (soc_is_ar934x()) {
++      if (soc_is_ar934x() || soc_is_qca955x()) {
+               ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
+               ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
+       }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -507,6 +507,7 @@
+ #define AR913X_GPIO_COUNT             22
+ #define AR933X_GPIO_COUNT             30
+ #define AR934X_GPIO_COUNT             23
++#define QCA955X_GPIO_COUNT            24
+ /*
+  * SRIF block
diff --git a/target/linux/ar71xx/patches-3.8/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch b/target/linux/ar71xx/patches-3.8/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch
new file mode 100644 (file)
index 0000000..f3e3b6e
--- /dev/null
@@ -0,0 +1,31 @@
+From 68368e80b4db83afe39664a7d43c8b5c7b8ac3b4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:49:33 +0200
+Subject: [PATCH 21/34] MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set,clear}
+
+---
+ arch/mips/ath79/common.c |    6 ++++--
+ 1 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -70,7 +70,8 @@ void ath79_device_reset_set(u32 mask)
+               reg = AR913X_RESET_REG_RESET_MODULE;
+       else if (soc_is_ar933x())
+               reg = AR933X_RESET_REG_RESET_MODULE;
+-      else if (soc_is_ar934x())
++      else if (soc_is_ar934x() ||
++               soc_is_qca955x())
+               reg = AR934X_RESET_REG_RESET_MODULE;
+       else
+               BUG();
+@@ -96,7 +97,8 @@ void ath79_device_reset_clear(u32 mask)
+               reg = AR913X_RESET_REG_RESET_MODULE;
+       else if (soc_is_ar933x())
+               reg = AR933X_RESET_REG_RESET_MODULE;
+-      else if (soc_is_ar934x())
++      else if (soc_is_ar934x() ||
++               soc_is_qca955x())
+               reg = AR934X_RESET_REG_RESET_MODULE;
+       else
+               BUG();
diff --git a/target/linux/ar71xx/patches-3.8/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.8/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch
new file mode 100644 (file)
index 0000000..aacb8bb
--- /dev/null
@@ -0,0 +1,22 @@
+From f7d7b362b51c51c1ae80bb7ade2039d6f74d4070 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:46:26 +0200
+Subject: [PATCH 22/34] MIPS: ath79: register UART for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/dev-common.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -90,7 +90,8 @@ void __init ath79_register_uart(void)
+       if (soc_is_ar71xx() ||
+           soc_is_ar724x() ||
+           soc_is_ar913x() ||
+-          soc_is_ar934x()) {
++          soc_is_ar934x() ||
++          soc_is_qca955x()) {
+               ath79_uart_data[0].uartclk = clk_get_rate(clk);
+               platform_device_register(&ath79_uart_device);
+       } else if (soc_is_ar933x()) {
diff --git a/target/linux/ar71xx/patches-3.8/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.8/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch
new file mode 100644 (file)
index 0000000..c0d8857
--- /dev/null
@@ -0,0 +1,93 @@
+From e4ba5e2bffd1f373f57dd692233aa6b7b46ae76c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:47:35 +0200
+Subject: [PATCH 23/34] MIPS: ath79: add USB controller registration code for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/dev-usb.c                      |   46 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    4 ++
+ 2 files changed, 50 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -73,6 +73,8 @@ static void __init ath79_usb_init_resour
+                                          unsigned long size,
+                                          int irq)
+ {
++      memset(res, 0, sizeof(res));
++
+       res[0].flags = IORESOURCE_MEM;
+       res[0].start = base;
+       res[0].end = base + size - 1;
+@@ -217,6 +219,48 @@ static void __init ar934x_usb_setup(void
+       platform_device_register(&ath79_ehci_device);
+ }
++static void __init qca955x_usb_setup(void)
++{
++      struct platform_device *pdev;
++
++      ath79_usb_init_resource(ath79_ehci_resources,
++                              QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
++                              ATH79_IP3_IRQ(0));
++
++      pdev = platform_device_register_resndata(NULL, "ehci-platform", 0,
++                                               ath79_ehci_resources,
++                                               ARRAY_SIZE(ath79_ehci_resources),
++                                               &ath79_ehci_pdata_v2,
++                                               sizeof(ath79_ehci_pdata_v2));
++      if (IS_ERR(pdev)) {
++              pr_err("Unable to register USB %d device, err=%d\n", 0,
++                      (int) PTR_ERR(pdev));
++              return;
++      }
++
++      pdev->dev.dma_mask = &ath79_ehci_dmamask;
++      pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++
++      ath79_usb_init_resource(ath79_ehci_resources,
++                              QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
++                              ATH79_IP3_IRQ(1));
++
++      pdev = platform_device_register_resndata(NULL, "ehci-platform", 1,
++                                               ath79_ehci_resources,
++                                               ARRAY_SIZE(ath79_ehci_resources),
++                                               &ath79_ehci_pdata_v2,
++                                               sizeof(ath79_ehci_pdata_v2));
++
++      if (IS_ERR(pdev)) {
++              pr_err("Unable to register USB %d device, err=%d\n", 1,
++                      (int) PTR_ERR(pdev));
++              return;
++      }
++
++      pdev->dev.dma_mask = &ath79_ehci_dmamask;
++      pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++}
++
+ void __init ath79_register_usb(void)
+ {
+       if (soc_is_ar71xx())
+@@ -231,6 +275,8 @@ void __init ath79_register_usb(void)
+               ar933x_usb_setup();
+       else if (soc_is_ar934x())
+               ar934x_usb_setup();
++      else if (soc_is_qca955x())
++              qca955x_usb_setup();
+       else
+               BUG();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -94,6 +94,10 @@
+ #define AR934X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE      0x1000
++#define QCA955X_EHCI0_BASE    0x1b000000
++#define QCA955X_EHCI1_BASE    0x1b400000
++#define QCA955X_EHCI_SIZE     0x200
++
+ /*
+  * DDR_CTRL block
+  */
diff --git a/target/linux/ar71xx/patches-3.8/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch b/target/linux/ar71xx/patches-3.8/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch
new file mode 100644 (file)
index 0000000..efc354e
--- /dev/null
@@ -0,0 +1,70 @@
+From 0568e7f92ecf2bfd2af0a5c59b1249fef002c89f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 3 Jul 2012 10:24:43 +0200
+Subject: [PATCH 24/34] MIPS: ath79: add WMAC registration code for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/Kconfig                        |    2 +-
+ arch/mips/ath79/dev-wmac.c                     |   20 ++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ 3 files changed, 23 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -108,7 +108,7 @@ config ATH79_DEV_USB
+       def_bool n
+ config ATH79_DEV_WMAC
+-      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
++      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
+       def_bool n
+ endif
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void)
+               ath79_wmac_data.is_clk_25mhz = true;
+ }
++static void qca955x_wmac_setup(void)
++{
++      u32 t;
++
++      ath79_wmac_device.name = "qca955x_wmac";
++
++      ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
++      ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
++      ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++      ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++
++      t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
++      if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
++              ath79_wmac_data.is_clk_25mhz = false;
++      else
++              ath79_wmac_data.is_clk_25mhz = true;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data)
+ {
+       if (soc_is_ar913x())
+@@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_
+               ar933x_wmac_setup();
+       else if (soc_is_ar934x())
+               ar934x_wmac_setup();
++      else if (soc_is_qca955x())
++              qca955x_wmac_setup();
+       else
+               BUG();
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -94,6 +94,8 @@
+ #define AR934X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE      0x1000
++#define QCA955X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
++#define QCA955X_WMAC_SIZE     0x20000
+ #define QCA955X_EHCI0_BASE    0x1b000000
+ #define QCA955X_EHCI1_BASE    0x1b400000
+ #define QCA955X_EHCI_SIZE     0x200
diff --git a/target/linux/ar71xx/patches-3.8/169-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch b/target/linux/ar71xx/patches-3.8/169-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch
new file mode 100644 (file)
index 0000000..bd95d71
--- /dev/null
@@ -0,0 +1,34 @@
+From 12c68e4fccadc22a0470177141a57892a76e4a2b Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 15:33:16 +0200
+Subject: [PATCH 25/34] MIPS: ath79: allow to specify bus number in PCI IRQ maps
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/pci.c |    4 +++-
+ arch/mips/ath79/pci.h |    1 +
+ 2 files changed, 4 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -75,7 +75,9 @@ int __init pcibios_map_irq(const struct
+               const struct ath79_pci_irq *entry;
+               entry = &ath79_pci_irq_map[i];
+-              if (entry->slot == slot && entry->pin == pin) {
++              if (entry->bus == dev->bus->number &&
++                  entry->slot == slot &&
++                  entry->pin == pin) {
+                       irq = entry->irq;
+                       break;
+               }
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -14,6 +14,7 @@
+ #define _ATH79_PCI_H
+ struct ath79_pci_irq {
++      int     bus;
+       u8      slot;
+       u8      pin;
+       int     irq;
diff --git a/target/linux/ar71xx/patches-3.8/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.8/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
new file mode 100644 (file)
index 0000000..0c3889f
--- /dev/null
@@ -0,0 +1,103 @@
+From 8bb54348722216a1dd6905d9d031ebdaa3a544a4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 23:05:20 +0200
+Subject: [PATCH 26/34] MIPS: ath79: add PCI controller registration code for the QCA9558 SoC
+
+---
+ arch/mips/ath79/Kconfig                        |    2 +
+ arch/mips/ath79/pci.c                          |   36 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   13 ++++++++
+ 3 files changed, 51 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -90,6 +90,8 @@ config SOC_AR934X
+ config SOC_QCA955X
+       select USB_ARCH_HAS_EHCI
++      select HW_HAS_PCI
++      select PCI_AR724X if PCI
+       def_bool n
+ config PCI_AR724X
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x
+       }
+ };
++static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
++      {
++              .bus    = 0,
++              .slot   = 0,
++              .pin    = 1,
++              .irq    = ATH79_PCI_IRQ(0),
++      },
++      {
++              .bus    = 1,
++              .slot   = 0,
++              .pin    = 1,
++              .irq    = ATH79_PCI_IRQ(1),
++      },
++};
++
+ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+ {
+       int irq = -1;
+@@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct
+                          soc_is_ar9344()) {
+                       ath79_pci_irq_map = ar724x_pci_irq_map;
+                       ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
++              } else if (soc_is_qca955x()) {
++                      ath79_pci_irq_map = qca955x_pci_irq_map;
++                      ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
+               } else {
+                       pr_crit("pci %s: invalid irq map\n",
+                               pci_name((struct pci_dev *) dev));
+@@ -215,6 +233,24 @@ int __init ath79_register_pci(void)
+                                                AR724X_PCI_MEM_SIZE,
+                                                0,
+                                                ATH79_IP2_IRQ(0));
++      } else if (soc_is_qca9558()) {
++              pdev = ath79_register_pci_ar724x(0,
++                                               QCA955X_PCI_CFG_BASE0,
++                                               QCA955X_PCI_CTRL_BASE0,
++                                               QCA955X_PCI_CRP_BASE0,
++                                               QCA955X_PCI_MEM_BASE0,
++                                               QCA955X_PCI_MEM_SIZE,
++                                               0,
++                                               ATH79_IP2_IRQ(0));
++
++              pdev = ath79_register_pci_ar724x(1,
++                                               QCA955X_PCI_CFG_BASE1,
++                                               QCA955X_PCI_CTRL_BASE1,
++                                               QCA955X_PCI_CRP_BASE1,
++                                               QCA955X_PCI_MEM_BASE1,
++                                               QCA955X_PCI_MEM_SIZE,
++                                               1,
++                                               ATH79_IP3_IRQ(2));
+       } else {
+               /* No PCI support */
+               return -ENODEV;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -94,6 +94,19 @@
+ #define AR934X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE      0x1000
++#define QCA955X_PCI_MEM_BASE0 0x10000000
++#define QCA955X_PCI_MEM_BASE1 0x12000000
++#define QCA955X_PCI_MEM_SIZE  0x02000000
++#define QCA955X_PCI_CFG_BASE0 0x14000000
++#define QCA955X_PCI_CFG_BASE1 0x16000000
++#define QCA955X_PCI_CFG_SIZE  0x1000
++#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
++#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
++#define QCA955X_PCI_CRP_SIZE  0x1000
++#define QCA955X_PCI_CTRL_BASE0        (AR71XX_APB_BASE + 0x000f0000)
++#define QCA955X_PCI_CTRL_BASE1        (AR71XX_APB_BASE + 0x00280000)
++#define QCA955X_PCI_CTRL_SIZE 0x100
++
+ #define QCA955X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE     0x20000
+ #define QCA955X_EHCI0_BASE    0x1b000000
diff --git a/target/linux/ar71xx/patches-3.8/171-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch b/target/linux/ar71xx/patches-3.8/171-MIPS-ath79-add-support-for-the-Qualcomm-Atheros-AP13.patch
new file mode 100644 (file)
index 0000000..dc26f9c
--- /dev/null
@@ -0,0 +1,213 @@
+From a034da3e4d4960266a94d15c811d5f4529fdff44 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:52:23 +0200
+Subject: [PATCH 27/34] MIPS: ath79: add support for the Qualcomm Atheros AP136 board
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/Kconfig      |   12 +++
+ arch/mips/ath79/Makefile     |    1 +
+ arch/mips/ath79/mach-ap136.c |  155 ++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ath79/machtypes.h  |    1 +
+ 4 files changed, 169 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/ath79/mach-ap136.c
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -14,6 +14,18 @@ config ATH79_MACH_AP121
+         Say 'Y' here if you want your kernel to support the
+         Atheros AP121 reference board.
++config ATH79_MACH_AP136
++      bool "Atheros AP136 reference board"
++      select SOC_QCA955X
++      select ATH79_DEV_GPIO_BUTTONS
++      select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_SPI
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
++      help
++        Say 'Y' here if you want your kernel to support the
++        Atheros AP136 reference board.
++
+ config ATH79_MACH_AP81
+       bool "Atheros AP81 reference board"
+       select SOC_AR913X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC)         += dev-wma
+ # Machines
+ #
+ obj-$(CONFIG_ATH79_MACH_AP121)                += mach-ap121.o
++obj-$(CONFIG_ATH79_MACH_AP136)                += mach-ap136.o
+ obj-$(CONFIG_ATH79_MACH_AP81)         += mach-ap81.o
+ obj-$(CONFIG_ATH79_MACH_DB120)                += mach-db120.o
+ obj-$(CONFIG_ATH79_MACH_PB44)         += mach-pb44.o
+--- /dev/null
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -0,0 +1,155 @@
++/*
++ * Qualcomm Atheros AP136 reference board support
++ *
++ * Copyright (c) 2012 Qualcomm Atheros
++ * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ *
++ */
++
++#include <linux/pci.h>
++#include <linux/ath9k_platform.h>
++
++#include "machtypes.h"
++#include "dev-gpio-buttons.h"
++#include "dev-leds-gpio.h"
++#include "dev-spi.h"
++#include "dev-usb.h"
++#include "dev-wmac.h"
++#include "pci.h"
++
++#define AP136_GPIO_LED_STATUS_RED     14
++#define AP136_GPIO_LED_STATUS_GREEN   19
++#define AP136_GPIO_LED_USB            4
++#define AP136_GPIO_LED_WLAN_2G                13
++#define AP136_GPIO_LED_WLAN_5G                12
++#define AP136_GPIO_LED_WPS_RED                15
++#define AP136_GPIO_LED_WPS_GREEN      20
++
++#define AP136_GPIO_BTN_WPS            16
++#define AP136_GPIO_BTN_RFKILL         21
++
++#define AP136_KEYS_POLL_INTERVAL      20      /* msecs */
++#define AP136_KEYS_DEBOUNCE_INTERVAL  (3 * AP136_KEYS_POLL_INTERVAL)
++
++#define AP136_WMAC_CALDATA_OFFSET 0x1000
++#define AP136_PCIE_CALDATA_OFFSET 0x5000
++
++static struct gpio_led ap136_leds_gpio[] __initdata = {
++      {
++              .name           = "ap136:green:status",
++              .gpio           = AP136_GPIO_LED_STATUS_GREEN,
++              .active_low     = 1,
++      },
++      {
++              .name           = "ap136:red:status",
++              .gpio           = AP136_GPIO_LED_STATUS_RED,
++              .active_low     = 1,
++      },
++      {
++              .name           = "ap136:green:wps",
++              .gpio           = AP136_GPIO_LED_WPS_GREEN,
++              .active_low     = 1,
++      },
++      {
++              .name           = "ap136:red:wps",
++              .gpio           = AP136_GPIO_LED_WPS_RED,
++              .active_low     = 1,
++      },
++      {
++              .name           = "ap136:red:wlan-2g",
++              .gpio           = AP136_GPIO_LED_WLAN_2G,
++              .active_low     = 1,
++      },
++      {
++              .name           = "ap136:red:usb",
++              .gpio           = AP136_GPIO_LED_USB,
++              .active_low     = 1,
++      }
++};
++
++static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
++      {
++              .desc           = "WPS button",
++              .type           = EV_KEY,
++              .code           = KEY_WPS_BUTTON,
++              .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
++              .gpio           = AP136_GPIO_BTN_WPS,
++              .active_low     = 1,
++      },
++      {
++              .desc           = "RFKILL button",
++              .type           = EV_KEY,
++              .code           = KEY_RFKILL,
++              .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
++              .gpio           = AP136_GPIO_BTN_RFKILL,
++              .active_low     = 1,
++      },
++};
++
++static struct spi_board_info ap136_spi_info[] = {
++      {
++              .bus_num        = 0,
++              .chip_select    = 0,
++              .max_speed_hz   = 25000000,
++              .modalias       = "mx25l6405d",
++      }
++};
++
++static struct ath79_spi_platform_data ap136_spi_data = {
++      .bus_num        = 0,
++      .num_chipselect = 1,
++};
++
++#ifdef CONFIG_PCI
++static struct ath9k_platform_data ap136_ath9k_data;
++
++static int ap136_pci_plat_dev_init(struct pci_dev *dev)
++{
++      if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
++              dev->dev.platform_data = &ap136_ath9k_data;
++
++      return 0;
++}
++
++static void __init ap136_pci_init(u8 *eeprom)
++{
++      memcpy(ap136_ath9k_data.eeprom_data, eeprom,
++             sizeof(ap136_ath9k_data.eeprom_data));
++
++      ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
++      ath79_register_pci();
++}
++#else
++static inline void ap136_pci_init(void) {}
++#endif /* CONFIG_PCI */
++
++static void __init ap136_setup(void)
++{
++      u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
++      ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
++                               ap136_leds_gpio);
++      ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
++                                      ARRAY_SIZE(ap136_gpio_keys),
++                                      ap136_gpio_keys);
++      ath79_register_spi(&ap136_spi_data, ap136_spi_info,
++                         ARRAY_SIZE(ap136_spi_info));
++      ath79_register_usb();
++      ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
++      ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
++}
++
++MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",
++           ap136_setup);
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -17,6 +17,7 @@
+ enum ath79_mach_type {
+       ATH79_MACH_GENERIC = 0,
+       ATH79_MACH_AP121,               /* Atheros AP121 reference board */
++      ATH79_MACH_AP136,               /* Atheros AP136 reference board */
+       ATH79_MACH_AP81,                /* Atheros AP81 reference board */
+       ATH79_MACH_DB120,               /* Atheros DB120 reference board */
+       ATH79_MACH_PB44,                /* Atheros PB44 reference board */
diff --git a/target/linux/ar71xx/patches-3.8/172-MIPS-ath79-add-support-for-the-QCA9556-SoC.patch b/target/linux/ar71xx/patches-3.8/172-MIPS-ath79-add-support-for-the-QCA9556-SoC.patch
new file mode 100644 (file)
index 0000000..2d039cb
--- /dev/null
@@ -0,0 +1,56 @@
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -164,6 +164,12 @@ static void __init ath79_detect_sys_type
+               rev = id & AR934X_REV_ID_REVISION_MASK;
+               break;
++      case REV_ID_MAJOR_QCA9556:
++              ath79_soc = ATH79_SOC_QCA9556;
++              chip = "9556";
++              rev = id & AR944X_REV_ID_REVISION_MASK;
++              break;
++
+       case REV_ID_MAJOR_QCA9558:
+               ath79_soc = ATH79_SOC_QCA9558;
+               chip = "9558";
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -460,6 +460,7 @@
+ #define REV_ID_MAJOR_AR9341           0x0120
+ #define REV_ID_MAJOR_AR9342           0x1120
+ #define REV_ID_MAJOR_AR9344           0x2120
++#define REV_ID_MAJOR_QCA9556          0x0130
+ #define REV_ID_MAJOR_QCA9558          0x1130
+ #define AR71XX_REV_ID_MINOR_MASK      0x3
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -32,6 +32,7 @@ enum ath79_soc_type {
+       ATH79_SOC_AR9341,
+       ATH79_SOC_AR9342,
+       ATH79_SOC_AR9344,
++      ATH79_SOC_QCA9556,
+       ATH79_SOC_QCA9558,
+ };
+@@ -99,6 +100,11 @@ static inline int soc_is_ar934x(void)
+       return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+ }
++static inline int soc_is_qca9556(void)
++{
++      return ath79_soc == ATH79_SOC_QCA9556;
++}
++
+ static inline int soc_is_qca9558(void)
+ {
+       return ath79_soc == ATH79_SOC_QCA9558;
+@@ -106,7 +112,7 @@ static inline int soc_is_qca9558(void)
+ static inline int soc_is_qca955x(void)
+ {
+-      return soc_is_qca9558();
++      return soc_is_qca9556() || soc_is_qca9558();
+ }
+ extern void __iomem *ath79_ddr_base;
diff --git a/target/linux/ar71xx/patches-3.8/200-spi-ath79-add-delay-between-SCK-changes.patch b/target/linux/ar71xx/patches-3.8/200-spi-ath79-add-delay-between-SCK-changes.patch
new file mode 100644 (file)
index 0000000..7db744a
--- /dev/null
@@ -0,0 +1,122 @@
+From cbb3ade4765bc715b5c2eae4a7b6eaf3ff7ad958 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 11 Jan 2012 20:06:35 +0100
+Subject: [PATCH 28/34] spi/ath79: add delay between SCK changes
+
+The driver uses the "as fast as it can" approach
+to drive the SCK signal. However this does not
+work with certain low speed SPI chips (e.g. the
+PCF2123 RTC chip). Add per-bit slowdowns in order
+to be able to use the driver with such chips as
+well.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c |   44 +++++++++++++++++++++++++++++++++++++++++++-
+ 1 files changed, 43 insertions(+), 1 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -24,17 +24,24 @@
+ #include <linux/spi/spi_bitbang.h>
+ #include <linux/bitops.h>
+ #include <linux/gpio.h>
++#include <linux/clk.h>
++#include <linux/err.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79_spi_platform.h>
+ #define DRV_NAME      "ath79-spi"
++#define ATH79_SPI_RRW_DELAY_FACTOR    12000
++#define MHZ                           (1000 * 1000)
++
+ struct ath79_spi {
+       struct spi_bitbang      bitbang;
+       u32                     ioc_base;
+       u32                     reg_ctrl;
+       void __iomem            *base;
++      struct clk              *clk;
++      unsigned                rrw_delay;
+ };
+ static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
+@@ -52,6 +59,12 @@ static inline struct ath79_spi *ath79_sp
+       return spi_master_get_devdata(spi->master);
+ }
++static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
++{
++      if (nsecs > sp->rrw_delay)
++              ndelay(nsecs - sp->rrw_delay);
++}
++
+ static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
+ {
+       struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+@@ -184,7 +197,9 @@ static u32 ath79_spi_txrx_mode0(struct s
+               /* setup MSB (to slave) on trailing edge */
+               ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
++              ath79_spi_delay(sp, nsecs);
+               ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
++              ath79_spi_delay(sp, nsecs);
+               word <<= 1;
+       }
+@@ -198,6 +213,7 @@ static int ath79_spi_probe(struct platfo
+       struct ath79_spi *sp;
+       struct ath79_spi_platform_data *pdata;
+       struct resource *r;
++      unsigned long rate;
+       int ret;
+       master = spi_alloc_master(&pdev->dev, sizeof(*sp));
+@@ -236,12 +252,36 @@ static int ath79_spi_probe(struct platfo
+               goto err_put_master;
+       }
++      sp->clk = clk_get(&pdev->dev, "ahb");
++      if (IS_ERR(sp->clk)) {
++              ret = PTR_ERR(sp->clk);
++              goto err_unmap;
++      }
++
++      ret = clk_enable(sp->clk);
++      if (ret)
++              goto err_clk_put;
++
++      rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
++      if (!rate) {
++              ret = -EINVAL;
++              goto err_clk_disable;
++      }
++
++      sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
++      dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
++              sp->rrw_delay);
++
+       ret = spi_bitbang_start(&sp->bitbang);
+       if (ret)
+-              goto err_unmap;
++              goto err_clk_disable;
+       return 0;
++err_clk_disable:
++      clk_disable(sp->clk);
++err_clk_put:
++      clk_put(sp->clk);
+ err_unmap:
+       iounmap(sp->base);
+ err_put_master:
+@@ -256,6 +296,8 @@ static int ath79_spi_remove(struct platf
+       struct ath79_spi *sp = platform_get_drvdata(pdev);
+       spi_bitbang_stop(&sp->bitbang);
++      clk_disable(sp->clk);
++      clk_put(sp->clk);
+       iounmap(sp->base);
+       platform_set_drvdata(pdev, NULL);
+       spi_master_put(sp->bitbang.master);
diff --git a/target/linux/ar71xx/patches-3.8/201-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch b/target/linux/ar71xx/patches-3.8/201-spi-ath79-add-missing-HIGH-LOW-SCK-transition.patch
new file mode 100644 (file)
index 0000000..fd3d968
--- /dev/null
@@ -0,0 +1,21 @@
+From bcb0fdebc08f828b54d0a2eb74a9d1378701a8e0 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 11 Jan 2012 20:33:41 +0100
+Subject: [PATCH 29/34] spi/ath79: add missing HIGH->LOW SCK transition
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c |    2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -200,6 +200,8 @@ static u32 ath79_spi_txrx_mode0(struct s
+               ath79_spi_delay(sp, nsecs);
+               ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
+               ath79_spi_delay(sp, nsecs);
++              if (bits == 1)
++                      ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
+               word <<= 1;
+       }
diff --git a/target/linux/ar71xx/patches-3.8/202-spi-ath79-remove-superfluous-chip-select-code.patch b/target/linux/ar71xx/patches-3.8/202-spi-ath79-remove-superfluous-chip-select-code.patch
new file mode 100644 (file)
index 0000000..eec3293
--- /dev/null
@@ -0,0 +1,30 @@
+From 06752f9b169493cd1323f8337c147ad2dd31025c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 9 Jan 2012 15:03:28 +0100
+Subject: [PATCH 30/34] spi/ath79: remove superfluous chip select code
+
+The spi_bitbang driver calls the chipselect function
+of the driver from spi_bitbang_setup in order to
+deselect the given SPI chip, so we don't have to
+initialize the CS line here.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c |    6 ------
+ 1 files changed, 0 insertions(+), 6 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -128,12 +128,6 @@ static int ath79_spi_setup_cs(struct spi
+                       gpio_free(cdata->gpio);
+                       return status;
+               }
+-      } else {
+-              if (spi->mode & SPI_CS_HIGH)
+-                      sp->ioc_base |= AR71XX_SPI_IOC_CS0;
+-              else
+-                      sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
+-              ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+       }
+       return 0;
diff --git a/target/linux/ar71xx/patches-3.8/203-spi-ath79-use-gpio_request_one.patch b/target/linux/ar71xx/patches-3.8/203-spi-ath79-use-gpio_request_one.patch
new file mode 100644 (file)
index 0000000..12559bc
--- /dev/null
@@ -0,0 +1,56 @@
+From 6bd876a46b977643f27d2cc63f49e1bc84b78134 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 9 Jan 2012 15:04:21 +0100
+Subject: [PATCH 31/34] spi/ath79: use gpio_request_one
+
+Use gpio_request_one() instead of multiple gpiolib calls.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c |   26 +++++++++++++-------------
+ 1 files changed, 13 insertions(+), 13 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -100,6 +100,7 @@ static int ath79_spi_setup_cs(struct spi
+ {
+       struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+       struct ath79_spi_controller_data *cdata;
++      int status;
+       cdata = spi->controller_data;
+       if (spi->chip_select && !cdata)
+@@ -115,22 +116,21 @@ static int ath79_spi_setup_cs(struct spi
+       /* TODO: setup speed? */
+       ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
++      status = 0;
+       if (spi->chip_select) {
+-              int status = 0;
++              unsigned long flags;
+-              status = gpio_request(cdata->gpio, dev_name(&spi->dev));
+-              if (status)
+-                      return status;
+-
+-              status = gpio_direction_output(cdata->gpio,
+-                                             spi->mode & SPI_CS_HIGH);
+-              if (status) {
+-                      gpio_free(cdata->gpio);
+-                      return status;
+-              }
++              flags = GPIOF_DIR_OUT;
++              if (spi->mode & SPI_CS_HIGH)
++                      flags |= GPIOF_INIT_HIGH;
++              else
++                      flags |= GPIOF_INIT_LOW;
++
++              status = gpio_request_one(cdata->gpio, flags,
++                                        dev_name(&spi->dev));
+       }
+-      return 0;
++      return status;
+ }
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
diff --git a/target/linux/ar71xx/patches-3.8/204-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch b/target/linux/ar71xx/patches-3.8/204-spi-ath79-avoid-multiple-initialization-of-the-SPI-c.patch
new file mode 100644 (file)
index 0000000..e69b9b3
--- /dev/null
@@ -0,0 +1,108 @@
+From e63ceaa0c4f7be0498cd452981073d3ce8e7d1f5 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 9 Jan 2012 15:00:46 +0100
+Subject: [PATCH 32/34] spi/ath79: avoid multiple initialization of the SPI controller
+
+Currently we are initializing the SPI controller in
+the chip select line function, and that function is
+called once for each SPI device on the bus. If a
+board has multiple SPI devices, the controller will
+be initialized multiple times.
+
+Introduce ath79_spi_{en,dis}able helper functions,
+and call those from probe/response in order to avoid
+the mutliple initialization of the controller.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c |   41 ++++++++++++++++++++++++-----------------
+ 1 files changed, 24 insertions(+), 17 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -96,16 +96,8 @@ static void ath79_spi_chipselect(struct
+ }
+-static int ath79_spi_setup_cs(struct spi_device *spi)
++static void ath79_spi_enable(struct ath79_spi *sp)
+ {
+-      struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+-      struct ath79_spi_controller_data *cdata;
+-      int status;
+-
+-      cdata = spi->controller_data;
+-      if (spi->chip_select && !cdata)
+-              return -EINVAL;
+-
+       /* enable GPIO mode */
+       ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
+@@ -115,6 +107,24 @@ static int ath79_spi_setup_cs(struct spi
+       /* TODO: setup speed? */
+       ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
++}
++
++static void ath79_spi_disable(struct ath79_spi *sp)
++{
++      /* restore CTRL register */
++      ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
++      /* disable GPIO mode */
++      ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++}
++
++static int ath79_spi_setup_cs(struct spi_device *spi)
++{
++      struct ath79_spi_controller_data *cdata;
++      int status;
++
++      cdata = spi->controller_data;
++      if (spi->chip_select && !cdata)
++              return -EINVAL;
+       status = 0;
+       if (spi->chip_select) {
+@@ -135,17 +145,10 @@ static int ath79_spi_setup_cs(struct spi
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
+ {
+-      struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+-
+       if (spi->chip_select) {
+               struct ath79_spi_controller_data *cdata = spi->controller_data;
+               gpio_free(cdata->gpio);
+       }
+-
+-      /* restore CTRL register */
+-      ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
+-      /* disable GPIO mode */
+-      ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
+ }
+ static int ath79_spi_setup(struct spi_device *spi)
+@@ -268,12 +271,15 @@ static int ath79_spi_probe(struct platfo
+       dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
+               sp->rrw_delay);
++      ath79_spi_enable(sp);
+       ret = spi_bitbang_start(&sp->bitbang);
+       if (ret)
+-              goto err_clk_disable;
++              goto err_disable;
+       return 0;
++err_disable:
++      ath79_spi_disable(sp);
+ err_clk_disable:
+       clk_disable(sp->clk);
+ err_clk_put:
+@@ -292,6 +298,7 @@ static int ath79_spi_remove(struct platf
+       struct ath79_spi *sp = platform_get_drvdata(pdev);
+       spi_bitbang_stop(&sp->bitbang);
++      ath79_spi_disable(sp);
+       clk_disable(sp->clk);
+       clk_put(sp->clk);
+       iounmap(sp->base);
diff --git a/target/linux/ar71xx/patches-3.8/205-spi-ath79-add-shutdown-handler.patch b/target/linux/ar71xx/patches-3.8/205-spi-ath79-add-shutdown-handler.patch
new file mode 100644 (file)
index 0000000..fc54923
--- /dev/null
@@ -0,0 +1,28 @@
+From dab305def68a9ea28c1c0ca2fc20bba645944914 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 11 Jan 2012 22:19:32 +0100
+Subject: [PATCH 33/34] spi/ath79: add shutdown handler
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c |   12 +++++++++++-
+ 1 files changed, 11 insertions(+), 1 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -308,9 +308,15 @@ static int ath79_spi_remove(struct platf
+       return 0;
+ }
++static void ath79_spi_shutdown(struct platform_device *pdev)
++{
++      ath79_spi_remove(pdev);
++}
++
+ static struct platform_driver ath79_spi_driver = {
+       .probe          = ath79_spi_probe,
+       .remove         = ath79_spi_remove,
++      .shutdown       = ath79_spi_shutdown,
+       .driver         = {
+               .name   = DRV_NAME,
+               .owner  = THIS_MODULE,
diff --git a/target/linux/ar71xx/patches-3.8/206-spi-ath79-make-chipselect-logic-more-flexible.patch b/target/linux/ar71xx/patches-3.8/206-spi-ath79-make-chipselect-logic-more-flexible.patch
new file mode 100644 (file)
index 0000000..93df466
--- /dev/null
@@ -0,0 +1,310 @@
+From 7008284716403237f6bc7d7590b3ed073555bd56 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 11 Jan 2012 22:25:11 +0100
+Subject: [PATCH 34/34] spi/ath79: make chipselect logic more flexible
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/mach-ap121.c                       |    6 ++
+ arch/mips/ath79/mach-ap136.c                       |    6 ++
+ arch/mips/ath79/mach-ap81.c                        |    6 ++
+ arch/mips/ath79/mach-db120.c                       |    6 ++
+ arch/mips/ath79/mach-pb44.c                        |    6 ++
+ arch/mips/ath79/mach-ubnt-xm.c                     |    6 ++
+ .../include/asm/mach-ath79/ath79_spi_platform.h    |    8 ++-
+ drivers/spi/spi-ath79.c                            |   67 +++++++++++++-------
+ 8 files changed, 88 insertions(+), 23 deletions(-)
+
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -58,12 +58,18 @@ static struct gpio_keys_button ap121_gpi
+       }
+ };
++static struct ath79_spi_controller_data ap121_spi0_data = {
++      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++      .cs_line = 0,
++};
++
+ static struct spi_board_info ap121_spi_info[] = {
+       {
+               .bus_num        = 0,
+               .chip_select    = 0,
+               .max_speed_hz   = 25000000,
+               .modalias       = "mx25l1606e",
++              .controller_data = &ap121_spi0_data,
+       }
+ };
+--- a/arch/mips/ath79/mach-ap136.c
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -98,12 +98,18 @@ static struct gpio_keys_button ap136_gpi
+       },
+ };
++static struct ath79_spi_controller_data ap136_spi0_data = {
++      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++      .cs_line = 0,
++};
++
+ static struct spi_board_info ap136_spi_info[] = {
+       {
+               .bus_num        = 0,
+               .chip_select    = 0,
+               .max_speed_hz   = 25000000,
+               .modalias       = "mx25l6405d",
++              .controller_data = &ap136_spi0_data,
+       }
+ };
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio
+       }
+ };
++static struct ath79_spi_controller_data ap81_spi0_data = {
++      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++      .cs_line = 0,
++};
++
+ static struct spi_board_info ap81_spi_info[] = {
+       {
+               .bus_num        = 0,
+               .chip_select    = 0,
+               .max_speed_hz   = 25000000,
+               .modalias       = "m25p64",
++              .controller_data = &ap81_spi0_data,
+       }
+ };
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -76,12 +76,18 @@ static struct gpio_keys_button db120_gpi
+       },
+ };
++static struct ath79_spi_controller_data db120_spi0_data = {
++      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++      .cs_line = 0,
++};
++
+ static struct spi_board_info db120_spi_info[] = {
+       {
+               .bus_num        = 0,
+               .chip_select    = 0,
+               .max_speed_hz   = 25000000,
+               .modalias       = "s25sl064a",
++              .controller_data = &db120_spi0_data,
+       }
+ };
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio
+       }
+ };
++static struct ath79_spi_controller_data pb44_spi0_data = {
++      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++      .cs_line = 0,
++};
++
+ static struct spi_board_info pb44_spi_info[] = {
+       {
+               .bus_num        = 0,
+               .chip_select    = 0,
+               .max_speed_hz   = 25000000,
+               .modalias       = "m25p64",
++              .controller_data = &pb44_spi0_data,
+       },
+ };
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -65,12 +65,18 @@ static struct gpio_keys_button ubnt_xm_g
+       }
+ };
++static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
++      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++      .cs_line = 0,
++};
++
+ static struct spi_board_info ubnt_xm_spi_info[] = {
+       {
+               .bus_num        = 0,
+               .chip_select    = 0,
+               .max_speed_hz   = 25000000,
+               .modalias       = "mx25l6405d",
++              .controller_data = &ubnt_xm_spi0_data,
+       }
+ };
+--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+@@ -16,8 +16,14 @@ struct ath79_spi_platform_data {
+       unsigned        num_chipselect;
+ };
++enum ath79_spi_cs_type {
++      ATH79_SPI_CS_TYPE_INTERNAL,
++      ATH79_SPI_CS_TYPE_GPIO,
++};
++
+ struct ath79_spi_controller_data {
+-      unsigned        gpio;
++      enum ath79_spi_cs_type cs_type;
++      unsigned cs_line;
+ };
+ #endif /* _ATH79_SPI_PLATFORM_H */
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -35,6 +35,8 @@
+ #define ATH79_SPI_RRW_DELAY_FACTOR    12000
+ #define MHZ                           (1000 * 1000)
++#define ATH79_SPI_CS_LINE_MAX         2
++
+ struct ath79_spi {
+       struct spi_bitbang      bitbang;
+       u32                     ioc_base;
+@@ -69,6 +71,7 @@ static void ath79_spi_chipselect(struct
+ {
+       struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+       int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
++      struct ath79_spi_controller_data *cdata = spi->controller_data;
+       if (is_active) {
+               /* set initial clock polarity */
+@@ -80,20 +83,24 @@ static void ath79_spi_chipselect(struct
+               ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+       }
+-      if (spi->chip_select) {
+-              struct ath79_spi_controller_data *cdata = spi->controller_data;
+-
+-              /* SPI is normally active-low */
+-              gpio_set_value(cdata->gpio, cs_high);
+-      } else {
++      switch (cdata->cs_type) {
++      case ATH79_SPI_CS_TYPE_INTERNAL:
+               if (cs_high)
+-                      sp->ioc_base |= AR71XX_SPI_IOC_CS0;
++                      sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line);
+               else
+-                      sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
++                      sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line);
+               ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+-      }
++              break;
++      case ATH79_SPI_CS_TYPE_GPIO:
++              /* SPI is normally active-low */
++              if (gpio_cansleep(cdata->cs_line))
++                      gpio_set_value_cansleep(cdata->cs_line, cs_high);
++              else
++                      gpio_set_value(cdata->cs_line, cs_high);
++              break;
++      }
+ }
+ static void ath79_spi_enable(struct ath79_spi *sp)
+@@ -120,24 +127,30 @@ static void ath79_spi_disable(struct ath
+ static int ath79_spi_setup_cs(struct spi_device *spi)
+ {
+       struct ath79_spi_controller_data *cdata;
++      unsigned long flags;
+       int status;
+       cdata = spi->controller_data;
+-      if (spi->chip_select && !cdata)
++      if (!cdata)
+               return -EINVAL;
+       status = 0;
+-      if (spi->chip_select) {
+-              unsigned long flags;
++      switch (cdata->cs_type) {
++      case ATH79_SPI_CS_TYPE_INTERNAL:
++              if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX)
++                      status = -EINVAL;
++              break;
++      case ATH79_SPI_CS_TYPE_GPIO:
+               flags = GPIOF_DIR_OUT;
+               if (spi->mode & SPI_CS_HIGH)
+                       flags |= GPIOF_INIT_HIGH;
+               else
+                       flags |= GPIOF_INIT_LOW;
+-              status = gpio_request_one(cdata->gpio, flags,
++              status = gpio_request_one(cdata->cs_line, flags,
+                                         dev_name(&spi->dev));
++              break;
+       }
+       return status;
+@@ -145,9 +158,19 @@ static int ath79_spi_setup_cs(struct spi
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
+ {
+-      if (spi->chip_select) {
+-              struct ath79_spi_controller_data *cdata = spi->controller_data;
+-              gpio_free(cdata->gpio);
++      struct ath79_spi_controller_data *cdata;
++
++      cdata = spi->controller_data;
++      if (!cdata)
++              return;
++
++      switch (cdata->cs_type) {
++      case ATH79_SPI_CS_TYPE_INTERNAL:
++              /* nothing to do */
++              break;
++      case ATH79_SPI_CS_TYPE_GPIO:
++              gpio_free(cdata->cs_line);
++              break;
+       }
+ }
+@@ -155,6 +178,9 @@ static int ath79_spi_setup(struct spi_de
+ {
+       int status = 0;
++      if (spi->controller_data == NULL)
++              return -EINVAL;
++
+       if (spi->bits_per_word > 32)
+               return -EINVAL;
+@@ -215,6 +241,10 @@ static int ath79_spi_probe(struct platfo
+       unsigned long rate;
+       int ret;
++      pdata = pdev->dev.platform_data;
++      if (!pdata)
++              return -EINVAL;
++
+       master = spi_alloc_master(&pdev->dev, sizeof(*sp));
+       if (master == NULL) {
+               dev_err(&pdev->dev, "failed to allocate spi master\n");
+@@ -224,14 +254,10 @@ static int ath79_spi_probe(struct platfo
+       sp = spi_master_get_devdata(master);
+       platform_set_drvdata(pdev, sp);
+-      pdata = pdev->dev.platform_data;
+-
+       master->setup = ath79_spi_setup;
+       master->cleanup = ath79_spi_cleanup;
+-      if (pdata) {
+-              master->bus_num = pdata->bus_num;
+-              master->num_chipselect = pdata->num_chipselect;
+-      }
++      master->bus_num = pdata->bus_num;
++      master->num_chipselect = pdata->num_chipselect;
+       sp->bitbang.master = spi_master_get(master);
+       sp->bitbang.chipselect = ath79_spi_chipselect;
diff --git a/target/linux/ar71xx/patches-3.8/210-MIPS-ath79-simplify-misc-irq-handling.patch b/target/linux/ar71xx/patches-3.8/210-MIPS-ath79-simplify-misc-irq-handling.patch
new file mode 100644 (file)
index 0000000..84a8ca3
--- /dev/null
@@ -0,0 +1,66 @@
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -35,44 +35,17 @@ static void ath79_misc_irq_handler(unsig
+       pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
+                 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+-      if (pending & MISC_INT_UART)
+-              generic_handle_irq(ATH79_MISC_IRQ_UART);
+-
+-      else if (pending & MISC_INT_DMA)
+-              generic_handle_irq(ATH79_MISC_IRQ_DMA);
+-
+-      else if (pending & MISC_INT_PERFC)
+-              generic_handle_irq(ATH79_MISC_IRQ_PERFC);
+-
+-      else if (pending & MISC_INT_TIMER)
+-              generic_handle_irq(ATH79_MISC_IRQ_TIMER);
+-
+-      else if (pending & MISC_INT_TIMER2)
+-              generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
+-
+-      else if (pending & MISC_INT_TIMER3)
+-              generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
+-
+-      else if (pending & MISC_INT_TIMER4)
+-              generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
+-
+-      else if (pending & MISC_INT_OHCI)
+-              generic_handle_irq(ATH79_MISC_IRQ_OHCI);
+-
+-      else if (pending & MISC_INT_ERROR)
+-              generic_handle_irq(ATH79_MISC_IRQ_ERROR);
+-
+-      else if (pending & MISC_INT_GPIO)
+-              generic_handle_irq(ATH79_MISC_IRQ_GPIO);
+-
+-      else if (pending & MISC_INT_WDOG)
+-              generic_handle_irq(ATH79_MISC_IRQ_WDOG);
++      if (!pending) {
++              spurious_interrupt();
++              return;
++      }
+-      else if (pending & MISC_INT_ETHSW)
+-              generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
++      while (pending) {
++              int bit = __ffs(pending);
+-      else
+-              spurious_interrupt();
++              generic_handle_irq(ATH79_MISC_IRQ(bit));
++              pending &= ~BIT(bit);
++      }
+ }
+ static void ar71xx_misc_irq_unmask(struct irq_data *d)
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -14,6 +14,7 @@
+ #define ATH79_MISC_IRQ_BASE   8
+ #define ATH79_MISC_IRQ_COUNT  32
++#define ATH79_MISC_IRQ(_x)    (ATH79_MISC_IRQ_BASE + (_x))
+ #define ATH79_PCI_IRQ_BASE    (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
+ #define ATH79_PCI_IRQ_COUNT   6
diff --git a/target/linux/ar71xx/patches-3.8/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch b/target/linux/ar71xx/patches-3.8/212-MIPS-ath79-fix-GPIO-function-selection-for-AR934x-So.patch
new file mode 100644 (file)
index 0000000..5df56e4
--- /dev/null
@@ -0,0 +1,106 @@
+From 177dc53a07e2c660d1c1a6cec4576c802325e330 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 14 Nov 2012 09:02:01 +0100
+Subject: [PATCH] MIPS: ath79: fix GPIO function selection for AR934x SoCs
+
+GPIO function selection is not working on the AR934x
+SoCs because the offset of the  function selection
+register is different on those.
+
+Add a helper routine which returns the correct
+register address based on the SoC type, and use
+that in the 'ath79_gpio_function_*' routines.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/gpio.c                         |   38 ++++++++++++++++--------
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ 2 files changed, 28 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -137,47 +137,61 @@ static struct gpio_chip ath79_gpio_chip
+       .base                   = 0,
+ };
++static void __iomem *ath79_gpio_get_function_reg(void)
++{
++      u32 reg = 0;
++
++      if (soc_is_ar71xx() ||
++          soc_is_ar724x() ||
++          soc_is_ar913x() ||
++          soc_is_ar933x())
++              reg = AR71XX_GPIO_REG_FUNC;
++      else if (soc_is_ar934x())
++              reg = AR934X_GPIO_REG_FUNC;
++      else
++              BUG();
++
++      return ath79_gpio_base + reg;
++}
++
+ void ath79_gpio_function_enable(u32 mask)
+ {
+-      void __iomem *base = ath79_gpio_base;
++      void __iomem *reg = ath79_gpio_get_function_reg();
+       unsigned long flags;
+       spin_lock_irqsave(&ath79_gpio_lock, flags);
+-      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,
+-                   base + AR71XX_GPIO_REG_FUNC);
++      __raw_writel(__raw_readl(reg) | mask, reg);
+       /* flush write */
+-      __raw_readl(base + AR71XX_GPIO_REG_FUNC);
++      __raw_readl(reg);
+       spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+ void ath79_gpio_function_disable(u32 mask)
+ {
+-      void __iomem *base = ath79_gpio_base;
++      void __iomem *reg = ath79_gpio_get_function_reg();
+       unsigned long flags;
+       spin_lock_irqsave(&ath79_gpio_lock, flags);
+-      __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,
+-                   base + AR71XX_GPIO_REG_FUNC);
++      __raw_writel(__raw_readl(reg) & ~mask, reg);
+       /* flush write */
+-      __raw_readl(base + AR71XX_GPIO_REG_FUNC);
++      __raw_readl(reg);
+       spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+ void ath79_gpio_function_setup(u32 set, u32 clear)
+ {
+-      void __iomem *base = ath79_gpio_base;
++      void __iomem *reg = ath79_gpio_get_function_reg();
+       unsigned long flags;
+       spin_lock_irqsave(&ath79_gpio_lock, flags);
+-      __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
+-                   base + AR71XX_GPIO_REG_FUNC);
++      __raw_writel((__raw_readl(reg) & ~clear) | set, reg);
+       /* flush write */
+-      __raw_readl(base + AR71XX_GPIO_REG_FUNC);
++      __raw_readl(reg);
+       spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -521,6 +521,8 @@
+ #define AR71XX_GPIO_REG_INT_ENABLE    0x24
+ #define AR71XX_GPIO_REG_FUNC          0x28
++#define AR934X_GPIO_REG_FUNC          0x6c
++
+ #define AR71XX_GPIO_COUNT             16
+ #define AR7240_GPIO_COUNT             18
+ #define AR7241_GPIO_COUNT             20
diff --git a/target/linux/ar71xx/patches-3.8/213-MIPS-ath79-fix-ar933x-wmac-reset.patch b/target/linux/ar71xx/patches-3.8/213-MIPS-ath79-fix-ar933x-wmac-reset.patch
new file mode 100644 (file)
index 0000000..e0821a7
--- /dev/null
@@ -0,0 +1,31 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -62,10 +62,27 @@ static void __init ar913x_wmac_setup(voi
+ static int ar933x_wmac_reset(void)
+ {
++      int retries = 20;
++
+       ath79_device_reset_set(AR933X_RESET_WMAC);
+       ath79_device_reset_clear(AR933X_RESET_WMAC);
+-      return 0;
++      while (1) {
++              u32 bootstrap;
++
++              bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
++              if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
++                      return 0;
++
++              if (retries-- == 0)
++                      break;
++
++              udelay(10000);
++              retries++;
++      }
++
++      pr_err("ar933x: WMAC reset timed out");
++      return -ETIMEDOUT;
+ }
+ static int ar933x_r1_get_wmac_revision(void)
diff --git a/target/linux/ar71xx/patches-3.8/220-add_cpu_feature_overrides.patch b/target/linux/ar71xx/patches-3.8/220-add_cpu_feature_overrides.patch
new file mode 100644 (file)
index 0000000..05406f2
--- /dev/null
@@ -0,0 +1,28 @@
+--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
++++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+@@ -36,6 +36,7 @@
+ #define cpu_has_mdmx          0
+ #define cpu_has_mips3d                0
+ #define cpu_has_smartmips     0
++#define cpu_has_rixi          0
+ #define cpu_has_mips32r1      1
+ #define cpu_has_mips32r2      1
+@@ -45,6 +46,7 @@
+ #define cpu_has_dsp           0
+ #define cpu_has_dsp2          0
+ #define cpu_has_mipsmt                0
++#define cpu_has_userlocal     0
+ #define cpu_has_64bits                0
+ #define cpu_has_64bit_zero_reg        0
+@@ -53,5 +55,9 @@
+ #define cpu_dcache_line_size()        32
+ #define cpu_icache_line_size()        32
++#define cpu_has_vtag_icache   0
++#define cpu_has_dc_aliases    1
++#define cpu_has_ic_fills_f_dc 0
++#define cpu_has_pindexed_dcache       0
+ #endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */
diff --git a/target/linux/ar71xx/patches-3.8/310-lib-add-rle-decompression.patch b/target/linux/ar71xx/patches-3.8/310-lib-add-rle-decompression.patch
new file mode 100644 (file)
index 0000000..d81fdd8
--- /dev/null
@@ -0,0 +1,114 @@
+--- a/lib/Kconfig
++++ b/lib/Kconfig
+@@ -197,6 +197,9 @@ config LZMA_COMPRESS
+ config LZMA_DECOMPRESS
+     tristate
++config RLE_DECOMPRESS
++      tristate
++
+ #
+ # These all provide a common interface (hence the apparent duplication with
+ # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.)
+--- a/lib/Makefile
++++ b/lib/Makefile
+@@ -86,6 +86,7 @@ obj-$(CONFIG_XZ_DEC) += xz/
+ obj-$(CONFIG_RAID6_PQ) += raid6/
+ obj-$(CONFIG_LZMA_COMPRESS) += lzma/
+ obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/
++obj-$(CONFIG_RLE_DECOMPRESS) += rle.o
+ lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o
+ lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o
+--- /dev/null
++++ b/include/linux/rle.h
+@@ -0,0 +1,8 @@
++#ifndef _RLE_H_
++#define _RLE_H_
++
++int rle_decode(const unsigned char *src, size_t srclen,
++             unsigned char *dst, size_t dstlen,
++             size_t *src_done, size_t *dst_done);
++
++#endif /* _RLE_H_ */
+--- /dev/null
++++ b/lib/rle.c
+@@ -0,0 +1,78 @@
++/*
++ *  RLE decoding routine
++ *
++ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/rle.h>
++
++int rle_decode(const unsigned char *src, size_t srclen,
++             unsigned char *dst, size_t dstlen,
++             size_t *src_done, size_t *dst_done)
++{
++      size_t srcpos, dstpos;
++      int ret;
++
++      srcpos = 0;
++      dstpos = 0;
++      ret = -EINVAL;
++
++      /* sanity checks */
++      if (!src || !srclen || !dst || !dstlen)
++              goto out;
++
++      while (1) {
++              char count;
++
++              if (srcpos >= srclen)
++                      break;
++
++              count = (char) src[srcpos++];
++              if (count == 0) {
++                      ret = 0;
++                      break;
++              }
++
++              if (count > 0) {
++                      unsigned char c;
++
++                      if (srcpos >= srclen)
++                              break;
++
++                      c = src[srcpos++];
++
++                      while (count--) {
++                              if (dstpos >= dstlen)
++                                      break;
++
++                              dst[dstpos++] = c;
++                      }
++              } else {
++                      count *= -1;
++
++                      while (count--) {
++                              if (srcpos >= srclen)
++                                      break;
++                              if (dstpos >= dstlen)
++                                      break;
++                              dst[dstpos++] = src[srcpos++];
++                      }
++              }
++      }
++
++out:
++      if (src_done)
++              *src_done = srcpos;
++      if (dst_done)
++              *dst_done = dstpos;
++
++      return ret;
++}
++
++EXPORT_SYMBOL_GPL(rle_decode);
diff --git a/target/linux/ar71xx/patches-3.8/401-mtd-physmap-add-lock-unlock.patch b/target/linux/ar71xx/patches-3.8/401-mtd-physmap-add-lock-unlock.patch
new file mode 100644 (file)
index 0000000..ead7685
--- /dev/null
@@ -0,0 +1,94 @@
+--- a/drivers/mtd/maps/physmap.c
++++ b/drivers/mtd/maps/physmap.c
+@@ -31,6 +31,66 @@ struct physmap_flash_info {
+       int                     vpp_refcnt;
+ };
++static struct platform_device *physmap_map2pdev(struct map_info *map)
++{
++      return (struct platform_device *) map->map_priv_1;
++}
++
++static void physmap_lock(struct map_info *map)
++{
++      struct platform_device *pdev;
++      struct physmap_flash_data *physmap_data;
++
++      pdev = physmap_map2pdev(map);
++      physmap_data = pdev->dev.platform_data;
++      physmap_data->lock(pdev);
++}
++
++static void physmap_unlock(struct map_info *map)
++{
++      struct platform_device *pdev;
++      struct physmap_flash_data *physmap_data;
++
++      pdev = physmap_map2pdev(map);
++      physmap_data = pdev->dev.platform_data;
++      physmap_data->unlock(pdev);
++}
++
++static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs)
++{
++      map_word ret;
++
++      physmap_lock(map);
++      ret = inline_map_read(map, ofs);
++      physmap_unlock(map);
++
++      return ret;
++}
++
++static void physmap_flash_write_lock(struct map_info *map, map_word d,
++                                   unsigned long ofs)
++{
++      physmap_lock(map);
++      inline_map_write(map, d, ofs);
++      physmap_unlock(map);
++}
++
++static void physmap_flash_copy_from_lock(struct map_info *map, void *to,
++                                       unsigned long from, ssize_t len)
++{
++      physmap_lock(map);
++      inline_map_copy_from(map, to, from, len);
++      physmap_unlock(map);
++}
++
++static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to,
++                                     const void *from, ssize_t len)
++{
++      physmap_lock(map);
++      inline_map_copy_to(map, to, from, len);
++      physmap_unlock(map);
++}
++
+ static int physmap_flash_remove(struct platform_device *dev)
+ {
+       struct physmap_flash_info *info;
+@@ -157,6 +217,13 @@ static int physmap_flash_probe(struct pl
+               simple_map_init(&info->map[i]);
++              if (physmap_data->lock && physmap_data->unlock) {
++                      info->map[i].read = physmap_flash_read_lock;
++                      info->map[i].write = physmap_flash_write_lock;
++                      info->map[i].copy_from = physmap_flash_copy_from_lock;
++                      info->map[i].copy_to = physmap_flash_copy_to_lock;
++              }
++
+               probe_type = rom_probe_types;
+               if (physmap_data->probe_type == NULL) {
+                       for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++)
+--- a/include/linux/mtd/physmap.h
++++ b/include/linux/mtd/physmap.h
+@@ -26,6 +26,8 @@ struct physmap_flash_data {
+       unsigned int            width;
+       int                     (*init)(struct platform_device *);
+       void                    (*exit)(struct platform_device *);
++      void                    (*lock)(struct platform_device *);
++      void                    (*unlock)(struct platform_device *);
+       void                    (*set_vpp)(struct platform_device *, int);
+       unsigned int            nr_parts;
+       unsigned int            pfow_base;
diff --git a/target/linux/ar71xx/patches-3.8/402-mtd-SST39VF6401B-support.patch b/target/linux/ar71xx/patches-3.8/402-mtd-SST39VF6401B-support.patch
new file mode 100644 (file)
index 0000000..246abd5
--- /dev/null
@@ -0,0 +1,29 @@
+--- a/drivers/mtd/chips/jedec_probe.c
++++ b/drivers/mtd/chips/jedec_probe.c
+@@ -148,6 +148,7 @@
+ #define SST39LF160    0x2782
+ #define SST39VF1601   0x234b
+ #define SST39VF3201   0x235b
++#define SST39VF6401B  0x236d
+ #define SST39WF1601   0x274b
+ #define SST39WF1602   0x274a
+ #define SST39LF512    0x00D4
+@@ -1568,6 +1569,18 @@ static const struct amd_flash_info jedec
+                       ERASEINFO(0x10000,64),
+               }
+       }, {
++              .mfr_id         = CFI_MFR_SST,
++              .dev_id         = SST39VF6401B,
++              .name           = "SST 39VF6401B",
++              .devtypes       = CFI_DEVICETYPE_X16,
++              .uaddr          = MTD_UADDR_0xAAAA_0x5555,
++              .dev_size       = SIZE_8MiB,
++              .cmd_set        = P_ID_AMD_STD,
++              .nr_regions     = 1,
++              .regions        = {
++                      ERASEINFO(0x10000,128)
++              }
++      }, {
+               .mfr_id         = CFI_MFR_ST,
+               .dev_id         = M29F800AB,
+               .name           = "ST M29F800AB",
diff --git a/target/linux/ar71xx/patches-3.8/403-mtd_fix_cfi_cmdset_0002_status_check.patch b/target/linux/ar71xx/patches-3.8/403-mtd_fix_cfi_cmdset_0002_status_check.patch
new file mode 100644 (file)
index 0000000..e569fe1
--- /dev/null
@@ -0,0 +1,69 @@
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -1288,8 +1288,8 @@ static int __xipram do_write_oneword(str
+                       break;
+               }
+-              if (chip_ready(map, adr))
+-                      break;
++              if (chip_good(map, adr, datum))
++                      goto enable_xip;
+               /* Latency issues. Drop the lock, wait a while and retry */
+               UDELAY(map, chip, adr, 1);
+@@ -1305,6 +1305,8 @@ static int __xipram do_write_oneword(str
+               ret = -EIO;
+       }
++
++ enable_xip:
+       xip_enable(map, chip, adr);
+  op_done:
+       chip->state = FL_READY;
+@@ -1875,7 +1877,6 @@ static int cfi_amdstd_panic_write(struct
+       return 0;
+ }
+-
+ /*
+  * Handle devices with one erase region, that only implement
+  * the chip erase command.
+@@ -1939,8 +1940,8 @@ static int __xipram do_erase_chip(struct
+                       chip->erase_suspended = 0;
+               }
+-              if (chip_ready(map, adr))
+-                      break;
++              if (chip_good(map, adr, map_word_ff(map)))
++                      goto op_done;
+               if (time_after(jiffies, timeo)) {
+                       printk(KERN_WARNING "MTD %s(): software timeout\n",
+@@ -1960,6 +1961,7 @@ static int __xipram do_erase_chip(struct
+               ret = -EIO;
+       }
++ op_done:
+       chip->state = FL_READY;
+       xip_enable(map, chip, adr);
+       DISABLE_VPP(map);
+@@ -2028,9 +2030,9 @@ static int __xipram do_erase_oneblock(st
+                       chip->erase_suspended = 0;
+               }
+-              if (chip_ready(map, adr)) {
++              if (chip_good(map, adr, map_word_ff(map))) {
+                       xip_enable(map, chip, adr);
+-                      break;
++                      goto op_done;
+               }
+               if (time_after(jiffies, timeo)) {
+@@ -2052,6 +2054,7 @@ static int __xipram do_erase_oneblock(st
+               ret = -EIO;
+       }
++ op_done:
+       chip->state = FL_READY;
+       DISABLE_VPP(map);
+       put_chip(map, chip, adr);
diff --git a/target/linux/ar71xx/patches-3.8/404-mtd-wrt160nl-trx-parser.patch b/target/linux/ar71xx/patches-3.8/404-mtd-wrt160nl-trx-parser.patch
new file mode 100644 (file)
index 0000000..71798c4
--- /dev/null
@@ -0,0 +1,25 @@
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -163,6 +163,12 @@ config MTD_BCM47XX_PARTS
+         This provides partitions parser for devices based on BCM47xx
+         boards.
++config MTD_WRT160NL_PARTS
++      tristate "Linksys WRT160NL partitioning support"
++      depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
++      ---help---
++         Linksys WRT160NL partitioning support
++
+ config MTD_MYLOADER_PARTS
+       tristate "MyLoader partition parsing"
+       depends on ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX || ATH79
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_AR7_PARTS)  += ar7part.o
+ obj-$(CONFIG_MTD_BCM63XX_PARTS)       += bcm63xxpart.o
+ obj-$(CONFIG_MTD_BCM47XX_PARTS)       += bcm47xxpart.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
++obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
+ # 'Users' - code which presents functionality to userspace.
+ obj-$(CONFIG_MTD_CHAR)                += mtdchar.o
diff --git a/target/linux/ar71xx/patches-3.8/405-mtd-tp-link-partition-parser.patch b/target/linux/ar71xx/patches-3.8/405-mtd-tp-link-partition-parser.patch
new file mode 100644 (file)
index 0000000..45676ec
--- /dev/null
@@ -0,0 +1,34 @@
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -165,7 +165,7 @@ config MTD_BCM47XX_PARTS
+ config MTD_WRT160NL_PARTS
+       tristate "Linksys WRT160NL partitioning support"
+-      depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
++      depends on ATH79_MACH_WRT160NL
+       ---help---
+          Linksys WRT160NL partitioning support
+@@ -185,6 +185,12 @@ config MTD_MYLOADER_PARTS
+         You will still need the parsing functions to be called by the driver
+         for your particular device. It won't happen automatically.
++config MTD_TPLINK_PARTS
++      tristate "TP-Link AR7XXX/AR9XXX partitioning support"
++      depends on ATH79
++      ---help---
++        TBD.
++
+ comment "User Modules And Translation Layers"
+ config MTD_CHAR
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_AR7_PARTS)  += ar7part.o
+ obj-$(CONFIG_MTD_BCM63XX_PARTS)       += bcm63xxpart.o
+ obj-$(CONFIG_MTD_BCM47XX_PARTS)       += bcm47xxpart.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
++obj-$(CONFIG_MTD_TPLINK_PARTS)        += tplinkpart.o
+ obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
+ # 'Users' - code which presents functionality to userspace.
diff --git a/target/linux/ar71xx/patches-3.8/406-mtd-m25p80-allow-to-specify-max-read-size.patch b/target/linux/ar71xx/patches-3.8/406-mtd-m25p80-allow-to-specify-max-read-size.patch
new file mode 100644 (file)
index 0000000..be308c6
--- /dev/null
@@ -0,0 +1,109 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -93,6 +93,7 @@ struct m25p {
+       u8                      erase_opcode;
+       u8                      *command;
+       bool                    fast_read;
++      size_t                  max_read_len;
+ };
+ static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
+@@ -344,6 +345,7 @@ static int m25p80_read(struct mtd_info *
+       struct spi_transfer t[2];
+       struct spi_message m;
+       uint8_t opcode;
++      loff_t ofs;
+       pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
+                       __func__, (u32)from, len);
+@@ -359,19 +361,10 @@ static int m25p80_read(struct mtd_info *
+       t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
+       spi_message_add_tail(&t[0], &m);
+-      t[1].rx_buf = buf;
+-      t[1].len = len;
+       spi_message_add_tail(&t[1], &m);
+       mutex_lock(&flash->lock);
+-      /* Wait till previous write/erase is done. */
+-      if (wait_till_ready(flash)) {
+-              /* REVISIT status return?? */
+-              mutex_unlock(&flash->lock);
+-              return 1;
+-      }
+-
+       /* FIXME switch to OPCODE_FAST_READ.  It's required for higher
+        * clocks; and at this writing, every chip this driver handles
+        * supports that opcode.
+@@ -380,13 +373,43 @@ static int m25p80_read(struct mtd_info *
+       /* Set up the write data buffer. */
+       opcode = flash->fast_read ? OPCODE_FAST_READ : OPCODE_NORM_READ;
+       flash->command[0] = opcode;
+-      m25p_addr2cmd(flash, from, flash->command);
++      ofs = 0;
++      while (len) {
++              size_t readlen;
++              size_t done;
++              int ret;
++
++              ret = wait_till_ready(flash);
++              if (ret) {
++                      mutex_unlock(&flash->lock);
++                      return 1;
++              }
++
++              if (flash->max_read_len > 0 &&
++                  flash->max_read_len < len)
++                      readlen = flash->max_read_len;
++              else
++                      readlen = len;
++
++              t[1].rx_buf = buf + ofs;
++              t[1].len = readlen;
++
++              m25p_addr2cmd(flash, from + ofs, flash->command);
++
++              spi_sync(flash->spi, &m);
+-      spi_sync(flash->spi, &m);
++              done = m.actual_length - m25p_cmdsz(flash) -
++                     (flash->fast_read ? 1 : 0);
++              if (done != readlen) {
++                      mutex_unlock(&flash->lock);
++                      return 1;
++              }
+-      *retlen = m.actual_length - m25p_cmdsz(flash) -
+-                      (flash->fast_read ? 1 : 0);
++              ofs += done;
++              len -= done;
++      }
++      *retlen = ofs;
+       mutex_unlock(&flash->lock);
+       return 0;
+@@ -916,6 +939,12 @@ static int m25p_probe(struct spi_device
+       flash->mtd._erase = m25p80_erase;
+       flash->mtd._read = m25p80_read;
++      if (data && data->max_read_len) {
++              flash->max_read_len = data->max_read_len;
++              dev_warn(&spi->dev, "max_read_len set to %d bytes\n",
++                      flash->max_read_len);
++      }
++
+       /* sst flash chips use AAI word program */
+       if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
+               flash->mtd._write = sst_write;
+--- a/include/linux/spi/flash.h
++++ b/include/linux/spi/flash.h
+@@ -25,6 +25,7 @@ struct flash_platform_data {
+       char            *type;
++      size_t          max_read_len;
+       /* we'll likely add more ... use JEDEC IDs, etc */
+ };
diff --git a/target/linux/ar71xx/patches-3.8/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch b/target/linux/ar71xx/patches-3.8/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
new file mode 100644 (file)
index 0000000..db0a542
--- /dev/null
@@ -0,0 +1,23 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -1016,7 +1016,9 @@ static int m25p_probe(struct spi_device
+       /* partitions should match sector boundaries; and it may be good to
+        * use readonly partitions for writeprotected sectors (BP2..BP0).
+        */
+-      return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
++      return mtd_device_parse_register(&flash->mtd,
++                      data ? data->part_probes : NULL,
++                      &ppdata,
+                       data ? data->parts : NULL,
+                       data ? data->nr_parts : 0);
+ }
+--- a/include/linux/spi/flash.h
++++ b/include/linux/spi/flash.h
+@@ -24,6 +24,7 @@ struct flash_platform_data {
+       unsigned int    nr_parts;
+       char            *type;
++      const char      **part_probes;
+       size_t          max_read_len;
+       /* we'll likely add more ... use JEDEC IDs, etc */
diff --git a/target/linux/ar71xx/patches-3.8/408-mtd-redboot_partition_scan.patch b/target/linux/ar71xx/patches-3.8/408-mtd-redboot_partition_scan.patch
new file mode 100644 (file)
index 0000000..cd41e7c
--- /dev/null
@@ -0,0 +1,44 @@
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -76,12 +76,18 @@ static int parse_redboot_partitions(stru
+       static char nullstring[] = "unallocated";
+ #endif
++      buf = vmalloc(master->erasesize);
++      if (!buf)
++              return -ENOMEM;
++
++ restart:
+       if ( directory < 0 ) {
+               offset = master->size + directory * master->erasesize;
+               while (mtd_block_isbad(master, offset)) {
+                       if (!offset) {
+                       nogood:
+                               printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
++                              vfree(buf);
+                               return -EIO;
+                       }
+                       offset -= master->erasesize;
+@@ -94,10 +100,6 @@ static int parse_redboot_partitions(stru
+                               goto nogood;
+               }
+       }
+-      buf = vmalloc(master->erasesize);
+-
+-      if (!buf)
+-              return -ENOMEM;
+       printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
+              master->name, offset);
+@@ -170,6 +172,11 @@ static int parse_redboot_partitions(stru
+       }
+       if (i == numslots) {
+               /* Didn't find it */
++              if (offset + master->erasesize < master->size) {
++                      /* not at the end of the flash yet, maybe next block :) */
++                      directory++;
++                      goto restart;
++              }
+               printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
+                      master->name);
+               ret = 0;
diff --git a/target/linux/ar71xx/patches-3.8/409-mtd-rb4xx_nand_driver.patch b/target/linux/ar71xx/patches-3.8/409-mtd-rb4xx_nand_driver.patch
new file mode 100644 (file)
index 0000000..082df87
--- /dev/null
@@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -575,4 +575,8 @@ config MTD_NAND_XWAY
+         Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
+         to the External Bus Unit (EBU).
++config MTD_NAND_RB4XX
++      tristate "NAND flash driver for RouterBoard 4xx series"
++      depends on MTD_NAND && ATH79_MACH_RB4XX
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270)               += cmx27
+ obj-$(CONFIG_MTD_NAND_PXA3xx)         += pxa3xx_nand.o
+ obj-$(CONFIG_MTD_NAND_TMIO)           += tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM)               += plat_nand.o
++obj-$(CONFIG_MTD_NAND_RB4XX)          += rb4xx_nand.o
+ obj-$(CONFIG_MTD_ALAUDA)              += alauda.o
+ obj-$(CONFIG_MTD_NAND_PASEMI)         += pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION)          += orion_nand.o
diff --git a/target/linux/ar71xx/patches-3.8/410-mtd-rb750-nand-driver.patch b/target/linux/ar71xx/patches-3.8/410-mtd-rb750-nand-driver.patch
new file mode 100644 (file)
index 0000000..1247866
--- /dev/null
@@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -579,4 +579,8 @@ config MTD_NAND_RB4XX
+       tristate "NAND flash driver for RouterBoard 4xx series"
+       depends on MTD_NAND && ATH79_MACH_RB4XX
++config MTD_NAND_RB750
++      tristate "NAND flash driver for the RouterBoard 750"
++      depends on MTD_NAND && ATH79_MACH_RB750
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx)                += pxa3xx
+ obj-$(CONFIG_MTD_NAND_TMIO)           += tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM)               += plat_nand.o
+ obj-$(CONFIG_MTD_NAND_RB4XX)          += rb4xx_nand.o
++obj-$(CONFIG_MTD_NAND_RB750)          += rb750_nand.o
+ obj-$(CONFIG_MTD_ALAUDA)              += alauda.o
+ obj-$(CONFIG_MTD_NAND_PASEMI)         += pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION)          += orion_nand.o
diff --git a/target/linux/ar71xx/patches-3.8/411-mtd-cfi_cmdset_0002-force-word-write.patch b/target/linux/ar71xx/patches-3.8/411-mtd-cfi_cmdset_0002-force-word-write.patch
new file mode 100644 (file)
index 0000000..2d8e6e6
--- /dev/null
@@ -0,0 +1,61 @@
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -39,7 +39,7 @@
+ #include <linux/mtd/xip.h>
+ #define AMD_BOOTLOC_BUG
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+ #define MAX_WORD_RETRIES 3
+@@ -50,7 +50,9 @@
+ static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#if !FORCE_WORD_WRITE
+ static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#endif
+ static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
+ static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_amdstd_sync (struct mtd_info *);
+@@ -186,6 +188,7 @@ static void fixup_amd_bootblock(struct m
+ }
+ #endif
++#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+       struct map_info *map = mtd->priv;
+@@ -195,6 +198,7 @@ static void fixup_use_write_buffers(stru
+               mtd->_write = cfi_amdstd_write_buffers;
+       }
+ }
++#endif /* !FORCE_WORD_WRITE */
+ /* Atmel chips don't use the same PRI format as AMD chips */
+ static void fixup_convert_atmel_pri(struct mtd_info *mtd)
+@@ -1445,6 +1449,7 @@ static int cfi_amdstd_write_words(struct
+ /*
+  * FIXME: interleaved mode not tested, and probably not supported!
+  */
++#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+                                   unsigned long adr, const u_char *buf,
+                                   int len)
+@@ -1569,7 +1574,6 @@ static int __xipram do_write_buffer(stru
+       return ret;
+ }
+-
+ static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
+                                   size_t *retlen, const u_char *buf)
+ {
+@@ -1644,6 +1648,7 @@ static int cfi_amdstd_write_buffers(stru
+       return 0;
+ }
++#endif /* !FORCE_WORD_WRITE */
+ /*
+  * Wait for the flash chip to become ready to write data
diff --git a/target/linux/ar71xx/patches-3.8/412-mtd-m25p80-zero-partition-parser-data.patch b/target/linux/ar71xx/patches-3.8/412-mtd-m25p80-zero-partition-parser-data.patch
new file mode 100644 (file)
index 0000000..e9beb6b
--- /dev/null
@@ -0,0 +1,10 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -966,6 +966,7 @@ static int m25p_probe(struct spi_device
+       if (info->flags & M25P_NO_ERASE)
+               flash->mtd.flags |= MTD_NO_ERASE;
++      memset(&ppdata, '\0', sizeof(ppdata));
+       ppdata.of_node = spi->dev.of_node;
+       flash->mtd.dev.parent = &spi->dev;
+       flash->page_size = info->page_size;
diff --git a/target/linux/ar71xx/patches-3.8/413-mtd-ar934x-nand-driver.patch b/target/linux/ar71xx/patches-3.8/413-mtd-ar934x-nand-driver.patch
new file mode 100644 (file)
index 0000000..f8362cb
--- /dev/null
@@ -0,0 +1,21 @@
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -583,4 +583,8 @@ config MTD_NAND_RB750
+       tristate "NAND flash driver for the RouterBoard 750"
+       depends on MTD_NAND && ATH79_MACH_RB750
++config MTD_NAND_AR934X
++      tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs"
++      depends on (SOC_AR934X || SOC_QCA955X)
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_AMS_DELTA)     += ams-
+ obj-$(CONFIG_MTD_NAND_DENALI)         += denali.o
+ obj-$(CONFIG_MTD_NAND_DENALI_PCI)     += denali_pci.o
+ obj-$(CONFIG_MTD_NAND_DENALI_DT)      += denali_dt.o
++obj-$(CONFIG_MTD_NAND_AR934X)         += ar934x_nfc.o
+ obj-$(CONFIG_MTD_NAND_AU1550)         += au1550nd.o
+ obj-$(CONFIG_MTD_NAND_BF5XX)          += bf5xx_nand.o
+ obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o
diff --git a/target/linux/ar71xx/patches-3.8/420-net-ar71xx_mac_driver.patch b/target/linux/ar71xx/patches-3.8/420-net-ar71xx_mac_driver.patch
new file mode 100644 (file)
index 0000000..f117133
--- /dev/null
@@ -0,0 +1,28 @@
+--- a/drivers/net/ethernet/atheros/Kconfig
++++ b/drivers/net/ethernet/atheros/Kconfig
+@@ -5,7 +5,7 @@
+ config NET_VENDOR_ATHEROS
+       bool "Atheros devices"
+       default y
+-      depends on PCI
++      depends on (PCI || ATH79)
+       ---help---
+         If you have a network (Ethernet) card belonging to this class, say Y
+         and read the Ethernet-HOWTO, available from
+@@ -67,4 +67,6 @@ config ATL1C
+         To compile this driver as a module, choose M here.  The module
+         will be called atl1c.
++source drivers/net/ethernet/atheros/ag71xx/Kconfig
++
+ endif # NET_VENDOR_ATHEROS
+--- a/drivers/net/ethernet/atheros/Makefile
++++ b/drivers/net/ethernet/atheros/Makefile
+@@ -2,6 +2,7 @@
+ # Makefile for the Atheros network device drivers.
+ #
++obj-$(CONFIG_AG71XX) += ag71xx/
+ obj-$(CONFIG_ATL1) += atlx/
+ obj-$(CONFIG_ATL2) += atlx/
+ obj-$(CONFIG_ATL1E) += atl1e/
diff --git a/target/linux/ar71xx/patches-3.8/422-dsa-trailer-tag-validation-fix.patch b/target/linux/ar71xx/patches-3.8/422-dsa-trailer-tag-validation-fix.patch
new file mode 100644 (file)
index 0000000..3e3902b
--- /dev/null
@@ -0,0 +1,11 @@
+--- a/net/dsa/tag_trailer.c
++++ b/net/dsa/tag_trailer.c
+@@ -87,7 +87,7 @@ static int trailer_rcv(struct sk_buff *s
+       trailer = skb_tail_pointer(skb) - 4;
+       if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||
+-          (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00)
++          (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00)
+               goto out_drop;
+       source_port = trailer[1] & 7;
diff --git a/target/linux/ar71xx/patches-3.8/423-dsa-add-88e6063-driver.patch b/target/linux/ar71xx/patches-3.8/423-dsa-add-88e6063-driver.patch
new file mode 100644 (file)
index 0000000..1348cd9
--- /dev/null
@@ -0,0 +1,24 @@
+--- a/drivers/net/dsa/Kconfig
++++ b/drivers/net/dsa/Kconfig
+@@ -13,6 +13,13 @@ config NET_DSA_MV88E6060
+         This enables support for the Marvell 88E6060 ethernet switch
+         chip.
++config NET_DSA_MV88E6063
++      bool "Marvell 88E6063 ethernet switch chip support"
++      select NET_DSA_TAG_TRAILER
++      ---help---
++        This enables support for the Marvell 88E6063 ethernet switch
++        chip
++
+ config NET_DSA_MV88E6XXX_NEED_PPU
+       bool
+       default n
+--- a/drivers/net/dsa/Makefile
++++ b/drivers/net/dsa/Makefile
+@@ -1,4 +1,5 @@
+ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
++obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
+ obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx_drv.o
+ mv88e6xxx_drv-y += mv88e6xxx.o
+ ifdef CONFIG_NET_DSA_MV88E6123_61_65
diff --git a/target/linux/ar71xx/patches-3.8/430-drivers-link-spi-before-mtd.patch b/target/linux/ar71xx/patches-3.8/430-drivers-link-spi-before-mtd.patch
new file mode 100644 (file)
index 0000000..88d1457
--- /dev/null
@@ -0,0 +1,12 @@
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -60,8 +60,8 @@ obj-$(CONFIG_IDE)            += ide/
+ obj-$(CONFIG_SCSI)            += scsi/
+ obj-$(CONFIG_ATA)             += ata/
+ obj-$(CONFIG_TARGET_CORE)     += target/
+-obj-$(CONFIG_MTD)             += mtd/
+ obj-$(CONFIG_SPI)             += spi/
++obj-$(CONFIG_MTD)             += mtd/
+ obj-y                         += hsi/
+ obj-y                         += net/
+ obj-$(CONFIG_ATM)             += atm/
diff --git a/target/linux/ar71xx/patches-3.8/431-spi-add-various-flags.patch b/target/linux/ar71xx/patches-3.8/431-spi-add-various-flags.patch
new file mode 100644 (file)
index 0000000..9f13db2
--- /dev/null
@@ -0,0 +1,19 @@
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -506,6 +506,8 @@ struct spi_transfer {
+       dma_addr_t      rx_dma;
+       unsigned        cs_change:1;
++      unsigned        verify:1;
++      unsigned        fast_write:1;
+       u8              bits_per_word;
+       u16             delay_usecs;
+       u32             speed_hz;
+@@ -547,6 +549,7 @@ struct spi_message {
+       struct spi_device       *spi;
+       unsigned                is_dma_mapped:1;
++      unsigned                fast_read:1;
+       /* REVISIT:  we might want a flag affecting the behavior of the
+        * last transfer ... allowing things like "read 16 bit length L"
diff --git a/target/linux/ar71xx/patches-3.8/432-spi-rb4xx-spi-driver.patch b/target/linux/ar71xx/patches-3.8/432-spi-rb4xx-spi-driver.patch
new file mode 100644 (file)
index 0000000..1ff133c
--- /dev/null
@@ -0,0 +1,25 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -324,6 +324,12 @@ config SPI_RSPI
+       help
+         SPI driver for Renesas RSPI blocks.
++config SPI_RB4XX
++      tristate "Mikrotik RB4XX SPI master"
++      depends on SPI_MASTER && ATH79_MACH_RB4XX
++      help
++        SPI controller driver for the Mikrotik RB4xx series boards.
++
+ config SPI_S3C24XX
+       tristate "Samsung S3C24XX series SPI"
+       depends on ARCH_S3C24XX && EXPERIMENTAL
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_PL022)                      += spi-pl022.o
+ obj-$(CONFIG_SPI_PPC4xx)              += spi-ppc4xx.o
+ obj-$(CONFIG_SPI_PXA2XX)              += spi-pxa2xx.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI)          += spi-pxa2xx-pci.o
++obj-$(CONFIG_SPI_RB4XX)                       += spi-rb4xx.o
+ obj-$(CONFIG_SPI_RSPI)                        += spi-rspi.o
+ obj-$(CONFIG_SPI_S3C24XX)             += spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y                      := spi-s3c24xx.o
diff --git a/target/linux/ar71xx/patches-3.8/433-spi-rb4xx-cpld-driver.patch b/target/linux/ar71xx/patches-3.8/433-spi-rb4xx-cpld-driver.patch
new file mode 100644 (file)
index 0000000..8fb9fa5
--- /dev/null
@@ -0,0 +1,26 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -509,6 +509,13 @@ config SPI_TLE62X0
+         sysfs interface, with each line presented as a kind of GPIO
+         exposing both switch control and diagnostic feedback.
++config SPI_RB4XX_CPLD
++      tristate "MikroTik RB4XX CPLD driver"
++      depends on ATH79_MACH_RB4XX
++      help
++        SPI driver for the Xilinx CPLD chip present on the
++        MikroTik RB4xx boards.
++
+ #
+ # Add new SPI protocol masters in alphabetical order above this line
+ #
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -51,6 +51,7 @@ obj-$(CONFIG_SPI_PPC4xx)             += spi-ppc4xx.
+ obj-$(CONFIG_SPI_PXA2XX)              += spi-pxa2xx.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI)          += spi-pxa2xx-pci.o
+ obj-$(CONFIG_SPI_RB4XX)                       += spi-rb4xx.o
++obj-$(CONFIG_SPI_RB4XX_CPLD)          += spi-rb4xx-cpld.o
+ obj-$(CONFIG_SPI_RSPI)                        += spi-rspi.o
+ obj-$(CONFIG_SPI_S3C24XX)             += spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y                      := spi-s3c24xx.o
diff --git a/target/linux/ar71xx/patches-3.8/434-spi-ap83_spi_controller.patch b/target/linux/ar71xx/patches-3.8/434-spi-ap83_spi_controller.patch
new file mode 100644 (file)
index 0000000..964ffe3
--- /dev/null
@@ -0,0 +1,27 @@
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_SPIDEV)             += spidev.o
+ # SPI master controller drivers (bus)
+ obj-$(CONFIG_SPI_ALTERA)              += spi-altera.o
+ obj-$(CONFIG_SPI_ATMEL)                       += spi-atmel.o
++obj-$(CONFIG_SPI_AP83)                        += spi-ap83.o
+ obj-$(CONFIG_SPI_ATH79)                       += spi-ath79.o
+ obj-$(CONFIG_SPI_AU1550)              += spi-au1550.o
+ obj-$(CONFIG_SPI_BCM63XX)             += spi-bcm63xx.o
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -59,6 +59,14 @@ config SPI_ALTERA
+       help
+         This is the driver for the Altera SPI Controller.
++config SPI_AP83
++      tristate "Atheros AP83 specific SPI Controller"
++      depends on SPI_MASTER && ATH79_MACH_AP83
++      select SPI_BITBANG
++      help
++        This is a specific SPI controller driver for the Atheros AP83
++        reference board.
++
+ config SPI_ATH79
+       tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
+       depends on ATH79 && GENERIC_GPIO
diff --git a/target/linux/ar71xx/patches-3.8/435-spi-vsc7385_driver.patch b/target/linux/ar71xx/patches-3.8/435-spi-vsc7385_driver.patch
new file mode 100644 (file)
index 0000000..c06ae53
--- /dev/null
@@ -0,0 +1,23 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -524,6 +524,11 @@ config SPI_RB4XX_CPLD
+         SPI driver for the Xilinx CPLD chip present on the
+         MikroTik RB4xx boards.
++config SPI_VSC7385
++      tristate "Vitesse VSC7385 ethernet switch driver"
++      help
++        SPI driver for the Vitesse VSC7385 ethernet switch.
++
+ #
+ # Add new SPI protocol masters in alphabetical order above this line
+ #
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -70,5 +70,6 @@ obj-$(CONFIG_SPI_TI_SSP)             += spi-ti-ssp.
+ obj-$(CONFIG_SPI_TLE62X0)             += spi-tle62x0.o
+ obj-$(CONFIG_SPI_TOPCLIFF_PCH)                += spi-topcliff-pch.o
+ obj-$(CONFIG_SPI_TXX9)                        += spi-txx9.o
++obj-$(CONFIG_SPI_VSC7385)             += spi-vsc7385.o
+ obj-$(CONFIG_SPI_XCOMM)               += spi-xcomm.o
+ obj-$(CONFIG_SPI_XILINX)              += spi-xilinx.o
diff --git a/target/linux/ar71xx/patches-3.8/440-leds-wndr3700-usb-led-driver.patch b/target/linux/ar71xx/patches-3.8/440-leds-wndr3700-usb-led-driver.patch
new file mode 100644 (file)
index 0000000..e82277a
--- /dev/null
@@ -0,0 +1,26 @@
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -467,6 +467,13 @@ config LEDS_TRIGGERS
+         These triggers allow kernel events to drive the LEDs and can
+         be configured via sysfs. If unsure, say Y.
++config LEDS_WNDR3700_USB
++      tristate "NETGEAR WNDR3700 USB LED driver"
++      depends on LEDS_CLASS && ATH79_MACH_WNDR3700
++      help
++        This option enables support for the USB LED found on the
++        NETGEAR WNDR3700 board.
++
+ comment "LED Triggers"
+ config LEDS_TRIGGER_TIMER
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -38,6 +38,7 @@ obj-$(CONFIG_LEDS_DA9052)            += leds-da905
+ obj-$(CONFIG_LEDS_WM831X_STATUS)      += leds-wm831x-status.o
+ obj-$(CONFIG_LEDS_WM8350)             += leds-wm8350.o
+ obj-$(CONFIG_LEDS_PWM)                        += leds-pwm.o
++obj-${CONFIG_LEDS_WNDR3700_USB}               += leds-wndr3700-usb.o
+ obj-$(CONFIG_LEDS_REGULATOR)          += leds-regulator.o
+ obj-$(CONFIG_LEDS_INTEL_SS4200)               += leds-ss4200.o
+ obj-$(CONFIG_LEDS_LT3593)             += leds-lt3593.o
diff --git a/target/linux/ar71xx/patches-3.8/441-leds-rb750-led-driver.patch b/target/linux/ar71xx/patches-3.8/441-leds-rb750-led-driver.patch
new file mode 100644 (file)
index 0000000..4eaa604
--- /dev/null
@@ -0,0 +1,23 @@
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -474,6 +474,10 @@ config LEDS_WNDR3700_USB
+         This option enables support for the USB LED found on the
+         NETGEAR WNDR3700 board.
++config LEDS_RB750
++      tristate "LED driver for the Mikrotik RouterBOARD 750"
++      depends on LEDS_CLASS && ATH79_MACH_RB750
++
+ comment "LED Triggers"
+ config LEDS_TRIGGER_TIMER
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -45,6 +45,7 @@ obj-$(CONFIG_LEDS_LT3593)            += leds-lt359
+ obj-$(CONFIG_LEDS_ADP5520)            += leds-adp5520.o
+ obj-$(CONFIG_LEDS_DELL_NETBOOKS)      += dell-led.o
+ obj-$(CONFIG_LEDS_MC13783)            += leds-mc13783.o
++obj-$(CONFIG_LEDS_RB750)              += leds-rb750.o
+ obj-$(CONFIG_LEDS_NS2)                        += leds-ns2.o
+ obj-$(CONFIG_LEDS_NETXBIG)            += leds-netxbig.o
+ obj-$(CONFIG_LEDS_ASIC3)              += leds-asic3.o
diff --git a/target/linux/ar71xx/patches-3.8/450-gpio-nxp-74hc153-gpio-chip-driver.patch b/target/linux/ar71xx/patches-3.8/450-gpio-nxp-74hc153-gpio-chip-driver.patch
new file mode 100644 (file)
index 0000000..97e15cd
--- /dev/null
@@ -0,0 +1,25 @@
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -697,4 +697,12 @@ config GPIO_VIPERBOARD
+           River Tech's viperboard.h for detailed meaning
+           of the module parameters.
++comment "Other GPIO expanders"
++
++config GPIO_NXP_74HC153
++      tristate "NXP 74HC153 Dual 4-input multiplexer"
++      help
++        Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
++        provides a GPIO interface supporting input mode only.
++
+ endif
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -48,6 +48,7 @@ obj-$(CONFIG_GPIO_MSM_V2)    += gpio-msm-v2
+ obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
+ obj-$(CONFIG_GPIO_MXC)                += gpio-mxc.o
+ obj-$(CONFIG_GPIO_MXS)                += gpio-mxs.o
++obj-$(CONFIG_GPIO_NXP_74HC153)        += gpio-nxp-74hc153.o
+ obj-$(CONFIG_ARCH_OMAP)               += gpio-omap.o
+ obj-$(CONFIG_GPIO_PCA953X)    += gpio-pca953x.o
+ obj-$(CONFIG_GPIO_PCF857X)    += gpio-pcf857x.o
diff --git a/target/linux/ar71xx/patches-3.8/460-spi-bitbang-export-spi_bitbang_bufs.patch b/target/linux/ar71xx/patches-3.8/460-spi-bitbang-export-spi_bitbang_bufs.patch
new file mode 100644 (file)
index 0000000..919b85c
--- /dev/null
@@ -0,0 +1,28 @@
+--- a/drivers/spi/spi-bitbang.c
++++ b/drivers/spi/spi-bitbang.c
+@@ -234,13 +234,14 @@ void spi_bitbang_cleanup(struct spi_devi
+ }
+ EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
+-static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
++int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
+ {
+       struct spi_bitbang_cs   *cs = spi->controller_state;
+       unsigned                nsecs = cs->nsecs;
+       return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
+ }
++EXPORT_SYMBOL_GPL(spi_bitbang_bufs);
+ /*----------------------------------------------------------------------*/
+--- a/include/linux/spi/spi_bitbang.h
++++ b/include/linux/spi/spi_bitbang.h
+@@ -44,6 +44,7 @@ extern void spi_bitbang_cleanup(struct s
+ extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m);
+ extern int spi_bitbang_setup_transfer(struct spi_device *spi,
+                                     struct spi_transfer *t);
++extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t);
+ /* start or stop queue processing */
+ extern int spi_bitbang_start(struct spi_bitbang *spi);
diff --git a/target/linux/ar71xx/patches-3.8/461-spi-add-type-field-to-spi_transfer.patch b/target/linux/ar71xx/patches-3.8/461-spi-add-type-field-to-spi_transfer.patch
new file mode 100644 (file)
index 0000000..d956499
--- /dev/null
@@ -0,0 +1,23 @@
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -409,6 +409,12 @@ extern struct spi_master *spi_busnum_to_
+ /*---------------------------------------------------------------------------*/
++enum spi_transfer_type {
++      SPI_TRANSFER_GENERIC = 0,
++      SPI_TRANSFER_FLASH_READ_CMD,
++      SPI_TRANSFER_FLASH_READ_DATA,
++};
++
+ /*
+  * I/O INTERFACE between SPI controller and protocol drivers
+  *
+@@ -511,6 +517,7 @@ struct spi_transfer {
+       u8              bits_per_word;
+       u16             delay_usecs;
+       u32             speed_hz;
++      enum spi_transfer_type type;
+       struct list_head transfer_list;
+ };
diff --git a/target/linux/ar71xx/patches-3.8/462-mtd-m25p80-set-spi-transfer-type.patch b/target/linux/ar71xx/patches-3.8/462-mtd-m25p80-set-spi-transfer-type.patch
new file mode 100644 (file)
index 0000000..e1ceb66
--- /dev/null
@@ -0,0 +1,15 @@
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -357,10 +357,12 @@ static int m25p80_read(struct mtd_info *
+        * OPCODE_FAST_READ (if available) is faster.
+        * Should add 1 byte DUMMY_BYTE.
+        */
++      t[0].type = SPI_TRANSFER_FLASH_READ_CMD;
+       t[0].tx_buf = flash->command;
+       t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
+       spi_message_add_tail(&t[0], &m);
++      t[1].type = SPI_TRANSFER_FLASH_READ_DATA;
+       spi_message_add_tail(&t[1], &m);
+       mutex_lock(&flash->lock);
diff --git a/target/linux/ar71xx/patches-3.8/463-spi-ath79-add-fast-flash-read.patch b/target/linux/ar71xx/patches-3.8/463-spi-ath79-add-fast-flash-read.patch
new file mode 100644 (file)
index 0000000..e861644
--- /dev/null
@@ -0,0 +1,185 @@
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -37,6 +37,11 @@
+ #define ATH79_SPI_CS_LINE_MAX         2
++enum ath79_spi_state {
++      ATH79_SPI_STATE_WAIT_CMD = 0,
++      ATH79_SPI_STATE_WAIT_READ,
++};
++
+ struct ath79_spi {
+       struct spi_bitbang      bitbang;
+       u32                     ioc_base;
+@@ -44,6 +49,11 @@ struct ath79_spi {
+       void __iomem            *base;
+       struct clk              *clk;
+       unsigned                rrw_delay;
++
++      enum ath79_spi_state    state;
++      u32                     clk_div;
++      unsigned long           read_addr;
++      unsigned long           ahb_rate;
+ };
+ static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
+@@ -111,9 +121,6 @@ static void ath79_spi_enable(struct ath7
+       /* save CTRL register */
+       sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
+       sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
+-
+-      /* TODO: setup speed? */
+-      ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
+ }
+ static void ath79_spi_disable(struct ath79_spi *sp)
+@@ -232,6 +239,110 @@ static u32 ath79_spi_txrx_mode0(struct s
+       return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
+ }
++static int ath79_spi_do_read_flash_data(struct spi_device *spi,
++                                      struct spi_transfer *t)
++{
++      struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++
++      /* disable GPIO mode */
++      ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++
++      memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len);
++
++      /* enable GPIO mode */
++      ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
++
++      /* restore IOC register */
++      ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
++
++      return t->len;
++}
++
++static int ath79_spi_do_read_flash_cmd(struct spi_device *spi,
++                                     struct spi_transfer *t)
++{
++      struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++      int len;
++      const u8 *p;
++
++      sp->read_addr = 0;
++
++      len = t->len - 1;
++      p = t->tx_buf;
++
++      while (len--) {
++              p++;
++              sp->read_addr <<= 8;
++              sp->read_addr |= *p;
++      }
++
++      return t->len;
++}
++
++static bool ath79_spi_is_read_cmd(struct spi_device *spi,
++                               struct spi_transfer *t)
++{
++      return t->type == SPI_TRANSFER_FLASH_READ_CMD;
++}
++
++static bool ath79_spi_is_data_read(struct spi_device *spi,
++                                struct spi_transfer *t)
++{
++      return t->type == SPI_TRANSFER_FLASH_READ_DATA;
++}
++
++static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
++{
++      struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++      int ret;
++
++      switch (sp->state) {
++      case ATH79_SPI_STATE_WAIT_CMD:
++              if (ath79_spi_is_read_cmd(spi, t)) {
++                      ret = ath79_spi_do_read_flash_cmd(spi, t);
++                      sp->state = ATH79_SPI_STATE_WAIT_READ;
++              } else {
++                      ret = spi_bitbang_bufs(spi, t);
++              }
++              break;
++
++      case ATH79_SPI_STATE_WAIT_READ:
++              if (ath79_spi_is_data_read(spi, t)) {
++                      ret = ath79_spi_do_read_flash_data(spi, t);
++              } else {
++                      dev_warn(&spi->dev, "flash data read expected\n");
++                      ret = -EIO;
++              }
++              sp->state = ATH79_SPI_STATE_WAIT_CMD;
++              break;
++
++      default:
++              BUG();
++      }
++
++      return ret;
++}
++
++static int ath79_spi_setup_transfer(struct spi_device *spi,
++                                  struct spi_transfer *t)
++{
++      struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++      struct ath79_spi_controller_data *cdata;
++      int ret;
++
++      ret = spi_bitbang_setup_transfer(spi, t);
++      if (ret)
++              return ret;
++
++      cdata = spi->controller_data;
++      if (cdata->is_flash)
++              sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs;
++      else
++              sp->bitbang.txrx_bufs = spi_bitbang_bufs;
++
++      return ret;
++}
++
+ static int ath79_spi_probe(struct platform_device *pdev)
+ {
+       struct spi_master *master;
+@@ -254,6 +365,8 @@ static int ath79_spi_probe(struct platfo
+       sp = spi_master_get_devdata(master);
+       platform_set_drvdata(pdev, sp);
++      sp->state = ATH79_SPI_STATE_WAIT_CMD;
++
+       master->setup = ath79_spi_setup;
+       master->cleanup = ath79_spi_cleanup;
+       master->bus_num = pdata->bus_num;
+@@ -262,7 +375,7 @@ static int ath79_spi_probe(struct platfo
+       sp->bitbang.master = spi_master_get(master);
+       sp->bitbang.chipselect = ath79_spi_chipselect;
+       sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
+-      sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
++      sp->bitbang.setup_transfer = ath79_spi_setup_transfer;
+       sp->bitbang.flags = SPI_CS_HIGH;
+       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -287,7 +400,8 @@ static int ath79_spi_probe(struct platfo
+       if (ret)
+               goto err_clk_put;
+-      rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
++      sp->ahb_rate = clk_get_rate(sp->clk);
++      rate = DIV_ROUND_UP(sp->ahb_rate, MHZ);
+       if (!rate) {
+               ret = -EINVAL;
+               goto err_clk_disable;
+--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+@@ -24,6 +24,7 @@ enum ath79_spi_cs_type {
+ struct ath79_spi_controller_data {
+       enum ath79_spi_cs_type cs_type;
+       unsigned cs_line;
++      bool is_flash;
+ };
+ #endif /* _ATH79_SPI_PLATFORM_H */
diff --git a/target/linux/ar71xx/patches-3.8/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ar71xx/patches-3.8/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch
new file mode 100644 (file)
index 0000000..7912384
--- /dev/null
@@ -0,0 +1,111 @@
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
+@@ -0,0 +1,37 @@
++/*
++ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
++ *      Copyright (C) 2003, 2004 Ralf Baechle
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
++#define __ASM_MACH_ATH79_MANGLE_PORT_H
++
++#ifdef CONFIG_PCI
++extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
++extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
++#else
++#define ath79_pci_swizzle_b(port) (port)
++#define ath79_pci_swizzle_w(port) (port)
++#endif
++
++#define __swizzle_addr_b(port)        ath79_pci_swizzle_b(port)
++#define __swizzle_addr_w(port)        ath79_pci_swizzle_w(port)
++#define __swizzle_addr_l(port)        (port)
++#define __swizzle_addr_q(port)        (port)
++
++# define ioswabb(a, x)           (x)
++# define __mem_ioswabb(a, x)     (x)
++# define ioswabw(a, x)           (x)
++# define __mem_ioswabw(a, x)     cpu_to_le16(x)
++# define ioswabl(a, x)           (x)
++# define __mem_ioswabl(a, x)     cpu_to_le32(x)
++# define ioswabq(a, x)           (x)
++# define __mem_ioswabq(a, x)     cpu_to_le64(x)
++
++#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -13,6 +13,7 @@
+  */
+ #include <linux/init.h>
++#include <linux/export.h>
+ #include <linux/pci.h>
+ #include <linux/resource.h>
+ #include <linux/platform_device.h>
+@@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st
+ static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
+ static unsigned ath79_pci_nr_irqs __initdata;
++static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
++static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
++
+ static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
+       {
+               .slot   = 17,
+@@ -202,12 +206,50 @@ ath79_register_pci_ar724x(int id,
+       return pdev;
+ }
++static inline bool ar71xx_is_pci_addr(unsigned long port)
++{
++      unsigned long phys = CPHYSADDR(port);
++
++      return (phys >= AR71XX_PCI_MEM_BASE &&
++              phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
++}
++
++static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
++{
++      return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
++}
++
++static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
++{
++      return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
++}
++
++unsigned long ath79_pci_swizzle_b(unsigned long port)
++{
++      if (__ath79_pci_swizzle_b)
++              return __ath79_pci_swizzle_b(port);
++
++      return port;
++}
++EXPORT_SYMBOL(ath79_pci_swizzle_b);
++
++unsigned long ath79_pci_swizzle_w(unsigned long port)
++{
++      if (__ath79_pci_swizzle_w)
++              return __ath79_pci_swizzle_w(port);
++
++      return port;
++}
++EXPORT_SYMBOL(ath79_pci_swizzle_w);
++
+ int __init ath79_register_pci(void)
+ {
+       struct platform_device *pdev = NULL;
+       if (soc_is_ar71xx()) {
+               pdev = ath79_register_pci_ar71xx();
++              __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
++              __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
+       } else if (soc_is_ar724x()) {
+               pdev = ath79_register_pci_ar724x(-1,
+                                                AR724X_PCI_CFG_BASE,
diff --git a/target/linux/ar71xx/patches-3.8/500-MIPS-fw-myloader.patch b/target/linux/ar71xx/patches-3.8/500-MIPS-fw-myloader.patch
new file mode 100644 (file)
index 0000000..4abd832
--- /dev/null
@@ -0,0 +1,22 @@
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -180,6 +180,7 @@ endif
+ #
+ libs-$(CONFIG_FW_ARC)         += arch/mips/fw/arc/
+ libs-$(CONFIG_FW_CFE)         += arch/mips/fw/cfe/
++libs-$(CONFIG_MYLOADER)               += arch/mips/fw/myloader/
+ libs-$(CONFIG_FW_SNIPROM)     += arch/mips/fw/sni/
+ libs-y                                += arch/mips/fw/lib/
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -989,6 +989,9 @@ config MIPS_NILE4
+ config MIPS_DISABLE_OBSOLETE_IDE
+       bool
++config MYLOADER
++      bool
++
+ config SYNC_R4K
+       bool
diff --git a/target/linux/ar71xx/patches-3.8/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch b/target/linux/ar71xx/patches-3.8/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch
new file mode 100644 (file)
index 0000000..de0db9a
--- /dev/null
@@ -0,0 +1,81 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -15,6 +15,7 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/irq.h>
++#include <linux/etherdevice.h>
+ #include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
+@@ -22,6 +23,7 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include "dev-wmac.h"
++static u8 ath79_wmac_mac[ETH_ALEN];
+ static struct ath9k_platform_data ath79_wmac_data;
+ static struct resource ath79_wmac_resources[] = {
+@@ -151,7 +153,7 @@ static void qca955x_wmac_setup(void)
+               ath79_wmac_data.is_clk_25mhz = true;
+ }
+-void __init ath79_register_wmac(u8 *cal_data)
++void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+       if (soc_is_ar913x())
+               ar913x_wmac_setup();
+@@ -168,5 +170,10 @@ void __init ath79_register_wmac(u8 *cal_
+               memcpy(ath79_wmac_data.eeprom_data, cal_data,
+                      sizeof(ath79_wmac_data.eeprom_data));
++      if (mac_addr) {
++              memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac));
++              ath79_wmac_data.macaddr = ath79_wmac_mac;
++      }
++
+       platform_device_register(&ath79_wmac_device);
+ }
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -12,6 +12,6 @@
+ #ifndef _ATH79_DEV_WMAC_H
+ #define _ATH79_DEV_WMAC_H
+-void ath79_register_wmac(u8 *cal_data);
++void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -98,7 +98,7 @@ static void __init ap81_setup(void)
+                                       ap81_gpio_keys);
+       ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+                          ARRAY_SIZE(ap81_spi_info));
+-      ath79_register_wmac(cal_data);
++      ath79_register_wmac(cal_data, NULL);
+       ath79_register_usb();
+ }
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -134,7 +134,7 @@ static void __init db120_setup(void)
+       ath79_register_spi(&db120_spi_data, db120_spi_info,
+                          ARRAY_SIZE(db120_spi_info));
+       ath79_register_usb();
+-      ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
++      ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+       db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
+ }
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -91,7 +91,7 @@ static void __init ap121_setup(void)
+       ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+                          ARRAY_SIZE(ap121_spi_info));
+       ath79_register_usb();
+-      ath79_register_wmac(cal_data);
++      ath79_register_wmac(cal_data, NULL);
+ }
+ MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
diff --git a/target/linux/ar71xx/patches-3.8/502-MIPS-ath79-export-ath79_gpio_base.patch b/target/linux/ar71xx/patches-3.8/502-MIPS-ath79-export-ath79_gpio_base.patch
new file mode 100644 (file)
index 0000000..73eb8e1
--- /dev/null
@@ -0,0 +1,23 @@
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -25,7 +25,9 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include "common.h"
+-static void __iomem *ath79_gpio_base;
++void __iomem *ath79_gpio_base;
++EXPORT_SYMBOL_GPL(ath79_gpio_base);
++
+ static unsigned long ath79_gpio_count;
+ static DEFINE_SPINLOCK(ath79_gpio_lock);
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -116,6 +116,7 @@ static inline int soc_is_qca955x(void)
+ }
+ extern void __iomem *ath79_ddr_base;
++extern void __iomem *ath79_gpio_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
diff --git a/target/linux/ar71xx/patches-3.8/503-MIPS-ath79-add-flash-acquire-release.patch b/target/linux/ar71xx/patches-3.8/503-MIPS-ath79-add-flash-acquire-release.patch
new file mode 100644 (file)
index 0000000..15e7faa
--- /dev/null
@@ -0,0 +1,37 @@
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -22,6 +22,7 @@
+ #include "common.h"
+ static DEFINE_SPINLOCK(ath79_device_reset_lock);
++static DEFINE_MUTEX(ath79_flash_mutex);
+ u32 ath79_cpu_freq;
+ EXPORT_SYMBOL_GPL(ath79_cpu_freq);
+@@ -109,3 +110,16 @@ void ath79_device_reset_clear(u32 mask)
+       spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
+ }
+ EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
++
++void ath79_flash_acquire(void)
++{
++      mutex_lock(&ath79_flash_mutex);
++}
++EXPORT_SYMBOL_GPL(ath79_flash_acquire);
++
++void ath79_flash_release(void)
++{
++      mutex_unlock(&ath79_flash_mutex);
++}
++EXPORT_SYMBOL_GPL(ath79_flash_release);
++
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -143,4 +143,7 @@ static inline u32 ath79_reset_rr(unsigne
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
++void ath79_flash_acquire(void);
++void ath79_flash_release(void);
++
+ #endif /* __ASM_MACH_ATH79_H */
diff --git a/target/linux/ar71xx/patches-3.8/504-MIPS-ath79-add-ath79_device_reset_get.patch b/target/linux/ar71xx/patches-3.8/504-MIPS-ath79-add-ath79_device_reset_get.patch
new file mode 100644 (file)
index 0000000..e99b66f
--- /dev/null
@@ -0,0 +1,45 @@
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -142,6 +142,7 @@ static inline u32 ath79_reset_rr(unsigne
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
++u32 ath79_device_reset_get(u32 mask);
+ void ath79_flash_acquire(void);
+ void ath79_flash_release(void);
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -111,6 +111,32 @@ void ath79_device_reset_clear(u32 mask)
+ }
+ EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
++u32 ath79_device_reset_get(u32 mask)
++{
++      unsigned long flags;
++      u32 reg;
++      u32 ret;
++
++      if (soc_is_ar71xx())
++              reg = AR71XX_RESET_REG_RESET_MODULE;
++      else if (soc_is_ar724x())
++              reg = AR724X_RESET_REG_RESET_MODULE;
++      else if (soc_is_ar913x())
++              reg = AR913X_RESET_REG_RESET_MODULE;
++      else if (soc_is_ar933x())
++              reg = AR933X_RESET_REG_RESET_MODULE;
++      else if (soc_is_ar934x())
++              reg = AR934X_RESET_REG_RESET_MODULE;
++      else
++              BUG();
++
++      spin_lock_irqsave(&ath79_device_reset_lock, flags);
++      ret = ath79_reset_rr(reg);
++      spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
++      return ret;
++}
++EXPORT_SYMBOL_GPL(ath79_device_reset_get);
++
+ void ath79_flash_acquire(void)
+ {
+       mutex_lock(&ath79_flash_mutex);
diff --git a/target/linux/ar71xx/patches-3.8/505-MIPS-ath79-add-ath79_gpio_function_select.patch b/target/linux/ar71xx/patches-3.8/505-MIPS-ath79-add-ath79_gpio_function_select.patch
new file mode 100644 (file)
index 0000000..86e136f
--- /dev/null
@@ -0,0 +1,47 @@
+--- a/arch/mips/ath79/common.h
++++ b/arch/mips/ath79/common.h
+@@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg
+ void ath79_gpio_function_enable(u32 mask);
+ void ath79_gpio_function_disable(u32 mask);
+ void ath79_gpio_function_setup(u32 set, u32 clear);
++void ath79_gpio_output_select(unsigned gpio, u8 val);
+ void ath79_gpio_init(void);
+ #endif /* __ATH79_COMMON_H */
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -198,6 +198,34 @@ void ath79_gpio_function_setup(u32 set,
+       spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
++void __init ath79_gpio_output_select(unsigned gpio, u8 val)
++{
++      void __iomem *base = ath79_gpio_base;
++      unsigned long flags;
++      unsigned int reg;
++      u32 t, s;
++
++      BUG_ON(!soc_is_ar934x());
++
++      if (gpio >= AR934X_GPIO_COUNT)
++              return;
++
++      reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
++      s = 8 * (gpio % 4);
++
++      spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++      t = __raw_readl(base + reg);
++      t &= ~(0xff << s);
++      t |= val << s;
++      __raw_writel(t, base + reg);
++
++      /* flush write */
++      (void) __raw_readl(base + reg);
++
++      spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++}
++
+ void __init ath79_gpio_init(void)
+ {
+       int err;
diff --git a/target/linux/ar71xx/patches-3.8/506-MIPS-ath79-prom-parse-redboot-args.patch b/target/linux/ar71xx/patches-3.8/506-MIPS-ath79-prom-parse-redboot-args.patch
new file mode 100644 (file)
index 0000000..aab959b
--- /dev/null
@@ -0,0 +1,86 @@
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -19,6 +19,8 @@
+ #include "common.h"
++static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata;
++
+ static inline int is_valid_ram_addr(void *addr)
+ {
+       if (((u32) addr > KSEG0) &&
+@@ -32,6 +34,41 @@ static inline int is_valid_ram_addr(void
+       return 0;
+ }
++static void __init ath79_prom_append_cmdline(const char *name,
++                                            const char *value)
++{
++      snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf),
++               " %s=%s", name, value);
++      strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline));
++}
++
++static const char * __init ath79_prom_find_env(char **envp, const char *name)
++{
++      const char *ret = NULL;
++      int len;
++      char **p;
++
++      if (!is_valid_ram_addr(envp))
++              return NULL;
++
++      len = strlen(name);
++      for (p = envp; is_valid_ram_addr(*p); p++) {
++              if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') {
++                      ret = *p + len + 1;
++                      break;
++              }
++
++              /* RedBoot env comes in pointer pairs - key, value */
++              if (strncmp(name, *p, len) == 0 && (*p)[len] == 0)
++                      if (is_valid_ram_addr(*(++p))) {
++                              ret = *p;
++                              break;
++                      }
++      }
++
++      return ret;
++}
++
+ static __init void ath79_prom_init_cmdline(int argc, char **argv)
+ {
+       int i;
+@@ -48,7 +85,32 @@ static __init void ath79_prom_init_cmdli
+ void __init prom_init(void)
+ {
++      const char *env;
++      char **envp;
++
+       ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
++
++      envp = (char **)fw_arg2;
++      if (!strstr(arcs_cmdline, "ethaddr=")) {
++              env = ath79_prom_find_env(envp, "ethaddr");
++              if (env)
++                      ath79_prom_append_cmdline("ethaddr", env);
++      }
++
++      if (!strstr(arcs_cmdline, "board=")) {
++              env = ath79_prom_find_env(envp, "board");
++              if (env) {
++                      /* Workaround for buggy bootloaders */
++                      if (strcmp(env, "RouterStation") == 0 ||
++                          strcmp(env, "Ubiquiti AR71xx-based board") == 0)
++                              env = "UBNT-RS";
++
++                      if (strcmp(env, "RouterStation PRO") == 0)
++                              env = "UBNT-RSPRO";
++
++                      ath79_prom_append_cmdline("board", env);
++              }
++      }
+ }
+ void __init prom_free_prom_memory(void)
diff --git a/target/linux/ar71xx/patches-3.8/507-MIPS-ath79-prom-add-myloader-support.patch b/target/linux/ar71xx/patches-3.8/507-MIPS-ath79-prom-add-myloader-support.patch
new file mode 100644 (file)
index 0000000..67c1faf
--- /dev/null
@@ -0,0 +1,58 @@
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -16,6 +16,7 @@
+ #include <asm/bootinfo.h>
+ #include <asm/addrspace.h>
++#include <asm/fw/myloader/myloader.h>
+ #include "common.h"
+@@ -69,6 +70,37 @@ static const char * __init ath79_prom_fi
+       return ret;
+ }
++static int __init ath79_prom_init_myloader(void)
++{
++      struct myloader_info *mylo;
++      char mac_buf[32];
++      unsigned char *mac;
++
++      mylo = myloader_get_info();
++      if (!mylo)
++              return 0;
++
++      switch (mylo->did) {
++      case DEVID_COMPEX_WP543:
++              ath79_prom_append_cmdline("board", "WP543");
++              break;
++      case DEVID_COMPEX_WPE72:
++              ath79_prom_append_cmdline("board", "WPE72");
++              break;
++      default:
++              pr_warn("prom: unknown device id: %x\n", mylo->did);
++              return 0;
++      }
++
++      mac = mylo->macs[0];
++      snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x",
++               mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++
++      ath79_prom_append_cmdline("ethaddr", mac_buf);
++
++      return 1;
++}
++
+ static __init void ath79_prom_init_cmdline(int argc, char **argv)
+ {
+       int i;
+@@ -88,6 +120,9 @@ void __init prom_init(void)
+       const char *env;
+       char **envp;
++      if (ath79_prom_init_myloader())
++              return;
++
+       ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
+       envp = (char **)fw_arg2;
diff --git a/target/linux/ar71xx/patches-3.8/508-MIPS-ath79-prom-image-command-line-hack.patch b/target/linux/ar71xx/patches-3.8/508-MIPS-ath79-prom-image-command-line-hack.patch
new file mode 100644 (file)
index 0000000..72a3b56
--- /dev/null
@@ -0,0 +1,57 @@
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -70,6 +70,35 @@ static const char * __init ath79_prom_fi
+       return ret;
+ }
++#ifdef CONFIG_IMAGE_CMDLINE_HACK
++extern char __image_cmdline[];
++
++static int __init ath79_use_image_cmdline(void)
++{
++      char *p = __image_cmdline;
++      int replace = 0;
++
++      if (*p == '-') {
++              replace = 1;
++              p++;
++      }
++
++      if (*p == '\0')
++              return 0;
++
++      if (replace) {
++              strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
++      } else {
++              strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
++              strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
++      }
++
++      return 1;
++}
++#else
++static inline int ath79_use_image_cmdline(void) { return 0; }
++#endif
++
+ static int __init ath79_prom_init_myloader(void)
+ {
+       struct myloader_info *mylo;
+@@ -98,6 +127,8 @@ static int __init ath79_prom_init_myload
+       ath79_prom_append_cmdline("ethaddr", mac_buf);
++      ath79_use_image_cmdline();
++
+       return 1;
+ }
+@@ -105,6 +136,9 @@ static __init void ath79_prom_init_cmdli
+ {
+       int i;
++      if (ath79_use_image_cmdline())
++              return;
++
+       if (!is_valid_ram_addr(argv))
+               return;
diff --git a/target/linux/ar71xx/patches-3.8/509-MIPS-ath79-process-board-kernel-option.patch b/target/linux/ar71xx/patches-3.8/509-MIPS-ath79-process-board-kernel-option.patch
new file mode 100644 (file)
index 0000000..7858a90
--- /dev/null
@@ -0,0 +1,11 @@
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -231,6 +231,8 @@ void __init plat_time_init(void)
+       mips_hpt_frequency = clk_get_rate(clk) / 2;
+ }
++__setup("board=", mips_machtype_setup);
++
+ static int __init ath79_setup(void)
+ {
+       ath79_gpio_init();
diff --git a/target/linux/ar71xx/patches-3.8/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch b/target/linux/ar71xx/patches-3.8/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch
new file mode 100644 (file)
index 0000000..2d2235e
--- /dev/null
@@ -0,0 +1,14 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -24,7 +24,10 @@
+ #include "dev-wmac.h"
+ static u8 ath79_wmac_mac[ETH_ALEN];
+-static struct ath9k_platform_data ath79_wmac_data;
++
++static struct ath9k_platform_data ath79_wmac_data = {
++      .led_pin = -1,
++};
+ static struct resource ath79_wmac_resources[] = {
+       {
diff --git a/target/linux/ar71xx/patches-3.8/520-MIPS-ath79-enable-UART-function.patch b/target/linux/ar71xx/patches-3.8/520-MIPS-ath79-enable-UART-function.patch
new file mode 100644 (file)
index 0000000..1cb407f
--- /dev/null
@@ -0,0 +1,18 @@
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -87,6 +87,15 @@ void __init ath79_register_uart(void)
+       if (IS_ERR(clk))
+               panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
++      if (soc_is_ar71xx())
++              ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN);
++      else if (soc_is_ar724x())
++              ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN);
++      else if (soc_is_ar913x())
++              ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN);
++      else if (soc_is_ar933x())
++              ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN);
++
+       if (soc_is_ar71xx() ||
+           soc_is_ar724x() ||
+           soc_is_ar913x() ||
diff --git a/target/linux/ar71xx/patches-3.8/521-MIPS-ath79-enable-UART-for-early_serial.patch b/target/linux/ar71xx/patches-3.8/521-MIPS-ath79-enable-UART-for-early_serial.patch
new file mode 100644 (file)
index 0000000..489bc96
--- /dev/null
@@ -0,0 +1,61 @@
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -56,6 +56,46 @@ static void prom_putchar_dummy(unsigned
+       /* nothing to do */
+ }
++static void prom_enable_uart(u32 id)
++{
++      void __iomem *gpio_base;
++      u32 uart_en;
++      u32 t;
++
++      switch (id) {
++      case REV_ID_MAJOR_AR71XX:
++              uart_en = AR71XX_GPIO_FUNC_UART_EN;
++              break;
++
++      case REV_ID_MAJOR_AR7240:
++      case REV_ID_MAJOR_AR7241:
++      case REV_ID_MAJOR_AR7242:
++              uart_en = AR724X_GPIO_FUNC_UART_EN;
++              break;
++
++      case REV_ID_MAJOR_AR913X:
++              uart_en = AR913X_GPIO_FUNC_UART_EN;
++              break;
++
++      case REV_ID_MAJOR_AR9330:
++      case REV_ID_MAJOR_AR9331:
++              uart_en = AR933X_GPIO_FUNC_UART_EN;
++              break;
++
++      case REV_ID_MAJOR_AR9341:
++      case REV_ID_MAJOR_AR9342:
++      case REV_ID_MAJOR_AR9344:
++              /* TODO */
++      default:
++              return;
++      }
++
++      gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE));
++      t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
++      t |= uart_en;
++      __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
++}
++
+ static void prom_putchar_init(void)
+ {
+       void __iomem *base;
+@@ -85,8 +125,10 @@ static void prom_putchar_init(void)
+       default:
+               _prom_putchar = prom_putchar_dummy;
+-              break;
++              return;
+       }
++
++      prom_enable_uart(id);
+ }
+ void prom_putchar(unsigned char ch)
diff --git a/target/linux/ar71xx/patches-3.8/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch b/target/linux/ar71xx/patches-3.8/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch
new file mode 100644 (file)
index 0000000..74309b6
--- /dev/null
@@ -0,0 +1,21 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -180,3 +180,9 @@ void __init ath79_register_wmac(u8 *cal_
+       platform_device_register(&ath79_wmac_device);
+ }
++
++void __init ath79_register_wmac_simple(void)
++{
++      ath79_register_wmac(NULL, NULL);
++      ath79_wmac_data.eeprom_name = "soc_wmac.eeprom";
++}
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -13,5 +13,6 @@
+ #define _ATH79_DEV_WMAC_H
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
++void ath79_register_wmac_simple(void);
+ #endif /* _ATH79_DEV_WMAC_H */
diff --git a/target/linux/ar71xx/patches-3.8/523-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-3.8/523-MIPS-ath79-OTP-support.patch
new file mode 100644 (file)
index 0000000..556a951
--- /dev/null
@@ -0,0 +1,166 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -156,6 +156,137 @@ static void qca955x_wmac_setup(void)
+               ath79_wmac_data.is_clk_25mhz = true;
+ }
++static bool __init
++ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
++{
++      int timeout = 1000;
++      u32 val;
++
++      __raw_readl(base + AR9300_OTP_BASE + (4 * addr));
++      while (timeout--) {
++              val = __raw_readl(base + AR9300_OTP_STATUS);
++              if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
++                      break;
++
++              udelay(10);
++      }
++
++      if (!timeout)
++              return false;
++
++      *data = __raw_readl(base + AR9300_OTP_READ_DATA);
++      return true;
++}
++
++static bool __init
++ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
++{
++      u32 data;
++      int i;
++
++      for (i = 0; i < len; i++) {
++              int offset = 8 * ((addr - i) % 4);
++
++              if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
++                      return false;
++
++              dest[i] = (data >> offset) & 0xff;
++      }
++
++      return true;
++}
++
++static bool __init
++ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
++                         int dest_start, int dest_len)
++{
++      int dest_bytes = 0;
++      int offset = 0;
++      int end = addr - len;
++      u8 hdr[2];
++
++      while (addr > end) {
++              if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
++                      return false;
++
++              addr -= 2;
++              offset += hdr[0];
++
++              if (offset <= dest_start + dest_len &&
++                  offset + len >= dest_start) {
++                      int data_offset = 0;
++                      int dest_offset = 0;
++                      int copy_len;
++
++                      if (offset < dest_start)
++                              data_offset = dest_start - offset;
++                      else
++                              dest_offset = offset - dest_start;
++
++                      copy_len = len - data_offset;
++                      if (copy_len > dest_len - dest_offset)
++                              copy_len = dest_len - dest_offset;
++
++                      ar93xx_wmac_otp_read(base, addr - data_offset,
++                                           dest + dest_offset,
++                                           copy_len);
++
++                      dest_bytes += copy_len;
++              }
++              addr -= hdr[1];
++      }
++      return !!dest_bytes;
++}
++
++bool __init ar93xx_wmac_read_mac_address(u8 *dest)
++{
++      void __iomem *base;
++      bool ret = false;
++      int addr = 0x1ff;
++      unsigned int len;
++      u32 hdr_u32;
++      u8 *hdr = (u8 *) &hdr_u32;
++      u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
++      int mac_start = 2, mac_end = 8;
++
++      BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
++      base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
++      while (addr > sizeof(hdr)) {
++              if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
++                      break;
++
++              if (hdr_u32 == 0 || hdr_u32 == ~0)
++                      break;
++
++              len = (hdr[1] << 4) | (hdr[2] >> 4);
++              addr -= 4;
++
++              switch (hdr[0] >> 5) {
++              case 0:
++                      if (len < mac_end)
++                              break;
++
++                      ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
++                      ret = true;
++                      break;
++              case 3:
++                      ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
++                                                        mac_start, 6);
++                      break;
++              default:
++                      break;
++              }
++
++              addr -= len + 2;
++      }
++
++      iounmap(base);
++      if (ret)
++              memcpy(dest, mac, 6);
++
++      return ret;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+       if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,5 +14,6 @@
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
++bool ar93xx_wmac_read_mac_address(u8 *dest);
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -113,6 +113,14 @@
+ #define QCA955X_EHCI1_BASE    0x1b400000
+ #define QCA955X_EHCI_SIZE     0x200
++#define AR9300_OTP_BASE               0x14000
++#define AR9300_OTP_STATUS     0x15f18
++#define AR9300_OTP_STATUS_TYPE                0x7
++#define AR9300_OTP_STATUS_VALID               0x4
++#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
++#define AR9300_OTP_STATUS_SM_BUSY     0x1
++#define AR9300_OTP_READ_DATA  0x15f1c
++
+ /*
+  * DDR_CTRL block
+  */
diff --git a/target/linux/ar71xx/patches-3.8/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch b/target/linux/ar71xx/patches-3.8/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
new file mode 100644 (file)
index 0000000..8c6fd40
--- /dev/null
@@ -0,0 +1,31 @@
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -287,6 +287,16 @@ bool __init ar93xx_wmac_read_mac_address
+       return ret;
+ }
++void __init ath79_wmac_disable_2ghz(void)
++{
++      ath79_wmac_data.disable_2ghz = true;
++}
++
++void __init ath79_wmac_disable_5ghz(void)
++{
++      ath79_wmac_data.disable_5ghz = true;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+       if (soc_is_ar913x())
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -14,6 +14,9 @@
+ void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+ void ath79_register_wmac_simple(void);
++void ath79_wmac_disable_2ghz(void);
++void ath79_wmac_disable_5ghz(void);
++
+ bool ar93xx_wmac_read_mac_address(u8 *dest);
+ #endif /* _ATH79_DEV_WMAC_H */
diff --git a/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch
new file mode 100644 (file)
index 0000000..fb7d169
--- /dev/null
@@ -0,0 +1,338 @@
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -21,6 +21,10 @@
+ #include <linux/bitops.h>
+ #define AR71XX_APB_BASE               0x18000000
++#define AR71XX_GE0_BASE               0x19000000
++#define AR71XX_GE0_SIZE               0x10000
++#define AR71XX_GE1_BASE               0x1a000000
++#define AR71XX_GE1_SIZE               0x10000
+ #define AR71XX_EHCI_BASE      0x1b000000
+ #define AR71XX_EHCI_SIZE      0x1000
+ #define AR71XX_OHCI_BASE      0x1c000000
+@@ -40,6 +44,8 @@
+ #define AR71XX_PLL_SIZE               0x100
+ #define AR71XX_RESET_BASE     (AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE     0x100
++#define AR71XX_MII_BASE               (AR71XX_APB_BASE + 0x00070000)
++#define AR71XX_MII_SIZE               0x100
+ #define AR71XX_PCI_MEM_BASE   0x10000000
+ #define AR71XX_PCI_MEM_SIZE   0x07000000
+@@ -82,15 +88,21 @@
+ #define AR933X_UART_BASE      (AR71XX_APB_BASE + 0x00020000)
+ #define AR933X_UART_SIZE      0x14
++#define AR933X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
++#define AR933X_GMAC_SIZE      0x04
+ #define AR933X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
+ #define AR933X_WMAC_SIZE      0x20000
+ #define AR933X_EHCI_BASE      0x1b000000
+ #define AR933X_EHCI_SIZE      0x1000
++#define AR934X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
++#define AR934X_GMAC_SIZE      0x14
+ #define AR934X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
+ #define AR934X_WMAC_SIZE      0x20000
+ #define AR934X_EHCI_BASE      0x1b000000
+ #define AR934X_EHCI_SIZE      0x200
++#define AR934X_NFC_BASE               0x1b000200
++#define AR934X_NFC_SIZE               0xb8
+ #define AR934X_SRIF_BASE      (AR71XX_APB_BASE + 0x00116000)
+ #define AR934X_SRIF_SIZE      0x1000
+@@ -112,6 +124,10 @@
+ #define QCA955X_EHCI0_BASE    0x1b000000
+ #define QCA955X_EHCI1_BASE    0x1b400000
+ #define QCA955X_EHCI_SIZE     0x200
++#define QCA955X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
++#define QCA955X_GMAC_SIZE     0x40
++#define QCA955X_NFC_BASE      0x1b800200
++#define QCA955X_NFC_SIZE      0xb8
+ #define AR9300_OTP_BASE               0x14000
+ #define AR9300_OTP_STATUS     0x15f18
+@@ -175,6 +191,9 @@
+ #define AR71XX_AHB_DIV_SHIFT          20
+ #define AR71XX_AHB_DIV_MASK           0x7
++#define AR71XX_ETH0_PLL_SHIFT         17
++#define AR71XX_ETH1_PLL_SHIFT         19
++
+ #define AR724X_PLL_REG_CPU_CONFIG     0x00
+ #define AR724X_PLL_REG_PCIE_CONFIG    0x18
+@@ -187,6 +206,8 @@
+ #define AR724X_DDR_DIV_SHIFT          22
+ #define AR724X_DDR_DIV_MASK           0x3
++#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
++
+ #define AR913X_PLL_REG_CPU_CONFIG     0x00
+ #define AR913X_PLL_REG_ETH_CONFIG     0x04
+ #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
+@@ -199,6 +220,9 @@
+ #define AR913X_AHB_DIV_SHIFT          19
+ #define AR913X_AHB_DIV_MASK           0x1
++#define AR913X_ETH0_PLL_SHIFT         20
++#define AR913X_ETH1_PLL_SHIFT         22
++
+ #define AR933X_PLL_CPU_CONFIG_REG     0x00
+ #define AR933X_PLL_CLOCK_CTRL_REG     0x08
+@@ -220,6 +244,8 @@
+ #define AR934X_PLL_CPU_CONFIG_REG             0x00
+ #define AR934X_PLL_DDR_CONFIG_REG             0x04
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG               0x08
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG   0x24
++#define AR934X_PLL_ETH_XMII_CONTROL_REG               0x2c
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
+ #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
+@@ -252,9 +278,13 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL        BIT(21)
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL        BIT(24)
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL  BIT(6)
++
+ #define QCA955X_PLL_CPU_CONFIG_REG            0x00
+ #define QCA955X_PLL_DDR_CONFIG_REG            0x04
+ #define QCA955X_PLL_CLK_CTRL_REG              0x08
++#define QCA955X_PLL_ETH_XMII_CONTROL_REG      0x28
++#define QCA955X_PLL_ETH_SGMII_CONTROL_REG     0x48
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT    0
+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK     0x3f
+@@ -378,16 +408,83 @@
+ #define AR913X_RESET_USB_HOST         BIT(5)
+ #define AR913X_RESET_USB_PHY          BIT(4)
++#define AR933X_RESET_GE1_MDIO         BIT(23)
++#define AR933X_RESET_GE0_MDIO         BIT(22)
++#define AR933X_RESET_GE1_MAC          BIT(13)
+ #define AR933X_RESET_WMAC             BIT(11)
++#define AR933X_RESET_GE0_MAC          BIT(9)
+ #define AR933X_RESET_USB_HOST         BIT(5)
+ #define AR933X_RESET_USB_PHY          BIT(4)
+ #define AR933X_RESET_USBSUS_OVERRIDE  BIT(3)
++#define AR934X_RESET_HOST             BIT(31)
++#define AR934X_RESET_SLIC             BIT(30)
++#define AR934X_RESET_HDMA             BIT(29)
++#define AR934X_RESET_EXTERNAL         BIT(28)
++#define AR934X_RESET_RTC              BIT(27)
++#define AR934X_RESET_PCIE_EP_INT      BIT(26)
++#define AR934X_RESET_CHKSUM_ACC               BIT(25)
++#define AR934X_RESET_FULL_CHIP                BIT(24)
++#define AR934X_RESET_GE1_MDIO         BIT(23)
++#define AR934X_RESET_GE0_MDIO         BIT(22)
++#define AR934X_RESET_CPU_NMI          BIT(21)
++#define AR934X_RESET_CPU_COLD         BIT(20)
++#define AR934X_RESET_HOST_RESET_INT   BIT(19)
++#define AR934X_RESET_PCIE_EP          BIT(18)
++#define AR934X_RESET_UART1            BIT(17)
++#define AR934X_RESET_DDR              BIT(16)
++#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define AR934X_RESET_NANDF            BIT(14)
++#define AR934X_RESET_GE1_MAC          BIT(13)
++#define AR934X_RESET_ETH_SWITCH_ANALOG        BIT(12)
+ #define AR934X_RESET_USB_PHY_ANALOG   BIT(11)
++#define AR934X_RESET_HOST_DMA_INT     BIT(10)
++#define AR934X_RESET_GE0_MAC          BIT(9)
++#define AR934X_RESET_ETH_SWITCH               BIT(8)
++#define AR934X_RESET_PCIE_PHY         BIT(7)
++#define AR934X_RESET_PCIE             BIT(6)
+ #define AR934X_RESET_USB_HOST         BIT(5)
+ #define AR934X_RESET_USB_PHY          BIT(4)
+ #define AR934X_RESET_USBSUS_OVERRIDE  BIT(3)
++#define AR934X_RESET_LUT              BIT(2)
++#define AR934X_RESET_MBOX             BIT(1)
++#define AR934X_RESET_I2S              BIT(0)
++
++#define QCA955X_RESET_HOST            BIT(31)
++#define QCA955X_RESET_SLIC            BIT(30)
++#define QCA955X_RESET_HDMA            BIT(29)
++#define QCA955X_RESET_EXTERNAL                BIT(28)
++#define QCA955X_RESET_RTC             BIT(27)
++#define QCA955X_RESET_PCIE_EP_INT     BIT(26)
++#define QCA955X_RESET_CHKSUM_ACC      BIT(25)
++#define QCA955X_RESET_FULL_CHIP               BIT(24)
++#define QCA955X_RESET_GE1_MDIO                BIT(23)
++#define QCA955X_RESET_GE0_MDIO                BIT(22)
++#define QCA955X_RESET_CPU_NMI         BIT(21)
++#define QCA955X_RESET_CPU_COLD                BIT(20)
++#define QCA955X_RESET_HOST_RESET_INT  BIT(19)
++#define QCA955X_RESET_PCIE_EP         BIT(18)
++#define QCA955X_RESET_UART1           BIT(17)
++#define QCA955X_RESET_DDR             BIT(16)
++#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define QCA955X_RESET_NANDF           BIT(14)
++#define QCA955X_RESET_GE1_MAC         BIT(13)
++#define QCA955X_RESET_SGMII_ANALOG    BIT(12)
++#define QCA955X_RESET_USB_PHY_ANALOG  BIT(11)
++#define QCA955X_RESET_HOST_DMA_INT    BIT(10)
++#define QCA955X_RESET_GE0_MAC         BIT(9)
++#define QCA955X_RESET_SGMII           BIT(8)
++#define QCA955X_RESET_PCIE_PHY                BIT(7)
++#define QCA955X_RESET_PCIE            BIT(6)
++#define QCA955X_RESET_USB_HOST                BIT(5)
++#define QCA955X_RESET_USB_PHY         BIT(4)
++#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
++#define QCA955X_RESET_LUT             BIT(2)
++#define QCA955X_RESET_MBOX            BIT(1)
++#define QCA955X_RESET_I2S             BIT(0)
++#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
++#define AR933X_BOOTSTRAP_EEPBUSY      BIT(4)
+ #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
+ #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)
+@@ -529,6 +626,12 @@
+ #define AR71XX_GPIO_REG_INT_ENABLE    0x24
+ #define AR71XX_GPIO_REG_FUNC          0x28
++#define AR934X_GPIO_REG_OUT_FUNC0     0x2c
++#define AR934X_GPIO_REG_OUT_FUNC1     0x30
++#define AR934X_GPIO_REG_OUT_FUNC2     0x34
++#define AR934X_GPIO_REG_OUT_FUNC3     0x38
++#define AR934X_GPIO_REG_OUT_FUNC4     0x3c
++#define AR934X_GPIO_REG_OUT_FUNC5     0x40
+ #define AR934X_GPIO_REG_FUNC          0x6c
+ #define AR71XX_GPIO_COUNT             16
+@@ -560,4 +663,133 @@
+ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT        13
+ #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
++#define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
++#define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)
++#define AR71XX_GPIO_FUNC_SPI_CS2_EN           BIT(13)
++#define AR71XX_GPIO_FUNC_SPI_CS1_EN           BIT(12)
++#define AR71XX_GPIO_FUNC_UART_EN              BIT(8)
++#define AR71XX_GPIO_FUNC_USB_OC_EN            BIT(4)
++#define AR71XX_GPIO_FUNC_USB_CLK_EN           BIT(0)
++
++#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN               BIT(19)
++#define AR724X_GPIO_FUNC_SPI_EN                       BIT(18)
++#define AR724X_GPIO_FUNC_SPI_CS_EN2           BIT(14)
++#define AR724X_GPIO_FUNC_SPI_CS_EN1           BIT(13)
++#define AR724X_GPIO_FUNC_CLK_OBS5_EN          BIT(12)
++#define AR724X_GPIO_FUNC_CLK_OBS4_EN          BIT(11)
++#define AR724X_GPIO_FUNC_CLK_OBS3_EN          BIT(10)
++#define AR724X_GPIO_FUNC_CLK_OBS2_EN          BIT(9)
++#define AR724X_GPIO_FUNC_CLK_OBS1_EN          BIT(8)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN   BIT(7)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN   BIT(6)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN   BIT(5)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN   BIT(4)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN   BIT(3)
++#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN      BIT(2)
++#define AR724X_GPIO_FUNC_UART_EN              BIT(1)
++#define AR724X_GPIO_FUNC_JTAG_DISABLE         BIT(0)
++
++#define AR913X_GPIO_FUNC_WMAC_LED_EN          BIT(22)
++#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN               BIT(21)
++#define AR913X_GPIO_FUNC_I2S_REFCLKEN         BIT(20)
++#define AR913X_GPIO_FUNC_I2S_MCKEN            BIT(19)
++#define AR913X_GPIO_FUNC_I2S1_EN              BIT(18)
++#define AR913X_GPIO_FUNC_I2S0_EN              BIT(17)
++#define AR913X_GPIO_FUNC_SLIC_EN              BIT(16)
++#define AR913X_GPIO_FUNC_UART_RTSCTS_EN               BIT(9)
++#define AR913X_GPIO_FUNC_UART_EN              BIT(8)
++#define AR913X_GPIO_FUNC_USB_CLK_EN           BIT(4)
++
++#define AR933X_GPIO_FUNC_SPDIF2TCK            BIT(31)
++#define AR933X_GPIO_FUNC_SPDIF_EN             BIT(30)
++#define AR933X_GPIO_FUNC_I2SO_22_18_EN                BIT(29)
++#define AR933X_GPIO_FUNC_I2S_MCK_EN           BIT(27)
++#define AR933X_GPIO_FUNC_I2SO_EN              BIT(26)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL  BIT(25)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL  BIT(24)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT   BIT(23)
++#define AR933X_GPIO_FUNC_SPI_EN                       BIT(18)
++#define AR933X_GPIO_FUNC_SPI_CS_EN2           BIT(14)
++#define AR933X_GPIO_FUNC_SPI_CS_EN1           BIT(13)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN   BIT(7)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN   BIT(6)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN   BIT(5)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN   BIT(4)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN   BIT(3)
++#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN      BIT(2)
++#define AR933X_GPIO_FUNC_UART_EN              BIT(1)
++#define AR933X_GPIO_FUNC_JTAG_DISABLE         BIT(0)
++
++#define AR934X_GPIO_FUNC_DDR_DQOE_EN  BIT(17)
++#define AR934X_GPIO_FUNC_SPI_CS_1_EN  BIT(14)
++#define AR934X_GPIO_FUNC_SPI_CS_0_EN  BIT(13)
++
++#define AR934X_GPIO_OUT_GPIO          0x00
++
++/*
++ * MII_CTRL block
++ */
++#define AR71XX_MII_REG_MII0_CTRL      0x00
++#define AR71XX_MII_REG_MII1_CTRL      0x04
++
++#define AR71XX_MII_CTRL_IF_MASK               3
++#define AR71XX_MII_CTRL_SPEED_SHIFT   4
++#define AR71XX_MII_CTRL_SPEED_MASK    3
++#define AR71XX_MII_CTRL_SPEED_10      0
++#define AR71XX_MII_CTRL_SPEED_100     1
++#define AR71XX_MII_CTRL_SPEED_1000    2
++
++#define AR71XX_MII0_CTRL_IF_GMII      0
++#define AR71XX_MII0_CTRL_IF_MII               1
++#define AR71XX_MII0_CTRL_IF_RGMII     2
++#define AR71XX_MII0_CTRL_IF_RMII      3
++
++#define AR71XX_MII1_CTRL_IF_RGMII     0
++#define AR71XX_MII1_CTRL_IF_RMII      1
++
++/*
++ * AR933X GMAC interface
++ */
++#define AR933X_GMAC_REG_ETH_CFG               0x00
++
++#define AR933X_ETH_CFG_RGMII_GE0      BIT(0)
++#define AR933X_ETH_CFG_MII_GE0                BIT(1)
++#define AR933X_ETH_CFG_GMII_GE0               BIT(2)
++#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
++#define AR933X_ETH_CFG_MII_GE0_SLAVE  BIT(4)
++#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
++#define AR933X_ETH_CFG_SW_PHY_SWAP    BIT(7)
++#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP       BIT(8)
++#define AR933X_ETH_CFG_RMII_GE0               BIT(9)
++#define AR933X_ETH_CFG_RMII_GE0_SPD_10        0
++#define AR933X_ETH_CFG_RMII_GE0_SPD_100       BIT(10)
++
++/*
++ * AR934X GMAC Interface
++ */
++#define AR934X_GMAC_REG_ETH_CFG               0x00
++
++#define AR934X_ETH_CFG_RGMII_GMAC0    BIT(0)
++#define AR934X_ETH_CFG_MII_GMAC0      BIT(1)
++#define AR934X_ETH_CFG_GMII_GMAC0     BIT(2)
++#define AR934X_ETH_CFG_MII_GMAC0_MASTER       BIT(3)
++#define AR934X_ETH_CFG_MII_GMAC0_SLAVE        BIT(4)
++#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN       BIT(5)
++#define AR934X_ETH_CFG_SW_ONLY_MODE   BIT(6)
++#define AR934X_ETH_CFG_SW_PHY_SWAP    BIT(7)
++#define AR934X_ETH_CFG_SW_APB_ACCESS  BIT(9)
++#define AR934X_ETH_CFG_RMII_GMAC0     BIT(10)
++#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
++#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
++#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST       BIT(13)
++
++/*
++ * QCA955X GMAC Interface
++ */
++
++#define QCA955X_GMAC_REG_ETH_CFG      0x00
++
++#define QCA955X_ETH_CFG_RGMII_EN      BIT(0)
++#define QCA955X_ETH_CFG_GE0_SGMII     BIT(6)
++
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/target/linux/ar71xx/patches-3.8/602-MIPS-ath79-add-openwrt-stuff.patch b/target/linux/ar71xx/patches-3.8/602-MIPS-ath79-add-openwrt-stuff.patch
new file mode 100644 (file)
index 0000000..da284e2
--- /dev/null
@@ -0,0 +1,76 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -106,6 +106,20 @@ config SOC_QCA955X
+       select PCI_AR724X if PCI
+       def_bool n
++config ATH79_DEV_M25P80
++      select ATH79_DEV_SPI
++      def_bool n
++
++config ATH79_DEV_AP9X_PCI
++      select ATH79_PCI_ATH9K_FIXUP
++      def_bool n
++
++config ATH79_DEV_DSA
++      def_bool n
++
++config ATH79_DEV_ETH
++      def_bool n
++
+ config PCI_AR724X
+       def_bool n
+@@ -115,6 +129,10 @@ config ATH79_DEV_GPIO_BUTTONS
+ config ATH79_DEV_LEDS_GPIO
+       def_bool n
++config ATH79_DEV_NFC
++      depends on (SOC_AR934X || SOC_QCA955X)
++      def_bool n
++
+ config ATH79_DEV_SPI
+       def_bool n
+@@ -125,4 +143,13 @@ config ATH79_DEV_WMAC
+       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
+       def_bool n
++config ATH79_NVRAM
++      def_bool n
++
++config ATH79_PCI_ATH9K_FIXUP
++      def_bool n
++
++config ATH79_ROUTERBOOT
++      def_bool n
++
+ endif
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -17,13 +17,25 @@ obj-$(CONFIG_PCI)                  += pci.o
+ # Devices
+ #
+ obj-y                                 += dev-common.o
++obj-$(CONFIG_ATH79_DEV_AP9X_PCI)      += dev-ap9x-pci.o
++obj-$(CONFIG_ATH79_DEV_DSA)           += dev-dsa.o
++obj-$(CONFIG_ATH79_DEV_ETH)           += dev-eth.o
+ obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS)  += dev-gpio-buttons.o
+ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO)     += dev-leds-gpio.o
++obj-$(CONFIG_ATH79_DEV_M25P80)                += dev-m25p80.o
++obj-$(CONFIG_ATH79_DEV_NFC)           += dev-nfc.o
+ obj-$(CONFIG_ATH79_DEV_SPI)           += dev-spi.o
+ obj-$(CONFIG_ATH79_DEV_USB)           += dev-usb.o
+ obj-$(CONFIG_ATH79_DEV_WMAC)          += dev-wmac.o
+ #
++# Miscellaneous objects
++#
++obj-$(CONFIG_ATH79_NVRAM)             += nvram.o
++obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP)   += pci-ath9k-fixup.o
++obj-$(CONFIG_ATH79_ROUTERBOOT)                += routerboot.o
++
++#
+ # Machines
+ #
+ obj-$(CONFIG_ATH79_MACH_AP121)                += mach-ap121.o
diff --git a/target/linux/ar71xx/patches-3.8/603-MIPS-ath79-ap121-fixes.patch b/target/linux/ar71xx/patches-3.8/603-MIPS-ath79-ap121-fixes.patch
new file mode 100644 (file)
index 0000000..1cacde6
--- /dev/null
@@ -0,0 +1,163 @@
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -1,19 +1,21 @@
+ /*
+  *  Atheros AP121 board support
+  *
+- *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+  *
+  *  This program is free software; you can redistribute it and/or modify it
+  *  under the terms of the GNU General Public License version 2 as published
+  *  by the Free Software Foundation.
+  */
+-#include "machtypes.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
++#include "dev-m25p80.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
++#include "machtypes.h"
+ #define AP121_GPIO_LED_WLAN           0
+ #define AP121_GPIO_LED_USB            1
+@@ -24,7 +26,14 @@
+ #define AP121_KEYS_POLL_INTERVAL      20      /* msecs */
+ #define AP121_KEYS_DEBOUNCE_INTERVAL  (3 * AP121_KEYS_POLL_INTERVAL)
+-#define AP121_CAL_DATA_ADDR   0x1fff1000
++#define AP121_MAC0_OFFSET             0x0000
++#define AP121_MAC1_OFFSET             0x0006
++#define AP121_CALDATA_OFFSET          0x1000
++#define AP121_WMAC_MAC_OFFSET         0x1002
++
++#define AP121_MINI_GPIO_LED_WLAN      0
++#define AP121_MINI_GPIO_BTN_JUMPSTART 12
++#define AP121_MINI_GPIO_BTN_RESET     11
+ static struct gpio_led ap121_leds_gpio[] __initdata = {
+       {
+@@ -58,41 +67,78 @@ static struct gpio_keys_button ap121_gpi
+       }
+ };
+-static struct ath79_spi_controller_data ap121_spi0_data = {
+-      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-      .cs_line = 0,
++static struct gpio_led ap121_mini_leds_gpio[] __initdata = {
++      {
++              .name           = "ap121:green:wlan",
++              .gpio           = AP121_MINI_GPIO_LED_WLAN,
++              .active_low     = 0,
++      },
+ };
+-static struct spi_board_info ap121_spi_info[] = {
++static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = {
+       {
+-              .bus_num        = 0,
+-              .chip_select    = 0,
+-              .max_speed_hz   = 25000000,
+-              .modalias       = "mx25l1606e",
+-              .controller_data = &ap121_spi0_data,
++              .desc           = "jumpstart button",
++              .type           = EV_KEY,
++              .code           = KEY_WPS_BUTTON,
++              .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
++              .gpio           = AP121_MINI_GPIO_BTN_JUMPSTART,
++              .active_low     = 1,
++      },
++      {
++              .desc           = "reset button",
++              .type           = EV_KEY,
++              .code           = KEY_RESTART,
++              .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
++              .gpio           = AP121_MINI_GPIO_BTN_RESET,
++              .active_low     = 1,
+       }
+ };
+-static struct ath79_spi_platform_data ap121_spi_data = {
+-      .bus_num        = 0,
+-      .num_chipselect = 1,
+-};
++static void __init ap121_common_setup(void)
++{
++      u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
++      ath79_register_m25p80(NULL);
++      ath79_register_wmac(art + AP121_CALDATA_OFFSET,
++                          art + AP121_WMAC_MAC_OFFSET);
++
++      ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0);
++      ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0);
++
++      ath79_register_mdio(0, 0x0);
++
++      /* LAN ports */
++      ath79_register_eth(1);
++
++      /* WAN port */
++      ath79_register_eth(0);
++}
+ static void __init ap121_setup(void)
+ {
+-      u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
++      ap121_common_setup();
+       ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
+                                ap121_leds_gpio);
+       ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
+                                       ARRAY_SIZE(ap121_gpio_keys),
+                                       ap121_gpio_keys);
+-
+-      ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+-                         ARRAY_SIZE(ap121_spi_info));
+       ath79_register_usb();
+-      ath79_register_wmac(cal_data, NULL);
+ }
+ MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
+            ap121_setup);
++
++static void __init ap121_mini_setup(void)
++{
++      ap121_common_setup();
++
++      ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio),
++                               ap121_mini_leds_gpio);
++      ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
++                                      ARRAY_SIZE(ap121_mini_gpio_keys),
++                                      ap121_mini_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI",
++           ap121_mini_setup);
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -5,9 +5,10 @@ menu "Atheros AR71XX/AR724X/AR913X machi
+ config ATH79_MACH_AP121
+       bool "Atheros AP121 reference board"
+       select SOC_AR933X
++      select ATH79_DEV_ETH
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+-      select ATH79_DEV_SPI
++      select ATH79_DEV_M25P80
+       select ATH79_DEV_USB
+       select ATH79_DEV_WMAC
+       help
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -17,6 +17,7 @@
+ enum ath79_mach_type {
+       ATH79_MACH_GENERIC = 0,
+       ATH79_MACH_AP121,               /* Atheros AP121 reference board */
++      ATH79_MACH_AP121_MINI,          /* Atheros AP121-MINI reference board */
+       ATH79_MACH_AP136,               /* Atheros AP136 reference board */
+       ATH79_MACH_AP81,                /* Atheros AP81 reference board */
+       ATH79_MACH_DB120,               /* Atheros DB120 reference board */
diff --git a/target/linux/ar71xx/patches-3.8/604-MIPS-ath79-ap81-fixes.patch b/target/linux/ar71xx/patches-3.8/604-MIPS-ath79-ap81-fixes.patch
new file mode 100644 (file)
index 0000000..3cc012d
--- /dev/null
@@ -0,0 +1,128 @@
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -9,12 +9,16 @@
+  *  by the Free Software Foundation.
+  */
+-#include "machtypes.h"
+-#include "dev-wmac.h"
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
+ #include "dev-usb.h"
++#include "dev-wmac.h"
++#include "machtypes.h"
+ #define AP81_GPIO_LED_STATUS  1
+ #define AP81_GPIO_LED_AOSS    3
+@@ -29,6 +33,37 @@
+ #define AP81_CAL_DATA_ADDR    0x1fff1000
++static struct mtd_partition ap81_partitions[] = {
++      {
++              .name           = "u-boot",
++              .offset         = 0,
++              .size           = 0x040000,
++              .mask_flags     = MTD_WRITEABLE,
++      }, {
++              .name           = "u-boot-env",
++              .offset         = 0x040000,
++              .size           = 0x010000,
++      }, {
++              .name           = "rootfs",
++              .offset         = 0x050000,
++              .size           = 0x500000,
++      }, {
++              .name           = "uImage",
++              .offset         = 0x550000,
++              .size           = 0x100000,
++      }, {
++              .name           = "ART",
++              .offset         = 0x650000,
++              .size           = 0x1b0000,
++              .mask_flags     = MTD_WRITEABLE,
++      }
++};
++
++static struct flash_platform_data ap81_flash_data = {
++      .parts          = ap81_partitions,
++      .nr_parts       = ARRAY_SIZE(ap81_partitions),
++};
++
+ static struct gpio_led ap81_leds_gpio[] __initdata = {
+       {
+               .name           = "ap81:green:status",
+@@ -67,26 +102,6 @@ static struct gpio_keys_button ap81_gpio
+       }
+ };
+-static struct ath79_spi_controller_data ap81_spi0_data = {
+-      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-      .cs_line = 0,
+-};
+-
+-static struct spi_board_info ap81_spi_info[] = {
+-      {
+-              .bus_num        = 0,
+-              .chip_select    = 0,
+-              .max_speed_hz   = 25000000,
+-              .modalias       = "m25p64",
+-              .controller_data = &ap81_spi0_data,
+-      }
+-};
+-
+-static struct ath79_spi_platform_data ap81_spi_data = {
+-      .bus_num        = 0,
+-      .num_chipselect = 1,
+-};
+-
+ static void __init ap81_setup(void)
+ {
+       u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR);
+@@ -96,10 +111,24 @@ static void __init ap81_setup(void)
+       ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
+                                       ARRAY_SIZE(ap81_gpio_keys),
+                                       ap81_gpio_keys);
+-      ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+-                         ARRAY_SIZE(ap81_spi_info));
++      ath79_register_m25p80(&ap81_flash_data);
+       ath79_register_wmac(cal_data, NULL);
+       ath79_register_usb();
++
++      ath79_register_mdio(0, 0x0);
++
++      ath79_init_mac(ath79_eth0_data.mac_addr, cal_data, 0);
++      ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
++      ath79_eth0_data.speed = SPEED_100;
++      ath79_eth0_data.duplex = DUPLEX_FULL;
++      ath79_eth0_data.has_ar8216 = 1;
++
++      ath79_init_mac(ath79_eth1_data.mac_addr, cal_data, 1);
++      ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
++      ath79_eth1_data.phy_mask = 0x10;
++
++      ath79_register_eth(0);
++      ath79_register_eth(1);
+ }
+ MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -30,9 +30,10 @@ config ATH79_MACH_AP136
+ config ATH79_MACH_AP81
+       bool "Atheros AP81 reference board"
+       select SOC_AR913X
++      select ATH79_DEV_ETH
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+-      select ATH79_DEV_SPI
++      select ATH79_DEV_M25P80
+       select ATH79_DEV_USB
+       select ATH79_DEV_WMAC
+       help
diff --git a/target/linux/ar71xx/patches-3.8/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-3.8/605-MIPS-ath79-db120-fixes.patch
new file mode 100644 (file)
index 0000000..0ca7861
--- /dev/null
@@ -0,0 +1,209 @@
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -2,7 +2,7 @@
+  * Atheros DB120 reference board support
+  *
+  * Copyright (c) 2011 Qualcomm Atheros
+- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+  *
+  * Permission to use, copy, modify, and/or distribute this software for any
+  * purpose with or without fee is hereby granted, provided that the above
+@@ -19,16 +19,26 @@
+  */
+ #include <linux/pci.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
++#include <linux/ar8216_platform.h>
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#include "common.h"
++#include "dev-ap9x-pci.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
++#include "dev-m25p80.h"
++#include "dev-nfc.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
+-#include "pci.h"
++#include "machtypes.h"
++#define DB120_GPIO_LED_USB            11
+ #define DB120_GPIO_LED_WLAN_5G                12
+ #define DB120_GPIO_LED_WLAN_2G                13
+ #define DB120_GPIO_LED_STATUS         14
+@@ -39,8 +49,10 @@
+ #define DB120_KEYS_POLL_INTERVAL      20      /* msecs */
+ #define DB120_KEYS_DEBOUNCE_INTERVAL  (3 * DB120_KEYS_POLL_INTERVAL)
+-#define DB120_WMAC_CALDATA_OFFSET 0x1000
+-#define DB120_PCIE_CALDATA_OFFSET 0x5000
++#define DB120_MAC0_OFFSET             0
++#define DB120_MAC1_OFFSET             6
++#define DB120_WMAC_CALDATA_OFFSET     0x1000
++#define DB120_PCIE_CALDATA_OFFSET     0x5000
+ static struct gpio_led db120_leds_gpio[] __initdata = {
+       {
+@@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[]
+               .gpio           = DB120_GPIO_LED_WLAN_2G,
+               .active_low     = 1,
+       },
++      {
++              .name           = "db120:green:usb",
++              .gpio           = DB120_GPIO_LED_USB,
++              .active_low     = 1,
++      }
+ };
+ static struct gpio_keys_button db120_gpio_keys[] __initdata = {
+@@ -76,66 +93,85 @@ static struct gpio_keys_button db120_gpi
+       },
+ };
+-static struct ath79_spi_controller_data db120_spi0_data = {
+-      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-      .cs_line = 0,
++static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
++      .mode = AR8327_PAD_MAC_RGMII,
++      .txclk_delay_en = true,
++      .rxclk_delay_en = true,
++      .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
++      .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
+ };
+-static struct spi_board_info db120_spi_info[] = {
+-      {
+-              .bus_num        = 0,
+-              .chip_select    = 0,
+-              .max_speed_hz   = 25000000,
+-              .modalias       = "s25sl064a",
+-              .controller_data = &db120_spi0_data,
+-      }
++static struct ar8327_led_cfg db120_ar8327_led_cfg = {
++      .led_ctrl0 = 0x00000000,
++      .led_ctrl1 = 0xc737c737,
++      .led_ctrl2 = 0x00000000,
++      .led_ctrl3 = 0x00c30c00,
++      .open_drain = true,
+ };
+-static struct ath79_spi_platform_data db120_spi_data = {
+-      .bus_num        = 0,
+-      .num_chipselect = 1,
++static struct ar8327_platform_data db120_ar8327_data = {
++      .pad0_cfg = &db120_ar8327_pad0_cfg,
++      .port0_cfg = {
++              .force_link = 1,
++              .speed = AR8327_PORT_SPEED_1000,
++              .duplex = 1,
++              .txpause = 1,
++              .rxpause = 1,
++      },
++      .led_cfg = &db120_ar8327_led_cfg,
+ };
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data db120_ath9k_data;
+-
+-static int db120_pci_plat_dev_init(struct pci_dev *dev)
+-{
+-      switch (PCI_SLOT(dev->devfn)) {
+-      case 0:
+-              dev->dev.platform_data = &db120_ath9k_data;
+-              break;
+-      }
+-
+-      return 0;
+-}
+-
+-static void __init db120_pci_init(u8 *eeprom)
+-{
+-      memcpy(db120_ath9k_data.eeprom_data, eeprom,
+-             sizeof(db120_ath9k_data.eeprom_data));
+-
+-      ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
+-      ath79_register_pci();
+-}
+-#else
+-static inline void db120_pci_init(void) {}
+-#endif /* CONFIG_PCI */
++static struct mdio_board_info db120_mdio0_info[] = {
++      {
++              .bus_id = "ag71xx-mdio.0",
++              .phy_addr = 0,
++              .platform_data = &db120_ar8327_data,
++      },
++};
+ static void __init db120_setup(void)
+ {
+       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++      ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
++      ath79_register_m25p80(NULL);
++
+       ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
+                                db120_leds_gpio);
+       ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
+                                       ARRAY_SIZE(db120_gpio_keys),
+                                       db120_gpio_keys);
+-      ath79_register_spi(&db120_spi_data, db120_spi_info,
+-                         ARRAY_SIZE(db120_spi_info));
+       ath79_register_usb();
+       ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+-      db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
++      ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
++
++      ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
++                                 AR934X_ETH_CFG_SW_ONLY_MODE);
++
++      ath79_register_mdio(1, 0x0);
++      ath79_register_mdio(0, 0x0);
++
++      ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
++
++      mdiobus_register_board_info(db120_mdio0_info,
++                                  ARRAY_SIZE(db120_mdio0_info));
++
++      /* GMAC0 is connected to an AR8327 switch */
++      ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++      ath79_eth0_data.phy_mask = BIT(0);
++      ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++      ath79_eth0_pll_data.pll_1000 = 0x06000000;
++      ath79_register_eth(0);
++
++      /* GMAC1 is connected to the internal switch */
++      ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
++      ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
++      ath79_eth1_data.speed = SPEED_1000;
++      ath79_eth1_data.duplex = DUPLEX_FULL;
++
++      ath79_register_eth(1);
++
++      ath79_register_nfc();
+ }
+ MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -43,9 +43,12 @@ config ATH79_MACH_AP81
+ config ATH79_MACH_DB120
+       bool "Atheros DB120 reference board"
+       select SOC_AR934X
++      select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+-      select ATH79_DEV_SPI
++      select ATH79_DEV_M25P80
++      select ATH79_DEV_NFC
+       select ATH79_DEV_USB
+       select ATH79_DEV_WMAC
+       help
diff --git a/target/linux/ar71xx/patches-3.8/606-MIPS-ath79-pb44-fixes.patch b/target/linux/ar71xx/patches-3.8/606-MIPS-ath79-pb44-fixes.patch
new file mode 100644 (file)
index 0000000..f9ec775
--- /dev/null
@@ -0,0 +1,153 @@
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -8,23 +8,48 @@
+  *  by the Free Software Foundation.
+  */
++#include <linux/delay.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c.h>
+ #include <linux/i2c-gpio.h>
+ #include <linux/i2c/pcf857x.h>
++#include <linux/i2c/pcf857x.h>
++#include <linux/spi/flash.h>
++#include <linux/spi/vsc7385.h>
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++#include <asm/mach-ath79/ath79.h>
++
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
++#include "machtypes.h"
+ #include "pci.h"
+ #define PB44_GPIO_I2C_SCL     0
+ #define PB44_GPIO_I2C_SDA     1
++#define PB44_PCF8757_VSC7395_CS       0
++#define PB44_PCF8757_STEREO_CS        1
++#define PB44_PCF8757_SLIC_CS0 2
++#define PB44_PCF8757_SLIC_TEST        3
++#define PB44_PCF8757_SLIC_INT0        4
++#define PB44_PCF8757_SLIC_INT1        5
++#define PB44_PCF8757_SW_RESET 6
++#define PB44_PCF8757_SW_JUMP  8
++#define PB44_PCF8757_LED_JUMP1        9
++#define PB44_PCF8757_LED_JUMP2        10
++#define PB44_PCF8757_TP24     11
++#define PB44_PCF8757_TP25     12
++#define PB44_PCF8757_TP26     13
++#define PB44_PCF8757_TP27     14
++#define PB44_PCF8757_TP28     15
++
+ #define PB44_GPIO_EXP_BASE    16
++#define PB44_GPIO_VSC7395_CS  (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
+ #define PB44_GPIO_SW_RESET    (PB44_GPIO_EXP_BASE + 6)
+ #define PB44_GPIO_SW_JUMP     (PB44_GPIO_EXP_BASE + 8)
+ #define PB44_GPIO_LED_JUMP1   (PB44_GPIO_EXP_BASE + 9)
+@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data
+       .cs_line = 0,
+ };
++static struct ath79_spi_controller_data pb44_spi1_data = {
++      .cs_type = ATH79_SPI_CS_TYPE_GPIO,
++      .cs_line = PB44_GPIO_VSC7395_CS,
++};
++
++static void pb44_vsc7395_reset(void)
++{
++      ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
++      udelay(10);
++      ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
++      mdelay(50);
++}
++
++static struct vsc7385_platform_data pb44_vsc7395_data = {
++      .reset          = pb44_vsc7395_reset,
++      .ucode_name     = "vsc7395_ucode_pb44.bin",
++      .mac_cfg = {
++              .tx_ipg         = 6,
++              .bit2           = 1,
++              .clk_sel        = 0,
++      },
++};
++
++static const char *pb44_part_probes[] = {
++      "RedBoot",
++      NULL,
++};
++
++static struct flash_platform_data pb44_flash_data = {
++      .part_probes    = pb44_part_probes,
++};
++
+ static struct spi_board_info pb44_spi_info[] = {
+       {
+               .bus_num        = 0,
+               .chip_select    = 0,
+               .max_speed_hz   = 25000000,
+               .modalias       = "m25p64",
++              .platform_data  = &pb44_flash_data,
+               .controller_data = &pb44_spi0_data,
+       },
++      {
++              .bus_num        = 0,
++              .chip_select    = 1,
++              .max_speed_hz   = 25000000,
++              .modalias       = "spi-vsc7385",
++              .platform_data  = &pb44_vsc7395_data,
++              .controller_data = &pb44_spi1_data,
++      }
+ };
+ static struct ath79_spi_platform_data pb44_spi_data = {
+       .bus_num                = 0,
+-      .num_chipselect         = 1,
++      .num_chipselect         = 2,
+ };
++#define PB44_WAN_PHYMASK      BIT(0)
++#define PB44_LAN_PHYMASK      0
++#define PB44_MDIO_PHYMASK     (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
++
+ static void __init pb44_init(void)
+ {
+       i2c_register_board_info(0, pb44_i2c_board_info,
+@@ -122,6 +192,22 @@ static void __init pb44_init(void)
+                          ARRAY_SIZE(pb44_spi_info));
+       ath79_register_usb();
+       ath79_register_pci();
++
++      ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
++
++      ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
++      ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++      ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
++
++      ath79_register_eth(0);
++
++      ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
++      ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++      ath79_eth1_data.speed = SPEED_1000;
++      ath79_eth1_data.duplex = DUPLEX_FULL;
++      ath79_eth1_pll_data.pll_1000 = 0x110000;
++
++      ath79_register_eth(1);
+ }
+ MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -58,6 +58,7 @@ config ATH79_MACH_DB120
+ config ATH79_MACH_PB44
+       bool "Atheros PB44 reference board"
+       select SOC_AR71XX
++      select ATH79_DEV_ETH
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+       select ATH79_DEV_SPI
diff --git a/target/linux/ar71xx/patches-3.8/607-MIPS-ath79-ubnt-xm-fixes.patch b/target/linux/ar71xx/patches-3.8/607-MIPS-ath79-ubnt-xm-fixes.patch
new file mode 100644 (file)
index 0000000..cbbe20b
--- /dev/null
@@ -0,0 +1,109 @@
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -70,9 +70,10 @@ config ATH79_MACH_PB44
+ config ATH79_MACH_UBNT_XM
+       bool "Ubiquiti Networks XM (rev 1.0) board"
+       select SOC_AR724X
++      select ATH79_DEV_AP9X_PCI if PCI
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+-      select ATH79_DEV_SPI
++      select ATH79_DEV_M25P80
+       help
+         Say 'Y' here if you want your kernel to support the
+         Ubiquiti Networks XM (rev 1.0) board.
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -16,10 +16,11 @@
+ #include <asm/mach-ath79/irq.h>
+-#include "machtypes.h"
++#include "dev-ap9x-pci.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
++#include "machtypes.h"
+ #include "pci.h"
+ #define UBNT_XM_GPIO_LED_L1           0
+@@ -32,7 +33,7 @@
+ #define UBNT_XM_KEYS_POLL_INTERVAL    20
+ #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL        (3 * UBNT_XM_KEYS_POLL_INTERVAL)
+-#define UBNT_XM_EEPROM_ADDR           (u8 *) KSEG1ADDR(0x1fff1000)
++#define UBNT_XM_EEPROM_ADDR           0x1fff1000
+ static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+       {
+@@ -65,54 +66,10 @@ static struct gpio_keys_button ubnt_xm_g
+       }
+ };
+-static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
+-      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-      .cs_line = 0,
+-};
+-
+-static struct spi_board_info ubnt_xm_spi_info[] = {
+-      {
+-              .bus_num        = 0,
+-              .chip_select    = 0,
+-              .max_speed_hz   = 25000000,
+-              .modalias       = "mx25l6405d",
+-              .controller_data = &ubnt_xm_spi0_data,
+-      }
+-};
+-
+-static struct ath79_spi_platform_data ubnt_xm_spi_data = {
+-      .bus_num                = 0,
+-      .num_chipselect         = 1,
+-};
+-
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ubnt_xm_eeprom_data;
+-
+-static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
+-{
+-      switch (PCI_SLOT(dev->devfn)) {
+-      case 0:
+-              dev->dev.platform_data = &ubnt_xm_eeprom_data;
+-              break;
+-      }
+-
+-      return 0;
+-}
+-
+-static void __init ubnt_xm_pci_init(void)
+-{
+-      memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+-             sizeof(ubnt_xm_eeprom_data.eeprom_data));
+-
+-      ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
+-      ath79_register_pci();
+-}
+-#else
+-static inline void ubnt_xm_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+-
+ static void __init ubnt_xm_init(void)
+ {
++      u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
++
+       ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+                                ubnt_xm_leds_gpio);
+@@ -120,10 +77,8 @@ static void __init ubnt_xm_init(void)
+                                       ARRAY_SIZE(ubnt_xm_gpio_keys),
+                                       ubnt_xm_gpio_keys);
+-      ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
+-                         ARRAY_SIZE(ubnt_xm_spi_info));
+-
+-      ubnt_xm_pci_init();
++      ath79_register_m25p80(NULL);
++      ap91_pci_init(eeprom, NULL);
+ }
+ MIPS_MACHINE(ATH79_MACH_UBNT_XM,
diff --git a/target/linux/ar71xx/patches-3.8/608-MIPS-ath79-ubnt-xm-add-more-boards.patch b/target/linux/ar71xx/patches-3.8/608-MIPS-ath79-ubnt-xm-add-more-boards.patch
new file mode 100644 (file)
index 0000000..2e8fbdc
--- /dev/null
@@ -0,0 +1,343 @@
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -12,16 +12,22 @@
+ #include <linux/init.h>
+ #include <linux/pci.h>
++#include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
++#include <linux/etherdevice.h>
++#include <linux/ar8216_platform.h>
+ #include <asm/mach-ath79/irq.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
+ #include "dev-ap9x-pci.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-m25p80.h"
++#include "dev-usb.h"
++#include "dev-wmac.h"
+ #include "machtypes.h"
+-#include "pci.h"
+ #define UBNT_XM_GPIO_LED_L1           0
+ #define UBNT_XM_GPIO_LED_L2           1
+@@ -37,19 +43,19 @@
+ static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+       {
+-              .name           = "ubnt-xm:red:link1",
++              .name           = "ubnt:red:link1",
+               .gpio           = UBNT_XM_GPIO_LED_L1,
+               .active_low     = 0,
+       }, {
+-              .name           = "ubnt-xm:orange:link2",
++              .name           = "ubnt:orange:link2",
+               .gpio           = UBNT_XM_GPIO_LED_L2,
+               .active_low     = 0,
+       }, {
+-              .name           = "ubnt-xm:green:link3",
++              .name           = "ubnt:green:link3",
+               .gpio           = UBNT_XM_GPIO_LED_L3,
+               .active_low     = 0,
+       }, {
+-              .name           = "ubnt-xm:green:link4",
++              .name           = "ubnt:green:link4",
+               .gpio           = UBNT_XM_GPIO_LED_L4,
+               .active_low     = 0,
+       },
+@@ -66,9 +72,13 @@ static struct gpio_keys_button ubnt_xm_g
+       }
+ };
++#define UBNT_M_WAN_PHYMASK    BIT(4)
++
+ static void __init ubnt_xm_init(void)
+ {
+       u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
++      u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++      u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
+       ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+                                ubnt_xm_leds_gpio);
+@@ -79,9 +89,242 @@ static void __init ubnt_xm_init(void)
+       ath79_register_m25p80(NULL);
+       ap91_pci_init(eeprom, NULL);
++
++      ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++      ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++      ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
++      ath79_register_eth(0);
+ }
+ MIPS_MACHINE(ATH79_MACH_UBNT_XM,
+            "UBNT-XM",
+            "Ubiquiti Networks XM (rev 1.0) board",
+            ubnt_xm_init);
++
++MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M",
++           ubnt_xm_init);
++
++static void __init ubnt_rocket_m_setup(void)
++{
++      ubnt_xm_init();
++      ath79_register_usb();
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M",
++           ubnt_rocket_m_setup);
++
++static void __init ubnt_nano_m_setup(void)
++{
++      ubnt_xm_init();
++      ath79_register_eth(1);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M",
++           ubnt_nano_m_setup);
++
++static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = {
++      {
++              .name           = "ubnt:green:globe",
++              .gpio           = 0,
++              .active_low     = 1,
++      }, {
++              .name           = "ubnt:green:power",
++              .gpio           = 11,
++              .active_low     = 1,
++              .default_state  = LEDS_GPIO_DEFSTATE_ON,
++      }
++};
++
++static void __init ubnt_airrouter_setup(void)
++{
++      u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++      u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++      ath79_register_m25p80(NULL);
++      ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++
++      ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++      ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1);
++
++      ath79_register_eth(1);
++      ath79_register_eth(0);
++      ath79_register_usb();
++
++      ap91_pci_init(ee, NULL);
++      ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio),
++                               ubnt_airrouter_leds_gpio);
++
++      ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(ubnt_xm_gpio_keys),
++                                        ubnt_xm_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter",
++           ubnt_airrouter_setup);
++
++static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = {
++      {
++              .name           = "ubnt:orange:dome",
++              .gpio           = 1,
++              .active_low     = 0,
++      }, {
++              .name           = "ubnt:green:dome",
++              .gpio           = 0,
++              .active_low     = 0,
++      }
++};
++
++static struct gpio_led ubnt_unifi_outdoor_leds_gpio[] __initdata = {
++      {
++              .name           = "ubnt:orange:front",
++              .gpio           = 1,
++              .active_low     = 0,
++      }, {
++              .name           = "ubnt:green:front",
++              .gpio           = 0,
++              .active_low     = 0,
++      }
++};
++
++static void __init ubnt_unifi_setup(void)
++{
++      u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
++      u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++      ath79_register_m25p80(NULL);
++
++      ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++
++      ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
++      ath79_register_eth(0);
++
++      ap91_pci_init(ee, NULL);
++
++      ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio),
++                               ubnt_unifi_leds_gpio);
++
++      ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(ubnt_xm_gpio_keys),
++                                        ubnt_xm_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi",
++           ubnt_unifi_setup);
++
++
++#define UBNT_UNIFIOD_PRI_PHYMASK      BIT(4)
++#define UBNT_UNIFIOD_2ND_PHYMASK      (BIT(0) | BIT(1) | BIT(2) | BIT(3))
++
++static void __init ubnt_unifi_outdoor_setup(void)
++{
++      u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++      u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
++      u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++      ath79_register_m25p80(NULL);
++
++      ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK |
++                               UBNT_UNIFIOD_2ND_PHYMASK));
++
++      ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++      ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
++      ath79_register_eth(0);
++      ath79_register_eth(1);
++
++      ap91_pci_init(ee, NULL);
++
++      ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_leds_gpio),
++                               ubnt_unifi_outdoor_leds_gpio);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR, "UBNT-U20",
++           "Ubiquiti UniFiAP Outdoor",
++           ubnt_unifi_outdoor_setup);
++
++static struct gpio_led ubnt_uap_pro_gpio_leds[] __initdata = {
++      {
++              .name           = "ubnt:white:dome",
++              .gpio           = 12,
++      }, {
++              .name           = "ubnt:blue:dome",
++              .gpio           = 13,
++      }
++};
++
++static struct gpio_keys_button uap_pro_gpio_keys[] __initdata = {
++      {
++              .desc                   = "reset",
++              .type                   = EV_KEY,
++              .code                   = KEY_RESTART,
++              .debounce_interval      = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
++              .gpio                   = 17,
++              .active_low             = 1,
++      }
++};
++
++static struct ar8327_pad_cfg uap_pro_ar8327_pad0_cfg = {
++      .mode = AR8327_PAD_MAC_RGMII,
++      .txclk_delay_en = true,
++      .rxclk_delay_en = true,
++      .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
++      .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
++};
++
++static struct ar8327_platform_data uap_pro_ar8327_data = {
++      .pad0_cfg = &uap_pro_ar8327_pad0_cfg,
++      .port0_cfg = {
++              .force_link = 1,
++              .speed = AR8327_PORT_SPEED_1000,
++              .duplex = 1,
++              .txpause = 1,
++              .rxpause = 1,
++      },
++};
++
++static struct mdio_board_info uap_pro_mdio0_info[] = {
++      {
++              .bus_id = "ag71xx-mdio.0",
++              .phy_addr = 0,
++              .platform_data = &uap_pro_ar8327_data,
++      },
++};
++
++#define UAP_PRO_MAC0_OFFSET           0x0000
++#define UAP_PRO_MAC1_OFFSET           0x0006
++#define UAP_PRO_WMAC_CALDATA_OFFSET   0x1000
++#define UAP_PRO_PCI_CALDATA_OFFSET    0x5000
++
++static void __init ubnt_uap_pro_setup(void)
++{
++      u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
++
++      ath79_register_m25p80(NULL);
++
++      ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_uap_pro_gpio_leds),
++                               ubnt_uap_pro_gpio_leds);
++      ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++                                        ARRAY_SIZE(uap_pro_gpio_keys),
++                                        uap_pro_gpio_keys);
++
++      ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL);
++      ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL);
++
++      ath79_register_mdio(0, 0x0);
++      mdiobus_register_board_info(uap_pro_mdio0_info,
++                                  ARRAY_SIZE(uap_pro_mdio0_info));
++
++      ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
++      ath79_init_mac(ath79_eth0_data.mac_addr,
++                     eeprom + UAP_PRO_MAC0_OFFSET, 0);
++
++      /* GMAC0 is connected to an AR8327 switch */
++      ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++      ath79_eth0_data.phy_mask = BIT(0);
++      ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++      ath79_eth0_pll_data.pll_1000 = 0x06000000;
++      ath79_register_eth(0);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_UAP_PRO, "UAP-PRO", "Ubiquiti UniFi AP Pro",
++           ubnt_uap_pro_setup);
++
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -68,12 +68,16 @@ config ATH79_MACH_PB44
+         Atheros PB44 reference board.
+ config ATH79_MACH_UBNT_XM
+-      bool "Ubiquiti Networks XM (rev 1.0) board"
++      bool "Ubiquiti Networks XM/UniFi boards"
+       select SOC_AR724X
++      select SOC_AR934X
+       select ATH79_DEV_AP9X_PCI if PCI
++      select ATH79_DEV_ETH
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+       select ATH79_DEV_M25P80
++      select ATH79_DEV_USB
++      select ATH79_DEV_WMAC
+       help
+         Say 'Y' here if you want your kernel to support the
+         Ubiquiti Networks XM (rev 1.0) board.
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -22,6 +22,13 @@ enum ath79_mach_type {
+       ATH79_MACH_AP81,                /* Atheros AP81 reference board */
+       ATH79_MACH_DB120,               /* Atheros DB120 reference board */
+       ATH79_MACH_PB44,                /* Atheros PB44 reference board */
++      ATH79_MACH_UBNT_AIRROUTER,      /* Ubiquiti AirRouter */
++      ATH79_MACH_UBNT_BULLET_M,       /* Ubiquiti Bullet M */
++      ATH79_MACH_UBNT_NANO_M,         /* Ubiquiti NanoStation M */
++      ATH79_MACH_UBNT_ROCKET_M,       /* Ubiquiti Rocket M */
++      ATH79_MACH_UBNT_UAP_PRO,        /* Ubiquiti UniFi AP Pro */
++      ATH79_MACH_UBNT_UNIFI,          /* Ubiquiti Unifi */
++      ATH79_MACH_UBNT_UNIFI_OUTDOOR,  /* Ubiquiti UnifiAP Outdoor */
+       ATH79_MACH_UBNT_XM,             /* Ubiquiti Networks XM board rev 1.0 */
+ };
diff --git a/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-3.8/609-MIPS-ath79-ap136-fixes.patch
new file mode 100644 (file)
index 0000000..6358e47
--- /dev/null
@@ -0,0 +1,291 @@
+--- a/arch/mips/ath79/mach-ap136.c
++++ b/arch/mips/ath79/mach-ap136.c
+@@ -1,5 +1,5 @@
+ /*
+- * Qualcomm Atheros AP136 reference board support
++ * Atheros AP136 reference board support
+  *
+  * Copyright (c) 2012 Qualcomm Atheros
+  * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
+@@ -18,23 +18,28 @@
+  *
+  */
+-#include <linux/pci.h>
+-#include <linux/ath9k_platform.h>
++#include <linux/platform_device.h>
++#include <linux/ar8216_platform.h>
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#include "common.h"
++#include "dev-ap9x-pci.h"
+ #include "dev-gpio-buttons.h"
++#include "dev-eth.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
++#include "dev-nfc.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
+-#include "pci.h"
++#include "machtypes.h"
+-#define AP136_GPIO_LED_STATUS_RED     14
+-#define AP136_GPIO_LED_STATUS_GREEN   19
+ #define AP136_GPIO_LED_USB            4
+-#define AP136_GPIO_LED_WLAN_2G                13
+ #define AP136_GPIO_LED_WLAN_5G                12
++#define AP136_GPIO_LED_WLAN_2G                13
++#define AP136_GPIO_LED_STATUS_RED     14
+ #define AP136_GPIO_LED_WPS_RED                15
++#define AP136_GPIO_LED_STATUS_GREEN   19
+ #define AP136_GPIO_LED_WPS_GREEN      20
+ #define AP136_GPIO_BTN_WPS            16
+@@ -43,8 +48,10 @@
+ #define AP136_KEYS_POLL_INTERVAL      20      /* msecs */
+ #define AP136_KEYS_DEBOUNCE_INTERVAL  (3 * AP136_KEYS_POLL_INTERVAL)
+-#define AP136_WMAC_CALDATA_OFFSET 0x1000
+-#define AP136_PCIE_CALDATA_OFFSET 0x5000
++#define AP136_MAC0_OFFSET             0
++#define AP136_MAC1_OFFSET             6
++#define AP136_WMAC_CALDATA_OFFSET     0x1000
++#define AP136_PCIE_CALDATA_OFFSET     0x5000
+ static struct gpio_led ap136_leds_gpio[] __initdata = {
+       {
+@@ -98,64 +105,158 @@ static struct gpio_keys_button ap136_gpi
+       },
+ };
+-static struct ath79_spi_controller_data ap136_spi0_data = {
+-      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+-      .cs_line = 0,
++static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
++static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
++
++static struct ar8327_platform_data ap136_ar8327_data = {
++      .pad0_cfg = &ap136_ar8327_pad0_cfg,
++      .pad6_cfg = &ap136_ar8327_pad6_cfg,
++      .port0_cfg = {
++              .force_link = 1,
++              .speed = AR8327_PORT_SPEED_1000,
++              .duplex = 1,
++              .txpause = 1,
++              .rxpause = 1,
++      },
++      .port6_cfg = {
++              .force_link = 1,
++              .speed = AR8327_PORT_SPEED_1000,
++              .duplex = 1,
++              .txpause = 1,
++              .rxpause = 1,
++      },
+ };
+-static struct spi_board_info ap136_spi_info[] = {
++static struct mdio_board_info ap136_mdio0_info[] = {
+       {
+-              .bus_num        = 0,
+-              .chip_select    = 0,
+-              .max_speed_hz   = 25000000,
+-              .modalias       = "mx25l6405d",
+-              .controller_data = &ap136_spi0_data,
+-      }
++              .bus_id = "ag71xx-mdio.0",
++              .phy_addr = 0,
++              .platform_data = &ap136_ar8327_data,
++      },
+ };
+-static struct ath79_spi_platform_data ap136_spi_data = {
+-      .bus_num        = 0,
+-      .num_chipselect = 1,
+-};
++static void __init ap136_gmac_setup(void)
++{
++      void __iomem *base;
++      u32 t;
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ap136_ath9k_data;
++      base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+-{
+-      if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
+-              dev->dev.platform_data = &ap136_ath9k_data;
++      t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
+-      return 0;
+-}
++      t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
++      t |= QCA955X_ETH_CFG_RGMII_EN;
+-static void __init ap136_pci_init(u8 *eeprom)
+-{
+-      memcpy(ap136_ath9k_data.eeprom_data, eeprom,
+-             sizeof(ap136_ath9k_data.eeprom_data));
++      __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
+-      ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
+-      ath79_register_pci();
++      iounmap(base);
+ }
+-#else
+-static inline void ap136_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+-static void __init ap136_setup(void)
++static void __init ap136_common_setup(void)
+ {
+       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++      ath79_register_m25p80(NULL);
++
+       ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
+                                ap136_leds_gpio);
+       ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
+                                       ARRAY_SIZE(ap136_gpio_keys),
+                                       ap136_gpio_keys);
+-      ath79_register_spi(&ap136_spi_data, ap136_spi_info,
+-                         ARRAY_SIZE(ap136_spi_info));
++
+       ath79_register_usb();
+-      ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
+-      ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
++      ath79_register_nfc();
++
++      ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
++      ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
++
++      ap136_gmac_setup();
++
++      ath79_register_mdio(0, 0x0);
++
++      ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
++
++      mdiobus_register_board_info(ap136_mdio0_info,
++                                  ARRAY_SIZE(ap136_mdio0_info));
++
++      /* GMAC0 is connected to the RMGII interface */
++      ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++      ath79_eth0_data.phy_mask = BIT(0);
++      ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++
++      ath79_register_eth(0);
++
++      /* GMAC1 is connected tot eh SGMII interface */
++      ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
++      ath79_eth1_data.speed = SPEED_1000;
++      ath79_eth1_data.duplex = DUPLEX_FULL;
++
++      ath79_register_eth(1);
++}
++
++static void __init ap136_010_setup(void)
++{
++      /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
++      ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
++      ap136_ar8327_pad0_cfg.txclk_delay_en = true;
++      ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
++      ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
++      ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
++
++      /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
++      ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
++      ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
++      ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
++
++      ath79_eth0_pll_data.pll_1000 = 0xa6000000;
++      ath79_eth1_pll_data.pll_1000 = 0x03000101;
++
++      ap136_common_setup();
++}
++
++MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
++           "Atheros AP136-010 reference board",
++           ap136_010_setup);
++
++static void __init ap136_020_setup(void)
++{
++      /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
++      ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
++      ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
++
++      /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
++      ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
++      ap136_ar8327_pad6_cfg.txclk_delay_en = true;
++      ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
++      ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
++      ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
++
++      ath79_eth0_pll_data.pll_1000 = 0x56000000;
++      ath79_eth1_pll_data.pll_1000 = 0x03000101;
++
++      ap136_common_setup();
++}
++
++MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
++           "Atheros AP136-020 reference board",
++           ap136_020_setup);
++
++/*
++ * AP135-020 is similar to AP136-020, any future AP135 specific init
++ * code can be added here.
++ */
++static void __init ap135_020_setup(void)
++{
++      ap136_leds_gpio[0].name = "ap135:green:status";
++      ap136_leds_gpio[1].name = "ap135:red:status";
++      ap136_leds_gpio[2].name = "ap135:green:wps";
++      ap136_leds_gpio[3].name = "ap135:red:wps";
++      ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
++      ap136_leds_gpio[5].name = "ap135:red:usb";
++
++      ap136_020_setup();
+ }
+-MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",
+-           ap136_setup);
++MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
++           "Atheros AP135-020 reference board",
++           ap135_020_setup);
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -18,7 +18,9 @@ enum ath79_mach_type {
+       ATH79_MACH_GENERIC = 0,
+       ATH79_MACH_AP121,               /* Atheros AP121 reference board */
+       ATH79_MACH_AP121_MINI,          /* Atheros AP121-MINI reference board */
+-      ATH79_MACH_AP136,               /* Atheros AP136 reference board */
++      ATH79_MACH_AP135_020,           /* Atheros AP135-020 reference board */
++      ATH79_MACH_AP136_010,           /* Atheros AP136-010 reference board */
++      ATH79_MACH_AP136_020,           /* Atheros AP136-020 reference board */
+       ATH79_MACH_AP81,                /* Atheros AP81 reference board */
+       ATH79_MACH_DB120,               /* Atheros DB120 reference board */
+       ATH79_MACH_PB44,                /* Atheros PB44 reference board */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -16,16 +16,17 @@ config ATH79_MACH_AP121
+         Atheros AP121 reference board.
+ config ATH79_MACH_AP136
+-      bool "Atheros AP136 reference board"
++      bool "Atheros AP136/AP135 reference board"
+       select SOC_QCA955X
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
++      select ATH79_DEV_NFC
+       select ATH79_DEV_SPI
+       select ATH79_DEV_USB
+       select ATH79_DEV_WMAC
+       help
+         Say 'Y' here if you want your kernel to support the
+-        Atheros AP136 reference board.
++        Atheros AP136 or AP135 reference boards.
+ config ATH79_MACH_AP81
+       bool "Atheros AP81 reference board"
diff --git a/target/linux/ar71xx/patches-3.8/610-MIPS-ath79-openwrt-machines.patch b/target/linux/ar71xx/patches-3.8/610-MIPS-ath79-openwrt-machines.patch
new file mode 100644 (file)
index 0000000..73253bb
--- /dev/null
@@ -0,0 +1,854 @@
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -16,22 +16,112 @@
+ enum ath79_mach_type {
+       ATH79_MACH_GENERIC = 0,
++      ATH79_MACH_ALFA_AP96,           /* ALFA Network AP96 board */
++      ATH79_MACH_ALFA_NX,             /* ALFA Network N2/N5 board */
++      ATH79_MACH_ALL0258N,            /* Allnet ALL0258N */
++      ATH79_MACH_ALL0305,             /* Allnet ALL0305 */
++      ATH79_MACH_ALL0315N,            /* Allnet ALL0315N */
++      ATH79_MACH_AP113,               /* Atheros AP113 reference board */
+       ATH79_MACH_AP121,               /* Atheros AP121 reference board */
+       ATH79_MACH_AP121_MINI,          /* Atheros AP121-MINI reference board */
+       ATH79_MACH_AP135_020,           /* Atheros AP135-020 reference board */
+       ATH79_MACH_AP136_010,           /* Atheros AP136-010 reference board */
+       ATH79_MACH_AP136_020,           /* Atheros AP136-020 reference board */
+       ATH79_MACH_AP81,                /* Atheros AP81 reference board */
++      ATH79_MACH_AP83,                /* Atheros AP83 */
++      ATH79_MACH_AP96,                /* Atheros AP96 */
++      ATH79_MACH_AW_NR580,            /* AzureWave AW-NR580 */
++      ATH79_MACH_CAP4200AG,           /* Senao CAP4200AG */
+       ATH79_MACH_DB120,               /* Atheros DB120 reference board */
+       ATH79_MACH_PB44,                /* Atheros PB44 reference board */
++      ATH79_MACH_DIR_600_A1,          /* D-Link DIR-600 rev. A1 */
++      ATH79_MACH_DIR_615_C1,          /* D-Link DIR-615 rev. C1 */
++      ATH79_MACH_DIR_615_E4,          /* D-Link DIR-615 rev. E4 */
++      ATH79_MACH_DIR_825_B1,          /* D-Link DIR-825 rev. B1 */
++      ATH79_MACH_EW_DORIN,            /* embedded wireless Dorin Platform */
++      ATH79_MACH_EW_DORIN_ROUTER,     /* embedded wireless Dorin Router Platform */
++      ATH79_MACH_EAP7660D,            /* Senao EAP7660D */
++      ATH79_MACH_JA76PF,              /* jjPlus JA76PF */
++      ATH79_MACH_JA76PF2,             /* jjPlus JA76PF2 */
++      ATH79_MACH_JWAP003,             /* jjPlus JWAP003 */
++      ATH79_MACH_HORNET_UB,           /* ALFA Networks Hornet-UB */
++      ATH79_MACH_MR600,               /* OpenMesh MR600 */
++      ATH79_MACH_MZK_W04NU,           /* Planex MZK-W04NU */
++      ATH79_MACH_MZK_W300NH,          /* Planex MZK-W300NH */
++      ATH79_MACH_NBG460N,             /* Zyxel NBG460N/550N/550NH */
++      ATH79_MACH_OM2P_HS,             /* OpenMesh OM2P-HS */
++      ATH79_MACH_OM2P_LC,             /* OpenMesh OM2P-LC */
++      ATH79_MACH_OM2P,                /* OpenMesh OM2P */
++      ATH79_MACH_PB42,                /* Atheros PB42 */
++      ATH79_MACH_PB92,                /* Atheros PB92 */
++      ATH79_MACH_RB_411,              /* MikroTik RouterBOARD 411/411A/411AH */
++      ATH79_MACH_RB_411U,             /* MikroTik RouterBOARD 411U */
++      ATH79_MACH_RB_433,              /* MikroTik RouterBOARD 433/433AH */
++      ATH79_MACH_RB_433U,             /* MikroTik RouterBOARD 433UAH */
++      ATH79_MACH_RB_435G,             /* MikroTik RouterBOARD 435G */
++      ATH79_MACH_RB_450G,             /* MikroTik RouterBOARD 450G */
++      ATH79_MACH_RB_450,              /* MikroTik RouterBOARD 450 */
++      ATH79_MACH_RB_493,              /* Mikrotik RouterBOARD 493/493AH */
++      ATH79_MACH_RB_493G,             /* Mikrotik RouterBOARD 493G */
++      ATH79_MACH_RB_750,              /* MikroTik RouterBOARD 750 */
++      ATH79_MACH_RB_750G_R3,          /* MikroTik RouterBOARD 750GL */
++      ATH79_MACH_RB_751,              /* MikroTik RouterBOARD 751 */
++      ATH79_MACH_RB_751G,             /* Mikrotik RouterBOARD 751G */
++      ATH79_MACH_RB_2011G,            /* Mikrotik RouterBOARD 2011UAS-2HnD */
++      ATH79_MACH_RB_2011L,            /* Mikrotik RouterBOARD 2011L */
++      ATH79_MACH_RW2458N,             /* Redwave RW2458N */
++      ATH79_MACH_TEW_632BRP,          /* TRENDnet TEW-632BRP */
++      ATH79_MACH_TEW_673GRU,          /* TRENDnet TEW-673GRU */
++      ATH79_MACH_TEW_712BR,           /* TRENDnet TEW-712BR */
++      ATH79_MACH_TL_MR11U,            /* TP-LINK TL-MR11U */
++      ATH79_MACH_TL_MR3020,           /* TP-LINK TL-MR3020 */
++      ATH79_MACH_TL_MR3040,           /* TP-LINK TL-MR3040 */
++      ATH79_MACH_TL_MR3220,           /* TP-LINK TL-MR3220 */
++      ATH79_MACH_TL_MR3220_V2,        /* TP-LINK TL-MR3220 v2 */
++      ATH79_MACH_TL_MR3420,     &n