Tested on Luxul XWR-3150 (boot, NAND, PCIe, switch, Ethernet).
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
SUBTARGETS:=generic
KERNEL_PATCHVER:=5.10
-KERNEL_TESTING_PATCHVER:=5.10
+KERNEL_TESTING_PATCHVER:=5.15
define Target/Description
Build firmware images for Broadcom based BCM47xx/53xx routers with ARM CPU, *not* MIPS.
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_5301X=y
+CONFIG_ARCH_BCM_53573=y
+# CONFIG_ARCH_BCM_HR2 is not set
+CONFIG_ARCH_BCM_IPROC=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GLOBAL_TIMER=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_B53=y
+CONFIG_B53_MDIO_DRIVER=y
+CONFIG_B53_SRAB_DRIVER=y
+CONFIG_BCM47XX_NVRAM=y
+CONFIG_BCM47XX_SPROM=y
+CONFIG_BCM47XX_WDT=y
+CONFIG_BCMA=y
+CONFIG_BCMA_BLOCKIO=y
+CONFIG_BCMA_DEBUG=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA_SFLASH=y
+# CONFIG_BCM_CYGNUS_PHY is not set
+CONFIG_BCM_NET_PHYLIB=y
+CONFIG_BCM_NS_THERMAL=y
+CONFIG_BCM_SR_THERMAL=y
+CONFIG_BGMAC=y
+CONFIG_BGMAC_BCMA=y
+# CONFIG_BGMAC_PLATFORM is not set
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
+CONFIG_CLKSRC_MMIO=y
+# CONFIG_CLK_BCM_NS2 is not set
+CONFIG_CLK_BCM_NSP=y
+# CONFIG_CLK_BCM_SR is not set
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_IPROC=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BCM_5301X=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DEBUG_UART_8250=y
+CONFIG_DEBUG_UART_8250_SHIFT=0
+CONFIG_DEBUG_UART_PHYS=0x18000300
+CONFIG_DEBUG_UART_VIRT=0xf1000300
+CONFIG_DEBUG_UNCOMPRESS=y
+CONFIG_DEBUG_USER=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_REMAP=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXTCON=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_74X164=y
+CONFIG_GPIO_BCM_XGS_IPROC=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GRO_CELLS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_BCM2835=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BCM_IPROC=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_BCM47XXSFLASH=y
+CONFIG_MTD_BCM47XX_PARTS=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_OF_PARTS_LINKSYS_NS=y
+CONFIG_MTD_PARSER_TRX=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_BRCM_NVRAM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCIE_IPROC=y
+CONFIG_PCIE_IPROC_BCMA=y
+# CONFIG_PCIE_IPROC_PLATFORM is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+# CONFIG_PHY_BCM_NS_USB2 is not set
+# CONFIG_PHY_BCM_NS_USB3 is not set
+# CONFIG_PHY_BCM_SR_PCIE is not set
+CONFIG_PHY_BCM_SR_USB=y
+# CONFIG_PHY_BRCM_SATA is not set
+# CONFIG_PHY_NS2_USB_DRD is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_IPROC_GPIO is not set
+CONFIG_PINCTRL_NS=y
+# CONFIG_PINCTRL_NS2_MUX is not set
+CONFIG_PWM=y
+CONFIG_PWM_BCM_IPROC=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BCM_QSPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SRCU=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+# CONFIG_VFP is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+From 465078bfdf5271601f098450ae2fc974865c59fd Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Thu, 10 Jun 2021 21:35:10 +0100
+Subject: [PATCH] ARM: dts: NSP: add device names to compatible
+
+Currently only the SoC type and platform are specified for all NSP
+devices. This patch adds the device names.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm958522er.dts | 2 +-
+ arch/arm/boot/dts/bcm958525er.dts | 2 +-
+ arch/arm/boot/dts/bcm958525xmc.dts | 2 +-
+ arch/arm/boot/dts/bcm958622hr.dts | 2 +-
+ arch/arm/boot/dts/bcm958625hr.dts | 2 +-
+ arch/arm/boot/dts/bcm958625k.dts | 2 +-
+ arch/arm/boot/dts/bcm988312hr.dts | 2 +-
+ 7 files changed, 7 insertions(+), 7 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm958522er.dts
++++ b/arch/arm/boot/dts/bcm958522er.dts
+@@ -37,7 +37,7 @@
+
+ / {
+ model = "NorthStar Plus SVK (BCM958522ER)";
+- compatible = "brcm,bcm58522", "brcm,nsp";
++ compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+--- a/arch/arm/boot/dts/bcm958525er.dts
++++ b/arch/arm/boot/dts/bcm958525er.dts
+@@ -37,7 +37,7 @@
+
+ / {
+ model = "NorthStar Plus SVK (BCM958525ER)";
+- compatible = "brcm,bcm58525", "brcm,nsp";
++ compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+--- a/arch/arm/boot/dts/bcm958525xmc.dts
++++ b/arch/arm/boot/dts/bcm958525xmc.dts
+@@ -37,7 +37,7 @@
+
+ / {
+ model = "NorthStar Plus XMC (BCM958525xmc)";
+- compatible = "brcm,bcm58525", "brcm,nsp";
++ compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+--- a/arch/arm/boot/dts/bcm958622hr.dts
++++ b/arch/arm/boot/dts/bcm958622hr.dts
+@@ -37,7 +37,7 @@
+
+ / {
+ model = "NorthStar Plus SVK (BCM958622HR)";
+- compatible = "brcm,bcm58622", "brcm,nsp";
++ compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+--- a/arch/arm/boot/dts/bcm958625hr.dts
++++ b/arch/arm/boot/dts/bcm958625hr.dts
+@@ -37,7 +37,7 @@
+
+ / {
+ model = "NorthStar Plus SVK (BCM958625HR)";
+- compatible = "brcm,bcm58625", "brcm,nsp";
++ compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+--- a/arch/arm/boot/dts/bcm958625k.dts
++++ b/arch/arm/boot/dts/bcm958625k.dts
+@@ -36,7 +36,7 @@
+
+ / {
+ model = "NorthStar Plus SVK (BCM958625K)";
+- compatible = "brcm,bcm58625", "brcm,nsp";
++ compatible = "brcm,bcm958625k", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+--- a/arch/arm/boot/dts/bcm988312hr.dts
++++ b/arch/arm/boot/dts/bcm988312hr.dts
+@@ -37,7 +37,7 @@
+
+ / {
+ model = "NorthStar Plus SVK (BCM988312HR)";
+- compatible = "brcm,bcm88312", "brcm,nsp";
++ compatible = "brcm,bcm988312hr", "brcm,bcm88312", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
--- /dev/null
+From 1b90dde4278a7b459979706b572785bc3a10bbb5 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Thu, 10 Jun 2021 21:35:12 +0100
+Subject: [PATCH] ARM: dts: NSP: enable DMA on bcm988312hr
+
+The previous patch "ARM: dts: NSP: Disable PL330 by default, add
+dma-coherent property" set the DMAC to disabled by default, requiring it
+to be manually enabled on each device. The bcm988312hr was mistakenly
+omitted. This patch adds it back.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm988312hr.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm988312hr.dts
++++ b/arch/arm/boot/dts/bcm988312hr.dts
+@@ -58,6 +58,10 @@
+
+ /* USB 3 support needed to be complete */
+
++&dma {
++ status = "okay";
++};
++
+ &amac0 {
+ status = "okay";
+ };
--- /dev/null
+From 091a12b1814142eac16a115dab206f735b5476a9 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Sun, 13 Jun 2021 10:46:34 +0100
+Subject: [PATCH] ARM: dts: NSP: disable qspi node by default
+
+The QSPI bus is enabled by default, however this may not used on all
+devices. This patch disables by default, requiring it to be explicitly
+enabled where required.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm-nsp.dtsi | 1 +
+ arch/arm/boot/dts/bcm958522er.dts | 1 +
+ arch/arm/boot/dts/bcm958525er.dts | 1 +
+ arch/arm/boot/dts/bcm958525xmc.dts | 1 +
+ arch/arm/boot/dts/bcm958622hr.dts | 1 +
+ arch/arm/boot/dts/bcm958623hr.dts | 1 +
+ arch/arm/boot/dts/bcm958625hr.dts | 1 +
+ arch/arm/boot/dts/bcm958625k.dts | 1 +
+ arch/arm/boot/dts/bcm988312hr.dts | 1 +
+ 9 files changed, 9 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm-nsp.dtsi
++++ b/arch/arm/boot/dts/bcm-nsp.dtsi
+@@ -310,6 +310,7 @@
+ num-cs = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
++ status = "disabled";
+ };
+
+ xhci: usb@29000 {
+--- a/arch/arm/boot/dts/bcm958522er.dts
++++ b/arch/arm/boot/dts/bcm958522er.dts
+@@ -134,6 +134,7 @@
+ };
+
+ &qspi {
++ status = "okay";
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+--- a/arch/arm/boot/dts/bcm958525er.dts
++++ b/arch/arm/boot/dts/bcm958525er.dts
+@@ -134,6 +134,7 @@
+ };
+
+ &qspi {
++ status = "okay";
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+--- a/arch/arm/boot/dts/bcm958525xmc.dts
++++ b/arch/arm/boot/dts/bcm958525xmc.dts
+@@ -150,6 +150,7 @@
+ };
+
+ &qspi {
++ status = "okay";
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+--- a/arch/arm/boot/dts/bcm958622hr.dts
++++ b/arch/arm/boot/dts/bcm958622hr.dts
+@@ -138,6 +138,7 @@
+ };
+
+ &qspi {
++ status = "okay";
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+--- a/arch/arm/boot/dts/bcm958623hr.dts
++++ b/arch/arm/boot/dts/bcm958623hr.dts
+@@ -142,6 +142,7 @@
+ };
+
+ &qspi {
++ status = "okay";
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+--- a/arch/arm/boot/dts/bcm958625hr.dts
++++ b/arch/arm/boot/dts/bcm958625hr.dts
+@@ -149,6 +149,7 @@
+ };
+
+ &qspi {
++ status = "okay";
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+--- a/arch/arm/boot/dts/bcm958625k.dts
++++ b/arch/arm/boot/dts/bcm958625k.dts
+@@ -153,6 +153,7 @@
+ };
+
+ &qspi {
++ status = "okay";
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
+--- a/arch/arm/boot/dts/bcm988312hr.dts
++++ b/arch/arm/boot/dts/bcm988312hr.dts
+@@ -138,6 +138,7 @@
+ };
+
+ &qspi {
++ status = "okay";
+ bspi-sel = <0>;
+ flash: m25p80@0 {
+ #address-cells = <1>;
--- /dev/null
+From 236b31b1d84eb0e4f10c5f113a2675529456f919 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Sun, 13 Jun 2021 10:46:36 +0100
+Subject: [PATCH] ARM: dts: NSP: add MDIO bus controller node
+
+This patch adds the node for the MDIO bus controller, present on the NSP
+SoC.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm-nsp.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm-nsp.dtsi
++++ b/arch/arm/boot/dts/bcm-nsp.dtsi
+@@ -363,6 +363,13 @@
+ status = "disabled";
+ };
+
++ mdio: mdio@32000 {
++ compatible = "brcm,iproc-mdio";
++ reg = <0x32000 0x8>;
++ #size-cells = <0>;
++ #address-cells = <1>;
++ };
++
+ rng: rng@33000 {
+ compatible = "brcm,bcm-nsp-rng";
+ reg = <0x33000 0x14>;
--- /dev/null
+From 1c615401bddb1be21e1d375aaa071680f40f1ae2 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Sun, 13 Jun 2021 10:46:37 +0100
+Subject: [PATCH] ARM: dts: NSP: Move USB3 PHY to internal MDIO bus
+
+This patch largely replicates Vivek Unune's patch "ARM: dts:
+BCM5301X:Make usb3 phy use mdio phy driver"[1] for the NSP platform,
+whereby we need to create an mdio-mux to facilitate switches
+configured via external MDIO, in this case on the Meraki MX65.
+
+However in doing so, we are creating an overlap with usb3_phy's
+ccb-mii range. To resolve this, usb3_phy should be moved to a child
+node of the internal MDIO bus. The result is heavily based upon Vivek's
+patch. This has also been cross-referenced with Yendapally Reddy's
+earlier work which utilised the subsequently dropped brcm,nsp-usb3-phy
+driver: "[PATCH v2 4/4] arm: dts: nsp: Add USB nodes to device tree"
+[2]. Finally, this change provides conformance to the bcm-ns-usb3-phy
+documentation, utilising the required usb3-dmp-syscon property. Note
+that support for the deprecated ccb-mii bindings has been dropped as of
+"phy: phy-bcm-ns-usb3: drop support for deprecated DT binding"[3].
+
+[1] https://lore.kernel.org/patchwork/patch/933971/
+[2] https://www.spinics.net/lists/arm-kernel/msg555132.html
+[3] https://lore.kernel.org/linux-devicetree/20201113113423.9466-1-zajec5@gmail.com/
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm-nsp.dtsi | 38 +++++++++++++++++++++++++++-------
+ 1 file changed, 31 insertions(+), 7 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm-nsp.dtsi
++++ b/arch/arm/boot/dts/bcm-nsp.dtsi
+@@ -370,6 +370,35 @@
+ #address-cells = <1>;
+ };
+
++ mdio-mux@32000 {
++ compatible = "mdio-mux-mmioreg";
++ reg = <0x32000 0x4>;
++ mux-mask = <0x200>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ mdio-parent-bus = <&mdio>;
++
++ mdio_int: mdio@0 {
++ reg = <0x0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ usb3_phy: usb3-phy@10 {
++ compatible = "brcm,ns-bx-usb3-phy";
++ reg = <0x10>;
++ usb3-dmp-syscon = <&usb3_dmp>;
++ #phy-cells = <0>;
++ status = "disabled";
++ };
++ };
++
++ mdio_ext: mdio@200 {
++ reg = <0x200>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++
+ rng: rng@33000 {
+ compatible = "brcm,bcm-nsp-rng";
+ reg = <0x33000 0x14>;
+@@ -528,13 +557,8 @@
+ };
+ };
+
+- usb3_phy: usb3-phy@104000 {
+- compatible = "brcm,ns-bx-usb3-phy";
+- reg = <0x104000 0x1000>,
+- <0x032000 0x1000>;
+- reg-names = "dmp", "ccb-mii";
+- #phy-cells = <0>;
+- status = "disabled";
++ usb3_dmp: syscon@104000 {
++ reg = <0x104000 0x1000>;
+ };
+ };
+
--- /dev/null
+From f111016a8293b968f05450fec83020c94d0f88c2 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Fri, 6 Aug 2021 21:44:32 +0100
+Subject: [PATCH] ARM: dts: NSP: Add common bindings for MX64/MX65
+
+These bindings are required for all Meraki MX64/MX65 devices. These
+common bindings include memory (2GB), PWM LEDs, AMAC, I2C (AT24), NAND
+partitions, EHCI, OHCI and pinctrl.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../dts/bcm958625-meraki-mx6x-common.dtsi | 129 ++++++++++++++++++
+ 1 file changed, 129 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
+
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
+@@ -0,0 +1,129 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices.
++ *
++ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
++ */
++
++#include "bcm-nsp.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++ pwm-leds {
++ compatible = "pwm-leds";
++
++ led-1 {
++ function = LED_FUNCTION_INDICATOR;
++ color = <LED_COLOR_ID_RED>;
++ pwms = <&pwm 1 50000>;
++ max-brightness = <255>;
++ };
++
++ led-2 {
++ function = LED_FUNCTION_INDICATOR;
++ color = <LED_COLOR_ID_GREEN>;
++ pwms = <&pwm 2 50000>;
++ max-brightness = <255>;
++ };
++
++ led-3 {
++ function = LED_FUNCTION_INDICATOR;
++ color = <LED_COLOR_ID_BLUE>;
++ pwms = <&pwm 3 50000>;
++ max-brightness = <255>;
++ };
++ };
++};
++
++&amac2 {
++ status = "okay";
++};
++
++&ehci0 {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++
++ at24@50 {
++ compatible = "atmel,24c64";
++ reg = <0x50>;
++ pagesize = <32>;
++ read-only;
++ };
++};
++
++&nand_controller {
++ nand@0 {
++ compatible = "brcm,nandcs";
++ reg = <0>;
++ nand-on-flash-bbt;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ nand-ecc-strength = <24>;
++ nand-ecc-step-size = <1024>;
++
++ brcm,nand-oob-sector-size = <27>;
++
++ partition@0 {
++ label = "u-boot";
++ reg = <0x0 0x80000>;
++ read-only;
++ };
++
++ partition@80000 {
++ label = "shmoo";
++ reg = <0x80000 0x80000>;
++ read-only;
++ };
++
++ partition@100000 {
++ label = "bootkernel1";
++ reg = <0x100000 0x300000>;
++ };
++
++ partition@400000 {
++ label = "nvram";
++ reg = <0x400000 0x100000>;
++ };
++
++ partition@500000 {
++ label = "bootkernel2";
++ reg = <0x500000 0x300000>;
++ };
++
++ partition@800000 {
++ label = "ubi";
++ reg = <0x800000 0x3f700000>;
++ };
++ };
++};
++
++&ohci0 {
++ status = "okay";
++};
++
++&pinctrl {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm_leds>;
++
++ pwm_leds: pwm_leds {
++ function = "pwm";
++ groups = "pwm1_grp", "pwm2_grp", "pwm3_grp";
++ };
++};
++
++&pwm {
++ status = "okay";
++ #pwm-cells = <2>;
++};
++
++&uart0 {
++ clock-frequency = <62500000>;
++ status = "okay";
++};
--- /dev/null
+From 2addf9266a1d0f4ba59c9868b3effcd50de441a4 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Fri, 6 Aug 2021 21:44:33 +0100
+Subject: [PATCH] ARM: dts: NSP: Add Ax stepping modifications
+
+While uncommon, some Ax NSP SoCs exist in the wild. This stepping
+requires a modified secondary CPU boot-reg and removal of DMA coherency
+properties. Without these modifications, the secondary CPU will be
+inactive and many peripherals will exhibit undefined behaviour.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm-nsp-ax.dtsi | 70 +++++++++++++++++++++++++++++++
+ 1 file changed, 70 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi
+
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm-nsp-ax.dtsi
+@@ -0,0 +1,70 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Broadcom Northstar Plus Ax stepping-specific bindings.
++ * Notable differences from B0+ are the secondary-boot-reg and
++ * lack of DMA coherency.
++ */
++
++&cpu1 {
++ secondary-boot-reg = <0xffff042c>;
++};
++
++&dma {
++ /delete-property/ dma-coherent;
++};
++
++&sdio {
++ /delete-property/ dma-coherent;
++};
++
++&amac0 {
++ /delete-property/ dma-coherent;
++};
++
++&amac1 {
++ /delete-property/ dma-coherent;
++};
++
++&amac2 {
++ /delete-property/ dma-coherent;
++};
++
++&ehci0 {
++ /delete-property/ dma-coherent;
++};
++
++&mailbox {
++ /delete-property/ dma-coherent;
++};
++
++&xhci {
++ /delete-property/ dma-coherent;
++};
++
++&ehci0 {
++ /delete-property/ dma-coherent;
++};
++
++&ohci0 {
++ /delete-property/ dma-coherent;
++};
++
++&i2c0 {
++ /delete-property/ dma-coherent;
++};
++
++&sata {
++ /delete-property/ dma-coherent;
++};
++
++&pcie0 {
++ /delete-property/ dma-coherent;
++};
++
++&pcie1 {
++ /delete-property/ dma-coherent;
++};
++
++&pcie2 {
++ /delete-property/ dma-coherent;
++};
--- /dev/null
+From 3f902645280baf0d7dab57c227cc14f43edb45ef Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Fri, 6 Aug 2021 21:44:34 +0100
+Subject: [PATCH] ARM: dts: NSP: Add DT files for Meraki MX64 series
+
+MX64 & MX64W Hardware info:
+ - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz
+ - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)
+ - Storage: 1 GB (Micron MT29F8G08ABACA)
+ - Networking: BCM58625 internal switch (5x 1GbE ports)
+ - USB: 1x USB2.0
+ - Serial: Internal header
+ - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus
+
+This patch adds the Meraki MX64 series-specific bindings. Since some
+devices make use of the older A0 SoC, changes need to be made to
+accommodate this case, including removal of coherency options and
+modification to the secondary-boot-reg.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 4 +
+ .../boot/dts/bcm958625-meraki-kingpin.dtsi | 163 ++++++++++++++++++
+ .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 25 +++
+ arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 24 +++
+ .../boot/dts/bcm958625-meraki-mx64w-a0.dts | 33 ++++
+ arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 32 ++++
+ 6 files changed, 281 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
+ create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts
+ create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts
+ create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts
+ create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -157,6 +157,10 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
+ bcm958525xmc.dtb \
+ bcm958622hr.dtb \
+ bcm958623hr.dtb \
++ bcm958625-meraki-mx64.dtb \
++ bcm958625-meraki-mx64-a0.dtb \
++ bcm958625-meraki-mx64w.dtb \
++ bcm958625-meraki-mx64w-a0.dtb \
+ bcm958625hr.dtb \
+ bcm988312hr.dtb \
+ bcm958625k.dtb
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
+@@ -0,0 +1,163 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin).
++ *
++ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
++ */
++
++#include "bcm958625-meraki-mx6x-common.dtsi"
++
++/ {
++
++ keys {
++ compatible = "gpio-keys-polled";
++ autorepeat;
++ poll-interval = <20>;
++
++ reset {
++ label = "reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ led-0 {
++ /* green:lan1-left */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <0>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 19 GPIO_ACTIVE_LOW>;
++ };
++
++ led-1 {
++ /* green:lan1-right */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <1>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 18 GPIO_ACTIVE_LOW>;
++ };
++
++ led-2 {
++ /* green:lan2-left */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <2>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
++ };
++
++ led-3 {
++ /* green:lan2-right */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <3>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 20 GPIO_ACTIVE_LOW>;
++ };
++
++ led-4 {
++ /* green:lan3-left */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <4>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
++ };
++
++ led-5 {
++ /* green:lan3-right */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <5>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
++ };
++
++ led-6 {
++ /* green:lan4-left */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <6>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
++ };
++
++ led-7 {
++ /* green:lan4-right */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <7>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
++ };
++
++ led-8 {
++ /* green:wan-left */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <8>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 30 GPIO_ACTIVE_LOW>;
++ };
++
++ led-9 {
++ /* green:wan-right */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <9>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 29 GPIO_ACTIVE_LOW>;
++ };
++
++ led-a {
++ /* amber:power */
++ function = LED_FUNCTION_POWER;
++ color = <LED_COLOR_ID_AMBER>;
++ gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
++ default-state = "on";
++ };
++
++ led-b {
++ /* white:status */
++ function = LED_FUNCTION_STATUS;
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
++ };
++ };
++};
++
++&srab {
++ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
++ status = "okay";
++
++ ports {
++ port@0 {
++ label = "lan1";
++ reg = <0>;
++ };
++
++ port@1 {
++ label = "lan2";
++ reg = <1>;
++ };
++
++ port@2 {
++ label = "lan3";
++ reg = <2>;
++ };
++
++ port@3 {
++ label = "lan4";
++ reg = <3>;
++ };
++
++ port@4 {
++ label = "wan";
++ reg = <4>;
++ };
++
++ port@8 {
++ ethernet = <&amac2>;
++ reg = <8>;
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts
+@@ -0,0 +1,25 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC.
++ *
++ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
++ */
++
++/dts-v1/;
++
++#include "bcm958625-meraki-kingpin.dtsi"
++#include "bcm-nsp-ax.dtsi"
++
++/ {
++ model = "Cisco Meraki MX64(A0)";
++ compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp";
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@60000000 {
++ device_type = "memory";
++ reg = <0x60000000 0x80000000>;
++ };
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts
+@@ -0,0 +1,24 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC.
++ *
++ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
++ */
++
++/dts-v1/;
++
++#include "bcm958625-meraki-kingpin.dtsi"
++
++/ {
++ model = "Cisco Meraki MX64";
++ compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp";
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@60000000 {
++ device_type = "memory";
++ reg = <0x60000000 0x80000000>;
++ };
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts
+@@ -0,0 +1,33 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC.
++ *
++ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
++ */
++
++/dts-v1/;
++
++#include "bcm958625-meraki-kingpin.dtsi"
++#include "bcm-nsp-ax.dtsi"
++
++/ {
++ model = "Cisco Meraki MX64W(A0)";
++ compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp";
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@60000000 {
++ device_type = "memory";
++ reg = <0x60000000 0x80000000>;
++ };
++};
++
++&pcie0 {
++ status = "okay";
++};
++
++&pcie1 {
++ status = "okay";
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts
+@@ -0,0 +1,32 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC.
++ *
++ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
++ */
++
++/dts-v1/;
++
++#include "bcm958625-meraki-kingpin.dtsi"
++
++/ {
++ model = "Cisco Meraki MX64W";
++ compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp";
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@60000000 {
++ device_type = "memory";
++ reg = <0x60000000 0x80000000>;
++ };
++};
++
++&pcie0 {
++ status = "okay";
++};
++
++&pcie1 {
++ status = "okay";
++};
--- /dev/null
+From 702a8f4744ed5b480f2b2411858184afdb10f9fd Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Fri, 6 Aug 2021 21:44:35 +0100
+Subject: [PATCH] ARM: dts: NSP: Add DT files for Meraki MX65 series
+
+MX65 & MX65W Hardware info:
+ - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz
+ - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)
+ - Storage: 1 GB (Micron MT29F8G08ABACA)
+ - Networking: BCM58625 switch (2x 1GbE ports)
+ 2x Qualcomm QCA8337 switches (10x 1GbE ports total)
+ - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12
+ - USB: 1x USB2.0
+ - Serial: Internal header
+ - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus.
+
+Note that a driver and firmware image for the BCM59111 PSE has been
+released under GPL, but this is not present in the kernel.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 2 +
+ arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++
+ arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 ++
+ arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 ++
+ 4 files changed, 337 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
+ create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts
+ create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -161,6 +161,8 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
+ bcm958625-meraki-mx64-a0.dtb \
+ bcm958625-meraki-mx64w.dtb \
+ bcm958625-meraki-mx64w-a0.dtb \
++ bcm958625-meraki-mx65.dtb \
++ bcm958625-meraki-mx65w.dtb \
+ bcm958625hr.dtb \
+ bcm988312hr.dtb \
+ bcm958625k.dtb
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
+@@ -0,0 +1,279 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Device Tree Bindings for Cisco Meraki MX65 series (Alamo).
++ *
++ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
++ */
++
++#include "bcm958625-meraki-mx6x-common.dtsi"
++
++/ {
++ keys {
++ compatible = "gpio-keys-polled";
++ autorepeat;
++ poll-interval = <20>;
++
++ reset {
++ label = "reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ led-0 {
++ /* green:wan1-left */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <0>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
++ };
++
++ led-1 {
++ /* green:wan1-right */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <1>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
++ };
++
++ led-2 {
++ /* green:wan2-left */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <2>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
++ };
++
++ led-3 {
++ /* green:wan2-right */
++ function = LED_FUNCTION_ACTIVITY;
++ function-enumerator = <3>;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
++ };
++
++ led-4 {
++ /* amber:power */
++ function = LED_FUNCTION_POWER;
++ color = <LED_COLOR_ID_AMBER>;
++ gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ };
++
++ led-5 {
++ /* white:status */
++ function = LED_FUNCTION_STATUS;
++ color = <LED_COLOR_ID_WHITE>;
++ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ mdio-mii-mux {
++ compatible = "mdio-mux-mmioreg";
++ reg = <0x1803f1c0 0x4>;
++ mux-mask = <0x2000>;
++ mdio-parent-bus = <&mdio_ext>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ mdio@0 {
++ reg = <0x0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy_port6: phy@0 {
++ reg = <0>;
++ };
++
++ phy_port7: phy@1 {
++ reg = <1>;
++ };
++
++ phy_port8: phy@2 {
++ reg = <2>;
++ };
++
++ phy_port9: phy@3 {
++ reg = <3>;
++ };
++
++ phy_port10: phy@4 {
++ reg = <4>;
++ };
++
++ switch@10 {
++ compatible = "qca,qca8337";
++ reg = <0x10>;
++ dsa,member = <1 0>;
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ port@0 {
++ reg = <0>;
++ ethernet = <&sgmii1>;
++ phy-mode = "sgmii";
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan8";
++ phy-handle = <&phy_port6>;
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan9";
++ phy-handle = <&phy_port7>;
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan10";
++ phy-handle = <&phy_port8>;
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan11";
++ phy-handle = <&phy_port9>;
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "lan12";
++ phy-handle = <&phy_port10>;
++ };
++ };
++ };
++ };
++
++ mdio-mii@2000 {
++ reg = <0x2000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy_port1: phy@0 {
++ reg = <0>;
++ };
++
++ phy_port2: phy@1 {
++ reg = <1>;
++ };
++
++ phy_port3: phy@2 {
++ reg = <2>;
++ };
++
++ phy_port4: phy@3 {
++ reg = <3>;
++ };
++
++ phy_port5: phy@4 {
++ reg = <4>;
++ };
++
++ switch@10 {
++ compatible = "qca,qca8337";
++ reg = <0x10>;
++ dsa,member = <2 0>;
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ port@0 {
++ reg = <0>;
++ ethernet = <&sgmii0>;
++ phy-mode = "sgmii";
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan3";
++ phy-handle = <&phy_port1>;
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan4";
++ phy-handle = <&phy_port2>;
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan5";
++ phy-handle = <&phy_port3>;
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan6";
++ phy-handle = <&phy_port4>;
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "lan7";
++ phy-handle = <&phy_port5>;
++ };
++ };
++ };
++ };
++ };
++};
++
++&srab {
++ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
++ status = "okay";
++ dsa,member = <0 0>;
++
++ ports {
++ port@0 {
++ label = "wan1";
++ reg = <0>;
++ };
++
++ port@1 {
++ label = "wan2";
++ reg = <1>;
++ };
++
++ sgmii0: port@4 {
++ label = "sw0";
++ reg = <4>;
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++
++ sgmii1: port@5 {
++ label = "sw1";
++ reg = <5>;
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++
++ port@8 {
++ ethernet = <&amac2>;
++ reg = <8>;
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts
+@@ -0,0 +1,24 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Device Tree Bindings for Cisco Meraki MX65.
++ *
++ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
++ */
++
++/dts-v1/;
++
++#include "bcm958625-meraki-alamo.dtsi"
++
++/ {
++ model = "Cisco Meraki MX65";
++ compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp";
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@60000000 {
++ device_type = "memory";
++ reg = <0x60000000 0x80000000>;
++ };
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
+@@ -0,0 +1,32 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Device Tree Bindings for Cisco Meraki MX65W.
++ *
++ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
++ */
++
++/dts-v1/;
++
++#include "bcm958625-meraki-alamo.dtsi"
++
++/ {
++ model = "Cisco Meraki MX65W";
++ compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp";
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@60000000 {
++ device_type = "memory";
++ reg = <0x60000000 0x80000000>;
++ };
++};
++
++&pcie0 {
++ status = "okay";
++};
++
++&pcie1 {
++ status = "okay";
++};
--- /dev/null
+From 695717eb4c61173d05a277e37132b5e2c6531bf1 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Sun, 29 Aug 2021 22:37:47 +0000
+Subject: [PATCH] ARM: dts: NSP: Add bcm958623hr board name to dts
+
+This board was previously added to
+Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
+however the dts file was not updated to reflect this change. This patch
+corrects bcm958623hr.dts by adding the board name to the compatible.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm958623hr.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/bcm958623hr.dts
++++ b/arch/arm/boot/dts/bcm958623hr.dts
+@@ -37,7 +37,7 @@
+
+ / {
+ model = "NorthStar Plus SVK (BCM958623HR)";
+- compatible = "brcm,bcm58623", "brcm,nsp";
++ compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
--- /dev/null
+From 38f8111369f318a538e9d4d89d8e48030c22fb40 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Sun, 29 Aug 2021 22:37:49 +0000
+Subject: [PATCH] ARM: dts: NSP: Fix MDIO mux node names
+
+While functional, the mdio-mux-mmioreg binding does not conform to
+Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml in that an
+mdio-mux compatible is also required. Without this the following output
+is observed when running dtbs_check:
+
+mdio-mux@32000: compatible: ['mdio-mux-mmioreg'] is too short
+
+This change brings conformance to this requirement and corresponds
+likewise to Rafal Milecki's change to the BCM5301x platform[1].
+
+[1] https://lore.kernel.org/linux-arm-kernel/20210822191256.3715003-1-f.fainelli@gmail.com/T/
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-
+ arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm-nsp.dtsi
++++ b/arch/arm/boot/dts/bcm-nsp.dtsi
+@@ -371,7 +371,7 @@
+ };
+
+ mdio-mux@32000 {
+- compatible = "mdio-mux-mmioreg";
++ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ reg = <0x32000 0x4>;
+ mux-mask = <0x200>;
+ #address-cells = <1>;
+--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
++++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
+@@ -72,7 +72,7 @@
+ };
+
+ mdio-mii-mux {
+- compatible = "mdio-mux-mmioreg";
++ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ reg = <0x1803f1c0 0x4>;
+ mux-mask = <0x2000>;
+ mdio-parent-bus = <&mdio_ext>;
--- /dev/null
+From 56e4e548427240d85fd220460d0ab5987e1dec00 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Sun, 29 Aug 2021 22:37:50 +0000
+Subject: [PATCH] ARM: dts: NSP: Fix MX64/MX65 eeprom node name
+
+Running dtbs_check yields the following message when checking the
+MX64/MX65 devicetree:
+at24@50: $nodename:0: 'at24@50' does not match '^eeprom@[0-9a-f]{1,2}$'
+
+This patch fixes the issue by renaming the at24 node appropriately.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
++++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
+@@ -48,7 +48,7 @@
+ &i2c0 {
+ status = "okay";
+
+- at24@50 {
++ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
--- /dev/null
+From f5fc9044e5d45a4d97b5240c8723f4677f647c9f Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Sun, 29 Aug 2021 22:37:51 +0000
+Subject: [PATCH] ARM: dts: NSP: Fix MX65 MDIO mux warnings
+
+The naming of this node is based upon that of the initial EA9500 dts[1].
+However this does not conform with the mdio-mux format, yielding the
+following message when running dtbs_check:
+mdio-mii-mux: $nodename:0: 'mdio-mii-mux' does not match '^mdio-mux[\\-@]?'
+
+Secondly, this node should be moved to within the axi node and given the
+appropriate unit address. This also requires exposing the axi node via a
+label in bcm-nsp.dtsi. This fixes the following warning:
+Warning (unit_address_vs_reg): /mdio-mii-mux: node has a reg or ranges property, but no unit name
+
+[1]https://patchwork.ozlabs.org/project/linux-imx/patch/20180618174159.86150-1-npcomplete13@gmail.com/#1941353
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-
+ arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 6 ++++--
+ 2 files changed, 5 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm-nsp.dtsi
++++ b/arch/arm/boot/dts/bcm-nsp.dtsi
+@@ -166,7 +166,7 @@
+ };
+ };
+
+- axi@18000000 {
++ axi: axi@18000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x18000000 0x0011c40c>;
+ #address-cells = <1>;
+--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
++++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
+@@ -70,10 +70,12 @@
+ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
++};
+
+- mdio-mii-mux {
++&axi {
++ mdio-mux@3f1c0 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+- reg = <0x1803f1c0 0x4>;
++ reg = <0x3f1c0 0x4>;
+ mux-mask = <0x2000>;
+ mdio-parent-bus = <&mdio_ext>;
+ #address-cells = <1>;
--- /dev/null
+From 225ffaf3d0e00daa2d0c7b68e8fd731ebbde3c03 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 7 Sep 2021 08:00:48 +0200
+Subject: [PATCH] ARM: dts: BCM5301X: Specify switch ports for more devices
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Those are remaining models I have that didn't have ports yet. All
+tested.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 37 ++++++++++++++++
+ .../boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 37 ++++++++++++++++
+ arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 42 +++++++++++++++++++
+ arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 42 +++++++++++++++++++
+ arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 37 ++++++++++++++++
+ arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 37 ++++++++++++++++
+ 6 files changed, 232 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+@@ -94,3 +94,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan4";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan3";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan1";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
+@@ -117,3 +117,40 @@
+ };
+ };
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
+@@ -187,3 +187,45 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@8 {
++ reg = <8>;
++ label = "cpu";
++ ethernet = <&gmac2>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+@@ -118,3 +118,45 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan4";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan3";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan1";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@8 {
++ reg = <8>;
++ label = "cpu";
++ ethernet = <&gmac2>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
++++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
+@@ -68,3 +68,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan4";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan2";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan1";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
++++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
+@@ -68,3 +68,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan4";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan2";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan1";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
--- /dev/null
+From 9fb90ae6cae7f8fe4fbf626945f32cd9da2c3892 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 20 Sep 2021 16:10:23 +0200
+Subject: [PATCH] ARM: dts: BCM53573: Describe on-SoC BCM53125 rev 4 switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM53573 family SoC have Ethernet switch connected to the first Ethernet
+controller (accessible over MDIO).
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm53573.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm53573.dtsi
++++ b/arch/arm/boot/dts/bcm53573.dtsi
+@@ -180,6 +180,24 @@
+
+ gmac0: ethernet@5000 {
+ reg = <0x5000 0x1000>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ switch: switch@1e {
++ compatible = "brcm,bcm53125";
++ reg = <0x1e>;
++
++ status = "disabled";
++
++ /* ports are defined in board DTS */
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++ };
++ };
+ };
+
+ gmac1: ethernet@b000 {
--- /dev/null
+From 64612828628cca6e3992e421f45c242dc6625647 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 20 Sep 2021 16:10:24 +0200
+Subject: [PATCH] ARM: dts: BCM53573: Add Tenda AC9 switch ports
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This router has 1 WAN and 4 LAN ports.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 37 ++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
++++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
+@@ -105,3 +105,40 @@
+ };
+ };
+ };
++
++&switch {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan1";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan3";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan4";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
--- /dev/null
+From 6abc4ca5a28070945e0d68cb4160b309bfbf4b8b Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sat, 18 Sep 2021 19:29:30 +0200
+Subject: [PATCH] ARM: BCM53016: Specify switch ports for Meraki MR32
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+the switch identifies itself as a BCM53012 (rev 5)...
+This patch has been tested & verified on OpenWrt's
+snapshot with Linux 5.10 (didn't test any older kernels).
+The MR32 is able to "talk to the network" as before with
+OpenWrt's SWITCHDEV b53 driver.
+
+| b53-srab-switch 18007000.ethernet-switch: found switch: BCM53012, rev 5
+| libphy: dsa slave smi: probed
+| b53-srab-switch 18007000.ethernet-switch poe (uninitialized):
+| PHY [dsa-0.0:00] driver [Generic PHY] (irq=POLL)
+| b53-srab-switch 18007000.ethernet-switch: Using legacy PHYLIB callbacks.
+| Please migrate to PHYLINK!
+| DSA: tree 0 setup
+
+Reported-by: Rafał Miłecki <zajec5@gmail.com>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
+@@ -217,3 +217,25 @@
+ };
+ };
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "poe";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++
++ fixed-link {
++ speed = <1000>;
++ duplex-full;
++ };
++ };
++ };
++};
--- /dev/null
+From 477ffdbdf389cc91294d66e251cc6f856da5820c Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sat, 18 Sep 2021 19:29:31 +0200
+Subject: [PATCH] ARM: BCM53016: MR32: get mac-address from nvmem
+
+The MAC-Address of the MR32's sole ethernet port is
+located in offset 0x66 of the attached AT24C64 eeprom.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
+@@ -110,6 +110,12 @@
+ reg = <0x50>;
+ pagesize = <32>;
+ read-only;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ mac_address: mac-address@66 {
++ reg = <0x66 0x6>;
++ };
+ };
+ };
+ };
+@@ -133,6 +139,11 @@
+ */
+ };
+
++&gmac0 {
++ nvmem-cell-names = "mac-address";
++ nvmem-cells = <&mac_address>;
++};
++
+ &gmac1 {
+ status = "disabled";
+ };
--- /dev/null
+From beff77b93452cd2057c859694709dd34a181488f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 21 Sep 2021 20:19:01 +0800
+Subject: [PATCH] ARM: dts: BCM5301X: Add DT for Asus RT-AC88U
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Hardware Info
+-------------
+
+Processor - Broadcom BCM4709C0KFEBG dual-core @ 1.4 GHz
+Switch - BCM53012 in BCM4709C0KFEBG & external RTL8365MB
+DDR3 RAM - 512 MB
+Flash - 128 MB (ESMT F59L1G81LA-25T)
+2.4GHz - BCM4366 4×4 2.4/5G single chip 802.11ac SoC
+5GHz - BCM4366 4×4 2.4/5G single chip 802.11ac SoC
+Ports - 8 Ports, 1 WAN Ports
+
+Tested on OpenWrt on kernel 5.10 built with DSA driver.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 1 +
+ arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 200 +++++++++++++++++++
+ 2 files changed, 201 insertions(+)
+ create mode 100644 arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm4709-netgear-r7000.dtb \
+ bcm4709-netgear-r8000.dtb \
+ bcm4709-tplink-archer-c9-v1.dtb \
++ bcm47094-asus-rt-ac88u.dtb \
+ bcm47094-dlink-dir-885l.dtb \
+ bcm47094-linksys-panamera.dtb \
+ bcm47094-luxul-abr-4500.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+@@ -0,0 +1,200 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (C) 2021 Arınç ÜNAL <arinc.unal@arinc9.com>
++ */
++
++/dts-v1/;
++
++#include "bcm47094.dtsi"
++#include "bcm5301x-nand-cs0-bch8.dtsi"
++
++/ {
++ compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
++ model = "Asus RT-AC88U";
++
++ chosen {
++ bootargs = "earlycon";
++ };
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x00000000 0x08000000>,
++ <0x88000000 0x18000000>;
++ };
++
++ nvram@1c080000 {
++ compatible = "brcm,nvram";
++ reg = <0x1c080000 0x00180000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ power {
++ label = "white:power";
++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-on";
++ };
++
++ wan-red {
++ label = "red:wan";
++ gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
++ };
++
++ lan {
++ label = "white:lan";
++ gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;
++ };
++
++ usb2 {
++ label = "white:usb2";
++ gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
++ trigger-sources = <&ehci_port2>;
++ linux,default-trigger = "usbport";
++ };
++
++ usb3 {
++ label = "white:usb3";
++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
++ trigger-sources = <&ehci_port1>, <&xhci_port1>;
++ linux,default-trigger = "usbport";
++ };
++
++ wps {
++ label = "white:wps";
++ gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ wps {
++ label = "WPS";
++ linux,code = <KEY_WPS_BUTTON>;
++ gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
++ };
++
++ reset {
++ label = "Reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
++ };
++
++ wifi {
++ label = "Wi-Fi";
++ linux,code = <KEY_RFKILL>;
++ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
++ };
++
++ led {
++ label = "Backlight";
++ linux,code = <KEY_BRIGHTNESS_ZERO>;
++ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&srab {
++ compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab";
++ status = "okay";
++ dsa,member = <0 0>;
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ label = "lan4";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan3";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan1";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ sw0_p5: port@5 {
++ reg = <5>;
++ label = "extsw";
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++
++ port@7 {
++ reg = <7>;
++ ethernet = <&gmac1>;
++ label = "cpu";
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++
++ port@8 {
++ reg = <8>;
++ ethernet = <&gmac2>;
++ label = "cpu";
++ status = "disabled";
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++ };
++};
++
++&usb2 {
++ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
++};
++
++&usb3_phy {
++ status = "okay";
++};
++
++&nandcs {
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "boot";
++ reg = <0x00000000 0x00080000>;
++ read-only;
++ };
++
++ partition@80000 {
++ label = "nvram";
++ reg = <0x00080000 0x00180000>;
++ };
++
++ partition@200000 {
++ label = "firmware";
++ reg = <0x00200000 0x07e00000>;
++ compatible = "brcm,trx";
++ };
++ };
++};
--- /dev/null
+From 58d3d07985c1adab31a3ed76360d016bb1c5b358 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Fri, 15 Oct 2021 23:50:22 +0100
+Subject: [PATCH] ARM: dts: NSP: MX65: add qca8k falling-edge, PLL properties
+
+This patch enables two properties for the QCA8337 switches on the MX65.
+
+Set the SGMII transmit clock to falling edge
+"qca,sgmii-txclk-falling-edge" to conform to the OEM configuration [1].
+
+The new explicit PLL enable option "qca,sgmii-enable-pll" is required
+[2].
+
+[1] https://git.kernel.org/netdev/net-next/c/6c43809bf1be
+[2] https://git.kernel.org/netdev/net-next/c/bbc4799e8bb6
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
++++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
+@@ -118,6 +118,8 @@
+ reg = <0>;
+ ethernet = <&sgmii1>;
+ phy-mode = "sgmii";
++ qca,sgmii-enable-pll;
++ qca,sgmii-txclk-falling-edge;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+@@ -194,6 +196,8 @@
+ reg = <0>;
+ ethernet = <&sgmii0>;
+ phy-mode = "sgmii";
++ qca,sgmii-enable-pll;
++ qca,sgmii-txclk-falling-edge;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
--- /dev/null
+From 835992e7eca4b29a87c204cefff2f7863fd087f3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Wed, 27 Oct 2021 00:57:03 +0800
+Subject: [PATCH] ARM: dts: BCM5301X: remove unnecessary address & size cells
+ from Asus RT-AC88U
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Remove the unnecessary #address-cells & #size-cells in the gpio-keys node
+from the device tree of Asus RT-AC88U.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
++++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+@@ -68,8 +68,6 @@
+
+ gpio-keys {
+ compatible = "gpio-keys";
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+ wps {
+ label = "WPS";
--- /dev/null
+From b6c99228c8edc5e67d8229ba1c5f76cce210ddfc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Wed, 27 Oct 2021 00:57:06 +0800
+Subject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Define the Realtek RTL8365MB switch without interrupt support on the device
+tree of Asus RT-AC88U.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Alvin Šipraga <alsi@bang-olufsen.dk>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++
+ 1 file changed, 77 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
++++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+@@ -93,6 +93,83 @@
+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+ };
+ };
++
++ switch {
++ compatible = "realtek,rtl8365mb";
++ /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
++ mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
++ mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
++ reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
++ realtek,disable-leds;
++ dsa,member = <1 0>;
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++
++ port@0 {
++ reg = <0>;
++ label = "lan5";
++ phy-handle = <ðphy0>;
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan6";
++ phy-handle = <ðphy1>;
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan7";
++ phy-handle = <ðphy2>;
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan8";
++ phy-handle = <ðphy3>;
++ };
++
++ port@6 {
++ reg = <6>;
++ label = "cpu";
++ ethernet = <&sw0_p5>;
++ phy-mode = "rgmii";
++ tx-internal-delay-ps = <2000>;
++ rx-internal-delay-ps = <2000>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ pause;
++ };
++ };
++ };
++
++ mdio {
++ compatible = "realtek,smi-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethphy0: ethernet-phy@0 {
++ reg = <0>;
++ };
++
++ ethphy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++
++ ethphy2: ethernet-phy@2 {
++ reg = <2>;
++ };
++
++ ethphy3: ethernet-phy@3 {
++ reg = <3>;
++ };
++ };
++ };
+ };
+
+ &srab {
--- /dev/null
+From de7880016665afe7fa7d40e1fafa859260d53ba1 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Thu, 28 Oct 2021 09:03:44 +0200
+Subject: [PATCH] ARM: BCM53016: MR32: convert to Broadcom iProc I2C Driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+replaces the bit-banged i2c-gpio provided i2c functionality
+with the hardware in the SoC.
+
+During review of the MR32, Florian Fainelli pointed out that the
+SoC has a real I2C-controller. Furthermore, the connected pins
+(SDA and SCL) would line up perfectly for use. Back then I couldn't
+get it working though and I left it with i2c-gpio (which worked).
+
+Now we know the reason: the interrupt was incorrectly specified.
+(Hence, this patch depends on Florian Fainelli's
+"ARM: dts: BCM5301X: Fix I2C controller interrupt" patch).
+
+Cc: Florian Fainelli <f.fainelli@gmail.com>
+Cc: Rafał Miłecki <zajec5@gmail.com>
+Cc: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 62 ++++++++++------------
+ 1 file changed, 28 insertions(+), 34 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
+@@ -84,40 +84,6 @@
+ max-brightness = <255>;
+ };
+ };
+-
+- i2c {
+- /*
+- * The platform provided I2C does not budge.
+- * This is a replacement until I can figure
+- * out what are the missing bits...
+- */
+-
+- compatible = "i2c-gpio";
+- sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
+- scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
+- i2c-gpio,delay-us = <10>; /* close to 100 kHz */
+- #address-cells = <1>;
+- #size-cells = <0>;
+-
+- current_sense: ina219@45 {
+- compatible = "ti,ina219";
+- reg = <0x45>;
+- shunt-resistor = <60000>; /* = 60 mOhms */
+- };
+-
+- eeprom: eeprom@50 {
+- compatible = "atmel,24c64";
+- reg = <0x50>;
+- pagesize = <32>;
+- read-only;
+- #address-cells = <1>;
+- #size-cells = <1>;
+-
+- mac_address: mac-address@66 {
+- reg = <0x66 0x6>;
+- };
+- };
+- };
+ };
+
+ &uart0 {
+@@ -250,3 +216,31 @@
+ };
+ };
+ };
++
++&i2c0 {
++ status = "okay";
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinmux_i2c>;
++
++ clock-frequency = <100000>;
++
++ current_sense: ina219@45 {
++ compatible = "ti,ina219";
++ reg = <0x45>;
++ shunt-resistor = <60000>; /* = 60 mOhms */
++ };
++
++ eeprom: eeprom@50 {
++ compatible = "atmel,24c64";
++ reg = <0x50>;
++ pagesize = <32>;
++ read-only;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ mac_address: mac-address@66 {
++ reg = <0x66 0x6>;
++ };
++ };
++};
--- /dev/null
+From 31fd9b79dc580301c53a001482755ba7e88c2809 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 29 Oct 2021 18:05:23 +0200
+Subject: [PATCH] ARM: dts: BCM5301X: update CRU block description
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This describes CRU in a way matching documentation and fixes:
+
+arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: cru@100: $nodename:0: 'cru@100' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
+ From schema: /lib/python3.6/site-packages/dtschema/schemas/simple-bus.yaml
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm5301x.dtsi | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -423,14 +423,14 @@
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+- cru@100 {
+- compatible = "simple-bus";
++ cru-bus@100 {
++ compatible = "brcm,ns-cru", "simple-mfd";
+ reg = <0x100 0x1a4>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+- lcpll0: lcpll0@100 {
++ lcpll0: clock-controller@100 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-lcpll0";
+ reg = <0x100 0x14>;
+@@ -439,7 +439,7 @@
+ "sdio", "ddr_phy";
+ };
+
+- genpll: genpll@140 {
++ genpll: clock-controller@140 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-genpll";
+ reg = <0x140 0x24>;
+@@ -450,6 +450,11 @@
+ "sata1", "sata2";
+ };
+
++ syscon@180 {
++ compatible = "brcm,cru-clkset", "syscon";
++ reg = <0x180 0x4>;
++ };
++
+ pinctrl: pin-controller@1c0 {
+ compatible = "brcm,bcm4708-pinmux";
+ reg = <0x1c0 0x24>;
--- /dev/null
+From 1a46061a2a4130a08841941ce6dcaa32be2ce312 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 23 Nov 2021 10:03:33 +0100
+Subject: [PATCH] ARM: dts: BCM5301X: use non-deprecated USB 2.0 PHY binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The new binding covers a single reg and uses syscon to reference shared
+register.
+
+References: 55b9b741712d ("dt-bindings: phy: brcm,ns-usb2-phy: bind just a PHY block")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm5301x.dtsi | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -148,15 +148,6 @@
+ };
+ };
+
+- usb2_phy: usb2-phy@1800c000 {
+- compatible = "brcm,ns-usb2-phy";
+- reg = <0x1800c000 0x1000>;
+- reg-names = "dmu";
+- #phy-cells = <0>;
+- clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
+- clock-names = "phy-ref-clk";
+- };
+-
+ axi@18000000 {
+ compatible = "brcm,bus-axi";
+ reg = <0x18000000 0x1000>;
+@@ -450,7 +441,16 @@
+ "sata1", "sata2";
+ };
+
+- syscon@180 {
++ usb2_phy: phy@164 {
++ compatible = "brcm,ns-usb2-phy";
++ reg = <0x164 0x4>;
++ brcm,syscon-clkset = <&cru_clkset>;
++ clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
++ clock-names = "phy-ref-clk";
++ #phy-cells = <0>;
++ };
++
++ cru_clkset: syscon@180 {
+ compatible = "brcm,cru-clkset", "syscon";
+ reg = <0x180 0x4>;
+ };
--- /dev/null
+From 69c4e53bdd055ecc27761f6971a50c631ff9072e Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Thu, 2 Dec 2021 15:16:27 -0800
+Subject: [PATCH] ARM: dts: NSP: Fixed iProc PCIe MSI sub-node
+
+Rename the msi controller unit name to 'msi' to avoid collisions with
+the 'msi-controller' boolean property.
+
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm-nsp.dtsi
++++ b/arch/arm/boot/dts/bcm-nsp.dtsi
+@@ -587,7 +587,7 @@
+ status = "disabled";
+
+ msi-parent = <&msi0>;
+- msi0: msi-controller {
++ msi0: msi {
+ compatible = "brcm,iproc-msi";
+ msi-controller;
+ interrupt-parent = <&gic>;
+@@ -624,7 +624,7 @@
+ status = "disabled";
+
+ msi-parent = <&msi1>;
+- msi1: msi-controller {
++ msi1: msi {
+ compatible = "brcm,iproc-msi";
+ msi-controller;
+ interrupt-parent = <&gic>;
+@@ -661,7 +661,7 @@
+ status = "disabled";
+
+ msi-parent = <&msi2>;
+- msi2: msi-controller {
++ msi2: msi {
+ compatible = "brcm,iproc-msi";
+ msi-controller;
+ interrupt-parent = <&gic>;
--- /dev/null
+From 9a68c53f875e88edd3403c001ad85f4ac0ed3486 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Tue, 7 Dec 2021 10:19:09 -0800
+Subject: [PATCH] ARM: dts: NSP: Rename SATA unit name
+
+Rename the SATA controller unit name from ahci to sata in preparation
+for adding the Broadcom SATA3 controller YAML binding which will bring
+validation.
+
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/bcm-nsp.dtsi
++++ b/arch/arm/boot/dts/bcm-nsp.dtsi
+@@ -534,7 +534,7 @@
+ };
+ };
+
+- sata: ahci@41000 {
++ sata: sata@41000 {
+ compatible = "brcm,bcm-nsp-ahci";
+ reg-names = "ahci", "top-ctrl";
+ reg = <0x41000 0x1000>, <0x40020 0x1c>;
--- /dev/null
+From 5e33f1c4a7cb914a003a304ab8eef705b17aabb7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 17 Dec 2021 00:03:19 +0800
+Subject: [PATCH] ARM: dts: BCM5301X: correct RX delay and enable flow control
+ on Asus RT-AC88U
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The current 'rx-internal-delay-ps' property value on the Realtek switch
+node, 2000, will be divided by 300, resulting in 6.66, which will be
+rounded to the closest step value, 7. Change it to 2100 to be accurate.
+See ef136837aaf6 ("net: dsa: rtl8365mb: set RGMII RX delay in steps of
+0.3 ns") for reference.
+
+Flow control needs to be enabled on both sides of the internal and
+external switch. It is already enabled on the CPU port of the Realtek
+switch so we also enable it on the external switch port of the Broadcom
+switch as well.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
++++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+@@ -138,7 +138,7 @@
+ ethernet = <&sw0_p5>;
+ phy-mode = "rgmii";
+ tx-internal-delay-ps = <2000>;
+- rx-internal-delay-ps = <2000>;
++ rx-internal-delay-ps = <2100>;
+
+ fixed-link {
+ speed = <1000>;
+@@ -213,6 +213,7 @@
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
++ pause;
+ };
+ };
+
--- /dev/null
+From 8b0c59c622dc4dab970ec63264fb5b152944ac80 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 23 Dec 2021 00:17:17 +0100
+Subject: [PATCH] Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus
+ RT-AC88U"
+
+This reverts commit 3d2d52a0d1835b56f6bd67d268f6c39df0e41692, it caused
+a build regression:
+
+arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:109.4-14: Warning (reg_format): /switch/ports:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
+arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format'
+arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
+arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
+arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
+arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #address-cells value
+arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #size-cells value
+
+Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 --------------------
+ 1 file changed, 77 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
++++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+@@ -93,83 +93,6 @@
+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+-
+- switch {
+- compatible = "realtek,rtl8365mb";
+- /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
+- mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
+- mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
+- reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
+- realtek,disable-leds;
+- dsa,member = <1 0>;
+-
+- ports {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- reg = <0>;
+-
+- port@0 {
+- reg = <0>;
+- label = "lan5";
+- phy-handle = <ðphy0>;
+- };
+-
+- port@1 {
+- reg = <1>;
+- label = "lan6";
+- phy-handle = <ðphy1>;
+- };
+-
+- port@2 {
+- reg = <2>;
+- label = "lan7";
+- phy-handle = <ðphy2>;
+- };
+-
+- port@3 {
+- reg = <3>;
+- label = "lan8";
+- phy-handle = <ðphy3>;
+- };
+-
+- port@6 {
+- reg = <6>;
+- label = "cpu";
+- ethernet = <&sw0_p5>;
+- phy-mode = "rgmii";
+- tx-internal-delay-ps = <2000>;
+- rx-internal-delay-ps = <2100>;
+-
+- fixed-link {
+- speed = <1000>;
+- full-duplex;
+- pause;
+- };
+- };
+- };
+-
+- mdio {
+- compatible = "realtek,smi-mdio";
+- #address-cells = <1>;
+- #size-cells = <0>;
+-
+- ethphy0: ethernet-phy@0 {
+- reg = <0>;
+- };
+-
+- ethphy1: ethernet-phy@1 {
+- reg = <1>;
+- };
+-
+- ethphy2: ethernet-phy@2 {
+- reg = <2>;
+- };
+-
+- ethphy3: ethernet-phy@3 {
+- reg = <3>;
+- };
+- };
+- };
+ };
+
+ &srab {
--- /dev/null
+From 441d531ec9b766f49e01c107a3043235daa4493f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Sun, 2 Jan 2022 23:33:04 +0300
+Subject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Define the Realtek RTL8365MB switch without interrupt support on the device
+tree of Asus RT-AC88U.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Alvin Šipraga <alsi@bang-olufsen.dk>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 76 ++++++++++++++++++++
+ 1 file changed, 76 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
++++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
+@@ -93,6 +93,82 @@
+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
+ };
+ };
++
++ switch {
++ compatible = "realtek,rtl8365mb";
++ /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
++ mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
++ mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
++ reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
++ realtek,disable-leds;
++ dsa,member = <1 0>;
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ label = "lan5";
++ phy-handle = <ðphy0>;
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan6";
++ phy-handle = <ðphy1>;
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan7";
++ phy-handle = <ðphy2>;
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan8";
++ phy-handle = <ðphy3>;
++ };
++
++ port@6 {
++ reg = <6>;
++ label = "cpu";
++ ethernet = <&sw0_p5>;
++ phy-mode = "rgmii";
++ tx-internal-delay-ps = <2000>;
++ rx-internal-delay-ps = <2100>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ pause;
++ };
++ };
++ };
++
++ mdio {
++ compatible = "realtek,smi-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethphy0: ethernet-phy@0 {
++ reg = <0>;
++ };
++
++ ethphy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++
++ ethphy2: ethernet-phy@2 {
++ reg = <2>;
++ };
++
++ ethphy3: ethernet-phy@3 {
++ reg = <3>;
++ };
++ };
++ };
+ };
+
+ &srab {
--- /dev/null
+From 66848aff05f669e95795b5f3a163f4762781333e Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Wed, 23 Feb 2022 23:50:39 +0000
+Subject: [PATCH] ARM: dts: NSP: MX6X: get mac-address from eeprom
+
+The MAC address on the MX64/MX65 series is located on the AT24 EEPROM.
+This is the same as other Meraki devices such as the MR32 [1].
+
+[1] https://lore.kernel.org/linux-arm-kernel/fa8271d02ef74a687f365cebe5c55ec846963ab7.1631986106.git.chunkeey@gmail.com/
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
++++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
+@@ -39,6 +39,8 @@
+
+ &amac2 {
+ status = "okay";
++ nvmem-cells = <&mac_address>;
++ nvmem-cell-names = "mac-address";
+ };
+
+ &ehci0 {
+@@ -53,6 +55,12 @@
+ reg = <0x50>;
+ pagesize = <32>;
+ read-only;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ mac_address: mac-address@66 {
++ reg = <0x66 0x6>;
++ };
+ };
+ };
+
--- /dev/null
+From 482c85c7fc95c572d368b2214b9e9d2c4a2e5789 Mon Sep 17 00:00:00 2001
+From: Matthew Hagan <mnhagan88@gmail.com>
+Date: Wed, 23 Feb 2022 23:50:40 +0000
+Subject: [PATCH] ARM: dts: NSP: MX6X: correct LED function types
+
+Currently, the amber LED will remain always on. This is due to a
+misinterpretation of the LED sub-node properties, where-by "default-state"
+was used to indicate the initial state when powering on the device. When in
+use, however, this resulted in the amber LED always being on. Instead change
+this to only indicate a fault state.
+
+Assign LED_FUNCTION_POWER to the green PWM LED.
+
+These changes bring the MX64/65 in line with the MR32's devicetree.
+
+Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 3 +--
+ arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi | 3 +--
+ arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 2 +-
+ 3 files changed, 3 insertions(+), 5 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
++++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
+@@ -57,10 +57,9 @@
+
+ led-4 {
+ /* amber:power */
+- function = LED_FUNCTION_POWER;
++ function = LED_FUNCTION_FAULT;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
+- default-state = "on";
+ };
+
+ led-5 {
+--- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
++++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
+@@ -106,10 +106,9 @@
+
+ led-a {
+ /* amber:power */
+- function = LED_FUNCTION_POWER;
++ function = LED_FUNCTION_FAULT;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
+- default-state = "on";
+ };
+
+ led-b {
+--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
++++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
+@@ -22,7 +22,7 @@
+ };
+
+ led-2 {
+- function = LED_FUNCTION_INDICATOR;
++ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm 2 50000>;
+ max-brightness = <255>;
--- /dev/null
+From c8442f0fb09ca3d842b9b23d1d0650f649fd10f8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 28 Feb 2022 10:52:07 +0100
+Subject: [PATCH] ARM: dts: BCM5301X: Add Ethernet MAC address to Luxul
+ XWR-3150
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Luxul XWR-3150 stores MAC as NVRAM variable. Add NVMEM cell for it and
+reference it in the Ethernet interface node.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
++++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
+@@ -25,6 +25,9 @@
+ nvram@1eff0000 {
+ compatible = "brcm,nvram";
+ reg = <0x1eff0000 0x10000>;
++
++ et0macaddr: et0macaddr {
++ };
+ };
+
+ leds {
+@@ -72,6 +75,11 @@
+ };
+ };
+
++&gmac0 {
++ nvmem-cells = <&et0macaddr>;
++ nvmem-cell-names = "mac-address";
++};
++
+ &usb3 {
+ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
+ };
--- /dev/null
+From d3bc6269e21fc474763708e79c7a118740befb94 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 26 Oct 2021 11:37:16 +0200
+Subject: [PATCH] phy: bcm-ns-usb2: support updated DT binding with PHY reg
+ space
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Updated DT binding maps just a PHY's register space instead of the whole
+DMU block. Accessing a common CRU reg is handled using syscon &
+regmap.
+
+The old binding has been deprecated and remains supported as a fallback
+method.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20211026093716.5567-1-zajec5@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/broadcom/phy-bcm-ns-usb2.c | 52 +++++++++++++++++++++-----
+ 1 file changed, 43 insertions(+), 9 deletions(-)
+
+--- a/drivers/phy/broadcom/phy-bcm-ns-usb2.c
++++ b/drivers/phy/broadcom/phy-bcm-ns-usb2.c
+@@ -9,17 +9,23 @@
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/err.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
+ #include <linux/of_platform.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
++#include <linux/regmap.h>
+ #include <linux/slab.h>
+
+ struct bcm_ns_usb2 {
+ struct device *dev;
+ struct clk *ref_clk;
+ struct phy *phy;
++ struct regmap *clkset;
++ void __iomem *base;
++
++ /* Deprecated binding */
+ void __iomem *dmu;
+ };
+
+@@ -27,7 +33,6 @@ static int bcm_ns_usb2_phy_init(struct p
+ {
+ struct bcm_ns_usb2 *usb2 = phy_get_drvdata(phy);
+ struct device *dev = usb2->dev;
+- void __iomem *dmu = usb2->dmu;
+ u32 ref_clk_rate, usb2ctl, usb_pll_ndiv, usb_pll_pdiv;
+ int err = 0;
+
+@@ -44,7 +49,10 @@ static int bcm_ns_usb2_phy_init(struct p
+ goto err_clk_off;
+ }
+
+- usb2ctl = readl(dmu + BCMA_DMU_CRU_USB2_CONTROL);
++ if (usb2->base)
++ usb2ctl = readl(usb2->base);
++ else
++ usb2ctl = readl(usb2->dmu + BCMA_DMU_CRU_USB2_CONTROL);
+
+ if (usb2ctl & BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK) {
+ usb_pll_pdiv = usb2ctl;
+@@ -58,15 +66,24 @@ static int bcm_ns_usb2_phy_init(struct p
+ usb_pll_ndiv = (1920000000 * usb_pll_pdiv) / ref_clk_rate;
+
+ /* Unlock DMU PLL settings with some magic value */
+- writel(0x0000ea68, dmu + BCMA_DMU_CRU_CLKSET_KEY);
++ if (usb2->clkset)
++ regmap_write(usb2->clkset, 0, 0x0000ea68);
++ else
++ writel(0x0000ea68, usb2->dmu + BCMA_DMU_CRU_CLKSET_KEY);
+
+ /* Write USB 2.0 PLL control setting */
+ usb2ctl &= ~BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK;
+ usb2ctl |= usb_pll_ndiv << BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT;
+- writel(usb2ctl, dmu + BCMA_DMU_CRU_USB2_CONTROL);
++ if (usb2->base)
++ writel(usb2ctl, usb2->base);
++ else
++ writel(usb2ctl, usb2->dmu + BCMA_DMU_CRU_USB2_CONTROL);
+
+ /* Lock DMU PLL settings */
+- writel(0x00000000, dmu + BCMA_DMU_CRU_CLKSET_KEY);
++ if (usb2->clkset)
++ regmap_write(usb2->clkset, 0, 0x00000000);
++ else
++ writel(0x00000000, usb2->dmu + BCMA_DMU_CRU_CLKSET_KEY);
+
+ err_clk_off:
+ clk_disable_unprepare(usb2->ref_clk);
+@@ -90,10 +107,27 @@ static int bcm_ns_usb2_probe(struct plat
+ return -ENOMEM;
+ usb2->dev = dev;
+
+- usb2->dmu = devm_platform_ioremap_resource_byname(pdev, "dmu");
+- if (IS_ERR(usb2->dmu)) {
+- dev_err(dev, "Failed to map DMU regs\n");
+- return PTR_ERR(usb2->dmu);
++ if (of_find_property(dev->of_node, "brcm,syscon-clkset", NULL)) {
++ usb2->base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(usb2->base)) {
++ dev_err(dev, "Failed to map control reg\n");
++ return PTR_ERR(usb2->base);
++ }
++
++ usb2->clkset = syscon_regmap_lookup_by_phandle(dev->of_node,
++ "brcm,syscon-clkset");
++ if (IS_ERR(usb2->clkset)) {
++ dev_err(dev, "Failed to lookup clkset regmap\n");
++ return PTR_ERR(usb2->clkset);
++ }
++ } else {
++ usb2->dmu = devm_platform_ioremap_resource_byname(pdev, "dmu");
++ if (IS_ERR(usb2->dmu)) {
++ dev_err(dev, "Failed to map DMU regs\n");
++ return PTR_ERR(usb2->dmu);
++ }
++
++ dev_warn(dev, "using deprecated DT binding\n");
+ }
+
+ usb2->ref_clk = devm_clk_get(dev, "phy-ref-clk");
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 13 Apr 2021 18:25:20 +0200
+Subject: [PATCH] mtd: parsers: trx: parse "firmware" MTD partitions only
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Parsing every partition with "compatible" set to "brcm,trx" results in
+parsing both: firmware partition and failsafe partition on devices that
+implement failsafe booting. This affects e.g. Linksys EA9500 which has:
+
+partition@200000 {
+ reg = <0x0200000 0x01d00000>;
+ compatible = "linksys,ns-firmware", "brcm,trx";
+};
+
+partition@1f00000 {
+ reg = <0x01f00000 0x01d00000>;
+ compatible = "linksys,ns-firmware", "brcm,trx";
+};
+
+Check for MTD partition name "firmware" before parsing. Recently added
+ofpart_linksys_ns.c creates "firmware" and "failsafe" depending on
+bootloader setup.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/mtd/parsers/parser_trx.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/mtd/parsers/parser_trx.c
++++ b/drivers/mtd/parsers/parser_trx.c
+@@ -92,6 +92,10 @@ static int parser_trx_parse(struct mtd_i
+ if (err != 0 && err != -EINVAL)
+ pr_err("failed to parse \"brcm,trx-magic\" DT attribute, using default: %d\n", err);
+
++ /* Don't parse any failsafe / backup partitions */
++ if (strcmp(mtd->name, "firmware"))
++ return -EINVAL;
++
+ parts = kcalloc(TRX_PARSER_MAX_PARTS, sizeof(struct mtd_partition),
+ GFP_KERNEL);
+ if (!parts)
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sat, 1 Oct 2016 22:54:48 +0200
+Subject: [PATCH] usb: xhci: add support for performing fake doorbell
+
+Broadcom's Northstar XHCI controllers seem to need a special start
+procedure to work correctly. There isn't any official documentation of
+this, the problem is that controller doesn't detect any connected
+devices with default setup. Moreover connecting USB device to controller
+that doesn't run properly can cause SoC's watchdog issues.
+
+A workaround that was successfully tested on multiple devices is to
+perform a fake doorbell. This patch adds code for doing this and enables
+it on BCM4708 family.
+---
+ drivers/usb/host/xhci-plat.c | 6 +++++
+ drivers/usb/host/xhci.c | 63 +++++++++++++++++++++++++++++++++++++++++---
+ drivers/usb/host/xhci.h | 1 +
+ 3 files changed, 67 insertions(+), 3 deletions(-)
+
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -77,6 +77,8 @@ static int xhci_priv_resume_quirk(struct
+ static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
+ {
+ struct xhci_plat_priv *priv = xhci_to_priv(xhci);
++ struct platform_device*pdev = to_platform_device(dev);
++ struct device_node *node = pdev->dev.of_node;
+
+ /*
+ * As of now platform drivers don't provide MSI support so we ensure
+@@ -84,6 +86,9 @@ static void xhci_plat_quirks(struct devi
+ * dev struct in order to setup MSI
+ */
+ xhci->quirks |= XHCI_PLAT | priv->quirks;
++
++ if (node && of_machine_is_compatible("brcm,bcm4708"))
++ xhci->quirks |= XHCI_FAKE_DOORBELL;
+ }
+
+ /* called during probe() after chip reset completes */
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -155,6 +155,49 @@ int xhci_start(struct xhci_hcd *xhci)
+ return ret;
+ }
+
++/**
++ * xhci_fake_doorbell - Perform a fake doorbell on a specified slot
++ *
++ * Some controllers require a fake doorbell to start correctly. Without that
++ * they simply don't detect any devices.
++ */
++static int xhci_fake_doorbell(struct xhci_hcd *xhci, int slot_id)
++{
++ u32 temp;
++
++ /* Alloc a virt device for that slot */
++ if (!xhci_alloc_virt_device(xhci, slot_id, NULL, GFP_NOIO)) {
++ xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
++ return -ENOMEM;
++ }
++
++ /* Ring fake doorbell for slot_id ep 0 */
++ xhci_ring_ep_doorbell(xhci, slot_id, 0, 0);
++ usleep_range(1000, 1500);
++
++ /* Read the status to check if HSE is set or not */
++ temp = readl(&xhci->op_regs->status);
++
++ /* Clear HSE if set */
++ if (temp & STS_FATAL) {
++ xhci_dbg(xhci, "HSE problem detected, status: 0x%08x\n", temp);
++ temp &= ~0x1fff;
++ temp |= STS_FATAL;
++ writel(temp, &xhci->op_regs->status);
++ usleep_range(1000, 1500);
++ readl(&xhci->op_regs->status);
++ }
++
++ /* Free virt device */
++ xhci_free_virt_device(xhci, slot_id);
++
++ /* We're done if controller is already running */
++ if (readl(&xhci->op_regs->command) & CMD_RUN)
++ return 0;
++
++ return xhci_start(xhci);
++}
++
+ /*
+ * Reset a halted HC.
+ *
+@@ -607,10 +650,20 @@ static int xhci_init(struct usb_hcd *hcd
+
+ static int xhci_run_finished(struct xhci_hcd *xhci)
+ {
+- if (xhci_start(xhci)) {
+- xhci_halt(xhci);
+- return -ENODEV;
++ int err;
++
++ err = xhci_start(xhci);
++ if (err) {
++ err = -ENODEV;
++ goto err_halt;
+ }
++
++ if (xhci->quirks & XHCI_FAKE_DOORBELL) {
++ err = xhci_fake_doorbell(xhci, 1);
++ if (err)
++ goto err_halt;
++ }
++
+ xhci->shared_hcd->state = HC_STATE_RUNNING;
+ xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
+
+@@ -620,6 +673,10 @@ static int xhci_run_finished(struct xhci
+ xhci_dbg_trace(xhci, trace_xhci_dbg_init,
+ "Finished xhci_run for USB3 roothub");
+ return 0;
++
++err_halt:
++ xhci_halt(xhci);
++ return err;
+ }
+
+ /*
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -1900,6 +1900,7 @@ struct xhci_hcd {
+ #define XHCI_NO_SOFT_RETRY BIT_ULL(40)
+ #define XHCI_BROKEN_D3COLD BIT_ULL(41)
+ #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
++#define XHCI_FAKE_DOORBELL BIT_ULL(44)
+
+ unsigned int num_active_eps;
+ unsigned int limit_active_eps;
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 24 Sep 2014 22:14:07 +0200
+Subject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache during decompression
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Broadcom devices have broken CFE (bootloader) that leaves hardware in an
+invalid state. It causes problems with booting Linux. On Northstar
+devices kernel was randomly hanging in ~25% of tries during early init.
+Hangs used to happen at random places in the start_kernel. On BCM53573
+kernel doesn't even seem to start booting.
+
+To workaround this problem we need to do following very early:
+1) Clear 2 following bits in the SCTLR register:
+#define CR_M (1 << 0) /* MMU enable */
+#define CR_C (1 << 2) /* Dcache enable */
+2) Flush the whole D-cache
+3) Disable L2 cache
+
+Unfortunately this patch is not upstreamable as it does above things
+unconditionally. We can't check if we are running on Broadcom platform
+in any safe way and doing such hacks with ARCH_MULTI_V7 is unacceptable
+as it could break other devices support.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/arch/arm/boot/compressed/Makefile
++++ b/arch/arm/boot/compressed/Makefile
+@@ -36,6 +36,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
+ OBJS += ll_char_wr.o font.o
+ endif
+
++ifeq ($(CONFIG_ARCH_BCM_5301X),y)
++OBJS += head-bcm_5301x-mpcore.o
++OBJS += cache-v7-min.o
++endif
++
+ ifeq ($(CONFIG_ARCH_SA1100),y)
+ OBJS += head-sa1100.o
+ endif
+--- /dev/null
++++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
+@@ -0,0 +1,37 @@
++/*
++ *
++ * Platform specific tweaks. This is merged into head.S by the linker.
++ *
++ */
++
++#include <linux/linkage.h>
++#include <asm/assembler.h>
++#include <asm/cp15.h>
++
++ .section ".start", "ax"
++
++/*
++ * This code section is spliced into the head code by the linker
++ */
++
++__plat_uncompress_start:
++
++ @ Preserve r8/r7 i.e. kernel entry values
++ mov r12, r8
++
++ @ Clear MMU enable and Dcache enable bits
++ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
++ bic r0, #CR_C|CR_M
++ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR
++ nop
++
++ @ Call the cache invalidation routine
++ bl v7_flush_dcache_all
++ nop
++ mov r0,#0
++ ldr r3, =0x19022000 @ L2 cache controller, control reg
++ str r0, [r3, #0x100] @ Disable L2 cache
++ nop
++
++ @ Restore
++ mov r8, r12
+--- a/arch/arm/boot/compressed/cache-v7-min.S
++++ b/arch/arm/boot/compressed/cache-v7-min.S
+@@ -12,6 +12,7 @@
+
+ #include <linux/linkage.h>
+ #include <linux/init.h>
++#include <asm/assembler.h>
+
+ __INIT
+
+@@ -63,7 +64,7 @@ loop2:
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+- mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
++ mcr p15, 0, r11, c7, c6, 2 @ clean & invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge loop2
+ subs r4, r4, #1 @ decrement the way
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Subject: [PATCH] ARM: dts: BCM5301X: Specify switch ports for remaining
+ devices
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
+@@ -93,3 +93,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
+@@ -83,3 +83,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan1";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan3";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan4";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+@@ -149,3 +149,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
++++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
+@@ -46,3 +46,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
++++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
+@@ -42,3 +42,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
+@@ -86,3 +86,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
+@@ -77,3 +77,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan1";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan3";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan4";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
+@@ -68,6 +68,38 @@
+ status = "okay";
+ };
+
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan1";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan3";
++ };
++
++ port@7 {
++ reg = <7>;
++ label = "cpu";
++ ethernet = <&gmac1>;
++ };
++ };
++};
++
+ &nandcs {
+ partitions {
+ compatible = "fixed-partitions";
+--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
+@@ -132,3 +132,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
++++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
+@@ -49,3 +49,45 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@8 {
++ reg = <8>;
++ label = "cpu";
++ ethernet = <&gmac2>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
+@@ -106,3 +106,40 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan1";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan3";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan4";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
++++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+@@ -94,3 +94,45 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan1";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan3";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan4";
++ };
++
++ port@8 {
++ reg = <8>;
++ label = "cpu";
++ ethernet = <&gmac2>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ };
++ };
++};
+--- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
++++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
+@@ -38,6 +38,38 @@
+ status = "okay";
+ };
+
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "wan";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
++
+ &nandcs {
+ partitions {
+ compatible = "fixed-partitions";
+--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
++++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
+@@ -91,6 +91,43 @@
+ };
+ };
+
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan1";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan3";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan4";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
++
+ &spi_nor {
+ status = "okay";
+
+--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
++++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
+@@ -102,6 +102,43 @@
+ vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
+ };
+
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan1";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan2";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan3";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan4";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
++
+ &spi_nor {
+ status = "okay";
+
+--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
+@@ -107,3 +107,41 @@
+ &usb3_phy {
+ status = "okay";
+ };
++
++&srab {
++ status = "okay";
++
++ ports {
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "wan";
++ };
++
++ port@5 {
++ reg = <5>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ };
++ };
++};
++
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Subject: [PATCH] ARM: BCM5301X: Add DT for Netgear R7900
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -115,6 +115,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
+ bcm4709-buffalo-wxr-1900dhp.dtb \
+ bcm4709-linksys-ea9200.dtb \
+ bcm4709-netgear-r7000.dtb \
++ bcm4709-netgear-r7900.dtb \
+ bcm4709-netgear-r8000.dtb \
+ bcm4709-tplink-archer-c9-v1.dtb \
+ bcm47094-asus-rt-ac88u.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/bcm4709-netgear-r7900.dts
+@@ -0,0 +1,42 @@
++/*
++ * Broadcom BCM470X / BCM5301X ARM platform code.
++ * DTS for Netgear R7900
++ *
++ * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++/dts-v1/;
++
++#include "bcm4709.dtsi"
++#include "bcm5301x-nand-cs0-bch8.dtsi"
++
++/ {
++ compatible = "netgear,r7900", "brcm,bcm4709", "brcm,bcm4708";
++ model = "Netgear R7900";
++
++ chosen {
++ bootargs = "console=ttyS0,115200";
++ };
++
++ memory {
++ reg = <0x00000000 0x08000000
++ 0x88000000 0x08000000>;
++ };
++
++ axi@18000000 {
++ usb3@23000 {
++ reg = <0x00023000 0x1000>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
++ };
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 23 Nov 2021 13:13:05 +0100
+Subject: [PATCH] ARM: dts: BCM5301X: Switch back to old clock nodes names
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+First of all using the same node name prefix resulted in trying to
+register 2 clocks under the same "clock-controller" name:
+
+[ 0.000000] __clk_core_init: clk clock-controller already initialized
+[ 0.000000] ------------[ cut here ]------------
+[ 0.000000] WARNING: CPU: 0 PID: 0 at drivers/clk/bcm/clk-iproc-pll.c:802 iproc_pll_clk_setup+0x4c8/0x4f4
+[ 0.000000] Modules linked in:
+[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.80 #0
+[ 0.000000] Hardware name: BCM5301X
+[ 0.000000] [<c0108410>] (unwind_backtrace) from [<c0104bc4>] (show_stack+0x10/0x14)
+[ 0.000000] [<c0104bc4>] (show_stack) from [<c03dca28>] (dump_stack+0x94/0xa8)
+[ 0.000000] [<c03dca28>] (dump_stack) from [<c0118440>] (__warn+0xb8/0x114)
+[ 0.000000] [<c0118440>] (__warn) from [<c0118504>] (warn_slowpath_fmt+0x68/0x78)
+[ 0.000000] [<c0118504>] (warn_slowpath_fmt) from [<c043281c>] (iproc_pll_clk_setup+0x4c8/0x4f4)
+[ 0.000000] [<c043281c>] (iproc_pll_clk_setup) from [<c0818c04>] (nsp_genpll_clk_init+0x30/0x38)
+[ 0.000000] [<c0818c04>] (nsp_genpll_clk_init) from [<c0818634>] (of_clk_init+0x118/0x1f8)
+[ 0.000000] [<c0818634>] (of_clk_init) from [<c08039b0>] (time_init+0x24/0x30)
+[ 0.000000] [<c08039b0>] (time_init) from [<c0800d14>] (start_kernel+0x398/0x50c)
+[ 0.000000] [<c0800d14>] (start_kernel) from [<00000000>] (0x0)
+[ 0.000000] ---[ end trace fe236bfe9559ee50 ]---
+
+Secondly using any other names than "lcpll0" and "genpll" breaks output
+clocks:
+
+$ cat /sys/kernel/debug/clk/usbclk/clk_rate
+0
+
+For some reason iproc_clk_recalc_rate() gets called with "parent_rate"
+argument 0 whenever clocks aren't named "lcpll0" and "genpll".
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ arch/arm/boot/dts/bcm5301x.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -421,7 +421,7 @@
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+- lcpll0: clock-controller@100 {
++ lcpll0: lcpll0@100 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-lcpll0";
+ reg = <0x100 0x14>;
+@@ -430,7 +430,7 @@
+ "sdio", "ddr_phy";
+ };
+
+- genpll: clock-controller@140 {
++ genpll: genpll@140 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-genpll";
+ reg = <0x140 0x24>;
--- /dev/null
+From 7166207bd1d8c46d09d640d46afc685df9bb9083 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 22 Nov 2018 09:21:49 +0100
+Subject: [PATCH] ARM: dts: BCM5301X: Describe partition formats
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's needed by OpenWrt for custom partitioning.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
++++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+@@ -35,6 +35,7 @@
+ partition@0 {
+ label = "firmware";
+ reg = <0x00000000 0x08000000>;
++ compatible = "seama";
+ };
+ };
+ };
--- /dev/null
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Thu, 7 Jun 2018 19:29:12 +0200
+Subject: bcm53xx: add LED status label alias for Meraki MR32
+
+add an led-status alias label. This is used by OpenWrt's LED
+DTS lookup function to identifiy the indicator LED
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+
+--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
++++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
+@@ -27,6 +27,7 @@
+
+ aliases {
+ serial1 = &uart2;
++ led-status = &led_status;
+ };
+
+ leds {
+@@ -68,7 +69,7 @@
+ max-brightness = <255>;
+ };
+
+- green {
++ led_status: green {
+ /* SYS-LED 1 - Tricolor */
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
--- /dev/null
+From 2a2af518266a29323cf30c3f9ba9ef2ceb1dd84b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Thu, 16 Oct 2014 20:52:16 +0200
+Subject: [PATCH] UBI: Detect EOF mark and erase all remaining blocks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+ drivers/mtd/ubi/attach.c | 5 +++++
+ drivers/mtd/ubi/io.c | 4 ++++
+ drivers/mtd/ubi/ubi.h | 1 +
+ 3 files changed, 10 insertions(+)
+
+--- a/drivers/mtd/ubi/attach.c
++++ b/drivers/mtd/ubi/attach.c
+@@ -82,6 +82,9 @@ static int self_check_ai(struct ubi_devi
+ #define AV_ADD BIT(1)
+ #define AV_FIND_OR_ADD (AV_FIND | AV_ADD)
+
++/* Set on finding block with 0xdeadc0de, indicates erasing all blocks behind */
++bool erase_all_next;
++
+ /**
+ * find_or_add_av - internal function to find a volume, add a volume or do
+ * both (find and add if missing).
+@@ -1580,6 +1583,8 @@ int ubi_attach(struct ubi_device *ubi, i
+ if (!ai)
+ return -ENOMEM;
+
++ erase_all_next = false;
++
+ #ifdef CONFIG_MTD_UBI_FASTMAP
+ /* On small flash devices we disable fastmap in any case. */
+ if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) {
+--- a/drivers/mtd/ubi/io.c
++++ b/drivers/mtd/ubi/io.c
+@@ -717,6 +717,10 @@ int ubi_io_read_ec_hdr(struct ubi_device
+ }
+
+ magic = be32_to_cpu(ec_hdr->magic);
++ if (magic == 0xdeadc0de)
++ erase_all_next = true;
++ if (erase_all_next)
++ return read_err ? UBI_IO_FF_BITFLIPS : UBI_IO_FF;
+ if (magic != UBI_EC_HDR_MAGIC) {
+ if (mtd_is_eccerr(read_err))
+ return UBI_IO_BAD_HDR_EBADMSG;
+--- a/drivers/mtd/ubi/ubi.h
++++ b/drivers/mtd/ubi/ubi.h
+@@ -822,6 +822,7 @@ extern struct mutex ubi_devices_mutex;
+ extern struct blocking_notifier_head ubi_notifiers;
+
+ /* attach.c */
++extern bool erase_all_next;
+ struct ubi_ainf_peb *ubi_alloc_aeb(struct ubi_attach_info *ai, int pnum,
+ int ec);
+ void ubi_free_aeb(struct ubi_attach_info *ai, struct ubi_ainf_peb *aeb);
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Mar 2021 08:24:44 +0100
+Subject: [PATCH] firmware: bcm47xx_nvram: support init from IO memory
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/firmware/broadcom/bcm47xx_nvram.c | 17 +++++++++++++++++
+ include/linux/bcm47xx_nvram.h | 6 ++++++
+ 2 files changed, 23 insertions(+)
+
+--- a/drivers/firmware/broadcom/bcm47xx_nvram.c
++++ b/drivers/firmware/broadcom/bcm47xx_nvram.c
+@@ -110,6 +110,23 @@ found:
+ return 0;
+ }
+
++int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size)
++{
++ if (nvram_len) {
++ pr_warn("nvram already initialized\n");
++ return -EEXIST;
++ }
++
++ if (!bcm47xx_nvram_is_valid(nvram_start)) {
++ pr_err("No valid NVRAM found\n");
++ return -ENOENT;
++ }
++
++ bcm47xx_nvram_copy(nvram_start, res_size);
++
++ return 0;
++}
++
+ /*
+ * On bcm47xx we need access to the NVRAM very early, so we can't use mtd
+ * subsystem to access flash. We can't even use platform device / driver to
+--- a/include/linux/bcm47xx_nvram.h
++++ b/include/linux/bcm47xx_nvram.h
+@@ -11,6 +11,7 @@
+ #include <linux/vmalloc.h>
+
+ #ifdef CONFIG_BCM47XX_NVRAM
++int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size);
+ int bcm47xx_nvram_init_from_mem(u32 base, u32 lim);
+ int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);
+ int bcm47xx_nvram_gpio_pin(const char *name);
+@@ -20,6 +21,11 @@ static inline void bcm47xx_nvram_release
+ vfree(nvram);
+ };
+ #else
++static inline int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start,
++ size_t res_size)
++{
++ return -ENOTSUPP;
++}
+ static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim)
+ {
+ return -ENOTSUPP;
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 11 Mar 2021 08:26:14 +0100
+Subject: [PATCH] nvmem: brcm_nvram: provide NVMEM content to the NVRAM driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/nvmem/brcm_nvram.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/nvmem/brcm_nvram.c
++++ b/drivers/nvmem/brcm_nvram.c
+@@ -3,6 +3,7 @@
+ * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>
+ */
+
++#include <linux/bcm47xx_nvram.h>
+ #include <linux/io.h>
+ #include <linux/mod_devicetable.h>
+ #include <linux/module.h>
+@@ -46,6 +47,8 @@ static int brcm_nvram_probe(struct platf
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
++ bcm47xx_nvram_init_from_iomem(priv->base, resource_size(res));
++
+ config.dev = dev;
+ config.priv = priv;
+ config.size = resource_size(res);
--- /dev/null
+From 6f1c62440eb6846cb8045d7a5480ec7bbe47c96f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 15 Aug 2016 10:30:41 +0200
+Subject: [PATCH] BCM53573 minor hacks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/arch/arm/boot/dts/bcm53573.dtsi
++++ b/arch/arm/boot/dts/bcm53573.dtsi
+@@ -54,6 +54,7 @@
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
++ clocks = <&ilp>;
+ };
+
+ clocks {
+--- a/drivers/bcma/main.c
++++ b/drivers/bcma/main.c
+@@ -330,14 +330,6 @@ static int bcma_register_devices(struct
+ }
+ #endif
+
+-#ifdef CONFIG_BCMA_SFLASH
+- if (bus->drv_cc.sflash.present) {
+- err = platform_device_register(&bcma_sflash_dev);
+- if (err)
+- bcma_err(bus, "Error registering serial flash\n");
+- }
+-#endif
+-
+ #ifdef CONFIG_BCMA_NFLASH
+ if (bus->drv_cc.nflash.present) {
+ err = platform_device_register(&bcma_nflash_dev);
+@@ -415,6 +407,14 @@ int bcma_bus_register(struct bcma_bus *b
+ bcma_register_core(bus, core);
+ }
+
++#ifdef CONFIG_BCMA_SFLASH
++ if (bus->drv_cc.sflash.present) {
++ err = platform_device_register(&bcma_sflash_dev);
++ if (err)
++ bcma_err(bus, "Error registering serial flash\n");
++ }
++#endif
++
+ /* Try to get SPROM */
+ err = bcma_sprom_get(bus);
+ if (err == -ENOENT) {
+--- a/drivers/clocksource/arm_arch_timer.c
++++ b/drivers/clocksource/arm_arch_timer.c
+@@ -14,6 +14,7 @@
+ #include <linux/smp.h>
+ #include <linux/cpu.h>
+ #include <linux/cpu_pm.h>
++#include <linux/clk.h>
+ #include <linux/clockchips.h>
+ #include <linux/clocksource.h>
+ #include <linux/clocksource_ids.h>
+@@ -946,6 +947,16 @@ static void __init arch_timer_of_configu
+ if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
+ arch_timer_rate = rate;
+
++ /* Get clk rate through clk driver if present */
++ if (!arch_timer_rate) {
++ struct clk *clk = of_clk_get(np, 0);
++
++ if (!IS_ERR(clk)) {
++ if (!clk_prepare_enable(clk))
++ arch_timer_rate = clk_get_rate(clk);
++ }
++ }
++
+ /* Check the timer frequency. */
+ if (validate_timer_rate())
+ pr_warn("frequency not available\n");
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