package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch

   1 From 37bcf4d1acb5f7ce93fa0bd59dc313a79004ae34 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 31 Aug 2022 19:00:25 +0800
   4 Subject: [PATCH 04/32] board: mediatek: add MT7981 reference boards
   5
   6 This patch adds general board files based on MT7981 SoCs.
   7
   8 MT7981 uses one mmc controller for booting from both SD and eMMC, and the
   9 pins of mmc controller are also shared with spi controller.
  10 So three configs are need for these boot types:
  11
  12 1. mt7981_rfb_defconfig - SPI-NOR and SPI-NAND
  13 2. mt7981_emmc_rfb_defconfig - eMMC only
  14 3. mt7981_sd_rfb_defconfig - SD only
  15
  16 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  17 ---
  18  arch/arm/dts/Makefile              |   3 +
  19  arch/arm/dts/mt7981-emmc-rfb.dts   | 139 +++++++++++++++++++++++
  20  arch/arm/dts/mt7981-rfb.dts        | 173 +++++++++++++++++++++++++++++
  21  arch/arm/dts/mt7981-sd-rfb.dts     | 139 +++++++++++++++++++++++
  22  board/mediatek/mt7981/MAINTAINERS  |  10 ++
  23  board/mediatek/mt7981/Makefile     |   3 +
  24  board/mediatek/mt7981/mt7981_rfb.c |  10 ++
  25  configs/mt7981_emmc_rfb_defconfig  |  64 +++++++++++
  26  configs/mt7981_rfb_defconfig       |  69 ++++++++++++
  27  configs/mt7981_sd_rfb_defconfig    |  64 +++++++++++
  28  include/configs/mt7981.h           |  26 +++++
  29  11 files changed, 700 insertions(+)
  30  create mode 100644 arch/arm/dts/mt7981-emmc-rfb.dts
  31  create mode 100644 arch/arm/dts/mt7981-rfb.dts
  32  create mode 100644 arch/arm/dts/mt7981-sd-rfb.dts
  33  create mode 100644 board/mediatek/mt7981/MAINTAINERS
  34  create mode 100644 board/mediatek/mt7981/Makefile
  35  create mode 100644 board/mediatek/mt7981/mt7981_rfb.c
  36  create mode 100644 configs/mt7981_emmc_rfb_defconfig
  37  create mode 100644 configs/mt7981_rfb_defconfig
  38  create mode 100644 configs/mt7981_sd_rfb_defconfig
  39  create mode 100644 include/configs/mt7981.h
  40
  41 --- a/arch/arm/dts/Makefile
  42 +++ b/arch/arm/dts/Makefile
  43 @@ -1233,6 +1233,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  44         mt7622-bananapi-bpi-r64.dtb \
  45         mt7623n-bananapi-bpi-r2.dtb \
  46         mt7629-rfb.dtb \
  47 +       mt7981-rfb.dtb \
  48 +       mt7981-emmc-rfb.dtb \
  49 +       mt7981-sd-rfb.dtb \
  50         mt7986a-rfb.dtb \
  51         mt7986b-rfb.dtb \
  52         mt7986a-sd-rfb.dtb \
  53 --- /dev/null
  54 +++ b/arch/arm/dts/mt7981-emmc-rfb.dts
  55 @@ -0,0 +1,139 @@
  56 +// SPDX-License-Identifier: GPL-2.0
  57 +/*
  58 + * Copyright (c) 2022 MediaTek Inc.
  59 + * Author: Sam Shih <sam.shih@mediatek.com>
  60 + */
  61 +
  62 +/dts-v1/;
  63 +#include "mt7981.dtsi"
  64 +#include <dt-bindings/gpio/gpio.h>
  65 +
  66 +/ {
  67 +       #address-cells = <1>;
  68 +       #size-cells = <1>;
  69 +       model = "mt7981-rfb";
  70 +       compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
  71 +       chosen {
  72 +               stdout-path = &uart0;
  73 +               tick-timer = &timer0;
  74 +       };
  75 +
  76 +       reg_3p3v: regulator-3p3v {
  77 +                 compatible = "regulator-fixed";
  78 +                 regulator-name = "fixed-3.3V";
  79 +                 regulator-min-microvolt = <3300000>;
  80 +                 regulator-max-microvolt = <3300000>;
  81 +                 regulator-boot-on;
  82 +                 regulator-always-on;
  83 +       };
  84 +};
  85 +
  86 +&uart0 {
  87 +       status = "okay";
  88 +};
  89 +
  90 +&uart1 {
  91 +       pinctrl-names = "default";
  92 +       pinctrl-0 = <&uart1_pins>;
  93 +       status = "disabled";
  94 +};
  95 +
  96 +&eth {
  97 +       status = "okay";
  98 +       mediatek,gmac-id = <0>;
  99 +       phy-mode = "sgmii";
 100 +       mediatek,switch = "mt7531";
 101 +       reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
 102 +
 103 +       fixed-link {
 104 +               speed = <1000>;
 105 +               full-duplex;
 106 +       };
 107 +};
 108 +
 109 +&pinctrl {
 110 +       spic_pins: spi1-pins-func-1 {
 111 +               mux {
 112 +                       function = "spi";
 113 +                       groups = "spi1_1";
 114 +               };
 115 +       };
 116 +
 117 +       uart1_pins: spi1-pins-func-3 {
 118 +               mux {
 119 +                       function = "uart";
 120 +                       groups = "uart1_2";
 121 +               };
 122 +       };
 123 +
 124 +       /* pin15 as pwm0 */
 125 +       one_pwm_pins: one-pwm-pins {
 126 +               mux {
 127 +                       function = "pwm";
 128 +                       groups = "pwm0_1";
 129 +               };
 130 +       };
 131 +
 132 +       /* pin15 as pwm0 and pin14 as pwm1 */
 133 +       two_pwm_pins: two-pwm-pins {
 134 +               mux {
 135 +                       function = "pwm";
 136 +                       groups = "pwm0_1", "pwm1_0";
 137 +               };
 138 +       };
 139 +
 140 +       /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
 141 +       three_pwm_pins: three-pwm-pins {
 142 +               mux {
 143 +                       function = "pwm";
 144 +                       groups = "pwm0_1", "pwm1_0", "pwm2";
 145 +               };
 146 +       };
 147 +
 148 +       mmc0_pins_default: mmc0default {
 149 +               mux {
 150 +                       function = "flash";
 151 +                       groups =  "emmc_45";
 152 +               };
 153 +               conf-cmd-dat {
 154 +                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
 155 +                               "SPI0_CS",  "SPI0_HOLD", "SPI0_WP",
 156 +                               "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
 157 +                       input-enable;
 158 +                       drive-strength = <MTK_DRIVE_4mA>;
 159 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 160 +               };
 161 +               conf-clk {
 162 +                       pins = "SPI1_CS";
 163 +                       drive-strength = <MTK_DRIVE_6mA>;
 164 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 165 +               };
 166 +               conf-rst {
 167 +                       pins = "PWM0";
 168 +                       drive-strength = <MTK_DRIVE_4mA>;
 169 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 170 +               };
 171 +       };
 172 +};
 173 +
 174 +&pwm {
 175 +       pinctrl-names = "default";
 176 +       pinctrl-0 = <&two_pwm_pins>;
 177 +       status = "okay";
 178 +};
 179 +
 180 +&watchdog {
 181 +       status = "disabled";
 182 +};
 183 +
 184 +&mmc0 {
 185 +       pinctrl-names = "default";
 186 +       pinctrl-0 = <&mmc0_pins_default>;
 187 +       bus-width = <8>;
 188 +       max-frequency = <52000000>;
 189 +       cap-mmc-highspeed;
 190 +       cap-mmc-hw-reset;
 191 +       vmmc-supply = <&reg_3p3v>;
 192 +       non-removable;
 193 +       status = "okay";
 194 +};
 195 --- /dev/null
 196 +++ b/arch/arm/dts/mt7981-rfb.dts
 197 @@ -0,0 +1,173 @@
 198 +// SPDX-License-Identifier: GPL-2.0
 199 +/*
 200 + * Copyright (c) 2022 MediaTek Inc.
 201 + * Author: Sam Shih <sam.shih@mediatek.com>
 202 + */
 203 +
 204 +/dts-v1/;
 205 +#include "mt7981.dtsi"
 206 +#include <dt-bindings/gpio/gpio.h>
 207 +
 208 +/ {
 209 +       #address-cells = <1>;
 210 +       #size-cells = <1>;
 211 +       model = "mt7981-rfb";
 212 +       compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
 213 +       chosen {
 214 +               stdout-path = &uart0;
 215 +               tick-timer = &timer0;
 216 +       };
 217 +};
 218 +
 219 +&uart0 {
 220 +       status = "okay";
 221 +};
 222 +
 223 +&uart1 {
 224 +       pinctrl-names = "default";
 225 +       pinctrl-0 = <&uart1_pins>;
 226 +       status = "disabled";
 227 +};
 228 +
 229 +&eth {
 230 +       status = "okay";
 231 +       mediatek,gmac-id = <0>;
 232 +       phy-mode = "sgmii";
 233 +       mediatek,switch = "mt7531";
 234 +       reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
 235 +
 236 +       fixed-link {
 237 +               speed = <1000>;
 238 +               full-duplex;
 239 +       };
 240 +};
 241 +
 242 +&pinctrl {
 243 +       spi_flash_pins: spi0-pins-func-1 {
 244 +               mux {
 245 +                       function = "flash";
 246 +                       groups = "spi0", "spi0_wp_hold";
 247 +               };
 248 +
 249 +               conf-pu {
 250 +                       pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
 251 +                       drive-strength = <MTK_DRIVE_8mA>;
 252 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
 253 +               };
 254 +
 255 +               conf-pd {
 256 +                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
 257 +                       drive-strength = <MTK_DRIVE_8mA>;
 258 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
 259 +               };
 260 +       };
 261 +
 262 +       spi2_flash_pins: spi2-spi2-pins {
 263 +               mux {
 264 +                       function = "spi";
 265 +                       groups = "spi2", "spi2_wp_hold";
 266 +               };
 267 +
 268 +               conf-pu {
 269 +                       pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 270 +                       drive-strength = <MTK_DRIVE_8mA>;
 271 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
 272 +               };
 273 +
 274 +               conf-pd {
 275 +                       pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 276 +                       drive-strength = <MTK_DRIVE_8mA>;
 277 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
 278 +               };
 279 +       };
 280 +
 281 +       spic_pins: spi1-pins-func-1 {
 282 +               mux {
 283 +                       function = "spi";
 284 +                       groups = "spi1_1";
 285 +               };
 286 +       };
 287 +
 288 +       uart1_pins: spi1-pins-func-3 {
 289 +               mux {
 290 +                       function = "uart";
 291 +                       groups = "uart1_2";
 292 +               };
 293 +       };
 294 +
 295 +       /* pin15 as pwm0 */
 296 +       one_pwm_pins: one-pwm-pins {
 297 +               mux {
 298 +                       function = "pwm";
 299 +                       groups = "pwm0_1";
 300 +               };
 301 +       };
 302 +
 303 +       /* pin15 as pwm0 and pin14 as pwm1 */
 304 +       two_pwm_pins: two-pwm-pins {
 305 +               mux {
 306 +                       function = "pwm";
 307 +                       groups = "pwm0_1", "pwm1_0";
 308 +               };
 309 +       };
 310 +
 311 +       /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
 312 +       three_pwm_pins: three-pwm-pins {
 313 +               mux {
 314 +                       function = "pwm";
 315 +                       groups = "pwm0_1", "pwm1_0", "pwm2";
 316 +               };
 317 +       };
 318 +};
 319 +
 320 +&spi0 {
 321 +       #address-cells = <1>;
 322 +       #size-cells = <0>;
 323 +       pinctrl-names = "default";
 324 +       pinctrl-0 = <&spi_flash_pins>;
 325 +       status = "okay";
 326 +       must_tx;
 327 +       enhance_timing;
 328 +       dma_ext;
 329 +       ipm_design;
 330 +       support_quad;
 331 +       tick_dly = <2>;
 332 +       sample_sel = <0>;
 333 +
 334 +       spi_nand@0 {
 335 +               compatible = "spi-nand";
 336 +               reg = <0>;
 337 +               spi-max-frequency = <52000000>;
 338 +       };
 339 +};
 340 +
 341 +&spi2 {
 342 +       #address-cells = <1>;
 343 +       #size-cells = <0>;
 344 +       pinctrl-names = "default";
 345 +       pinctrl-0 = <&spi2_flash_pins>;
 346 +       status = "okay";
 347 +       must_tx;
 348 +       enhance_timing;
 349 +       dma_ext;
 350 +       ipm_design;
 351 +       support_quad;
 352 +       tick_dly = <2>;
 353 +       sample_sel = <0>;
 354 +
 355 +       spi_nor@0 {
 356 +               compatible = "jedec,spi-nor";
 357 +               reg = <0>;
 358 +               spi-max-frequency = <52000000>;
 359 +       };
 360 +};
 361 +
 362 +&pwm {
 363 +       pinctrl-names = "default";
 364 +       pinctrl-0 = <&two_pwm_pins>;
 365 +       status = "okay";
 366 +};
 367 +
 368 +&watchdog {
 369 +       status = "disabled";
 370 +};
 371 --- /dev/null
 372 +++ b/arch/arm/dts/mt7981-sd-rfb.dts
 373 @@ -0,0 +1,139 @@
 374 +// SPDX-License-Identifier: GPL-2.0
 375 +/*
 376 + * Copyright (c) 2022 MediaTek Inc.
 377 + * Author: Sam Shih <sam.shih@mediatek.com>
 378 + */
 379 +
 380 +/dts-v1/;
 381 +#include "mt7981.dtsi"
 382 +#include <dt-bindings/gpio/gpio.h>
 383 +
 384 +/ {
 385 +       #address-cells = <1>;
 386 +       #size-cells = <1>;
 387 +       model = "mt7981-rfb";
 388 +       compatible = "mediatek,mt7981", "mediatek,mt7981-sd-rfb";
 389 +       chosen {
 390 +               stdout-path = &uart0;
 391 +               tick-timer = &timer0;
 392 +       };
 393 +
 394 +       reg_3p3v: regulator-3p3v {
 395 +                 compatible = "regulator-fixed";
 396 +                 regulator-name = "fixed-3.3V";
 397 +                 regulator-min-microvolt = <3300000>;
 398 +                 regulator-max-microvolt = <3300000>;
 399 +                 regulator-boot-on;
 400 +                 regulator-always-on;
 401 +       };
 402 +};
 403 +
 404 +&uart0 {
 405 +       status = "okay";
 406 +};
 407 +
 408 +&uart1 {
 409 +       pinctrl-names = "default";
 410 +       pinctrl-0 = <&uart1_pins>;
 411 +       status = "disabled";
 412 +};
 413 +
 414 +&eth {
 415 +       status = "okay";
 416 +       mediatek,gmac-id = <0>;
 417 +       phy-mode = "sgmii";
 418 +       mediatek,switch = "mt7531";
 419 +       reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
 420 +
 421 +       fixed-link {
 422 +               speed = <1000>;
 423 +               full-duplex;
 424 +       };
 425 +};
 426 +
 427 +&pinctrl {
 428 +       spic_pins: spi1-pins-func-1 {
 429 +               mux {
 430 +                       function = "spi";
 431 +                       groups = "spi1_1";
 432 +               };
 433 +       };
 434 +
 435 +       uart1_pins: spi1-pins-func-3 {
 436 +               mux {
 437 +                       function = "uart";
 438 +                       groups = "uart1_2";
 439 +               };
 440 +       };
 441 +
 442 +       /* pin15 as pwm0 */
 443 +       one_pwm_pins: one-pwm-pins {
 444 +               mux {
 445 +                       function = "pwm";
 446 +                       groups = "pwm0_1";
 447 +               };
 448 +       };
 449 +
 450 +       /* pin15 as pwm0 and pin14 as pwm1 */
 451 +       two_pwm_pins: two-pwm-pins {
 452 +               mux {
 453 +                       function = "pwm";
 454 +                       groups = "pwm0_1", "pwm1_0";
 455 +               };
 456 +       };
 457 +
 458 +       /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
 459 +       three_pwm_pins: three-pwm-pins {
 460 +               mux {
 461 +                       function = "pwm";
 462 +                       groups = "pwm0_1", "pwm1_0", "pwm2";
 463 +               };
 464 +       };
 465 +
 466 +       mmc0_pins_default: mmc0default {
 467 +               mux {
 468 +                       function = "flash";
 469 +                       groups =  "emmc_45";
 470 +               };
 471 +               conf-cmd-dat {
 472 +                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
 473 +                               "SPI0_CS",  "SPI0_HOLD", "SPI0_WP",
 474 +                               "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
 475 +                       input-enable;
 476 +                       drive-strength = <MTK_DRIVE_4mA>;
 477 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 478 +               };
 479 +               conf-clk {
 480 +                       pins = "SPI1_CS";
 481 +                       drive-strength = <MTK_DRIVE_6mA>;
 482 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 483 +               };
 484 +               conf-rst {
 485 +                       pins = "PWM0";
 486 +                       drive-strength = <MTK_DRIVE_4mA>;
 487 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 488 +               };
 489 +       };
 490 +};
 491 +
 492 +&pwm {
 493 +       pinctrl-names = "default";
 494 +       pinctrl-0 = <&two_pwm_pins>;
 495 +       status = "okay";
 496 +};
 497 +
 498 +&watchdog {
 499 +       status = "disabled";
 500 +};
 501 +
 502 +&mmc0 {
 503 +       pinctrl-names = "default";
 504 +       pinctrl-0 = <&mmc0_pins_default>;
 505 +       bus-width = <4>;
 506 +       max-frequency = <52000000>;
 507 +       cap-sd-highspeed;
 508 +       r_smpl = <0>;
 509 +       vmmc-supply = <&reg_3p3v>;
 510 +       vqmmc-supply = <&reg_3p3v>;
 511 +       status = "okay";
 512 +};
 513 --- /dev/null
 514 +++ b/board/mediatek/mt7981/MAINTAINERS
 515 @@ -0,0 +1,10 @@
 516 +MT7981
 517 +M:     Sam Shih <sam.shih@mediatek.com>
 518 +S:     Maintained
 519 +F:     board/mediatek/mt7981
 520 +F:     include/configs/mt7981.h
 521 +F:     configs/mt7981_emmc_rfb_defconfig
 522 +F:     configs/mt7981_rfb_defconfig
 523 +F:     configs/mt7981_sd_rfb_defconfig
 524 +F:     configs/mt7981_spim_nand_rfb_defconfig
 525 +F:     configs/mt7981_spim_nor_rfb_defconfig
 526 --- /dev/null
 527 +++ b/board/mediatek/mt7981/Makefile
 528 @@ -0,0 +1,3 @@
 529 +# SPDX-License-Identifier:     GPL-2.0
 530 +
 531 +obj-y  += mt7981_rfb.o
 532 --- /dev/null
 533 +++ b/board/mediatek/mt7981/mt7981_rfb.c
 534 @@ -0,0 +1,10 @@
 535 +// SPDX-License-Identifier: GPL-2.0
 536 +/*
 537 + * Copyright (C) 2022 MediaTek Inc.
 538 + * Author: Sam Shih <sam.shih@mediatek.com>
 539 + */
 540 +
 541 +int board_init(void)
 542 +{
 543 +       return 0;
 544 +}
 545 --- /dev/null
 546 +++ b/configs/mt7981_emmc_rfb_defconfig
 547 @@ -0,0 +1,64 @@
 548 +CONFIG_ARM=y
 549 +CONFIG_POSITION_INDEPENDENT=y
 550 +CONFIG_ARCH_MEDIATEK=y
 551 +CONFIG_SYS_TEXT_BASE=0x41e00000
 552 +CONFIG_SYS_MALLOC_F_LEN=0x4000
 553 +CONFIG_NR_DRAM_BANKS=1
 554 +CONFIG_ENV_SIZE=0x80000
 555 +CONFIG_ENV_OFFSET=0x300000
 556 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-emmc-rfb"
 557 +CONFIG_TARGET_MT7981=y
 558 +CONFIG_DEBUG_UART_BASE=0x11002000
 559 +CONFIG_DEBUG_UART_CLOCK=40000000
 560 +CONFIG_SYS_LOAD_ADDR=0x46000000
 561 +CONFIG_DEBUG_UART=y
 562 +# CONFIG_AUTOBOOT is not set
 563 +CONFIG_DEFAULT_FDT_FILE="mt7981-emmc-rfb"
 564 +CONFIG_LOGLEVEL=7
 565 +CONFIG_LOG=y
 566 +CONFIG_SYS_PROMPT="MT7981> "
 567 +CONFIG_SYS_CBSIZE=512
 568 +CONFIG_SYS_PBSIZE=1049
 569 +# CONFIG_BOOTM_NETBSD is not set
 570 +# CONFIG_BOOTM_PLAN9 is not set
 571 +# CONFIG_BOOTM_RTEMS is not set
 572 +# CONFIG_BOOTM_VXWORKS is not set
 573 +# CONFIG_CMD_ELF is not set
 574 +# CONFIG_CMD_UNLZ4 is not set
 575 +# CONFIG_CMD_UNZIP is not set
 576 +CONFIG_CMD_GPIO=y
 577 +CONFIG_CMD_GPT=y
 578 +CONFIG_CMD_GPT_RENAME=y
 579 +CONFIG_CMD_LSBLK=y
 580 +CONFIG_CMD_MMC=y
 581 +CONFIG_CMD_PART=y
 582 +CONFIG_CMD_READ=y
 583 +CONFIG_CMD_PING=y
 584 +CONFIG_CMD_SMC=y
 585 +CONFIG_CMD_FAT=y
 586 +CONFIG_CMD_FS_GENERIC=y
 587 +CONFIG_PARTITION_TYPE_GUID=y
 588 +CONFIG_ENV_OVERWRITE=y
 589 +CONFIG_ENV_IS_IN_MMC=y
 590 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 591 +CONFIG_NET_RANDOM_ETHADDR=y
 592 +CONFIG_REGMAP=y
 593 +CONFIG_SYSCON=y
 594 +CONFIG_CLK=y
 595 +CONFIG_MMC_HS200_SUPPORT=y
 596 +CONFIG_MMC_MTK=y
 597 +CONFIG_PHY_FIXED=y
 598 +CONFIG_DM_ETH=y
 599 +CONFIG_MEDIATEK_ETH=y
 600 +CONFIG_PINCTRL=y
 601 +CONFIG_PINCONF=y
 602 +CONFIG_PINCTRL_MT7981=y
 603 +CONFIG_POWER_DOMAIN=y
 604 +CONFIG_MTK_POWER_DOMAIN=y
 605 +CONFIG_DM_REGULATOR=y
 606 +CONFIG_DM_REGULATOR_FIXED=y
 607 +CONFIG_DM_SERIAL=y
 608 +CONFIG_MTK_SERIAL=y
 609 +CONFIG_FAT_WRITE=y
 610 +CONFIG_HEXDUMP=y
 611 +# CONFIG_EFI_LOADER is not set
 612 --- /dev/null
 613 +++ b/configs/mt7981_rfb_defconfig
 614 @@ -0,0 +1,69 @@
 615 +CONFIG_ARM=y
 616 +CONFIG_POSITION_INDEPENDENT=y
 617 +CONFIG_ARCH_MEDIATEK=y
 618 +CONFIG_SYS_TEXT_BASE=0x41e00000
 619 +CONFIG_SYS_MALLOC_F_LEN=0x4000
 620 +CONFIG_NR_DRAM_BANKS=1
 621 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-rfb"
 622 +CONFIG_TARGET_MT7981=y
 623 +CONFIG_DEBUG_UART_BASE=0x11002000
 624 +CONFIG_DEBUG_UART_CLOCK=40000000
 625 +CONFIG_SYS_LOAD_ADDR=0x46000000
 626 +CONFIG_DEBUG_UART=y
 627 +# CONFIG_AUTOBOOT is not set
 628 +CONFIG_DEFAULT_FDT_FILE="mt7981-rfb"
 629 +CONFIG_LOGLEVEL=7
 630 +CONFIG_LOG=y
 631 +CONFIG_SYS_PROMPT="MT7981> "
 632 +CONFIG_SYS_CBSIZE=512
 633 +CONFIG_SYS_PBSIZE=1049
 634 +# CONFIG_BOOTM_NETBSD is not set
 635 +# CONFIG_BOOTM_PLAN9 is not set
 636 +# CONFIG_BOOTM_RTEMS is not set
 637 +# CONFIG_BOOTM_VXWORKS is not set
 638 +# CONFIG_CMD_ELF is not set
 639 +# CONFIG_CMD_UNLZ4 is not set
 640 +# CONFIG_CMD_UNZIP is not set
 641 +CONFIG_CMD_GPIO=y
 642 +CONFIG_CMD_MTD=y
 643 +CONFIG_CMD_SF_TEST=y
 644 +CONFIG_CMD_PING=y
 645 +CONFIG_CMD_SMC=y
 646 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 647 +CONFIG_NET_RANDOM_ETHADDR=y
 648 +CONFIG_REGMAP=y
 649 +CONFIG_SYSCON=y
 650 +CONFIG_BLK=y
 651 +CONFIG_HAVE_BLOCK_DEVICE=y
 652 +CONFIG_CLK=y
 653 +# CONFIG_MMC is not set
 654 +CONFIG_MTD=y
 655 +CONFIG_DM_MTD=y
 656 +CONFIG_MTD_SPI_NAND=y
 657 +CONFIG_DM_SPI_FLASH=y
 658 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 659 +CONFIG_SPI_FLASH_EON=y
 660 +CONFIG_SPI_FLASH_GIGADEVICE=y
 661 +CONFIG_SPI_FLASH_ISSI=y
 662 +CONFIG_SPI_FLASH_MACRONIX=y
 663 +CONFIG_SPI_FLASH_SPANSION=y
 664 +CONFIG_SPI_FLASH_STMICRO=y
 665 +CONFIG_SPI_FLASH_WINBOND=y
 666 +CONFIG_SPI_FLASH_XMC=y
 667 +CONFIG_SPI_FLASH_XTX=y
 668 +CONFIG_SPI_FLASH_MTD=y
 669 +CONFIG_PHY_FIXED=y
 670 +CONFIG_DM_ETH=y
 671 +CONFIG_MEDIATEK_ETH=y
 672 +CONFIG_PINCTRL=y
 673 +CONFIG_PINCONF=y
 674 +CONFIG_PINCTRL_MT7981=y
 675 +CONFIG_POWER_DOMAIN=y
 676 +CONFIG_MTK_POWER_DOMAIN=y
 677 +CONFIG_DM_SERIAL=y
 678 +CONFIG_MTK_SERIAL=y
 679 +CONFIG_SPI=y
 680 +CONFIG_DM_SPI=y
 681 +CONFIG_MTK_SPIM=y
 682 +CONFIG_HEXDUMP=y
 683 +# CONFIG_EFI_LOADER is not set
 684 --- /dev/null
 685 +++ b/configs/mt7981_sd_rfb_defconfig
 686 @@ -0,0 +1,64 @@
 687 +CONFIG_ARM=y
 688 +CONFIG_POSITION_INDEPENDENT=y
 689 +CONFIG_ARCH_MEDIATEK=y
 690 +CONFIG_SYS_TEXT_BASE=0x41e00000
 691 +CONFIG_SYS_MALLOC_F_LEN=0x4000
 692 +CONFIG_NR_DRAM_BANKS=1
 693 +CONFIG_ENV_SIZE=0x80000
 694 +CONFIG_ENV_OFFSET=0x300000
 695 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-sd-rfb"
 696 +CONFIG_TARGET_MT7981=y
 697 +CONFIG_DEBUG_UART_BASE=0x11002000
 698 +CONFIG_DEBUG_UART_CLOCK=40000000
 699 +CONFIG_SYS_LOAD_ADDR=0x46000000
 700 +CONFIG_DEBUG_UART=y
 701 +# CONFIG_AUTOBOOT is not set
 702 +CONFIG_DEFAULT_FDT_FILE="mt7981-sd-rfb"
 703 +CONFIG_LOGLEVEL=7
 704 +CONFIG_LOG=y
 705 +CONFIG_SYS_PROMPT="MT7981> "
 706 +CONFIG_SYS_CBSIZE=512
 707 +CONFIG_SYS_PBSIZE=1049
 708 +# CONFIG_BOOTM_NETBSD is not set
 709 +# CONFIG_BOOTM_PLAN9 is not set
 710 +# CONFIG_BOOTM_RTEMS is not set
 711 +# CONFIG_BOOTM_VXWORKS is not set
 712 +# CONFIG_CMD_ELF is not set
 713 +# CONFIG_CMD_UNLZ4 is not set
 714 +# CONFIG_CMD_UNZIP is not set
 715 +CONFIG_CMD_GPIO=y
 716 +CONFIG_CMD_GPT=y
 717 +CONFIG_CMD_GPT_RENAME=y
 718 +CONFIG_CMD_LSBLK=y
 719 +CONFIG_CMD_MMC=y
 720 +CONFIG_CMD_PART=y
 721 +CONFIG_CMD_READ=y
 722 +CONFIG_CMD_PING=y
 723 +CONFIG_CMD_SMC=y
 724 +CONFIG_CMD_FAT=y
 725 +CONFIG_CMD_FS_GENERIC=y
 726 +CONFIG_PARTITION_TYPE_GUID=y
 727 +CONFIG_ENV_OVERWRITE=y
 728 +CONFIG_ENV_IS_IN_MMC=y
 729 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 730 +CONFIG_NET_RANDOM_ETHADDR=y
 731 +CONFIG_REGMAP=y
 732 +CONFIG_SYSCON=y
 733 +CONFIG_CLK=y
 734 +CONFIG_MMC_HS200_SUPPORT=y
 735 +CONFIG_MMC_MTK=y
 736 +CONFIG_PHY_FIXED=y
 737 +CONFIG_DM_ETH=y
 738 +CONFIG_MEDIATEK_ETH=y
 739 +CONFIG_PINCTRL=y
 740 +CONFIG_PINCONF=y
 741 +CONFIG_PINCTRL_MT7981=y
 742 +CONFIG_POWER_DOMAIN=y
 743 +CONFIG_MTK_POWER_DOMAIN=y
 744 +CONFIG_DM_REGULATOR=y
 745 +CONFIG_DM_REGULATOR_FIXED=y
 746 +CONFIG_DM_SERIAL=y
 747 +CONFIG_MTK_SERIAL=y
 748 +CONFIG_FAT_WRITE=y
 749 +CONFIG_HEXDUMP=y
 750 +# CONFIG_EFI_LOADER is not set
 751 --- /dev/null
 752 +++ b/include/configs/mt7981.h
 753 @@ -0,0 +1,26 @@
 754 +/* SPDX-License-Identifier: GPL-2.0 */
 755 +/*
 756 + * Configuration for MediaTek MT7981 SoC
 757 + *
 758 + * Copyright (C) 2022 MediaTek Inc.
 759 + * Author: Sam Shih <sam.shih@mediatek.com>
 760 + */
 761 +
 762 +#ifndef __MT7981_H
 763 +#define __MT7981_H
 764 +
 765 +#include <linux/sizes.h>
 766 +
 767 +#define CONFIG_SYS_NONCACHED_MEMORY    SZ_1M
 768 +#define CONFIG_SYS_MMC_ENV_DEV         0
 769 +
 770 +/* Uboot definition */
 771 +#define CONFIG_SYS_UBOOT_BASE          CONFIG_SYS_TEXT_BASE
 772 +
 773 +/* SPL -> Uboot */
 774 +#define CONFIG_SYS_UBOOT_START         CONFIG_SYS_TEXT_BASE
 775 +
 776 +/* DRAM */
 777 +#define CONFIG_SYS_SDRAM_BASE          0x40000000
 778 +
 779 +#endif