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ath79: ag71xx: apply interface mode to MII0/1_CTRL on ar71xx/ar913x
[openwrt/openwrt.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include "ag71xx.h"
19
20 #define AG71XX_DEFAULT_MSG_ENABLE \
21 (NETIF_MSG_DRV \
22 | NETIF_MSG_PROBE \
23 | NETIF_MSG_LINK \
24 | NETIF_MSG_TIMER \
25 | NETIF_MSG_IFDOWN \
26 | NETIF_MSG_IFUP \
27 | NETIF_MSG_RX_ERR \
28 | NETIF_MSG_TX_ERR)
29
30 static int ag71xx_msg_level = -1;
31
32 module_param_named(msg_level, ag71xx_msg_level, int, 0);
33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
34
35 #define ETH_SWITCH_HEADER_LEN 2
36
37 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
38
39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
40 {
41 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
42 }
43
44 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
45 {
46 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
51
52 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
53 ag->dev->name,
54 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
55 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
56 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
57 }
58
59 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
60 {
61 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
62 ag->dev->name, label, intr,
63 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
64 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
65 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
66 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
67 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
68 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
69 }
70
71 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
72 {
73 struct ag71xx_ring *ring = &ag->tx_ring;
74 struct net_device *dev = ag->dev;
75 int ring_mask = BIT(ring->order) - 1;
76 u32 bytes_compl = 0, pkts_compl = 0;
77
78 while (ring->curr != ring->dirty) {
79 struct ag71xx_desc *desc;
80 u32 i = ring->dirty & ring_mask;
81
82 desc = ag71xx_ring_desc(ring, i);
83 if (!ag71xx_desc_empty(desc)) {
84 desc->ctrl = 0;
85 dev->stats.tx_errors++;
86 }
87
88 if (ring->buf[i].skb) {
89 bytes_compl += ring->buf[i].len;
90 pkts_compl++;
91 dev_kfree_skb_any(ring->buf[i].skb);
92 }
93 ring->buf[i].skb = NULL;
94 ring->dirty++;
95 }
96
97 /* flush descriptors */
98 wmb();
99
100 netdev_completed_queue(dev, pkts_compl, bytes_compl);
101 }
102
103 static void ag71xx_ring_tx_init(struct ag71xx *ag)
104 {
105 struct ag71xx_ring *ring = &ag->tx_ring;
106 int ring_size = BIT(ring->order);
107 int ring_mask = ring_size - 1;
108 int i;
109
110 for (i = 0; i < ring_size; i++) {
111 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
112
113 desc->next = (u32) (ring->descs_dma +
114 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
115
116 desc->ctrl = DESC_EMPTY;
117 ring->buf[i].skb = NULL;
118 }
119
120 /* flush descriptors */
121 wmb();
122
123 ring->curr = 0;
124 ring->dirty = 0;
125 netdev_reset_queue(ag->dev);
126 }
127
128 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
129 {
130 struct ag71xx_ring *ring = &ag->rx_ring;
131 int ring_size = BIT(ring->order);
132 int i;
133
134 if (!ring->buf)
135 return;
136
137 for (i = 0; i < ring_size; i++)
138 if (ring->buf[i].rx_buf) {
139 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
140 ag->rx_buf_size, DMA_FROM_DEVICE);
141 skb_free_frag(ring->buf[i].rx_buf);
142 }
143 }
144
145 static int ag71xx_buffer_size(struct ag71xx *ag)
146 {
147 return ag->rx_buf_size +
148 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
149 }
150
151 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
152 int offset,
153 void *(*alloc)(unsigned int size))
154 {
155 struct ag71xx_ring *ring = &ag->rx_ring;
156 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
157 void *data;
158
159 data = alloc(ag71xx_buffer_size(ag));
160 if (!data)
161 return false;
162
163 buf->rx_buf = data;
164 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
165 DMA_FROM_DEVICE);
166 desc->data = (u32) buf->dma_addr + offset;
167 return true;
168 }
169
170 static int ag71xx_ring_rx_init(struct ag71xx *ag)
171 {
172 struct ag71xx_ring *ring = &ag->rx_ring;
173 int ring_size = BIT(ring->order);
174 int ring_mask = BIT(ring->order) - 1;
175 unsigned int i;
176 int ret;
177
178 ret = 0;
179 for (i = 0; i < ring_size; i++) {
180 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
181
182 desc->next = (u32) (ring->descs_dma +
183 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
184
185 DBG("ag71xx: RX desc at %p, next is %08x\n",
186 desc, desc->next);
187 }
188
189 for (i = 0; i < ring_size; i++) {
190 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
191
192 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
193 netdev_alloc_frag)) {
194 ret = -ENOMEM;
195 break;
196 }
197
198 desc->ctrl = DESC_EMPTY;
199 }
200
201 /* flush descriptors */
202 wmb();
203
204 ring->curr = 0;
205 ring->dirty = 0;
206
207 return ret;
208 }
209
210 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
211 {
212 struct ag71xx_ring *ring = &ag->rx_ring;
213 int ring_mask = BIT(ring->order) - 1;
214 unsigned int count;
215 int offset = ag->rx_buf_offset;
216
217 count = 0;
218 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
219 struct ag71xx_desc *desc;
220 unsigned int i;
221
222 i = ring->dirty & ring_mask;
223 desc = ag71xx_ring_desc(ring, i);
224
225 if (!ring->buf[i].rx_buf &&
226 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
227 napi_alloc_frag))
228 break;
229
230 desc->ctrl = DESC_EMPTY;
231 count++;
232 }
233
234 /* flush descriptors */
235 wmb();
236
237 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
238
239 return count;
240 }
241
242 static int ag71xx_rings_init(struct ag71xx *ag)
243 {
244 struct ag71xx_ring *tx = &ag->tx_ring;
245 struct ag71xx_ring *rx = &ag->rx_ring;
246 int ring_size = BIT(tx->order) + BIT(rx->order);
247 int tx_size = BIT(tx->order);
248
249 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
250 if (!tx->buf)
251 return -ENOMEM;
252
253 tx->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
254 &tx->descs_dma, GFP_ATOMIC);
255 if (!tx->descs_cpu) {
256 kfree(tx->buf);
257 tx->buf = NULL;
258 return -ENOMEM;
259 }
260
261 rx->buf = &tx->buf[BIT(tx->order)];
262 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
263 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
264
265 ag71xx_ring_tx_init(ag);
266 return ag71xx_ring_rx_init(ag);
267 }
268
269 static void ag71xx_rings_free(struct ag71xx *ag)
270 {
271 struct ag71xx_ring *tx = &ag->tx_ring;
272 struct ag71xx_ring *rx = &ag->rx_ring;
273 int ring_size = BIT(tx->order) + BIT(rx->order);
274
275 if (tx->descs_cpu)
276 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
277 tx->descs_cpu, tx->descs_dma);
278
279 kfree(tx->buf);
280
281 tx->descs_cpu = NULL;
282 rx->descs_cpu = NULL;
283 tx->buf = NULL;
284 rx->buf = NULL;
285 }
286
287 static void ag71xx_rings_cleanup(struct ag71xx *ag)
288 {
289 ag71xx_ring_rx_clean(ag);
290 ag71xx_ring_tx_clean(ag);
291 ag71xx_rings_free(ag);
292
293 netdev_reset_queue(ag->dev);
294 }
295
296 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
297 {
298 switch (ag->speed) {
299 case SPEED_1000:
300 return "1000";
301 case SPEED_100:
302 return "100";
303 case SPEED_10:
304 return "10";
305 }
306
307 return "?";
308 }
309
310 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
311 {
312 u32 t;
313
314 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
315 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
316
317 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
318
319 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
320 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
321 }
322
323 static void ag71xx_dma_reset(struct ag71xx *ag)
324 {
325 u32 val;
326 int i;
327
328 ag71xx_dump_dma_regs(ag);
329
330 /* stop RX and TX */
331 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
332 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
333
334 /*
335 * give the hardware some time to really stop all rx/tx activity
336 * clearing the descriptors too early causes random memory corruption
337 */
338 mdelay(1);
339
340 /* clear descriptor addresses */
341 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
342 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
343
344 /* clear pending RX/TX interrupts */
345 for (i = 0; i < 256; i++) {
346 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
347 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
348 }
349
350 /* clear pending errors */
351 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
352 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
353
354 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
355 if (val)
356 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
357 ag->dev->name, val);
358
359 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
360
361 /* mask out reserved bits */
362 val &= ~0xff000000;
363
364 if (val)
365 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
366 ag->dev->name, val);
367
368 ag71xx_dump_dma_regs(ag);
369 }
370
371 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
372 MAC_CFG1_SRX | MAC_CFG1_STX)
373
374 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
375
376 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
377 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
378 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
379 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
380 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
381 FIFO_CFG4_VT)
382
383 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
384 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
385 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
386 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
387 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
388 FIFO_CFG5_17 | FIFO_CFG5_SF)
389
390 static void ag71xx_hw_stop(struct ag71xx *ag)
391 {
392 /* disable all interrupts and stop the rx/tx engine */
393 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
394 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
395 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
396 }
397
398 static void ag71xx_hw_setup(struct ag71xx *ag)
399 {
400 struct device_node *np = ag->pdev->dev.of_node;
401 u32 init = MAC_CFG1_INIT;
402
403 /* setup MAC configuration registers */
404 if (of_property_read_bool(np, "flow-control"))
405 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
406 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
407
408 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
409 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
410
411 /* setup max frame length to zero */
412 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
413
414 /* setup FIFO configuration registers */
415 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
416 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
417 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
418 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
419 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
420 }
421
422 static void ag71xx_hw_init(struct ag71xx *ag)
423 {
424 ag71xx_hw_stop(ag);
425
426 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
427 udelay(20);
428
429 reset_control_assert(ag->mac_reset);
430 msleep(100);
431 reset_control_deassert(ag->mac_reset);
432 msleep(200);
433
434 ag71xx_hw_setup(ag);
435
436 ag71xx_dma_reset(ag);
437 }
438
439 static void ag71xx_fast_reset(struct ag71xx *ag)
440 {
441 struct net_device *dev = ag->dev;
442 u32 rx_ds;
443 u32 mii_reg;
444
445 ag71xx_hw_stop(ag);
446 wmb();
447
448 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
449 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
450
451 ag71xx_tx_packets(ag, true);
452
453 reset_control_assert(ag->mac_reset);
454 udelay(10);
455 reset_control_deassert(ag->mac_reset);
456 udelay(10);
457
458 ag71xx_dma_reset(ag);
459 ag71xx_hw_setup(ag);
460 ag->tx_ring.curr = 0;
461 ag->tx_ring.dirty = 0;
462 netdev_reset_queue(ag->dev);
463
464 /* setup max frame length */
465 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
466 ag71xx_max_frame_len(ag->dev->mtu));
467
468 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
469 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
470 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
471
472 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
473 }
474
475 static void ag71xx_hw_start(struct ag71xx *ag)
476 {
477 /* start RX engine */
478 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
479
480 /* enable interrupts */
481 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
482
483 netif_wake_queue(ag->dev);
484 }
485
486 static void ath79_set_pllval(struct ag71xx *ag)
487 {
488 u32 pll_reg = ag->pllreg[1];
489 u32 pll_val;
490
491 if (!ag->pllregmap)
492 return;
493
494 switch (ag->speed) {
495 case SPEED_10:
496 pll_val = ag->plldata[2];
497 break;
498 case SPEED_100:
499 pll_val = ag->plldata[1];
500 break;
501 case SPEED_1000:
502 pll_val = ag->plldata[0];
503 break;
504 default:
505 BUG();
506 }
507
508 if (pll_val)
509 regmap_write(ag->pllregmap, pll_reg, pll_val);
510 }
511
512 static void ath79_set_pll(struct ag71xx *ag)
513 {
514 u32 pll_cfg = ag->pllreg[0];
515 u32 pll_shift = ag->pllreg[2];
516
517 if (!ag->pllregmap)
518 return;
519
520 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
521 udelay(100);
522
523 ath79_set_pllval(ag);
524
525 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
526 udelay(100);
527
528 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
529 udelay(100);
530 }
531
532 static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
533 {
534 u32 t;
535
536 t = __raw_readl(ag->mii_base);
537 t &= ~(AR71XX_MII_CTRL_IF_MASK);
538 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
539 __raw_writel(t, ag->mii_base);
540 }
541
542 static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
543 {
544 unsigned int mii_if;
545
546 switch (ag->phy_if_mode) {
547 case PHY_INTERFACE_MODE_MII:
548 mii_if = AR71XX_MII0_CTRL_IF_MII;
549 break;
550 case PHY_INTERFACE_MODE_GMII:
551 mii_if = AR71XX_MII0_CTRL_IF_GMII;
552 break;
553 case PHY_INTERFACE_MODE_RGMII:
554 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
555 break;
556 case PHY_INTERFACE_MODE_RMII:
557 mii_if = AR71XX_MII0_CTRL_IF_RMII;
558 break;
559 default:
560 WARN(1, "Impossible PHY mode defined.\n");
561 return;
562 }
563
564 ath79_mii_ctrl_set_if(ag, mii_if);
565 }
566
567 static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
568 {
569 unsigned int mii_if;
570
571 switch (ag->phy_if_mode) {
572 case PHY_INTERFACE_MODE_RMII:
573 mii_if = AR71XX_MII1_CTRL_IF_RMII;
574 break;
575 case PHY_INTERFACE_MODE_RGMII:
576 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
577 break;
578 default:
579 WARN(1, "Impossible PHY mode defined.\n");
580 return;
581 }
582
583 ath79_mii_ctrl_set_if(ag, mii_if);
584 }
585
586 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
587 {
588 unsigned int mii_speed;
589 u32 t;
590
591 if (!ag->mii_base)
592 return;
593
594 switch (ag->speed) {
595 case SPEED_10:
596 mii_speed = AR71XX_MII_CTRL_SPEED_10;
597 break;
598 case SPEED_100:
599 mii_speed = AR71XX_MII_CTRL_SPEED_100;
600 break;
601 case SPEED_1000:
602 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
603 break;
604 default:
605 BUG();
606 }
607
608 t = __raw_readl(ag->mii_base);
609 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
610 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
611 __raw_writel(t, ag->mii_base);
612 }
613
614 static void
615 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
616 {
617 struct device_node *np = ag->pdev->dev.of_node;
618 u32 cfg2;
619 u32 ifctl;
620 u32 fifo5;
621
622 if (!ag->link && update) {
623 ag71xx_hw_stop(ag);
624 netif_carrier_off(ag->dev);
625 if (netif_msg_link(ag))
626 pr_info("%s: link down\n", ag->dev->name);
627 return;
628 }
629
630 if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
631 !of_device_is_compatible(np, "qca,ar7100-eth"))
632 ag71xx_fast_reset(ag);
633
634 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
635 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
636 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
637
638 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
639 ifctl &= ~(MAC_IFCTL_SPEED);
640
641 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
642 fifo5 &= ~FIFO_CFG5_BM;
643
644 switch (ag->speed) {
645 case SPEED_1000:
646 cfg2 |= MAC_CFG2_IF_1000;
647 fifo5 |= FIFO_CFG5_BM;
648 break;
649 case SPEED_100:
650 cfg2 |= MAC_CFG2_IF_10_100;
651 ifctl |= MAC_IFCTL_SPEED;
652 break;
653 case SPEED_10:
654 cfg2 |= MAC_CFG2_IF_10_100;
655 break;
656 default:
657 BUG();
658 return;
659 }
660
661 if (ag->tx_ring.desc_split) {
662 ag->fifodata[2] &= 0xffff;
663 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
664 }
665
666 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
667
668 if (update) {
669 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
670 of_device_is_compatible(np, "qca,ar9130-eth")) {
671 ath79_set_pll(ag);
672 ath79_mii_ctrl_set_speed(ag);
673 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
674 of_device_is_compatible(np, "qca,ar9340-eth") ||
675 of_device_is_compatible(np, "qca,qca9550-eth") ||
676 of_device_is_compatible(np, "qca,qca9560-eth")) {
677 ath79_set_pllval(ag);
678 }
679 }
680
681 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
682 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
683 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
684
685 if (of_device_is_compatible(np, "qca,qca9530-eth") ||
686 of_device_is_compatible(np, "qca,qca9560-eth")) {
687 /*
688 * The rx ring buffer can stall on small packets on QCA953x and
689 * QCA956x. Disabling the inline checksum engine fixes the stall.
690 * The wr, rr functions cannot be used since this hidden register
691 * is outside of the normal ag71xx register block.
692 */
693 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
694 if (dam) {
695 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
696 (void)__raw_readl(dam);
697 iounmap(dam);
698 }
699 }
700
701 ag71xx_hw_start(ag);
702
703 netif_carrier_on(ag->dev);
704 if (update && netif_msg_link(ag))
705 pr_info("%s: link up (%sMbps/%s duplex)\n",
706 ag->dev->name,
707 ag71xx_speed_str(ag),
708 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
709
710 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
711 ag->dev->name,
712 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
713 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
714 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
715
716 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
717 ag->dev->name,
718 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
719 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
720 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
721
722 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
723 ag->dev->name,
724 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
725 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
726 }
727
728 void ag71xx_link_adjust(struct ag71xx *ag)
729 {
730 __ag71xx_link_adjust(ag, true);
731 }
732
733 static int ag71xx_hw_enable(struct ag71xx *ag)
734 {
735 int ret;
736
737 ret = ag71xx_rings_init(ag);
738 if (ret)
739 return ret;
740
741 napi_enable(&ag->napi);
742 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
743 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
744 netif_start_queue(ag->dev);
745
746 return 0;
747 }
748
749 static void ag71xx_hw_disable(struct ag71xx *ag)
750 {
751 unsigned long flags;
752
753 spin_lock_irqsave(&ag->lock, flags);
754
755 netif_stop_queue(ag->dev);
756
757 ag71xx_hw_stop(ag);
758 ag71xx_dma_reset(ag);
759
760 napi_disable(&ag->napi);
761 del_timer_sync(&ag->oom_timer);
762
763 spin_unlock_irqrestore(&ag->lock, flags);
764
765 ag71xx_rings_cleanup(ag);
766 }
767
768 static int ag71xx_open(struct net_device *dev)
769 {
770 struct ag71xx *ag = netdev_priv(dev);
771 unsigned int max_frame_len;
772 int ret;
773
774 netif_carrier_off(dev);
775 max_frame_len = ag71xx_max_frame_len(dev->mtu);
776 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
777
778 /* setup max frame length */
779 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
780 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
781
782 ret = ag71xx_hw_enable(ag);
783 if (ret)
784 goto err;
785
786 phy_start(ag->phy_dev);
787
788 return 0;
789
790 err:
791 ag71xx_rings_cleanup(ag);
792 return ret;
793 }
794
795 static int ag71xx_stop(struct net_device *dev)
796 {
797 struct ag71xx *ag = netdev_priv(dev);
798
799 netif_carrier_off(dev);
800 phy_stop(ag->phy_dev);
801 ag71xx_hw_disable(ag);
802
803 return 0;
804 }
805
806 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
807 {
808 int i;
809 struct ag71xx_desc *desc;
810 int ring_mask = BIT(ring->order) - 1;
811 int ndesc = 0;
812 int split = ring->desc_split;
813
814 if (!split)
815 split = len;
816
817 while (len > 0) {
818 unsigned int cur_len = len;
819
820 i = (ring->curr + ndesc) & ring_mask;
821 desc = ag71xx_ring_desc(ring, i);
822
823 if (!ag71xx_desc_empty(desc))
824 return -1;
825
826 if (cur_len > split) {
827 cur_len = split;
828
829 /*
830 * TX will hang if DMA transfers <= 4 bytes,
831 * make sure next segment is more than 4 bytes long.
832 */
833 if (len <= split + 4)
834 cur_len -= 4;
835 }
836
837 desc->data = addr;
838 addr += cur_len;
839 len -= cur_len;
840
841 if (len > 0)
842 cur_len |= DESC_MORE;
843
844 /* prevent early tx attempt of this descriptor */
845 if (!ndesc)
846 cur_len |= DESC_EMPTY;
847
848 desc->ctrl = cur_len;
849 ndesc++;
850 }
851
852 return ndesc;
853 }
854
855 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
856 struct net_device *dev)
857 {
858 struct ag71xx *ag = netdev_priv(dev);
859 struct ag71xx_ring *ring = &ag->tx_ring;
860 int ring_mask = BIT(ring->order) - 1;
861 int ring_size = BIT(ring->order);
862 struct ag71xx_desc *desc;
863 dma_addr_t dma_addr;
864 int i, n, ring_min;
865
866 if (skb->len <= 4) {
867 DBG("%s: packet len is too small\n", ag->dev->name);
868 goto err_drop;
869 }
870
871 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
872 DMA_TO_DEVICE);
873
874 i = ring->curr & ring_mask;
875 desc = ag71xx_ring_desc(ring, i);
876
877 /* setup descriptor fields */
878 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
879 if (n < 0)
880 goto err_drop_unmap;
881
882 i = (ring->curr + n - 1) & ring_mask;
883 ring->buf[i].len = skb->len;
884 ring->buf[i].skb = skb;
885
886 netdev_sent_queue(dev, skb->len);
887
888 skb_tx_timestamp(skb);
889
890 desc->ctrl &= ~DESC_EMPTY;
891 ring->curr += n;
892
893 /* flush descriptor */
894 wmb();
895
896 ring_min = 2;
897 if (ring->desc_split)
898 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
899
900 if (ring->curr - ring->dirty >= ring_size - ring_min) {
901 DBG("%s: tx queue full\n", dev->name);
902 netif_stop_queue(dev);
903 }
904
905 DBG("%s: packet injected into TX queue\n", ag->dev->name);
906
907 /* enable TX engine */
908 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
909
910 return NETDEV_TX_OK;
911
912 err_drop_unmap:
913 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
914
915 err_drop:
916 dev->stats.tx_dropped++;
917
918 dev_kfree_skb(skb);
919 return NETDEV_TX_OK;
920 }
921
922 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
923 {
924 struct ag71xx *ag = netdev_priv(dev);
925 int ret;
926
927 switch (cmd) {
928 case SIOCETHTOOL:
929 if (ag->phy_dev == NULL)
930 break;
931
932 spin_lock_irq(&ag->lock);
933 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
934 spin_unlock_irq(&ag->lock);
935 return ret;
936
937 case SIOCSIFHWADDR:
938 if (copy_from_user
939 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
940 return -EFAULT;
941 return 0;
942
943 case SIOCGIFHWADDR:
944 if (copy_to_user
945 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
946 return -EFAULT;
947 return 0;
948
949 case SIOCGMIIPHY:
950 case SIOCGMIIREG:
951 case SIOCSMIIREG:
952 if (ag->phy_dev == NULL)
953 break;
954
955 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
956
957 default:
958 break;
959 }
960
961 return -EOPNOTSUPP;
962 }
963
964 static void ag71xx_oom_timer_handler(unsigned long data)
965 {
966 struct net_device *dev = (struct net_device *) data;
967 struct ag71xx *ag = netdev_priv(dev);
968
969 napi_schedule(&ag->napi);
970 }
971
972 static void ag71xx_tx_timeout(struct net_device *dev)
973 {
974 struct ag71xx *ag = netdev_priv(dev);
975
976 if (netif_msg_tx_err(ag))
977 pr_info("%s: tx timeout\n", ag->dev->name);
978
979 schedule_delayed_work(&ag->restart_work, 1);
980 }
981
982 static void ag71xx_restart_work_func(struct work_struct *work)
983 {
984 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
985
986 rtnl_lock();
987 ag71xx_hw_disable(ag);
988 ag71xx_hw_enable(ag);
989 if (ag->link)
990 __ag71xx_link_adjust(ag, false);
991 rtnl_unlock();
992 }
993
994 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
995 {
996 unsigned long timestamp;
997 u32 rx_sm, tx_sm, rx_fd;
998
999 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
1000 if (likely(time_before(jiffies, timestamp + HZ/10)))
1001 return false;
1002
1003 if (!netif_carrier_ok(ag->dev))
1004 return false;
1005
1006 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
1007 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
1008 return true;
1009
1010 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
1011 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
1012 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
1013 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
1014 return true;
1015
1016 return false;
1017 }
1018
1019 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
1020 {
1021 struct ag71xx_ring *ring = &ag->tx_ring;
1022 bool dma_stuck = false;
1023 int ring_mask = BIT(ring->order) - 1;
1024 int ring_size = BIT(ring->order);
1025 int sent = 0;
1026 int bytes_compl = 0;
1027 int n = 0;
1028
1029 DBG("%s: processing TX ring\n", ag->dev->name);
1030
1031 while (ring->dirty + n != ring->curr) {
1032 unsigned int i = (ring->dirty + n) & ring_mask;
1033 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1034 struct sk_buff *skb = ring->buf[i].skb;
1035
1036 if (!flush && !ag71xx_desc_empty(desc)) {
1037 if (ag->tx_hang_workaround &&
1038 ag71xx_check_dma_stuck(ag)) {
1039 schedule_delayed_work(&ag->restart_work, HZ / 2);
1040 dma_stuck = true;
1041 }
1042 break;
1043 }
1044
1045 if (flush)
1046 desc->ctrl |= DESC_EMPTY;
1047
1048 n++;
1049 if (!skb)
1050 continue;
1051
1052 dev_kfree_skb_any(skb);
1053 ring->buf[i].skb = NULL;
1054
1055 bytes_compl += ring->buf[i].len;
1056
1057 sent++;
1058 ring->dirty += n;
1059
1060 while (n > 0) {
1061 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1062 n--;
1063 }
1064 }
1065
1066 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1067
1068 if (!sent)
1069 return 0;
1070
1071 ag->dev->stats.tx_bytes += bytes_compl;
1072 ag->dev->stats.tx_packets += sent;
1073
1074 netdev_completed_queue(ag->dev, sent, bytes_compl);
1075 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1076 netif_wake_queue(ag->dev);
1077
1078 if (!dma_stuck)
1079 cancel_delayed_work(&ag->restart_work);
1080
1081 return sent;
1082 }
1083
1084 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1085 {
1086 struct net_device *dev = ag->dev;
1087 struct ag71xx_ring *ring = &ag->rx_ring;
1088 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1089 unsigned int offset = ag->rx_buf_offset;
1090 int ring_mask = BIT(ring->order) - 1;
1091 int ring_size = BIT(ring->order);
1092 struct sk_buff_head queue;
1093 struct sk_buff *skb;
1094 int done = 0;
1095
1096 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1097 dev->name, limit, ring->curr, ring->dirty);
1098
1099 skb_queue_head_init(&queue);
1100
1101 while (done < limit) {
1102 unsigned int i = ring->curr & ring_mask;
1103 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1104 int pktlen;
1105 int err = 0;
1106
1107 if (ag71xx_desc_empty(desc))
1108 break;
1109
1110 if ((ring->dirty + ring_size) == ring->curr) {
1111 ag71xx_assert(0);
1112 break;
1113 }
1114
1115 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1116
1117 pktlen = desc->ctrl & pktlen_mask;
1118 pktlen -= ETH_FCS_LEN;
1119
1120 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1121 ag->rx_buf_size, DMA_FROM_DEVICE);
1122
1123 dev->stats.rx_packets++;
1124 dev->stats.rx_bytes += pktlen;
1125
1126 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1127 if (!skb) {
1128 skb_free_frag(ring->buf[i].rx_buf);
1129 goto next;
1130 }
1131
1132 skb_reserve(skb, offset);
1133 skb_put(skb, pktlen);
1134
1135 if (err) {
1136 dev->stats.rx_dropped++;
1137 kfree_skb(skb);
1138 } else {
1139 skb->dev = dev;
1140 skb->ip_summed = CHECKSUM_NONE;
1141 __skb_queue_tail(&queue, skb);
1142 }
1143
1144 next:
1145 ring->buf[i].rx_buf = NULL;
1146 done++;
1147
1148 ring->curr++;
1149 }
1150
1151 ag71xx_ring_rx_refill(ag);
1152
1153 while ((skb = __skb_dequeue(&queue)) != NULL) {
1154 skb->protocol = eth_type_trans(skb, dev);
1155 netif_receive_skb(skb);
1156 }
1157
1158 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1159 dev->name, ring->curr, ring->dirty, done);
1160
1161 return done;
1162 }
1163
1164 static int ag71xx_poll(struct napi_struct *napi, int limit)
1165 {
1166 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1167 struct net_device *dev = ag->dev;
1168 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1169 int rx_ring_size = BIT(rx_ring->order);
1170 unsigned long flags;
1171 u32 status;
1172 int tx_done;
1173 int rx_done;
1174
1175 tx_done = ag71xx_tx_packets(ag, false);
1176
1177 DBG("%s: processing RX ring\n", dev->name);
1178 rx_done = ag71xx_rx_packets(ag, limit);
1179
1180 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1181
1182 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1183 goto oom;
1184
1185 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1186 if (unlikely(status & RX_STATUS_OF)) {
1187 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1188 dev->stats.rx_fifo_errors++;
1189
1190 /* restart RX */
1191 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1192 }
1193
1194 if (rx_done < limit) {
1195 if (status & RX_STATUS_PR)
1196 goto more;
1197
1198 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1199 if (status & TX_STATUS_PS)
1200 goto more;
1201
1202 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1203 dev->name, rx_done, tx_done, limit);
1204
1205 napi_complete(napi);
1206
1207 /* enable interrupts */
1208 spin_lock_irqsave(&ag->lock, flags);
1209 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1210 spin_unlock_irqrestore(&ag->lock, flags);
1211 return rx_done;
1212 }
1213
1214 more:
1215 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1216 dev->name, rx_done, tx_done, limit);
1217 return limit;
1218
1219 oom:
1220 if (netif_msg_rx_err(ag))
1221 pr_info("%s: out of memory\n", dev->name);
1222
1223 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1224 napi_complete(napi);
1225 return 0;
1226 }
1227
1228 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1229 {
1230 struct net_device *dev = dev_id;
1231 struct ag71xx *ag = netdev_priv(dev);
1232 u32 status;
1233
1234 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1235 ag71xx_dump_intr(ag, "raw", status);
1236
1237 if (unlikely(!status))
1238 return IRQ_NONE;
1239
1240 if (unlikely(status & AG71XX_INT_ERR)) {
1241 if (status & AG71XX_INT_TX_BE) {
1242 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1243 dev_err(&dev->dev, "TX BUS error\n");
1244 }
1245 if (status & AG71XX_INT_RX_BE) {
1246 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1247 dev_err(&dev->dev, "RX BUS error\n");
1248 }
1249 }
1250
1251 if (likely(status & AG71XX_INT_POLL)) {
1252 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1253 DBG("%s: enable polling mode\n", dev->name);
1254 napi_schedule(&ag->napi);
1255 }
1256
1257 ag71xx_debugfs_update_int_stats(ag, status);
1258
1259 return IRQ_HANDLED;
1260 }
1261
1262 #ifdef CONFIG_NET_POLL_CONTROLLER
1263 /*
1264 * Polling 'interrupt' - used by things like netconsole to send skbs
1265 * without having to re-enable interrupts. It's not called while
1266 * the interrupt routine is executing.
1267 */
1268 static void ag71xx_netpoll(struct net_device *dev)
1269 {
1270 disable_irq(dev->irq);
1271 ag71xx_interrupt(dev->irq, dev);
1272 enable_irq(dev->irq);
1273 }
1274 #endif
1275
1276 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1277 {
1278 struct ag71xx *ag = netdev_priv(dev);
1279
1280 dev->mtu = new_mtu;
1281 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1282 ag71xx_max_frame_len(dev->mtu));
1283
1284 return 0;
1285 }
1286
1287 static const struct net_device_ops ag71xx_netdev_ops = {
1288 .ndo_open = ag71xx_open,
1289 .ndo_stop = ag71xx_stop,
1290 .ndo_start_xmit = ag71xx_hard_start_xmit,
1291 .ndo_do_ioctl = ag71xx_do_ioctl,
1292 .ndo_tx_timeout = ag71xx_tx_timeout,
1293 .ndo_change_mtu = ag71xx_change_mtu,
1294 .ndo_set_mac_address = eth_mac_addr,
1295 .ndo_validate_addr = eth_validate_addr,
1296 #ifdef CONFIG_NET_POLL_CONTROLLER
1297 .ndo_poll_controller = ag71xx_netpoll,
1298 #endif
1299 };
1300
1301 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1302 {
1303 switch (mode) {
1304 case PHY_INTERFACE_MODE_MII:
1305 return "MII";
1306 case PHY_INTERFACE_MODE_GMII:
1307 return "GMII";
1308 case PHY_INTERFACE_MODE_RMII:
1309 return "RMII";
1310 case PHY_INTERFACE_MODE_RGMII:
1311 return "RGMII";
1312 case PHY_INTERFACE_MODE_SGMII:
1313 return "SGMII";
1314 default:
1315 break;
1316 }
1317
1318 return "unknown";
1319 }
1320
1321 static int ag71xx_probe(struct platform_device *pdev)
1322 {
1323 struct device_node *np = pdev->dev.of_node;
1324 struct device_node *mdio_node;
1325 struct net_device *dev;
1326 struct resource *res;
1327 struct ag71xx *ag;
1328 const void *mac_addr;
1329 u32 max_frame_len;
1330 int tx_size, err;
1331
1332 if (!np)
1333 return -ENODEV;
1334
1335 dev = alloc_etherdev(sizeof(*ag));
1336 if (!dev)
1337 return -ENOMEM;
1338
1339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1340 if (!res)
1341 return -EINVAL;
1342
1343 err = ag71xx_setup_gmac(np);
1344 if (err)
1345 return err;
1346
1347 SET_NETDEV_DEV(dev, &pdev->dev);
1348
1349 ag = netdev_priv(dev);
1350 ag->pdev = pdev;
1351 ag->dev = dev;
1352 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1353 AG71XX_DEFAULT_MSG_ENABLE);
1354 spin_lock_init(&ag->lock);
1355
1356 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac");
1357 if (IS_ERR(ag->mac_reset)) {
1358 dev_err(&pdev->dev, "missing mac reset\n");
1359 err = PTR_ERR(ag->mac_reset);
1360 goto err_free;
1361 }
1362
1363 if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1364 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1365 of_device_is_compatible(np, "qca,ar7100-eth")) {
1366 ag->fifodata[0] = 0x0fff0000;
1367 ag->fifodata[1] = 0x00001fff;
1368 } else {
1369 ag->fifodata[0] = 0x0010ffff;
1370 ag->fifodata[1] = 0x015500aa;
1371 ag->fifodata[2] = 0x01f00140;
1372 }
1373 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1374 ag->fifodata[2] = 0x00780fff;
1375 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1376 ag->fifodata[2] = 0x008001ff;
1377 }
1378
1379 if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1380 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1381
1382 if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1383 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1384
1385 ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1386 if (IS_ERR(ag->pllregmap)) {
1387 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1388 ag->pllregmap = NULL;
1389 }
1390
1391 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1392 res->end - res->start + 1);
1393 if (!ag->mac_base) {
1394 err = -ENOMEM;
1395 goto err_free;
1396 }
1397 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1398 if (res) {
1399 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1400 res->end - res->start + 1);
1401 if (!ag->mii_base) {
1402 err = -ENOMEM;
1403 goto err_free;
1404 }
1405 }
1406
1407 dev->irq = platform_get_irq(pdev, 0);
1408 err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1409 0x0, dev_name(&pdev->dev), dev);
1410 if (err) {
1411 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1412 goto err_free;
1413 }
1414
1415 dev->netdev_ops = &ag71xx_netdev_ops;
1416 dev->ethtool_ops = &ag71xx_ethtool_ops;
1417
1418 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1419
1420 init_timer(&ag->oom_timer);
1421 ag->oom_timer.data = (unsigned long) dev;
1422 ag->oom_timer.function = ag71xx_oom_timer_handler;
1423
1424 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1425 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1426
1427 if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1428 of_device_is_compatible(np, "qca,qca9530-eth") ||
1429 of_device_is_compatible(np, "qca,qca9550-eth") ||
1430 of_device_is_compatible(np, "qca,qca9560-eth"))
1431 ag->desc_pktlen_mask = SZ_16K - 1;
1432 else
1433 ag->desc_pktlen_mask = SZ_4K - 1;
1434
1435 if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1436 !of_device_is_compatible(np, "qca,qca9550-eth") &&
1437 !of_device_is_compatible(np, "qca,qca9560-eth"))
1438 max_frame_len = ag->desc_pktlen_mask;
1439 else
1440 max_frame_len = 1540;
1441
1442 dev->min_mtu = 68;
1443 dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1444
1445 if (of_device_is_compatible(np, "qca,ar7240-eth"))
1446 ag->tx_hang_workaround = 1;
1447
1448 ag->rx_buf_offset = NET_SKB_PAD;
1449 if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1450 !of_device_is_compatible(np, "qca,ar9130-eth"))
1451 ag->rx_buf_offset += NET_IP_ALIGN;
1452
1453 if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1454 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1455 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1456 }
1457 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1458
1459 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1460 sizeof(struct ag71xx_desc),
1461 &ag->stop_desc_dma, GFP_KERNEL);
1462 if (!ag->stop_desc)
1463 goto err_free;
1464
1465 ag->stop_desc->data = 0;
1466 ag->stop_desc->ctrl = 0;
1467 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1468
1469 mac_addr = of_get_mac_address(np);
1470 if (mac_addr)
1471 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1472 if (!mac_addr || !is_valid_ether_addr(dev->dev_addr)) {
1473 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1474 eth_random_addr(dev->dev_addr);
1475 }
1476
1477 ag->phy_if_mode = of_get_phy_mode(np);
1478 if (ag->phy_if_mode < 0) {
1479 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1480 err = ag->phy_if_mode;
1481 goto err_free;
1482 }
1483
1484 if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
1485 ag->mac_idx = -1;
1486 if (ag->mii_base)
1487 switch (ag->mac_idx) {
1488 case 0:
1489 ath79_mii0_ctrl_set_if(ag);
1490 break;
1491 case 1:
1492 ath79_mii1_ctrl_set_if(ag);
1493 break;
1494 default:
1495 break;
1496 }
1497
1498 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1499
1500 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1501 ag71xx_hw_init(ag);
1502
1503 if(!of_device_is_compatible(np, "simple-mfd")) {
1504 mdio_node = of_get_child_by_name(np, "mdio-bus");
1505 if(!IS_ERR(mdio_node))
1506 of_platform_device_create(mdio_node, NULL, NULL);
1507 }
1508
1509 err = ag71xx_phy_connect(ag);
1510 if (err)
1511 goto err_free;
1512
1513 err = ag71xx_debugfs_init(ag);
1514 if (err)
1515 goto err_phy_disconnect;
1516
1517 platform_set_drvdata(pdev, dev);
1518
1519 err = register_netdev(dev);
1520 if (err) {
1521 dev_err(&pdev->dev, "unable to register net device\n");
1522 platform_set_drvdata(pdev, NULL);
1523 ag71xx_debugfs_exit(ag);
1524 goto err_phy_disconnect;
1525 }
1526
1527 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1528 dev->name, (unsigned long) ag->mac_base, dev->irq,
1529 ag71xx_get_phy_if_mode_name(ag->phy_if_mode));
1530
1531 return 0;
1532
1533 err_phy_disconnect:
1534 ag71xx_phy_disconnect(ag);
1535 err_free:
1536 free_netdev(dev);
1537 return err;
1538 }
1539
1540 static int ag71xx_remove(struct platform_device *pdev)
1541 {
1542 struct net_device *dev = platform_get_drvdata(pdev);
1543 struct ag71xx *ag;
1544
1545 if (!dev)
1546 return 0;
1547
1548 ag = netdev_priv(dev);
1549 ag71xx_debugfs_exit(ag);
1550 ag71xx_phy_disconnect(ag);
1551 unregister_netdev(dev);
1552 free_irq(dev->irq, dev);
1553 iounmap(ag->mac_base);
1554 kfree(dev);
1555 platform_set_drvdata(pdev, NULL);
1556
1557 return 0;
1558 }
1559
1560 static const struct of_device_id ag71xx_match[] = {
1561 { .compatible = "qca,ar7100-eth" },
1562 { .compatible = "qca,ar7240-eth" },
1563 { .compatible = "qca,ar7241-eth" },
1564 { .compatible = "qca,ar7242-eth" },
1565 { .compatible = "qca,ar9130-eth" },
1566 { .compatible = "qca,ar9330-eth" },
1567 { .compatible = "qca,ar9340-eth" },
1568 { .compatible = "qca,qca9530-eth" },
1569 { .compatible = "qca,qca9550-eth" },
1570 { .compatible = "qca,qca9560-eth" },
1571 {}
1572 };
1573
1574 static struct platform_driver ag71xx_driver = {
1575 .probe = ag71xx_probe,
1576 .remove = ag71xx_remove,
1577 .driver = {
1578 .name = AG71XX_DRV_NAME,
1579 .of_match_table = ag71xx_match,
1580 }
1581 };
1582
1583 static int __init ag71xx_module_init(void)
1584 {
1585 int ret;
1586
1587 ret = ag71xx_debugfs_root_init();
1588 if (ret)
1589 goto err_out;
1590
1591 ret = platform_driver_register(&ag71xx_driver);
1592 if (ret)
1593 goto err_debugfs_exit;
1594
1595 return 0;
1596
1597 err_debugfs_exit:
1598 ag71xx_debugfs_root_exit();
1599 err_out:
1600 return ret;
1601 }
1602
1603 static void __exit ag71xx_module_exit(void)
1604 {
1605 platform_driver_unregister(&ag71xx_driver);
1606 ag71xx_debugfs_root_exit();
1607 }
1608
1609 module_init(ag71xx_module_init);
1610 module_exit(ag71xx_module_exit);
1611
1612 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1613 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1614 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1615 MODULE_LICENSE("GPL v2");
1616 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository