2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
51 AR8XXX_VER_AR8216
= 0x01,
52 AR8XXX_VER_AR8236
= 0x03,
53 AR8XXX_VER_AR8316
= 0x10,
54 AR8XXX_VER_AR8327
= 0x12,
57 struct ar8xxx_mib_desc
{
66 int (*hw_init
)(struct ar8216_priv
*priv
);
67 void (*init_globals
)(struct ar8216_priv
*priv
);
68 void (*init_port
)(struct ar8216_priv
*priv
, int port
);
69 void (*setup_port
)(struct ar8216_priv
*priv
, int port
, u32 egress
,
70 u32 ingress
, u32 members
, u32 pvid
);
71 u32 (*read_port_status
)(struct ar8216_priv
*priv
, int port
);
72 int (*atu_flush
)(struct ar8216_priv
*priv
);
73 void (*vtu_flush
)(struct ar8216_priv
*priv
);
74 void (*vtu_load_vlan
)(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
);
76 const struct ar8xxx_mib_desc
*mib_decs
;
81 struct switch_dev dev
;
82 struct mii_bus
*mii_bus
;
83 struct phy_device
*phy
;
84 u32 (*read
)(struct ar8216_priv
*priv
, int reg
);
85 void (*write
)(struct ar8216_priv
*priv
, int reg
, u32 val
);
86 const struct net_device_ops
*ndo_old
;
87 struct net_device_ops ndo
;
88 struct mutex reg_mutex
;
91 const struct ar8xxx_chip
*chip
;
99 struct mutex mib_lock
;
100 struct delayed_work mib_work
;
104 /* all fields below are cleared on reset */
106 u16 vlan_id
[AR8X16_MAX_VLANS
];
107 u8 vlan_table
[AR8X16_MAX_VLANS
];
109 u16 pvid
[AR8X16_MAX_PORTS
];
112 #define MIB_DESC(_s , _o, _n) \
119 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
120 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
121 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
122 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
123 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
124 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
125 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
126 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
127 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
128 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
129 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
130 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
131 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
132 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
133 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
134 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
135 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
136 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
137 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
138 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
139 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
140 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
141 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
142 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
143 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
144 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
145 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
146 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
147 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
148 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
149 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
150 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
151 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
152 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
153 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
154 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
155 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
156 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
159 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
160 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
161 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
162 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
163 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
164 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
165 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
166 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
167 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
168 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
169 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
170 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
171 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
172 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
173 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
174 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
175 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
176 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
177 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
178 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
179 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
180 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
181 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
182 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
183 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
184 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
185 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
186 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
187 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
188 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
189 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
190 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
191 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
192 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
193 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
194 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
195 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
196 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
197 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
198 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
201 static inline struct ar8216_priv
*
202 swdev_to_ar8216(struct switch_dev
*swdev
)
204 return container_of(swdev
, struct ar8216_priv
, dev
);
207 static inline bool ar8xxx_has_gige(struct ar8216_priv
*priv
)
209 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
212 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv
*priv
)
214 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
217 static inline bool chip_is_ar8216(struct ar8216_priv
*priv
)
219 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
222 static inline bool chip_is_ar8236(struct ar8216_priv
*priv
)
224 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
227 static inline bool chip_is_ar8316(struct ar8216_priv
*priv
)
229 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
232 static inline bool chip_is_ar8327(struct ar8216_priv
*priv
)
234 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
238 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
241 *r1
= regaddr
& 0x1e;
247 *page
= regaddr
& 0x1ff;
251 ar8216_mii_read(struct ar8216_priv
*priv
, int reg
)
253 struct mii_bus
*bus
= priv
->mii_bus
;
257 split_addr((u32
) reg
, &r1
, &r2
, &page
);
259 mutex_lock(&bus
->mdio_lock
);
261 bus
->write(bus
, 0x18, 0, page
);
262 usleep_range(1000, 2000); /* wait for the page switch to propagate */
263 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
264 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
266 mutex_unlock(&bus
->mdio_lock
);
268 return (hi
<< 16) | lo
;
272 ar8216_mii_write(struct ar8216_priv
*priv
, int reg
, u32 val
)
274 struct mii_bus
*bus
= priv
->mii_bus
;
278 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
280 hi
= (u16
) (val
>> 16);
282 mutex_lock(&bus
->mdio_lock
);
284 bus
->write(bus
, 0x18, 0, r3
);
285 usleep_range(1000, 2000); /* wait for the page switch to propagate */
286 if (priv
->mii_lo_first
) {
287 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
288 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
290 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
291 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
294 mutex_unlock(&bus
->mdio_lock
);
298 ar8216_phy_dbg_write(struct ar8216_priv
*priv
, int phy_addr
,
299 u16 dbg_addr
, u16 dbg_data
)
301 struct mii_bus
*bus
= priv
->mii_bus
;
303 mutex_lock(&bus
->mdio_lock
);
304 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
305 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
306 mutex_unlock(&bus
->mdio_lock
);
310 ar8216_phy_mmd_write(struct ar8216_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
312 struct mii_bus
*bus
= priv
->mii_bus
;
314 mutex_lock(&bus
->mdio_lock
);
315 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
316 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
317 mutex_unlock(&bus
->mdio_lock
);
321 ar8216_rmw(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
325 lockdep_assert_held(&priv
->reg_mutex
);
327 v
= priv
->read(priv
, reg
);
330 priv
->write(priv
, reg
, v
);
336 ar8216_reg_set(struct ar8216_priv
*priv
, int reg
, u32 val
)
340 lockdep_assert_held(&priv
->reg_mutex
);
342 v
= priv
->read(priv
, reg
);
344 priv
->write(priv
, reg
, v
);
348 ar8216_reg_wait(struct ar8216_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
353 for (i
= 0; i
< timeout
; i
++) {
356 t
= priv
->read(priv
, reg
);
357 if ((t
& mask
) == val
)
360 usleep_range(1000, 2000);
367 ar8216_mib_op(struct ar8216_priv
*priv
, u32 op
)
372 lockdep_assert_held(&priv
->mib_lock
);
374 if (chip_is_ar8327(priv
))
375 mib_func
= AR8327_REG_MIB_FUNC
;
377 mib_func
= AR8216_REG_MIB_FUNC
;
379 mutex_lock(&priv
->reg_mutex
);
380 /* Capture the hardware statistics for all ports */
381 ar8216_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
382 mutex_unlock(&priv
->reg_mutex
);
384 /* Wait for the capturing to complete. */
385 ret
= ar8216_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
396 ar8216_mib_capture(struct ar8216_priv
*priv
)
398 return ar8216_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
402 ar8216_mib_flush(struct ar8216_priv
*priv
)
404 return ar8216_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
408 ar8216_mib_fetch_port_stat(struct ar8216_priv
*priv
, int port
, bool flush
)
414 WARN_ON(port
>= priv
->dev
.ports
);
416 lockdep_assert_held(&priv
->mib_lock
);
418 if (chip_is_ar8327(priv
))
419 base
= AR8327_REG_PORT_STATS_BASE(port
);
420 else if (chip_is_ar8236(priv
) ||
421 chip_is_ar8316(priv
))
422 base
= AR8236_REG_PORT_STATS_BASE(port
);
424 base
= AR8216_REG_PORT_STATS_BASE(port
);
426 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
427 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
428 const struct ar8xxx_mib_desc
*mib
;
431 mib
= &priv
->chip
->mib_decs
[i
];
432 t
= priv
->read(priv
, base
+ mib
->offset
);
433 if (mib
->size
== 2) {
436 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
448 ar8216_read_port_link(struct ar8216_priv
*priv
, int port
,
449 struct switch_port_link
*link
)
454 memset(link
, '\0', sizeof(*link
));
456 status
= priv
->chip
->read_port_status(priv
, port
);
458 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
460 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
467 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
468 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
469 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
471 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
472 AR8216_PORT_STATUS_SPEED_S
;
475 case AR8216_PORT_SPEED_10M
:
476 link
->speed
= SWITCH_PORT_SPEED_10
;
478 case AR8216_PORT_SPEED_100M
:
479 link
->speed
= SWITCH_PORT_SPEED_100
;
481 case AR8216_PORT_SPEED_1000M
:
482 link
->speed
= SWITCH_PORT_SPEED_1000
;
485 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
490 static struct sk_buff
*
491 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
493 struct ar8216_priv
*priv
= dev
->phy_ptr
;
502 if (unlikely(skb_headroom(skb
) < 2)) {
503 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
507 buf
= skb_push(skb
, 2);
515 dev_kfree_skb_any(skb
);
520 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
522 struct ar8216_priv
*priv
;
530 /* don't strip the header if vlan mode is disabled */
534 /* strip header, get vlan id */
538 /* check for vlan header presence */
539 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
544 /* no need to fix up packets coming from a tagged source */
545 if (priv
->vlan_tagged
& (1 << port
))
548 /* lookup port vid from local table, the switch passes an invalid vlan id */
549 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
552 buf
[14 + 2] |= vlan
>> 8;
553 buf
[15 + 2] = vlan
& 0xff;
557 ar8216_wait_bit(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
563 t
= priv
->read(priv
, reg
);
564 if ((t
& mask
) == val
)
573 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
574 (unsigned int) reg
, t
, mask
, val
);
579 ar8216_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
581 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
583 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
584 val
&= AR8216_VTUDATA_MEMBER
;
585 val
|= AR8216_VTUDATA_VALID
;
586 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
588 op
|= AR8216_VTU_ACTIVE
;
589 priv
->write(priv
, AR8216_REG_VTU
, op
);
593 ar8216_vtu_flush(struct ar8216_priv
*priv
)
595 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
599 ar8216_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
603 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
604 ar8216_vtu_op(priv
, op
, port_mask
);
608 ar8216_atu_flush(struct ar8216_priv
*priv
)
612 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
614 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
620 ar8216_read_port_status(struct ar8216_priv
*priv
, int port
)
622 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
626 ar8216_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
627 u32 members
, u32 pvid
)
631 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
632 header
= AR8216_PORT_CTRL_HEADER
;
636 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
637 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
638 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
639 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
640 AR8216_PORT_CTRL_LEARN
| header
|
641 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
642 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
644 ar8216_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
645 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
646 AR8216_PORT_VLAN_DEFAULT_ID
,
647 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
648 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
649 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
653 ar8216_hw_init(struct ar8216_priv
*priv
)
659 ar8216_init_globals(struct ar8216_priv
*priv
)
661 /* standard atheros magic */
662 priv
->write(priv
, 0x38, 0xc000050e);
664 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
665 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
669 ar8216_init_port(struct ar8216_priv
*priv
, int port
)
671 /* Enable port learning and tx */
672 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
673 AR8216_PORT_CTRL_LEARN
|
674 (4 << AR8216_PORT_CTRL_STATE_S
));
676 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
678 if (port
== AR8216_PORT_CPU
) {
679 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
680 AR8216_PORT_STATUS_LINK_UP
|
681 (ar8xxx_has_gige(priv
) ?
682 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
683 AR8216_PORT_STATUS_TXMAC
|
684 AR8216_PORT_STATUS_RXMAC
|
685 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
686 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
687 AR8216_PORT_STATUS_DUPLEX
);
689 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
690 AR8216_PORT_STATUS_LINK_AUTO
);
694 static const struct ar8xxx_chip ar8216_chip
= {
695 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
697 .hw_init
= ar8216_hw_init
,
698 .init_globals
= ar8216_init_globals
,
699 .init_port
= ar8216_init_port
,
700 .setup_port
= ar8216_setup_port
,
701 .read_port_status
= ar8216_read_port_status
,
702 .atu_flush
= ar8216_atu_flush
,
703 .vtu_flush
= ar8216_vtu_flush
,
704 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
706 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
707 .mib_decs
= ar8216_mibs
,
711 ar8236_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
712 u32 members
, u32 pvid
)
714 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
715 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
716 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
717 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
718 AR8216_PORT_CTRL_LEARN
|
719 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
720 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
722 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
723 AR8236_PORT_VLAN_DEFAULT_ID
,
724 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
726 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
727 AR8236_PORT_VLAN2_VLAN_MODE
|
728 AR8236_PORT_VLAN2_MEMBER
,
729 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
730 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
734 ar8236_hw_init(struct ar8216_priv
*priv
)
739 if (priv
->initialized
)
742 /* Initialize the PHYs */
744 for (i
= 0; i
< 5; i
++) {
745 mdiobus_write(bus
, i
, MII_ADVERTISE
,
746 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
747 ADVERTISE_PAUSE_ASYM
);
748 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
752 priv
->initialized
= true;
757 ar8236_init_globals(struct ar8216_priv
*priv
)
759 /* enable jumbo frames */
760 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
761 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
763 /* Enable MIB counters */
764 ar8216_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
765 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
769 static const struct ar8xxx_chip ar8236_chip
= {
770 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
771 .hw_init
= ar8236_hw_init
,
772 .init_globals
= ar8236_init_globals
,
773 .init_port
= ar8216_init_port
,
774 .setup_port
= ar8236_setup_port
,
775 .read_port_status
= ar8216_read_port_status
,
776 .atu_flush
= ar8216_atu_flush
,
777 .vtu_flush
= ar8216_vtu_flush
,
778 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
780 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
781 .mib_decs
= ar8236_mibs
,
785 ar8316_hw_init(struct ar8216_priv
*priv
)
791 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
793 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
794 if (priv
->port4_phy
) {
795 /* value taken from Ubiquiti RouterStation Pro */
797 printk(KERN_INFO
"ar8316: Using port 4 as PHY\n");
800 printk(KERN_INFO
"ar8316: Using port 4 as switch port\n");
802 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
803 /* value taken from AVM Fritz!Box 7390 sources */
806 /* no known value for phy interface */
807 printk(KERN_ERR
"ar8316: unsupported mii mode: %d.\n",
808 priv
->phy
->interface
);
815 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
817 /* Initialize the ports */
819 for (i
= 0; i
< 5; i
++) {
820 if ((i
== 4) && priv
->port4_phy
&&
821 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
822 /* work around for phy4 rgmii mode */
823 ar8216_phy_dbg_write(priv
, i
, 0x12, 0x480c);
825 ar8216_phy_dbg_write(priv
, i
, 0x0, 0x824e);
827 ar8216_phy_dbg_write(priv
, i
, 0x5, 0x3d47);
831 /* initialize the port itself */
832 mdiobus_write(bus
, i
, MII_ADVERTISE
,
833 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
834 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
835 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
841 priv
->initialized
= true;
846 ar8316_init_globals(struct ar8216_priv
*priv
)
848 /* standard atheros magic */
849 priv
->write(priv
, 0x38, 0xc000050e);
851 /* enable cpu port to receive multicast and broadcast frames */
852 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
854 /* enable jumbo frames */
855 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
856 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
858 /* Enable MIB counters */
859 ar8216_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
860 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
864 static const struct ar8xxx_chip ar8316_chip
= {
865 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
866 .hw_init
= ar8316_hw_init
,
867 .init_globals
= ar8316_init_globals
,
868 .init_port
= ar8216_init_port
,
869 .setup_port
= ar8216_setup_port
,
870 .read_port_status
= ar8216_read_port_status
,
871 .atu_flush
= ar8216_atu_flush
,
872 .vtu_flush
= ar8216_vtu_flush
,
873 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
875 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
876 .mib_decs
= ar8236_mibs
,
880 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
892 case AR8327_PAD_MAC2MAC_MII
:
893 t
= AR8327_PAD_MAC_MII_EN
;
895 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
897 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
900 case AR8327_PAD_MAC2MAC_GMII
:
901 t
= AR8327_PAD_MAC_GMII_EN
;
903 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
905 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
908 case AR8327_PAD_MAC_SGMII
:
909 t
= AR8327_PAD_SGMII_EN
;
912 * WAR for the QUalcomm Atheros AP136 board.
913 * It seems that RGMII TX/RX delay settings needs to be
914 * applied for SGMII mode as well, The ethernet is not
915 * reliable without this.
917 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
918 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
919 if (cfg
->rxclk_delay_en
)
920 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
921 if (cfg
->txclk_delay_en
)
922 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
924 if (cfg
->sgmii_delay_en
)
925 t
|= AR8327_PAD_SGMII_DELAY_EN
;
929 case AR8327_PAD_MAC2PHY_MII
:
930 t
= AR8327_PAD_PHY_MII_EN
;
932 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
934 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
937 case AR8327_PAD_MAC2PHY_GMII
:
938 t
= AR8327_PAD_PHY_GMII_EN
;
939 if (cfg
->pipe_rxclk_sel
)
940 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
942 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
944 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
947 case AR8327_PAD_MAC_RGMII
:
948 t
= AR8327_PAD_RGMII_EN
;
949 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
950 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
951 if (cfg
->rxclk_delay_en
)
952 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
953 if (cfg
->txclk_delay_en
)
954 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
957 case AR8327_PAD_PHY_GMII
:
958 t
= AR8327_PAD_PHYX_GMII_EN
;
961 case AR8327_PAD_PHY_RGMII
:
962 t
= AR8327_PAD_PHYX_RGMII_EN
;
965 case AR8327_PAD_PHY_MII
:
966 t
= AR8327_PAD_PHYX_MII_EN
;
974 ar8327_phy_fixup(struct ar8216_priv
*priv
, int phy
)
976 switch (priv
->chip_rev
) {
978 /* For 100M waveform */
979 ar8216_phy_dbg_write(priv
, phy
, 0, 0x02ea);
980 /* Turn on Gigabit clock */
981 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
985 ar8216_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
986 ar8216_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
989 ar8216_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
990 ar8216_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
992 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
993 ar8216_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
994 ar8216_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1000 ar8327_hw_init(struct ar8216_priv
*priv
)
1002 struct ar8327_platform_data
*pdata
;
1003 struct ar8327_led_cfg
*led_cfg
;
1004 struct mii_bus
*bus
;
1009 pdata
= priv
->phy
->dev
.platform_data
;
1013 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1014 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1015 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1016 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1017 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1018 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1020 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1023 led_cfg
= pdata
->led_cfg
;
1025 if (led_cfg
->open_drain
)
1026 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1028 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1030 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1031 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1032 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1033 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1036 if (new_pos
!= pos
) {
1037 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1038 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1041 bus
= priv
->mii_bus
;
1042 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
1043 ar8327_phy_fixup(priv
, i
);
1045 /* start aneg on the PHY */
1046 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
1047 ADVERTISE_PAUSE_CAP
|
1048 ADVERTISE_PAUSE_ASYM
);
1049 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
1050 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1059 ar8327_init_globals(struct ar8216_priv
*priv
)
1063 /* enable CPU port and disable mirror port */
1064 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1065 AR8327_FWD_CTRL0_MIRROR_PORT
;
1066 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1068 /* forward multicast and broadcast frames to CPU */
1069 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1070 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1071 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1072 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1075 ar8216_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1076 AR8327_MAX_FRAME_SIZE_MTU
, 1518 + 8 + 2);
1078 /* Enable MIB counters */
1079 ar8216_reg_set(priv
, AR8327_REG_MODULE_EN
,
1080 AR8327_MODULE_EN_MIB
);
1084 ar8327_config_port(struct ar8216_priv
*priv
, unsigned int port
,
1085 struct ar8327_port_cfg
*cfg
)
1089 if (!cfg
|| !cfg
->force_link
) {
1090 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
),
1091 AR8216_PORT_STATUS_LINK_AUTO
);
1095 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1096 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1097 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1098 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1100 switch (cfg
->speed
) {
1101 case AR8327_PORT_SPEED_10
:
1102 t
|= AR8216_PORT_SPEED_10M
;
1104 case AR8327_PORT_SPEED_100
:
1105 t
|= AR8216_PORT_SPEED_100M
;
1107 case AR8327_PORT_SPEED_1000
:
1108 t
|= AR8216_PORT_SPEED_1000M
;
1112 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1116 ar8327_init_port(struct ar8216_priv
*priv
, int port
)
1118 struct ar8327_platform_data
*pdata
;
1119 struct ar8327_port_cfg
*cfg
;
1122 pdata
= priv
->phy
->dev
.platform_data
;
1124 if (pdata
&& port
== AR8216_PORT_CPU
)
1125 cfg
= &pdata
->port0_cfg
;
1126 else if (pdata
&& port
== 6)
1127 cfg
= &pdata
->port6_cfg
;
1131 ar8327_config_port(priv
, port
, cfg
);
1133 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1135 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1136 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1137 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1139 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1140 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1142 t
= AR8327_PORT_LOOKUP_LEARN
;
1143 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1144 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1148 ar8327_read_port_status(struct ar8216_priv
*priv
, int port
)
1150 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1154 ar8327_atu_flush(struct ar8216_priv
*priv
)
1158 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1159 AR8327_ATU_FUNC_BUSY
, 0);
1161 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1162 AR8327_ATU_FUNC_OP_FLUSH
);
1168 ar8327_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
1170 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1171 AR8327_VTU_FUNC1_BUSY
, 0))
1174 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1175 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1177 op
|= AR8327_VTU_FUNC1_BUSY
;
1178 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1182 ar8327_vtu_flush(struct ar8216_priv
*priv
)
1184 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1188 ar8327_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
1194 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1195 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1196 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1199 if ((port_mask
& BIT(i
)) == 0)
1200 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1201 else if (priv
->vlan
== 0)
1202 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1203 else if (priv
->vlan_tagged
& BIT(i
))
1204 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1206 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1208 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1210 ar8327_vtu_op(priv
, op
, val
);
1214 ar8327_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
1215 u32 members
, u32 pvid
)
1220 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1221 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1222 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1224 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1226 case AR8216_OUT_KEEP
:
1227 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1229 case AR8216_OUT_STRIP_VLAN
:
1230 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
1232 case AR8216_OUT_ADD_VLAN
:
1233 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
1237 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1238 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1239 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1242 t
|= AR8327_PORT_LOOKUP_LEARN
;
1243 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1244 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1245 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1248 static const struct ar8xxx_chip ar8327_chip
= {
1249 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1250 .hw_init
= ar8327_hw_init
,
1251 .init_globals
= ar8327_init_globals
,
1252 .init_port
= ar8327_init_port
,
1253 .setup_port
= ar8327_setup_port
,
1254 .read_port_status
= ar8327_read_port_status
,
1255 .atu_flush
= ar8327_atu_flush
,
1256 .vtu_flush
= ar8327_vtu_flush
,
1257 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1259 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1260 .mib_decs
= ar8236_mibs
,
1264 ar8216_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1265 struct switch_val
*val
)
1267 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1268 priv
->vlan
= !!val
->value
.i
;
1273 ar8216_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1274 struct switch_val
*val
)
1276 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1277 val
->value
.i
= priv
->vlan
;
1283 ar8216_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1285 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1287 /* make sure no invalid PVIDs get set */
1289 if (vlan
>= dev
->vlans
)
1292 priv
->pvid
[port
] = vlan
;
1297 ar8216_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1299 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1300 *vlan
= priv
->pvid
[port
];
1305 ar8216_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1306 struct switch_val
*val
)
1308 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1309 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1314 ar8216_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1315 struct switch_val
*val
)
1317 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1318 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1323 ar8216_sw_get_port_link(struct switch_dev
*dev
, int port
,
1324 struct switch_port_link
*link
)
1326 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1328 ar8216_read_port_link(priv
, port
, link
);
1333 ar8216_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1335 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1336 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1340 for (i
= 0; i
< dev
->ports
; i
++) {
1341 struct switch_port
*p
;
1343 if (!(ports
& (1 << i
)))
1346 p
= &val
->value
.ports
[val
->len
++];
1348 if (priv
->vlan_tagged
& (1 << i
))
1349 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1357 ar8216_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1359 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1360 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1364 for (i
= 0; i
< val
->len
; i
++) {
1365 struct switch_port
*p
= &val
->value
.ports
[i
];
1367 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1368 priv
->vlan_tagged
|= (1 << p
->id
);
1370 priv
->vlan_tagged
&= ~(1 << p
->id
);
1371 priv
->pvid
[p
->id
] = val
->port_vlan
;
1373 /* make sure that an untagged port does not
1374 * appear in other vlans */
1375 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1376 if (j
== val
->port_vlan
)
1378 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1388 ar8216_sw_hw_apply(struct switch_dev
*dev
)
1390 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1391 u8 portmask
[AR8X16_MAX_PORTS
];
1394 mutex_lock(&priv
->reg_mutex
);
1395 /* flush all vlan translation unit entries */
1396 priv
->chip
->vtu_flush(priv
);
1398 memset(portmask
, 0, sizeof(portmask
));
1400 /* calculate the port destination masks and load vlans
1401 * into the vlan translation unit */
1402 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1403 u8 vp
= priv
->vlan_table
[j
];
1408 for (i
= 0; i
< dev
->ports
; i
++) {
1411 portmask
[i
] |= vp
& ~mask
;
1414 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1415 priv
->vlan_table
[j
]);
1419 * isolate all ports, but connect them to the cpu port */
1420 for (i
= 0; i
< dev
->ports
; i
++) {
1421 if (i
== AR8216_PORT_CPU
)
1424 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1425 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1429 /* update the port destination mask registers and tag settings */
1430 for (i
= 0; i
< dev
->ports
; i
++) {
1431 int egress
, ingress
;
1435 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1436 if (priv
->vlan_tagged
& (1 << i
))
1437 egress
= AR8216_OUT_ADD_VLAN
;
1439 egress
= AR8216_OUT_STRIP_VLAN
;
1440 ingress
= AR8216_IN_SECURE
;
1443 egress
= AR8216_OUT_KEEP
;
1444 ingress
= AR8216_IN_PORT_ONLY
;
1447 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1450 mutex_unlock(&priv
->reg_mutex
);
1455 ar8216_sw_reset_switch(struct switch_dev
*dev
)
1457 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1460 mutex_lock(&priv
->reg_mutex
);
1461 memset(&priv
->vlan
, 0, sizeof(struct ar8216_priv
) -
1462 offsetof(struct ar8216_priv
, vlan
));
1464 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1465 priv
->vlan_id
[i
] = i
;
1467 /* Configure all ports */
1468 for (i
= 0; i
< dev
->ports
; i
++)
1469 priv
->chip
->init_port(priv
, i
);
1471 priv
->chip
->init_globals(priv
);
1472 mutex_unlock(&priv
->reg_mutex
);
1474 return ar8216_sw_hw_apply(dev
);
1478 ar8216_sw_set_reset_mibs(struct switch_dev
*dev
,
1479 const struct switch_attr
*attr
,
1480 struct switch_val
*val
)
1482 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1486 if (!ar8xxx_has_mib_counters(priv
))
1489 mutex_lock(&priv
->mib_lock
);
1491 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1492 sizeof(*priv
->mib_stats
);
1493 memset(priv
->mib_stats
, '\0', len
);
1494 ret
= ar8216_mib_flush(priv
);
1501 mutex_unlock(&priv
->mib_lock
);
1506 ar8216_sw_set_port_reset_mib(struct switch_dev
*dev
,
1507 const struct switch_attr
*attr
,
1508 struct switch_val
*val
)
1510 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1514 if (!ar8xxx_has_mib_counters(priv
))
1517 port
= val
->port_vlan
;
1518 if (port
>= dev
->ports
)
1521 mutex_lock(&priv
->mib_lock
);
1522 ret
= ar8216_mib_capture(priv
);
1526 ar8216_mib_fetch_port_stat(priv
, port
, true);
1531 mutex_unlock(&priv
->mib_lock
);
1536 ar8216_sw_get_port_mib(struct switch_dev
*dev
,
1537 const struct switch_attr
*attr
,
1538 struct switch_val
*val
)
1540 struct ar8216_priv
*priv
= swdev_to_ar8216(dev
);
1541 const struct ar8xxx_chip
*chip
= priv
->chip
;
1545 char *buf
= priv
->buf
;
1548 if (!ar8xxx_has_mib_counters(priv
))
1551 port
= val
->port_vlan
;
1552 if (port
>= dev
->ports
)
1555 mutex_lock(&priv
->mib_lock
);
1556 ret
= ar8216_mib_capture(priv
);
1560 ar8216_mib_fetch_port_stat(priv
, port
, false);
1562 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1563 "Port %d MIB counters\n",
1566 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1567 for (i
= 0; i
< chip
->num_mibs
; i
++)
1568 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1570 chip
->mib_decs
[i
].name
,
1579 mutex_unlock(&priv
->mib_lock
);
1583 static struct switch_attr ar8216_globals
[] = {
1585 .type
= SWITCH_TYPE_INT
,
1586 .name
= "enable_vlan",
1587 .description
= "Enable VLAN mode",
1588 .set
= ar8216_sw_set_vlan
,
1589 .get
= ar8216_sw_get_vlan
,
1593 .type
= SWITCH_TYPE_NOVAL
,
1594 .name
= "reset_mibs",
1595 .description
= "Reset all MIB counters",
1596 .set
= ar8216_sw_set_reset_mibs
,
1601 static struct switch_attr ar8216_port
[] = {
1603 .type
= SWITCH_TYPE_NOVAL
,
1604 .name
= "reset_mib",
1605 .description
= "Reset single port MIB counters",
1606 .set
= ar8216_sw_set_port_reset_mib
,
1609 .type
= SWITCH_TYPE_STRING
,
1611 .description
= "Get port's MIB counters",
1613 .get
= ar8216_sw_get_port_mib
,
1617 static struct switch_attr ar8216_vlan
[] = {
1619 .type
= SWITCH_TYPE_INT
,
1621 .description
= "VLAN ID (0-4094)",
1622 .set
= ar8216_sw_set_vid
,
1623 .get
= ar8216_sw_get_vid
,
1628 static const struct switch_dev_ops ar8216_sw_ops
= {
1630 .attr
= ar8216_globals
,
1631 .n_attr
= ARRAY_SIZE(ar8216_globals
),
1634 .attr
= ar8216_port
,
1635 .n_attr
= ARRAY_SIZE(ar8216_port
),
1638 .attr
= ar8216_vlan
,
1639 .n_attr
= ARRAY_SIZE(ar8216_vlan
),
1641 .get_port_pvid
= ar8216_sw_get_pvid
,
1642 .set_port_pvid
= ar8216_sw_set_pvid
,
1643 .get_vlan_ports
= ar8216_sw_get_ports
,
1644 .set_vlan_ports
= ar8216_sw_set_ports
,
1645 .apply_config
= ar8216_sw_hw_apply
,
1646 .reset_switch
= ar8216_sw_reset_switch
,
1647 .get_port_link
= ar8216_sw_get_port_link
,
1651 ar8216_id_chip(struct ar8216_priv
*priv
)
1657 val
= priv
->read(priv
, AR8216_REG_CTRL
);
1661 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1662 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1665 val
= priv
->read(priv
, AR8216_REG_CTRL
);
1669 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1674 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1675 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1677 switch (priv
->chip_ver
) {
1678 case AR8XXX_VER_AR8216
:
1679 priv
->chip
= &ar8216_chip
;
1681 case AR8XXX_VER_AR8236
:
1682 priv
->chip
= &ar8236_chip
;
1684 case AR8XXX_VER_AR8316
:
1685 priv
->chip
= &ar8316_chip
;
1687 case AR8XXX_VER_AR8327
:
1688 priv
->mii_lo_first
= true;
1689 priv
->chip
= &ar8327_chip
;
1693 "ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1694 priv
->chip_ver
, priv
->chip_rev
);
1703 ar8xxx_mib_work_func(struct work_struct
*work
)
1705 struct ar8216_priv
*priv
;
1708 priv
= container_of(work
, struct ar8216_priv
, mib_work
.work
);
1710 mutex_lock(&priv
->mib_lock
);
1712 err
= ar8216_mib_capture(priv
);
1716 ar8216_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1719 priv
->mib_next_port
++;
1720 if (priv
->mib_next_port
>= priv
->dev
.ports
)
1721 priv
->mib_next_port
= 0;
1723 mutex_unlock(&priv
->mib_lock
);
1724 schedule_delayed_work(&priv
->mib_work
,
1725 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1729 ar8xxx_mib_init(struct ar8216_priv
*priv
)
1733 if (!ar8xxx_has_mib_counters(priv
))
1736 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1738 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1739 sizeof(*priv
->mib_stats
);
1740 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1742 if (!priv
->mib_stats
)
1745 mutex_init(&priv
->mib_lock
);
1746 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1752 ar8xxx_mib_start(struct ar8216_priv
*priv
)
1754 if (!ar8xxx_has_mib_counters(priv
))
1757 schedule_delayed_work(&priv
->mib_work
,
1758 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1762 ar8xxx_mib_cleanup(struct ar8216_priv
*priv
)
1764 if (!ar8xxx_has_mib_counters(priv
))
1767 cancel_delayed_work(&priv
->mib_work
);
1768 kfree(priv
->mib_stats
);
1772 ar8216_config_init(struct phy_device
*pdev
)
1774 struct ar8216_priv
*priv
= pdev
->priv
;
1775 struct net_device
*dev
= pdev
->attached_dev
;
1776 struct switch_dev
*swdev
;
1780 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
1784 priv
->mii_bus
= pdev
->bus
;
1785 priv
->read
= ar8216_mii_read
;
1786 priv
->write
= ar8216_mii_write
;
1788 ret
= ar8216_id_chip(priv
);
1795 if (ar8xxx_has_gige(priv
))
1796 pdev
->supported
= SUPPORTED_1000baseT_Full
;
1798 pdev
->supported
= SUPPORTED_100baseT_Full
;
1799 pdev
->advertising
= pdev
->supported
;
1801 if (pdev
->addr
!= 0) {
1802 if (chip_is_ar8316(priv
)) {
1803 /* check if we're attaching to the switch twice */
1804 pdev
= pdev
->bus
->phy_map
[0];
1810 /* switch device has not been initialized, reuse priv */
1812 priv
->port4_phy
= true;
1819 /* switch device has been initialized, reinit */
1821 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1822 priv
->initialized
= false;
1823 priv
->port4_phy
= true;
1824 ar8316_hw_init(priv
);
1832 mutex_init(&priv
->reg_mutex
);
1837 swdev
->cpu_port
= AR8216_PORT_CPU
;
1838 swdev
->ops
= &ar8216_sw_ops
;
1839 swdev
->ports
= AR8216_NUM_PORTS
;
1841 if (chip_is_ar8316(priv
)) {
1842 swdev
->name
= "Atheros AR8316";
1843 swdev
->vlans
= AR8X16_MAX_VLANS
;
1845 if (priv
->port4_phy
) {
1846 /* port 5 connected to the other mac, therefore unusable */
1847 swdev
->ports
= (AR8216_NUM_PORTS
- 1);
1849 } else if (chip_is_ar8236(priv
)) {
1850 swdev
->name
= "Atheros AR8236";
1851 swdev
->vlans
= AR8216_NUM_VLANS
;
1852 swdev
->ports
= AR8216_NUM_PORTS
;
1853 } else if (chip_is_ar8327(priv
)) {
1854 swdev
->name
= "Atheros AR8327";
1855 swdev
->vlans
= AR8X16_MAX_VLANS
;
1856 swdev
->ports
= AR8327_NUM_PORTS
;
1858 swdev
->name
= "Atheros AR8216";
1859 swdev
->vlans
= AR8216_NUM_VLANS
;
1862 ret
= ar8xxx_mib_init(priv
);
1866 ret
= register_switch(swdev
, pdev
->attached_dev
);
1868 goto err_cleanup_mib
;
1870 printk(KERN_INFO
"%s: %s switch driver attached.\n",
1871 pdev
->attached_dev
->name
, swdev
->name
);
1875 ret
= priv
->chip
->hw_init(priv
);
1877 goto err_unregister_switch
;
1879 ret
= ar8216_sw_reset_switch(&priv
->dev
);
1881 goto err_unregister_switch
;
1883 dev
->phy_ptr
= priv
;
1885 /* VID fixup only needed on ar8216 */
1886 if (chip_is_ar8216(priv
) && pdev
->addr
== 0) {
1887 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1888 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1889 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1894 ar8xxx_mib_start(priv
);
1898 err_unregister_switch
:
1899 unregister_switch(&priv
->dev
);
1901 ar8xxx_mib_cleanup(priv
);
1909 ar8216_read_status(struct phy_device
*phydev
)
1911 struct ar8216_priv
*priv
= phydev
->priv
;
1912 struct switch_port_link link
;
1915 if (phydev
->addr
!= 0)
1916 return genphy_read_status(phydev
);
1918 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1919 phydev
->link
= !!link
.link
;
1923 switch (link
.speed
) {
1924 case SWITCH_PORT_SPEED_10
:
1925 phydev
->speed
= SPEED_10
;
1927 case SWITCH_PORT_SPEED_100
:
1928 phydev
->speed
= SPEED_100
;
1930 case SWITCH_PORT_SPEED_1000
:
1931 phydev
->speed
= SPEED_1000
;
1936 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1938 /* flush the address translation unit */
1939 mutex_lock(&priv
->reg_mutex
);
1940 ret
= priv
->chip
->atu_flush(priv
);
1941 mutex_unlock(&priv
->reg_mutex
);
1943 phydev
->state
= PHY_RUNNING
;
1944 netif_carrier_on(phydev
->attached_dev
);
1945 phydev
->adjust_link(phydev
->attached_dev
);
1951 ar8216_config_aneg(struct phy_device
*phydev
)
1953 if (phydev
->addr
== 0)
1956 return genphy_config_aneg(phydev
);
1959 static const u32 ar8xxx_phy_ids
[] = {
1966 ar8xxx_phy_match(u32 phy_id
)
1970 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
1971 if (phy_id
== ar8xxx_phy_ids
[i
])
1978 ar8xxx_is_possible(struct mii_bus
*bus
)
1982 for (i
= 0; i
< 4; i
++) {
1985 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
1986 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
1987 if (!ar8xxx_phy_match(phy_id
)) {
1988 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1989 dev_name(&bus
->dev
), i
, phy_id
);
1998 ar8216_probe(struct phy_device
*pdev
)
2000 struct ar8216_priv
*priv
;
2003 /* skip PHYs at unused adresses */
2004 if (pdev
->addr
!= 0 && pdev
->addr
!= 4)
2007 if (!ar8xxx_is_possible(pdev
->bus
))
2010 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
2014 priv
->mii_bus
= pdev
->bus
;
2015 priv
->read
= ar8216_mii_read
;
2016 priv
->write
= ar8216_mii_write
;
2019 ret
= ar8216_id_chip(priv
);
2026 ar8216_detach(struct phy_device
*pdev
)
2028 struct net_device
*dev
= pdev
->attached_dev
;
2033 dev
->phy_ptr
= NULL
;
2034 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2035 dev
->eth_mangle_rx
= NULL
;
2036 dev
->eth_mangle_tx
= NULL
;
2040 ar8216_remove(struct phy_device
*pdev
)
2042 struct ar8216_priv
*priv
= pdev
->priv
;
2049 if (pdev
->addr
== 0)
2050 unregister_switch(&priv
->dev
);
2052 ar8xxx_mib_cleanup(priv
);
2056 static struct phy_driver ar8216_driver
= {
2057 .phy_id
= 0x004d0000,
2058 .name
= "Atheros AR8216/AR8236/AR8316",
2059 .phy_id_mask
= 0xffff0000,
2060 .features
= PHY_BASIC_FEATURES
,
2061 .probe
= ar8216_probe
,
2062 .remove
= ar8216_remove
,
2063 .detach
= ar8216_detach
,
2064 .config_init
= &ar8216_config_init
,
2065 .config_aneg
= &ar8216_config_aneg
,
2066 .read_status
= &ar8216_read_status
,
2067 .driver
= { .owner
= THIS_MODULE
},
2073 return phy_driver_register(&ar8216_driver
);
2079 phy_driver_unregister(&ar8216_driver
);
2082 module_init(ar8216_init
);
2083 module_exit(ar8216_exit
);
2084 MODULE_LICENSE("GPL");