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sunxi: update the 6.6 DTS_DIR hack
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
39
40 #include "ar8216.h"
41
42 extern const struct ar8xxx_chip ar8327_chip;
43 extern const struct ar8xxx_chip ar8337_chip;
44
45 #define MIB_DESC_BASIC(_s , _o, _n) \
46 { \
47 .size = (_s), \
48 .offset = (_o), \
49 .name = (_n), \
50 .type = AR8XXX_MIB_BASIC, \
51 }
52
53 #define MIB_DESC_EXT(_s , _o, _n) \
54 { \
55 .size = (_s), \
56 .offset = (_o), \
57 .name = (_n), \
58 .type = AR8XXX_MIB_EXTENDED, \
59 }
60
61 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
62 MIB_DESC_EXT(1, AR8216_STATS_RXBROAD, "RxBroad"),
63 MIB_DESC_EXT(1, AR8216_STATS_RXPAUSE, "RxPause"),
64 MIB_DESC_EXT(1, AR8216_STATS_RXMULTI, "RxMulti"),
65 MIB_DESC_EXT(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
66 MIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
67 MIB_DESC_EXT(1, AR8216_STATS_RXRUNT, "RxRunt"),
68 MIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
69 MIB_DESC_EXT(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
70 MIB_DESC_EXT(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
71 MIB_DESC_EXT(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
72 MIB_DESC_EXT(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
73 MIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
74 MIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
75 MIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
76 MIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
77 MIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
78 MIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
79 MIB_DESC_EXT(1, AR8216_STATS_FILTERED, "Filtered"),
80 MIB_DESC_EXT(1, AR8216_STATS_TXBROAD, "TxBroad"),
81 MIB_DESC_EXT(1, AR8216_STATS_TXPAUSE, "TxPause"),
82 MIB_DESC_EXT(1, AR8216_STATS_TXMULTI, "TxMulti"),
83 MIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
84 MIB_DESC_EXT(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
85 MIB_DESC_EXT(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
86 MIB_DESC_EXT(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
87 MIB_DESC_EXT(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
88 MIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
89 MIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
90 MIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
91 MIB_DESC_BASIC(2, AR8216_STATS_TXBYTE, "TxByte"),
92 MIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
93 MIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
94 MIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
95 MIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
96 MIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
97 MIB_DESC_EXT(1, AR8216_STATS_TXDEFER, "TxDefer"),
98 MIB_DESC_EXT(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
99 };
100
101 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
102 MIB_DESC_EXT(1, AR8236_STATS_RXBROAD, "RxBroad"),
103 MIB_DESC_EXT(1, AR8236_STATS_RXPAUSE, "RxPause"),
104 MIB_DESC_EXT(1, AR8236_STATS_RXMULTI, "RxMulti"),
105 MIB_DESC_EXT(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
106 MIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
107 MIB_DESC_EXT(1, AR8236_STATS_RXRUNT, "RxRunt"),
108 MIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
109 MIB_DESC_EXT(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
110 MIB_DESC_EXT(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
111 MIB_DESC_EXT(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
112 MIB_DESC_EXT(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
113 MIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
114 MIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
115 MIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
116 MIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
117 MIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
118 MIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
119 MIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
120 MIB_DESC_EXT(1, AR8236_STATS_FILTERED, "Filtered"),
121 MIB_DESC_EXT(1, AR8236_STATS_TXBROAD, "TxBroad"),
122 MIB_DESC_EXT(1, AR8236_STATS_TXPAUSE, "TxPause"),
123 MIB_DESC_EXT(1, AR8236_STATS_TXMULTI, "TxMulti"),
124 MIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
125 MIB_DESC_EXT(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
126 MIB_DESC_EXT(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
127 MIB_DESC_EXT(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
128 MIB_DESC_EXT(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
129 MIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
130 MIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
131 MIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
132 MIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
133 MIB_DESC_BASIC(2, AR8236_STATS_TXBYTE, "TxByte"),
134 MIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
135 MIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
136 MIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
137 MIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
138 MIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
139 MIB_DESC_EXT(1, AR8236_STATS_TXDEFER, "TxDefer"),
140 MIB_DESC_EXT(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
141 };
142
143 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
144 static LIST_HEAD(ar8xxx_dev_list);
145
146 static void
147 ar8xxx_mib_start(struct ar8xxx_priv *priv);
148 static void
149 ar8xxx_mib_stop(struct ar8xxx_priv *priv);
150
151 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
152 static int
153 ar8xxx_phy_poll_reset(struct mii_bus *bus)
154 {
155 unsigned int sleep_msecs = 20;
156 int ret, elapsed, i;
157
158 for (elapsed = sleep_msecs; elapsed <= 600;
159 elapsed += sleep_msecs) {
160 msleep(sleep_msecs);
161 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
162 ret = mdiobus_read(bus, i, MII_BMCR);
163 if (ret < 0)
164 return ret;
165 if (ret & BMCR_RESET)
166 break;
167 if (i == AR8XXX_NUM_PHYS - 1) {
168 usleep_range(1000, 2000);
169 return 0;
170 }
171 }
172 }
173 return -ETIMEDOUT;
174 }
175
176 static int
177 ar8xxx_phy_check_aneg(struct phy_device *phydev)
178 {
179 int ret;
180
181 if (phydev->autoneg != AUTONEG_ENABLE)
182 return 0;
183 /*
184 * BMCR_ANENABLE might have been cleared
185 * by phy_init_hw in certain kernel versions
186 * therefore check for it
187 */
188 ret = phy_read(phydev, MII_BMCR);
189 if (ret < 0)
190 return ret;
191 if (ret & BMCR_ANENABLE)
192 return 0;
193
194 dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
195 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
196 return phy_write(phydev, MII_BMCR, ret);
197 }
198
199 void
200 ar8xxx_phy_init(struct ar8xxx_priv *priv)
201 {
202 int i;
203 struct mii_bus *bus;
204
205 bus = priv->sw_mii_bus ?: priv->mii_bus;
206 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
207 if (priv->chip->phy_fixup)
208 priv->chip->phy_fixup(priv, i);
209
210 /* initialize the port itself */
211 mdiobus_write(bus, i, MII_ADVERTISE,
212 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
213 if (ar8xxx_has_gige(priv))
214 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
215 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
216 }
217
218 ar8xxx_phy_poll_reset(bus);
219 }
220
221 u32
222 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
223 {
224 struct mii_bus *bus = priv->mii_bus;
225 u16 lo, hi;
226
227 lo = bus->read(bus, phy_id, regnum);
228 hi = bus->read(bus, phy_id, regnum + 1);
229
230 return (hi << 16) | lo;
231 }
232
233 void
234 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
235 {
236 struct mii_bus *bus = priv->mii_bus;
237 u16 lo, hi;
238
239 lo = val & 0xffff;
240 hi = (u16) (val >> 16);
241
242 if (priv->chip->mii_lo_first)
243 {
244 bus->write(bus, phy_id, regnum, lo);
245 bus->write(bus, phy_id, regnum + 1, hi);
246 } else {
247 bus->write(bus, phy_id, regnum + 1, hi);
248 bus->write(bus, phy_id, regnum, lo);
249 }
250 }
251
252 u32
253 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
254 {
255 struct mii_bus *bus = priv->mii_bus;
256 u16 r1, r2, page;
257 u32 val;
258
259 split_addr((u32) reg, &r1, &r2, &page);
260
261 mutex_lock(&bus->mdio_lock);
262
263 bus->write(bus, 0x18, 0, page);
264 wait_for_page_switch();
265 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
266
267 mutex_unlock(&bus->mdio_lock);
268
269 return val;
270 }
271
272 void
273 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
274 {
275 struct mii_bus *bus = priv->mii_bus;
276 u16 r1, r2, page;
277
278 split_addr((u32) reg, &r1, &r2, &page);
279
280 mutex_lock(&bus->mdio_lock);
281
282 bus->write(bus, 0x18, 0, page);
283 wait_for_page_switch();
284 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
285
286 mutex_unlock(&bus->mdio_lock);
287 }
288
289 u32
290 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
291 {
292 struct mii_bus *bus = priv->mii_bus;
293 u16 r1, r2, page;
294 u32 ret;
295
296 split_addr((u32) reg, &r1, &r2, &page);
297
298 mutex_lock(&bus->mdio_lock);
299
300 bus->write(bus, 0x18, 0, page);
301 wait_for_page_switch();
302
303 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
304 ret &= ~mask;
305 ret |= val;
306 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
307
308 mutex_unlock(&bus->mdio_lock);
309
310 return ret;
311 }
312 void
313 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
314 u16 dbg_addr, u16 *dbg_data)
315 {
316 struct mii_bus *bus = priv->mii_bus;
317
318 mutex_lock(&bus->mdio_lock);
319 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
320 *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
321 mutex_unlock(&bus->mdio_lock);
322 }
323
324 void
325 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
326 u16 dbg_addr, u16 dbg_data)
327 {
328 struct mii_bus *bus = priv->mii_bus;
329
330 mutex_lock(&bus->mdio_lock);
331 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
332 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
333 mutex_unlock(&bus->mdio_lock);
334 }
335
336 static inline void
337 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
338 {
339 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
340 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
341 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
342 }
343
344 void
345 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
346 {
347 struct mii_bus *bus = priv->mii_bus;
348
349 mutex_lock(&bus->mdio_lock);
350 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
351 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
352 mutex_unlock(&bus->mdio_lock);
353 }
354
355 u16
356 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
357 {
358 struct mii_bus *bus = priv->mii_bus;
359 u16 data;
360
361 mutex_lock(&bus->mdio_lock);
362 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
363 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
364 mutex_unlock(&bus->mdio_lock);
365
366 return data;
367 }
368
369 static int
370 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
371 unsigned timeout)
372 {
373 int i;
374
375 for (i = 0; i < timeout; i++) {
376 u32 t;
377
378 t = ar8xxx_read(priv, reg);
379 if ((t & mask) == val)
380 return 0;
381
382 usleep_range(1000, 2000);
383 cond_resched();
384 }
385
386 return -ETIMEDOUT;
387 }
388
389 static int
390 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
391 {
392 unsigned mib_func = priv->chip->mib_func;
393 int ret;
394
395 lockdep_assert_held(&priv->mib_lock);
396
397 /* Capture the hardware statistics for all ports */
398 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
399
400 /* Wait for the capturing to complete. */
401 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
402 if (ret)
403 goto out;
404
405 ret = 0;
406
407 out:
408 return ret;
409 }
410
411 static int
412 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
413 {
414 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
415 }
416
417 static int
418 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
419 {
420 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
421 }
422
423 static void
424 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
425 {
426 unsigned int base;
427 u64 *mib_stats;
428 int i;
429
430 WARN_ON(port >= priv->dev.ports);
431
432 lockdep_assert_held(&priv->mib_lock);
433
434 base = priv->chip->reg_port_stats_start +
435 priv->chip->reg_port_stats_length * port;
436
437 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
438 for (i = 0; i < priv->chip->num_mibs; i++) {
439 const struct ar8xxx_mib_desc *mib;
440 u64 t;
441
442 mib = &priv->chip->mib_decs[i];
443 if (mib->type > priv->mib_type)
444 continue;
445 t = ar8xxx_read(priv, base + mib->offset);
446 if (mib->size == 2) {
447 u64 hi;
448
449 hi = ar8xxx_read(priv, base + mib->offset + 4);
450 t |= hi << 32;
451 }
452
453 if (flush)
454 mib_stats[i] = 0;
455 else
456 mib_stats[i] += t;
457 cond_resched();
458 }
459 }
460
461 static void
462 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
463 struct switch_port_link *link)
464 {
465 u32 status;
466 u32 speed;
467
468 memset(link, '\0', sizeof(*link));
469
470 status = priv->chip->read_port_status(priv, port);
471
472 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
473 if (link->aneg) {
474 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
475 } else {
476 link->link = true;
477
478 if (priv->get_port_link) {
479 int err;
480
481 err = priv->get_port_link(port);
482 if (err >= 0)
483 link->link = !!err;
484 }
485 }
486
487 if (!link->link)
488 return;
489
490 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
491 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
492 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
493
494 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
495 link->eee = priv->chip->read_port_eee_status(priv, port);
496
497 speed = (status & AR8216_PORT_STATUS_SPEED) >>
498 AR8216_PORT_STATUS_SPEED_S;
499
500 switch (speed) {
501 case AR8216_PORT_SPEED_10M:
502 link->speed = SWITCH_PORT_SPEED_10;
503 break;
504 case AR8216_PORT_SPEED_100M:
505 link->speed = SWITCH_PORT_SPEED_100;
506 break;
507 case AR8216_PORT_SPEED_1000M:
508 link->speed = SWITCH_PORT_SPEED_1000;
509 break;
510 default:
511 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
512 break;
513 }
514 }
515
516 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
517
518 static struct sk_buff *
519 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
520 {
521 struct ar8xxx_priv *priv = dev->phy_ptr;
522 unsigned char *buf;
523
524 if (unlikely(!priv))
525 goto error;
526
527 if (!priv->vlan)
528 goto send;
529
530 if (unlikely(skb_headroom(skb) < 2)) {
531 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
532 goto error;
533 }
534
535 buf = skb_push(skb, 2);
536 buf[0] = 0x10;
537 buf[1] = 0x80;
538
539 send:
540 return skb;
541
542 error:
543 dev_kfree_skb_any(skb);
544 return NULL;
545 }
546
547 static void
548 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
549 {
550 struct ar8xxx_priv *priv;
551 unsigned char *buf;
552 int port, vlan;
553
554 priv = dev->phy_ptr;
555 if (!priv)
556 return;
557
558 /* don't strip the header if vlan mode is disabled */
559 if (!priv->vlan)
560 return;
561
562 /* strip header, get vlan id */
563 buf = skb->data;
564 skb_pull(skb, 2);
565
566 /* check for vlan header presence */
567 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
568 return;
569
570 port = buf[0] & 0x7;
571
572 /* no need to fix up packets coming from a tagged source */
573 if (priv->vlan_tagged & (1 << port))
574 return;
575
576 /* lookup port vid from local table, the switch passes an invalid vlan id */
577 vlan = priv->vlan_id[priv->pvid[port]];
578
579 buf[14 + 2] &= 0xf0;
580 buf[14 + 2] |= vlan >> 8;
581 buf[15 + 2] = vlan & 0xff;
582 }
583
584 #endif
585
586 int
587 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
588 {
589 int timeout = 20;
590 u32 t = 0;
591
592 while (1) {
593 t = ar8xxx_read(priv, reg);
594 if ((t & mask) == val)
595 return 0;
596
597 if (timeout-- <= 0)
598 break;
599
600 udelay(10);
601 cond_resched();
602 }
603
604 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
605 (unsigned int) reg, t, mask, val);
606 return -ETIMEDOUT;
607 }
608
609 static void
610 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
611 {
612 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
613 return;
614 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
615 val &= AR8216_VTUDATA_MEMBER;
616 val |= AR8216_VTUDATA_VALID;
617 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
618 }
619 op |= AR8216_VTU_ACTIVE;
620 ar8xxx_write(priv, AR8216_REG_VTU, op);
621 }
622
623 static void
624 ar8216_vtu_flush(struct ar8xxx_priv *priv)
625 {
626 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
627 }
628
629 static void
630 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
631 {
632 u32 op;
633
634 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
635 ar8216_vtu_op(priv, op, port_mask);
636 }
637
638 static int
639 ar8216_atu_flush(struct ar8xxx_priv *priv)
640 {
641 int ret;
642
643 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
644 if (!ret)
645 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
646 AR8216_ATU_ACTIVE);
647
648 return ret;
649 }
650
651 static int
652 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
653 {
654 u32 t;
655 int ret;
656
657 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
658 if (!ret) {
659 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
660 t |= AR8216_ATU_ACTIVE;
661 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
662 }
663
664 return ret;
665 }
666
667 static u32
668 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
669 {
670 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
671 }
672
673 static void
674 __ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members,
675 bool ath_hdr_en)
676 {
677 u32 header;
678 u32 egress, ingress;
679 u32 pvid;
680
681 if (priv->vlan) {
682 pvid = priv->vlan_id[priv->pvid[port]];
683 if (priv->vlan_tagged & (1 << port))
684 egress = AR8216_OUT_ADD_VLAN;
685 else
686 egress = AR8216_OUT_STRIP_VLAN;
687 ingress = AR8216_IN_SECURE;
688 } else {
689 pvid = port;
690 egress = AR8216_OUT_KEEP;
691 ingress = AR8216_IN_PORT_ONLY;
692 }
693
694 header = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0;
695
696 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
697 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
698 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
699 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
700 AR8216_PORT_CTRL_LEARN | header |
701 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
702 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
703
704 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
705 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
706 AR8216_PORT_VLAN_DEFAULT_ID,
707 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
708 (ingress << AR8216_PORT_VLAN_MODE_S) |
709 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
710 }
711
712 static void
713 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
714 {
715 return __ar8216_setup_port(priv, port, members,
716 chip_is_ar8216(priv) && priv->vlan &&
717 port == AR8216_PORT_CPU);
718 }
719
720 static int
721 ar8216_hw_init(struct ar8xxx_priv *priv)
722 {
723 if (priv->initialized)
724 return 0;
725
726 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
727 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
728
729 ar8xxx_phy_init(priv);
730
731 priv->initialized = true;
732 return 0;
733 }
734
735 static void
736 ar8216_init_globals(struct ar8xxx_priv *priv)
737 {
738 /* standard atheros magic */
739 ar8xxx_write(priv, 0x38, 0xc000050e);
740
741 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
742 AR8216_GCTRL_MTU, 1518 + 8 + 2);
743 }
744
745 static void
746 __ar8216_init_port(struct ar8xxx_priv *priv, int port,
747 bool cpu_ge, bool flow_en)
748 {
749 /* Enable port learning and tx */
750 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
751 AR8216_PORT_CTRL_LEARN |
752 (4 << AR8216_PORT_CTRL_STATE_S));
753
754 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
755
756 if (port == AR8216_PORT_CPU) {
757 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
758 AR8216_PORT_STATUS_LINK_UP |
759 (cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
760 AR8216_PORT_STATUS_TXMAC |
761 AR8216_PORT_STATUS_RXMAC |
762 (flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |
763 (flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |
764 AR8216_PORT_STATUS_DUPLEX);
765 } else {
766 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
767 AR8216_PORT_STATUS_LINK_AUTO);
768 }
769 }
770
771 static void
772 ar8216_init_port(struct ar8xxx_priv *priv, int port)
773 {
774 __ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
775 chip_is_ar8316(priv));
776 }
777
778 static void
779 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
780 {
781 int timeout = 20;
782
783 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
784 udelay(10);
785 cond_resched();
786 }
787
788 if (!timeout)
789 pr_err("ar8216: timeout waiting for atu to become ready\n");
790 }
791
792 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
793 struct arl_entry *a, u32 *status, enum arl_op op)
794 {
795 struct mii_bus *bus = priv->mii_bus;
796 u16 r2, page;
797 u16 r1_func0, r1_func1, r1_func2;
798 u32 t, val0, val1, val2;
799
800 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
801 r2 |= 0x10;
802
803 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
804 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
805
806 switch (op) {
807 case AR8XXX_ARL_INITIALIZE:
808 /* all ATU registers are on the same page
809 * therefore set page only once
810 */
811 bus->write(bus, 0x18, 0, page);
812 wait_for_page_switch();
813
814 ar8216_wait_atu_ready(priv, r2, r1_func0);
815
816 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
817 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
818 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
819 break;
820 case AR8XXX_ARL_GET_NEXT:
821 t = ar8xxx_mii_read32(priv, r2, r1_func0);
822 t |= AR8216_ATU_ACTIVE;
823 ar8xxx_mii_write32(priv, r2, r1_func0, t);
824 ar8216_wait_atu_ready(priv, r2, r1_func0);
825
826 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
827 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
828 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
829
830 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
831 if (!*status)
832 break;
833
834 a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
835 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
836 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
837 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
838 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
839 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
840 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
841 break;
842 }
843 }
844
845 static int
846 ar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum)
847 {
848 u32 t, val = 0xffff;
849 int err;
850
851 if (addr >= AR8216_NUM_PORTS)
852 return 0xffff;
853 t = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
854 (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
855 AR8216_MDIO_CTRL_MASTER_EN |
856 AR8216_MDIO_CTRL_BUSY |
857 AR8216_MDIO_CTRL_CMD_READ;
858
859 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
860 err = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
861 AR8216_MDIO_CTRL_BUSY, 0, 5);
862 if (!err)
863 val = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL);
864
865 return val & AR8216_MDIO_CTRL_DATA_M;
866 }
867
868 static int
869 ar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val)
870 {
871 u32 t;
872 int ret;
873
874 if (addr >= AR8216_NUM_PORTS)
875 return -EINVAL;
876
877 t = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
878 (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
879 AR8216_MDIO_CTRL_MASTER_EN |
880 AR8216_MDIO_CTRL_BUSY |
881 AR8216_MDIO_CTRL_CMD_WRITE |
882 val;
883
884 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
885 ret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
886 AR8216_MDIO_CTRL_BUSY, 0, 5);
887
888 return ret;
889 }
890
891 static int
892 ar8229_hw_init(struct ar8xxx_priv *priv)
893 {
894 phy_interface_t phy_if_mode;
895
896 if (priv->initialized)
897 return 0;
898
899 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
900 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
901
902 of_get_phy_mode(priv->pdev->of_node, &phy_if_mode);
903
904 if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
905 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
906 AR8229_OPER_MODE0_MAC_GMII_EN);
907 } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
908 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
909 AR8229_OPER_MODE0_PHY_MII_EN);
910 } else {
911 pr_err("ar8229: unsupported mii mode\n");
912 return -EINVAL;
913 }
914
915 if (priv->port4_phy) {
916 ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
917 AR8229_REG_OPER_MODE1_PHY4_MII_EN);
918 /* disable port5 to prevent mii conflict */
919 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
920 }
921
922 ar8xxx_phy_init(priv);
923
924 priv->initialized = true;
925 return 0;
926 }
927
928 static void
929 ar8229_init_globals(struct ar8xxx_priv *priv)
930 {
931
932 /* Enable CPU port, and disable mirror port */
933 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
934 AR8216_GLOBAL_CPUPORT_EN |
935 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
936
937 /* Setup TAG priority mapping */
938 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
939
940 /* Enable aging, MAC replacing */
941 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
942 0x2b /* 5 min age time */ |
943 AR8216_ATU_CTRL_AGE_EN |
944 AR8216_ATU_CTRL_LEARN_CHANGE);
945
946 /* Enable ARP frame acknowledge */
947 ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
948 AR8229_QM_CTRL_ARP_EN);
949
950 /*
951 * Enable Broadcast/unknown multicast and unicast frames
952 * transmitted to the CPU port.
953 */
954 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
955 AR8229_FLOOD_MASK_BC_DP(0) |
956 AR8229_FLOOD_MASK_MC_DP(0) |
957 AR8229_FLOOD_MASK_UC_DP(0));
958
959 /* setup MTU */
960 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
961 AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);
962
963 /* Enable MIB counters */
964 ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,
965 AR8236_MIB_EN);
966
967 /* setup Service TAG */
968 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
969 }
970
971 static void
972 ar8229_init_port(struct ar8xxx_priv *priv, int port)
973 {
974 __ar8216_init_port(priv, port, true, true);
975 }
976
977
978 static int
979 ar7240sw_hw_init(struct ar8xxx_priv *priv)
980 {
981 if (priv->initialized)
982 return 0;
983
984 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
985 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
986
987 priv->port4_phy = 1;
988 /* disable port5 to prevent mii conflict */
989 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
990
991 ar8xxx_phy_init(priv);
992
993 priv->initialized = true;
994 return 0;
995 }
996
997 static void
998 ar7240sw_init_globals(struct ar8xxx_priv *priv)
999 {
1000
1001 /* Enable CPU port, and disable mirror port */
1002 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
1003 AR8216_GLOBAL_CPUPORT_EN |
1004 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1005
1006 /* Setup TAG priority mapping */
1007 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
1008
1009 /* Enable ARP frame acknowledge, aging, MAC replacing */
1010 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
1011 AR8216_ATU_CTRL_RESERVED |
1012 0x2b /* 5 min age time */ |
1013 AR8216_ATU_CTRL_AGE_EN |
1014 AR8216_ATU_CTRL_ARP_EN |
1015 AR8216_ATU_CTRL_LEARN_CHANGE);
1016
1017 /* Enable Broadcast frames transmitted to the CPU */
1018 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
1019 AR8216_FM_CPU_BROADCAST_EN);
1020
1021 /* setup MTU */
1022 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1023 AR8216_GCTRL_MTU,
1024 AR8216_GCTRL_MTU);
1025
1026 /* setup Service TAG */
1027 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
1028 }
1029
1030 static void
1031 ar7240sw_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1032 {
1033 return __ar8216_setup_port(priv, port, members, false);
1034 }
1035
1036 static void
1037 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1038 {
1039 u32 egress, ingress;
1040 u32 pvid;
1041
1042 if (priv->vlan) {
1043 pvid = priv->vlan_id[priv->pvid[port]];
1044 if (priv->vlan_tagged & (1 << port))
1045 egress = AR8216_OUT_ADD_VLAN;
1046 else
1047 egress = AR8216_OUT_STRIP_VLAN;
1048 ingress = AR8216_IN_SECURE;
1049 } else {
1050 pvid = port;
1051 egress = AR8216_OUT_KEEP;
1052 ingress = AR8216_IN_PORT_ONLY;
1053 }
1054
1055 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1056 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
1057 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
1058 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
1059 AR8216_PORT_CTRL_LEARN |
1060 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
1061 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
1062
1063 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
1064 AR8236_PORT_VLAN_DEFAULT_ID,
1065 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
1066
1067 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
1068 AR8236_PORT_VLAN2_VLAN_MODE |
1069 AR8236_PORT_VLAN2_MEMBER,
1070 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
1071 (members << AR8236_PORT_VLAN2_MEMBER_S));
1072 }
1073
1074 static void
1075 ar8236_init_globals(struct ar8xxx_priv *priv)
1076 {
1077 /* enable jumbo frames */
1078 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1079 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1080
1081 /* enable cpu port to receive arp frames */
1082 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
1083 AR8236_ATU_CTRL_RES);
1084
1085 /*
1086 * Enable Broadcast/unknown multicast and unicast frames
1087 * transmitted to the CPU port.
1088 */
1089 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
1090 AR8229_FLOOD_MASK_BC_DP(0) |
1091 AR8229_FLOOD_MASK_MC_DP(0) |
1092 AR8229_FLOOD_MASK_UC_DP(0));
1093
1094 /* Enable MIB counters */
1095 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1096 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1097 AR8236_MIB_EN);
1098 }
1099
1100 static int
1101 ar8316_hw_init(struct ar8xxx_priv *priv)
1102 {
1103 u32 val, newval;
1104
1105 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
1106
1107 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1108 if (priv->port4_phy) {
1109 /* value taken from Ubiquiti RouterStation Pro */
1110 newval = 0x81461bea;
1111 pr_info("ar8316: Using port 4 as PHY\n");
1112 } else {
1113 newval = 0x01261be2;
1114 pr_info("ar8316: Using port 4 as switch port\n");
1115 }
1116 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
1117 /* value taken from AVM Fritz!Box 7390 sources */
1118 newval = 0x010e5b71;
1119 } else {
1120 /* no known value for phy interface */
1121 pr_err("ar8316: unsupported mii mode: %d.\n",
1122 priv->phy->interface);
1123 return -EINVAL;
1124 }
1125
1126 if (val == newval)
1127 goto out;
1128
1129 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
1130
1131 if (priv->port4_phy &&
1132 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1133 /* work around for phy4 rgmii mode */
1134 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1135 /* rx delay */
1136 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1137 /* tx delay */
1138 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1139 msleep(1000);
1140 }
1141
1142 ar8xxx_phy_init(priv);
1143
1144 out:
1145 priv->initialized = true;
1146 return 0;
1147 }
1148
1149 static void
1150 ar8316_init_globals(struct ar8xxx_priv *priv)
1151 {
1152 /* standard atheros magic */
1153 ar8xxx_write(priv, 0x38, 0xc000050e);
1154
1155 /* enable cpu port to receive multicast and broadcast frames */
1156 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1157
1158 /* enable jumbo frames */
1159 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1160 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1161
1162 /* Enable MIB counters */
1163 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1164 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1165 AR8236_MIB_EN);
1166 }
1167
1168 int
1169 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1170 struct switch_val *val)
1171 {
1172 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1173 priv->vlan = !!val->value.i;
1174 return 0;
1175 }
1176
1177 int
1178 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1179 struct switch_val *val)
1180 {
1181 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1182 val->value.i = priv->vlan;
1183 return 0;
1184 }
1185
1186
1187 int
1188 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1189 {
1190 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1191
1192 /* make sure no invalid PVIDs get set */
1193
1194 if (vlan < 0 || vlan >= dev->vlans ||
1195 port < 0 || port >= AR8X16_MAX_PORTS)
1196 return -EINVAL;
1197
1198 priv->pvid[port] = vlan;
1199 return 0;
1200 }
1201
1202 int
1203 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1204 {
1205 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1206
1207 if (port < 0 || port >= AR8X16_MAX_PORTS)
1208 return -EINVAL;
1209
1210 *vlan = priv->pvid[port];
1211 return 0;
1212 }
1213
1214 static int
1215 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1216 struct switch_val *val)
1217 {
1218 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1219
1220 if (val->port_vlan >= dev->vlans)
1221 return -EINVAL;
1222
1223 priv->vlan_id[val->port_vlan] = val->value.i;
1224 return 0;
1225 }
1226
1227 static int
1228 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1229 struct switch_val *val)
1230 {
1231 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1232 val->value.i = priv->vlan_id[val->port_vlan];
1233 return 0;
1234 }
1235
1236 int
1237 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1238 struct switch_port_link *link)
1239 {
1240 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1241
1242 ar8216_read_port_link(priv, port, link);
1243 return 0;
1244 }
1245
1246 static int
1247 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1248 {
1249 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1250 u8 ports;
1251 int i;
1252
1253 if (val->port_vlan >= dev->vlans)
1254 return -EINVAL;
1255
1256 ports = priv->vlan_table[val->port_vlan];
1257 val->len = 0;
1258 for (i = 0; i < dev->ports; i++) {
1259 struct switch_port *p;
1260
1261 if (!(ports & (1 << i)))
1262 continue;
1263
1264 p = &val->value.ports[val->len++];
1265 p->id = i;
1266 if (priv->vlan_tagged & (1 << i))
1267 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1268 else
1269 p->flags = 0;
1270 }
1271 return 0;
1272 }
1273
1274 static int
1275 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1276 {
1277 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1278 u8 *vt = &priv->vlan_table[val->port_vlan];
1279 int i, j;
1280
1281 *vt = 0;
1282 for (i = 0; i < val->len; i++) {
1283 struct switch_port *p = &val->value.ports[i];
1284
1285 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1286 priv->vlan_tagged |= (1 << p->id);
1287 } else {
1288 priv->vlan_tagged &= ~(1 << p->id);
1289 priv->pvid[p->id] = val->port_vlan;
1290
1291 /* make sure that an untagged port does not
1292 * appear in other vlans */
1293 for (j = 0; j < dev->vlans; j++) {
1294 if (j == val->port_vlan)
1295 continue;
1296 priv->vlan_table[j] &= ~(1 << p->id);
1297 }
1298 }
1299
1300 *vt |= 1 << p->id;
1301 }
1302 return 0;
1303 }
1304
1305 static void
1306 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1307 {
1308 int port;
1309
1310 /* reset all mirror registers */
1311 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1312 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1313 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1314 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1315 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1316 AR8216_PORT_CTRL_MIRROR_RX);
1317
1318 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1319 AR8216_PORT_CTRL_MIRROR_TX);
1320 }
1321
1322 /* now enable mirroring if necessary */
1323 if (priv->source_port >= AR8216_NUM_PORTS ||
1324 priv->monitor_port >= AR8216_NUM_PORTS ||
1325 priv->source_port == priv->monitor_port) {
1326 return;
1327 }
1328
1329 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1330 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1331 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1332
1333 if (priv->mirror_rx)
1334 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1335 AR8216_PORT_CTRL_MIRROR_RX);
1336
1337 if (priv->mirror_tx)
1338 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1339 AR8216_PORT_CTRL_MIRROR_TX);
1340 }
1341
1342 static inline u32
1343 ar8xxx_age_time_val(int age_time)
1344 {
1345 return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1346 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1347 }
1348
1349 static inline void
1350 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1351 {
1352 u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1353 ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1354 }
1355
1356 int
1357 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1358 {
1359 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1360 const struct ar8xxx_chip *chip = priv->chip;
1361 u8 portmask[AR8X16_MAX_PORTS];
1362 int i, j;
1363
1364 mutex_lock(&priv->reg_mutex);
1365 /* flush all vlan translation unit entries */
1366 priv->chip->vtu_flush(priv);
1367
1368 memset(portmask, 0, sizeof(portmask));
1369 if (!priv->init) {
1370 /* calculate the port destination masks and load vlans
1371 * into the vlan translation unit */
1372 for (j = 0; j < dev->vlans; j++) {
1373 u8 vp = priv->vlan_table[j];
1374
1375 if (!vp)
1376 continue;
1377
1378 for (i = 0; i < dev->ports; i++) {
1379 u8 mask = (1 << i);
1380 if (vp & mask)
1381 portmask[i] |= vp & ~mask;
1382 }
1383
1384 chip->vtu_load_vlan(priv, priv->vlan_id[j],
1385 priv->vlan_table[j]);
1386 }
1387 } else {
1388 /* vlan disabled:
1389 * isolate all ports, but connect them to the cpu port */
1390 for (i = 0; i < dev->ports; i++) {
1391 if (i == AR8216_PORT_CPU)
1392 continue;
1393
1394 portmask[i] = 1 << AR8216_PORT_CPU;
1395 portmask[AR8216_PORT_CPU] |= (1 << i);
1396 }
1397 }
1398
1399 /* update the port destination mask registers and tag settings */
1400 for (i = 0; i < dev->ports; i++) {
1401 chip->setup_port(priv, i, portmask[i]);
1402 }
1403
1404 chip->set_mirror_regs(priv);
1405
1406 /* set age time */
1407 if (chip->reg_arl_ctrl)
1408 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1409
1410 mutex_unlock(&priv->reg_mutex);
1411 return 0;
1412 }
1413
1414 int
1415 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1416 {
1417 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1418 const struct ar8xxx_chip *chip = priv->chip;
1419 int i;
1420
1421 mutex_lock(&priv->reg_mutex);
1422 memset(&priv->ar8xxx_priv_volatile, 0, sizeof(priv->ar8xxx_priv_volatile));
1423
1424 for (i = 0; i < dev->vlans; i++)
1425 priv->vlan_id[i] = i;
1426
1427 /* Configure all ports */
1428 for (i = 0; i < dev->ports; i++)
1429 chip->init_port(priv, i);
1430
1431 priv->mirror_rx = false;
1432 priv->mirror_tx = false;
1433 priv->source_port = 0;
1434 priv->monitor_port = 0;
1435 priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1436
1437 chip->init_globals(priv);
1438 chip->atu_flush(priv);
1439
1440 mutex_unlock(&priv->reg_mutex);
1441
1442 return chip->sw_hw_apply(dev);
1443 }
1444
1445 int
1446 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1447 const struct switch_attr *attr,
1448 struct switch_val *val)
1449 {
1450 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1451 unsigned int len;
1452 int ret;
1453
1454 if (!ar8xxx_has_mib_counters(priv))
1455 return -EOPNOTSUPP;
1456
1457 mutex_lock(&priv->mib_lock);
1458
1459 len = priv->dev.ports * priv->chip->num_mibs *
1460 sizeof(*priv->mib_stats);
1461 memset(priv->mib_stats, '\0', len);
1462 ret = ar8xxx_mib_flush(priv);
1463 if (ret)
1464 goto unlock;
1465
1466 ret = 0;
1467
1468 unlock:
1469 mutex_unlock(&priv->mib_lock);
1470 return ret;
1471 }
1472
1473 int
1474 ar8xxx_sw_set_mib_poll_interval(struct switch_dev *dev,
1475 const struct switch_attr *attr,
1476 struct switch_val *val)
1477 {
1478 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1479
1480 if (!ar8xxx_has_mib_counters(priv))
1481 return -EOPNOTSUPP;
1482
1483 ar8xxx_mib_stop(priv);
1484 priv->mib_poll_interval = val->value.i;
1485 ar8xxx_mib_start(priv);
1486
1487 return 0;
1488 }
1489
1490 int
1491 ar8xxx_sw_get_mib_poll_interval(struct switch_dev *dev,
1492 const struct switch_attr *attr,
1493 struct switch_val *val)
1494 {
1495 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1496
1497 if (!ar8xxx_has_mib_counters(priv))
1498 return -EOPNOTSUPP;
1499 val->value.i = priv->mib_poll_interval;
1500 return 0;
1501 }
1502
1503 int
1504 ar8xxx_sw_set_mib_type(struct switch_dev *dev,
1505 const struct switch_attr *attr,
1506 struct switch_val *val)
1507 {
1508 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1509
1510 if (!ar8xxx_has_mib_counters(priv))
1511 return -EOPNOTSUPP;
1512 priv->mib_type = val->value.i;
1513 return 0;
1514 }
1515
1516 int
1517 ar8xxx_sw_get_mib_type(struct switch_dev *dev,
1518 const struct switch_attr *attr,
1519 struct switch_val *val)
1520 {
1521 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1522
1523 if (!ar8xxx_has_mib_counters(priv))
1524 return -EOPNOTSUPP;
1525 val->value.i = priv->mib_type;
1526 return 0;
1527 }
1528
1529 int
1530 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1531 const struct switch_attr *attr,
1532 struct switch_val *val)
1533 {
1534 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1535
1536 mutex_lock(&priv->reg_mutex);
1537 priv->mirror_rx = !!val->value.i;
1538 priv->chip->set_mirror_regs(priv);
1539 mutex_unlock(&priv->reg_mutex);
1540
1541 return 0;
1542 }
1543
1544 int
1545 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1546 const struct switch_attr *attr,
1547 struct switch_val *val)
1548 {
1549 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1550 val->value.i = priv->mirror_rx;
1551 return 0;
1552 }
1553
1554 int
1555 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1556 const struct switch_attr *attr,
1557 struct switch_val *val)
1558 {
1559 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1560
1561 mutex_lock(&priv->reg_mutex);
1562 priv->mirror_tx = !!val->value.i;
1563 priv->chip->set_mirror_regs(priv);
1564 mutex_unlock(&priv->reg_mutex);
1565
1566 return 0;
1567 }
1568
1569 int
1570 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1571 const struct switch_attr *attr,
1572 struct switch_val *val)
1573 {
1574 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1575 val->value.i = priv->mirror_tx;
1576 return 0;
1577 }
1578
1579 int
1580 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1581 const struct switch_attr *attr,
1582 struct switch_val *val)
1583 {
1584 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1585
1586 mutex_lock(&priv->reg_mutex);
1587 priv->monitor_port = val->value.i;
1588 priv->chip->set_mirror_regs(priv);
1589 mutex_unlock(&priv->reg_mutex);
1590
1591 return 0;
1592 }
1593
1594 int
1595 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1596 const struct switch_attr *attr,
1597 struct switch_val *val)
1598 {
1599 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1600 val->value.i = priv->monitor_port;
1601 return 0;
1602 }
1603
1604 int
1605 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1606 const struct switch_attr *attr,
1607 struct switch_val *val)
1608 {
1609 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1610
1611 mutex_lock(&priv->reg_mutex);
1612 priv->source_port = val->value.i;
1613 priv->chip->set_mirror_regs(priv);
1614 mutex_unlock(&priv->reg_mutex);
1615
1616 return 0;
1617 }
1618
1619 int
1620 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1621 const struct switch_attr *attr,
1622 struct switch_val *val)
1623 {
1624 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1625 val->value.i = priv->source_port;
1626 return 0;
1627 }
1628
1629 int
1630 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1631 const struct switch_attr *attr,
1632 struct switch_val *val)
1633 {
1634 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1635 int port;
1636 int ret;
1637
1638 if (!ar8xxx_has_mib_counters(priv))
1639 return -EOPNOTSUPP;
1640
1641 port = val->port_vlan;
1642 if (port >= dev->ports)
1643 return -EINVAL;
1644
1645 mutex_lock(&priv->mib_lock);
1646 ret = ar8xxx_mib_capture(priv);
1647 if (ret)
1648 goto unlock;
1649
1650 ar8xxx_mib_fetch_port_stat(priv, port, true);
1651
1652 ret = 0;
1653
1654 unlock:
1655 mutex_unlock(&priv->mib_lock);
1656 return ret;
1657 }
1658
1659 static void
1660 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1661 {
1662 unsigned long b;
1663 const char *unit;
1664
1665 if (byte >= 0x40000000) { /* 1 GiB */
1666 b = byte * 10 / 0x40000000;
1667 unit = "GiB";
1668 } else if (byte >= 0x100000) { /* 1 MiB */
1669 b = byte * 10 / 0x100000;
1670 unit = "MiB";
1671 } else if (byte >= 0x400) { /* 1 KiB */
1672 b = byte * 10 / 0x400;
1673 unit = "KiB";
1674 } else {
1675 b = byte;
1676 unit = "Byte";
1677 }
1678 if (strcmp(unit, "Byte"))
1679 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1680 else
1681 snprintf(buf, len, "%lu %s", b, unit);
1682 }
1683
1684 int
1685 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1686 const struct switch_attr *attr,
1687 struct switch_val *val)
1688 {
1689 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1690 const struct ar8xxx_chip *chip = priv->chip;
1691 u64 *mib_stats, mib_data;
1692 unsigned int port;
1693 int ret;
1694 char *buf = priv->buf;
1695 char buf1[64];
1696 const char *mib_name;
1697 int i, len = 0;
1698 bool mib_stats_empty = true;
1699
1700 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
1701 return -EOPNOTSUPP;
1702
1703 port = val->port_vlan;
1704 if (port >= dev->ports)
1705 return -EINVAL;
1706
1707 mutex_lock(&priv->mib_lock);
1708 ret = ar8xxx_mib_capture(priv);
1709 if (ret)
1710 goto unlock;
1711
1712 ar8xxx_mib_fetch_port_stat(priv, port, false);
1713
1714 len += snprintf(buf + len, sizeof(priv->buf) - len,
1715 "MIB counters\n");
1716
1717 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1718 for (i = 0; i < chip->num_mibs; i++) {
1719 if (chip->mib_decs[i].type > priv->mib_type)
1720 continue;
1721 mib_name = chip->mib_decs[i].name;
1722 mib_data = mib_stats[i];
1723 len += snprintf(buf + len, sizeof(priv->buf) - len,
1724 "%-12s: %llu\n", mib_name, mib_data);
1725 if ((!strcmp(mib_name, "TxByte") ||
1726 !strcmp(mib_name, "RxGoodByte")) &&
1727 mib_data >= 1024) {
1728 ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1729 --len; /* discard newline at the end of buf */
1730 len += snprintf(buf + len, sizeof(priv->buf) - len,
1731 " (%s)\n", buf1);
1732 }
1733 if (mib_stats_empty && mib_data)
1734 mib_stats_empty = false;
1735 }
1736
1737 if (mib_stats_empty)
1738 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1739
1740 val->value.s = buf;
1741 val->len = len;
1742
1743 ret = 0;
1744
1745 unlock:
1746 mutex_unlock(&priv->mib_lock);
1747 return ret;
1748 }
1749
1750 int
1751 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1752 struct switch_val *val)
1753 {
1754 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1755 int age_time = val->value.i;
1756 u32 age_time_val;
1757
1758 if (age_time < 0)
1759 return -EINVAL;
1760
1761 age_time_val = ar8xxx_age_time_val(age_time);
1762 if (age_time_val == 0 || age_time_val > 0xffff)
1763 return -EINVAL;
1764
1765 priv->arl_age_time = age_time;
1766 return 0;
1767 }
1768
1769 int
1770 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1771 struct switch_val *val)
1772 {
1773 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1774 val->value.i = priv->arl_age_time;
1775 return 0;
1776 }
1777
1778 int
1779 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1780 const struct switch_attr *attr,
1781 struct switch_val *val)
1782 {
1783 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1784 struct mii_bus *bus = priv->mii_bus;
1785 const struct ar8xxx_chip *chip = priv->chip;
1786 char *buf = priv->arl_buf;
1787 int i, j, k, len = 0;
1788 struct arl_entry *a, *a1;
1789 u32 status;
1790
1791 if (!chip->get_arl_entry)
1792 return -EOPNOTSUPP;
1793
1794 mutex_lock(&priv->reg_mutex);
1795 mutex_lock(&bus->mdio_lock);
1796
1797 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1798
1799 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1800 a = &priv->arl_table[i];
1801 duplicate:
1802 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1803
1804 if (!status)
1805 break;
1806
1807 /* avoid duplicates
1808 * ARL table can include multiple valid entries
1809 * per MAC, just with differing status codes
1810 */
1811 for (j = 0; j < i; ++j) {
1812 a1 = &priv->arl_table[j];
1813 if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
1814 /* ignore ports already seen in former entry */
1815 a->portmap &= ~a1->portmap;
1816 if (!a->portmap)
1817 goto duplicate;
1818 }
1819 }
1820 }
1821
1822 mutex_unlock(&bus->mdio_lock);
1823
1824 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1825 "address resolution table\n");
1826
1827 if (i == AR8XXX_NUM_ARL_RECORDS)
1828 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1829 "Too many entries found, displaying the first %d only!\n",
1830 AR8XXX_NUM_ARL_RECORDS);
1831
1832 for (j = 0; j < priv->dev.ports; ++j) {
1833 for (k = 0; k < i; ++k) {
1834 a = &priv->arl_table[k];
1835 if (!(a->portmap & BIT(j)))
1836 continue;
1837 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1838 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1839 j,
1840 a->mac[5], a->mac[4], a->mac[3],
1841 a->mac[2], a->mac[1], a->mac[0]);
1842 }
1843 }
1844
1845 val->value.s = buf;
1846 val->len = len;
1847
1848 mutex_unlock(&priv->reg_mutex);
1849
1850 return 0;
1851 }
1852
1853 int
1854 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1855 const struct switch_attr *attr,
1856 struct switch_val *val)
1857 {
1858 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1859 int ret;
1860
1861 mutex_lock(&priv->reg_mutex);
1862 ret = priv->chip->atu_flush(priv);
1863 mutex_unlock(&priv->reg_mutex);
1864
1865 return ret;
1866 }
1867
1868 int
1869 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1870 const struct switch_attr *attr,
1871 struct switch_val *val)
1872 {
1873 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1874 int port, ret;
1875
1876 port = val->port_vlan;
1877 if (port >= dev->ports)
1878 return -EINVAL;
1879
1880 mutex_lock(&priv->reg_mutex);
1881 ret = priv->chip->atu_flush_port(priv, port);
1882 mutex_unlock(&priv->reg_mutex);
1883
1884 return ret;
1885 }
1886
1887 int
1888 ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
1889 struct switch_port_stats *stats)
1890 {
1891 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1892 u64 *mib_stats;
1893
1894 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
1895 return -EOPNOTSUPP;
1896
1897 if (!(priv->chip->mib_rxb_id || priv->chip->mib_txb_id))
1898 return -EOPNOTSUPP;
1899
1900 if (port >= dev->ports)
1901 return -EINVAL;
1902
1903 mutex_lock(&priv->mib_lock);
1904
1905 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
1906
1907 stats->tx_bytes = mib_stats[priv->chip->mib_txb_id];
1908 stats->rx_bytes = mib_stats[priv->chip->mib_rxb_id];
1909
1910 mutex_unlock(&priv->mib_lock);
1911 return 0;
1912 }
1913
1914 static int
1915 ar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
1916 {
1917 struct ar8xxx_priv *priv = bus->priv;
1918 return priv->chip->phy_read(priv, phy_addr, reg_addr);
1919 }
1920
1921 static int
1922 ar8xxx_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr,
1923 u16 reg_val)
1924 {
1925 struct ar8xxx_priv *priv = bus->priv;
1926 return priv->chip->phy_write(priv, phy_addr, reg_addr, reg_val);
1927 }
1928
1929 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1930 {
1931 .type = SWITCH_TYPE_INT,
1932 .name = "enable_vlan",
1933 .description = "Enable VLAN mode",
1934 .set = ar8xxx_sw_set_vlan,
1935 .get = ar8xxx_sw_get_vlan,
1936 .max = 1
1937 },
1938 {
1939 .type = SWITCH_TYPE_NOVAL,
1940 .name = "reset_mibs",
1941 .description = "Reset all MIB counters",
1942 .set = ar8xxx_sw_set_reset_mibs,
1943 },
1944 {
1945 .type = SWITCH_TYPE_INT,
1946 .name = "ar8xxx_mib_poll_interval",
1947 .description = "MIB polling interval in msecs (0 to disable)",
1948 .set = ar8xxx_sw_set_mib_poll_interval,
1949 .get = ar8xxx_sw_get_mib_poll_interval
1950 },
1951 {
1952 .type = SWITCH_TYPE_INT,
1953 .name = "ar8xxx_mib_type",
1954 .description = "MIB type (0=basic 1=extended)",
1955 .set = ar8xxx_sw_set_mib_type,
1956 .get = ar8xxx_sw_get_mib_type
1957 },
1958 {
1959 .type = SWITCH_TYPE_INT,
1960 .name = "enable_mirror_rx",
1961 .description = "Enable mirroring of RX packets",
1962 .set = ar8xxx_sw_set_mirror_rx_enable,
1963 .get = ar8xxx_sw_get_mirror_rx_enable,
1964 .max = 1
1965 },
1966 {
1967 .type = SWITCH_TYPE_INT,
1968 .name = "enable_mirror_tx",
1969 .description = "Enable mirroring of TX packets",
1970 .set = ar8xxx_sw_set_mirror_tx_enable,
1971 .get = ar8xxx_sw_get_mirror_tx_enable,
1972 .max = 1
1973 },
1974 {
1975 .type = SWITCH_TYPE_INT,
1976 .name = "mirror_monitor_port",
1977 .description = "Mirror monitor port",
1978 .set = ar8xxx_sw_set_mirror_monitor_port,
1979 .get = ar8xxx_sw_get_mirror_monitor_port,
1980 .max = AR8216_NUM_PORTS - 1
1981 },
1982 {
1983 .type = SWITCH_TYPE_INT,
1984 .name = "mirror_source_port",
1985 .description = "Mirror source port",
1986 .set = ar8xxx_sw_set_mirror_source_port,
1987 .get = ar8xxx_sw_get_mirror_source_port,
1988 .max = AR8216_NUM_PORTS - 1
1989 },
1990 {
1991 .type = SWITCH_TYPE_STRING,
1992 .name = "arl_table",
1993 .description = "Get ARL table",
1994 .set = NULL,
1995 .get = ar8xxx_sw_get_arl_table,
1996 },
1997 {
1998 .type = SWITCH_TYPE_NOVAL,
1999 .name = "flush_arl_table",
2000 .description = "Flush ARL table",
2001 .set = ar8xxx_sw_set_flush_arl_table,
2002 },
2003 };
2004
2005 const struct switch_attr ar8xxx_sw_attr_port[] = {
2006 {
2007 .type = SWITCH_TYPE_NOVAL,
2008 .name = "reset_mib",
2009 .description = "Reset single port MIB counters",
2010 .set = ar8xxx_sw_set_port_reset_mib,
2011 },
2012 {
2013 .type = SWITCH_TYPE_STRING,
2014 .name = "mib",
2015 .description = "Get port's MIB counters",
2016 .set = NULL,
2017 .get = ar8xxx_sw_get_port_mib,
2018 },
2019 {
2020 .type = SWITCH_TYPE_NOVAL,
2021 .name = "flush_arl_table",
2022 .description = "Flush port's ARL table entries",
2023 .set = ar8xxx_sw_set_flush_port_arl_table,
2024 },
2025 };
2026
2027 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
2028 {
2029 .type = SWITCH_TYPE_INT,
2030 .name = "vid",
2031 .description = "VLAN ID (0-4094)",
2032 .set = ar8xxx_sw_set_vid,
2033 .get = ar8xxx_sw_get_vid,
2034 .max = 4094,
2035 },
2036 };
2037
2038 static const struct switch_dev_ops ar8xxx_sw_ops = {
2039 .attr_global = {
2040 .attr = ar8xxx_sw_attr_globals,
2041 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2042 },
2043 .attr_port = {
2044 .attr = ar8xxx_sw_attr_port,
2045 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2046 },
2047 .attr_vlan = {
2048 .attr = ar8xxx_sw_attr_vlan,
2049 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2050 },
2051 .get_port_pvid = ar8xxx_sw_get_pvid,
2052 .set_port_pvid = ar8xxx_sw_set_pvid,
2053 .get_vlan_ports = ar8xxx_sw_get_ports,
2054 .set_vlan_ports = ar8xxx_sw_set_ports,
2055 .apply_config = ar8xxx_sw_hw_apply,
2056 .reset_switch = ar8xxx_sw_reset_switch,
2057 .get_port_link = ar8xxx_sw_get_port_link,
2058 .get_port_stats = ar8xxx_sw_get_port_stats,
2059 };
2060
2061 static const struct ar8xxx_chip ar7240sw_chip = {
2062 .caps = AR8XXX_CAP_MIB_COUNTERS,
2063
2064 .reg_port_stats_start = 0x20000,
2065 .reg_port_stats_length = 0x100,
2066 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2067
2068 .name = "Atheros AR724X/AR933X built-in",
2069 .ports = AR7240SW_NUM_PORTS,
2070 .vlans = AR8216_NUM_VLANS,
2071 .swops = &ar8xxx_sw_ops,
2072
2073 .hw_init = ar7240sw_hw_init,
2074 .init_globals = ar7240sw_init_globals,
2075 .init_port = ar8229_init_port,
2076 .phy_read = ar8216_phy_read,
2077 .phy_write = ar8216_phy_write,
2078 .setup_port = ar7240sw_setup_port,
2079 .read_port_status = ar8216_read_port_status,
2080 .atu_flush = ar8216_atu_flush,
2081 .atu_flush_port = ar8216_atu_flush_port,
2082 .vtu_flush = ar8216_vtu_flush,
2083 .vtu_load_vlan = ar8216_vtu_load_vlan,
2084 .set_mirror_regs = ar8216_set_mirror_regs,
2085 .get_arl_entry = ar8216_get_arl_entry,
2086 .sw_hw_apply = ar8xxx_sw_hw_apply,
2087
2088 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2089 .mib_decs = ar8236_mibs,
2090 .mib_func = AR8216_REG_MIB_FUNC,
2091 .mib_rxb_id = AR8236_MIB_RXB_ID,
2092 .mib_txb_id = AR8236_MIB_TXB_ID,
2093 };
2094
2095 static const struct ar8xxx_chip ar8216_chip = {
2096 .caps = AR8XXX_CAP_MIB_COUNTERS,
2097
2098 .reg_port_stats_start = 0x19000,
2099 .reg_port_stats_length = 0xa0,
2100 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2101
2102 .name = "Atheros AR8216",
2103 .ports = AR8216_NUM_PORTS,
2104 .vlans = AR8216_NUM_VLANS,
2105 .swops = &ar8xxx_sw_ops,
2106
2107 .hw_init = ar8216_hw_init,
2108 .init_globals = ar8216_init_globals,
2109 .init_port = ar8216_init_port,
2110 .setup_port = ar8216_setup_port,
2111 .read_port_status = ar8216_read_port_status,
2112 .atu_flush = ar8216_atu_flush,
2113 .atu_flush_port = ar8216_atu_flush_port,
2114 .vtu_flush = ar8216_vtu_flush,
2115 .vtu_load_vlan = ar8216_vtu_load_vlan,
2116 .set_mirror_regs = ar8216_set_mirror_regs,
2117 .get_arl_entry = ar8216_get_arl_entry,
2118 .sw_hw_apply = ar8xxx_sw_hw_apply,
2119
2120 .num_mibs = ARRAY_SIZE(ar8216_mibs),
2121 .mib_decs = ar8216_mibs,
2122 .mib_func = AR8216_REG_MIB_FUNC,
2123 .mib_rxb_id = AR8216_MIB_RXB_ID,
2124 .mib_txb_id = AR8216_MIB_TXB_ID,
2125 };
2126
2127 static const struct ar8xxx_chip ar8229_chip = {
2128 .caps = AR8XXX_CAP_MIB_COUNTERS,
2129
2130 .reg_port_stats_start = 0x20000,
2131 .reg_port_stats_length = 0x100,
2132 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2133
2134 .name = "Atheros AR8229",
2135 .ports = AR8216_NUM_PORTS,
2136 .vlans = AR8216_NUM_VLANS,
2137 .swops = &ar8xxx_sw_ops,
2138
2139 .hw_init = ar8229_hw_init,
2140 .init_globals = ar8229_init_globals,
2141 .init_port = ar8229_init_port,
2142 .phy_read = ar8216_phy_read,
2143 .phy_write = ar8216_phy_write,
2144 .setup_port = ar8236_setup_port,
2145 .read_port_status = ar8216_read_port_status,
2146 .atu_flush = ar8216_atu_flush,
2147 .atu_flush_port = ar8216_atu_flush_port,
2148 .vtu_flush = ar8216_vtu_flush,
2149 .vtu_load_vlan = ar8216_vtu_load_vlan,
2150 .set_mirror_regs = ar8216_set_mirror_regs,
2151 .get_arl_entry = ar8216_get_arl_entry,
2152 .sw_hw_apply = ar8xxx_sw_hw_apply,
2153
2154 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2155 .mib_decs = ar8236_mibs,
2156 .mib_func = AR8216_REG_MIB_FUNC,
2157 .mib_rxb_id = AR8236_MIB_RXB_ID,
2158 .mib_txb_id = AR8236_MIB_TXB_ID,
2159 };
2160
2161 static const struct ar8xxx_chip ar8236_chip = {
2162 .caps = AR8XXX_CAP_MIB_COUNTERS,
2163
2164 .reg_port_stats_start = 0x20000,
2165 .reg_port_stats_length = 0x100,
2166 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2167
2168 .name = "Atheros AR8236",
2169 .ports = AR8216_NUM_PORTS,
2170 .vlans = AR8216_NUM_VLANS,
2171 .swops = &ar8xxx_sw_ops,
2172
2173 .hw_init = ar8216_hw_init,
2174 .init_globals = ar8236_init_globals,
2175 .init_port = ar8216_init_port,
2176 .setup_port = ar8236_setup_port,
2177 .read_port_status = ar8216_read_port_status,
2178 .atu_flush = ar8216_atu_flush,
2179 .atu_flush_port = ar8216_atu_flush_port,
2180 .vtu_flush = ar8216_vtu_flush,
2181 .vtu_load_vlan = ar8216_vtu_load_vlan,
2182 .set_mirror_regs = ar8216_set_mirror_regs,
2183 .get_arl_entry = ar8216_get_arl_entry,
2184 .sw_hw_apply = ar8xxx_sw_hw_apply,
2185
2186 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2187 .mib_decs = ar8236_mibs,
2188 .mib_func = AR8216_REG_MIB_FUNC,
2189 .mib_rxb_id = AR8236_MIB_RXB_ID,
2190 .mib_txb_id = AR8236_MIB_TXB_ID,
2191 };
2192
2193 static const struct ar8xxx_chip ar8316_chip = {
2194 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2195
2196 .reg_port_stats_start = 0x20000,
2197 .reg_port_stats_length = 0x100,
2198 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2199
2200 .name = "Atheros AR8316",
2201 .ports = AR8216_NUM_PORTS,
2202 .vlans = AR8X16_MAX_VLANS,
2203 .swops = &ar8xxx_sw_ops,
2204
2205 .hw_init = ar8316_hw_init,
2206 .init_globals = ar8316_init_globals,
2207 .init_port = ar8216_init_port,
2208 .setup_port = ar8216_setup_port,
2209 .read_port_status = ar8216_read_port_status,
2210 .atu_flush = ar8216_atu_flush,
2211 .atu_flush_port = ar8216_atu_flush_port,
2212 .vtu_flush = ar8216_vtu_flush,
2213 .vtu_load_vlan = ar8216_vtu_load_vlan,
2214 .set_mirror_regs = ar8216_set_mirror_regs,
2215 .get_arl_entry = ar8216_get_arl_entry,
2216 .sw_hw_apply = ar8xxx_sw_hw_apply,
2217
2218 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2219 .mib_decs = ar8236_mibs,
2220 .mib_func = AR8216_REG_MIB_FUNC,
2221 .mib_rxb_id = AR8236_MIB_RXB_ID,
2222 .mib_txb_id = AR8236_MIB_TXB_ID,
2223 };
2224
2225 static int
2226 ar8xxx_read_id(struct ar8xxx_priv *priv)
2227 {
2228 u32 val;
2229 u16 id;
2230 int i;
2231
2232 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2233 if (val == ~0)
2234 return -ENODEV;
2235
2236 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2237 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2238 u16 t;
2239
2240 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2241 if (val == ~0)
2242 return -ENODEV;
2243
2244 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2245 if (t != id)
2246 return -ENODEV;
2247 }
2248
2249 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2250 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2251 return 0;
2252 }
2253
2254 static int
2255 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2256 {
2257 int ret;
2258
2259 ret = ar8xxx_read_id(priv);
2260 if(ret)
2261 return ret;
2262
2263 switch (priv->chip_ver) {
2264 case AR8XXX_VER_AR8216:
2265 priv->chip = &ar8216_chip;
2266 break;
2267 case AR8XXX_VER_AR8236:
2268 priv->chip = &ar8236_chip;
2269 break;
2270 case AR8XXX_VER_AR8316:
2271 priv->chip = &ar8316_chip;
2272 break;
2273 case AR8XXX_VER_AR8327:
2274 priv->chip = &ar8327_chip;
2275 break;
2276 case AR8XXX_VER_AR8337:
2277 priv->chip = &ar8337_chip;
2278 break;
2279 default:
2280 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2281 priv->chip_ver, priv->chip_rev);
2282
2283 return -ENODEV;
2284 }
2285
2286 return 0;
2287 }
2288
2289 static void
2290 ar8xxx_mib_work_func(struct work_struct *work)
2291 {
2292 struct ar8xxx_priv *priv;
2293 int err, i;
2294
2295 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2296
2297 mutex_lock(&priv->mib_lock);
2298
2299 err = ar8xxx_mib_capture(priv);
2300 if (err)
2301 goto next_attempt;
2302
2303 for (i = 0; i < priv->dev.ports; i++)
2304 ar8xxx_mib_fetch_port_stat(priv, i, false);
2305
2306 next_attempt:
2307 mutex_unlock(&priv->mib_lock);
2308 schedule_delayed_work(&priv->mib_work,
2309 msecs_to_jiffies(priv->mib_poll_interval));
2310 }
2311
2312 static int
2313 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2314 {
2315 unsigned int len;
2316
2317 if (!ar8xxx_has_mib_counters(priv))
2318 return 0;
2319
2320 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2321
2322 len = priv->dev.ports * priv->chip->num_mibs *
2323 sizeof(*priv->mib_stats);
2324 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2325
2326 if (!priv->mib_stats)
2327 return -ENOMEM;
2328
2329 return 0;
2330 }
2331
2332 static void
2333 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2334 {
2335 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
2336 return;
2337
2338 schedule_delayed_work(&priv->mib_work,
2339 msecs_to_jiffies(priv->mib_poll_interval));
2340 }
2341
2342 static void
2343 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2344 {
2345 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
2346 return;
2347
2348 cancel_delayed_work_sync(&priv->mib_work);
2349 }
2350
2351 static struct ar8xxx_priv *
2352 ar8xxx_create(void)
2353 {
2354 struct ar8xxx_priv *priv;
2355
2356 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2357 if (priv == NULL)
2358 return NULL;
2359
2360 mutex_init(&priv->reg_mutex);
2361 mutex_init(&priv->mib_lock);
2362 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2363
2364 return priv;
2365 }
2366
2367 static void
2368 ar8xxx_free(struct ar8xxx_priv *priv)
2369 {
2370 if (priv->chip && priv->chip->cleanup)
2371 priv->chip->cleanup(priv);
2372
2373 kfree(priv->chip_data);
2374 kfree(priv->mib_stats);
2375 kfree(priv);
2376 }
2377
2378 static int
2379 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2380 {
2381 const struct ar8xxx_chip *chip;
2382 struct switch_dev *swdev;
2383 int ret;
2384
2385 chip = priv->chip;
2386
2387 swdev = &priv->dev;
2388 swdev->cpu_port = AR8216_PORT_CPU;
2389 swdev->name = chip->name;
2390 swdev->vlans = chip->vlans;
2391 swdev->ports = chip->ports;
2392 swdev->ops = chip->swops;
2393
2394 ret = ar8xxx_mib_init(priv);
2395 if (ret)
2396 return ret;
2397
2398 return 0;
2399 }
2400
2401 static int
2402 ar8xxx_start(struct ar8xxx_priv *priv)
2403 {
2404 int ret;
2405
2406 priv->init = true;
2407
2408 ret = priv->chip->hw_init(priv);
2409 if (ret)
2410 return ret;
2411
2412 ret = ar8xxx_sw_reset_switch(&priv->dev);
2413 if (ret)
2414 return ret;
2415
2416 priv->init = false;
2417
2418 ar8xxx_mib_start(priv);
2419
2420 return 0;
2421 }
2422
2423 static int
2424 ar8xxx_phy_config_init(struct phy_device *phydev)
2425 {
2426 struct ar8xxx_priv *priv = phydev->priv;
2427 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
2428 struct net_device *dev = phydev->attached_dev;
2429 #endif
2430 int ret;
2431
2432 if (WARN_ON(!priv))
2433 return -ENODEV;
2434
2435 if (priv->chip->config_at_probe)
2436 return ar8xxx_phy_check_aneg(phydev);
2437
2438 priv->phy = phydev;
2439
2440 if (phydev->mdio.addr != 0) {
2441 if (chip_is_ar8316(priv)) {
2442 /* switch device has been initialized, reinit */
2443 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2444 priv->initialized = false;
2445 priv->port4_phy = true;
2446 ar8316_hw_init(priv);
2447 return 0;
2448 }
2449
2450 return 0;
2451 }
2452
2453 ret = ar8xxx_start(priv);
2454 if (ret)
2455 return ret;
2456
2457 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
2458 /* VID fixup only needed on ar8216 */
2459 if (chip_is_ar8216(priv)) {
2460 dev->phy_ptr = priv;
2461 #if LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)
2462 dev->priv_flags |= IFF_NO_IP_ALIGN;
2463 #else
2464 dev->extra_priv_flags |= IFF_NO_IP_ALIGN;
2465 #endif
2466 dev->eth_mangle_rx = ar8216_mangle_rx;
2467 dev->eth_mangle_tx = ar8216_mangle_tx;
2468 }
2469 #endif
2470
2471 return 0;
2472 }
2473
2474 static bool
2475 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2476 {
2477 bool link_new, changed = false;
2478 u32 status;
2479 int i;
2480
2481 mutex_lock(&priv->reg_mutex);
2482
2483 for (i = 0; i < priv->dev.ports; i++) {
2484 status = priv->chip->read_port_status(priv, i);
2485 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2486 if (link_new == priv->link_up[i])
2487 continue;
2488
2489 priv->link_up[i] = link_new;
2490 changed = true;
2491 /* flush ARL entries for this port if it went down*/
2492 if (!link_new)
2493 priv->chip->atu_flush_port(priv, i);
2494 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2495 i, link_new ? "up" : "down");
2496 }
2497
2498 mutex_unlock(&priv->reg_mutex);
2499
2500 return changed;
2501 }
2502
2503 static int
2504 ar8xxx_phy_read_status(struct phy_device *phydev)
2505 {
2506 struct ar8xxx_priv *priv = phydev->priv;
2507 struct switch_port_link link;
2508
2509 /* check for switch port link changes */
2510 ar8xxx_check_link_states(priv);
2511
2512 if (phydev->mdio.addr != 0)
2513 return genphy_read_status(phydev);
2514
2515 ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2516 phydev->link = !!link.link;
2517 if (!phydev->link)
2518 return 0;
2519
2520 switch (link.speed) {
2521 case SWITCH_PORT_SPEED_10:
2522 phydev->speed = SPEED_10;
2523 break;
2524 case SWITCH_PORT_SPEED_100:
2525 phydev->speed = SPEED_100;
2526 break;
2527 case SWITCH_PORT_SPEED_1000:
2528 phydev->speed = SPEED_1000;
2529 break;
2530 default:
2531 phydev->speed = 0;
2532 }
2533 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2534
2535 phydev->state = PHY_RUNNING;
2536 netif_carrier_on(phydev->attached_dev);
2537 if (phydev->adjust_link)
2538 phydev->adjust_link(phydev->attached_dev);
2539
2540 return 0;
2541 }
2542
2543 static int
2544 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2545 {
2546 if (phydev->mdio.addr == 0)
2547 return 0;
2548
2549 return genphy_config_aneg(phydev);
2550 }
2551
2552 static int
2553 ar8xxx_get_features(struct phy_device *phydev)
2554 {
2555 struct ar8xxx_priv *priv = phydev->priv;
2556
2557 linkmode_copy(phydev->supported, PHY_BASIC_FEATURES);
2558 if (ar8xxx_has_gige(priv))
2559 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported);
2560
2561 return 0;
2562 }
2563
2564 static const u32 ar8xxx_phy_ids[] = {
2565 0x004dd033,
2566 0x004dd034, /* AR8327 */
2567 0x004dd036, /* AR8337 */
2568 0x004dd041,
2569 0x004dd042,
2570 0x004dd043, /* AR8236 */
2571 };
2572
2573 static bool
2574 ar8xxx_phy_match(u32 phy_id)
2575 {
2576 int i;
2577
2578 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2579 if (phy_id == ar8xxx_phy_ids[i])
2580 return true;
2581
2582 return false;
2583 }
2584
2585 static bool
2586 ar8xxx_is_possible(struct mii_bus *bus)
2587 {
2588 unsigned int i, found_phys = 0;
2589
2590 for (i = 0; i < 5; i++) {
2591 u32 phy_id;
2592
2593 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2594 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2595 if (ar8xxx_phy_match(phy_id)) {
2596 found_phys++;
2597 } else if (phy_id) {
2598 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2599 dev_name(&bus->dev), i, phy_id);
2600 }
2601 }
2602 return !!found_phys;
2603 }
2604
2605 static int
2606 ar8xxx_phy_probe(struct phy_device *phydev)
2607 {
2608 struct ar8xxx_priv *priv;
2609 struct switch_dev *swdev;
2610 int ret;
2611
2612 /* skip PHYs at unused adresses */
2613 if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
2614 return -ENODEV;
2615
2616 if (!ar8xxx_is_possible(phydev->mdio.bus))
2617 return -ENODEV;
2618
2619 mutex_lock(&ar8xxx_dev_list_lock);
2620 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2621 if (priv->mii_bus == phydev->mdio.bus)
2622 goto found;
2623
2624 priv = ar8xxx_create();
2625 if (priv == NULL) {
2626 ret = -ENOMEM;
2627 goto unlock;
2628 }
2629
2630 priv->mii_bus = phydev->mdio.bus;
2631 priv->pdev = &phydev->mdio.dev;
2632
2633 ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
2634 &priv->mib_poll_interval);
2635 if (ret)
2636 priv->mib_poll_interval = 0;
2637
2638 ret = ar8xxx_id_chip(priv);
2639 if (ret)
2640 goto free_priv;
2641
2642 ret = ar8xxx_probe_switch(priv);
2643 if (ret)
2644 goto free_priv;
2645
2646 swdev = &priv->dev;
2647 swdev->alias = dev_name(&priv->mii_bus->dev);
2648 ret = register_switch(swdev, NULL);
2649 if (ret)
2650 goto free_priv;
2651
2652 pr_info("%s: %s rev. %u switch registered on %s\n",
2653 swdev->devname, swdev->name, priv->chip_rev,
2654 dev_name(&priv->mii_bus->dev));
2655
2656 list_add(&priv->list, &ar8xxx_dev_list);
2657
2658 found:
2659 priv->use_count++;
2660
2661 if (phydev->mdio.addr == 0 && priv->chip->config_at_probe) {
2662 priv->phy = phydev;
2663
2664 ret = ar8xxx_start(priv);
2665 if (ret)
2666 goto err_unregister_switch;
2667 } else if (priv->chip->phy_rgmii_set) {
2668 priv->chip->phy_rgmii_set(priv, phydev);
2669 }
2670
2671 phydev->priv = priv;
2672
2673 mutex_unlock(&ar8xxx_dev_list_lock);
2674
2675 return 0;
2676
2677 err_unregister_switch:
2678 if (--priv->use_count)
2679 goto unlock;
2680
2681 unregister_switch(&priv->dev);
2682
2683 free_priv:
2684 ar8xxx_free(priv);
2685 unlock:
2686 mutex_unlock(&ar8xxx_dev_list_lock);
2687 return ret;
2688 }
2689
2690 static void
2691 ar8xxx_phy_detach(struct phy_device *phydev)
2692 {
2693 struct net_device *dev = phydev->attached_dev;
2694
2695 if (!dev)
2696 return;
2697
2698 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
2699 dev->phy_ptr = NULL;
2700 #if LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)
2701 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2702 #else
2703 dev->extra_priv_flags &= ~IFF_NO_IP_ALIGN;
2704 #endif
2705 dev->eth_mangle_rx = NULL;
2706 dev->eth_mangle_tx = NULL;
2707 #endif
2708 }
2709
2710 static void
2711 ar8xxx_phy_remove(struct phy_device *phydev)
2712 {
2713 struct ar8xxx_priv *priv = phydev->priv;
2714
2715 if (WARN_ON(!priv))
2716 return;
2717
2718 phydev->priv = NULL;
2719
2720 mutex_lock(&ar8xxx_dev_list_lock);
2721
2722 if (--priv->use_count > 0) {
2723 mutex_unlock(&ar8xxx_dev_list_lock);
2724 return;
2725 }
2726
2727 list_del(&priv->list);
2728 mutex_unlock(&ar8xxx_dev_list_lock);
2729
2730 unregister_switch(&priv->dev);
2731 ar8xxx_mib_stop(priv);
2732 ar8xxx_free(priv);
2733 }
2734
2735 static struct phy_driver ar8xxx_phy_driver[] = {
2736 {
2737 .phy_id = 0x004d0000,
2738 .name = "Atheros AR8216/AR8236/AR8316",
2739 .phy_id_mask = 0xffff0000,
2740 .probe = ar8xxx_phy_probe,
2741 .remove = ar8xxx_phy_remove,
2742 .detach = ar8xxx_phy_detach,
2743 .config_init = ar8xxx_phy_config_init,
2744 .config_aneg = ar8xxx_phy_config_aneg,
2745 .read_status = ar8xxx_phy_read_status,
2746 .get_features = ar8xxx_get_features,
2747 }
2748 };
2749
2750 static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
2751 {
2752 .compatible = "qca,ar7240sw",
2753 .data = &ar7240sw_chip,
2754 }, {
2755 .compatible = "qca,ar8229",
2756 .data = &ar8229_chip,
2757 }, {
2758 .compatible = "qca,ar8236",
2759 .data = &ar8236_chip,
2760 }, {
2761 .compatible = "qca,ar8327",
2762 .data = &ar8327_chip,
2763 },
2764 { /* sentinel */ },
2765 };
2766
2767 static int
2768 ar8xxx_mdiodev_probe(struct mdio_device *mdiodev)
2769 {
2770 const struct of_device_id *match;
2771 struct ar8xxx_priv *priv;
2772 struct switch_dev *swdev;
2773 struct device_node *mdio_node;
2774 int ret;
2775
2776 match = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev);
2777 if (!match)
2778 return -EINVAL;
2779
2780 priv = ar8xxx_create();
2781 if (priv == NULL)
2782 return -ENOMEM;
2783
2784 priv->mii_bus = mdiodev->bus;
2785 priv->pdev = &mdiodev->dev;
2786 priv->chip = (const struct ar8xxx_chip *) match->data;
2787
2788 ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
2789 &priv->mib_poll_interval);
2790 if (ret)
2791 priv->mib_poll_interval = 0;
2792
2793 ret = ar8xxx_read_id(priv);
2794 if (ret)
2795 goto free_priv;
2796
2797 ret = ar8xxx_probe_switch(priv);
2798 if (ret)
2799 goto free_priv;
2800
2801 if (priv->chip->phy_read && priv->chip->phy_write) {
2802 priv->sw_mii_bus = devm_mdiobus_alloc(&mdiodev->dev);
2803 priv->sw_mii_bus->name = "ar8xxx-mdio";
2804 priv->sw_mii_bus->read = ar8xxx_phy_read;
2805 priv->sw_mii_bus->write = ar8xxx_phy_write;
2806 priv->sw_mii_bus->priv = priv;
2807 priv->sw_mii_bus->parent = &mdiodev->dev;
2808 snprintf(priv->sw_mii_bus->id, MII_BUS_ID_SIZE, "%s",
2809 dev_name(&mdiodev->dev));
2810 mdio_node = of_get_child_by_name(priv->pdev->of_node, "mdio-bus");
2811 ret = of_mdiobus_register(priv->sw_mii_bus, mdio_node);
2812 if (ret)
2813 goto free_priv;
2814 }
2815
2816 swdev = &priv->dev;
2817 swdev->alias = dev_name(&mdiodev->dev);
2818
2819 if (of_property_read_bool(priv->pdev->of_node, "qca,phy4-mii-enable")) {
2820 priv->port4_phy = true;
2821 swdev->ports--;
2822 }
2823
2824 ret = register_switch(swdev, NULL);
2825 if (ret)
2826 goto free_priv;
2827
2828 pr_info("%s: %s rev. %u switch registered on %s\n",
2829 swdev->devname, swdev->name, priv->chip_rev,
2830 dev_name(&priv->mii_bus->dev));
2831
2832 mutex_lock(&ar8xxx_dev_list_lock);
2833 list_add(&priv->list, &ar8xxx_dev_list);
2834 mutex_unlock(&ar8xxx_dev_list_lock);
2835
2836 priv->use_count++;
2837
2838 ret = ar8xxx_start(priv);
2839 if (ret)
2840 goto err_unregister_switch;
2841
2842 dev_set_drvdata(&mdiodev->dev, priv);
2843
2844 return 0;
2845
2846 err_unregister_switch:
2847 if (--priv->use_count)
2848 return ret;
2849
2850 unregister_switch(&priv->dev);
2851
2852 free_priv:
2853 ar8xxx_free(priv);
2854 return ret;
2855 }
2856
2857 static void
2858 ar8xxx_mdiodev_remove(struct mdio_device *mdiodev)
2859 {
2860 struct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev);
2861
2862 if (WARN_ON(!priv))
2863 return;
2864
2865 mutex_lock(&ar8xxx_dev_list_lock);
2866
2867 if (--priv->use_count > 0) {
2868 mutex_unlock(&ar8xxx_dev_list_lock);
2869 return;
2870 }
2871
2872 list_del(&priv->list);
2873 mutex_unlock(&ar8xxx_dev_list_lock);
2874
2875 unregister_switch(&priv->dev);
2876 ar8xxx_mib_stop(priv);
2877 if(priv->sw_mii_bus)
2878 mdiobus_unregister(priv->sw_mii_bus);
2879 ar8xxx_free(priv);
2880 }
2881
2882 static struct mdio_driver ar8xxx_mdio_driver = {
2883 .probe = ar8xxx_mdiodev_probe,
2884 .remove = ar8xxx_mdiodev_remove,
2885 .mdiodrv.driver = {
2886 .name = "ar8xxx-switch",
2887 .of_match_table = ar8xxx_mdiodev_of_match,
2888 },
2889 };
2890
2891 static int __init ar8216_init(void)
2892 {
2893 int ret;
2894
2895 ret = phy_drivers_register(ar8xxx_phy_driver,
2896 ARRAY_SIZE(ar8xxx_phy_driver),
2897 THIS_MODULE);
2898 if (ret)
2899 return ret;
2900
2901 ret = mdio_driver_register(&ar8xxx_mdio_driver);
2902 if (ret)
2903 phy_drivers_unregister(ar8xxx_phy_driver,
2904 ARRAY_SIZE(ar8xxx_phy_driver));
2905
2906 return ret;
2907 }
2908 module_init(ar8216_init);
2909
2910 static void __exit ar8216_exit(void)
2911 {
2912 mdio_driver_unregister(&ar8xxx_mdio_driver);
2913 phy_drivers_unregister(ar8xxx_phy_driver,
2914 ARRAY_SIZE(ar8xxx_phy_driver));
2915 }
2916 module_exit(ar8216_exit);
2917
2918 MODULE_LICENSE("GPL");
OpenWrt Source Repository