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ar8216: replace ar8xxx_rmw with ar8xxx_reg_set where appropriate
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
37
38 #include "ar8216.h"
39
40 extern const struct ar8xxx_chip ar8327_chip;
41 extern const struct ar8xxx_chip ar8337_chip;
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 #define MIB_DESC(_s , _o, _n) \
46 { \
47 .size = (_s), \
48 .offset = (_o), \
49 .name = (_n), \
50 }
51
52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
90 };
91
92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
132 };
133
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
135 static LIST_HEAD(ar8xxx_dev_list);
136
137 static inline void
138 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
139 {
140 regaddr >>= 1;
141 *r1 = regaddr & 0x1e;
142
143 regaddr >>= 5;
144 *r2 = regaddr & 0x7;
145
146 regaddr >>= 3;
147 *page = regaddr & 0x1ff;
148 }
149
150 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
151 static int
152 ar8xxx_phy_poll_reset(struct mii_bus *bus)
153 {
154 unsigned int sleep_msecs = 20;
155 int ret, elapsed, i;
156
157 for (elapsed = sleep_msecs; elapsed <= 600;
158 elapsed += sleep_msecs) {
159 msleep(sleep_msecs);
160 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
161 ret = mdiobus_read(bus, i, MII_BMCR);
162 if (ret < 0)
163 return ret;
164 if (ret & BMCR_RESET)
165 break;
166 if (i == AR8XXX_NUM_PHYS - 1) {
167 usleep_range(1000, 2000);
168 return 0;
169 }
170 }
171 }
172 return -ETIMEDOUT;
173 }
174
175 static int
176 ar8xxx_phy_check_aneg(struct phy_device *phydev)
177 {
178 int ret;
179
180 if (phydev->autoneg != AUTONEG_ENABLE)
181 return 0;
182 /*
183 * BMCR_ANENABLE might have been cleared
184 * by phy_init_hw in certain kernel versions
185 * therefore check for it
186 */
187 ret = phy_read(phydev, MII_BMCR);
188 if (ret < 0)
189 return ret;
190 if (ret & BMCR_ANENABLE)
191 return 0;
192
193 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
194 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
195 return phy_write(phydev, MII_BMCR, ret);
196 }
197
198 void
199 ar8xxx_phy_init(struct ar8xxx_priv *priv)
200 {
201 int i;
202 struct mii_bus *bus;
203
204 bus = priv->mii_bus;
205 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
206 if (priv->chip->phy_fixup)
207 priv->chip->phy_fixup(priv, i);
208
209 /* initialize the port itself */
210 mdiobus_write(bus, i, MII_ADVERTISE,
211 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
212 if (ar8xxx_has_gige(priv))
213 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
214 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
215 }
216
217 ar8xxx_phy_poll_reset(bus);
218 }
219
220 static u32
221 mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
222 {
223 struct mii_bus *bus = priv->mii_bus;
224 u16 lo, hi;
225
226 lo = bus->read(bus, phy_id, regnum);
227 hi = bus->read(bus, phy_id, regnum + 1);
228
229 return (hi << 16) | lo;
230 }
231
232 static void
233 mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
234 {
235 struct mii_bus *bus = priv->mii_bus;
236 u16 lo, hi;
237
238 lo = val & 0xffff;
239 hi = (u16) (val >> 16);
240
241 if (priv->chip->mii_lo_first)
242 {
243 bus->write(bus, phy_id, regnum, lo);
244 bus->write(bus, phy_id, regnum + 1, hi);
245 } else {
246 bus->write(bus, phy_id, regnum + 1, hi);
247 bus->write(bus, phy_id, regnum, lo);
248 }
249 }
250
251 u32
252 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
253 {
254 struct mii_bus *bus = priv->mii_bus;
255 u16 r1, r2, page;
256 u32 val;
257
258 split_addr((u32) reg, &r1, &r2, &page);
259
260 mutex_lock(&bus->mdio_lock);
261
262 bus->write(bus, 0x18, 0, page);
263 usleep_range(1000, 2000); /* wait for the page switch to propagate */
264 val = mii_read32(priv, 0x10 | r2, r1);
265
266 mutex_unlock(&bus->mdio_lock);
267
268 return val;
269 }
270
271 void
272 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
273 {
274 struct mii_bus *bus = priv->mii_bus;
275 u16 r1, r2, page;
276
277 split_addr((u32) reg, &r1, &r2, &page);
278
279 mutex_lock(&bus->mdio_lock);
280
281 bus->write(bus, 0x18, 0, page);
282 usleep_range(1000, 2000); /* wait for the page switch to propagate */
283 mii_write32(priv, 0x10 | r2, r1, val);
284
285 mutex_unlock(&bus->mdio_lock);
286 }
287
288 u32
289 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
290 {
291 struct mii_bus *bus = priv->mii_bus;
292 u16 r1, r2, page;
293 u32 ret;
294
295 split_addr((u32) reg, &r1, &r2, &page);
296
297 mutex_lock(&bus->mdio_lock);
298
299 bus->write(bus, 0x18, 0, page);
300 usleep_range(1000, 2000); /* wait for the page switch to propagate */
301
302 ret = mii_read32(priv, 0x10 | r2, r1);
303 ret &= ~mask;
304 ret |= val;
305 mii_write32(priv, 0x10 | r2, r1, ret);
306
307 mutex_unlock(&bus->mdio_lock);
308
309 return ret;
310 }
311
312 void
313 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
314 u16 dbg_addr, u16 dbg_data)
315 {
316 struct mii_bus *bus = priv->mii_bus;
317
318 mutex_lock(&bus->mdio_lock);
319 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
320 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
321 mutex_unlock(&bus->mdio_lock);
322 }
323
324 void
325 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
326 {
327 struct mii_bus *bus = priv->mii_bus;
328
329 mutex_lock(&bus->mdio_lock);
330 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
331 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
332 mutex_unlock(&bus->mdio_lock);
333 }
334
335 static int
336 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
337 unsigned timeout)
338 {
339 int i;
340
341 for (i = 0; i < timeout; i++) {
342 u32 t;
343
344 t = ar8xxx_read(priv, reg);
345 if ((t & mask) == val)
346 return 0;
347
348 usleep_range(1000, 2000);
349 }
350
351 return -ETIMEDOUT;
352 }
353
354 static int
355 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
356 {
357 unsigned mib_func = priv->chip->mib_func;
358 int ret;
359
360 lockdep_assert_held(&priv->mib_lock);
361
362 /* Capture the hardware statistics for all ports */
363 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
364
365 /* Wait for the capturing to complete. */
366 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
367 if (ret)
368 goto out;
369
370 ret = 0;
371
372 out:
373 return ret;
374 }
375
376 static int
377 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
378 {
379 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
380 }
381
382 static int
383 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
384 {
385 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
386 }
387
388 static void
389 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
390 {
391 unsigned int base;
392 u64 *mib_stats;
393 int i;
394
395 WARN_ON(port >= priv->dev.ports);
396
397 lockdep_assert_held(&priv->mib_lock);
398
399 base = priv->chip->reg_port_stats_start +
400 priv->chip->reg_port_stats_length * port;
401
402 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
403 for (i = 0; i < priv->chip->num_mibs; i++) {
404 const struct ar8xxx_mib_desc *mib;
405 u64 t;
406
407 mib = &priv->chip->mib_decs[i];
408 t = ar8xxx_read(priv, base + mib->offset);
409 if (mib->size == 2) {
410 u64 hi;
411
412 hi = ar8xxx_read(priv, base + mib->offset + 4);
413 t |= hi << 32;
414 }
415
416 if (flush)
417 mib_stats[i] = 0;
418 else
419 mib_stats[i] += t;
420 }
421 }
422
423 static void
424 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
425 struct switch_port_link *link)
426 {
427 u32 status;
428 u32 speed;
429
430 memset(link, '\0', sizeof(*link));
431
432 status = priv->chip->read_port_status(priv, port);
433
434 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
435 if (link->aneg) {
436 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
437 } else {
438 link->link = true;
439
440 if (priv->get_port_link) {
441 int err;
442
443 err = priv->get_port_link(port);
444 if (err >= 0)
445 link->link = !!err;
446 }
447 }
448
449 if (!link->link)
450 return;
451
452 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
453 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
454 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
455
456 speed = (status & AR8216_PORT_STATUS_SPEED) >>
457 AR8216_PORT_STATUS_SPEED_S;
458
459 switch (speed) {
460 case AR8216_PORT_SPEED_10M:
461 link->speed = SWITCH_PORT_SPEED_10;
462 break;
463 case AR8216_PORT_SPEED_100M:
464 link->speed = SWITCH_PORT_SPEED_100;
465 break;
466 case AR8216_PORT_SPEED_1000M:
467 link->speed = SWITCH_PORT_SPEED_1000;
468 break;
469 default:
470 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
471 break;
472 }
473 }
474
475 static struct sk_buff *
476 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
477 {
478 struct ar8xxx_priv *priv = dev->phy_ptr;
479 unsigned char *buf;
480
481 if (unlikely(!priv))
482 goto error;
483
484 if (!priv->vlan)
485 goto send;
486
487 if (unlikely(skb_headroom(skb) < 2)) {
488 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
489 goto error;
490 }
491
492 buf = skb_push(skb, 2);
493 buf[0] = 0x10;
494 buf[1] = 0x80;
495
496 send:
497 return skb;
498
499 error:
500 dev_kfree_skb_any(skb);
501 return NULL;
502 }
503
504 static void
505 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
506 {
507 struct ar8xxx_priv *priv;
508 unsigned char *buf;
509 int port, vlan;
510
511 priv = dev->phy_ptr;
512 if (!priv)
513 return;
514
515 /* don't strip the header if vlan mode is disabled */
516 if (!priv->vlan)
517 return;
518
519 /* strip header, get vlan id */
520 buf = skb->data;
521 skb_pull(skb, 2);
522
523 /* check for vlan header presence */
524 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
525 return;
526
527 port = buf[0] & 0xf;
528
529 /* no need to fix up packets coming from a tagged source */
530 if (priv->vlan_tagged & (1 << port))
531 return;
532
533 /* lookup port vid from local table, the switch passes an invalid vlan id */
534 vlan = priv->vlan_id[priv->pvid[port]];
535
536 buf[14 + 2] &= 0xf0;
537 buf[14 + 2] |= vlan >> 8;
538 buf[15 + 2] = vlan & 0xff;
539 }
540
541 int
542 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
543 {
544 int timeout = 20;
545 u32 t = 0;
546
547 while (1) {
548 t = ar8xxx_read(priv, reg);
549 if ((t & mask) == val)
550 return 0;
551
552 if (timeout-- <= 0)
553 break;
554
555 udelay(10);
556 }
557
558 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
559 (unsigned int) reg, t, mask, val);
560 return -ETIMEDOUT;
561 }
562
563 static void
564 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
565 {
566 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
567 return;
568 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
569 val &= AR8216_VTUDATA_MEMBER;
570 val |= AR8216_VTUDATA_VALID;
571 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
572 }
573 op |= AR8216_VTU_ACTIVE;
574 ar8xxx_write(priv, AR8216_REG_VTU, op);
575 }
576
577 static void
578 ar8216_vtu_flush(struct ar8xxx_priv *priv)
579 {
580 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
581 }
582
583 static void
584 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
585 {
586 u32 op;
587
588 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
589 ar8216_vtu_op(priv, op, port_mask);
590 }
591
592 static int
593 ar8216_atu_flush(struct ar8xxx_priv *priv)
594 {
595 int ret;
596
597 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
598 if (!ret)
599 ar8xxx_write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
600
601 return ret;
602 }
603
604 static u32
605 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
606 {
607 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
608 }
609
610 static void
611 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
612 {
613 u32 header;
614 u32 egress, ingress;
615 u32 pvid;
616
617 if (priv->vlan) {
618 pvid = priv->vlan_id[priv->pvid[port]];
619 if (priv->vlan_tagged & (1 << port))
620 egress = AR8216_OUT_ADD_VLAN;
621 else
622 egress = AR8216_OUT_STRIP_VLAN;
623 ingress = AR8216_IN_SECURE;
624 } else {
625 pvid = port;
626 egress = AR8216_OUT_KEEP;
627 ingress = AR8216_IN_PORT_ONLY;
628 }
629
630 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
631 header = AR8216_PORT_CTRL_HEADER;
632 else
633 header = 0;
634
635 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
636 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
637 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
638 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
639 AR8216_PORT_CTRL_LEARN | header |
640 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
641 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
642
643 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
644 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
645 AR8216_PORT_VLAN_DEFAULT_ID,
646 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
647 (ingress << AR8216_PORT_VLAN_MODE_S) |
648 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
649 }
650
651 static int
652 ar8216_hw_init(struct ar8xxx_priv *priv)
653 {
654 if (priv->initialized)
655 return 0;
656
657 ar8xxx_phy_init(priv);
658
659 priv->initialized = true;
660 return 0;
661 }
662
663 static void
664 ar8216_init_globals(struct ar8xxx_priv *priv)
665 {
666 /* standard atheros magic */
667 ar8xxx_write(priv, 0x38, 0xc000050e);
668
669 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
670 AR8216_GCTRL_MTU, 1518 + 8 + 2);
671 }
672
673 static void
674 ar8216_init_port(struct ar8xxx_priv *priv, int port)
675 {
676 /* Enable port learning and tx */
677 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
678 AR8216_PORT_CTRL_LEARN |
679 (4 << AR8216_PORT_CTRL_STATE_S));
680
681 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
682
683 if (port == AR8216_PORT_CPU) {
684 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
685 AR8216_PORT_STATUS_LINK_UP |
686 (ar8xxx_has_gige(priv) ?
687 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
688 AR8216_PORT_STATUS_TXMAC |
689 AR8216_PORT_STATUS_RXMAC |
690 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
691 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
692 AR8216_PORT_STATUS_DUPLEX);
693 } else {
694 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
695 AR8216_PORT_STATUS_LINK_AUTO);
696 }
697 }
698
699 static void
700 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
701 {
702 u32 egress, ingress;
703 u32 pvid;
704
705 if (priv->vlan) {
706 pvid = priv->vlan_id[priv->pvid[port]];
707 if (priv->vlan_tagged & (1 << port))
708 egress = AR8216_OUT_ADD_VLAN;
709 else
710 egress = AR8216_OUT_STRIP_VLAN;
711 ingress = AR8216_IN_SECURE;
712 } else {
713 pvid = port;
714 egress = AR8216_OUT_KEEP;
715 ingress = AR8216_IN_PORT_ONLY;
716 }
717
718 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
719 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
720 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
721 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
722 AR8216_PORT_CTRL_LEARN |
723 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
724 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
725
726 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
727 AR8236_PORT_VLAN_DEFAULT_ID,
728 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
729
730 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
731 AR8236_PORT_VLAN2_VLAN_MODE |
732 AR8236_PORT_VLAN2_MEMBER,
733 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
734 (members << AR8236_PORT_VLAN2_MEMBER_S));
735 }
736
737 static void
738 ar8236_init_globals(struct ar8xxx_priv *priv)
739 {
740 /* enable jumbo frames */
741 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
742 AR8316_GCTRL_MTU, 9018 + 8 + 2);
743
744 /* enable cpu port to receive arp frames */
745 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
746 AR8236_ATU_CTRL_RES);
747
748 /* enable cpu port to receive multicast and broadcast frames */
749 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
750 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
751
752 /* Enable MIB counters */
753 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
754 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
755 AR8236_MIB_EN);
756 }
757
758 static int
759 ar8316_hw_init(struct ar8xxx_priv *priv)
760 {
761 u32 val, newval;
762
763 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
764
765 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
766 if (priv->port4_phy) {
767 /* value taken from Ubiquiti RouterStation Pro */
768 newval = 0x81461bea;
769 pr_info("ar8316: Using port 4 as PHY\n");
770 } else {
771 newval = 0x01261be2;
772 pr_info("ar8316: Using port 4 as switch port\n");
773 }
774 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
775 /* value taken from AVM Fritz!Box 7390 sources */
776 newval = 0x010e5b71;
777 } else {
778 /* no known value for phy interface */
779 pr_err("ar8316: unsupported mii mode: %d.\n",
780 priv->phy->interface);
781 return -EINVAL;
782 }
783
784 if (val == newval)
785 goto out;
786
787 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
788
789 if (priv->port4_phy &&
790 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
791 /* work around for phy4 rgmii mode */
792 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
793 /* rx delay */
794 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
795 /* tx delay */
796 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
797 msleep(1000);
798 }
799
800 ar8xxx_phy_init(priv);
801
802 out:
803 priv->initialized = true;
804 return 0;
805 }
806
807 static void
808 ar8316_init_globals(struct ar8xxx_priv *priv)
809 {
810 /* standard atheros magic */
811 ar8xxx_write(priv, 0x38, 0xc000050e);
812
813 /* enable cpu port to receive multicast and broadcast frames */
814 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
815
816 /* enable jumbo frames */
817 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
818 AR8316_GCTRL_MTU, 9018 + 8 + 2);
819
820 /* Enable MIB counters */
821 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
822 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
823 AR8236_MIB_EN);
824 }
825
826 int
827 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
828 struct switch_val *val)
829 {
830 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
831 priv->vlan = !!val->value.i;
832 return 0;
833 }
834
835 int
836 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
837 struct switch_val *val)
838 {
839 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
840 val->value.i = priv->vlan;
841 return 0;
842 }
843
844
845 int
846 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
847 {
848 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
849
850 /* make sure no invalid PVIDs get set */
851
852 if (vlan >= dev->vlans)
853 return -EINVAL;
854
855 priv->pvid[port] = vlan;
856 return 0;
857 }
858
859 int
860 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
861 {
862 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
863 *vlan = priv->pvid[port];
864 return 0;
865 }
866
867 static int
868 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
869 struct switch_val *val)
870 {
871 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
872 priv->vlan_id[val->port_vlan] = val->value.i;
873 return 0;
874 }
875
876 static int
877 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
878 struct switch_val *val)
879 {
880 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
881 val->value.i = priv->vlan_id[val->port_vlan];
882 return 0;
883 }
884
885 int
886 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
887 struct switch_port_link *link)
888 {
889 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
890
891 ar8216_read_port_link(priv, port, link);
892 return 0;
893 }
894
895 static int
896 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
897 {
898 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
899 u8 ports = priv->vlan_table[val->port_vlan];
900 int i;
901
902 val->len = 0;
903 for (i = 0; i < dev->ports; i++) {
904 struct switch_port *p;
905
906 if (!(ports & (1 << i)))
907 continue;
908
909 p = &val->value.ports[val->len++];
910 p->id = i;
911 if (priv->vlan_tagged & (1 << i))
912 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
913 else
914 p->flags = 0;
915 }
916 return 0;
917 }
918
919 static int
920 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
921 {
922 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
923 u8 *vt = &priv->vlan_table[val->port_vlan];
924 int i, j;
925
926 *vt = 0;
927 for (i = 0; i < val->len; i++) {
928 struct switch_port *p = &val->value.ports[i];
929
930 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
931 priv->vlan_tagged |= (1 << p->id);
932 } else {
933 priv->vlan_tagged &= ~(1 << p->id);
934 priv->pvid[p->id] = val->port_vlan;
935
936 /* make sure that an untagged port does not
937 * appear in other vlans */
938 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
939 if (j == val->port_vlan)
940 continue;
941 priv->vlan_table[j] &= ~(1 << p->id);
942 }
943 }
944
945 *vt |= 1 << p->id;
946 }
947 return 0;
948 }
949
950 static void
951 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
952 {
953 int port;
954
955 /* reset all mirror registers */
956 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
957 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
958 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
959 for (port = 0; port < AR8216_NUM_PORTS; port++) {
960 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
961 AR8216_PORT_CTRL_MIRROR_RX,
962 0);
963
964 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
965 AR8216_PORT_CTRL_MIRROR_TX,
966 0);
967 }
968
969 /* now enable mirroring if necessary */
970 if (priv->source_port >= AR8216_NUM_PORTS ||
971 priv->monitor_port >= AR8216_NUM_PORTS ||
972 priv->source_port == priv->monitor_port) {
973 return;
974 }
975
976 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
977 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
978 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
979
980 if (priv->mirror_rx)
981 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
982 AR8216_PORT_CTRL_MIRROR_RX);
983
984 if (priv->mirror_tx)
985 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
986 AR8216_PORT_CTRL_MIRROR_TX);
987 }
988
989 int
990 ar8xxx_sw_hw_apply(struct switch_dev *dev)
991 {
992 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
993 u8 portmask[AR8X16_MAX_PORTS];
994 int i, j;
995
996 mutex_lock(&priv->reg_mutex);
997 /* flush all vlan translation unit entries */
998 priv->chip->vtu_flush(priv);
999
1000 memset(portmask, 0, sizeof(portmask));
1001 if (!priv->init) {
1002 /* calculate the port destination masks and load vlans
1003 * into the vlan translation unit */
1004 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1005 u8 vp = priv->vlan_table[j];
1006
1007 if (!vp)
1008 continue;
1009
1010 for (i = 0; i < dev->ports; i++) {
1011 u8 mask = (1 << i);
1012 if (vp & mask)
1013 portmask[i] |= vp & ~mask;
1014 }
1015
1016 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1017 priv->vlan_table[j]);
1018 }
1019 } else {
1020 /* vlan disabled:
1021 * isolate all ports, but connect them to the cpu port */
1022 for (i = 0; i < dev->ports; i++) {
1023 if (i == AR8216_PORT_CPU)
1024 continue;
1025
1026 portmask[i] = 1 << AR8216_PORT_CPU;
1027 portmask[AR8216_PORT_CPU] |= (1 << i);
1028 }
1029 }
1030
1031 /* update the port destination mask registers and tag settings */
1032 for (i = 0; i < dev->ports; i++) {
1033 priv->chip->setup_port(priv, i, portmask[i]);
1034 }
1035
1036 priv->chip->set_mirror_regs(priv);
1037
1038 mutex_unlock(&priv->reg_mutex);
1039 return 0;
1040 }
1041
1042 int
1043 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1044 {
1045 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1046 int i;
1047
1048 mutex_lock(&priv->reg_mutex);
1049 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1050 offsetof(struct ar8xxx_priv, vlan));
1051
1052 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1053 priv->vlan_id[i] = i;
1054
1055 /* Configure all ports */
1056 for (i = 0; i < dev->ports; i++)
1057 priv->chip->init_port(priv, i);
1058
1059 priv->mirror_rx = false;
1060 priv->mirror_tx = false;
1061 priv->source_port = 0;
1062 priv->monitor_port = 0;
1063
1064 priv->chip->init_globals(priv);
1065
1066 mutex_unlock(&priv->reg_mutex);
1067
1068 return ar8xxx_sw_hw_apply(dev);
1069 }
1070
1071 int
1072 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1073 const struct switch_attr *attr,
1074 struct switch_val *val)
1075 {
1076 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1077 unsigned int len;
1078 int ret;
1079
1080 if (!ar8xxx_has_mib_counters(priv))
1081 return -EOPNOTSUPP;
1082
1083 mutex_lock(&priv->mib_lock);
1084
1085 len = priv->dev.ports * priv->chip->num_mibs *
1086 sizeof(*priv->mib_stats);
1087 memset(priv->mib_stats, '\0', len);
1088 ret = ar8xxx_mib_flush(priv);
1089 if (ret)
1090 goto unlock;
1091
1092 ret = 0;
1093
1094 unlock:
1095 mutex_unlock(&priv->mib_lock);
1096 return ret;
1097 }
1098
1099 int
1100 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1101 const struct switch_attr *attr,
1102 struct switch_val *val)
1103 {
1104 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1105
1106 mutex_lock(&priv->reg_mutex);
1107 priv->mirror_rx = !!val->value.i;
1108 priv->chip->set_mirror_regs(priv);
1109 mutex_unlock(&priv->reg_mutex);
1110
1111 return 0;
1112 }
1113
1114 int
1115 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1116 const struct switch_attr *attr,
1117 struct switch_val *val)
1118 {
1119 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1120 val->value.i = priv->mirror_rx;
1121 return 0;
1122 }
1123
1124 int
1125 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1126 const struct switch_attr *attr,
1127 struct switch_val *val)
1128 {
1129 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1130
1131 mutex_lock(&priv->reg_mutex);
1132 priv->mirror_tx = !!val->value.i;
1133 priv->chip->set_mirror_regs(priv);
1134 mutex_unlock(&priv->reg_mutex);
1135
1136 return 0;
1137 }
1138
1139 int
1140 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1141 const struct switch_attr *attr,
1142 struct switch_val *val)
1143 {
1144 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1145 val->value.i = priv->mirror_tx;
1146 return 0;
1147 }
1148
1149 int
1150 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1151 const struct switch_attr *attr,
1152 struct switch_val *val)
1153 {
1154 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1155
1156 mutex_lock(&priv->reg_mutex);
1157 priv->monitor_port = val->value.i;
1158 priv->chip->set_mirror_regs(priv);
1159 mutex_unlock(&priv->reg_mutex);
1160
1161 return 0;
1162 }
1163
1164 int
1165 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1166 const struct switch_attr *attr,
1167 struct switch_val *val)
1168 {
1169 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1170 val->value.i = priv->monitor_port;
1171 return 0;
1172 }
1173
1174 int
1175 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1176 const struct switch_attr *attr,
1177 struct switch_val *val)
1178 {
1179 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1180
1181 mutex_lock(&priv->reg_mutex);
1182 priv->source_port = val->value.i;
1183 priv->chip->set_mirror_regs(priv);
1184 mutex_unlock(&priv->reg_mutex);
1185
1186 return 0;
1187 }
1188
1189 int
1190 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1191 const struct switch_attr *attr,
1192 struct switch_val *val)
1193 {
1194 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1195 val->value.i = priv->source_port;
1196 return 0;
1197 }
1198
1199 static int
1200 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1201 const struct switch_attr *attr,
1202 struct switch_val *val)
1203 {
1204 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1205 int port;
1206 int ret;
1207
1208 if (!ar8xxx_has_mib_counters(priv))
1209 return -EOPNOTSUPP;
1210
1211 port = val->port_vlan;
1212 if (port >= dev->ports)
1213 return -EINVAL;
1214
1215 mutex_lock(&priv->mib_lock);
1216 ret = ar8xxx_mib_capture(priv);
1217 if (ret)
1218 goto unlock;
1219
1220 ar8xxx_mib_fetch_port_stat(priv, port, true);
1221
1222 ret = 0;
1223
1224 unlock:
1225 mutex_unlock(&priv->mib_lock);
1226 return ret;
1227 }
1228
1229 static int
1230 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1231 const struct switch_attr *attr,
1232 struct switch_val *val)
1233 {
1234 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1235 const struct ar8xxx_chip *chip = priv->chip;
1236 u64 *mib_stats;
1237 int port;
1238 int ret;
1239 char *buf = priv->buf;
1240 int i, len = 0;
1241
1242 if (!ar8xxx_has_mib_counters(priv))
1243 return -EOPNOTSUPP;
1244
1245 port = val->port_vlan;
1246 if (port >= dev->ports)
1247 return -EINVAL;
1248
1249 mutex_lock(&priv->mib_lock);
1250 ret = ar8xxx_mib_capture(priv);
1251 if (ret)
1252 goto unlock;
1253
1254 ar8xxx_mib_fetch_port_stat(priv, port, false);
1255
1256 len += snprintf(buf + len, sizeof(priv->buf) - len,
1257 "Port %d MIB counters\n",
1258 port);
1259
1260 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1261 for (i = 0; i < chip->num_mibs; i++)
1262 len += snprintf(buf + len, sizeof(priv->buf) - len,
1263 "%-12s: %llu\n",
1264 chip->mib_decs[i].name,
1265 mib_stats[i]);
1266
1267 val->value.s = buf;
1268 val->len = len;
1269
1270 ret = 0;
1271
1272 unlock:
1273 mutex_unlock(&priv->mib_lock);
1274 return ret;
1275 }
1276
1277 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1278 {
1279 .type = SWITCH_TYPE_INT,
1280 .name = "enable_vlan",
1281 .description = "Enable VLAN mode",
1282 .set = ar8xxx_sw_set_vlan,
1283 .get = ar8xxx_sw_get_vlan,
1284 .max = 1
1285 },
1286 {
1287 .type = SWITCH_TYPE_NOVAL,
1288 .name = "reset_mibs",
1289 .description = "Reset all MIB counters",
1290 .set = ar8xxx_sw_set_reset_mibs,
1291 },
1292 {
1293 .type = SWITCH_TYPE_INT,
1294 .name = "enable_mirror_rx",
1295 .description = "Enable mirroring of RX packets",
1296 .set = ar8xxx_sw_set_mirror_rx_enable,
1297 .get = ar8xxx_sw_get_mirror_rx_enable,
1298 .max = 1
1299 },
1300 {
1301 .type = SWITCH_TYPE_INT,
1302 .name = "enable_mirror_tx",
1303 .description = "Enable mirroring of TX packets",
1304 .set = ar8xxx_sw_set_mirror_tx_enable,
1305 .get = ar8xxx_sw_get_mirror_tx_enable,
1306 .max = 1
1307 },
1308 {
1309 .type = SWITCH_TYPE_INT,
1310 .name = "mirror_monitor_port",
1311 .description = "Mirror monitor port",
1312 .set = ar8xxx_sw_set_mirror_monitor_port,
1313 .get = ar8xxx_sw_get_mirror_monitor_port,
1314 .max = AR8216_NUM_PORTS - 1
1315 },
1316 {
1317 .type = SWITCH_TYPE_INT,
1318 .name = "mirror_source_port",
1319 .description = "Mirror source port",
1320 .set = ar8xxx_sw_set_mirror_source_port,
1321 .get = ar8xxx_sw_get_mirror_source_port,
1322 .max = AR8216_NUM_PORTS - 1
1323 },
1324 };
1325
1326 const struct switch_attr ar8xxx_sw_attr_port[2] = {
1327 {
1328 .type = SWITCH_TYPE_NOVAL,
1329 .name = "reset_mib",
1330 .description = "Reset single port MIB counters",
1331 .set = ar8xxx_sw_set_port_reset_mib,
1332 },
1333 {
1334 .type = SWITCH_TYPE_STRING,
1335 .name = "mib",
1336 .description = "Get port's MIB counters",
1337 .set = NULL,
1338 .get = ar8xxx_sw_get_port_mib,
1339 },
1340 };
1341
1342 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1343 {
1344 .type = SWITCH_TYPE_INT,
1345 .name = "vid",
1346 .description = "VLAN ID (0-4094)",
1347 .set = ar8xxx_sw_set_vid,
1348 .get = ar8xxx_sw_get_vid,
1349 .max = 4094,
1350 },
1351 };
1352
1353 static const struct switch_dev_ops ar8xxx_sw_ops = {
1354 .attr_global = {
1355 .attr = ar8xxx_sw_attr_globals,
1356 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1357 },
1358 .attr_port = {
1359 .attr = ar8xxx_sw_attr_port,
1360 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1361 },
1362 .attr_vlan = {
1363 .attr = ar8xxx_sw_attr_vlan,
1364 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1365 },
1366 .get_port_pvid = ar8xxx_sw_get_pvid,
1367 .set_port_pvid = ar8xxx_sw_set_pvid,
1368 .get_vlan_ports = ar8xxx_sw_get_ports,
1369 .set_vlan_ports = ar8xxx_sw_set_ports,
1370 .apply_config = ar8xxx_sw_hw_apply,
1371 .reset_switch = ar8xxx_sw_reset_switch,
1372 .get_port_link = ar8xxx_sw_get_port_link,
1373 };
1374
1375 static const struct ar8xxx_chip ar8216_chip = {
1376 .caps = AR8XXX_CAP_MIB_COUNTERS,
1377
1378 .reg_port_stats_start = 0x19000,
1379 .reg_port_stats_length = 0xa0,
1380
1381 .name = "Atheros AR8216",
1382 .ports = AR8216_NUM_PORTS,
1383 .vlans = AR8216_NUM_VLANS,
1384 .swops = &ar8xxx_sw_ops,
1385
1386 .hw_init = ar8216_hw_init,
1387 .init_globals = ar8216_init_globals,
1388 .init_port = ar8216_init_port,
1389 .setup_port = ar8216_setup_port,
1390 .read_port_status = ar8216_read_port_status,
1391 .atu_flush = ar8216_atu_flush,
1392 .vtu_flush = ar8216_vtu_flush,
1393 .vtu_load_vlan = ar8216_vtu_load_vlan,
1394 .set_mirror_regs = ar8216_set_mirror_regs,
1395
1396 .num_mibs = ARRAY_SIZE(ar8216_mibs),
1397 .mib_decs = ar8216_mibs,
1398 .mib_func = AR8216_REG_MIB_FUNC
1399 };
1400
1401 static const struct ar8xxx_chip ar8236_chip = {
1402 .caps = AR8XXX_CAP_MIB_COUNTERS,
1403
1404 .reg_port_stats_start = 0x20000,
1405 .reg_port_stats_length = 0x100,
1406
1407 .name = "Atheros AR8236",
1408 .ports = AR8216_NUM_PORTS,
1409 .vlans = AR8216_NUM_VLANS,
1410 .swops = &ar8xxx_sw_ops,
1411
1412 .hw_init = ar8216_hw_init,
1413 .init_globals = ar8236_init_globals,
1414 .init_port = ar8216_init_port,
1415 .setup_port = ar8236_setup_port,
1416 .read_port_status = ar8216_read_port_status,
1417 .atu_flush = ar8216_atu_flush,
1418 .vtu_flush = ar8216_vtu_flush,
1419 .vtu_load_vlan = ar8216_vtu_load_vlan,
1420 .set_mirror_regs = ar8216_set_mirror_regs,
1421
1422 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1423 .mib_decs = ar8236_mibs,
1424 .mib_func = AR8216_REG_MIB_FUNC
1425 };
1426
1427 static const struct ar8xxx_chip ar8316_chip = {
1428 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1429
1430 .reg_port_stats_start = 0x20000,
1431 .reg_port_stats_length = 0x100,
1432
1433 .name = "Atheros AR8316",
1434 .ports = AR8216_NUM_PORTS,
1435 .vlans = AR8X16_MAX_VLANS,
1436 .swops = &ar8xxx_sw_ops,
1437
1438 .hw_init = ar8316_hw_init,
1439 .init_globals = ar8316_init_globals,
1440 .init_port = ar8216_init_port,
1441 .setup_port = ar8216_setup_port,
1442 .read_port_status = ar8216_read_port_status,
1443 .atu_flush = ar8216_atu_flush,
1444 .vtu_flush = ar8216_vtu_flush,
1445 .vtu_load_vlan = ar8216_vtu_load_vlan,
1446 .set_mirror_regs = ar8216_set_mirror_regs,
1447
1448 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1449 .mib_decs = ar8236_mibs,
1450 .mib_func = AR8216_REG_MIB_FUNC
1451 };
1452
1453 static int
1454 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1455 {
1456 u32 val;
1457 u16 id;
1458 int i;
1459
1460 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1461 if (val == ~0)
1462 return -ENODEV;
1463
1464 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1465 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1466 u16 t;
1467
1468 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1469 if (val == ~0)
1470 return -ENODEV;
1471
1472 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1473 if (t != id)
1474 return -ENODEV;
1475 }
1476
1477 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1478 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1479
1480 switch (priv->chip_ver) {
1481 case AR8XXX_VER_AR8216:
1482 priv->chip = &ar8216_chip;
1483 break;
1484 case AR8XXX_VER_AR8236:
1485 priv->chip = &ar8236_chip;
1486 break;
1487 case AR8XXX_VER_AR8316:
1488 priv->chip = &ar8316_chip;
1489 break;
1490 case AR8XXX_VER_AR8327:
1491 priv->chip = &ar8327_chip;
1492 break;
1493 case AR8XXX_VER_AR8337:
1494 priv->chip = &ar8337_chip;
1495 break;
1496 default:
1497 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1498 priv->chip_ver, priv->chip_rev);
1499
1500 return -ENODEV;
1501 }
1502
1503 return 0;
1504 }
1505
1506 static void
1507 ar8xxx_mib_work_func(struct work_struct *work)
1508 {
1509 struct ar8xxx_priv *priv;
1510 int err;
1511
1512 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1513
1514 mutex_lock(&priv->mib_lock);
1515
1516 err = ar8xxx_mib_capture(priv);
1517 if (err)
1518 goto next_port;
1519
1520 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1521
1522 next_port:
1523 priv->mib_next_port++;
1524 if (priv->mib_next_port >= priv->dev.ports)
1525 priv->mib_next_port = 0;
1526
1527 mutex_unlock(&priv->mib_lock);
1528 schedule_delayed_work(&priv->mib_work,
1529 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1530 }
1531
1532 static int
1533 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1534 {
1535 unsigned int len;
1536
1537 if (!ar8xxx_has_mib_counters(priv))
1538 return 0;
1539
1540 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1541
1542 len = priv->dev.ports * priv->chip->num_mibs *
1543 sizeof(*priv->mib_stats);
1544 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1545
1546 if (!priv->mib_stats)
1547 return -ENOMEM;
1548
1549 return 0;
1550 }
1551
1552 static void
1553 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1554 {
1555 if (!ar8xxx_has_mib_counters(priv))
1556 return;
1557
1558 schedule_delayed_work(&priv->mib_work,
1559 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1560 }
1561
1562 static void
1563 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1564 {
1565 if (!ar8xxx_has_mib_counters(priv))
1566 return;
1567
1568 cancel_delayed_work(&priv->mib_work);
1569 }
1570
1571 static struct ar8xxx_priv *
1572 ar8xxx_create(void)
1573 {
1574 struct ar8xxx_priv *priv;
1575
1576 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1577 if (priv == NULL)
1578 return NULL;
1579
1580 mutex_init(&priv->reg_mutex);
1581 mutex_init(&priv->mib_lock);
1582 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1583
1584 return priv;
1585 }
1586
1587 static void
1588 ar8xxx_free(struct ar8xxx_priv *priv)
1589 {
1590 if (priv->chip && priv->chip->cleanup)
1591 priv->chip->cleanup(priv);
1592
1593 kfree(priv->chip_data);
1594 kfree(priv->mib_stats);
1595 kfree(priv);
1596 }
1597
1598 static int
1599 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1600 {
1601 const struct ar8xxx_chip *chip;
1602 struct switch_dev *swdev;
1603 int ret;
1604
1605 ret = ar8xxx_id_chip(priv);
1606 if (ret)
1607 return ret;
1608
1609 chip = priv->chip;
1610
1611 swdev = &priv->dev;
1612 swdev->cpu_port = AR8216_PORT_CPU;
1613 swdev->name = chip->name;
1614 swdev->vlans = chip->vlans;
1615 swdev->ports = chip->ports;
1616 swdev->ops = chip->swops;
1617
1618 ret = ar8xxx_mib_init(priv);
1619 if (ret)
1620 return ret;
1621
1622 return 0;
1623 }
1624
1625 static int
1626 ar8xxx_start(struct ar8xxx_priv *priv)
1627 {
1628 int ret;
1629
1630 priv->init = true;
1631
1632 ret = priv->chip->hw_init(priv);
1633 if (ret)
1634 return ret;
1635
1636 ret = ar8xxx_sw_reset_switch(&priv->dev);
1637 if (ret)
1638 return ret;
1639
1640 priv->init = false;
1641
1642 ar8xxx_mib_start(priv);
1643
1644 return 0;
1645 }
1646
1647 static int
1648 ar8xxx_phy_config_init(struct phy_device *phydev)
1649 {
1650 struct ar8xxx_priv *priv = phydev->priv;
1651 struct net_device *dev = phydev->attached_dev;
1652 int ret;
1653
1654 if (WARN_ON(!priv))
1655 return -ENODEV;
1656
1657 if (priv->chip->config_at_probe)
1658 return ar8xxx_phy_check_aneg(phydev);
1659
1660 priv->phy = phydev;
1661
1662 if (phydev->addr != 0) {
1663 if (chip_is_ar8316(priv)) {
1664 /* switch device has been initialized, reinit */
1665 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1666 priv->initialized = false;
1667 priv->port4_phy = true;
1668 ar8316_hw_init(priv);
1669 return 0;
1670 }
1671
1672 return 0;
1673 }
1674
1675 ret = ar8xxx_start(priv);
1676 if (ret)
1677 return ret;
1678
1679 /* VID fixup only needed on ar8216 */
1680 if (chip_is_ar8216(priv)) {
1681 dev->phy_ptr = priv;
1682 dev->priv_flags |= IFF_NO_IP_ALIGN;
1683 dev->eth_mangle_rx = ar8216_mangle_rx;
1684 dev->eth_mangle_tx = ar8216_mangle_tx;
1685 }
1686
1687 return 0;
1688 }
1689
1690 static int
1691 ar8xxx_phy_read_status(struct phy_device *phydev)
1692 {
1693 struct ar8xxx_priv *priv = phydev->priv;
1694 struct switch_port_link link;
1695 int ret;
1696
1697 if (phydev->addr != 0)
1698 return genphy_read_status(phydev);
1699
1700 ar8216_read_port_link(priv, phydev->addr, &link);
1701 phydev->link = !!link.link;
1702 if (!phydev->link)
1703 return 0;
1704
1705 switch (link.speed) {
1706 case SWITCH_PORT_SPEED_10:
1707 phydev->speed = SPEED_10;
1708 break;
1709 case SWITCH_PORT_SPEED_100:
1710 phydev->speed = SPEED_100;
1711 break;
1712 case SWITCH_PORT_SPEED_1000:
1713 phydev->speed = SPEED_1000;
1714 break;
1715 default:
1716 phydev->speed = 0;
1717 }
1718 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1719
1720 /* flush the address translation unit */
1721 mutex_lock(&priv->reg_mutex);
1722 ret = priv->chip->atu_flush(priv);
1723 mutex_unlock(&priv->reg_mutex);
1724
1725 phydev->state = PHY_RUNNING;
1726 netif_carrier_on(phydev->attached_dev);
1727 phydev->adjust_link(phydev->attached_dev);
1728
1729 return ret;
1730 }
1731
1732 static int
1733 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1734 {
1735 if (phydev->addr == 0)
1736 return 0;
1737
1738 return genphy_config_aneg(phydev);
1739 }
1740
1741 static const u32 ar8xxx_phy_ids[] = {
1742 0x004dd033,
1743 0x004dd034, /* AR8327 */
1744 0x004dd036, /* AR8337 */
1745 0x004dd041,
1746 0x004dd042,
1747 0x004dd043, /* AR8236 */
1748 };
1749
1750 static bool
1751 ar8xxx_phy_match(u32 phy_id)
1752 {
1753 int i;
1754
1755 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
1756 if (phy_id == ar8xxx_phy_ids[i])
1757 return true;
1758
1759 return false;
1760 }
1761
1762 static bool
1763 ar8xxx_is_possible(struct mii_bus *bus)
1764 {
1765 unsigned i;
1766
1767 for (i = 0; i < 4; i++) {
1768 u32 phy_id;
1769
1770 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1771 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1772 if (!ar8xxx_phy_match(phy_id)) {
1773 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1774 dev_name(&bus->dev), i, phy_id);
1775 return false;
1776 }
1777 }
1778
1779 return true;
1780 }
1781
1782 static int
1783 ar8xxx_phy_probe(struct phy_device *phydev)
1784 {
1785 struct ar8xxx_priv *priv;
1786 struct switch_dev *swdev;
1787 int ret;
1788
1789 /* skip PHYs at unused adresses */
1790 if (phydev->addr != 0 && phydev->addr != 4)
1791 return -ENODEV;
1792
1793 if (!ar8xxx_is_possible(phydev->bus))
1794 return -ENODEV;
1795
1796 mutex_lock(&ar8xxx_dev_list_lock);
1797 list_for_each_entry(priv, &ar8xxx_dev_list, list)
1798 if (priv->mii_bus == phydev->bus)
1799 goto found;
1800
1801 priv = ar8xxx_create();
1802 if (priv == NULL) {
1803 ret = -ENOMEM;
1804 goto unlock;
1805 }
1806
1807 priv->mii_bus = phydev->bus;
1808
1809 ret = ar8xxx_probe_switch(priv);
1810 if (ret)
1811 goto free_priv;
1812
1813 swdev = &priv->dev;
1814 swdev->alias = dev_name(&priv->mii_bus->dev);
1815 ret = register_switch(swdev, NULL);
1816 if (ret)
1817 goto free_priv;
1818
1819 pr_info("%s: %s rev. %u switch registered on %s\n",
1820 swdev->devname, swdev->name, priv->chip_rev,
1821 dev_name(&priv->mii_bus->dev));
1822
1823 found:
1824 priv->use_count++;
1825
1826 if (phydev->addr == 0) {
1827 if (ar8xxx_has_gige(priv)) {
1828 phydev->supported = SUPPORTED_1000baseT_Full;
1829 phydev->advertising = ADVERTISED_1000baseT_Full;
1830 } else {
1831 phydev->supported = SUPPORTED_100baseT_Full;
1832 phydev->advertising = ADVERTISED_100baseT_Full;
1833 }
1834
1835 if (priv->chip->config_at_probe) {
1836 priv->phy = phydev;
1837
1838 ret = ar8xxx_start(priv);
1839 if (ret)
1840 goto err_unregister_switch;
1841 }
1842 } else {
1843 if (ar8xxx_has_gige(priv)) {
1844 phydev->supported |= SUPPORTED_1000baseT_Full;
1845 phydev->advertising |= ADVERTISED_1000baseT_Full;
1846 }
1847 }
1848
1849 phydev->priv = priv;
1850
1851 list_add(&priv->list, &ar8xxx_dev_list);
1852
1853 mutex_unlock(&ar8xxx_dev_list_lock);
1854
1855 return 0;
1856
1857 err_unregister_switch:
1858 if (--priv->use_count)
1859 goto unlock;
1860
1861 unregister_switch(&priv->dev);
1862
1863 free_priv:
1864 ar8xxx_free(priv);
1865 unlock:
1866 mutex_unlock(&ar8xxx_dev_list_lock);
1867 return ret;
1868 }
1869
1870 static void
1871 ar8xxx_phy_detach(struct phy_device *phydev)
1872 {
1873 struct net_device *dev = phydev->attached_dev;
1874
1875 if (!dev)
1876 return;
1877
1878 dev->phy_ptr = NULL;
1879 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1880 dev->eth_mangle_rx = NULL;
1881 dev->eth_mangle_tx = NULL;
1882 }
1883
1884 static void
1885 ar8xxx_phy_remove(struct phy_device *phydev)
1886 {
1887 struct ar8xxx_priv *priv = phydev->priv;
1888
1889 if (WARN_ON(!priv))
1890 return;
1891
1892 phydev->priv = NULL;
1893 if (--priv->use_count > 0)
1894 return;
1895
1896 mutex_lock(&ar8xxx_dev_list_lock);
1897 list_del(&priv->list);
1898 mutex_unlock(&ar8xxx_dev_list_lock);
1899
1900 unregister_switch(&priv->dev);
1901 ar8xxx_mib_stop(priv);
1902 ar8xxx_free(priv);
1903 }
1904
1905 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1906 static int
1907 ar8xxx_phy_soft_reset(struct phy_device *phydev)
1908 {
1909 /* we don't need an extra reset */
1910 return 0;
1911 }
1912 #endif
1913
1914 static struct phy_driver ar8xxx_phy_driver = {
1915 .phy_id = 0x004d0000,
1916 .name = "Atheros AR8216/AR8236/AR8316",
1917 .phy_id_mask = 0xffff0000,
1918 .features = PHY_BASIC_FEATURES,
1919 .probe = ar8xxx_phy_probe,
1920 .remove = ar8xxx_phy_remove,
1921 .detach = ar8xxx_phy_detach,
1922 .config_init = ar8xxx_phy_config_init,
1923 .config_aneg = ar8xxx_phy_config_aneg,
1924 .read_status = ar8xxx_phy_read_status,
1925 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
1926 .soft_reset = ar8xxx_phy_soft_reset,
1927 #endif
1928 .driver = { .owner = THIS_MODULE },
1929 };
1930
1931 int __init
1932 ar8xxx_init(void)
1933 {
1934 return phy_driver_register(&ar8xxx_phy_driver);
1935 }
1936
1937 void __exit
1938 ar8xxx_exit(void)
1939 {
1940 phy_driver_unregister(&ar8xxx_phy_driver);
1941 }
1942
1943 module_init(ar8xxx_init);
1944 module_exit(ar8xxx_exit);
1945 MODULE_LICENSE("GPL");
1946
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