2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
37 /* size of the vlan table */
38 #define AR8X16_MAX_VLANS 128
39 #define AR8X16_PROBE_RETRIES 10
40 #define AR8X16_MAX_PORTS 8
44 #define AR8XXX_CAP_GIGE BIT(0)
47 AR8XXX_VER_AR8216
= 0x01,
48 AR8XXX_VER_AR8236
= 0x03,
49 AR8XXX_VER_AR8316
= 0x10,
50 AR8XXX_VER_AR8327
= 0x12,
56 int (*hw_init
)(struct ar8216_priv
*priv
);
57 void (*init_globals
)(struct ar8216_priv
*priv
);
58 void (*init_port
)(struct ar8216_priv
*priv
, int port
);
59 void (*setup_port
)(struct ar8216_priv
*priv
, int port
, u32 egress
,
60 u32 ingress
, u32 members
, u32 pvid
);
61 u32 (*read_port_status
)(struct ar8216_priv
*priv
, int port
);
62 int (*atu_flush
)(struct ar8216_priv
*priv
);
63 void (*vtu_flush
)(struct ar8216_priv
*priv
);
64 void (*vtu_load_vlan
)(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
);
68 struct switch_dev dev
;
69 struct phy_device
*phy
;
70 u32 (*read
)(struct ar8216_priv
*priv
, int reg
);
71 void (*write
)(struct ar8216_priv
*priv
, int reg
, u32 val
);
72 const struct net_device_ops
*ndo_old
;
73 struct net_device_ops ndo
;
74 struct mutex reg_mutex
;
77 const struct ar8xxx_chip
*chip
;
85 /* all fields below are cleared on reset */
87 u16 vlan_id
[AR8X16_MAX_VLANS
];
88 u8 vlan_table
[AR8X16_MAX_VLANS
];
90 u16 pvid
[AR8X16_MAX_PORTS
];
93 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
95 static inline bool ar8xxx_has_gige(struct ar8216_priv
*priv
)
97 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
100 static inline bool chip_is_ar8216(struct ar8216_priv
*priv
)
102 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
105 static inline bool chip_is_ar8236(struct ar8216_priv
*priv
)
107 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
110 static inline bool chip_is_ar8316(struct ar8216_priv
*priv
)
112 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
115 static inline bool chip_is_ar8327(struct ar8216_priv
*priv
)
117 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
121 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
124 *r1
= regaddr
& 0x1e;
130 *page
= regaddr
& 0x1ff;
134 ar8216_mii_read(struct ar8216_priv
*priv
, int reg
)
136 struct phy_device
*phy
= priv
->phy
;
137 struct mii_bus
*bus
= phy
->bus
;
141 split_addr((u32
) reg
, &r1
, &r2
, &page
);
143 mutex_lock(&bus
->mdio_lock
);
145 bus
->write(bus
, 0x18, 0, page
);
146 usleep_range(1000, 2000); /* wait for the page switch to propagate */
147 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
148 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
150 mutex_unlock(&bus
->mdio_lock
);
152 return (hi
<< 16) | lo
;
156 ar8216_mii_write(struct ar8216_priv
*priv
, int reg
, u32 val
)
158 struct phy_device
*phy
= priv
->phy
;
159 struct mii_bus
*bus
= phy
->bus
;
163 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
165 hi
= (u16
) (val
>> 16);
167 mutex_lock(&bus
->mdio_lock
);
169 bus
->write(bus
, 0x18, 0, r3
);
170 usleep_range(1000, 2000); /* wait for the page switch to propagate */
171 if (priv
->mii_lo_first
) {
172 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
173 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
175 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
176 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
179 mutex_unlock(&bus
->mdio_lock
);
183 ar8216_phy_dbg_write(struct ar8216_priv
*priv
, int phy_addr
,
184 u16 dbg_addr
, u16 dbg_data
)
186 struct mii_bus
*bus
= priv
->phy
->bus
;
188 mutex_lock(&bus
->mdio_lock
);
189 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
190 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
191 mutex_unlock(&bus
->mdio_lock
);
195 ar8216_phy_mmd_write(struct ar8216_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
197 struct mii_bus
*bus
= priv
->phy
->bus
;
199 mutex_lock(&bus
->mdio_lock
);
200 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
201 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
202 mutex_unlock(&bus
->mdio_lock
);
206 ar8216_rmw(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
210 lockdep_assert_held(&priv
->reg_mutex
);
212 v
= priv
->read(priv
, reg
);
215 priv
->write(priv
, reg
, v
);
221 ar8216_read_port_link(struct ar8216_priv
*priv
, int port
,
222 struct switch_port_link
*link
)
227 memset(link
, '\0', sizeof(*link
));
229 status
= priv
->chip
->read_port_status(priv
, port
);
231 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
233 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
240 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
241 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
242 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
244 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
245 AR8216_PORT_STATUS_SPEED_S
;
248 case AR8216_PORT_SPEED_10M
:
249 link
->speed
= SWITCH_PORT_SPEED_10
;
251 case AR8216_PORT_SPEED_100M
:
252 link
->speed
= SWITCH_PORT_SPEED_100
;
254 case AR8216_PORT_SPEED_1000M
:
255 link
->speed
= SWITCH_PORT_SPEED_1000
;
258 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
263 static struct sk_buff
*
264 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
266 struct ar8216_priv
*priv
= dev
->phy_ptr
;
275 if (unlikely(skb_headroom(skb
) < 2)) {
276 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
280 buf
= skb_push(skb
, 2);
288 dev_kfree_skb_any(skb
);
293 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
295 struct ar8216_priv
*priv
;
303 /* don't strip the header if vlan mode is disabled */
307 /* strip header, get vlan id */
311 /* check for vlan header presence */
312 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
317 /* no need to fix up packets coming from a tagged source */
318 if (priv
->vlan_tagged
& (1 << port
))
321 /* lookup port vid from local table, the switch passes an invalid vlan id */
322 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
325 buf
[14 + 2] |= vlan
>> 8;
326 buf
[15 + 2] = vlan
& 0xff;
330 ar8216_wait_bit(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
336 t
= priv
->read(priv
, reg
);
337 if ((t
& mask
) == val
)
346 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
347 (unsigned int) reg
, t
, mask
, val
);
352 ar8216_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
354 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
356 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
357 val
&= AR8216_VTUDATA_MEMBER
;
358 val
|= AR8216_VTUDATA_VALID
;
359 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
361 op
|= AR8216_VTU_ACTIVE
;
362 priv
->write(priv
, AR8216_REG_VTU
, op
);
366 ar8216_vtu_flush(struct ar8216_priv
*priv
)
368 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
372 ar8216_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
376 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
377 ar8216_vtu_op(priv
, op
, port_mask
);
381 ar8216_atu_flush(struct ar8216_priv
*priv
)
385 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
387 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
393 ar8216_read_port_status(struct ar8216_priv
*priv
, int port
)
395 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
399 ar8216_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
400 u32 members
, u32 pvid
)
404 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
405 header
= AR8216_PORT_CTRL_HEADER
;
409 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
410 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
411 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
412 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
413 AR8216_PORT_CTRL_LEARN
| header
|
414 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
415 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
417 ar8216_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
418 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
419 AR8216_PORT_VLAN_DEFAULT_ID
,
420 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
421 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
422 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
426 ar8216_hw_init(struct ar8216_priv
*priv
)
432 ar8216_init_globals(struct ar8216_priv
*priv
)
434 /* standard atheros magic */
435 priv
->write(priv
, 0x38, 0xc000050e);
437 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
438 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
442 ar8216_init_port(struct ar8216_priv
*priv
, int port
)
444 /* Enable port learning and tx */
445 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
446 AR8216_PORT_CTRL_LEARN
|
447 (4 << AR8216_PORT_CTRL_STATE_S
));
449 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
451 if (port
== AR8216_PORT_CPU
) {
452 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
453 AR8216_PORT_STATUS_LINK_UP
|
454 (ar8xxx_has_gige(priv
) ?
455 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
456 AR8216_PORT_STATUS_TXMAC
|
457 AR8216_PORT_STATUS_RXMAC
|
458 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
459 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
460 AR8216_PORT_STATUS_DUPLEX
);
462 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
463 AR8216_PORT_STATUS_LINK_AUTO
);
467 static const struct ar8xxx_chip ar8216_chip
= {
468 .hw_init
= ar8216_hw_init
,
469 .init_globals
= ar8216_init_globals
,
470 .init_port
= ar8216_init_port
,
471 .setup_port
= ar8216_setup_port
,
472 .read_port_status
= ar8216_read_port_status
,
473 .atu_flush
= ar8216_atu_flush
,
474 .vtu_flush
= ar8216_vtu_flush
,
475 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
479 ar8236_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
480 u32 members
, u32 pvid
)
482 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
483 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
484 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
485 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
486 AR8216_PORT_CTRL_LEARN
|
487 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
488 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
490 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
491 AR8236_PORT_VLAN_DEFAULT_ID
,
492 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
494 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
495 AR8236_PORT_VLAN2_VLAN_MODE
|
496 AR8236_PORT_VLAN2_MEMBER
,
497 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
498 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
502 ar8236_hw_init(struct ar8216_priv
*priv
)
507 if (priv
->initialized
)
510 /* Initialize the PHYs */
511 bus
= priv
->phy
->bus
;
512 for (i
= 0; i
< 5; i
++) {
513 mdiobus_write(bus
, i
, MII_ADVERTISE
,
514 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
515 ADVERTISE_PAUSE_ASYM
);
516 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
520 priv
->initialized
= true;
525 ar8236_init_globals(struct ar8216_priv
*priv
)
527 /* enable jumbo frames */
528 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
529 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
532 static const struct ar8xxx_chip ar8236_chip
= {
533 .hw_init
= ar8236_hw_init
,
534 .init_globals
= ar8236_init_globals
,
535 .init_port
= ar8216_init_port
,
536 .setup_port
= ar8236_setup_port
,
537 .read_port_status
= ar8216_read_port_status
,
538 .atu_flush
= ar8216_atu_flush
,
539 .vtu_flush
= ar8216_vtu_flush
,
540 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
544 ar8316_hw_init(struct ar8216_priv
*priv
)
550 val
= priv
->read(priv
, 0x8);
552 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
553 if (priv
->port4_phy
) {
554 /* value taken from Ubiquiti RouterStation Pro */
556 printk(KERN_INFO
"ar8316: Using port 4 as PHY\n");
559 printk(KERN_INFO
"ar8316: Using port 4 as switch port\n");
561 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
562 /* value taken from AVM Fritz!Box 7390 sources */
565 /* no known value for phy interface */
566 printk(KERN_ERR
"ar8316: unsupported mii mode: %d.\n",
567 priv
->phy
->interface
);
574 priv
->write(priv
, 0x8, newval
);
576 /* Initialize the ports */
577 bus
= priv
->phy
->bus
;
578 for (i
= 0; i
< 5; i
++) {
579 if ((i
== 4) && priv
->port4_phy
&&
580 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
581 /* work around for phy4 rgmii mode */
582 ar8216_phy_dbg_write(priv
, i
, 0x12, 0x480c);
584 ar8216_phy_dbg_write(priv
, i
, 0x0, 0x824e);
586 ar8216_phy_dbg_write(priv
, i
, 0x5, 0x3d47);
590 /* initialize the port itself */
591 mdiobus_write(bus
, i
, MII_ADVERTISE
,
592 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
593 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
594 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
599 priv
->initialized
= true;
604 ar8316_init_globals(struct ar8216_priv
*priv
)
606 /* standard atheros magic */
607 priv
->write(priv
, 0x38, 0xc000050e);
609 /* enable cpu port to receive multicast and broadcast frames */
610 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
612 /* enable jumbo frames */
613 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
614 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
617 static const struct ar8xxx_chip ar8316_chip
= {
618 .caps
= AR8XXX_CAP_GIGE
,
619 .hw_init
= ar8316_hw_init
,
620 .init_globals
= ar8316_init_globals
,
621 .init_port
= ar8216_init_port
,
622 .setup_port
= ar8216_setup_port
,
623 .read_port_status
= ar8216_read_port_status
,
624 .atu_flush
= ar8216_atu_flush
,
625 .vtu_flush
= ar8216_vtu_flush
,
626 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
630 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
642 case AR8327_PAD_MAC2MAC_MII
:
643 t
= AR8327_PAD_MAC_MII_EN
;
645 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
647 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
650 case AR8327_PAD_MAC2MAC_GMII
:
651 t
= AR8327_PAD_MAC_GMII_EN
;
653 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
655 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
658 case AR8327_PAD_MAC_SGMII
:
659 t
= AR8327_PAD_SGMII_EN
;
662 case AR8327_PAD_MAC2PHY_MII
:
663 t
= AR8327_PAD_PHY_MII_EN
;
665 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
667 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
670 case AR8327_PAD_MAC2PHY_GMII
:
671 t
= AR8327_PAD_PHY_GMII_EN
;
672 if (cfg
->pipe_rxclk_sel
)
673 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
675 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
677 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
680 case AR8327_PAD_MAC_RGMII
:
681 t
= AR8327_PAD_RGMII_EN
;
682 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
683 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
684 if (cfg
->rxclk_delay_en
)
685 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
686 if (cfg
->txclk_delay_en
)
687 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
690 case AR8327_PAD_PHY_GMII
:
691 t
= AR8327_PAD_PHYX_GMII_EN
;
694 case AR8327_PAD_PHY_RGMII
:
695 t
= AR8327_PAD_PHYX_RGMII_EN
;
698 case AR8327_PAD_PHY_MII
:
699 t
= AR8327_PAD_PHYX_MII_EN
;
707 ar8327_phy_fixup(struct ar8216_priv
*priv
, int phy
)
709 switch (priv
->chip_rev
) {
711 /* For 100M waveform */
712 ar8216_phy_dbg_write(priv
, phy
, 0, 0x02ea);
713 /* Turn on Gigabit clock */
714 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
718 ar8216_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
719 ar8216_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
722 ar8216_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
723 ar8216_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
725 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
726 ar8216_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
727 ar8216_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
733 ar8327_hw_init(struct ar8216_priv
*priv
)
735 struct ar8327_platform_data
*pdata
;
739 pdata
= priv
->phy
->dev
.platform_data
;
743 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
744 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
745 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
746 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
747 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
748 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
750 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, 0x40000000);
752 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++)
753 ar8327_phy_fixup(priv
, i
);
759 ar8327_init_globals(struct ar8216_priv
*priv
)
763 /* enable CPU port and disable mirror port */
764 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
765 AR8327_FWD_CTRL0_MIRROR_PORT
;
766 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
768 /* forward multicast and broadcast frames to CPU */
769 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
770 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
771 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
772 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
775 ar8216_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
776 AR8327_MAX_FRAME_SIZE_MTU
, 1518 + 8 + 2);
780 ar8327_init_cpuport(struct ar8216_priv
*priv
)
782 struct ar8327_platform_data
*pdata
;
783 struct ar8327_port_cfg
*cfg
;
786 pdata
= priv
->phy
->dev
.platform_data
;
790 cfg
= &pdata
->cpuport_cfg
;
791 if (!cfg
->force_link
) {
792 priv
->write(priv
, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU
),
793 AR8216_PORT_STATUS_LINK_AUTO
);
797 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
798 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
799 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
800 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
801 switch (cfg
->speed
) {
802 case AR8327_PORT_SPEED_10
:
803 t
|= AR8216_PORT_SPEED_10M
;
805 case AR8327_PORT_SPEED_100
:
806 t
|= AR8216_PORT_SPEED_100M
;
808 case AR8327_PORT_SPEED_1000
:
809 t
|= AR8216_PORT_SPEED_1000M
;
813 priv
->write(priv
, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU
), t
);
817 ar8327_init_port(struct ar8216_priv
*priv
, int port
)
821 if (port
== AR8216_PORT_CPU
) {
822 ar8327_init_cpuport(priv
);
824 t
= AR8216_PORT_STATUS_LINK_AUTO
;
825 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
828 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
830 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), 0);
832 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
833 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
835 t
= AR8327_PORT_LOOKUP_LEARN
;
836 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
837 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
841 ar8327_read_port_status(struct ar8216_priv
*priv
, int port
)
843 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
847 ar8327_atu_flush(struct ar8216_priv
*priv
)
851 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
852 AR8327_ATU_FUNC_BUSY
, 0);
854 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
855 AR8327_ATU_FUNC_OP_FLUSH
);
861 ar8327_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
863 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
864 AR8327_VTU_FUNC1_BUSY
, 0))
867 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
868 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
870 op
|= AR8327_VTU_FUNC1_BUSY
;
871 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
875 ar8327_vtu_flush(struct ar8216_priv
*priv
)
877 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
881 ar8327_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
887 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
888 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
889 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
892 if ((port_mask
& BIT(i
)) == 0)
893 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
894 else if (priv
->vlan
== 0)
895 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
896 else if (priv
->vlan_tagged
& BIT(i
))
897 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
899 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
901 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
903 ar8327_vtu_op(priv
, op
, val
);
907 ar8327_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
908 u32 members
, u32 pvid
)
913 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
914 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
915 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
917 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
919 case AR8216_OUT_KEEP
:
920 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
922 case AR8216_OUT_STRIP_VLAN
:
923 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
925 case AR8216_OUT_ADD_VLAN
:
926 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
930 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
931 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
932 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
935 t
|= AR8327_PORT_LOOKUP_LEARN
;
936 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
937 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
938 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
941 static const struct ar8xxx_chip ar8327_chip
= {
942 .caps
= AR8XXX_CAP_GIGE
,
943 .hw_init
= ar8327_hw_init
,
944 .init_globals
= ar8327_init_globals
,
945 .init_port
= ar8327_init_port
,
946 .setup_port
= ar8327_setup_port
,
947 .read_port_status
= ar8327_read_port_status
,
948 .atu_flush
= ar8327_atu_flush
,
949 .vtu_flush
= ar8327_vtu_flush
,
950 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
954 ar8216_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
955 struct switch_val
*val
)
957 struct ar8216_priv
*priv
= to_ar8216(dev
);
958 priv
->vlan
= !!val
->value
.i
;
963 ar8216_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
964 struct switch_val
*val
)
966 struct ar8216_priv
*priv
= to_ar8216(dev
);
967 val
->value
.i
= priv
->vlan
;
973 ar8216_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
975 struct ar8216_priv
*priv
= to_ar8216(dev
);
977 /* make sure no invalid PVIDs get set */
979 if (vlan
>= dev
->vlans
)
982 priv
->pvid
[port
] = vlan
;
987 ar8216_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
989 struct ar8216_priv
*priv
= to_ar8216(dev
);
990 *vlan
= priv
->pvid
[port
];
995 ar8216_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
996 struct switch_val
*val
)
998 struct ar8216_priv
*priv
= to_ar8216(dev
);
999 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1004 ar8216_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1005 struct switch_val
*val
)
1007 struct ar8216_priv
*priv
= to_ar8216(dev
);
1008 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1013 ar8216_sw_get_port_link(struct switch_dev
*dev
, int port
,
1014 struct switch_port_link
*link
)
1016 struct ar8216_priv
*priv
= to_ar8216(dev
);
1018 ar8216_read_port_link(priv
, port
, link
);
1023 ar8216_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1025 struct ar8216_priv
*priv
= to_ar8216(dev
);
1026 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1030 for (i
= 0; i
< dev
->ports
; i
++) {
1031 struct switch_port
*p
;
1033 if (!(ports
& (1 << i
)))
1036 p
= &val
->value
.ports
[val
->len
++];
1038 if (priv
->vlan_tagged
& (1 << i
))
1039 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1047 ar8216_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1049 struct ar8216_priv
*priv
= to_ar8216(dev
);
1050 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1054 for (i
= 0; i
< val
->len
; i
++) {
1055 struct switch_port
*p
= &val
->value
.ports
[i
];
1057 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1058 priv
->vlan_tagged
|= (1 << p
->id
);
1060 priv
->vlan_tagged
&= ~(1 << p
->id
);
1061 priv
->pvid
[p
->id
] = val
->port_vlan
;
1063 /* make sure that an untagged port does not
1064 * appear in other vlans */
1065 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1066 if (j
== val
->port_vlan
)
1068 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1078 ar8216_sw_hw_apply(struct switch_dev
*dev
)
1080 struct ar8216_priv
*priv
= to_ar8216(dev
);
1081 u8 portmask
[AR8X16_MAX_PORTS
];
1084 mutex_lock(&priv
->reg_mutex
);
1085 /* flush all vlan translation unit entries */
1086 priv
->chip
->vtu_flush(priv
);
1088 memset(portmask
, 0, sizeof(portmask
));
1090 /* calculate the port destination masks and load vlans
1091 * into the vlan translation unit */
1092 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1093 u8 vp
= priv
->vlan_table
[j
];
1098 for (i
= 0; i
< dev
->ports
; i
++) {
1101 portmask
[i
] |= vp
& ~mask
;
1104 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1105 priv
->vlan_table
[j
]);
1109 * isolate all ports, but connect them to the cpu port */
1110 for (i
= 0; i
< dev
->ports
; i
++) {
1111 if (i
== AR8216_PORT_CPU
)
1114 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1115 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1119 /* update the port destination mask registers and tag settings */
1120 for (i
= 0; i
< dev
->ports
; i
++) {
1121 int egress
, ingress
;
1125 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1126 if (priv
->vlan_tagged
& (1 << i
))
1127 egress
= AR8216_OUT_ADD_VLAN
;
1129 egress
= AR8216_OUT_STRIP_VLAN
;
1130 ingress
= AR8216_IN_SECURE
;
1133 egress
= AR8216_OUT_KEEP
;
1134 ingress
= AR8216_IN_PORT_ONLY
;
1137 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1140 mutex_unlock(&priv
->reg_mutex
);
1145 ar8216_sw_reset_switch(struct switch_dev
*dev
)
1147 struct ar8216_priv
*priv
= to_ar8216(dev
);
1150 mutex_lock(&priv
->reg_mutex
);
1151 memset(&priv
->vlan
, 0, sizeof(struct ar8216_priv
) -
1152 offsetof(struct ar8216_priv
, vlan
));
1154 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1155 priv
->vlan_id
[i
] = i
;
1157 /* Configure all ports */
1158 for (i
= 0; i
< dev
->ports
; i
++)
1159 priv
->chip
->init_port(priv
, i
);
1161 priv
->chip
->init_globals(priv
);
1162 mutex_unlock(&priv
->reg_mutex
);
1164 return ar8216_sw_hw_apply(dev
);
1167 static struct switch_attr ar8216_globals
[] = {
1169 .type
= SWITCH_TYPE_INT
,
1170 .name
= "enable_vlan",
1171 .description
= "Enable VLAN mode",
1172 .set
= ar8216_sw_set_vlan
,
1173 .get
= ar8216_sw_get_vlan
,
1178 static struct switch_attr ar8216_port
[] = {
1181 static struct switch_attr ar8216_vlan
[] = {
1183 .type
= SWITCH_TYPE_INT
,
1185 .description
= "VLAN ID (0-4094)",
1186 .set
= ar8216_sw_set_vid
,
1187 .get
= ar8216_sw_get_vid
,
1192 static const struct switch_dev_ops ar8216_sw_ops
= {
1194 .attr
= ar8216_globals
,
1195 .n_attr
= ARRAY_SIZE(ar8216_globals
),
1198 .attr
= ar8216_port
,
1199 .n_attr
= ARRAY_SIZE(ar8216_port
),
1202 .attr
= ar8216_vlan
,
1203 .n_attr
= ARRAY_SIZE(ar8216_vlan
),
1205 .get_port_pvid
= ar8216_sw_get_pvid
,
1206 .set_port_pvid
= ar8216_sw_set_pvid
,
1207 .get_vlan_ports
= ar8216_sw_get_ports
,
1208 .set_vlan_ports
= ar8216_sw_set_ports
,
1209 .apply_config
= ar8216_sw_hw_apply
,
1210 .reset_switch
= ar8216_sw_reset_switch
,
1211 .get_port_link
= ar8216_sw_get_port_link
,
1215 ar8216_id_chip(struct ar8216_priv
*priv
)
1221 val
= ar8216_mii_read(priv
, AR8216_REG_CTRL
);
1225 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1226 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1229 val
= ar8216_mii_read(priv
, AR8216_REG_CTRL
);
1233 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1238 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1239 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1241 switch (priv
->chip_ver
) {
1242 case AR8XXX_VER_AR8216
:
1243 priv
->chip
= &ar8216_chip
;
1245 case AR8XXX_VER_AR8236
:
1246 priv
->chip
= &ar8236_chip
;
1248 case AR8XXX_VER_AR8316
:
1249 priv
->chip
= &ar8316_chip
;
1251 case AR8XXX_VER_AR8327
:
1252 priv
->mii_lo_first
= true;
1253 priv
->chip
= &ar8327_chip
;
1257 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1258 priv
->chip_ver
, priv
->chip_rev
,
1259 mdiobus_read(priv
->phy
->bus
, priv
->phy
->addr
, 2),
1260 mdiobus_read(priv
->phy
->bus
, priv
->phy
->addr
, 3));
1269 ar8216_config_init(struct phy_device
*pdev
)
1271 struct ar8216_priv
*priv
= pdev
->priv
;
1272 struct net_device
*dev
= pdev
->attached_dev
;
1273 struct switch_dev
*swdev
;
1277 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
1284 ret
= ar8216_id_chip(priv
);
1288 if (pdev
->addr
!= 0) {
1289 if (ar8xxx_has_gige(priv
)) {
1290 pdev
->supported
|= SUPPORTED_1000baseT_Full
;
1291 pdev
->advertising
|= ADVERTISED_1000baseT_Full
;
1294 if (chip_is_ar8316(priv
)) {
1295 /* check if we're attaching to the switch twice */
1296 pdev
= pdev
->bus
->phy_map
[0];
1302 /* switch device has not been initialized, reuse priv */
1304 priv
->port4_phy
= true;
1311 /* switch device has been initialized, reinit */
1313 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1314 priv
->initialized
= false;
1315 priv
->port4_phy
= true;
1316 ar8316_hw_init(priv
);
1324 if (ar8xxx_has_gige(priv
))
1325 pdev
->supported
= SUPPORTED_1000baseT_Full
;
1327 pdev
->supported
= SUPPORTED_100baseT_Full
;
1328 pdev
->advertising
= pdev
->supported
;
1330 mutex_init(&priv
->reg_mutex
);
1331 priv
->read
= ar8216_mii_read
;
1332 priv
->write
= ar8216_mii_write
;
1337 swdev
->cpu_port
= AR8216_PORT_CPU
;
1338 swdev
->ops
= &ar8216_sw_ops
;
1339 swdev
->ports
= AR8216_NUM_PORTS
;
1341 if (chip_is_ar8316(priv
)) {
1342 swdev
->name
= "Atheros AR8316";
1343 swdev
->vlans
= AR8X16_MAX_VLANS
;
1345 if (priv
->port4_phy
) {
1346 /* port 5 connected to the other mac, therefore unusable */
1347 swdev
->ports
= (AR8216_NUM_PORTS
- 1);
1349 } else if (chip_is_ar8236(priv
)) {
1350 swdev
->name
= "Atheros AR8236";
1351 swdev
->vlans
= AR8216_NUM_VLANS
;
1352 swdev
->ports
= AR8216_NUM_PORTS
;
1353 } else if (chip_is_ar8327(priv
)) {
1354 swdev
->name
= "Atheros AR8327";
1355 swdev
->vlans
= AR8X16_MAX_VLANS
;
1356 swdev
->ports
= AR8327_NUM_PORTS
;
1358 swdev
->name
= "Atheros AR8216";
1359 swdev
->vlans
= AR8216_NUM_VLANS
;
1362 ret
= register_switch(&priv
->dev
, pdev
->attached_dev
);
1366 printk(KERN_INFO
"%s: %s switch driver attached.\n",
1367 pdev
->attached_dev
->name
, swdev
->name
);
1371 ret
= priv
->chip
->hw_init(priv
);
1375 ret
= ar8216_sw_reset_switch(&priv
->dev
);
1379 dev
->phy_ptr
= priv
;
1381 /* VID fixup only needed on ar8216 */
1382 if (chip_is_ar8216(priv
) && pdev
->addr
== 0) {
1383 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1384 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1385 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1398 ar8216_read_status(struct phy_device
*phydev
)
1400 struct ar8216_priv
*priv
= phydev
->priv
;
1401 struct switch_port_link link
;
1404 if (phydev
->addr
!= 0)
1405 return genphy_read_status(phydev
);
1407 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1408 phydev
->link
= !!link
.link
;
1412 switch (link
.speed
) {
1413 case SWITCH_PORT_SPEED_10
:
1414 phydev
->speed
= SPEED_10
;
1416 case SWITCH_PORT_SPEED_100
:
1417 phydev
->speed
= SPEED_100
;
1419 case SWITCH_PORT_SPEED_1000
:
1420 phydev
->speed
= SPEED_1000
;
1425 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1427 /* flush the address translation unit */
1428 mutex_lock(&priv
->reg_mutex
);
1429 ret
= priv
->chip
->atu_flush(priv
);
1430 mutex_unlock(&priv
->reg_mutex
);
1432 phydev
->state
= PHY_RUNNING
;
1433 netif_carrier_on(phydev
->attached_dev
);
1434 phydev
->adjust_link(phydev
->attached_dev
);
1440 ar8216_config_aneg(struct phy_device
*phydev
)
1442 if (phydev
->addr
== 0)
1445 return genphy_config_aneg(phydev
);
1449 ar8216_probe(struct phy_device
*pdev
)
1451 struct ar8216_priv priv
;
1454 return ar8216_id_chip(&priv
);
1458 ar8216_remove(struct phy_device
*pdev
)
1460 struct ar8216_priv
*priv
= pdev
->priv
;
1461 struct net_device
*dev
= pdev
->attached_dev
;
1466 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
1467 dev
->eth_mangle_rx
= NULL
;
1468 dev
->eth_mangle_tx
= NULL
;
1470 if (pdev
->addr
== 0)
1471 unregister_switch(&priv
->dev
);
1475 static struct phy_driver ar8216_driver
= {
1476 .phy_id
= 0x004d0000,
1477 .name
= "Atheros AR8216/AR8236/AR8316",
1478 .phy_id_mask
= 0xffff0000,
1479 .features
= PHY_BASIC_FEATURES
,
1480 .probe
= ar8216_probe
,
1481 .remove
= ar8216_remove
,
1482 .config_init
= &ar8216_config_init
,
1483 .config_aneg
= &ar8216_config_aneg
,
1484 .read_status
= &ar8216_read_status
,
1485 .driver
= { .owner
= THIS_MODULE
},
1491 return phy_driver_register(&ar8216_driver
);
1497 phy_driver_unregister(&ar8216_driver
);
1500 module_init(ar8216_init
);
1501 module_exit(ar8216_exit
);
1502 MODULE_LICENSE("GPL");