2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
38 /* size of the vlan table */
39 #define AR8X16_MAX_VLANS 128
40 #define AR8X16_PROBE_RETRIES 10
41 #define AR8X16_MAX_PORTS 8
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
47 #define AR8XXX_CAP_GIGE BIT(0)
48 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
51 AR8XXX_VER_AR8216
= 0x01,
52 AR8XXX_VER_AR8236
= 0x03,
53 AR8XXX_VER_AR8316
= 0x10,
54 AR8XXX_VER_AR8327
= 0x12,
57 struct ar8xxx_mib_desc
{
66 int (*hw_init
)(struct ar8216_priv
*priv
);
67 void (*init_globals
)(struct ar8216_priv
*priv
);
68 void (*init_port
)(struct ar8216_priv
*priv
, int port
);
69 void (*setup_port
)(struct ar8216_priv
*priv
, int port
, u32 egress
,
70 u32 ingress
, u32 members
, u32 pvid
);
71 u32 (*read_port_status
)(struct ar8216_priv
*priv
, int port
);
72 int (*atu_flush
)(struct ar8216_priv
*priv
);
73 void (*vtu_flush
)(struct ar8216_priv
*priv
);
74 void (*vtu_load_vlan
)(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
);
76 const struct ar8xxx_mib_desc
*mib_decs
;
81 struct switch_dev dev
;
82 struct phy_device
*phy
;
83 u32 (*read
)(struct ar8216_priv
*priv
, int reg
);
84 void (*write
)(struct ar8216_priv
*priv
, int reg
, u32 val
);
85 const struct net_device_ops
*ndo_old
;
86 struct net_device_ops ndo
;
87 struct mutex reg_mutex
;
90 const struct ar8xxx_chip
*chip
;
98 struct mutex mib_lock
;
99 struct delayed_work mib_work
;
103 /* all fields below are cleared on reset */
105 u16 vlan_id
[AR8X16_MAX_VLANS
];
106 u8 vlan_table
[AR8X16_MAX_VLANS
];
108 u16 pvid
[AR8X16_MAX_PORTS
];
111 #define MIB_DESC(_s , _o, _n) \
118 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
119 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
120 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
121 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
122 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
123 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
124 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
125 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
126 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
127 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
128 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
129 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
130 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
131 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
132 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
133 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
134 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
135 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
136 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
137 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
138 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
139 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
140 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
141 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
142 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
143 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
144 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
145 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
146 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
147 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
148 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
149 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
150 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
151 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
152 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
153 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
154 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
155 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
156 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
157 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
160 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
162 static inline bool ar8xxx_has_gige(struct ar8216_priv
*priv
)
164 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
167 static inline bool ar8xxx_has_mib_counters(struct ar8216_priv
*priv
)
169 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
172 static inline bool chip_is_ar8216(struct ar8216_priv
*priv
)
174 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
177 static inline bool chip_is_ar8236(struct ar8216_priv
*priv
)
179 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
182 static inline bool chip_is_ar8316(struct ar8216_priv
*priv
)
184 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
187 static inline bool chip_is_ar8327(struct ar8216_priv
*priv
)
189 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
193 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
196 *r1
= regaddr
& 0x1e;
202 *page
= regaddr
& 0x1ff;
206 ar8216_mii_read(struct ar8216_priv
*priv
, int reg
)
208 struct phy_device
*phy
= priv
->phy
;
209 struct mii_bus
*bus
= phy
->bus
;
213 split_addr((u32
) reg
, &r1
, &r2
, &page
);
215 mutex_lock(&bus
->mdio_lock
);
217 bus
->write(bus
, 0x18, 0, page
);
218 usleep_range(1000, 2000); /* wait for the page switch to propagate */
219 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
220 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
222 mutex_unlock(&bus
->mdio_lock
);
224 return (hi
<< 16) | lo
;
228 ar8216_mii_write(struct ar8216_priv
*priv
, int reg
, u32 val
)
230 struct phy_device
*phy
= priv
->phy
;
231 struct mii_bus
*bus
= phy
->bus
;
235 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
237 hi
= (u16
) (val
>> 16);
239 mutex_lock(&bus
->mdio_lock
);
241 bus
->write(bus
, 0x18, 0, r3
);
242 usleep_range(1000, 2000); /* wait for the page switch to propagate */
243 if (priv
->mii_lo_first
) {
244 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
245 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
247 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
248 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
251 mutex_unlock(&bus
->mdio_lock
);
255 ar8216_phy_dbg_write(struct ar8216_priv
*priv
, int phy_addr
,
256 u16 dbg_addr
, u16 dbg_data
)
258 struct mii_bus
*bus
= priv
->phy
->bus
;
260 mutex_lock(&bus
->mdio_lock
);
261 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
262 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
263 mutex_unlock(&bus
->mdio_lock
);
267 ar8216_phy_mmd_write(struct ar8216_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
269 struct mii_bus
*bus
= priv
->phy
->bus
;
271 mutex_lock(&bus
->mdio_lock
);
272 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
273 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
274 mutex_unlock(&bus
->mdio_lock
);
278 ar8216_rmw(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
282 lockdep_assert_held(&priv
->reg_mutex
);
284 v
= priv
->read(priv
, reg
);
287 priv
->write(priv
, reg
, v
);
293 ar8216_reg_set(struct ar8216_priv
*priv
, int reg
, u32 val
)
297 lockdep_assert_held(&priv
->reg_mutex
);
299 v
= priv
->read(priv
, reg
);
301 priv
->write(priv
, reg
, v
);
305 ar8216_reg_wait(struct ar8216_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
310 for (i
= 0; i
< timeout
; i
++) {
313 t
= priv
->read(priv
, reg
);
314 if ((t
& mask
) == val
)
317 usleep_range(1000, 2000);
324 ar8216_mib_capture(struct ar8216_priv
*priv
)
329 lockdep_assert_held(&priv
->mib_lock
);
331 if (chip_is_ar8327(priv
))
332 mib_func
= AR8327_REG_MIB_FUNC
;
334 mib_func
= AR8216_REG_MIB_FUNC
;
336 /* Capture the hardware statistics for all ports */
337 ar8216_rmw(priv
, mib_func
, AR8216_MIB_FUNC
,
338 (AR8216_MIB_FUNC_CAPTURE
<< AR8216_MIB_FUNC_S
));
340 /* Wait for the capturing to complete. */
341 ret
= ar8216_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
352 ar8216_mib_flush(struct ar8216_priv
*priv
)
357 lockdep_assert_held(&priv
->mib_lock
);
359 if (chip_is_ar8327(priv
))
360 mib_func
= AR8327_REG_MIB_FUNC
;
362 mib_func
= AR8216_REG_MIB_FUNC
;
364 /* Flush hardware statistics for all ports */
365 ar8216_rmw(priv
, mib_func
, AR8216_MIB_FUNC
,
366 (AR8216_MIB_FUNC_FLUSH
<< AR8216_MIB_FUNC_S
));
368 /* Wait for the capturing to complete. */
369 ret
= ar8216_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
380 ar8216_mib_fetch_port_stat(struct ar8216_priv
*priv
, int port
, bool flush
)
386 lockdep_assert_held(&priv
->mib_lock
);
388 if (chip_is_ar8327(priv
))
389 base
= AR8327_REG_PORT_STATS_BASE(port
);
391 base
= AR8236_REG_PORT_STATS_BASE(port
);
393 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
394 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
395 const struct ar8xxx_mib_desc
*mib
;
398 mib
= &priv
->chip
->mib_decs
[i
];
399 t
= priv
->read(priv
, base
+ mib
->offset
);
400 if (mib
->size
== 2) {
403 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
415 ar8216_read_port_link(struct ar8216_priv
*priv
, int port
,
416 struct switch_port_link
*link
)
421 memset(link
, '\0', sizeof(*link
));
423 status
= priv
->chip
->read_port_status(priv
, port
);
425 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
427 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
434 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
435 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
436 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
438 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
439 AR8216_PORT_STATUS_SPEED_S
;
442 case AR8216_PORT_SPEED_10M
:
443 link
->speed
= SWITCH_PORT_SPEED_10
;
445 case AR8216_PORT_SPEED_100M
:
446 link
->speed
= SWITCH_PORT_SPEED_100
;
448 case AR8216_PORT_SPEED_1000M
:
449 link
->speed
= SWITCH_PORT_SPEED_1000
;
452 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
457 static struct sk_buff
*
458 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
460 struct ar8216_priv
*priv
= dev
->phy_ptr
;
469 if (unlikely(skb_headroom(skb
) < 2)) {
470 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
474 buf
= skb_push(skb
, 2);
482 dev_kfree_skb_any(skb
);
487 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
489 struct ar8216_priv
*priv
;
497 /* don't strip the header if vlan mode is disabled */
501 /* strip header, get vlan id */
505 /* check for vlan header presence */
506 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
511 /* no need to fix up packets coming from a tagged source */
512 if (priv
->vlan_tagged
& (1 << port
))
515 /* lookup port vid from local table, the switch passes an invalid vlan id */
516 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
519 buf
[14 + 2] |= vlan
>> 8;
520 buf
[15 + 2] = vlan
& 0xff;
524 ar8216_wait_bit(struct ar8216_priv
*priv
, int reg
, u32 mask
, u32 val
)
530 t
= priv
->read(priv
, reg
);
531 if ((t
& mask
) == val
)
540 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
541 (unsigned int) reg
, t
, mask
, val
);
546 ar8216_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
548 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
550 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
551 val
&= AR8216_VTUDATA_MEMBER
;
552 val
|= AR8216_VTUDATA_VALID
;
553 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
555 op
|= AR8216_VTU_ACTIVE
;
556 priv
->write(priv
, AR8216_REG_VTU
, op
);
560 ar8216_vtu_flush(struct ar8216_priv
*priv
)
562 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
566 ar8216_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
570 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
571 ar8216_vtu_op(priv
, op
, port_mask
);
575 ar8216_atu_flush(struct ar8216_priv
*priv
)
579 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
581 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
587 ar8216_read_port_status(struct ar8216_priv
*priv
, int port
)
589 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
593 ar8216_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
594 u32 members
, u32 pvid
)
598 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
599 header
= AR8216_PORT_CTRL_HEADER
;
603 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
604 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
605 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
606 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
607 AR8216_PORT_CTRL_LEARN
| header
|
608 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
609 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
611 ar8216_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
612 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
613 AR8216_PORT_VLAN_DEFAULT_ID
,
614 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
615 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
616 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
620 ar8216_hw_init(struct ar8216_priv
*priv
)
626 ar8216_init_globals(struct ar8216_priv
*priv
)
628 /* standard atheros magic */
629 priv
->write(priv
, 0x38, 0xc000050e);
631 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
632 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
636 ar8216_init_port(struct ar8216_priv
*priv
, int port
)
638 /* Enable port learning and tx */
639 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
640 AR8216_PORT_CTRL_LEARN
|
641 (4 << AR8216_PORT_CTRL_STATE_S
));
643 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
645 if (port
== AR8216_PORT_CPU
) {
646 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
647 AR8216_PORT_STATUS_LINK_UP
|
648 (ar8xxx_has_gige(priv
) ?
649 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
650 AR8216_PORT_STATUS_TXMAC
|
651 AR8216_PORT_STATUS_RXMAC
|
652 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
653 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
654 AR8216_PORT_STATUS_DUPLEX
);
656 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
657 AR8216_PORT_STATUS_LINK_AUTO
);
661 static const struct ar8xxx_chip ar8216_chip
= {
662 .hw_init
= ar8216_hw_init
,
663 .init_globals
= ar8216_init_globals
,
664 .init_port
= ar8216_init_port
,
665 .setup_port
= ar8216_setup_port
,
666 .read_port_status
= ar8216_read_port_status
,
667 .atu_flush
= ar8216_atu_flush
,
668 .vtu_flush
= ar8216_vtu_flush
,
669 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
673 ar8236_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
674 u32 members
, u32 pvid
)
676 ar8216_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
677 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
678 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
679 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
680 AR8216_PORT_CTRL_LEARN
|
681 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
682 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
684 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
685 AR8236_PORT_VLAN_DEFAULT_ID
,
686 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
688 ar8216_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
689 AR8236_PORT_VLAN2_VLAN_MODE
|
690 AR8236_PORT_VLAN2_MEMBER
,
691 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
692 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
696 ar8236_hw_init(struct ar8216_priv
*priv
)
701 if (priv
->initialized
)
704 /* Initialize the PHYs */
705 bus
= priv
->phy
->bus
;
706 for (i
= 0; i
< 5; i
++) {
707 mdiobus_write(bus
, i
, MII_ADVERTISE
,
708 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
709 ADVERTISE_PAUSE_ASYM
);
710 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
714 priv
->initialized
= true;
719 ar8236_init_globals(struct ar8216_priv
*priv
)
721 /* enable jumbo frames */
722 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
723 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
725 /* Enable MIB counters */
726 ar8216_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
727 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
731 static const struct ar8xxx_chip ar8236_chip
= {
732 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
733 .hw_init
= ar8236_hw_init
,
734 .init_globals
= ar8236_init_globals
,
735 .init_port
= ar8216_init_port
,
736 .setup_port
= ar8236_setup_port
,
737 .read_port_status
= ar8216_read_port_status
,
738 .atu_flush
= ar8216_atu_flush
,
739 .vtu_flush
= ar8216_vtu_flush
,
740 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
742 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
743 .mib_decs
= ar8236_mibs
,
747 ar8316_hw_init(struct ar8216_priv
*priv
)
753 val
= priv
->read(priv
, 0x8);
755 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
756 if (priv
->port4_phy
) {
757 /* value taken from Ubiquiti RouterStation Pro */
759 printk(KERN_INFO
"ar8316: Using port 4 as PHY\n");
762 printk(KERN_INFO
"ar8316: Using port 4 as switch port\n");
764 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
765 /* value taken from AVM Fritz!Box 7390 sources */
768 /* no known value for phy interface */
769 printk(KERN_ERR
"ar8316: unsupported mii mode: %d.\n",
770 priv
->phy
->interface
);
777 priv
->write(priv
, 0x8, newval
);
779 /* Initialize the ports */
780 bus
= priv
->phy
->bus
;
781 for (i
= 0; i
< 5; i
++) {
782 if ((i
== 4) && priv
->port4_phy
&&
783 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
784 /* work around for phy4 rgmii mode */
785 ar8216_phy_dbg_write(priv
, i
, 0x12, 0x480c);
787 ar8216_phy_dbg_write(priv
, i
, 0x0, 0x824e);
789 ar8216_phy_dbg_write(priv
, i
, 0x5, 0x3d47);
793 /* initialize the port itself */
794 mdiobus_write(bus
, i
, MII_ADVERTISE
,
795 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
796 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
797 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
802 priv
->initialized
= true;
807 ar8316_init_globals(struct ar8216_priv
*priv
)
809 /* standard atheros magic */
810 priv
->write(priv
, 0x38, 0xc000050e);
812 /* enable cpu port to receive multicast and broadcast frames */
813 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
815 /* enable jumbo frames */
816 ar8216_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
817 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
819 /* Enable MIB counters */
820 ar8216_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
821 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
825 static const struct ar8xxx_chip ar8316_chip
= {
826 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
827 .hw_init
= ar8316_hw_init
,
828 .init_globals
= ar8316_init_globals
,
829 .init_port
= ar8216_init_port
,
830 .setup_port
= ar8216_setup_port
,
831 .read_port_status
= ar8216_read_port_status
,
832 .atu_flush
= ar8216_atu_flush
,
833 .vtu_flush
= ar8216_vtu_flush
,
834 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
836 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
837 .mib_decs
= ar8236_mibs
,
841 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
853 case AR8327_PAD_MAC2MAC_MII
:
854 t
= AR8327_PAD_MAC_MII_EN
;
856 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
858 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
861 case AR8327_PAD_MAC2MAC_GMII
:
862 t
= AR8327_PAD_MAC_GMII_EN
;
864 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
866 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
869 case AR8327_PAD_MAC_SGMII
:
870 t
= AR8327_PAD_SGMII_EN
;
873 case AR8327_PAD_MAC2PHY_MII
:
874 t
= AR8327_PAD_PHY_MII_EN
;
876 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
878 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
881 case AR8327_PAD_MAC2PHY_GMII
:
882 t
= AR8327_PAD_PHY_GMII_EN
;
883 if (cfg
->pipe_rxclk_sel
)
884 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
886 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
888 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
891 case AR8327_PAD_MAC_RGMII
:
892 t
= AR8327_PAD_RGMII_EN
;
893 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
894 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
895 if (cfg
->rxclk_delay_en
)
896 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
897 if (cfg
->txclk_delay_en
)
898 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
901 case AR8327_PAD_PHY_GMII
:
902 t
= AR8327_PAD_PHYX_GMII_EN
;
905 case AR8327_PAD_PHY_RGMII
:
906 t
= AR8327_PAD_PHYX_RGMII_EN
;
909 case AR8327_PAD_PHY_MII
:
910 t
= AR8327_PAD_PHYX_MII_EN
;
918 ar8327_phy_fixup(struct ar8216_priv
*priv
, int phy
)
920 switch (priv
->chip_rev
) {
922 /* For 100M waveform */
923 ar8216_phy_dbg_write(priv
, phy
, 0, 0x02ea);
924 /* Turn on Gigabit clock */
925 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
929 ar8216_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
930 ar8216_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
933 ar8216_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
934 ar8216_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
936 ar8216_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
937 ar8216_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
938 ar8216_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
944 ar8327_hw_init(struct ar8216_priv
*priv
)
946 struct ar8327_platform_data
*pdata
;
947 struct ar8327_led_cfg
*led_cfg
;
953 pdata
= priv
->phy
->dev
.platform_data
;
957 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
958 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
959 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
960 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
961 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
962 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
964 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
967 led_cfg
= pdata
->led_cfg
;
969 if (led_cfg
->open_drain
)
970 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
972 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
974 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
975 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
976 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
977 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
980 if (new_pos
!= pos
) {
981 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
982 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
985 bus
= priv
->phy
->bus
;
986 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
987 ar8327_phy_fixup(priv
, i
);
989 /* start aneg on the PHY */
990 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
991 ADVERTISE_PAUSE_CAP
|
992 ADVERTISE_PAUSE_ASYM
);
993 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
994 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1003 ar8327_init_globals(struct ar8216_priv
*priv
)
1007 /* enable CPU port and disable mirror port */
1008 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1009 AR8327_FWD_CTRL0_MIRROR_PORT
;
1010 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1012 /* forward multicast and broadcast frames to CPU */
1013 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1014 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1015 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1016 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1019 ar8216_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1020 AR8327_MAX_FRAME_SIZE_MTU
, 1518 + 8 + 2);
1022 /* Enable MIB counters */
1023 ar8216_reg_set(priv
, AR8327_REG_MODULE_EN
,
1024 AR8327_MODULE_EN_MIB
);
1028 ar8327_init_cpuport(struct ar8216_priv
*priv
)
1030 struct ar8327_platform_data
*pdata
;
1031 struct ar8327_port_cfg
*cfg
;
1034 pdata
= priv
->phy
->dev
.platform_data
;
1038 cfg
= &pdata
->cpuport_cfg
;
1039 if (!cfg
->force_link
) {
1040 priv
->write(priv
, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU
),
1041 AR8216_PORT_STATUS_LINK_AUTO
);
1045 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1046 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1047 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1048 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1049 switch (cfg
->speed
) {
1050 case AR8327_PORT_SPEED_10
:
1051 t
|= AR8216_PORT_SPEED_10M
;
1053 case AR8327_PORT_SPEED_100
:
1054 t
|= AR8216_PORT_SPEED_100M
;
1056 case AR8327_PORT_SPEED_1000
:
1057 t
|= AR8216_PORT_SPEED_1000M
;
1061 priv
->write(priv
, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU
), t
);
1065 ar8327_init_port(struct ar8216_priv
*priv
, int port
)
1069 if (port
== AR8216_PORT_CPU
) {
1070 ar8327_init_cpuport(priv
);
1072 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1073 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1076 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1078 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), 0);
1080 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1081 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1083 t
= AR8327_PORT_LOOKUP_LEARN
;
1084 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1085 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1089 ar8327_read_port_status(struct ar8216_priv
*priv
, int port
)
1091 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1095 ar8327_atu_flush(struct ar8216_priv
*priv
)
1099 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1100 AR8327_ATU_FUNC_BUSY
, 0);
1102 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1103 AR8327_ATU_FUNC_OP_FLUSH
);
1109 ar8327_vtu_op(struct ar8216_priv
*priv
, u32 op
, u32 val
)
1111 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1112 AR8327_VTU_FUNC1_BUSY
, 0))
1115 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1116 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1118 op
|= AR8327_VTU_FUNC1_BUSY
;
1119 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1123 ar8327_vtu_flush(struct ar8216_priv
*priv
)
1125 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1129 ar8327_vtu_load_vlan(struct ar8216_priv
*priv
, u32 vid
, u32 port_mask
)
1135 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1136 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1137 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1140 if ((port_mask
& BIT(i
)) == 0)
1141 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1142 else if (priv
->vlan
== 0)
1143 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1144 else if (priv
->vlan_tagged
& BIT(i
))
1145 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1147 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1149 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1151 ar8327_vtu_op(priv
, op
, val
);
1155 ar8327_setup_port(struct ar8216_priv
*priv
, int port
, u32 egress
, u32 ingress
,
1156 u32 members
, u32 pvid
)
1161 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1162 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1163 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1165 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1167 case AR8216_OUT_KEEP
:
1168 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1170 case AR8216_OUT_STRIP_VLAN
:
1171 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
1173 case AR8216_OUT_ADD_VLAN
:
1174 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
1178 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1179 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1180 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1183 t
|= AR8327_PORT_LOOKUP_LEARN
;
1184 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1185 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1186 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1189 static const struct ar8xxx_chip ar8327_chip
= {
1190 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1191 .hw_init
= ar8327_hw_init
,
1192 .init_globals
= ar8327_init_globals
,
1193 .init_port
= ar8327_init_port
,
1194 .setup_port
= ar8327_setup_port
,
1195 .read_port_status
= ar8327_read_port_status
,
1196 .atu_flush
= ar8327_atu_flush
,
1197 .vtu_flush
= ar8327_vtu_flush
,
1198 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1200 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1201 .mib_decs
= ar8236_mibs
,
1205 ar8216_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1206 struct switch_val
*val
)
1208 struct ar8216_priv
*priv
= to_ar8216(dev
);
1209 priv
->vlan
= !!val
->value
.i
;
1214 ar8216_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1215 struct switch_val
*val
)
1217 struct ar8216_priv
*priv
= to_ar8216(dev
);
1218 val
->value
.i
= priv
->vlan
;
1224 ar8216_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1226 struct ar8216_priv
*priv
= to_ar8216(dev
);
1228 /* make sure no invalid PVIDs get set */
1230 if (vlan
>= dev
->vlans
)
1233 priv
->pvid
[port
] = vlan
;
1238 ar8216_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1240 struct ar8216_priv
*priv
= to_ar8216(dev
);
1241 *vlan
= priv
->pvid
[port
];
1246 ar8216_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1247 struct switch_val
*val
)
1249 struct ar8216_priv
*priv
= to_ar8216(dev
);
1250 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1255 ar8216_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1256 struct switch_val
*val
)
1258 struct ar8216_priv
*priv
= to_ar8216(dev
);
1259 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1264 ar8216_sw_get_port_link(struct switch_dev
*dev
, int port
,
1265 struct switch_port_link
*link
)
1267 struct ar8216_priv
*priv
= to_ar8216(dev
);
1269 ar8216_read_port_link(priv
, port
, link
);
1274 ar8216_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1276 struct ar8216_priv
*priv
= to_ar8216(dev
);
1277 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1281 for (i
= 0; i
< dev
->ports
; i
++) {
1282 struct switch_port
*p
;
1284 if (!(ports
& (1 << i
)))
1287 p
= &val
->value
.ports
[val
->len
++];
1289 if (priv
->vlan_tagged
& (1 << i
))
1290 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1298 ar8216_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1300 struct ar8216_priv
*priv
= to_ar8216(dev
);
1301 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1305 for (i
= 0; i
< val
->len
; i
++) {
1306 struct switch_port
*p
= &val
->value
.ports
[i
];
1308 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1309 priv
->vlan_tagged
|= (1 << p
->id
);
1311 priv
->vlan_tagged
&= ~(1 << p
->id
);
1312 priv
->pvid
[p
->id
] = val
->port_vlan
;
1314 /* make sure that an untagged port does not
1315 * appear in other vlans */
1316 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1317 if (j
== val
->port_vlan
)
1319 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1329 ar8216_sw_hw_apply(struct switch_dev
*dev
)
1331 struct ar8216_priv
*priv
= to_ar8216(dev
);
1332 u8 portmask
[AR8X16_MAX_PORTS
];
1335 mutex_lock(&priv
->reg_mutex
);
1336 /* flush all vlan translation unit entries */
1337 priv
->chip
->vtu_flush(priv
);
1339 memset(portmask
, 0, sizeof(portmask
));
1341 /* calculate the port destination masks and load vlans
1342 * into the vlan translation unit */
1343 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1344 u8 vp
= priv
->vlan_table
[j
];
1349 for (i
= 0; i
< dev
->ports
; i
++) {
1352 portmask
[i
] |= vp
& ~mask
;
1355 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1356 priv
->vlan_table
[j
]);
1360 * isolate all ports, but connect them to the cpu port */
1361 for (i
= 0; i
< dev
->ports
; i
++) {
1362 if (i
== AR8216_PORT_CPU
)
1365 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1366 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1370 /* update the port destination mask registers and tag settings */
1371 for (i
= 0; i
< dev
->ports
; i
++) {
1372 int egress
, ingress
;
1376 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1377 if (priv
->vlan_tagged
& (1 << i
))
1378 egress
= AR8216_OUT_ADD_VLAN
;
1380 egress
= AR8216_OUT_STRIP_VLAN
;
1381 ingress
= AR8216_IN_SECURE
;
1384 egress
= AR8216_OUT_KEEP
;
1385 ingress
= AR8216_IN_PORT_ONLY
;
1388 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1391 mutex_unlock(&priv
->reg_mutex
);
1396 ar8216_sw_reset_switch(struct switch_dev
*dev
)
1398 struct ar8216_priv
*priv
= to_ar8216(dev
);
1401 mutex_lock(&priv
->reg_mutex
);
1402 memset(&priv
->vlan
, 0, sizeof(struct ar8216_priv
) -
1403 offsetof(struct ar8216_priv
, vlan
));
1405 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1406 priv
->vlan_id
[i
] = i
;
1408 /* Configure all ports */
1409 for (i
= 0; i
< dev
->ports
; i
++)
1410 priv
->chip
->init_port(priv
, i
);
1412 priv
->chip
->init_globals(priv
);
1413 mutex_unlock(&priv
->reg_mutex
);
1415 return ar8216_sw_hw_apply(dev
);
1419 ar8216_sw_set_reset_mibs(struct switch_dev
*dev
,
1420 const struct switch_attr
*attr
,
1421 struct switch_val
*val
)
1423 struct ar8216_priv
*priv
= to_ar8216(dev
);
1427 if (!ar8xxx_has_mib_counters(priv
))
1430 mutex_lock(&priv
->mib_lock
);
1432 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1433 sizeof(*priv
->mib_stats
);
1434 memset(priv
->mib_stats
, '\0', len
);
1435 ret
= ar8216_mib_flush(priv
);
1442 mutex_unlock(&priv
->mib_lock
);
1447 ar8216_sw_set_port_reset_mib(struct switch_dev
*dev
,
1448 const struct switch_attr
*attr
,
1449 struct switch_val
*val
)
1451 struct ar8216_priv
*priv
= to_ar8216(dev
);
1455 if (!ar8xxx_has_mib_counters(priv
))
1458 port
= val
->port_vlan
;
1459 if (port
>= dev
->ports
)
1462 mutex_lock(&priv
->mib_lock
);
1463 ret
= ar8216_mib_capture(priv
);
1467 ar8216_mib_fetch_port_stat(priv
, port
, true);
1472 mutex_unlock(&priv
->mib_lock
);
1477 ar8216_sw_get_port_mib(struct switch_dev
*dev
,
1478 const struct switch_attr
*attr
,
1479 struct switch_val
*val
)
1481 struct ar8216_priv
*priv
= to_ar8216(dev
);
1482 const struct ar8xxx_chip
*chip
= priv
->chip
;
1486 char *buf
= priv
->buf
;
1489 if (!ar8xxx_has_mib_counters(priv
))
1492 port
= val
->port_vlan
;
1493 if (port
>= dev
->ports
)
1496 mutex_lock(&priv
->mib_lock
);
1497 ret
= ar8216_mib_capture(priv
);
1501 ar8216_mib_fetch_port_stat(priv
, port
, false);
1502 mutex_unlock(&priv
->mib_lock
);
1504 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1505 "Port %d MIB counters\n",
1508 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1509 for (i
= 0; i
< chip
->num_mibs
; i
++)
1510 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1512 chip
->mib_decs
[i
].name
,
1521 mutex_unlock(&priv
->mib_lock
);
1525 static struct switch_attr ar8216_globals
[] = {
1527 .type
= SWITCH_TYPE_INT
,
1528 .name
= "enable_vlan",
1529 .description
= "Enable VLAN mode",
1530 .set
= ar8216_sw_set_vlan
,
1531 .get
= ar8216_sw_get_vlan
,
1535 .type
= SWITCH_TYPE_NOVAL
,
1536 .name
= "reset_mibs",
1537 .description
= "Reset all MIB counters",
1538 .set
= ar8216_sw_set_reset_mibs
,
1543 static struct switch_attr ar8216_port
[] = {
1545 .type
= SWITCH_TYPE_NOVAL
,
1546 .name
= "reset_mib",
1547 .description
= "Reset single port MIB counters",
1548 .set
= ar8216_sw_set_port_reset_mib
,
1551 .type
= SWITCH_TYPE_STRING
,
1553 .description
= "Get port's MIB counters",
1555 .get
= ar8216_sw_get_port_mib
,
1559 static struct switch_attr ar8216_vlan
[] = {
1561 .type
= SWITCH_TYPE_INT
,
1563 .description
= "VLAN ID (0-4094)",
1564 .set
= ar8216_sw_set_vid
,
1565 .get
= ar8216_sw_get_vid
,
1570 static const struct switch_dev_ops ar8216_sw_ops
= {
1572 .attr
= ar8216_globals
,
1573 .n_attr
= ARRAY_SIZE(ar8216_globals
),
1576 .attr
= ar8216_port
,
1577 .n_attr
= ARRAY_SIZE(ar8216_port
),
1580 .attr
= ar8216_vlan
,
1581 .n_attr
= ARRAY_SIZE(ar8216_vlan
),
1583 .get_port_pvid
= ar8216_sw_get_pvid
,
1584 .set_port_pvid
= ar8216_sw_set_pvid
,
1585 .get_vlan_ports
= ar8216_sw_get_ports
,
1586 .set_vlan_ports
= ar8216_sw_set_ports
,
1587 .apply_config
= ar8216_sw_hw_apply
,
1588 .reset_switch
= ar8216_sw_reset_switch
,
1589 .get_port_link
= ar8216_sw_get_port_link
,
1593 ar8216_id_chip(struct ar8216_priv
*priv
)
1599 val
= ar8216_mii_read(priv
, AR8216_REG_CTRL
);
1603 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1604 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
1607 val
= ar8216_mii_read(priv
, AR8216_REG_CTRL
);
1611 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
1616 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
1617 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
1619 switch (priv
->chip_ver
) {
1620 case AR8XXX_VER_AR8216
:
1621 priv
->chip
= &ar8216_chip
;
1623 case AR8XXX_VER_AR8236
:
1624 priv
->chip
= &ar8236_chip
;
1626 case AR8XXX_VER_AR8316
:
1627 priv
->chip
= &ar8316_chip
;
1629 case AR8XXX_VER_AR8327
:
1630 priv
->mii_lo_first
= true;
1631 priv
->chip
= &ar8327_chip
;
1635 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1636 priv
->chip_ver
, priv
->chip_rev
,
1637 mdiobus_read(priv
->phy
->bus
, priv
->phy
->addr
, 2),
1638 mdiobus_read(priv
->phy
->bus
, priv
->phy
->addr
, 3));
1647 ar8xxx_mib_work_func(struct work_struct
*work
)
1649 struct ar8216_priv
*priv
;
1652 priv
= container_of(work
, struct ar8216_priv
, mib_work
.work
);
1654 mutex_lock(&priv
->mib_lock
);
1656 err
= ar8216_mib_capture(priv
);
1660 ar8216_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
1663 priv
->mib_next_port
++;
1664 if (priv
->mib_next_port
> priv
->dev
.ports
)
1665 priv
->mib_next_port
= 0;
1667 mutex_unlock(&priv
->mib_lock
);
1668 schedule_delayed_work(&priv
->mib_work
,
1669 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1673 ar8xxx_mib_init(struct ar8216_priv
*priv
)
1677 if (!ar8xxx_has_mib_counters(priv
))
1680 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
1682 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1683 sizeof(*priv
->mib_stats
);
1684 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
1686 if (!priv
->mib_stats
)
1689 mutex_init(&priv
->mib_lock
);
1690 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
1696 ar8xxx_mib_start(struct ar8216_priv
*priv
)
1698 if (!ar8xxx_has_mib_counters(priv
))
1701 schedule_delayed_work(&priv
->mib_work
,
1702 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
1706 ar8xxx_mib_cleanup(struct ar8216_priv
*priv
)
1708 if (!ar8xxx_has_mib_counters(priv
))
1711 cancel_delayed_work(&priv
->mib_work
);
1712 kfree(priv
->mib_stats
);
1716 ar8216_config_init(struct phy_device
*pdev
)
1718 struct ar8216_priv
*priv
= pdev
->priv
;
1719 struct net_device
*dev
= pdev
->attached_dev
;
1720 struct switch_dev
*swdev
;
1724 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
1731 ret
= ar8216_id_chip(priv
);
1735 if (pdev
->addr
!= 0) {
1736 if (ar8xxx_has_gige(priv
)) {
1737 pdev
->supported
|= SUPPORTED_1000baseT_Full
;
1738 pdev
->advertising
|= ADVERTISED_1000baseT_Full
;
1741 if (chip_is_ar8316(priv
)) {
1742 /* check if we're attaching to the switch twice */
1743 pdev
= pdev
->bus
->phy_map
[0];
1749 /* switch device has not been initialized, reuse priv */
1751 priv
->port4_phy
= true;
1758 /* switch device has been initialized, reinit */
1760 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
1761 priv
->initialized
= false;
1762 priv
->port4_phy
= true;
1763 ar8316_hw_init(priv
);
1771 if (ar8xxx_has_gige(priv
))
1772 pdev
->supported
= SUPPORTED_1000baseT_Full
;
1774 pdev
->supported
= SUPPORTED_100baseT_Full
;
1775 pdev
->advertising
= pdev
->supported
;
1777 mutex_init(&priv
->reg_mutex
);
1778 priv
->read
= ar8216_mii_read
;
1779 priv
->write
= ar8216_mii_write
;
1784 swdev
->cpu_port
= AR8216_PORT_CPU
;
1785 swdev
->ops
= &ar8216_sw_ops
;
1786 swdev
->ports
= AR8216_NUM_PORTS
;
1788 if (chip_is_ar8316(priv
)) {
1789 swdev
->name
= "Atheros AR8316";
1790 swdev
->vlans
= AR8X16_MAX_VLANS
;
1792 if (priv
->port4_phy
) {
1793 /* port 5 connected to the other mac, therefore unusable */
1794 swdev
->ports
= (AR8216_NUM_PORTS
- 1);
1796 } else if (chip_is_ar8236(priv
)) {
1797 swdev
->name
= "Atheros AR8236";
1798 swdev
->vlans
= AR8216_NUM_VLANS
;
1799 swdev
->ports
= AR8216_NUM_PORTS
;
1800 } else if (chip_is_ar8327(priv
)) {
1801 swdev
->name
= "Atheros AR8327";
1802 swdev
->vlans
= AR8X16_MAX_VLANS
;
1803 swdev
->ports
= AR8327_NUM_PORTS
;
1805 swdev
->name
= "Atheros AR8216";
1806 swdev
->vlans
= AR8216_NUM_VLANS
;
1809 ret
= ar8xxx_mib_init(priv
);
1813 ret
= register_switch(&priv
->dev
, pdev
->attached_dev
);
1815 goto err_cleanup_mib
;
1817 printk(KERN_INFO
"%s: %s switch driver attached.\n",
1818 pdev
->attached_dev
->name
, swdev
->name
);
1822 ret
= priv
->chip
->hw_init(priv
);
1824 goto err_cleanup_mib
;
1826 ret
= ar8216_sw_reset_switch(&priv
->dev
);
1828 goto err_cleanup_mib
;
1830 dev
->phy_ptr
= priv
;
1832 /* VID fixup only needed on ar8216 */
1833 if (chip_is_ar8216(priv
) && pdev
->addr
== 0) {
1834 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
1835 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
1836 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
1841 ar8xxx_mib_start(priv
);
1846 ar8xxx_mib_cleanup(priv
);
1853 ar8216_read_status(struct phy_device
*phydev
)
1855 struct ar8216_priv
*priv
= phydev
->priv
;
1856 struct switch_port_link link
;
1859 if (phydev
->addr
!= 0)
1860 return genphy_read_status(phydev
);
1862 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
1863 phydev
->link
= !!link
.link
;
1867 switch (link
.speed
) {
1868 case SWITCH_PORT_SPEED_10
:
1869 phydev
->speed
= SPEED_10
;
1871 case SWITCH_PORT_SPEED_100
:
1872 phydev
->speed
= SPEED_100
;
1874 case SWITCH_PORT_SPEED_1000
:
1875 phydev
->speed
= SPEED_1000
;
1880 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1882 /* flush the address translation unit */
1883 mutex_lock(&priv
->reg_mutex
);
1884 ret
= priv
->chip
->atu_flush(priv
);
1885 mutex_unlock(&priv
->reg_mutex
);
1887 phydev
->state
= PHY_RUNNING
;
1888 netif_carrier_on(phydev
->attached_dev
);
1889 phydev
->adjust_link(phydev
->attached_dev
);
1895 ar8216_config_aneg(struct phy_device
*phydev
)
1897 if (phydev
->addr
== 0)
1900 return genphy_config_aneg(phydev
);
1904 ar8216_probe(struct phy_device
*pdev
)
1906 struct ar8216_priv
*priv
;
1909 priv
= kzalloc(sizeof(struct ar8216_priv
), GFP_KERNEL
);
1915 ret
= ar8216_id_chip(priv
);
1922 ar8216_remove(struct phy_device
*pdev
)
1924 struct ar8216_priv
*priv
= pdev
->priv
;
1925 struct net_device
*dev
= pdev
->attached_dev
;
1930 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
1931 dev
->eth_mangle_rx
= NULL
;
1932 dev
->eth_mangle_tx
= NULL
;
1934 if (pdev
->addr
== 0)
1935 unregister_switch(&priv
->dev
);
1937 ar8xxx_mib_cleanup(priv
);
1941 static struct phy_driver ar8216_driver
= {
1942 .phy_id
= 0x004d0000,
1943 .name
= "Atheros AR8216/AR8236/AR8316",
1944 .phy_id_mask
= 0xffff0000,
1945 .features
= PHY_BASIC_FEATURES
,
1946 .probe
= ar8216_probe
,
1947 .remove
= ar8216_remove
,
1948 .config_init
= &ar8216_config_init
,
1949 .config_aneg
= &ar8216_config_aneg
,
1950 .read_status
= &ar8216_read_status
,
1951 .driver
= { .owner
= THIS_MODULE
},
1957 return phy_driver_register(&ar8216_driver
);
1963 phy_driver_unregister(&ar8216_driver
);
1966 module_init(ar8216_init
);
1967 module_exit(ar8216_exit
);
1968 MODULE_LICENSE("GPL");