2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
40 /* size of the vlan table */
41 #define AR8X16_MAX_VLANS 128
42 #define AR8X16_PROBE_RETRIES 10
43 #define AR8X16_MAX_PORTS 8
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
49 #define AR8XXX_CAP_GIGE BIT(0)
50 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
53 AR8XXX_VER_AR8216
= 0x01,
54 AR8XXX_VER_AR8236
= 0x03,
55 AR8XXX_VER_AR8316
= 0x10,
56 AR8XXX_VER_AR8327
= 0x12,
57 AR8XXX_VER_AR8337
= 0x13,
60 struct ar8xxx_mib_desc
{
69 int (*hw_init
)(struct ar8xxx_priv
*priv
);
70 void (*cleanup
)(struct ar8xxx_priv
*priv
);
72 void (*init_globals
)(struct ar8xxx_priv
*priv
);
73 void (*init_port
)(struct ar8xxx_priv
*priv
, int port
);
74 void (*setup_port
)(struct ar8xxx_priv
*priv
, int port
, u32 egress
,
75 u32 ingress
, u32 members
, u32 pvid
);
76 u32 (*read_port_status
)(struct ar8xxx_priv
*priv
, int port
);
77 int (*atu_flush
)(struct ar8xxx_priv
*priv
);
78 void (*vtu_flush
)(struct ar8xxx_priv
*priv
);
79 void (*vtu_load_vlan
)(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
);
81 const struct ar8xxx_mib_desc
*mib_decs
;
91 struct switch_dev dev
;
92 struct mii_bus
*mii_bus
;
93 struct phy_device
*phy
;
95 u32 (*read
)(struct ar8xxx_priv
*priv
, int reg
);
96 void (*write
)(struct ar8xxx_priv
*priv
, int reg
, u32 val
);
97 u32 (*rmw
)(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
);
99 int (*get_port_link
)(unsigned port
);
101 const struct net_device_ops
*ndo_old
;
102 struct net_device_ops ndo
;
103 struct mutex reg_mutex
;
106 const struct ar8xxx_chip
*chip
;
108 struct ar8327_data ar8327
;
117 struct mutex mib_lock
;
118 struct delayed_work mib_work
;
122 struct list_head list
;
123 unsigned int use_count
;
125 /* all fields below are cleared on reset */
127 u16 vlan_id
[AR8X16_MAX_VLANS
];
128 u8 vlan_table
[AR8X16_MAX_VLANS
];
130 u16 pvid
[AR8X16_MAX_PORTS
];
139 #define MIB_DESC(_s , _o, _n) \
146 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
147 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
148 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
149 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
150 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
151 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
152 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
153 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
154 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
155 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
156 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
157 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
158 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
159 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
160 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
161 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
162 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
163 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
164 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
165 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
166 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
167 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
168 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
169 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
170 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
171 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
172 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
173 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
174 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
175 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
176 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
177 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
178 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
179 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
180 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
181 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
182 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
183 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
186 static const struct ar8xxx_mib_desc ar8236_mibs
[] = {
187 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
188 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
189 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
190 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
191 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
192 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
193 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
194 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
195 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
196 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
197 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
198 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
199 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
200 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
201 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
202 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
203 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
204 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
205 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
206 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
207 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
208 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
209 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
210 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
211 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
212 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
213 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
214 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
215 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
216 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
217 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
218 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
219 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
220 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
221 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
222 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
223 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
224 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
225 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
228 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
229 static LIST_HEAD(ar8xxx_dev_list
);
231 static inline struct ar8xxx_priv
*
232 swdev_to_ar8xxx(struct switch_dev
*swdev
)
234 return container_of(swdev
, struct ar8xxx_priv
, dev
);
237 static inline bool ar8xxx_has_gige(struct ar8xxx_priv
*priv
)
239 return priv
->chip
->caps
& AR8XXX_CAP_GIGE
;
242 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv
*priv
)
244 return priv
->chip
->caps
& AR8XXX_CAP_MIB_COUNTERS
;
247 static inline bool chip_is_ar8216(struct ar8xxx_priv
*priv
)
249 return priv
->chip_ver
== AR8XXX_VER_AR8216
;
252 static inline bool chip_is_ar8236(struct ar8xxx_priv
*priv
)
254 return priv
->chip_ver
== AR8XXX_VER_AR8236
;
257 static inline bool chip_is_ar8316(struct ar8xxx_priv
*priv
)
259 return priv
->chip_ver
== AR8XXX_VER_AR8316
;
262 static inline bool chip_is_ar8327(struct ar8xxx_priv
*priv
)
264 return priv
->chip_ver
== AR8XXX_VER_AR8327
;
267 static inline bool chip_is_ar8337(struct ar8xxx_priv
*priv
)
269 return priv
->chip_ver
== AR8XXX_VER_AR8337
;
273 split_addr(u32 regaddr
, u16
*r1
, u16
*r2
, u16
*page
)
276 *r1
= regaddr
& 0x1e;
282 *page
= regaddr
& 0x1ff;
286 ar8xxx_mii_read(struct ar8xxx_priv
*priv
, int reg
)
288 struct mii_bus
*bus
= priv
->mii_bus
;
292 split_addr((u32
) reg
, &r1
, &r2
, &page
);
294 mutex_lock(&bus
->mdio_lock
);
296 bus
->write(bus
, 0x18, 0, page
);
297 usleep_range(1000, 2000); /* wait for the page switch to propagate */
298 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
299 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
301 mutex_unlock(&bus
->mdio_lock
);
303 return (hi
<< 16) | lo
;
307 ar8xxx_mii_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
309 struct mii_bus
*bus
= priv
->mii_bus
;
313 split_addr((u32
) reg
, &r1
, &r2
, &r3
);
315 hi
= (u16
) (val
>> 16);
317 mutex_lock(&bus
->mdio_lock
);
319 bus
->write(bus
, 0x18, 0, r3
);
320 usleep_range(1000, 2000); /* wait for the page switch to propagate */
321 if (priv
->mii_lo_first
) {
322 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
323 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
325 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
326 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
329 mutex_unlock(&bus
->mdio_lock
);
333 ar8xxx_mii_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
335 struct mii_bus
*bus
= priv
->mii_bus
;
340 split_addr((u32
) reg
, &r1
, &r2
, &page
);
342 mutex_lock(&bus
->mdio_lock
);
344 bus
->write(bus
, 0x18, 0, page
);
345 usleep_range(1000, 2000); /* wait for the page switch to propagate */
347 lo
= bus
->read(bus
, 0x10 | r2
, r1
);
348 hi
= bus
->read(bus
, 0x10 | r2
, r1
+ 1);
355 hi
= (u16
) (ret
>> 16);
357 if (priv
->mii_lo_first
) {
358 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
359 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
361 bus
->write(bus
, 0x10 | r2
, r1
+ 1, hi
);
362 bus
->write(bus
, 0x10 | r2
, r1
, lo
);
365 mutex_unlock(&bus
->mdio_lock
);
372 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
373 u16 dbg_addr
, u16 dbg_data
)
375 struct mii_bus
*bus
= priv
->mii_bus
;
377 mutex_lock(&bus
->mdio_lock
);
378 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
379 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
380 mutex_unlock(&bus
->mdio_lock
);
384 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 data
)
386 struct mii_bus
*bus
= priv
->mii_bus
;
388 mutex_lock(&bus
->mdio_lock
);
389 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
390 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
391 mutex_unlock(&bus
->mdio_lock
);
395 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
397 return priv
->rmw(priv
, reg
, mask
, val
);
401 ar8xxx_reg_set(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
403 priv
->rmw(priv
, reg
, 0, val
);
407 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
412 for (i
= 0; i
< timeout
; i
++) {
415 t
= priv
->read(priv
, reg
);
416 if ((t
& mask
) == val
)
419 usleep_range(1000, 2000);
426 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
431 lockdep_assert_held(&priv
->mib_lock
);
433 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
434 mib_func
= AR8327_REG_MIB_FUNC
;
436 mib_func
= AR8216_REG_MIB_FUNC
;
438 /* Capture the hardware statistics for all ports */
439 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
441 /* Wait for the capturing to complete. */
442 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
453 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
455 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
459 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
461 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
465 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
471 WARN_ON(port
>= priv
->dev
.ports
);
473 lockdep_assert_held(&priv
->mib_lock
);
475 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
476 base
= AR8327_REG_PORT_STATS_BASE(port
);
477 else if (chip_is_ar8236(priv
) ||
478 chip_is_ar8316(priv
))
479 base
= AR8236_REG_PORT_STATS_BASE(port
);
481 base
= AR8216_REG_PORT_STATS_BASE(port
);
483 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
484 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
485 const struct ar8xxx_mib_desc
*mib
;
488 mib
= &priv
->chip
->mib_decs
[i
];
489 t
= priv
->read(priv
, base
+ mib
->offset
);
490 if (mib
->size
== 2) {
493 hi
= priv
->read(priv
, base
+ mib
->offset
+ 4);
505 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
506 struct switch_port_link
*link
)
511 memset(link
, '\0', sizeof(*link
));
513 status
= priv
->chip
->read_port_status(priv
, port
);
515 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
517 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
521 if (priv
->get_port_link
) {
524 err
= priv
->get_port_link(port
);
533 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
534 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
535 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
537 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
538 AR8216_PORT_STATUS_SPEED_S
;
541 case AR8216_PORT_SPEED_10M
:
542 link
->speed
= SWITCH_PORT_SPEED_10
;
544 case AR8216_PORT_SPEED_100M
:
545 link
->speed
= SWITCH_PORT_SPEED_100
;
547 case AR8216_PORT_SPEED_1000M
:
548 link
->speed
= SWITCH_PORT_SPEED_1000
;
551 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
556 static struct sk_buff
*
557 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
559 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
568 if (unlikely(skb_headroom(skb
) < 2)) {
569 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
573 buf
= skb_push(skb
, 2);
581 dev_kfree_skb_any(skb
);
586 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
588 struct ar8xxx_priv
*priv
;
596 /* don't strip the header if vlan mode is disabled */
600 /* strip header, get vlan id */
604 /* check for vlan header presence */
605 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
610 /* no need to fix up packets coming from a tagged source */
611 if (priv
->vlan_tagged
& (1 << port
))
614 /* lookup port vid from local table, the switch passes an invalid vlan id */
615 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
618 buf
[14 + 2] |= vlan
>> 8;
619 buf
[15 + 2] = vlan
& 0xff;
623 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
629 t
= priv
->read(priv
, reg
);
630 if ((t
& mask
) == val
)
639 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
640 (unsigned int) reg
, t
, mask
, val
);
645 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
647 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
649 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
650 val
&= AR8216_VTUDATA_MEMBER
;
651 val
|= AR8216_VTUDATA_VALID
;
652 priv
->write(priv
, AR8216_REG_VTU_DATA
, val
);
654 op
|= AR8216_VTU_ACTIVE
;
655 priv
->write(priv
, AR8216_REG_VTU
, op
);
659 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
661 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
665 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
669 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
670 ar8216_vtu_op(priv
, op
, port_mask
);
674 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
678 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU
, AR8216_ATU_ACTIVE
, 0);
680 priv
->write(priv
, AR8216_REG_ATU
, AR8216_ATU_OP_FLUSH
);
686 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
688 return priv
->read(priv
, AR8216_REG_PORT_STATUS(port
));
692 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
693 u32 members
, u32 pvid
)
697 if (chip_is_ar8216(priv
) && priv
->vlan
&& port
== AR8216_PORT_CPU
)
698 header
= AR8216_PORT_CTRL_HEADER
;
702 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
703 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
704 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
705 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
706 AR8216_PORT_CTRL_LEARN
| header
|
707 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
708 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
710 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
711 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
712 AR8216_PORT_VLAN_DEFAULT_ID
,
713 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
714 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
715 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
719 ar8216_hw_init(struct ar8xxx_priv
*priv
)
725 ar8216_init_globals(struct ar8xxx_priv
*priv
)
727 /* standard atheros magic */
728 priv
->write(priv
, 0x38, 0xc000050e);
730 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
731 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
735 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
737 /* Enable port learning and tx */
738 priv
->write(priv
, AR8216_REG_PORT_CTRL(port
),
739 AR8216_PORT_CTRL_LEARN
|
740 (4 << AR8216_PORT_CTRL_STATE_S
));
742 priv
->write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
744 if (port
== AR8216_PORT_CPU
) {
745 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
746 AR8216_PORT_STATUS_LINK_UP
|
747 (ar8xxx_has_gige(priv
) ?
748 AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
749 AR8216_PORT_STATUS_TXMAC
|
750 AR8216_PORT_STATUS_RXMAC
|
751 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_RXFLOW
: 0) |
752 (chip_is_ar8316(priv
) ? AR8216_PORT_STATUS_TXFLOW
: 0) |
753 AR8216_PORT_STATUS_DUPLEX
);
755 priv
->write(priv
, AR8216_REG_PORT_STATUS(port
),
756 AR8216_PORT_STATUS_LINK_AUTO
);
760 static const struct ar8xxx_chip ar8216_chip
= {
761 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
763 .hw_init
= ar8216_hw_init
,
764 .init_globals
= ar8216_init_globals
,
765 .init_port
= ar8216_init_port
,
766 .setup_port
= ar8216_setup_port
,
767 .read_port_status
= ar8216_read_port_status
,
768 .atu_flush
= ar8216_atu_flush
,
769 .vtu_flush
= ar8216_vtu_flush
,
770 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
772 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
773 .mib_decs
= ar8216_mibs
,
777 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
778 u32 members
, u32 pvid
)
780 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
781 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
782 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
783 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
784 AR8216_PORT_CTRL_LEARN
|
785 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
786 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
788 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
789 AR8236_PORT_VLAN_DEFAULT_ID
,
790 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
792 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
793 AR8236_PORT_VLAN2_VLAN_MODE
|
794 AR8236_PORT_VLAN2_MEMBER
,
795 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
796 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
800 ar8236_hw_init(struct ar8xxx_priv
*priv
)
805 if (priv
->initialized
)
808 /* Initialize the PHYs */
810 for (i
= 0; i
< 5; i
++) {
811 mdiobus_write(bus
, i
, MII_ADVERTISE
,
812 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
813 ADVERTISE_PAUSE_ASYM
);
814 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
818 priv
->initialized
= true;
823 ar8236_init_globals(struct ar8xxx_priv
*priv
)
825 /* enable jumbo frames */
826 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
827 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
829 /* Enable MIB counters */
830 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
831 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
835 static const struct ar8xxx_chip ar8236_chip
= {
836 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
837 .hw_init
= ar8236_hw_init
,
838 .init_globals
= ar8236_init_globals
,
839 .init_port
= ar8216_init_port
,
840 .setup_port
= ar8236_setup_port
,
841 .read_port_status
= ar8216_read_port_status
,
842 .atu_flush
= ar8216_atu_flush
,
843 .vtu_flush
= ar8216_vtu_flush
,
844 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
846 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
847 .mib_decs
= ar8236_mibs
,
851 ar8316_hw_init(struct ar8xxx_priv
*priv
)
857 val
= priv
->read(priv
, AR8316_REG_POSTRIP
);
859 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
860 if (priv
->port4_phy
) {
861 /* value taken from Ubiquiti RouterStation Pro */
863 pr_info("ar8316: Using port 4 as PHY\n");
866 pr_info("ar8316: Using port 4 as switch port\n");
868 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
869 /* value taken from AVM Fritz!Box 7390 sources */
872 /* no known value for phy interface */
873 pr_err("ar8316: unsupported mii mode: %d.\n",
874 priv
->phy
->interface
);
881 priv
->write(priv
, AR8316_REG_POSTRIP
, newval
);
883 if (priv
->port4_phy
&&
884 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
885 /* work around for phy4 rgmii mode */
886 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
888 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
890 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
894 /* Initialize the ports */
896 for (i
= 0; i
< 5; i
++) {
897 /* initialize the port itself */
898 mdiobus_write(bus
, i
, MII_ADVERTISE
,
899 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
900 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
901 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
907 priv
->initialized
= true;
912 ar8316_init_globals(struct ar8xxx_priv
*priv
)
914 /* standard atheros magic */
915 priv
->write(priv
, 0x38, 0xc000050e);
917 /* enable cpu port to receive multicast and broadcast frames */
918 priv
->write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
920 /* enable jumbo frames */
921 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
922 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
924 /* Enable MIB counters */
925 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
926 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
930 static const struct ar8xxx_chip ar8316_chip
= {
931 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
932 .hw_init
= ar8316_hw_init
,
933 .init_globals
= ar8316_init_globals
,
934 .init_port
= ar8216_init_port
,
935 .setup_port
= ar8216_setup_port
,
936 .read_port_status
= ar8216_read_port_status
,
937 .atu_flush
= ar8216_atu_flush
,
938 .vtu_flush
= ar8216_vtu_flush
,
939 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
941 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
942 .mib_decs
= ar8236_mibs
,
946 ar8327_get_pad_cfg(struct ar8327_pad_cfg
*cfg
)
958 case AR8327_PAD_MAC2MAC_MII
:
959 t
= AR8327_PAD_MAC_MII_EN
;
961 t
|= AR8327_PAD_MAC_MII_RXCLK_SEL
;
963 t
|= AR8327_PAD_MAC_MII_TXCLK_SEL
;
966 case AR8327_PAD_MAC2MAC_GMII
:
967 t
= AR8327_PAD_MAC_GMII_EN
;
969 t
|= AR8327_PAD_MAC_GMII_RXCLK_SEL
;
971 t
|= AR8327_PAD_MAC_GMII_TXCLK_SEL
;
974 case AR8327_PAD_MAC_SGMII
:
975 t
= AR8327_PAD_SGMII_EN
;
978 * WAR for the QUalcomm Atheros AP136 board.
979 * It seems that RGMII TX/RX delay settings needs to be
980 * applied for SGMII mode as well, The ethernet is not
981 * reliable without this.
983 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
984 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
985 if (cfg
->rxclk_delay_en
)
986 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
987 if (cfg
->txclk_delay_en
)
988 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
990 if (cfg
->sgmii_delay_en
)
991 t
|= AR8327_PAD_SGMII_DELAY_EN
;
995 case AR8327_PAD_MAC2PHY_MII
:
996 t
= AR8327_PAD_PHY_MII_EN
;
998 t
|= AR8327_PAD_PHY_MII_RXCLK_SEL
;
1000 t
|= AR8327_PAD_PHY_MII_TXCLK_SEL
;
1003 case AR8327_PAD_MAC2PHY_GMII
:
1004 t
= AR8327_PAD_PHY_GMII_EN
;
1005 if (cfg
->pipe_rxclk_sel
)
1006 t
|= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL
;
1008 t
|= AR8327_PAD_PHY_GMII_RXCLK_SEL
;
1010 t
|= AR8327_PAD_PHY_GMII_TXCLK_SEL
;
1013 case AR8327_PAD_MAC_RGMII
:
1014 t
= AR8327_PAD_RGMII_EN
;
1015 t
|= cfg
->txclk_delay_sel
<< AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S
;
1016 t
|= cfg
->rxclk_delay_sel
<< AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S
;
1017 if (cfg
->rxclk_delay_en
)
1018 t
|= AR8327_PAD_RGMII_RXCLK_DELAY_EN
;
1019 if (cfg
->txclk_delay_en
)
1020 t
|= AR8327_PAD_RGMII_TXCLK_DELAY_EN
;
1023 case AR8327_PAD_PHY_GMII
:
1024 t
= AR8327_PAD_PHYX_GMII_EN
;
1027 case AR8327_PAD_PHY_RGMII
:
1028 t
= AR8327_PAD_PHYX_RGMII_EN
;
1031 case AR8327_PAD_PHY_MII
:
1032 t
= AR8327_PAD_PHYX_MII_EN
;
1040 ar8327_phy_fixup(struct ar8xxx_priv
*priv
, int phy
)
1042 switch (priv
->chip_rev
) {
1044 /* For 100M waveform */
1045 ar8xxx_phy_dbg_write(priv
, phy
, 0, 0x02ea);
1046 /* Turn on Gigabit clock */
1047 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x68a0);
1051 ar8xxx_phy_mmd_write(priv
, phy
, 0x7, 0x3c);
1052 ar8xxx_phy_mmd_write(priv
, phy
, 0x4007, 0x0);
1055 ar8xxx_phy_mmd_write(priv
, phy
, 0x3, 0x800d);
1056 ar8xxx_phy_mmd_write(priv
, phy
, 0x4003, 0x803f);
1058 ar8xxx_phy_dbg_write(priv
, phy
, 0x3d, 0x6860);
1059 ar8xxx_phy_dbg_write(priv
, phy
, 0x5, 0x2c46);
1060 ar8xxx_phy_dbg_write(priv
, phy
, 0x3c, 0x6000);
1066 ar8327_get_port_init_status(struct ar8327_port_cfg
*cfg
)
1070 if (!cfg
->force_link
)
1071 return AR8216_PORT_STATUS_LINK_AUTO
;
1073 t
= AR8216_PORT_STATUS_TXMAC
| AR8216_PORT_STATUS_RXMAC
;
1074 t
|= cfg
->duplex
? AR8216_PORT_STATUS_DUPLEX
: 0;
1075 t
|= cfg
->rxpause
? AR8216_PORT_STATUS_RXFLOW
: 0;
1076 t
|= cfg
->txpause
? AR8216_PORT_STATUS_TXFLOW
: 0;
1078 switch (cfg
->speed
) {
1079 case AR8327_PORT_SPEED_10
:
1080 t
|= AR8216_PORT_SPEED_10M
;
1082 case AR8327_PORT_SPEED_100
:
1083 t
|= AR8216_PORT_SPEED_100M
;
1085 case AR8327_PORT_SPEED_1000
:
1086 t
|= AR8216_PORT_SPEED_1000M
;
1094 ar8327_hw_config_pdata(struct ar8xxx_priv
*priv
,
1095 struct ar8327_platform_data
*pdata
)
1097 struct ar8327_led_cfg
*led_cfg
;
1098 struct ar8327_data
*data
;
1105 priv
->get_port_link
= pdata
->get_port_link
;
1107 data
= &priv
->chip_data
.ar8327
;
1109 data
->port0_status
= ar8327_get_port_init_status(&pdata
->port0_cfg
);
1110 data
->port6_status
= ar8327_get_port_init_status(&pdata
->port6_cfg
);
1112 t
= ar8327_get_pad_cfg(pdata
->pad0_cfg
);
1113 if (chip_is_ar8337(priv
))
1114 t
|= AR8337_PAD_MAC06_EXCHANGE_EN
;
1116 priv
->write(priv
, AR8327_REG_PAD0_MODE
, t
);
1117 t
= ar8327_get_pad_cfg(pdata
->pad5_cfg
);
1118 priv
->write(priv
, AR8327_REG_PAD5_MODE
, t
);
1119 t
= ar8327_get_pad_cfg(pdata
->pad6_cfg
);
1120 priv
->write(priv
, AR8327_REG_PAD6_MODE
, t
);
1122 pos
= priv
->read(priv
, AR8327_REG_POWER_ON_STRIP
);
1125 led_cfg
= pdata
->led_cfg
;
1127 if (led_cfg
->open_drain
)
1128 new_pos
|= AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1130 new_pos
&= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN
;
1132 priv
->write(priv
, AR8327_REG_LED_CTRL0
, led_cfg
->led_ctrl0
);
1133 priv
->write(priv
, AR8327_REG_LED_CTRL1
, led_cfg
->led_ctrl1
);
1134 priv
->write(priv
, AR8327_REG_LED_CTRL2
, led_cfg
->led_ctrl2
);
1135 priv
->write(priv
, AR8327_REG_LED_CTRL3
, led_cfg
->led_ctrl3
);
1138 new_pos
|= AR8327_POWER_ON_STRIP_POWER_ON_SEL
;
1141 if (pdata
->sgmii_cfg
) {
1142 t
= pdata
->sgmii_cfg
->sgmii_ctrl
;
1143 if (priv
->chip_rev
== 1)
1144 t
|= AR8327_SGMII_CTRL_EN_PLL
|
1145 AR8327_SGMII_CTRL_EN_RX
|
1146 AR8327_SGMII_CTRL_EN_TX
;
1148 t
&= ~(AR8327_SGMII_CTRL_EN_PLL
|
1149 AR8327_SGMII_CTRL_EN_RX
|
1150 AR8327_SGMII_CTRL_EN_TX
);
1152 priv
->write(priv
, AR8327_REG_SGMII_CTRL
, t
);
1154 if (pdata
->sgmii_cfg
->serdes_aen
)
1155 new_pos
&= ~AR8327_POWER_ON_STRIP_SERDES_AEN
;
1157 new_pos
|= AR8327_POWER_ON_STRIP_SERDES_AEN
;
1160 priv
->write(priv
, AR8327_REG_POWER_ON_STRIP
, new_pos
);
1167 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1169 const __be32
*paddr
;
1173 paddr
= of_get_property(np
, "qca,ar8327-initvals", &len
);
1174 if (!paddr
|| len
< (2 * sizeof(*paddr
)))
1177 len
/= sizeof(*paddr
);
1179 for (i
= 0; i
< len
- 1; i
+= 2) {
1183 reg
= be32_to_cpup(paddr
+ i
);
1184 val
= be32_to_cpup(paddr
+ i
+ 1);
1187 case AR8327_REG_PORT_STATUS(0):
1188 priv
->chip_data
.ar8327
.port0_status
= val
;
1190 case AR8327_REG_PORT_STATUS(6):
1191 priv
->chip_data
.ar8327
.port6_status
= val
;
1194 priv
->write(priv
, reg
, val
);
1203 ar8327_hw_config_of(struct ar8xxx_priv
*priv
, struct device_node
*np
)
1210 ar8327_hw_init(struct ar8xxx_priv
*priv
)
1212 struct mii_bus
*bus
;
1216 if (priv
->phy
->dev
.of_node
)
1217 ret
= ar8327_hw_config_of(priv
, priv
->phy
->dev
.of_node
);
1219 ret
= ar8327_hw_config_pdata(priv
,
1220 priv
->phy
->dev
.platform_data
);
1225 bus
= priv
->mii_bus
;
1226 for (i
= 0; i
< AR8327_NUM_PHYS
; i
++) {
1227 ar8327_phy_fixup(priv
, i
);
1229 /* start aneg on the PHY */
1230 mdiobus_write(bus
, i
, MII_ADVERTISE
, ADVERTISE_ALL
|
1231 ADVERTISE_PAUSE_CAP
|
1232 ADVERTISE_PAUSE_ASYM
);
1233 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
1234 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
1243 ar8327_init_globals(struct ar8xxx_priv
*priv
)
1247 /* enable CPU port and disable mirror port */
1248 t
= AR8327_FWD_CTRL0_CPU_PORT_EN
|
1249 AR8327_FWD_CTRL0_MIRROR_PORT
;
1250 priv
->write(priv
, AR8327_REG_FWD_CTRL0
, t
);
1252 /* forward multicast and broadcast frames to CPU */
1253 t
= (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_UC_FLOOD_S
) |
1254 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_MC_FLOOD_S
) |
1255 (AR8327_PORTS_ALL
<< AR8327_FWD_CTRL1_BC_FLOOD_S
);
1256 priv
->write(priv
, AR8327_REG_FWD_CTRL1
, t
);
1258 /* enable jumbo frames */
1259 ar8xxx_rmw(priv
, AR8327_REG_MAX_FRAME_SIZE
,
1260 AR8327_MAX_FRAME_SIZE_MTU
, 9018 + 8 + 2);
1262 /* Enable MIB counters */
1263 ar8xxx_reg_set(priv
, AR8327_REG_MODULE_EN
,
1264 AR8327_MODULE_EN_MIB
);
1268 ar8327_init_port(struct ar8xxx_priv
*priv
, int port
)
1272 if (port
== AR8216_PORT_CPU
)
1273 t
= priv
->chip_data
.ar8327
.port0_status
;
1275 t
= priv
->chip_data
.ar8327
.port6_status
;
1277 t
= AR8216_PORT_STATUS_LINK_AUTO
;
1279 priv
->write(priv
, AR8327_REG_PORT_STATUS(port
), t
);
1280 priv
->write(priv
, AR8327_REG_PORT_HEADER(port
), 0);
1282 t
= 1 << AR8327_PORT_VLAN0_DEF_SVID_S
;
1283 t
|= 1 << AR8327_PORT_VLAN0_DEF_CVID_S
;
1284 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1286 t
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1287 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1289 t
= AR8327_PORT_LOOKUP_LEARN
;
1290 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1291 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1295 ar8327_read_port_status(struct ar8xxx_priv
*priv
, int port
)
1297 return priv
->read(priv
, AR8327_REG_PORT_STATUS(port
));
1301 ar8327_atu_flush(struct ar8xxx_priv
*priv
)
1305 ret
= ar8216_wait_bit(priv
, AR8327_REG_ATU_FUNC
,
1306 AR8327_ATU_FUNC_BUSY
, 0);
1308 priv
->write(priv
, AR8327_REG_ATU_FUNC
,
1309 AR8327_ATU_FUNC_OP_FLUSH
);
1315 ar8327_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
1317 if (ar8216_wait_bit(priv
, AR8327_REG_VTU_FUNC1
,
1318 AR8327_VTU_FUNC1_BUSY
, 0))
1321 if ((op
& AR8327_VTU_FUNC1_OP
) == AR8327_VTU_FUNC1_OP_LOAD
)
1322 priv
->write(priv
, AR8327_REG_VTU_FUNC0
, val
);
1324 op
|= AR8327_VTU_FUNC1_BUSY
;
1325 priv
->write(priv
, AR8327_REG_VTU_FUNC1
, op
);
1329 ar8327_vtu_flush(struct ar8xxx_priv
*priv
)
1331 ar8327_vtu_op(priv
, AR8327_VTU_FUNC1_OP_FLUSH
, 0);
1335 ar8327_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
1341 op
= AR8327_VTU_FUNC1_OP_LOAD
| (vid
<< AR8327_VTU_FUNC1_VID_S
);
1342 val
= AR8327_VTU_FUNC0_VALID
| AR8327_VTU_FUNC0_IVL
;
1343 for (i
= 0; i
< AR8327_NUM_PORTS
; i
++) {
1346 if ((port_mask
& BIT(i
)) == 0)
1347 mode
= AR8327_VTU_FUNC0_EG_MODE_NOT
;
1348 else if (priv
->vlan
== 0)
1349 mode
= AR8327_VTU_FUNC0_EG_MODE_KEEP
;
1350 else if (priv
->vlan_tagged
& BIT(i
))
1351 mode
= AR8327_VTU_FUNC0_EG_MODE_TAG
;
1353 mode
= AR8327_VTU_FUNC0_EG_MODE_UNTAG
;
1355 val
|= mode
<< AR8327_VTU_FUNC0_EG_MODE_S(i
);
1357 ar8327_vtu_op(priv
, op
, val
);
1361 ar8327_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 egress
, u32 ingress
,
1362 u32 members
, u32 pvid
)
1367 t
= pvid
<< AR8327_PORT_VLAN0_DEF_SVID_S
;
1368 t
|= pvid
<< AR8327_PORT_VLAN0_DEF_CVID_S
;
1369 priv
->write(priv
, AR8327_REG_PORT_VLAN0(port
), t
);
1371 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNMOD
;
1373 case AR8216_OUT_KEEP
:
1374 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH
;
1376 case AR8216_OUT_STRIP_VLAN
:
1377 mode
= AR8327_PORT_VLAN1_OUT_MODE_UNTAG
;
1379 case AR8216_OUT_ADD_VLAN
:
1380 mode
= AR8327_PORT_VLAN1_OUT_MODE_TAG
;
1384 t
= AR8327_PORT_VLAN1_PORT_VLAN_PROP
;
1385 t
|= mode
<< AR8327_PORT_VLAN1_OUT_MODE_S
;
1386 priv
->write(priv
, AR8327_REG_PORT_VLAN1(port
), t
);
1389 t
|= AR8327_PORT_LOOKUP_LEARN
;
1390 t
|= ingress
<< AR8327_PORT_LOOKUP_IN_MODE_S
;
1391 t
|= AR8216_PORT_STATE_FORWARD
<< AR8327_PORT_LOOKUP_STATE_S
;
1392 priv
->write(priv
, AR8327_REG_PORT_LOOKUP(port
), t
);
1395 static const struct ar8xxx_chip ar8327_chip
= {
1396 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
1397 .hw_init
= ar8327_hw_init
,
1398 .init_globals
= ar8327_init_globals
,
1399 .init_port
= ar8327_init_port
,
1400 .setup_port
= ar8327_setup_port
,
1401 .read_port_status
= ar8327_read_port_status
,
1402 .atu_flush
= ar8327_atu_flush
,
1403 .vtu_flush
= ar8327_vtu_flush
,
1404 .vtu_load_vlan
= ar8327_vtu_load_vlan
,
1406 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
1407 .mib_decs
= ar8236_mibs
,
1411 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1412 struct switch_val
*val
)
1414 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1415 priv
->vlan
= !!val
->value
.i
;
1420 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1421 struct switch_val
*val
)
1423 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1424 val
->value
.i
= priv
->vlan
;
1430 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1432 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1434 /* make sure no invalid PVIDs get set */
1436 if (vlan
>= dev
->vlans
)
1439 priv
->pvid
[port
] = vlan
;
1444 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1446 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1447 *vlan
= priv
->pvid
[port
];
1452 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1453 struct switch_val
*val
)
1455 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1456 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1461 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1462 struct switch_val
*val
)
1464 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1465 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1470 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1471 struct switch_port_link
*link
)
1473 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1475 ar8216_read_port_link(priv
, port
, link
);
1480 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1482 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1483 u8 ports
= priv
->vlan_table
[val
->port_vlan
];
1487 for (i
= 0; i
< dev
->ports
; i
++) {
1488 struct switch_port
*p
;
1490 if (!(ports
& (1 << i
)))
1493 p
= &val
->value
.ports
[val
->len
++];
1495 if (priv
->vlan_tagged
& (1 << i
))
1496 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1504 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1506 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1507 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1511 for (i
= 0; i
< val
->len
; i
++) {
1512 struct switch_port
*p
= &val
->value
.ports
[i
];
1514 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1515 priv
->vlan_tagged
|= (1 << p
->id
);
1517 priv
->vlan_tagged
&= ~(1 << p
->id
);
1518 priv
->pvid
[p
->id
] = val
->port_vlan
;
1520 /* make sure that an untagged port does not
1521 * appear in other vlans */
1522 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1523 if (j
== val
->port_vlan
)
1525 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1535 ar8327_set_mirror_regs(struct ar8xxx_priv
*priv
)
1539 /* reset all mirror registers */
1540 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1541 AR8327_FWD_CTRL0_MIRROR_PORT
,
1542 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1543 for (port
= 0; port
< AR8327_NUM_PORTS
; port
++) {
1544 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(port
),
1545 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
1548 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(port
),
1549 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
1553 /* now enable mirroring if necessary */
1554 if (priv
->source_port
>= AR8327_NUM_PORTS
||
1555 priv
->monitor_port
>= AR8327_NUM_PORTS
||
1556 priv
->source_port
== priv
->monitor_port
) {
1560 ar8xxx_rmw(priv
, AR8327_REG_FWD_CTRL0
,
1561 AR8327_FWD_CTRL0_MIRROR_PORT
,
1562 (priv
->monitor_port
<< AR8327_FWD_CTRL0_MIRROR_PORT_S
));
1564 if (priv
->mirror_rx
)
1565 ar8xxx_rmw(priv
, AR8327_REG_PORT_LOOKUP(priv
->source_port
),
1566 AR8327_PORT_LOOKUP_ING_MIRROR_EN
,
1567 AR8327_PORT_LOOKUP_ING_MIRROR_EN
);
1569 if (priv
->mirror_tx
)
1570 ar8xxx_rmw(priv
, AR8327_REG_PORT_HOL_CTRL1(priv
->source_port
),
1571 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
,
1572 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN
);
1576 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1580 /* reset all mirror registers */
1581 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1582 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1583 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1584 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1585 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1586 AR8216_PORT_CTRL_MIRROR_RX
,
1589 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1590 AR8216_PORT_CTRL_MIRROR_TX
,
1594 /* now enable mirroring if necessary */
1595 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1596 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1597 priv
->source_port
== priv
->monitor_port
) {
1601 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1602 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1603 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1605 if (priv
->mirror_rx
)
1606 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1607 AR8216_PORT_CTRL_MIRROR_RX
,
1608 AR8216_PORT_CTRL_MIRROR_RX
);
1610 if (priv
->mirror_tx
)
1611 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1612 AR8216_PORT_CTRL_MIRROR_TX
,
1613 AR8216_PORT_CTRL_MIRROR_TX
);
1617 ar8xxx_set_mirror_regs(struct ar8xxx_priv
*priv
)
1619 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
1620 ar8327_set_mirror_regs(priv
);
1622 ar8216_set_mirror_regs(priv
);
1627 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1629 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1630 u8 portmask
[AR8X16_MAX_PORTS
];
1633 mutex_lock(&priv
->reg_mutex
);
1634 /* flush all vlan translation unit entries */
1635 priv
->chip
->vtu_flush(priv
);
1637 memset(portmask
, 0, sizeof(portmask
));
1639 /* calculate the port destination masks and load vlans
1640 * into the vlan translation unit */
1641 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1642 u8 vp
= priv
->vlan_table
[j
];
1647 for (i
= 0; i
< dev
->ports
; i
++) {
1650 portmask
[i
] |= vp
& ~mask
;
1653 priv
->chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1654 priv
->vlan_table
[j
]);
1658 * isolate all ports, but connect them to the cpu port */
1659 for (i
= 0; i
< dev
->ports
; i
++) {
1660 if (i
== AR8216_PORT_CPU
)
1663 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1664 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1668 /* update the port destination mask registers and tag settings */
1669 for (i
= 0; i
< dev
->ports
; i
++) {
1670 int egress
, ingress
;
1674 pvid
= priv
->vlan_id
[priv
->pvid
[i
]];
1675 if (priv
->vlan_tagged
& (1 << i
))
1676 egress
= AR8216_OUT_ADD_VLAN
;
1678 egress
= AR8216_OUT_STRIP_VLAN
;
1679 ingress
= AR8216_IN_SECURE
;
1682 egress
= AR8216_OUT_KEEP
;
1683 ingress
= AR8216_IN_PORT_ONLY
;
1686 priv
->chip
->setup_port(priv
, i
, egress
, ingress
, portmask
[i
],
1690 ar8xxx_set_mirror_regs(priv
);
1692 mutex_unlock(&priv
->reg_mutex
);
1697 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1699 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1702 mutex_lock(&priv
->reg_mutex
);
1703 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1704 offsetof(struct ar8xxx_priv
, vlan
));
1706 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1707 priv
->vlan_id
[i
] = i
;
1709 /* Configure all ports */
1710 for (i
= 0; i
< dev
->ports
; i
++)
1711 priv
->chip
->init_port(priv
, i
);
1713 priv
->mirror_rx
= false;
1714 priv
->mirror_tx
= false;
1715 priv
->source_port
= 0;
1716 priv
->monitor_port
= 0;
1718 priv
->chip
->init_globals(priv
);
1720 mutex_unlock(&priv
->reg_mutex
);
1722 return ar8xxx_sw_hw_apply(dev
);
1726 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1727 const struct switch_attr
*attr
,
1728 struct switch_val
*val
)
1730 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1734 if (!ar8xxx_has_mib_counters(priv
))
1737 mutex_lock(&priv
->mib_lock
);
1739 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1740 sizeof(*priv
->mib_stats
);
1741 memset(priv
->mib_stats
, '\0', len
);
1742 ret
= ar8xxx_mib_flush(priv
);
1749 mutex_unlock(&priv
->mib_lock
);
1754 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1755 const struct switch_attr
*attr
,
1756 struct switch_val
*val
)
1758 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1760 mutex_lock(&priv
->reg_mutex
);
1761 priv
->mirror_rx
= !!val
->value
.i
;
1762 ar8xxx_set_mirror_regs(priv
);
1763 mutex_unlock(&priv
->reg_mutex
);
1769 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1770 const struct switch_attr
*attr
,
1771 struct switch_val
*val
)
1773 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1774 val
->value
.i
= priv
->mirror_rx
;
1779 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1780 const struct switch_attr
*attr
,
1781 struct switch_val
*val
)
1783 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1785 mutex_lock(&priv
->reg_mutex
);
1786 priv
->mirror_tx
= !!val
->value
.i
;
1787 ar8xxx_set_mirror_regs(priv
);
1788 mutex_unlock(&priv
->reg_mutex
);
1794 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1795 const struct switch_attr
*attr
,
1796 struct switch_val
*val
)
1798 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1799 val
->value
.i
= priv
->mirror_tx
;
1804 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1805 const struct switch_attr
*attr
,
1806 struct switch_val
*val
)
1808 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1810 mutex_lock(&priv
->reg_mutex
);
1811 priv
->monitor_port
= val
->value
.i
;
1812 ar8xxx_set_mirror_regs(priv
);
1813 mutex_unlock(&priv
->reg_mutex
);
1819 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1820 const struct switch_attr
*attr
,
1821 struct switch_val
*val
)
1823 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1824 val
->value
.i
= priv
->monitor_port
;
1829 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1830 const struct switch_attr
*attr
,
1831 struct switch_val
*val
)
1833 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1835 mutex_lock(&priv
->reg_mutex
);
1836 priv
->source_port
= val
->value
.i
;
1837 ar8xxx_set_mirror_regs(priv
);
1838 mutex_unlock(&priv
->reg_mutex
);
1844 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1845 const struct switch_attr
*attr
,
1846 struct switch_val
*val
)
1848 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1849 val
->value
.i
= priv
->source_port
;
1854 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1855 const struct switch_attr
*attr
,
1856 struct switch_val
*val
)
1858 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1862 if (!ar8xxx_has_mib_counters(priv
))
1865 port
= val
->port_vlan
;
1866 if (port
>= dev
->ports
)
1869 mutex_lock(&priv
->mib_lock
);
1870 ret
= ar8xxx_mib_capture(priv
);
1874 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1879 mutex_unlock(&priv
->mib_lock
);
1884 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1885 const struct switch_attr
*attr
,
1886 struct switch_val
*val
)
1888 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1889 const struct ar8xxx_chip
*chip
= priv
->chip
;
1893 char *buf
= priv
->buf
;
1896 if (!ar8xxx_has_mib_counters(priv
))
1899 port
= val
->port_vlan
;
1900 if (port
>= dev
->ports
)
1903 mutex_lock(&priv
->mib_lock
);
1904 ret
= ar8xxx_mib_capture(priv
);
1908 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1910 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1911 "Port %d MIB counters\n",
1914 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1915 for (i
= 0; i
< chip
->num_mibs
; i
++)
1916 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1918 chip
->mib_decs
[i
].name
,
1927 mutex_unlock(&priv
->mib_lock
);
1931 static struct switch_attr ar8xxx_sw_attr_globals
[] = {
1933 .type
= SWITCH_TYPE_INT
,
1934 .name
= "enable_vlan",
1935 .description
= "Enable VLAN mode",
1936 .set
= ar8xxx_sw_set_vlan
,
1937 .get
= ar8xxx_sw_get_vlan
,
1941 .type
= SWITCH_TYPE_NOVAL
,
1942 .name
= "reset_mibs",
1943 .description
= "Reset all MIB counters",
1944 .set
= ar8xxx_sw_set_reset_mibs
,
1947 .type
= SWITCH_TYPE_INT
,
1948 .name
= "enable_mirror_rx",
1949 .description
= "Enable mirroring of RX packets",
1950 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1951 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1955 .type
= SWITCH_TYPE_INT
,
1956 .name
= "enable_mirror_tx",
1957 .description
= "Enable mirroring of TX packets",
1958 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1959 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1963 .type
= SWITCH_TYPE_INT
,
1964 .name
= "mirror_monitor_port",
1965 .description
= "Mirror monitor port",
1966 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1967 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1968 .max
= AR8216_NUM_PORTS
- 1
1971 .type
= SWITCH_TYPE_INT
,
1972 .name
= "mirror_source_port",
1973 .description
= "Mirror source port",
1974 .set
= ar8xxx_sw_set_mirror_source_port
,
1975 .get
= ar8xxx_sw_get_mirror_source_port
,
1976 .max
= AR8216_NUM_PORTS
- 1
1980 static struct switch_attr ar8327_sw_attr_globals
[] = {
1982 .type
= SWITCH_TYPE_INT
,
1983 .name
= "enable_vlan",
1984 .description
= "Enable VLAN mode",
1985 .set
= ar8xxx_sw_set_vlan
,
1986 .get
= ar8xxx_sw_get_vlan
,
1990 .type
= SWITCH_TYPE_NOVAL
,
1991 .name
= "reset_mibs",
1992 .description
= "Reset all MIB counters",
1993 .set
= ar8xxx_sw_set_reset_mibs
,
1996 .type
= SWITCH_TYPE_INT
,
1997 .name
= "enable_mirror_rx",
1998 .description
= "Enable mirroring of RX packets",
1999 .set
= ar8xxx_sw_set_mirror_rx_enable
,
2000 .get
= ar8xxx_sw_get_mirror_rx_enable
,
2004 .type
= SWITCH_TYPE_INT
,
2005 .name
= "enable_mirror_tx",
2006 .description
= "Enable mirroring of TX packets",
2007 .set
= ar8xxx_sw_set_mirror_tx_enable
,
2008 .get
= ar8xxx_sw_get_mirror_tx_enable
,
2012 .type
= SWITCH_TYPE_INT
,
2013 .name
= "mirror_monitor_port",
2014 .description
= "Mirror monitor port",
2015 .set
= ar8xxx_sw_set_mirror_monitor_port
,
2016 .get
= ar8xxx_sw_get_mirror_monitor_port
,
2017 .max
= AR8327_NUM_PORTS
- 1
2020 .type
= SWITCH_TYPE_INT
,
2021 .name
= "mirror_source_port",
2022 .description
= "Mirror source port",
2023 .set
= ar8xxx_sw_set_mirror_source_port
,
2024 .get
= ar8xxx_sw_get_mirror_source_port
,
2025 .max
= AR8327_NUM_PORTS
- 1
2029 static struct switch_attr ar8xxx_sw_attr_port
[] = {
2031 .type
= SWITCH_TYPE_NOVAL
,
2032 .name
= "reset_mib",
2033 .description
= "Reset single port MIB counters",
2034 .set
= ar8xxx_sw_set_port_reset_mib
,
2037 .type
= SWITCH_TYPE_STRING
,
2039 .description
= "Get port's MIB counters",
2041 .get
= ar8xxx_sw_get_port_mib
,
2045 static struct switch_attr ar8xxx_sw_attr_vlan
[] = {
2047 .type
= SWITCH_TYPE_INT
,
2049 .description
= "VLAN ID (0-4094)",
2050 .set
= ar8xxx_sw_set_vid
,
2051 .get
= ar8xxx_sw_get_vid
,
2056 static const struct switch_dev_ops ar8xxx_sw_ops
= {
2058 .attr
= ar8xxx_sw_attr_globals
,
2059 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
2062 .attr
= ar8xxx_sw_attr_port
,
2063 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2066 .attr
= ar8xxx_sw_attr_vlan
,
2067 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2069 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2070 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2071 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2072 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2073 .apply_config
= ar8xxx_sw_hw_apply
,
2074 .reset_switch
= ar8xxx_sw_reset_switch
,
2075 .get_port_link
= ar8xxx_sw_get_port_link
,
2078 static const struct switch_dev_ops ar8327_sw_ops
= {
2080 .attr
= ar8327_sw_attr_globals
,
2081 .n_attr
= ARRAY_SIZE(ar8327_sw_attr_globals
),
2084 .attr
= ar8xxx_sw_attr_port
,
2085 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
2088 .attr
= ar8xxx_sw_attr_vlan
,
2089 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
2091 .get_port_pvid
= ar8xxx_sw_get_pvid
,
2092 .set_port_pvid
= ar8xxx_sw_set_pvid
,
2093 .get_vlan_ports
= ar8xxx_sw_get_ports
,
2094 .set_vlan_ports
= ar8xxx_sw_set_ports
,
2095 .apply_config
= ar8xxx_sw_hw_apply
,
2096 .reset_switch
= ar8xxx_sw_reset_switch
,
2097 .get_port_link
= ar8xxx_sw_get_port_link
,
2101 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2107 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2111 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2112 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2115 val
= priv
->read(priv
, AR8216_REG_CTRL
);
2119 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2124 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2125 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2127 switch (priv
->chip_ver
) {
2128 case AR8XXX_VER_AR8216
:
2129 priv
->chip
= &ar8216_chip
;
2131 case AR8XXX_VER_AR8236
:
2132 priv
->chip
= &ar8236_chip
;
2134 case AR8XXX_VER_AR8316
:
2135 priv
->chip
= &ar8316_chip
;
2137 case AR8XXX_VER_AR8327
:
2138 priv
->mii_lo_first
= true;
2139 priv
->chip
= &ar8327_chip
;
2141 case AR8XXX_VER_AR8337
:
2142 priv
->mii_lo_first
= true;
2143 priv
->chip
= &ar8327_chip
;
2146 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2147 priv
->chip_ver
, priv
->chip_rev
);
2156 ar8xxx_mib_work_func(struct work_struct
*work
)
2158 struct ar8xxx_priv
*priv
;
2161 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2163 mutex_lock(&priv
->mib_lock
);
2165 err
= ar8xxx_mib_capture(priv
);
2169 ar8xxx_mib_fetch_port_stat(priv
, priv
->mib_next_port
, false);
2172 priv
->mib_next_port
++;
2173 if (priv
->mib_next_port
>= priv
->dev
.ports
)
2174 priv
->mib_next_port
= 0;
2176 mutex_unlock(&priv
->mib_lock
);
2177 schedule_delayed_work(&priv
->mib_work
,
2178 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2182 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2186 if (!ar8xxx_has_mib_counters(priv
))
2189 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2191 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2192 sizeof(*priv
->mib_stats
);
2193 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2195 if (!priv
->mib_stats
)
2202 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2204 if (!ar8xxx_has_mib_counters(priv
))
2207 schedule_delayed_work(&priv
->mib_work
,
2208 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY
));
2212 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2214 if (!ar8xxx_has_mib_counters(priv
))
2217 cancel_delayed_work(&priv
->mib_work
);
2220 static struct ar8xxx_priv
*
2223 struct ar8xxx_priv
*priv
;
2225 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2229 mutex_init(&priv
->reg_mutex
);
2230 mutex_init(&priv
->mib_lock
);
2231 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2237 ar8xxx_free(struct ar8xxx_priv
*priv
)
2239 if (priv
->chip
&& priv
->chip
->cleanup
)
2240 priv
->chip
->cleanup(priv
);
2242 kfree(priv
->mib_stats
);
2246 static struct ar8xxx_priv
*
2247 ar8xxx_create_mii(struct mii_bus
*bus
)
2249 struct ar8xxx_priv
*priv
;
2251 priv
= ar8xxx_create();
2253 priv
->mii_bus
= bus
;
2254 priv
->read
= ar8xxx_mii_read
;
2255 priv
->write
= ar8xxx_mii_write
;
2256 priv
->rmw
= ar8xxx_mii_rmw
;
2263 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2265 struct switch_dev
*swdev
;
2268 ret
= ar8xxx_id_chip(priv
);
2273 swdev
->cpu_port
= AR8216_PORT_CPU
;
2274 swdev
->ops
= &ar8xxx_sw_ops
;
2276 if (chip_is_ar8316(priv
)) {
2277 swdev
->name
= "Atheros AR8316";
2278 swdev
->vlans
= AR8X16_MAX_VLANS
;
2279 swdev
->ports
= AR8216_NUM_PORTS
;
2280 } else if (chip_is_ar8236(priv
)) {
2281 swdev
->name
= "Atheros AR8236";
2282 swdev
->vlans
= AR8216_NUM_VLANS
;
2283 swdev
->ports
= AR8216_NUM_PORTS
;
2284 } else if (chip_is_ar8327(priv
)) {
2285 swdev
->name
= "Atheros AR8327";
2286 swdev
->vlans
= AR8X16_MAX_VLANS
;
2287 swdev
->ports
= AR8327_NUM_PORTS
;
2288 swdev
->ops
= &ar8327_sw_ops
;
2289 } else if (chip_is_ar8337(priv
)) {
2290 swdev
->name
= "Atheros AR8337";
2291 swdev
->vlans
= AR8X16_MAX_VLANS
;
2292 swdev
->ports
= AR8327_NUM_PORTS
;
2293 swdev
->ops
= &ar8327_sw_ops
;
2295 swdev
->name
= "Atheros AR8216";
2296 swdev
->vlans
= AR8216_NUM_VLANS
;
2297 swdev
->ports
= AR8216_NUM_PORTS
;
2300 ret
= ar8xxx_mib_init(priv
);
2308 ar8xxx_start(struct ar8xxx_priv
*priv
)
2314 ret
= priv
->chip
->hw_init(priv
);
2318 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2324 ar8xxx_mib_start(priv
);
2330 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2332 struct ar8xxx_priv
*priv
= phydev
->priv
;
2333 struct net_device
*dev
= phydev
->attached_dev
;
2339 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
))
2344 if (phydev
->addr
!= 0) {
2345 if (chip_is_ar8316(priv
)) {
2346 /* switch device has been initialized, reinit */
2347 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2348 priv
->initialized
= false;
2349 priv
->port4_phy
= true;
2350 ar8316_hw_init(priv
);
2357 ret
= ar8xxx_start(priv
);
2361 /* VID fixup only needed on ar8216 */
2362 if (chip_is_ar8216(priv
)) {
2363 dev
->phy_ptr
= priv
;
2364 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2365 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2366 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2373 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2375 struct ar8xxx_priv
*priv
= phydev
->priv
;
2376 struct switch_port_link link
;
2379 if (phydev
->addr
!= 0)
2380 return genphy_read_status(phydev
);
2382 ar8216_read_port_link(priv
, phydev
->addr
, &link
);
2383 phydev
->link
= !!link
.link
;
2387 switch (link
.speed
) {
2388 case SWITCH_PORT_SPEED_10
:
2389 phydev
->speed
= SPEED_10
;
2391 case SWITCH_PORT_SPEED_100
:
2392 phydev
->speed
= SPEED_100
;
2394 case SWITCH_PORT_SPEED_1000
:
2395 phydev
->speed
= SPEED_1000
;
2400 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2402 /* flush the address translation unit */
2403 mutex_lock(&priv
->reg_mutex
);
2404 ret
= priv
->chip
->atu_flush(priv
);
2405 mutex_unlock(&priv
->reg_mutex
);
2407 phydev
->state
= PHY_RUNNING
;
2408 netif_carrier_on(phydev
->attached_dev
);
2409 phydev
->adjust_link(phydev
->attached_dev
);
2415 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2417 if (phydev
->addr
== 0)
2420 return genphy_config_aneg(phydev
);
2423 static const u32 ar8xxx_phy_ids
[] = {
2425 0x004dd034, /* AR8327 */
2426 0x004dd036, /* AR8337 */
2432 ar8xxx_phy_match(u32 phy_id
)
2436 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2437 if (phy_id
== ar8xxx_phy_ids
[i
])
2444 ar8xxx_is_possible(struct mii_bus
*bus
)
2448 for (i
= 0; i
< 4; i
++) {
2451 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2452 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2453 if (!ar8xxx_phy_match(phy_id
)) {
2454 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2455 dev_name(&bus
->dev
), i
, phy_id
);
2464 ar8xxx_phy_probe(struct phy_device
*phydev
)
2466 struct ar8xxx_priv
*priv
;
2467 struct switch_dev
*swdev
;
2470 /* skip PHYs at unused adresses */
2471 if (phydev
->addr
!= 0 && phydev
->addr
!= 4)
2474 if (!ar8xxx_is_possible(phydev
->bus
))
2477 mutex_lock(&ar8xxx_dev_list_lock
);
2478 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2479 if (priv
->mii_bus
== phydev
->bus
)
2482 priv
= ar8xxx_create_mii(phydev
->bus
);
2488 ret
= ar8xxx_probe_switch(priv
);
2493 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2494 ret
= register_switch(swdev
, NULL
);
2498 pr_info("%s: %s rev. %u switch registered on %s\n",
2499 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2500 dev_name(&priv
->mii_bus
->dev
));
2505 if (phydev
->addr
== 0) {
2506 if (ar8xxx_has_gige(priv
)) {
2507 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2508 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2510 phydev
->supported
= SUPPORTED_100baseT_Full
;
2511 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2514 if (chip_is_ar8327(priv
) || chip_is_ar8337(priv
)) {
2517 ret
= ar8xxx_start(priv
);
2519 goto err_unregister_switch
;
2522 if (ar8xxx_has_gige(priv
)) {
2523 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2524 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2528 phydev
->priv
= priv
;
2530 list_add(&priv
->list
, &ar8xxx_dev_list
);
2532 mutex_unlock(&ar8xxx_dev_list_lock
);
2536 err_unregister_switch
:
2537 if (--priv
->use_count
)
2540 unregister_switch(&priv
->dev
);
2545 mutex_unlock(&ar8xxx_dev_list_lock
);
2550 ar8xxx_phy_detach(struct phy_device
*phydev
)
2552 struct net_device
*dev
= phydev
->attached_dev
;
2557 dev
->phy_ptr
= NULL
;
2558 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2559 dev
->eth_mangle_rx
= NULL
;
2560 dev
->eth_mangle_tx
= NULL
;
2564 ar8xxx_phy_remove(struct phy_device
*phydev
)
2566 struct ar8xxx_priv
*priv
= phydev
->priv
;
2571 phydev
->priv
= NULL
;
2572 if (--priv
->use_count
> 0)
2575 mutex_lock(&ar8xxx_dev_list_lock
);
2576 list_del(&priv
->list
);
2577 mutex_unlock(&ar8xxx_dev_list_lock
);
2579 unregister_switch(&priv
->dev
);
2580 ar8xxx_mib_stop(priv
);
2584 static struct phy_driver ar8xxx_phy_driver
= {
2585 .phy_id
= 0x004d0000,
2586 .name
= "Atheros AR8216/AR8236/AR8316",
2587 .phy_id_mask
= 0xffff0000,
2588 .features
= PHY_BASIC_FEATURES
,
2589 .probe
= ar8xxx_phy_probe
,
2590 .remove
= ar8xxx_phy_remove
,
2591 .detach
= ar8xxx_phy_detach
,
2592 .config_init
= ar8xxx_phy_config_init
,
2593 .config_aneg
= ar8xxx_phy_config_aneg
,
2594 .read_status
= ar8xxx_phy_read_status
,
2595 .driver
= { .owner
= THIS_MODULE
},
2601 return phy_driver_register(&ar8xxx_phy_driver
);
2607 phy_driver_unregister(&ar8xxx_phy_driver
);
2610 module_init(ar8xxx_init
);
2611 module_exit(ar8xxx_exit
);
2612 MODULE_LICENSE("GPL");